drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 205 /* Single VLAN tag in the inner L2 header */
 206 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 207 /* Source IPv4 address */
 208 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 209 /* Destination IPv4 address */
 210 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 211 /* IPv4 Type of Service (TOS) */
 212 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 213 /* IPv4 Protocol */
 214 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 215 /* IPv4 Time to Live */
 216 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 217 /* Source IPv6 address */
 218 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 219 /* Destination IPv6 address */
 220 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 221 /* IPv6 Traffic Class (TC) */
 222 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 223 /* IPv6 Next Header */
 224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 225 /* IPv6 Hop Limit */
 226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263 /* all 8 words flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 265 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 266
 267 #define I40E_TRANSLATE_INSET 0
 268 #define I40E_TRANSLATE_REG   1
 269
 270 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 271 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 272 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 275 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 276
 277 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 280         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 281
 282 /* PCI offset for querying capability */
 283 #define PCI_DEV_CAP_REG            0xA4
 284 /* PCI offset for enabling/disabling Extended Tag */
 285 #define PCI_DEV_CTRL_REG           0xA8
 286 /* Bit mask of Extended Tag capability */
 287 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 288 /* Bit shift of Extended Tag enable/disable */
 289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 290 /* Bit mask of Extended Tag enable/disable */
 291 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 292
 293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 295 static int i40e_dev_configure(struct rte_eth_dev *dev);
 296 static int i40e_dev_start(struct rte_eth_dev *dev);
 297 static void i40e_dev_stop(struct rte_eth_dev *dev);
 298 static void i40e_dev_close(struct rte_eth_dev *dev);
 299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 306                                struct rte_eth_stats *stats);
 307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 308                                struct rte_eth_xstats *xstats, unsigned n);
 309 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 310 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 311                                             uint16_t queue_id,
 312                                             uint8_t stat_idx,
 313                                             uint8_t is_rx);
 314 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 315                               struct rte_eth_dev_info *dev_info);
 316 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 317                                 uint16_t vlan_id,
 318                                 int on);
 319 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 320                               enum rte_vlan_type vlan_type,
 321                               uint16_t tpid);
 322 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 323 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 324                                       uint16_t queue,
 325                                       int on);
 326 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 327 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 328 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 329 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 330                               struct rte_eth_fc_conf *fc_conf);
 331 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 332                               struct rte_eth_fc_conf *fc_conf);
 333 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 334                                        struct rte_eth_pfc_conf *pfc_conf);
 335 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 336                           struct ether_addr *mac_addr,
 337                           uint32_t index,
 338                           uint32_t pool);
 339 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 340 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 341                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 342                                     uint16_t reta_size);
 343 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 344                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 345                                    uint16_t reta_size);
 346
 347 static int i40e_get_cap(struct i40e_hw *hw);
 348 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 349 static int i40e_pf_setup(struct i40e_pf *pf);
 350 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 351 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 352 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 353 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 354 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 355                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 356 static void i40e_stat_update_48(struct i40e_hw *hw,
 357                                uint32_t hireg,
 358                                uint32_t loreg,
 359                                bool offset_loaded,
 360                                uint64_t *offset,
 361                                uint64_t *stat);
 362 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 363 static void i40e_dev_interrupt_handler(
 364                 __rte_unused struct rte_intr_handle *handle, void *param);
 365 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 366                                 uint32_t base, uint32_t num);
 367 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 368 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 369                         uint32_t base);
 370 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 371                         uint16_t num);
 372 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 373 static int i40e_veb_release(struct i40e_veb *veb);
 374 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 375                                                 struct i40e_vsi *vsi);
 376 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 377 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 378 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 379                                              struct i40e_macvlan_filter *mv_f,
 380                                              int num,
 381                                              struct ether_addr *addr);
 382 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 383                                              struct i40e_macvlan_filter *mv_f,
 384                                              int num,
 385                                              uint16_t vlan);
 386 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 387 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 388                                     struct rte_eth_rss_conf *rss_conf);
 389 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 390                                       struct rte_eth_rss_conf *rss_conf);
 391 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                         struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                         struct rte_eth_udp_tunnel *udp_tunnel);
 395 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 396 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 397                         struct rte_eth_ethertype_filter *filter,
 398                         bool add);
 399 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 400                                 enum rte_filter_op filter_op,
 401                                 void *arg);
 402 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 403                                 enum rte_filter_type filter_type,
 404                                 enum rte_filter_op filter_op,
 405                                 void *arg);
 406 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 407                                   struct rte_eth_dcb_info *dcb_info);
 408 static void i40e_configure_registers(struct i40e_hw *hw);
 409 static void i40e_hw_init(struct rte_eth_dev *dev);
 410 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 411 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 412                         struct rte_eth_mirror_conf *mirror_conf,
 413                         uint8_t sw_id, uint8_t on);
 414 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 415
 416 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 417 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 418 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 419                                            struct timespec *timestamp,
 420                                            uint32_t flags);
 421 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 422                                            struct timespec *timestamp);
 423 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 424
 425 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 426
 427 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 428                                    struct timespec *timestamp);
 429 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 430                                     const struct timespec *timestamp);
 431
 432 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 433                                          uint16_t queue_id);
 434 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 435                                           uint16_t queue_id);
 436
 437 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 438
 439 static int i40e_get_regs(struct rte_eth_dev *dev,
 440                          struct rte_dev_reg_info *regs);
 441
 442 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 443
 444 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 445                            struct rte_dev_eeprom_info *eeprom);
 446
 447 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 448                                       struct ether_addr *mac_addr);
 449
 450 static const struct rte_pci_id pci_id_i40e_map[] = {
 451 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 452 #include "rte_pci_dev_ids.h"
 453 { .vendor_id = 0, /* sentinel */ },
 454 };
 455
 456 static const struct eth_dev_ops i40e_eth_dev_ops = {
 457         .dev_configure                = i40e_dev_configure,
 458         .dev_start                    = i40e_dev_start,
 459         .dev_stop                     = i40e_dev_stop,
 460         .dev_close                    = i40e_dev_close,
 461         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 462         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 463         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 464         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 465         .dev_set_link_up              = i40e_dev_set_link_up,
 466         .dev_set_link_down            = i40e_dev_set_link_down,
 467         .link_update                  = i40e_dev_link_update,
 468         .stats_get                    = i40e_dev_stats_get,
 469         .xstats_get                   = i40e_dev_xstats_get,
 470         .stats_reset                  = i40e_dev_stats_reset,
 471         .xstats_reset                 = i40e_dev_stats_reset,
 472         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 473         .dev_infos_get                = i40e_dev_info_get,
 474         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 475         .vlan_filter_set              = i40e_vlan_filter_set,
 476         .vlan_tpid_set                = i40e_vlan_tpid_set,
 477         .vlan_offload_set             = i40e_vlan_offload_set,
 478         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 479         .vlan_pvid_set                = i40e_vlan_pvid_set,
 480         .rx_queue_start               = i40e_dev_rx_queue_start,
 481         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 482         .tx_queue_start               = i40e_dev_tx_queue_start,
 483         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 484         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 485         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 486         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 487         .rx_queue_release             = i40e_dev_rx_queue_release,
 488         .rx_queue_count               = i40e_dev_rx_queue_count,
 489         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .mirror_rule_set              = i40e_mirror_rule_set,
 509         .mirror_rule_reset            = i40e_mirror_rule_reset,
 510         .timesync_enable              = i40e_timesync_enable,
 511         .timesync_disable             = i40e_timesync_disable,
 512         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 513         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 514         .get_dcb_info                 = i40e_dev_get_dcb_info,
 515         .timesync_adjust_time         = i40e_timesync_adjust_time,
 516         .timesync_read_time           = i40e_timesync_read_time,
 517         .timesync_write_time          = i40e_timesync_write_time,
 518         .get_reg_length               = i40e_get_reg_length,
 519         .get_reg                      = i40e_get_regs,
 520         .get_eeprom_length            = i40e_get_eeprom_length,
 521         .get_eeprom                   = i40e_get_eeprom,
 522         .mac_addr_set                 = i40e_set_default_mac_addr,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_i40e_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 532         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 533         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 534         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 535         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 536         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 537                 rx_unknown_protocol)},
 538         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 539         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 540         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 541         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 542 };
 543
 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 545                 sizeof(rte_i40e_stats_strings[0]))
 546
 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 548         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 549                 tx_dropped_link_down)},
 550         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 551         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 552                 illegal_bytes)},
 553         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 554         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_local_faults)},
 556         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_remote_faults)},
 558         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_length_errors)},
 560         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 561         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 562         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 563         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 564         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 565         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_127)},
 567         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_255)},
 569         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_511)},
 571         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1023)},
 573         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1522)},
 575         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_big)},
 577         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_undersize)},
 579         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_oversize)},
 581         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 582                 mac_short_packet_dropped)},
 583         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_fragments)},
 585         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 586         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 587         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_127)},
 589         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_255)},
 591         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_511)},
 593         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1023)},
 595         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1522)},
 597         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_big)},
 599         {"rx_flow_director_atr_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 601         {"rx_flow_director_sb_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 603         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_status)},
 605         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_status)},
 607         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_count)},
 609         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_count)},
 611 };
 612
 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 614                 sizeof(rte_i40e_hw_port_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_rx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_rx)},
 621 };
 622
 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 624                 sizeof(rte_i40e_rxq_prio_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_tx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_tx)},
 631         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_2_xoff)},
 633 };
 634
 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 636                 sizeof(rte_i40e_txq_prio_strings[0]))
 637
 638 static struct eth_driver rte_i40e_pmd = {
 639         .pci_drv = {
 640                 .name = "rte_i40e_pmd",
 641                 .id_table = pci_id_i40e_map,
 642                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 643                         RTE_PCI_DRV_DETACHABLE,
 644         },
 645         .eth_dev_init = eth_i40e_dev_init,
 646         .eth_dev_uninit = eth_i40e_dev_uninit,
 647         .dev_private_size = sizeof(struct i40e_adapter),
 648 };
 649
 650 static inline int
 651 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 652                                      struct rte_eth_link *link)
 653 {
 654         struct rte_eth_link *dst = link;
 655         struct rte_eth_link *src = &(dev->data->dev_link);
 656
 657         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 658                                         *(uint64_t *)src) == 0)
 659                 return -1;
 660
 661         return 0;
 662 }
 663
 664 static inline int
 665 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 666                                       struct rte_eth_link *link)
 667 {
 668         struct rte_eth_link *dst = &(dev->data->dev_link);
 669         struct rte_eth_link *src = link;
 670
 671         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 672                                         *(uint64_t *)src) == 0)
 673                 return -1;
 674
 675         return 0;
 676 }
 677
 678 /*
 679  * Driver initialization routine.
 680  * Invoked once at EAL init time.
 681  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 682  */
 683 static int
 684 rte_i40e_pmd_init(const char *name __rte_unused,
 685                   const char *params __rte_unused)
 686 {
 687         PMD_INIT_FUNC_TRACE();
 688         rte_eth_driver_register(&rte_i40e_pmd);
 689
 690         return 0;
 691 }
 692
 693 static struct rte_driver rte_i40e_driver = {
 694         .type = PMD_PDEV,
 695         .init = rte_i40e_pmd_init,
 696 };
 697
 698 PMD_REGISTER_DRIVER(rte_i40e_driver);
 699
 700 /*
 701  * Initialize registers for flexible payload, which should be set by NVM.
 702  * This should be removed from code once it is fixed in NVM.
 703  */
 704 #ifndef I40E_GLQF_ORT
 705 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 706 #endif
 707 #ifndef I40E_GLQF_PIT
 708 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 709 #endif
 710
 711 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 712 {
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 723
 724         /* GLQF_PIT Registers */
 725         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 726         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 727 }
 728
 729 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 730
 731 /*
 732  * Add a ethertype filter to drop all flow control frames transmitted
 733  * from VSIs.
 734 */
 735 static void
 736 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 737 {
 738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 739         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 740                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 741                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 742         int ret;
 743
 744         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 745                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 746                                 pf->main_vsi_seid, 0,
 747                                 TRUE, NULL, NULL);
 748         if (ret)
 749                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 750                                   " frames from VSIs.");
 751 }
 752
 753 static int
 754 eth_i40e_dev_init(struct rte_eth_dev *dev)
 755 {
 756         struct rte_pci_device *pci_dev;
 757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 759         struct i40e_vsi *vsi;
 760         int ret;
 761         uint32_t len;
 762         uint8_t aq_fail = 0;
 763
 764         PMD_INIT_FUNC_TRACE();
 765
 766         dev->dev_ops = &i40e_eth_dev_ops;
 767         dev->rx_pkt_burst = i40e_recv_pkts;
 768         dev->tx_pkt_burst = i40e_xmit_pkts;
 769
 770         /* for secondary processes, we don't initialise any further as primary
 771          * has already done this work. Only check we don't need a different
 772          * RX function */
 773         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 774                 i40e_set_rx_function(dev);
 775                 i40e_set_tx_function(dev);
 776                 return 0;
 777         }
 778         pci_dev = dev->pci_dev;
 779
 780         rte_eth_copy_pci_info(dev, pci_dev);
 781
 782         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 783         pf->adapter->eth_dev = dev;
 784         pf->dev_data = dev->data;
 785
 786         hw->back = I40E_PF_TO_ADAPTER(pf);
 787         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 788         if (!hw->hw_addr) {
 789                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 790                              "as address is NULL");
 791                 return -ENODEV;
 792         }
 793
 794         hw->vendor_id = pci_dev->id.vendor_id;
 795         hw->device_id = pci_dev->id.device_id;
 796         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 797         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 798         hw->bus.device = pci_dev->addr.devid;
 799         hw->bus.func = pci_dev->addr.function;
 800         hw->adapter_stopped = 0;
 801
 802         /* Make sure all is clean before doing PF reset */
 803         i40e_clear_hw(hw);
 804
 805         /* Initialize the hardware */
 806         i40e_hw_init(dev);
 807
 808         /* Reset here to make sure all is clean for each PF */
 809         ret = i40e_pf_reset(hw);
 810         if (ret) {
 811                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 812                 return ret;
 813         }
 814
 815         /* Initialize the shared code (base driver) */
 816         ret = i40e_init_shared_code(hw);
 817         if (ret) {
 818                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 819                 return ret;
 820         }
 821
 822         /*
 823          * To work around the NVM issue,initialize registers
 824          * for flexible payload by software.
 825          * It should be removed once issues are fixed in NVM.
 826          */
 827         i40e_flex_payload_reg_init(hw);
 828
 829         /* Initialize the input set for filters (hash and fd) to default value */
 830         i40e_filter_input_set_init(pf);
 831
 832         /* Initialize the parameters for adminq */
 833         i40e_init_adminq_parameter(hw);
 834         ret = i40e_init_adminq(hw);
 835         if (ret != I40E_SUCCESS) {
 836                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 837                 return -EIO;
 838         }
 839         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 840                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 841                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 842                      ((hw->nvm.version >> 12) & 0xf),
 843                      ((hw->nvm.version >> 4) & 0xff),
 844                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 845
 846         /* Clear PXE mode */
 847         i40e_clear_pxe_mode(hw);
 848
 849         /*
 850          * On X710, performance number is far from the expectation on recent
 851          * firmware versions. The fix for this issue may not be integrated in
 852          * the following firmware version. So the workaround in software driver
 853          * is needed. It needs to modify the initial values of 3 internal only
 854          * registers. Note that the workaround can be removed when it is fixed
 855          * in firmware in the future.
 856          */
 857         i40e_configure_registers(hw);
 858
 859         /* Get hw capabilities */
 860         ret = i40e_get_cap(hw);
 861         if (ret != I40E_SUCCESS) {
 862                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 863                 goto err_get_capabilities;
 864         }
 865
 866         /* Initialize parameters for PF */
 867         ret = i40e_pf_parameter_init(dev);
 868         if (ret != 0) {
 869                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 870                 goto err_parameter_init;
 871         }
 872
 873         /* Initialize the queue management */
 874         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 875         if (ret < 0) {
 876                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 877                 goto err_qp_pool_init;
 878         }
 879         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 880                                 hw->func_caps.num_msix_vectors - 1);
 881         if (ret < 0) {
 882                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 883                 goto err_msix_pool_init;
 884         }
 885
 886         /* Initialize lan hmc */
 887         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 888                                 hw->func_caps.num_rx_qp, 0, 0);
 889         if (ret != I40E_SUCCESS) {
 890                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 891                 goto err_init_lan_hmc;
 892         }
 893
 894         /* Configure lan hmc */
 895         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 898                 goto err_configure_lan_hmc;
 899         }
 900
 901         /* Get and check the mac address */
 902         i40e_get_mac_addr(hw, hw->mac.addr);
 903         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 904                 PMD_INIT_LOG(ERR, "mac address is not valid");
 905                 ret = -EIO;
 906                 goto err_get_mac_addr;
 907         }
 908         /* Copy the permanent MAC address */
 909         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 910                         (struct ether_addr *) hw->mac.perm_addr);
 911
 912         /* Disable flow control */
 913         hw->fc.requested_mode = I40E_FC_NONE;
 914         i40e_set_fc(hw, &aq_fail, TRUE);
 915
 916         /* Set the global registers with default ether type value */
 917         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 918         if (ret != I40E_SUCCESS) {
 919                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 920                              "VLAN ether type");
 921                 goto err_setup_pf_switch;
 922         }
 923         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 924         if (ret != I40E_SUCCESS) {
 925                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 926                              "VLAN ether type");
 927                 goto err_setup_pf_switch;
 928         }
 929
 930         /* PF setup, which includes VSI setup */
 931         ret = i40e_pf_setup(pf);
 932         if (ret) {
 933                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 934                 goto err_setup_pf_switch;
 935         }
 936
 937         vsi = pf->main_vsi;
 938
 939         /* Disable double vlan by default */
 940         i40e_vsi_config_double_vlan(vsi, FALSE);
 941
 942         if (!vsi->max_macaddrs)
 943                 len = ETHER_ADDR_LEN;
 944         else
 945                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 946
 947         /* Should be after VSI initialized */
 948         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 949         if (!dev->data->mac_addrs) {
 950                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 951                                         "for storing mac address");
 952                 goto err_mac_alloc;
 953         }
 954         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 955                                         &dev->data->mac_addrs[0]);
 956
 957         /* initialize pf host driver to setup SRIOV resource if applicable */
 958         i40e_pf_host_init(dev);
 959
 960         /* register callback func to eal lib */
 961         rte_intr_callback_register(&(pci_dev->intr_handle),
 962                 i40e_dev_interrupt_handler, (void *)dev);
 963
 964         /* configure and enable device interrupt */
 965         i40e_pf_config_irq0(hw, TRUE);
 966         i40e_pf_enable_irq0(hw);
 967
 968         /* enable uio intr after callback register */
 969         rte_intr_enable(&(pci_dev->intr_handle));
 970         /*
 971          * Add an ethertype filter to drop all flow control frames transmitted
 972          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 973          * frames to wire.
 974          */
 975         i40e_add_tx_flow_control_drop_filter(pf);
 976
 977         /* Set the max frame size to 0x2600 by default,
 978          * in case other drivers changed the default value.
 979          */
 980         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 981
 982         /* initialize mirror rule list */
 983         TAILQ_INIT(&pf->mirror_list);
 984
 985         /* Init dcb to sw mode by default */
 986         ret = i40e_dcb_init_configure(dev, TRUE);
 987         if (ret != I40E_SUCCESS) {
 988                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 989                 pf->flags &= ~I40E_FLAG_DCB;
 990         }
 991
 992         return 0;
 993
 994 err_mac_alloc:
 995         i40e_vsi_release(pf->main_vsi);
 996 err_setup_pf_switch:
 997 err_get_mac_addr:
 998 err_configure_lan_hmc:
 999         (void)i40e_shutdown_lan_hmc(hw);
1000 err_init_lan_hmc:
1001         i40e_res_pool_destroy(&pf->msix_pool);
1002 err_msix_pool_init:
1003         i40e_res_pool_destroy(&pf->qp_pool);
1004 err_qp_pool_init:
1005 err_parameter_init:
1006 err_get_capabilities:
1007         (void)i40e_shutdown_adminq(hw);
1008
1009         return ret;
1010 }
1011
1012 static int
1013 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1014 {
1015         struct rte_pci_device *pci_dev;
1016         struct i40e_hw *hw;
1017         struct i40e_filter_control_settings settings;
1018         int ret;
1019         uint8_t aq_fail = 0;
1020
1021         PMD_INIT_FUNC_TRACE();
1022
1023         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1024                 return 0;
1025
1026         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         pci_dev = dev->pci_dev;
1028
1029         if (hw->adapter_stopped == 0)
1030                 i40e_dev_close(dev);
1031
1032         dev->dev_ops = NULL;
1033         dev->rx_pkt_burst = NULL;
1034         dev->tx_pkt_burst = NULL;
1035
1036         /* Disable LLDP */
1037         ret = i40e_aq_stop_lldp(hw, true, NULL);
1038         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1039                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1040
1041         /* Clear PXE mode */
1042         i40e_clear_pxe_mode(hw);
1043
1044         /* Unconfigure filter control */
1045         memset(&settings, 0, sizeof(settings));
1046         ret = i40e_set_filter_control(hw, &settings);
1047         if (ret)
1048                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1049                                         ret);
1050
1051         /* Disable flow control */
1052         hw->fc.requested_mode = I40E_FC_NONE;
1053         i40e_set_fc(hw, &aq_fail, TRUE);
1054
1055         /* uninitialize pf host driver */
1056         i40e_pf_host_uninit(dev);
1057
1058         rte_free(dev->data->mac_addrs);
1059         dev->data->mac_addrs = NULL;
1060
1061         /* disable uio intr before callback unregister */
1062         rte_intr_disable(&(pci_dev->intr_handle));
1063
1064         /* register callback func to eal lib */
1065         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1066                 i40e_dev_interrupt_handler, (void *)dev);
1067
1068         return 0;
1069 }
1070
1071 static int
1072 i40e_dev_configure(struct rte_eth_dev *dev)
1073 {
1074         struct i40e_adapter *ad =
1075                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1078         int i, ret;
1079
1080         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1081          * bulk allocation or vector Rx preconditions we will reset it.
1082          */
1083         ad->rx_bulk_alloc_allowed = true;
1084         ad->rx_vec_allowed = true;
1085         ad->tx_simple_allowed = true;
1086         ad->tx_vec_allowed = true;
1087
1088         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1089                 ret = i40e_fdir_setup(pf);
1090                 if (ret != I40E_SUCCESS) {
1091                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1092                         return -ENOTSUP;
1093                 }
1094                 ret = i40e_fdir_configure(dev);
1095                 if (ret < 0) {
1096                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1097                         goto err;
1098                 }
1099         } else
1100                 i40e_fdir_teardown(pf);
1101
1102         ret = i40e_dev_init_vlan(dev);
1103         if (ret < 0)
1104                 goto err;
1105
1106         /* VMDQ setup.
1107          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1108          *  RSS setting have different requirements.
1109          *  General PMD driver call sequence are NIC init, configure,
1110          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1111          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1112          *  applicable. So, VMDQ setting has to be done before
1113          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1114          *  For RSS setting, it will try to calculate actual configured RX queue
1115          *  number, which will be available after rx_queue_setup(). dev_start()
1116          *  function is good to place RSS setup.
1117          */
1118         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1119                 ret = i40e_vmdq_setup(dev);
1120                 if (ret)
1121                         goto err;
1122         }
1123
1124         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1125                 ret = i40e_dcb_setup(dev);
1126                 if (ret) {
1127                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1128                         goto err_dcb;
1129                 }
1130         }
1131
1132         return 0;
1133
1134 err_dcb:
1135         /* need to release vmdq resource if exists */
1136         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1137                 i40e_vsi_release(pf->vmdq[i].vsi);
1138                 pf->vmdq[i].vsi = NULL;
1139         }
1140         rte_free(pf->vmdq);
1141         pf->vmdq = NULL;
1142 err:
1143         /* need to release fdir resource if exists */
1144         i40e_fdir_teardown(pf);
1145         return ret;
1146 }
1147
1148 void
1149 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1150 {
1151         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1152         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1154         uint16_t msix_vect = vsi->msix_intr;
1155         uint16_t i;
1156
1157         for (i = 0; i < vsi->nb_qps; i++) {
1158                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1159                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1160                 rte_wmb();
1161         }
1162
1163         if (vsi->type != I40E_VSI_SRIOV) {
1164                 if (!rte_intr_allow_others(intr_handle)) {
1165                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1166                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1167                         I40E_WRITE_REG(hw,
1168                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1169                                        0);
1170                 } else {
1171                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1172                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1173                         I40E_WRITE_REG(hw,
1174                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1175                                                        msix_vect - 1), 0);
1176                 }
1177         } else {
1178                 uint32_t reg;
1179                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1180                         vsi->user_param + (msix_vect - 1);
1181
1182                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1183                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1184         }
1185         I40E_WRITE_FLUSH(hw);
1186 }
1187
1188 static void
1189 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1190                        int base_queue, int nb_queue)
1191 {
1192         int i;
1193         uint32_t val;
1194         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1195
1196         /* Bind all RX queues to allocated MSIX interrupt */
1197         for (i = 0; i < nb_queue; i++) {
1198                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1199                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1200                         ((base_queue + i + 1) <<
1201                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1202                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1203                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1204
1205                 if (i == nb_queue - 1)
1206                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1207                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1208         }
1209
1210         /* Write first RX queue to Link list register as the head element */
1211         if (vsi->type != I40E_VSI_SRIOV) {
1212                 uint16_t interval =
1213                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1214
1215                 if (msix_vect == I40E_MISC_VEC_ID) {
1216                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1217                                        (base_queue <<
1218                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1219                                        (0x0 <<
1220                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1221                         I40E_WRITE_REG(hw,
1222                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1223                                        interval);
1224                 } else {
1225                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1226                                        (base_queue <<
1227                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1228                                        (0x0 <<
1229                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1230                         I40E_WRITE_REG(hw,
1231                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1232                                                        msix_vect - 1),
1233                                        interval);
1234                 }
1235         } else {
1236                 uint32_t reg;
1237
1238                 if (msix_vect == I40E_MISC_VEC_ID) {
1239                         I40E_WRITE_REG(hw,
1240                                        I40E_VPINT_LNKLST0(vsi->user_param),
1241                                        (base_queue <<
1242                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1243                                        (0x0 <<
1244                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1245                 } else {
1246                         /* num_msix_vectors_vf needs to minus irq0 */
1247                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1248                                 vsi->user_param + (msix_vect - 1);
1249
1250                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1251                                        (base_queue <<
1252                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1253                                        (0x0 <<
1254                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1255                 }
1256         }
1257
1258         I40E_WRITE_FLUSH(hw);
1259 }
1260
1261 void
1262 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1263 {
1264         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1265         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1266         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1267         uint16_t msix_vect = vsi->msix_intr;
1268         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1269         uint16_t queue_idx = 0;
1270         int record = 0;
1271         uint32_t val;
1272         int i;
1273
1274         for (i = 0; i < vsi->nb_qps; i++) {
1275                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1276                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1277         }
1278
1279         /* INTENA flag is not auto-cleared for interrupt */
1280         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1281         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1282                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1283                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1284         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1285
1286         /* VF bind interrupt */
1287         if (vsi->type == I40E_VSI_SRIOV) {
1288                 __vsi_queues_bind_intr(vsi, msix_vect,
1289                                        vsi->base_queue, vsi->nb_qps);
1290                 return;
1291         }
1292
1293         /* PF & VMDq bind interrupt */
1294         if (rte_intr_dp_is_en(intr_handle)) {
1295                 if (vsi->type == I40E_VSI_MAIN) {
1296                         queue_idx = 0;
1297                         record = 1;
1298                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1299                         struct i40e_vsi *main_vsi =
1300                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1301                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1302                         record = 1;
1303                 }
1304         }
1305
1306         for (i = 0; i < vsi->nb_used_qps; i++) {
1307                 if (nb_msix <= 1) {
1308                         if (!rte_intr_allow_others(intr_handle))
1309                                 /* allow to share MISC_VEC_ID */
1310                                 msix_vect = I40E_MISC_VEC_ID;
1311
1312                         /* no enough msix_vect, map all to one */
1313                         __vsi_queues_bind_intr(vsi, msix_vect,
1314                                                vsi->base_queue + i,
1315                                                vsi->nb_used_qps - i);
1316                         for (; !!record && i < vsi->nb_used_qps; i++)
1317                                 intr_handle->intr_vec[queue_idx + i] =
1318                                         msix_vect;
1319                         break;
1320                 }
1321                 /* 1:1 queue/msix_vect mapping */
1322                 __vsi_queues_bind_intr(vsi, msix_vect,
1323                                        vsi->base_queue + i, 1);
1324                 if (!!record)
1325                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1326
1327                 msix_vect++;
1328                 nb_msix--;
1329         }
1330 }
1331
1332 static void
1333 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1334 {
1335         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1336         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1337         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1338         uint16_t interval = i40e_calc_itr_interval(\
1339                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1340         uint16_t msix_intr, i;
1341
1342         if (rte_intr_allow_others(intr_handle))
1343                 for (i = 0; i < vsi->nb_msix; i++) {
1344                         msix_intr = vsi->msix_intr + i;
1345                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1346                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1347                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1348                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1349                                 (interval <<
1350                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1351                 }
1352         else
1353                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1354                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1355                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1356                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1357                                (interval <<
1358                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1359
1360         I40E_WRITE_FLUSH(hw);
1361 }
1362
1363 static void
1364 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1365 {
1366         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1367         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1368         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1369         uint16_t msix_intr, i;
1370
1371         if (rte_intr_allow_others(intr_handle))
1372                 for (i = 0; i < vsi->nb_msix; i++) {
1373                         msix_intr = vsi->msix_intr + i;
1374                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1375                                        0);
1376                 }
1377         else
1378                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1379
1380         I40E_WRITE_FLUSH(hw);
1381 }
1382
1383 static inline uint8_t
1384 i40e_parse_link_speed(uint16_t eth_link_speed)
1385 {
1386         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1387
1388         switch (eth_link_speed) {
1389         case ETH_LINK_SPEED_40G:
1390                 link_speed = I40E_LINK_SPEED_40GB;
1391                 break;
1392         case ETH_LINK_SPEED_20G:
1393                 link_speed = I40E_LINK_SPEED_20GB;
1394                 break;
1395         case ETH_LINK_SPEED_10G:
1396                 link_speed = I40E_LINK_SPEED_10GB;
1397                 break;
1398         case ETH_LINK_SPEED_1000:
1399                 link_speed = I40E_LINK_SPEED_1GB;
1400                 break;
1401         case ETH_LINK_SPEED_100:
1402                 link_speed = I40E_LINK_SPEED_100MB;
1403                 break;
1404         }
1405
1406         return link_speed;
1407 }
1408
1409 static int
1410 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1411                    __rte_unused uint8_t abilities,
1412                    __rte_unused uint8_t force_speed)
1413 {
1414         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1415          * for the link control limitation of that all link control should be
1416          * handled by firmware. It should follow up if link control will be
1417          * opened to software driver in future firmware versions.
1418          */
1419         return I40E_SUCCESS;
1420 }
1421
1422 static int
1423 i40e_apply_link_speed(struct rte_eth_dev *dev)
1424 {
1425         uint8_t speed;
1426         uint8_t abilities = 0;
1427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct rte_eth_conf *conf = &dev->data->dev_conf;
1429
1430         speed = i40e_parse_link_speed(conf->link_speed);
1431         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1432         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1433                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1434         else
1435                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1436
1437         return i40e_phy_conf_link(hw, abilities, speed);
1438 }
1439
1440 static int
1441 i40e_dev_start(struct rte_eth_dev *dev)
1442 {
1443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         struct i40e_vsi *main_vsi = pf->main_vsi;
1446         int ret, i;
1447         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448         uint32_t intr_vector = 0;
1449
1450         hw->adapter_stopped = 0;
1451
1452         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1453                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1454                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1455                              dev->data->dev_conf.link_duplex,
1456                              dev->data->port_id);
1457                 return -EINVAL;
1458         }
1459
1460         rte_intr_disable(intr_handle);
1461
1462         if ((rte_intr_cap_multiple(intr_handle) ||
1463              !RTE_ETH_DEV_SRIOV(dev).active) &&
1464             dev->data->dev_conf.intr_conf.rxq != 0) {
1465                 intr_vector = dev->data->nb_rx_queues;
1466                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1467                         return -1;
1468         }
1469
1470         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1471                 intr_handle->intr_vec =
1472                         rte_zmalloc("intr_vec",
1473                                     dev->data->nb_rx_queues * sizeof(int),
1474                                     0);
1475                 if (!intr_handle->intr_vec) {
1476                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1477                                      " intr_vec\n", dev->data->nb_rx_queues);
1478                         return -ENOMEM;
1479                 }
1480         }
1481
1482         /* Initialize VSI */
1483         ret = i40e_dev_rxtx_init(pf);
1484         if (ret != I40E_SUCCESS) {
1485                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1486                 goto err_up;
1487         }
1488
1489         /* Map queues with MSIX interrupt */
1490         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1491                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1492         i40e_vsi_queues_bind_intr(main_vsi);
1493         i40e_vsi_enable_queues_intr(main_vsi);
1494
1495         /* Map VMDQ VSI queues with MSIX interrupt */
1496         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1497                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1498                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1499                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1500         }
1501
1502         /* enable FDIR MSIX interrupt */
1503         if (pf->fdir.fdir_vsi) {
1504                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1505                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1506         }
1507
1508         /* Enable all queues which have been configured */
1509         ret = i40e_dev_switch_queues(pf, TRUE);
1510         if (ret != I40E_SUCCESS) {
1511                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1512                 goto err_up;
1513         }
1514
1515         /* Enable receiving broadcast packets */
1516         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1517         if (ret != I40E_SUCCESS)
1518                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1519
1520         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1521                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1522                                                 true, NULL);
1523                 if (ret != I40E_SUCCESS)
1524                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1525         }
1526
1527         /* Apply link configure */
1528         ret = i40e_apply_link_speed(dev);
1529         if (I40E_SUCCESS != ret) {
1530                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1531                 goto err_up;
1532         }
1533
1534         if (!rte_intr_allow_others(intr_handle)) {
1535                 rte_intr_callback_unregister(intr_handle,
1536                                              i40e_dev_interrupt_handler,
1537                                              (void *)dev);
1538                 /* configure and enable device interrupt */
1539                 i40e_pf_config_irq0(hw, FALSE);
1540                 i40e_pf_enable_irq0(hw);
1541
1542                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1543                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1544                                      " no intr multiplex\n");
1545         }
1546
1547         /* enable uio intr after callback register */
1548         rte_intr_enable(intr_handle);
1549
1550         return I40E_SUCCESS;
1551
1552 err_up:
1553         i40e_dev_switch_queues(pf, FALSE);
1554         i40e_dev_clear_queues(dev);
1555
1556         return ret;
1557 }
1558
1559 static void
1560 i40e_dev_stop(struct rte_eth_dev *dev)
1561 {
1562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1563         struct i40e_vsi *main_vsi = pf->main_vsi;
1564         struct i40e_mirror_rule *p_mirror;
1565         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1566         int i;
1567
1568         /* Disable all queues */
1569         i40e_dev_switch_queues(pf, FALSE);
1570
1571         /* un-map queues with interrupt registers */
1572         i40e_vsi_disable_queues_intr(main_vsi);
1573         i40e_vsi_queues_unbind_intr(main_vsi);
1574
1575         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1576                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1577                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1578         }
1579
1580         if (pf->fdir.fdir_vsi) {
1581                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1582                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1583         }
1584         /* Clear all queues and release memory */
1585         i40e_dev_clear_queues(dev);
1586
1587         /* Set link down */
1588         i40e_dev_set_link_down(dev);
1589
1590         /* Remove all mirror rules */
1591         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1592                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1593                 rte_free(p_mirror);
1594         }
1595         pf->nb_mirror_rule = 0;
1596
1597         if (!rte_intr_allow_others(intr_handle))
1598                 /* resume to the default handler */
1599                 rte_intr_callback_register(intr_handle,
1600                                            i40e_dev_interrupt_handler,
1601                                            (void *)dev);
1602
1603         /* Clean datapath event and queue/vec mapping */
1604         rte_intr_efd_disable(intr_handle);
1605         if (intr_handle->intr_vec) {
1606                 rte_free(intr_handle->intr_vec);
1607                 intr_handle->intr_vec = NULL;
1608         }
1609 }
1610
1611 static void
1612 i40e_dev_close(struct rte_eth_dev *dev)
1613 {
1614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         uint32_t reg;
1617         int i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         i40e_dev_stop(dev);
1622         hw->adapter_stopped = 1;
1623         i40e_dev_free_queues(dev);
1624
1625         /* Disable interrupt */
1626         i40e_pf_disable_irq0(hw);
1627         rte_intr_disable(&(dev->pci_dev->intr_handle));
1628
1629         /* shutdown and destroy the HMC */
1630         i40e_shutdown_lan_hmc(hw);
1631
1632         /* release all the existing VSIs and VEBs */
1633         i40e_fdir_teardown(pf);
1634         i40e_vsi_release(pf->main_vsi);
1635
1636         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1637                 i40e_vsi_release(pf->vmdq[i].vsi);
1638                 pf->vmdq[i].vsi = NULL;
1639         }
1640
1641         rte_free(pf->vmdq);
1642         pf->vmdq = NULL;
1643
1644         /* shutdown the adminq */
1645         i40e_aq_queue_shutdown(hw, true);
1646         i40e_shutdown_adminq(hw);
1647
1648         i40e_res_pool_destroy(&pf->qp_pool);
1649         i40e_res_pool_destroy(&pf->msix_pool);
1650
1651         /* force a PF reset to clean anything leftover */
1652         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1653         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1654                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1655         I40E_WRITE_FLUSH(hw);
1656 }
1657
1658 static void
1659 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1660 {
1661         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         struct i40e_vsi *vsi = pf->main_vsi;
1664         int status;
1665
1666         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1667                                                         true, NULL);
1668         if (status != I40E_SUCCESS)
1669                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1670
1671         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1672                                                         TRUE, NULL);
1673         if (status != I40E_SUCCESS)
1674                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1675
1676 }
1677
1678 static void
1679 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1680 {
1681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683         struct i40e_vsi *vsi = pf->main_vsi;
1684         int status;
1685
1686         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1687                                                         false, NULL);
1688         if (status != I40E_SUCCESS)
1689                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1690
1691         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1692                                                         false, NULL);
1693         if (status != I40E_SUCCESS)
1694                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1695 }
1696
1697 static void
1698 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1699 {
1700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct i40e_vsi *vsi = pf->main_vsi;
1703         int ret;
1704
1705         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1706         if (ret != I40E_SUCCESS)
1707                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1708 }
1709
1710 static void
1711 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1712 {
1713         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715         struct i40e_vsi *vsi = pf->main_vsi;
1716         int ret;
1717
1718         if (dev->data->promiscuous == 1)
1719                 return; /* must remain in all_multicast mode */
1720
1721         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1722                                 vsi->seid, FALSE, NULL);
1723         if (ret != I40E_SUCCESS)
1724                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1725 }
1726
1727 /*
1728  * Set device link up.
1729  */
1730 static int
1731 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1732 {
1733         /* re-apply link speed setting */
1734         return i40e_apply_link_speed(dev);
1735 }
1736
1737 /*
1738  * Set device link down.
1739  */
1740 static int
1741 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1742 {
1743         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1744         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746
1747         return i40e_phy_conf_link(hw, abilities, speed);
1748 }
1749
1750 int
1751 i40e_dev_link_update(struct rte_eth_dev *dev,
1752                      int wait_to_complete)
1753 {
1754 #define CHECK_INTERVAL 100  /* 100ms */
1755 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         struct i40e_link_status link_status;
1758         struct rte_eth_link link, old;
1759         int status;
1760         unsigned rep_cnt = MAX_REPEAT_TIME;
1761
1762         memset(&link, 0, sizeof(link));
1763         memset(&old, 0, sizeof(old));
1764         memset(&link_status, 0, sizeof(link_status));
1765         rte_i40e_dev_atomic_read_link_status(dev, &old);
1766
1767         do {
1768                 /* Get link status information from hardware */
1769                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1770                 if (status != I40E_SUCCESS) {
1771                         link.link_speed = ETH_LINK_SPEED_100;
1772                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1773                         PMD_DRV_LOG(ERR, "Failed to get link info");
1774                         goto out;
1775                 }
1776
1777                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1778                 if (!wait_to_complete)
1779                         break;
1780
1781                 rte_delay_ms(CHECK_INTERVAL);
1782         } while (!link.link_status && rep_cnt--);
1783
1784         if (!link.link_status)
1785                 goto out;
1786
1787         /* i40e uses full duplex only */
1788         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1789
1790         /* Parse the link status */
1791         switch (link_status.link_speed) {
1792         case I40E_LINK_SPEED_100MB:
1793                 link.link_speed = ETH_LINK_SPEED_100;
1794                 break;
1795         case I40E_LINK_SPEED_1GB:
1796                 link.link_speed = ETH_LINK_SPEED_1000;
1797                 break;
1798         case I40E_LINK_SPEED_10GB:
1799                 link.link_speed = ETH_LINK_SPEED_10G;
1800                 break;
1801         case I40E_LINK_SPEED_20GB:
1802                 link.link_speed = ETH_LINK_SPEED_20G;
1803                 break;
1804         case I40E_LINK_SPEED_40GB:
1805                 link.link_speed = ETH_LINK_SPEED_40G;
1806                 break;
1807         default:
1808                 link.link_speed = ETH_LINK_SPEED_100;
1809                 break;
1810         }
1811
1812 out:
1813         rte_i40e_dev_atomic_write_link_status(dev, &link);
1814         if (link.link_status == old.link_status)
1815                 return -1;
1816
1817         return 0;
1818 }
1819
1820 /* Get all the statistics of a VSI */
1821 void
1822 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1823 {
1824         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1825         struct i40e_eth_stats *nes = &vsi->eth_stats;
1826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1827         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1828
1829         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1830                             vsi->offset_loaded, &oes->rx_bytes,
1831                             &nes->rx_bytes);
1832         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1833                             vsi->offset_loaded, &oes->rx_unicast,
1834                             &nes->rx_unicast);
1835         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1836                             vsi->offset_loaded, &oes->rx_multicast,
1837                             &nes->rx_multicast);
1838         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1839                             vsi->offset_loaded, &oes->rx_broadcast,
1840                             &nes->rx_broadcast);
1841         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1842                             &oes->rx_discards, &nes->rx_discards);
1843         /* GLV_REPC not supported */
1844         /* GLV_RMPC not supported */
1845         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1846                             &oes->rx_unknown_protocol,
1847                             &nes->rx_unknown_protocol);
1848         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1849                             vsi->offset_loaded, &oes->tx_bytes,
1850                             &nes->tx_bytes);
1851         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1852                             vsi->offset_loaded, &oes->tx_unicast,
1853                             &nes->tx_unicast);
1854         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1855                             vsi->offset_loaded, &oes->tx_multicast,
1856                             &nes->tx_multicast);
1857         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1858                             vsi->offset_loaded,  &oes->tx_broadcast,
1859                             &nes->tx_broadcast);
1860         /* GLV_TDPC not supported */
1861         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1862                             &oes->tx_errors, &nes->tx_errors);
1863         vsi->offset_loaded = true;
1864
1865         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1866                     vsi->vsi_id);
1867         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1868         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1869         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1870         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1871         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1872         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1873                     nes->rx_unknown_protocol);
1874         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1875         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1876         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1877         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1878         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1879         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1880         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1881                     vsi->vsi_id);
1882 }
1883
1884 static void
1885 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1886 {
1887         unsigned int i;
1888         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1889         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1890
1891         /* Get statistics of struct i40e_eth_stats */
1892         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1893                             I40E_GLPRT_GORCL(hw->port),
1894                             pf->offset_loaded, &os->eth.rx_bytes,
1895                             &ns->eth.rx_bytes);
1896         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1897                             I40E_GLPRT_UPRCL(hw->port),
1898                             pf->offset_loaded, &os->eth.rx_unicast,
1899                             &ns->eth.rx_unicast);
1900         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1901                             I40E_GLPRT_MPRCL(hw->port),
1902                             pf->offset_loaded, &os->eth.rx_multicast,
1903                             &ns->eth.rx_multicast);
1904         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1905                             I40E_GLPRT_BPRCL(hw->port),
1906                             pf->offset_loaded, &os->eth.rx_broadcast,
1907                             &ns->eth.rx_broadcast);
1908         /* Workaround: CRC size should not be included in byte statistics,
1909          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1910          */
1911         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1912                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1913
1914         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1915                             pf->offset_loaded, &os->eth.rx_discards,
1916                             &ns->eth.rx_discards);
1917         /* GLPRT_REPC not supported */
1918         /* GLPRT_RMPC not supported */
1919         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1920                             pf->offset_loaded,
1921                             &os->eth.rx_unknown_protocol,
1922                             &ns->eth.rx_unknown_protocol);
1923         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1924                             I40E_GLPRT_GOTCL(hw->port),
1925                             pf->offset_loaded, &os->eth.tx_bytes,
1926                             &ns->eth.tx_bytes);
1927         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1928                             I40E_GLPRT_UPTCL(hw->port),
1929                             pf->offset_loaded, &os->eth.tx_unicast,
1930                             &ns->eth.tx_unicast);
1931         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1932                             I40E_GLPRT_MPTCL(hw->port),
1933                             pf->offset_loaded, &os->eth.tx_multicast,
1934                             &ns->eth.tx_multicast);
1935         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1936                             I40E_GLPRT_BPTCL(hw->port),
1937                             pf->offset_loaded, &os->eth.tx_broadcast,
1938                             &ns->eth.tx_broadcast);
1939         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1940                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1941         /* GLPRT_TEPC not supported */
1942
1943         /* additional port specific stats */
1944         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1945                             pf->offset_loaded, &os->tx_dropped_link_down,
1946                             &ns->tx_dropped_link_down);
1947         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1948                             pf->offset_loaded, &os->crc_errors,
1949                             &ns->crc_errors);
1950         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1951                             pf->offset_loaded, &os->illegal_bytes,
1952                             &ns->illegal_bytes);
1953         /* GLPRT_ERRBC not supported */
1954         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1955                             pf->offset_loaded, &os->mac_local_faults,
1956                             &ns->mac_local_faults);
1957         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1958                             pf->offset_loaded, &os->mac_remote_faults,
1959                             &ns->mac_remote_faults);
1960         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1961                             pf->offset_loaded, &os->rx_length_errors,
1962                             &ns->rx_length_errors);
1963         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1964                             pf->offset_loaded, &os->link_xon_rx,
1965                             &ns->link_xon_rx);
1966         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1967                             pf->offset_loaded, &os->link_xoff_rx,
1968                             &ns->link_xoff_rx);
1969         for (i = 0; i < 8; i++) {
1970                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1971                                     pf->offset_loaded,
1972                                     &os->priority_xon_rx[i],
1973                                     &ns->priority_xon_rx[i]);
1974                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1975                                     pf->offset_loaded,
1976                                     &os->priority_xoff_rx[i],
1977                                     &ns->priority_xoff_rx[i]);
1978         }
1979         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1980                             pf->offset_loaded, &os->link_xon_tx,
1981                             &ns->link_xon_tx);
1982         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1983                             pf->offset_loaded, &os->link_xoff_tx,
1984                             &ns->link_xoff_tx);
1985         for (i = 0; i < 8; i++) {
1986                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1987                                     pf->offset_loaded,
1988                                     &os->priority_xon_tx[i],
1989                                     &ns->priority_xon_tx[i]);
1990                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1991                                     pf->offset_loaded,
1992                                     &os->priority_xoff_tx[i],
1993                                     &ns->priority_xoff_tx[i]);
1994                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1995                                     pf->offset_loaded,
1996                                     &os->priority_xon_2_xoff[i],
1997                                     &ns->priority_xon_2_xoff[i]);
1998         }
1999         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2000                             I40E_GLPRT_PRC64L(hw->port),
2001                             pf->offset_loaded, &os->rx_size_64,
2002                             &ns->rx_size_64);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2004                             I40E_GLPRT_PRC127L(hw->port),
2005                             pf->offset_loaded, &os->rx_size_127,
2006                             &ns->rx_size_127);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2008                             I40E_GLPRT_PRC255L(hw->port),
2009                             pf->offset_loaded, &os->rx_size_255,
2010                             &ns->rx_size_255);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2012                             I40E_GLPRT_PRC511L(hw->port),
2013                             pf->offset_loaded, &os->rx_size_511,
2014                             &ns->rx_size_511);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2016                             I40E_GLPRT_PRC1023L(hw->port),
2017                             pf->offset_loaded, &os->rx_size_1023,
2018                             &ns->rx_size_1023);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2020                             I40E_GLPRT_PRC1522L(hw->port),
2021                             pf->offset_loaded, &os->rx_size_1522,
2022                             &ns->rx_size_1522);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2024                             I40E_GLPRT_PRC9522L(hw->port),
2025                             pf->offset_loaded, &os->rx_size_big,
2026                             &ns->rx_size_big);
2027         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2028                             pf->offset_loaded, &os->rx_undersize,
2029                             &ns->rx_undersize);
2030         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2031                             pf->offset_loaded, &os->rx_fragments,
2032                             &ns->rx_fragments);
2033         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2034                             pf->offset_loaded, &os->rx_oversize,
2035                             &ns->rx_oversize);
2036         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2037                             pf->offset_loaded, &os->rx_jabber,
2038                             &ns->rx_jabber);
2039         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2040                             I40E_GLPRT_PTC64L(hw->port),
2041                             pf->offset_loaded, &os->tx_size_64,
2042                             &ns->tx_size_64);
2043         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2044                             I40E_GLPRT_PTC127L(hw->port),
2045                             pf->offset_loaded, &os->tx_size_127,
2046                             &ns->tx_size_127);
2047         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2048                             I40E_GLPRT_PTC255L(hw->port),
2049                             pf->offset_loaded, &os->tx_size_255,
2050                             &ns->tx_size_255);
2051         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2052                             I40E_GLPRT_PTC511L(hw->port),
2053                             pf->offset_loaded, &os->tx_size_511,
2054                             &ns->tx_size_511);
2055         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2056                             I40E_GLPRT_PTC1023L(hw->port),
2057                             pf->offset_loaded, &os->tx_size_1023,
2058                             &ns->tx_size_1023);
2059         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2060                             I40E_GLPRT_PTC1522L(hw->port),
2061                             pf->offset_loaded, &os->tx_size_1522,
2062                             &ns->tx_size_1522);
2063         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2064                             I40E_GLPRT_PTC9522L(hw->port),
2065                             pf->offset_loaded, &os->tx_size_big,
2066                             &ns->tx_size_big);
2067         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2068                            pf->offset_loaded,
2069                            &os->fd_sb_match, &ns->fd_sb_match);
2070         /* GLPRT_MSPDC not supported */
2071         /* GLPRT_XEC not supported */
2072
2073         pf->offset_loaded = true;
2074
2075         if (pf->main_vsi)
2076                 i40e_update_vsi_stats(pf->main_vsi);
2077 }
2078
2079 /* Get all statistics of a port */
2080 static void
2081 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2082 {
2083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2086         unsigned i;
2087
2088         /* call read registers - updates values, now write them to struct */
2089         i40e_read_stats_registers(pf, hw);
2090
2091         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2092                         pf->main_vsi->eth_stats.rx_multicast +
2093                         pf->main_vsi->eth_stats.rx_broadcast -
2094                         pf->main_vsi->eth_stats.rx_discards;
2095         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2096                         pf->main_vsi->eth_stats.tx_multicast +
2097                         pf->main_vsi->eth_stats.tx_broadcast;
2098         stats->ibytes   = ns->eth.rx_bytes;
2099         stats->obytes   = ns->eth.tx_bytes;
2100         stats->oerrors  = ns->eth.tx_errors +
2101                         pf->main_vsi->eth_stats.tx_errors;
2102         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2103
2104         /* Rx Errors */
2105         stats->imissed  = ns->eth.rx_discards +
2106                         pf->main_vsi->eth_stats.rx_discards;
2107         stats->ierrors  = ns->crc_errors +
2108                         ns->rx_length_errors + ns->rx_undersize +
2109                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2110
2111         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2112         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2113         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2114         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2115         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2116         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2117         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2118                     ns->eth.rx_unknown_protocol);
2119         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2120         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2121         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2122         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2123         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2124         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2125
2126         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2127                     ns->tx_dropped_link_down);
2128         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2129         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2130                     ns->illegal_bytes);
2131         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2132         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2133                     ns->mac_local_faults);
2134         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2135                     ns->mac_remote_faults);
2136         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2137                     ns->rx_length_errors);
2138         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2139         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2140         for (i = 0; i < 8; i++) {
2141                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2142                                 i, ns->priority_xon_rx[i]);
2143                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2144                                 i, ns->priority_xoff_rx[i]);
2145         }
2146         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2147         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2148         for (i = 0; i < 8; i++) {
2149                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2150                                 i, ns->priority_xon_tx[i]);
2151                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2152                                 i, ns->priority_xoff_tx[i]);
2153                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2154                                 i, ns->priority_xon_2_xoff[i]);
2155         }
2156         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2157         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2158         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2159         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2160         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2161         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2162         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2163         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2164         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2165         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2166         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2167         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2168         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2169         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2170         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2171         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2172         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2173         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2174         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2175                         ns->mac_short_packet_dropped);
2176         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2177                     ns->checksum_error);
2178         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2179         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2180 }
2181
2182 /* Reset the statistics */
2183 static void
2184 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2185 {
2186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188
2189         /* Mark PF and VSI stats to update the offset, aka "reset" */
2190         pf->offset_loaded = false;
2191         if (pf->main_vsi)
2192                 pf->main_vsi->offset_loaded = false;
2193
2194         /* read the stats, reading current register values into offset */
2195         i40e_read_stats_registers(pf, hw);
2196 }
2197
2198 static uint32_t
2199 i40e_xstats_calc_num(void)
2200 {
2201         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2202                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2203                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2204 }
2205
2206 static int
2207 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2208                     unsigned n)
2209 {
2210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         unsigned i, count, prio;
2213         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2214
2215         count = i40e_xstats_calc_num();
2216         if (n < count)
2217                 return count;
2218
2219         i40e_read_stats_registers(pf, hw);
2220
2221         if (xstats == NULL)
2222                 return 0;
2223
2224         count = 0;
2225
2226         /* Get stats from i40e_eth_stats struct */
2227         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2228                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2229                          "%s", rte_i40e_stats_strings[i].name);
2230                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2231                         rte_i40e_stats_strings[i].offset);
2232                 count++;
2233         }
2234
2235         /* Get individiual stats from i40e_hw_port struct */
2236         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2237                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2238                          "%s", rte_i40e_hw_port_strings[i].name);
2239                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2240                                 rte_i40e_hw_port_strings[i].offset);
2241                 count++;
2242         }
2243
2244         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2245                 for (prio = 0; prio < 8; prio++) {
2246                         snprintf(xstats[count].name,
2247                                  sizeof(xstats[count].name),
2248                                  "rx_priority%u_%s", prio,
2249                                  rte_i40e_rxq_prio_strings[i].name);
2250                         xstats[count].value =
2251                                 *(uint64_t *)(((char *)hw_stats) +
2252                                 rte_i40e_rxq_prio_strings[i].offset +
2253                                 (sizeof(uint64_t) * prio));
2254                         count++;
2255                 }
2256         }
2257
2258         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2259                 for (prio = 0; prio < 8; prio++) {
2260                         snprintf(xstats[count].name,
2261                                  sizeof(xstats[count].name),
2262                                  "tx_priority%u_%s", prio,
2263                                  rte_i40e_txq_prio_strings[i].name);
2264                         xstats[count].value =
2265                                 *(uint64_t *)(((char *)hw_stats) +
2266                                 rte_i40e_txq_prio_strings[i].offset +
2267                                 (sizeof(uint64_t) * prio));
2268                         count++;
2269                 }
2270         }
2271
2272         return count;
2273 }
2274
2275 static int
2276 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2277                                  __rte_unused uint16_t queue_id,
2278                                  __rte_unused uint8_t stat_idx,
2279                                  __rte_unused uint8_t is_rx)
2280 {
2281         PMD_INIT_FUNC_TRACE();
2282
2283         return -ENOSYS;
2284 }
2285
2286 static void
2287 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2288 {
2289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2290         struct i40e_vsi *vsi = pf->main_vsi;
2291
2292         dev_info->max_rx_queues = vsi->nb_qps;
2293         dev_info->max_tx_queues = vsi->nb_qps;
2294         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2295         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2296         dev_info->max_mac_addrs = vsi->max_macaddrs;
2297         dev_info->max_vfs = dev->pci_dev->max_vfs;
2298         dev_info->rx_offload_capa =
2299                 DEV_RX_OFFLOAD_VLAN_STRIP |
2300                 DEV_RX_OFFLOAD_QINQ_STRIP |
2301                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2302                 DEV_RX_OFFLOAD_UDP_CKSUM |
2303                 DEV_RX_OFFLOAD_TCP_CKSUM;
2304         dev_info->tx_offload_capa =
2305                 DEV_TX_OFFLOAD_VLAN_INSERT |
2306                 DEV_TX_OFFLOAD_QINQ_INSERT |
2307                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2308                 DEV_TX_OFFLOAD_UDP_CKSUM |
2309                 DEV_TX_OFFLOAD_TCP_CKSUM |
2310                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2311                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2312                 DEV_TX_OFFLOAD_TCP_TSO;
2313         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2314                                                 sizeof(uint32_t);
2315         dev_info->reta_size = pf->hash_lut_size;
2316         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2317
2318         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2319                 .rx_thresh = {
2320                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2321                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2322                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2323                 },
2324                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2325                 .rx_drop_en = 0,
2326         };
2327
2328         dev_info->default_txconf = (struct rte_eth_txconf) {
2329                 .tx_thresh = {
2330                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2331                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2332                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2333                 },
2334                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2335                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2336                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2337                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2338         };
2339
2340         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2341                 .nb_max = I40E_MAX_RING_DESC,
2342                 .nb_min = I40E_MIN_RING_DESC,
2343                 .nb_align = I40E_ALIGN_RING_DESC,
2344         };
2345
2346         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2347                 .nb_max = I40E_MAX_RING_DESC,
2348                 .nb_min = I40E_MIN_RING_DESC,
2349                 .nb_align = I40E_ALIGN_RING_DESC,
2350         };
2351
2352         if (pf->flags & I40E_FLAG_VMDQ) {
2353                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2354                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2355                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2356                                                 pf->max_nb_vmdq_vsi;
2357                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2358                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2359                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2360         }
2361 }
2362
2363 static int
2364 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2365 {
2366         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2367         struct i40e_vsi *vsi = pf->main_vsi;
2368         PMD_INIT_FUNC_TRACE();
2369
2370         if (on)
2371                 return i40e_vsi_add_vlan(vsi, vlan_id);
2372         else
2373                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2374 }
2375
2376 static int
2377 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2378                    enum rte_vlan_type vlan_type,
2379                    uint16_t tpid)
2380 {
2381         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         uint64_t reg_r = 0, reg_w = 0;
2383         uint16_t reg_id = 0;
2384         int ret = 0;
2385
2386         switch (vlan_type) {
2387         case ETH_VLAN_TYPE_OUTER:
2388                 reg_id = 2;
2389                 break;
2390         case ETH_VLAN_TYPE_INNER:
2391                 reg_id = 3;
2392                 break;
2393         default:
2394                 ret = -EINVAL;
2395                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2396                 return ret;
2397         }
2398         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2399                                           &reg_r, NULL);
2400         if (ret != I40E_SUCCESS) {
2401                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2402                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2403                 ret = -EIO;
2404                 return ret;
2405         }
2406         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2407                     "0x%08"PRIx64"", reg_id, reg_r);
2408
2409         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2410         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2411         if (reg_r == reg_w) {
2412                 ret = 0;
2413                 PMD_DRV_LOG(DEBUG, "No need to write");
2414                 return ret;
2415         }
2416
2417         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2418                                            reg_w, NULL);
2419         if (ret != I40E_SUCCESS) {
2420                 ret = -EIO;
2421                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2422                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2423                 return ret;
2424         }
2425         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2426                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2427
2428         return ret;
2429 }
2430
2431 static void
2432 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2433 {
2434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2435         struct i40e_vsi *vsi = pf->main_vsi;
2436
2437         if (mask & ETH_VLAN_FILTER_MASK) {
2438                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2439                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2440                 else
2441                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2442         }
2443
2444         if (mask & ETH_VLAN_STRIP_MASK) {
2445                 /* Enable or disable VLAN stripping */
2446                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2447                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2448                 else
2449                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2450         }
2451
2452         if (mask & ETH_VLAN_EXTEND_MASK) {
2453                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2454                         i40e_vsi_config_double_vlan(vsi, TRUE);
2455                 else
2456                         i40e_vsi_config_double_vlan(vsi, FALSE);
2457         }
2458 }
2459
2460 static void
2461 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2462                           __rte_unused uint16_t queue,
2463                           __rte_unused int on)
2464 {
2465         PMD_INIT_FUNC_TRACE();
2466 }
2467
2468 static int
2469 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2470 {
2471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472         struct i40e_vsi *vsi = pf->main_vsi;
2473         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2474         struct i40e_vsi_vlan_pvid_info info;
2475
2476         memset(&info, 0, sizeof(info));
2477         info.on = on;
2478         if (info.on)
2479                 info.config.pvid = pvid;
2480         else {
2481                 info.config.reject.tagged =
2482                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2483                 info.config.reject.untagged =
2484                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2485         }
2486
2487         return i40e_vsi_vlan_pvid_set(vsi, &info);
2488 }
2489
2490 static int
2491 i40e_dev_led_on(struct rte_eth_dev *dev)
2492 {
2493         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494         uint32_t mode = i40e_led_get(hw);
2495
2496         if (mode == 0)
2497                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2498
2499         return 0;
2500 }
2501
2502 static int
2503 i40e_dev_led_off(struct rte_eth_dev *dev)
2504 {
2505         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506         uint32_t mode = i40e_led_get(hw);
2507
2508         if (mode != 0)
2509                 i40e_led_set(hw, 0, false);
2510
2511         return 0;
2512 }
2513
2514 static int
2515 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2516 {
2517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2519
2520         fc_conf->pause_time = pf->fc_conf.pause_time;
2521         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2522         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2523
2524          /* Return current mode according to actual setting*/
2525         switch (hw->fc.current_mode) {
2526         case I40E_FC_FULL:
2527                 fc_conf->mode = RTE_FC_FULL;
2528                 break;
2529         case I40E_FC_TX_PAUSE:
2530                 fc_conf->mode = RTE_FC_TX_PAUSE;
2531                 break;
2532         case I40E_FC_RX_PAUSE:
2533                 fc_conf->mode = RTE_FC_RX_PAUSE;
2534                 break;
2535         case I40E_FC_NONE:
2536         default:
2537                 fc_conf->mode = RTE_FC_NONE;
2538         };
2539
2540         return 0;
2541 }
2542
2543 static int
2544 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2545 {
2546         uint32_t mflcn_reg, fctrl_reg, reg;
2547         uint32_t max_high_water;
2548         uint8_t i, aq_failure;
2549         int err;
2550         struct i40e_hw *hw;
2551         struct i40e_pf *pf;
2552         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2553                 [RTE_FC_NONE] = I40E_FC_NONE,
2554                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2555                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2556                 [RTE_FC_FULL] = I40E_FC_FULL
2557         };
2558
2559         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2560
2561         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2562         if ((fc_conf->high_water > max_high_water) ||
2563                         (fc_conf->high_water < fc_conf->low_water)) {
2564                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2565                         "High_water must <= %d.", max_high_water);
2566                 return -EINVAL;
2567         }
2568
2569         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2572
2573         pf->fc_conf.pause_time = fc_conf->pause_time;
2574         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2575         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2576
2577         PMD_INIT_FUNC_TRACE();
2578
2579         /* All the link flow control related enable/disable register
2580          * configuration is handle by the F/W
2581          */
2582         err = i40e_set_fc(hw, &aq_failure, true);
2583         if (err < 0)
2584                 return -ENOSYS;
2585
2586         if (i40e_is_40G_device(hw->device_id)) {
2587                 /* Configure flow control refresh threshold,
2588                  * the value for stat_tx_pause_refresh_timer[8]
2589                  * is used for global pause operation.
2590                  */
2591
2592                 I40E_WRITE_REG(hw,
2593                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2594                                pf->fc_conf.pause_time);
2595
2596                 /* configure the timer value included in transmitted pause
2597                  * frame,
2598                  * the value for stat_tx_pause_quanta[8] is used for global
2599                  * pause operation
2600                  */
2601                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2602                                pf->fc_conf.pause_time);
2603
2604                 fctrl_reg = I40E_READ_REG(hw,
2605                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2606
2607                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2608                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2609                 else
2610                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2611
2612                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2613                                fctrl_reg);
2614         } else {
2615                 /* Configure pause time (2 TCs per register) */
2616                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2617                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2618                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2619
2620                 /* Configure flow control refresh threshold value */
2621                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2622                                pf->fc_conf.pause_time / 2);
2623
2624                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2625
2626                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2627                  *depending on configuration
2628                  */
2629                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2630                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2631                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2632                 } else {
2633                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2634                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2635                 }
2636
2637                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2638         }
2639
2640         /* config the water marker both based on the packets and bytes */
2641         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2642                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2643                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2644         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2645                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2646                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2647         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2648                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2649                        << I40E_KILOSHIFT);
2650         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2651                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2652                        << I40E_KILOSHIFT);
2653
2654         I40E_WRITE_FLUSH(hw);
2655
2656         return 0;
2657 }
2658
2659 static int
2660 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2661                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2662 {
2663         PMD_INIT_FUNC_TRACE();
2664
2665         return -ENOSYS;
2666 }
2667
2668 /* Add a MAC address, and update filters */
2669 static void
2670 i40e_macaddr_add(struct rte_eth_dev *dev,
2671                  struct ether_addr *mac_addr,
2672                  __rte_unused uint32_t index,
2673                  uint32_t pool)
2674 {
2675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2676         struct i40e_mac_filter_info mac_filter;
2677         struct i40e_vsi *vsi;
2678         int ret;
2679
2680         /* If VMDQ not enabled or configured, return */
2681         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2682                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2683                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2684                         pool);
2685                 return;
2686         }
2687
2688         if (pool > pf->nb_cfg_vmdq_vsi) {
2689                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2690                                 pool, pf->nb_cfg_vmdq_vsi);
2691                 return;
2692         }
2693
2694         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2695         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2696                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2697         else
2698                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2699
2700         if (pool == 0)
2701                 vsi = pf->main_vsi;
2702         else
2703                 vsi = pf->vmdq[pool - 1].vsi;
2704
2705         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2706         if (ret != I40E_SUCCESS) {
2707                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2708                 return;
2709         }
2710 }
2711
2712 /* Remove a MAC address, and update filters */
2713 static void
2714 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2715 {
2716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2717         struct i40e_vsi *vsi;
2718         struct rte_eth_dev_data *data = dev->data;
2719         struct ether_addr *macaddr;
2720         int ret;
2721         uint32_t i;
2722         uint64_t pool_sel;
2723
2724         macaddr = &(data->mac_addrs[index]);
2725
2726         pool_sel = dev->data->mac_pool_sel[index];
2727
2728         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2729                 if (pool_sel & (1ULL << i)) {
2730                         if (i == 0)
2731                                 vsi = pf->main_vsi;
2732                         else {
2733                                 /* No VMDQ pool enabled or configured */
2734                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2735                                         (i > pf->nb_cfg_vmdq_vsi)) {
2736                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2737                                                         "/configured");
2738                                         return;
2739                                 }
2740                                 vsi = pf->vmdq[i - 1].vsi;
2741                         }
2742                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2743
2744                         if (ret) {
2745                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2746                                 return;
2747                         }
2748                 }
2749         }
2750 }
2751
2752 /* Set perfect match or hash match of MAC and VLAN for a VF */
2753 static int
2754 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2755                  struct rte_eth_mac_filter *filter,
2756                  bool add)
2757 {
2758         struct i40e_hw *hw;
2759         struct i40e_mac_filter_info mac_filter;
2760         struct ether_addr old_mac;
2761         struct ether_addr *new_mac;
2762         struct i40e_pf_vf *vf = NULL;
2763         uint16_t vf_id;
2764         int ret;
2765
2766         if (pf == NULL) {
2767                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2768                 return -EINVAL;
2769         }
2770         hw = I40E_PF_TO_HW(pf);
2771
2772         if (filter == NULL) {
2773                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2774                 return -EINVAL;
2775         }
2776
2777         new_mac = &filter->mac_addr;
2778
2779         if (is_zero_ether_addr(new_mac)) {
2780                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2781                 return -EINVAL;
2782         }
2783
2784         vf_id = filter->dst_id;
2785
2786         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2787                 PMD_DRV_LOG(ERR, "Invalid argument.");
2788                 return -EINVAL;
2789         }
2790         vf = &pf->vfs[vf_id];
2791
2792         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2793                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2794                 return -EINVAL;
2795         }
2796
2797         if (add) {
2798                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2799                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2800                                 ETHER_ADDR_LEN);
2801                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2802                                  ETHER_ADDR_LEN);
2803
2804                 mac_filter.filter_type = filter->filter_type;
2805                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2806                 if (ret != I40E_SUCCESS) {
2807                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2808                         return -1;
2809                 }
2810                 ether_addr_copy(new_mac, &pf->dev_addr);
2811         } else {
2812                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2813                                 ETHER_ADDR_LEN);
2814                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2815                 if (ret != I40E_SUCCESS) {
2816                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2817                         return -1;
2818                 }
2819
2820                 /* Clear device address as it has been removed */
2821                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2822                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2823         }
2824
2825         return 0;
2826 }
2827
2828 /* MAC filter handle */
2829 static int
2830 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2831                 void *arg)
2832 {
2833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2834         struct rte_eth_mac_filter *filter;
2835         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2836         int ret = I40E_NOT_SUPPORTED;
2837
2838         filter = (struct rte_eth_mac_filter *)(arg);
2839
2840         switch (filter_op) {
2841         case RTE_ETH_FILTER_NOP:
2842                 ret = I40E_SUCCESS;
2843                 break;
2844         case RTE_ETH_FILTER_ADD:
2845                 i40e_pf_disable_irq0(hw);
2846                 if (filter->is_vf)
2847                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2848                 i40e_pf_enable_irq0(hw);
2849                 break;
2850         case RTE_ETH_FILTER_DELETE:
2851                 i40e_pf_disable_irq0(hw);
2852                 if (filter->is_vf)
2853                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2854                 i40e_pf_enable_irq0(hw);
2855                 break;
2856         default:
2857                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2858                 ret = I40E_ERR_PARAM;
2859                 break;
2860         }
2861
2862         return ret;
2863 }
2864
2865 static int
2866 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2867 {
2868         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2869         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2870         int ret;
2871
2872         if (!lut)
2873                 return -EINVAL;
2874
2875         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2876                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2877                                           lut, lut_size);
2878                 if (ret) {
2879                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2880                         return ret;
2881                 }
2882         } else {
2883                 uint32_t *lut_dw = (uint32_t *)lut;
2884                 uint16_t i, lut_size_dw = lut_size / 4;
2885
2886                 for (i = 0; i < lut_size_dw; i++)
2887                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2888         }
2889
2890         return 0;
2891 }
2892
2893 static int
2894 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2895 {
2896         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2897         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2898         int ret;
2899
2900         if (!vsi || !lut)
2901                 return -EINVAL;
2902
2903         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2904                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2905                                           lut, lut_size);
2906                 if (ret) {
2907                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2908                         return ret;
2909                 }
2910         } else {
2911                 uint32_t *lut_dw = (uint32_t *)lut;
2912                 uint16_t i, lut_size_dw = lut_size / 4;
2913
2914                 for (i = 0; i < lut_size_dw; i++)
2915                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2916                 I40E_WRITE_FLUSH(hw);
2917         }
2918
2919         return 0;
2920 }
2921
2922 static int
2923 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2924                          struct rte_eth_rss_reta_entry64 *reta_conf,
2925                          uint16_t reta_size)
2926 {
2927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928         uint16_t i, lut_size = pf->hash_lut_size;
2929         uint16_t idx, shift;
2930         uint8_t *lut;
2931         int ret;
2932
2933         if (reta_size != lut_size ||
2934                 reta_size > ETH_RSS_RETA_SIZE_512) {
2935                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2936                         "(%d) doesn't match the number hardware can supported "
2937                                         "(%d)\n", reta_size, lut_size);
2938                 return -EINVAL;
2939         }
2940
2941         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2942         if (!lut) {
2943                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2944                 return -ENOMEM;
2945         }
2946         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2947         if (ret)
2948                 goto out;
2949         for (i = 0; i < reta_size; i++) {
2950                 idx = i / RTE_RETA_GROUP_SIZE;
2951                 shift = i % RTE_RETA_GROUP_SIZE;
2952                 if (reta_conf[idx].mask & (1ULL << shift))
2953                         lut[i] = reta_conf[idx].reta[shift];
2954         }
2955         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2956
2957 out:
2958         rte_free(lut);
2959
2960         return ret;
2961 }
2962
2963 static int
2964 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2965                         struct rte_eth_rss_reta_entry64 *reta_conf,
2966                         uint16_t reta_size)
2967 {
2968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2969         uint16_t i, lut_size = pf->hash_lut_size;
2970         uint16_t idx, shift;
2971         uint8_t *lut;
2972         int ret;
2973
2974         if (reta_size != lut_size ||
2975                 reta_size > ETH_RSS_RETA_SIZE_512) {
2976                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2977                         "(%d) doesn't match the number hardware can supported "
2978                                         "(%d)\n", reta_size, lut_size);
2979                 return -EINVAL;
2980         }
2981
2982         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2983         if (!lut) {
2984                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2985                 return -ENOMEM;
2986         }
2987
2988         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2989         if (ret)
2990                 goto out;
2991         for (i = 0; i < reta_size; i++) {
2992                 idx = i / RTE_RETA_GROUP_SIZE;
2993                 shift = i % RTE_RETA_GROUP_SIZE;
2994                 if (reta_conf[idx].mask & (1ULL << shift))
2995                         reta_conf[idx].reta[shift] = lut[i];
2996         }
2997
2998 out:
2999         rte_free(lut);
3000
3001         return ret;
3002 }
3003
3004 /**
3005  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3006  * @hw:   pointer to the HW structure
3007  * @mem:  pointer to mem struct to fill out
3008  * @size: size of memory requested
3009  * @alignment: what to align the allocation to
3010  **/
3011 enum i40e_status_code
3012 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3013                         struct i40e_dma_mem *mem,
3014                         u64 size,
3015                         u32 alignment)
3016 {
3017         const struct rte_memzone *mz = NULL;
3018         char z_name[RTE_MEMZONE_NAMESIZE];
3019
3020         if (!mem)
3021                 return I40E_ERR_PARAM;
3022
3023         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3024         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3025                                          alignment, RTE_PGSIZE_2M);
3026         if (!mz)
3027                 return I40E_ERR_NO_MEMORY;
3028
3029         mem->size = size;
3030         mem->va = mz->addr;
3031         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3032         mem->zone = (const void *)mz;
3033         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3034                     "%"PRIu64, mz->name, mem->pa);
3035
3036         return I40E_SUCCESS;
3037 }
3038
3039 /**
3040  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3041  * @hw:   pointer to the HW structure
3042  * @mem:  ptr to mem struct to free
3043  **/
3044 enum i40e_status_code
3045 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3046                     struct i40e_dma_mem *mem)
3047 {
3048         if (!mem)
3049                 return I40E_ERR_PARAM;
3050
3051         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3052                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3053                     mem->pa);
3054         rte_memzone_free((const struct rte_memzone *)mem->zone);
3055         mem->zone = NULL;
3056         mem->va = NULL;
3057         mem->pa = (u64)0;
3058
3059         return I40E_SUCCESS;
3060 }
3061
3062 /**
3063  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3064  * @hw:   pointer to the HW structure
3065  * @mem:  pointer to mem struct to fill out
3066  * @size: size of memory requested
3067  **/
3068 enum i40e_status_code
3069 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3070                          struct i40e_virt_mem *mem,
3071                          u32 size)
3072 {
3073         if (!mem)
3074                 return I40E_ERR_PARAM;
3075
3076         mem->size = size;
3077         mem->va = rte_zmalloc("i40e", size, 0);
3078
3079         if (mem->va)
3080                 return I40E_SUCCESS;
3081         else
3082                 return I40E_ERR_NO_MEMORY;
3083 }
3084
3085 /**
3086  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3087  * @hw:   pointer to the HW structure
3088  * @mem:  pointer to mem struct to free
3089  **/
3090 enum i40e_status_code
3091 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3092                      struct i40e_virt_mem *mem)
3093 {
3094         if (!mem)
3095                 return I40E_ERR_PARAM;
3096
3097         rte_free(mem->va);
3098         mem->va = NULL;
3099
3100         return I40E_SUCCESS;
3101 }
3102
3103 void
3104 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3105 {
3106         rte_spinlock_init(&sp->spinlock);
3107 }
3108
3109 void
3110 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3111 {
3112         rte_spinlock_lock(&sp->spinlock);
3113 }
3114
3115 void
3116 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3117 {
3118         rte_spinlock_unlock(&sp->spinlock);
3119 }
3120
3121 void
3122 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3123 {
3124         return;
3125 }
3126
3127 /**
3128  * Get the hardware capabilities, which will be parsed
3129  * and saved into struct i40e_hw.
3130  */
3131 static int
3132 i40e_get_cap(struct i40e_hw *hw)
3133 {
3134         struct i40e_aqc_list_capabilities_element_resp *buf;
3135         uint16_t len, size = 0;
3136         int ret;
3137
3138         /* Calculate a huge enough buff for saving response data temporarily */
3139         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3140                                                 I40E_MAX_CAP_ELE_NUM;
3141         buf = rte_zmalloc("i40e", len, 0);
3142         if (!buf) {
3143                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3144                 return I40E_ERR_NO_MEMORY;
3145         }
3146
3147         /* Get, parse the capabilities and save it to hw */
3148         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3149                         i40e_aqc_opc_list_func_capabilities, NULL);
3150         if (ret != I40E_SUCCESS)
3151                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3152
3153         /* Free the temporary buffer after being used */
3154         rte_free(buf);
3155
3156         return ret;
3157 }
3158
3159 static int
3160 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3161 {
3162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3164         uint16_t qp_count = 0, vsi_count = 0;
3165
3166         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3167                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3168                 return -EINVAL;
3169         }
3170         /* Add the parameter init for LFC */
3171         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3172         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3173         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3174
3175         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3176         pf->max_num_vsi = hw->func_caps.num_vsis;
3177         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3178         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3179         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3180
3181         /* FDir queue/VSI allocation */
3182         pf->fdir_qp_offset = 0;
3183         if (hw->func_caps.fd) {
3184                 pf->flags |= I40E_FLAG_FDIR;
3185                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3186         } else {
3187                 pf->fdir_nb_qps = 0;
3188         }
3189         qp_count += pf->fdir_nb_qps;
3190         vsi_count += 1;
3191
3192         /* LAN queue/VSI allocation */
3193         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3194         if (!hw->func_caps.rss) {
3195                 pf->lan_nb_qps = 1;
3196         } else {
3197                 pf->flags |= I40E_FLAG_RSS;
3198                 if (hw->mac.type == I40E_MAC_X722)
3199                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3200                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3201         }
3202         qp_count += pf->lan_nb_qps;
3203         vsi_count += 1;
3204
3205         /* VF queue/VSI allocation */
3206         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3207         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3208                 pf->flags |= I40E_FLAG_SRIOV;
3209                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3210                 pf->vf_num = dev->pci_dev->max_vfs;
3211                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3212                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3213                             pf->vf_nb_qps * pf->vf_num);
3214         } else {
3215                 pf->vf_nb_qps = 0;
3216                 pf->vf_num = 0;
3217         }
3218         qp_count += pf->vf_nb_qps * pf->vf_num;
3219         vsi_count += pf->vf_num;
3220
3221         /* VMDq queue/VSI allocation */
3222         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3223         pf->vmdq_nb_qps = 0;
3224         pf->max_nb_vmdq_vsi = 0;
3225         if (hw->func_caps.vmdq) {
3226                 if (qp_count < hw->func_caps.num_tx_qp &&
3227                         vsi_count < hw->func_caps.num_vsis) {
3228                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3229                                 qp_count) / pf->vmdq_nb_qp_max;
3230
3231                         /* Limit the maximum number of VMDq vsi to the maximum
3232                          * ethdev can support
3233                          */
3234                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3235                                 hw->func_caps.num_vsis - vsi_count);
3236                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3237                                 ETH_64_POOLS);
3238                         if (pf->max_nb_vmdq_vsi) {
3239                                 pf->flags |= I40E_FLAG_VMDQ;
3240                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3241                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3242                                             "per VMDQ VSI, in total %u queues",
3243                                             pf->max_nb_vmdq_vsi,
3244                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3245                                             pf->max_nb_vmdq_vsi);
3246                         } else {
3247                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3248                                             "VMDq");
3249                         }
3250                 } else {
3251                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3252                 }
3253         }
3254         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3255         vsi_count += pf->max_nb_vmdq_vsi;
3256
3257         if (hw->func_caps.dcb)
3258                 pf->flags |= I40E_FLAG_DCB;
3259
3260         if (qp_count > hw->func_caps.num_tx_qp) {
3261                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3262                             "the hardware maximum %u", qp_count,
3263                             hw->func_caps.num_tx_qp);
3264                 return -EINVAL;
3265         }
3266         if (vsi_count > hw->func_caps.num_vsis) {
3267                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3268                             "the hardware maximum %u", vsi_count,
3269                             hw->func_caps.num_vsis);
3270                 return -EINVAL;
3271         }
3272
3273         return 0;
3274 }
3275
3276 static int
3277 i40e_pf_get_switch_config(struct i40e_pf *pf)
3278 {
3279         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3280         struct i40e_aqc_get_switch_config_resp *switch_config;
3281         struct i40e_aqc_switch_config_element_resp *element;
3282         uint16_t start_seid = 0, num_reported;
3283         int ret;
3284
3285         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3286                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3287         if (!switch_config) {
3288                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3289                 return -ENOMEM;
3290         }
3291
3292         /* Get the switch configurations */
3293         ret = i40e_aq_get_switch_config(hw, switch_config,
3294                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3295         if (ret != I40E_SUCCESS) {
3296                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3297                 goto fail;
3298         }
3299         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3300         if (num_reported != 1) { /* The number should be 1 */
3301                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3302                 goto fail;
3303         }
3304
3305         /* Parse the switch configuration elements */
3306         element = &(switch_config->element[0]);
3307         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3308                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3309                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3310         } else
3311                 PMD_DRV_LOG(INFO, "Unknown element type");
3312
3313 fail:
3314         rte_free(switch_config);
3315
3316         return ret;
3317 }
3318
3319 static int
3320 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3321                         uint32_t num)
3322 {
3323         struct pool_entry *entry;
3324
3325         if (pool == NULL || num == 0)
3326                 return -EINVAL;
3327
3328         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3329         if (entry == NULL) {
3330                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3331                 return -ENOMEM;
3332         }
3333
3334         /* queue heap initialize */
3335         pool->num_free = num;
3336         pool->num_alloc = 0;
3337         pool->base = base;
3338         LIST_INIT(&pool->alloc_list);
3339         LIST_INIT(&pool->free_list);
3340
3341         /* Initialize element  */
3342         entry->base = 0;
3343         entry->len = num;
3344
3345         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3346         return 0;
3347 }
3348
3349 static void
3350 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3351 {
3352         struct pool_entry *entry;
3353
3354         if (pool == NULL)
3355                 return;
3356
3357         LIST_FOREACH(entry, &pool->alloc_list, next) {
3358                 LIST_REMOVE(entry, next);
3359                 rte_free(entry);
3360         }
3361
3362         LIST_FOREACH(entry, &pool->free_list, next) {
3363                 LIST_REMOVE(entry, next);
3364                 rte_free(entry);
3365         }
3366
3367         pool->num_free = 0;
3368         pool->num_alloc = 0;
3369         pool->base = 0;
3370         LIST_INIT(&pool->alloc_list);
3371         LIST_INIT(&pool->free_list);
3372 }
3373
3374 static int
3375 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3376                        uint32_t base)
3377 {
3378         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3379         uint32_t pool_offset;
3380         int insert;
3381
3382         if (pool == NULL) {
3383                 PMD_DRV_LOG(ERR, "Invalid parameter");
3384                 return -EINVAL;
3385         }
3386
3387         pool_offset = base - pool->base;
3388         /* Lookup in alloc list */
3389         LIST_FOREACH(entry, &pool->alloc_list, next) {
3390                 if (entry->base == pool_offset) {
3391                         valid_entry = entry;
3392                         LIST_REMOVE(entry, next);
3393                         break;
3394                 }
3395         }
3396
3397         /* Not find, return */
3398         if (valid_entry == NULL) {
3399                 PMD_DRV_LOG(ERR, "Failed to find entry");
3400                 return -EINVAL;
3401         }
3402
3403         /**
3404          * Found it, move it to free list  and try to merge.
3405          * In order to make merge easier, always sort it by qbase.
3406          * Find adjacent prev and last entries.
3407          */
3408         prev = next = NULL;
3409         LIST_FOREACH(entry, &pool->free_list, next) {
3410                 if (entry->base > valid_entry->base) {
3411                         next = entry;
3412                         break;
3413                 }
3414                 prev = entry;
3415         }
3416
3417         insert = 0;
3418         /* Try to merge with next one*/
3419         if (next != NULL) {
3420                 /* Merge with next one */
3421                 if (valid_entry->base + valid_entry->len == next->base) {
3422                         next->base = valid_entry->base;
3423                         next->len += valid_entry->len;
3424                         rte_free(valid_entry);
3425                         valid_entry = next;
3426                         insert = 1;
3427                 }
3428         }
3429
3430         if (prev != NULL) {
3431                 /* Merge with previous one */
3432                 if (prev->base + prev->len == valid_entry->base) {
3433                         prev->len += valid_entry->len;
3434                         /* If it merge with next one, remove next node */
3435                         if (insert == 1) {
3436                                 LIST_REMOVE(valid_entry, next);
3437                                 rte_free(valid_entry);
3438                         } else {
3439                                 rte_free(valid_entry);
3440                                 insert = 1;
3441                         }
3442                 }
3443         }
3444
3445         /* Not find any entry to merge, insert */
3446         if (insert == 0) {
3447                 if (prev != NULL)
3448                         LIST_INSERT_AFTER(prev, valid_entry, next);
3449                 else if (next != NULL)
3450                         LIST_INSERT_BEFORE(next, valid_entry, next);
3451                 else /* It's empty list, insert to head */
3452                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3453         }
3454
3455         pool->num_free += valid_entry->len;
3456         pool->num_alloc -= valid_entry->len;
3457
3458         return 0;
3459 }
3460
3461 static int
3462 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3463                        uint16_t num)
3464 {
3465         struct pool_entry *entry, *valid_entry;
3466
3467         if (pool == NULL || num == 0) {
3468                 PMD_DRV_LOG(ERR, "Invalid parameter");
3469                 return -EINVAL;
3470         }
3471
3472         if (pool->num_free < num) {
3473                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3474                             num, pool->num_free);
3475                 return -ENOMEM;
3476         }
3477
3478         valid_entry = NULL;
3479         /* Lookup  in free list and find most fit one */
3480         LIST_FOREACH(entry, &pool->free_list, next) {
3481                 if (entry->len >= num) {
3482                         /* Find best one */
3483                         if (entry->len == num) {
3484                                 valid_entry = entry;
3485                                 break;
3486                         }
3487                         if (valid_entry == NULL || valid_entry->len > entry->len)
3488                                 valid_entry = entry;
3489                 }
3490         }
3491
3492         /* Not find one to satisfy the request, return */
3493         if (valid_entry == NULL) {
3494                 PMD_DRV_LOG(ERR, "No valid entry found");
3495                 return -ENOMEM;
3496         }
3497         /**
3498          * The entry have equal queue number as requested,
3499          * remove it from alloc_list.
3500          */
3501         if (valid_entry->len == num) {
3502                 LIST_REMOVE(valid_entry, next);
3503         } else {
3504                 /**
3505                  * The entry have more numbers than requested,
3506                  * create a new entry for alloc_list and minus its
3507                  * queue base and number in free_list.
3508                  */
3509                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3510                 if (entry == NULL) {
3511                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3512                                     "resource pool");
3513                         return -ENOMEM;
3514                 }
3515                 entry->base = valid_entry->base;
3516                 entry->len = num;
3517                 valid_entry->base += num;
3518                 valid_entry->len -= num;
3519                 valid_entry = entry;
3520         }
3521
3522         /* Insert it into alloc list, not sorted */
3523         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3524
3525         pool->num_free -= valid_entry->len;
3526         pool->num_alloc += valid_entry->len;
3527
3528         return valid_entry->base + pool->base;
3529 }
3530
3531 /**
3532  * bitmap_is_subset - Check whether src2 is subset of src1
3533  **/
3534 static inline int
3535 bitmap_is_subset(uint8_t src1, uint8_t src2)
3536 {
3537         return !((src1 ^ src2) & src2);
3538 }
3539
3540 static enum i40e_status_code
3541 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3542 {
3543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3544
3545         /* If DCB is not supported, only default TC is supported */
3546         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3547                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3548                 return I40E_NOT_SUPPORTED;
3549         }
3550
3551         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3552                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3553                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3554                             enabled_tcmap);
3555                 return I40E_NOT_SUPPORTED;
3556         }
3557         return I40E_SUCCESS;
3558 }
3559
3560 int
3561 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3562                                 struct i40e_vsi_vlan_pvid_info *info)
3563 {
3564         struct i40e_hw *hw;
3565         struct i40e_vsi_context ctxt;
3566         uint8_t vlan_flags = 0;
3567         int ret;
3568
3569         if (vsi == NULL || info == NULL) {
3570                 PMD_DRV_LOG(ERR, "invalid parameters");
3571                 return I40E_ERR_PARAM;
3572         }
3573
3574         if (info->on) {
3575                 vsi->info.pvid = info->config.pvid;
3576                 /**
3577                  * If insert pvid is enabled, only tagged pkts are
3578                  * allowed to be sent out.
3579                  */
3580                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3581                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3582         } else {
3583                 vsi->info.pvid = 0;
3584                 if (info->config.reject.tagged == 0)
3585                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3586
3587                 if (info->config.reject.untagged == 0)
3588                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3589         }
3590         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3591                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3592         vsi->info.port_vlan_flags |= vlan_flags;
3593         vsi->info.valid_sections =
3594                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3595         memset(&ctxt, 0, sizeof(ctxt));
3596         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3597         ctxt.seid = vsi->seid;
3598
3599         hw = I40E_VSI_TO_HW(vsi);
3600         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3601         if (ret != I40E_SUCCESS)
3602                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3603
3604         return ret;
3605 }
3606
3607 static int
3608 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3609 {
3610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3611         int i, ret;
3612         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3613
3614         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3615         if (ret != I40E_SUCCESS)
3616                 return ret;
3617
3618         if (!vsi->seid) {
3619                 PMD_DRV_LOG(ERR, "seid not valid");
3620                 return -EINVAL;
3621         }
3622
3623         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3624         tc_bw_data.tc_valid_bits = enabled_tcmap;
3625         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3626                 tc_bw_data.tc_bw_credits[i] =
3627                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3628
3629         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3630         if (ret != I40E_SUCCESS) {
3631                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3632                 return ret;
3633         }
3634
3635         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3636                                         sizeof(vsi->info.qs_handle));
3637         return I40E_SUCCESS;
3638 }
3639
3640 static enum i40e_status_code
3641 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3642                                  struct i40e_aqc_vsi_properties_data *info,
3643                                  uint8_t enabled_tcmap)
3644 {
3645         enum i40e_status_code ret;
3646         int i, total_tc = 0;
3647         uint16_t qpnum_per_tc, bsf, qp_idx;
3648
3649         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3650         if (ret != I40E_SUCCESS)
3651                 return ret;
3652
3653         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3654                 if (enabled_tcmap & (1 << i))
3655                         total_tc++;
3656         vsi->enabled_tc = enabled_tcmap;
3657
3658         /* Number of queues per enabled TC */
3659         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3660         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3661         bsf = rte_bsf32(qpnum_per_tc);
3662
3663         /* Adjust the queue number to actual queues that can be applied */
3664         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3665                 vsi->nb_qps = qpnum_per_tc * total_tc;
3666
3667         /**
3668          * Configure TC and queue mapping parameters, for enabled TC,
3669          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3670          * default queue will serve it.
3671          */
3672         qp_idx = 0;
3673         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3674                 if (vsi->enabled_tc & (1 << i)) {
3675                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3676                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3677                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3678                         qp_idx += qpnum_per_tc;
3679                 } else
3680                         info->tc_mapping[i] = 0;
3681         }
3682
3683         /* Associate queue number with VSI */
3684         if (vsi->type == I40E_VSI_SRIOV) {
3685                 info->mapping_flags |=
3686                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3687                 for (i = 0; i < vsi->nb_qps; i++)
3688                         info->queue_mapping[i] =
3689                                 rte_cpu_to_le_16(vsi->base_queue + i);
3690         } else {
3691                 info->mapping_flags |=
3692                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3693                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3694         }
3695         info->valid_sections |=
3696                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3697
3698         return I40E_SUCCESS;
3699 }
3700
3701 static int
3702 i40e_veb_release(struct i40e_veb *veb)
3703 {
3704         struct i40e_vsi *vsi;
3705         struct i40e_hw *hw;
3706
3707         if (veb == NULL || veb->associate_vsi == NULL)
3708                 return -EINVAL;
3709
3710         if (!TAILQ_EMPTY(&veb->head)) {
3711                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3712                 return -EACCES;
3713         }
3714
3715         vsi = veb->associate_vsi;
3716         hw = I40E_VSI_TO_HW(vsi);
3717
3718         vsi->uplink_seid = veb->uplink_seid;
3719         i40e_aq_delete_element(hw, veb->seid, NULL);
3720         rte_free(veb);
3721         vsi->veb = NULL;
3722         return I40E_SUCCESS;
3723 }
3724
3725 /* Setup a veb */
3726 static struct i40e_veb *
3727 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3728 {
3729         struct i40e_veb *veb;
3730         int ret;
3731         struct i40e_hw *hw;
3732
3733         if (NULL == pf || vsi == NULL) {
3734                 PMD_DRV_LOG(ERR, "veb setup failed, "
3735                             "associated VSI shouldn't null");
3736                 return NULL;
3737         }
3738         hw = I40E_PF_TO_HW(pf);
3739
3740         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3741         if (!veb) {
3742                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3743                 goto fail;
3744         }
3745
3746         veb->associate_vsi = vsi;
3747         TAILQ_INIT(&veb->head);
3748         veb->uplink_seid = vsi->uplink_seid;
3749
3750         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3751                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3752
3753         if (ret != I40E_SUCCESS) {
3754                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3755                             hw->aq.asq_last_status);
3756                 goto fail;
3757         }
3758
3759         /* get statistics index */
3760         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3761                                 &veb->stats_idx, NULL, NULL, NULL);
3762         if (ret != I40E_SUCCESS) {
3763                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3764                             hw->aq.asq_last_status);
3765                 goto fail;
3766         }
3767
3768         /* Get VEB bandwidth, to be implemented */
3769         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3770         vsi->uplink_seid = veb->seid;
3771
3772         return veb;
3773 fail:
3774         rte_free(veb);
3775         return NULL;
3776 }
3777
3778 int
3779 i40e_vsi_release(struct i40e_vsi *vsi)
3780 {
3781         struct i40e_pf *pf;
3782         struct i40e_hw *hw;
3783         struct i40e_vsi_list *vsi_list;
3784         int ret;
3785         struct i40e_mac_filter *f;
3786
3787         if (!vsi)
3788                 return I40E_SUCCESS;
3789
3790         pf = I40E_VSI_TO_PF(vsi);
3791         hw = I40E_VSI_TO_HW(vsi);
3792
3793         /* VSI has child to attach, release child first */
3794         if (vsi->veb) {
3795                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3796                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3797                                 return -1;
3798                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3799                 }
3800                 i40e_veb_release(vsi->veb);
3801         }
3802
3803         /* Remove all macvlan filters of the VSI */
3804         i40e_vsi_remove_all_macvlan_filter(vsi);
3805         TAILQ_FOREACH(f, &vsi->mac_list, next)
3806                 rte_free(f);
3807
3808         if (vsi->type != I40E_VSI_MAIN) {
3809                 /* Remove vsi from parent's sibling list */
3810                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3811                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3812                         return I40E_ERR_PARAM;
3813                 }
3814                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3815                                 &vsi->sib_vsi_list, list);
3816
3817                 /* Remove all switch element of the VSI */
3818                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3819                 if (ret != I40E_SUCCESS)
3820                         PMD_DRV_LOG(ERR, "Failed to delete element");
3821         }
3822         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3823
3824         if (vsi->type != I40E_VSI_SRIOV)
3825                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3826         rte_free(vsi);
3827
3828         return I40E_SUCCESS;
3829 }
3830
3831 static int
3832 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3833 {
3834         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3835         struct i40e_aqc_remove_macvlan_element_data def_filter;
3836         struct i40e_mac_filter_info filter;
3837         int ret;
3838
3839         if (vsi->type != I40E_VSI_MAIN)
3840                 return I40E_ERR_CONFIG;
3841         memset(&def_filter, 0, sizeof(def_filter));
3842         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3843                                         ETH_ADDR_LEN);
3844         def_filter.vlan_tag = 0;
3845         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3846                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3847         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3848         if (ret != I40E_SUCCESS) {
3849                 struct i40e_mac_filter *f;
3850                 struct ether_addr *mac;
3851
3852                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3853                             "macvlan filter");
3854                 /* It needs to add the permanent mac into mac list */
3855                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3856                 if (f == NULL) {
3857                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3858                         return I40E_ERR_NO_MEMORY;
3859                 }
3860                 mac = &f->mac_info.mac_addr;
3861                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3862                                 ETH_ADDR_LEN);
3863                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3864                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3865                 vsi->mac_num++;
3866
3867                 return ret;
3868         }
3869         (void)rte_memcpy(&filter.mac_addr,
3870                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3871         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3872         return i40e_vsi_add_mac(vsi, &filter);
3873 }
3874
3875 /*
3876  * i40e_vsi_get_bw_config - Query VSI BW Information
3877  * @vsi: the VSI to be queried
3878  *
3879  * Returns 0 on success, negative value on failure
3880  */
3881 static enum i40e_status_code
3882 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3883 {
3884         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3885         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3886         struct i40e_hw *hw = &vsi->adapter->hw;
3887         i40e_status ret;
3888         int i;
3889         uint32_t bw_max;
3890
3891         memset(&bw_config, 0, sizeof(bw_config));
3892         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3893         if (ret != I40E_SUCCESS) {
3894                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3895                             hw->aq.asq_last_status);
3896                 return ret;
3897         }
3898
3899         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3900         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3901                                         &ets_sla_config, NULL);
3902         if (ret != I40E_SUCCESS) {
3903                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3904                             "configuration %u", hw->aq.asq_last_status);
3905                 return ret;
3906         }
3907
3908         /* store and print out BW info */
3909         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3910         vsi->bw_info.bw_max = bw_config.max_bw;
3911         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3912         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3913         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3914                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3915                      I40E_16_BIT_WIDTH);
3916         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3917                 vsi->bw_info.bw_ets_share_credits[i] =
3918                                 ets_sla_config.share_credits[i];
3919                 vsi->bw_info.bw_ets_credits[i] =
3920                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3921                 /* 4 bits per TC, 4th bit is reserved */
3922                 vsi->bw_info.bw_ets_max[i] =
3923                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3924                                   RTE_LEN2MASK(3, uint8_t));
3925                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3926                             vsi->bw_info.bw_ets_share_credits[i]);
3927                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3928                             vsi->bw_info.bw_ets_credits[i]);
3929                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3930                             vsi->bw_info.bw_ets_max[i]);
3931         }
3932
3933         return I40E_SUCCESS;
3934 }
3935
3936 /* i40e_enable_pf_lb
3937  * @pf: pointer to the pf structure
3938  *
3939  * allow loopback on pf
3940  */
3941 static inline void
3942 i40e_enable_pf_lb(struct i40e_pf *pf)
3943 {
3944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3945         struct i40e_vsi_context ctxt;
3946         int ret;
3947
3948         /* Use the FW API if FW >= v5.0 */
3949         if (hw->aq.fw_maj_ver < 5) {
3950                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3951                 return;
3952         }
3953
3954         memset(&ctxt, 0, sizeof(ctxt));
3955         ctxt.seid = pf->main_vsi_seid;
3956         ctxt.pf_num = hw->pf_id;
3957         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3958         if (ret) {
3959                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3960                             ret, hw->aq.asq_last_status);
3961                 return;
3962         }
3963         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3964         ctxt.info.valid_sections =
3965                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3966         ctxt.info.switch_id |=
3967                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3968
3969         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3970         if (ret)
3971                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3972                             hw->aq.asq_last_status);
3973 }
3974
3975 /* Setup a VSI */
3976 struct i40e_vsi *
3977 i40e_vsi_setup(struct i40e_pf *pf,
3978                enum i40e_vsi_type type,
3979                struct i40e_vsi *uplink_vsi,
3980                uint16_t user_param)
3981 {
3982         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3983         struct i40e_vsi *vsi;
3984         struct i40e_mac_filter_info filter;
3985         int ret;
3986         struct i40e_vsi_context ctxt;
3987         struct ether_addr broadcast =
3988                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3989
3990         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3991                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3992                             "VSI link shouldn't be NULL");
3993                 return NULL;
3994         }
3995
3996         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3997                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3998                             "uplink VSI should be NULL");
3999                 return NULL;
4000         }
4001
4002         /* If uplink vsi didn't setup VEB, create one first */
4003         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4004                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4005
4006                 if (NULL == uplink_vsi->veb) {
4007                         PMD_DRV_LOG(ERR, "VEB setup failed");
4008                         return NULL;
4009                 }
4010                 /* set ALLOWLOOPBACk on pf, when veb is created */
4011                 i40e_enable_pf_lb(pf);
4012         }
4013
4014         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4015         if (!vsi) {
4016                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4017                 return NULL;
4018         }
4019         TAILQ_INIT(&vsi->mac_list);
4020         vsi->type = type;
4021         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4022         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4023         vsi->parent_vsi = uplink_vsi;
4024         vsi->user_param = user_param;
4025         /* Allocate queues */
4026         switch (vsi->type) {
4027         case I40E_VSI_MAIN  :
4028                 vsi->nb_qps = pf->lan_nb_qps;
4029                 break;
4030         case I40E_VSI_SRIOV :
4031                 vsi->nb_qps = pf->vf_nb_qps;
4032                 break;
4033         case I40E_VSI_VMDQ2:
4034                 vsi->nb_qps = pf->vmdq_nb_qps;
4035                 break;
4036         case I40E_VSI_FDIR:
4037                 vsi->nb_qps = pf->fdir_nb_qps;
4038                 break;
4039         default:
4040                 goto fail_mem;
4041         }
4042         /*
4043          * The filter status descriptor is reported in rx queue 0,
4044          * while the tx queue for fdir filter programming has no
4045          * such constraints, can be non-zero queues.
4046          * To simplify it, choose FDIR vsi use queue 0 pair.
4047          * To make sure it will use queue 0 pair, queue allocation
4048          * need be done before this function is called
4049          */
4050         if (type != I40E_VSI_FDIR) {
4051                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4052                         if (ret < 0) {
4053                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4054                                                 vsi->seid, ret);
4055                                 goto fail_mem;
4056                         }
4057                         vsi->base_queue = ret;
4058         } else
4059                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4060
4061         /* VF has MSIX interrupt in VF range, don't allocate here */
4062         if (type == I40E_VSI_MAIN) {
4063                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4064                                           RTE_MIN(vsi->nb_qps,
4065                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4066                 if (ret < 0) {
4067                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4068                                     vsi->seid, ret);
4069                         goto fail_queue_alloc;
4070                 }
4071                 vsi->msix_intr = ret;
4072                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4073         } else if (type != I40E_VSI_SRIOV) {
4074                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4075                 if (ret < 0) {
4076                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4077                         goto fail_queue_alloc;
4078                 }
4079                 vsi->msix_intr = ret;
4080                 vsi->nb_msix = 1;
4081         } else {
4082                 vsi->msix_intr = 0;
4083                 vsi->nb_msix = 0;
4084         }
4085
4086         /* Add VSI */
4087         if (type == I40E_VSI_MAIN) {
4088                 /* For main VSI, no need to add since it's default one */
4089                 vsi->uplink_seid = pf->mac_seid;
4090                 vsi->seid = pf->main_vsi_seid;
4091                 /* Bind queues with specific MSIX interrupt */
4092                 /**
4093                  * Needs 2 interrupt at least, one for misc cause which will
4094                  * enabled from OS side, Another for queues binding the
4095                  * interrupt from device side only.
4096                  */
4097
4098                 /* Get default VSI parameters from hardware */
4099                 memset(&ctxt, 0, sizeof(ctxt));
4100                 ctxt.seid = vsi->seid;
4101                 ctxt.pf_num = hw->pf_id;
4102                 ctxt.uplink_seid = vsi->uplink_seid;
4103                 ctxt.vf_num = 0;
4104                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4105                 if (ret != I40E_SUCCESS) {
4106                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4107                         goto fail_msix_alloc;
4108                 }
4109                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4110                         sizeof(struct i40e_aqc_vsi_properties_data));
4111                 vsi->vsi_id = ctxt.vsi_number;
4112                 vsi->info.valid_sections = 0;
4113
4114                 /* Configure tc, enabled TC0 only */
4115                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4116                         I40E_SUCCESS) {
4117                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4118                         goto fail_msix_alloc;
4119                 }
4120
4121                 /* TC, queue mapping */
4122                 memset(&ctxt, 0, sizeof(ctxt));
4123                 vsi->info.valid_sections |=
4124                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4125                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4126                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4127                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4128                         sizeof(struct i40e_aqc_vsi_properties_data));
4129                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4130                                                 I40E_DEFAULT_TCMAP);
4131                 if (ret != I40E_SUCCESS) {
4132                         PMD_DRV_LOG(ERR, "Failed to configure "
4133                                     "TC queue mapping");
4134                         goto fail_msix_alloc;
4135                 }
4136                 ctxt.seid = vsi->seid;
4137                 ctxt.pf_num = hw->pf_id;
4138                 ctxt.uplink_seid = vsi->uplink_seid;
4139                 ctxt.vf_num = 0;
4140
4141                 /* Update VSI parameters */
4142                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4143                 if (ret != I40E_SUCCESS) {
4144                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4145                         goto fail_msix_alloc;
4146                 }
4147
4148                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4149                                                 sizeof(vsi->info.tc_mapping));
4150                 (void)rte_memcpy(&vsi->info.queue_mapping,
4151                                 &ctxt.info.queue_mapping,
4152                         sizeof(vsi->info.queue_mapping));
4153                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4154                 vsi->info.valid_sections = 0;
4155
4156                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4157                                 ETH_ADDR_LEN);
4158
4159                 /**
4160                  * Updating default filter settings are necessary to prevent
4161                  * reception of tagged packets.
4162                  * Some old firmware configurations load a default macvlan
4163                  * filter which accepts both tagged and untagged packets.
4164                  * The updating is to use a normal filter instead if needed.
4165                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4166                  * The firmware with correct configurations load the default
4167                  * macvlan filter which is expected and cannot be removed.
4168                  */
4169                 i40e_update_default_filter_setting(vsi);
4170                 i40e_config_qinq(hw, vsi);
4171         } else if (type == I40E_VSI_SRIOV) {
4172                 memset(&ctxt, 0, sizeof(ctxt));
4173                 /**
4174                  * For other VSI, the uplink_seid equals to uplink VSI's
4175                  * uplink_seid since they share same VEB
4176                  */
4177                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4178                 ctxt.pf_num = hw->pf_id;
4179                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4180                 ctxt.uplink_seid = vsi->uplink_seid;
4181                 ctxt.connection_type = 0x1;
4182                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4183
4184                 /* Use the VEB configuration if FW >= v5.0 */
4185                 if (hw->aq.fw_maj_ver >= 5) {
4186                         /* Configure switch ID */
4187                         ctxt.info.valid_sections |=
4188                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4189                         ctxt.info.switch_id =
4190                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4191                 }
4192
4193                 /* Configure port/vlan */
4194                 ctxt.info.valid_sections |=
4195                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4196                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4197                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4198                                                 I40E_DEFAULT_TCMAP);
4199                 if (ret != I40E_SUCCESS) {
4200                         PMD_DRV_LOG(ERR, "Failed to configure "
4201                                     "TC queue mapping");
4202                         goto fail_msix_alloc;
4203                 }
4204                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4205                 ctxt.info.valid_sections |=
4206                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4207                 /**
4208                  * Since VSI is not created yet, only configure parameter,
4209                  * will add vsi below.
4210                  */
4211
4212                 i40e_config_qinq(hw, vsi);
4213         } else if (type == I40E_VSI_VMDQ2) {
4214                 memset(&ctxt, 0, sizeof(ctxt));
4215                 /*
4216                  * For other VSI, the uplink_seid equals to uplink VSI's
4217                  * uplink_seid since they share same VEB
4218                  */
4219                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4220                 ctxt.pf_num = hw->pf_id;
4221                 ctxt.vf_num = 0;
4222                 ctxt.uplink_seid = vsi->uplink_seid;
4223                 ctxt.connection_type = 0x1;
4224                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4225
4226                 ctxt.info.valid_sections |=
4227                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4228                 /* user_param carries flag to enable loop back */
4229                 if (user_param) {
4230                         ctxt.info.switch_id =
4231                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4232                         ctxt.info.switch_id |=
4233                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4234                 }
4235
4236                 /* Configure port/vlan */
4237                 ctxt.info.valid_sections |=
4238                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4239                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4240                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4241                                                 I40E_DEFAULT_TCMAP);
4242                 if (ret != I40E_SUCCESS) {
4243                         PMD_DRV_LOG(ERR, "Failed to configure "
4244                                         "TC queue mapping");
4245                         goto fail_msix_alloc;
4246                 }
4247                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4248                 ctxt.info.valid_sections |=
4249                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4250         } else if (type == I40E_VSI_FDIR) {
4251                 memset(&ctxt, 0, sizeof(ctxt));
4252                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4253                 ctxt.pf_num = hw->pf_id;
4254                 ctxt.vf_num = 0;
4255                 ctxt.uplink_seid = vsi->uplink_seid;
4256                 ctxt.connection_type = 0x1;     /* regular data port */
4257                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4258                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4259                                                 I40E_DEFAULT_TCMAP);
4260                 if (ret != I40E_SUCCESS) {
4261                         PMD_DRV_LOG(ERR, "Failed to configure "
4262                                         "TC queue mapping.");
4263                         goto fail_msix_alloc;
4264                 }
4265                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4266                 ctxt.info.valid_sections |=
4267                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4268         } else {
4269                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4270                 goto fail_msix_alloc;
4271         }
4272
4273         if (vsi->type != I40E_VSI_MAIN) {
4274                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4275                 if (ret != I40E_SUCCESS) {
4276                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4277                                     hw->aq.asq_last_status);
4278                         goto fail_msix_alloc;
4279                 }
4280                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4281                 vsi->info.valid_sections = 0;
4282                 vsi->seid = ctxt.seid;
4283                 vsi->vsi_id = ctxt.vsi_number;
4284                 vsi->sib_vsi_list.vsi = vsi;
4285                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4286                                 &vsi->sib_vsi_list, list);
4287         }
4288
4289         /* MAC/VLAN configuration */
4290         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4291         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4292
4293         ret = i40e_vsi_add_mac(vsi, &filter);
4294         if (ret != I40E_SUCCESS) {
4295                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4296                 goto fail_msix_alloc;
4297         }
4298
4299         /* Get VSI BW information */
4300         i40e_vsi_get_bw_config(vsi);
4301         return vsi;
4302 fail_msix_alloc:
4303         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4304 fail_queue_alloc:
4305         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4306 fail_mem:
4307         rte_free(vsi);
4308         return NULL;
4309 }
4310
4311 /* Configure vlan filter on or off */
4312 int
4313 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4314 {
4315         int i, num;
4316         struct i40e_mac_filter *f;
4317         struct i40e_mac_filter_info *mac_filter;
4318         enum rte_mac_filter_type desired_filter;
4319         int ret = I40E_SUCCESS;
4320
4321         if (on) {
4322                 /* Filter to match MAC and VLAN */
4323                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4324         } else {
4325                 /* Filter to match only MAC */
4326                 desired_filter = RTE_MAC_PERFECT_MATCH;
4327         }
4328
4329         num = vsi->mac_num;
4330
4331         mac_filter = rte_zmalloc("mac_filter_info_data",
4332                                  num * sizeof(*mac_filter), 0);
4333         if (mac_filter == NULL) {
4334                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4335                 return I40E_ERR_NO_MEMORY;
4336         }
4337
4338         i = 0;
4339
4340         /* Remove all existing mac */
4341         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4342                 mac_filter[i] = f->mac_info;
4343                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4344                 if (ret) {
4345                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4346                                     on ? "enable" : "disable");
4347                         goto DONE;
4348                 }
4349                 i++;
4350         }
4351
4352         /* Override with new filter */
4353         for (i = 0; i < num; i++) {
4354                 mac_filter[i].filter_type = desired_filter;
4355                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4356                 if (ret) {
4357                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4358                                     on ? "enable" : "disable");
4359                         goto DONE;
4360                 }
4361         }
4362
4363 DONE:
4364         rte_free(mac_filter);
4365         return ret;
4366 }
4367
4368 /* Configure vlan stripping on or off */
4369 int
4370 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4371 {
4372         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4373         struct i40e_vsi_context ctxt;
4374         uint8_t vlan_flags;
4375         int ret = I40E_SUCCESS;
4376
4377         /* Check if it has been already on or off */
4378         if (vsi->info.valid_sections &
4379                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4380                 if (on) {
4381                         if ((vsi->info.port_vlan_flags &
4382                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4383                                 return 0; /* already on */
4384                 } else {
4385                         if ((vsi->info.port_vlan_flags &
4386                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4387                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4388                                 return 0; /* already off */
4389                 }
4390         }
4391
4392         if (on)
4393                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4394         else
4395                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4396         vsi->info.valid_sections =
4397                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4398         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4399         vsi->info.port_vlan_flags |= vlan_flags;
4400         ctxt.seid = vsi->seid;
4401         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4402         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4403         if (ret)
4404                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4405                             on ? "enable" : "disable");
4406
4407         return ret;
4408 }
4409
4410 static int
4411 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4412 {
4413         struct rte_eth_dev_data *data = dev->data;
4414         int ret;
4415         int mask = 0;
4416
4417         /* Apply vlan offload setting */
4418         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4419         i40e_vlan_offload_set(dev, mask);
4420
4421         /* Apply double-vlan setting, not implemented yet */
4422
4423         /* Apply pvid setting */
4424         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4425                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4426         if (ret)
4427                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4428
4429         return ret;
4430 }
4431
4432 static int
4433 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4434 {
4435         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4436
4437         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4438 }
4439
4440 static int
4441 i40e_update_flow_control(struct i40e_hw *hw)
4442 {
4443 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4444         struct i40e_link_status link_status;
4445         uint32_t rxfc = 0, txfc = 0, reg;
4446         uint8_t an_info;
4447         int ret;
4448
4449         memset(&link_status, 0, sizeof(link_status));
4450         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4451         if (ret != I40E_SUCCESS) {
4452                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4453                 goto write_reg; /* Disable flow control */
4454         }
4455
4456         an_info = hw->phy.link_info.an_info;
4457         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4458                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4459                 ret = I40E_ERR_NOT_READY;
4460                 goto write_reg; /* Disable flow control */
4461         }
4462         /**
4463          * If link auto negotiation is enabled, flow control needs to
4464          * be configured according to it
4465          */
4466         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4467         case I40E_LINK_PAUSE_RXTX:
4468                 rxfc = 1;
4469                 txfc = 1;
4470                 hw->fc.current_mode = I40E_FC_FULL;
4471                 break;
4472         case I40E_AQ_LINK_PAUSE_RX:
4473                 rxfc = 1;
4474                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4475                 break;
4476         case I40E_AQ_LINK_PAUSE_TX:
4477                 txfc = 1;
4478                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4479                 break;
4480         default:
4481                 hw->fc.current_mode = I40E_FC_NONE;
4482                 break;
4483         }
4484
4485 write_reg:
4486         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4487                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4488         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4489         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4490         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4491         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4492
4493         return ret;
4494 }
4495
4496 /* PF setup */
4497 static int
4498 i40e_pf_setup(struct i40e_pf *pf)
4499 {
4500         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4501         struct i40e_filter_control_settings settings;
4502         struct i40e_vsi *vsi;
4503         int ret;
4504
4505         /* Clear all stats counters */
4506         pf->offset_loaded = FALSE;
4507         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4508         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4509
4510         ret = i40e_pf_get_switch_config(pf);
4511         if (ret != I40E_SUCCESS) {
4512                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4513                 return ret;
4514         }
4515         if (pf->flags & I40E_FLAG_FDIR) {
4516                 /* make queue allocated first, let FDIR use queue pair 0*/
4517                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4518                 if (ret != I40E_FDIR_QUEUE_ID) {
4519                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4520                                     " ret =%d", ret);
4521                         pf->flags &= ~I40E_FLAG_FDIR;
4522                 }
4523         }
4524         /*  main VSI setup */
4525         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4526         if (!vsi) {
4527                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4528                 return I40E_ERR_NOT_READY;
4529         }
4530         pf->main_vsi = vsi;
4531
4532         /* Configure filter control */
4533         memset(&settings, 0, sizeof(settings));
4534         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4535                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4536         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4537                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4538         else {
4539                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4540                                                 hw->func_caps.rss_table_size);
4541                 return I40E_ERR_PARAM;
4542         }
4543         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4544                         "size: %u\n", hw->func_caps.rss_table_size);
4545         pf->hash_lut_size = hw->func_caps.rss_table_size;
4546
4547         /* Enable ethtype and macvlan filters */
4548         settings.enable_ethtype = TRUE;
4549         settings.enable_macvlan = TRUE;
4550         ret = i40e_set_filter_control(hw, &settings);
4551         if (ret)
4552                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4553                                                                 ret);
4554
4555         /* Update flow control according to the auto negotiation */
4556         i40e_update_flow_control(hw);
4557
4558         return I40E_SUCCESS;
4559 }
4560
4561 int
4562 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4563 {
4564         uint32_t reg;
4565         uint16_t j;
4566
4567         /**
4568          * Set or clear TX Queue Disable flags,
4569          * which is required by hardware.
4570          */
4571         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4572         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4573
4574         /* Wait until the request is finished */
4575         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4576                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4577                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4578                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4579                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4580                                                         & 0x1))) {
4581                         break;
4582                 }
4583         }
4584         if (on) {
4585                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4586                         return I40E_SUCCESS; /* already on, skip next steps */
4587
4588                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4589                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4590         } else {
4591                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4592                         return I40E_SUCCESS; /* already off, skip next steps */
4593                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4594         }
4595         /* Write the register */
4596         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4597         /* Check the result */
4598         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4599                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4600                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4601                 if (on) {
4602                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4603                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4604                                 break;
4605                 } else {
4606                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4607                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4608                                 break;
4609                 }
4610         }
4611         /* Check if it is timeout */
4612         if (j >= I40E_CHK_Q_ENA_COUNT) {
4613                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4614                             (on ? "enable" : "disable"), q_idx);
4615                 return I40E_ERR_TIMEOUT;
4616         }
4617
4618         return I40E_SUCCESS;
4619 }
4620
4621 /* Swith on or off the tx queues */
4622 static int
4623 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4624 {
4625         struct rte_eth_dev_data *dev_data = pf->dev_data;
4626         struct i40e_tx_queue *txq;
4627         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4628         uint16_t i;
4629         int ret;
4630
4631         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4632                 txq = dev_data->tx_queues[i];
4633                 /* Don't operate the queue if not configured or
4634                  * if starting only per queue */
4635                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4636                         continue;
4637                 if (on)
4638                         ret = i40e_dev_tx_queue_start(dev, i);
4639                 else
4640                         ret = i40e_dev_tx_queue_stop(dev, i);
4641                 if ( ret != I40E_SUCCESS)
4642                         return ret;
4643         }
4644
4645         return I40E_SUCCESS;
4646 }
4647
4648 int
4649 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4650 {
4651         uint32_t reg;
4652         uint16_t j;
4653
4654         /* Wait until the request is finished */
4655         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4656                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4657                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4658                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4659                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4660                         break;
4661         }
4662
4663         if (on) {
4664                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4665                         return I40E_SUCCESS; /* Already on, skip next steps */
4666                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4667         } else {
4668                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4669                         return I40E_SUCCESS; /* Already off, skip next steps */
4670                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4671         }
4672
4673         /* Write the register */
4674         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4675         /* Check the result */
4676         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4677                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4678                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4679                 if (on) {
4680                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4681                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4682                                 break;
4683                 } else {
4684                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4685                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4686                                 break;
4687                 }
4688         }
4689
4690         /* Check if it is timeout */
4691         if (j >= I40E_CHK_Q_ENA_COUNT) {
4692                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4693                             (on ? "enable" : "disable"), q_idx);
4694                 return I40E_ERR_TIMEOUT;
4695         }
4696
4697         return I40E_SUCCESS;
4698 }
4699 /* Switch on or off the rx queues */
4700 static int
4701 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4702 {
4703         struct rte_eth_dev_data *dev_data = pf->dev_data;
4704         struct i40e_rx_queue *rxq;
4705         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4706         uint16_t i;
4707         int ret;
4708
4709         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4710                 rxq = dev_data->rx_queues[i];
4711                 /* Don't operate the queue if not configured or
4712                  * if starting only per queue */
4713                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4714                         continue;
4715                 if (on)
4716                         ret = i40e_dev_rx_queue_start(dev, i);
4717                 else
4718                         ret = i40e_dev_rx_queue_stop(dev, i);
4719                 if (ret != I40E_SUCCESS)
4720                         return ret;
4721         }
4722
4723         return I40E_SUCCESS;
4724 }
4725
4726 /* Switch on or off all the rx/tx queues */
4727 int
4728 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4729 {
4730         int ret;
4731
4732         if (on) {
4733                 /* enable rx queues before enabling tx queues */
4734                 ret = i40e_dev_switch_rx_queues(pf, on);
4735                 if (ret) {
4736                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4737                         return ret;
4738                 }
4739                 ret = i40e_dev_switch_tx_queues(pf, on);
4740         } else {
4741                 /* Stop tx queues before stopping rx queues */
4742                 ret = i40e_dev_switch_tx_queues(pf, on);
4743                 if (ret) {
4744                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4745                         return ret;
4746                 }
4747                 ret = i40e_dev_switch_rx_queues(pf, on);
4748         }
4749
4750         return ret;
4751 }
4752
4753 /* Initialize VSI for TX */
4754 static int
4755 i40e_dev_tx_init(struct i40e_pf *pf)
4756 {
4757         struct rte_eth_dev_data *data = pf->dev_data;
4758         uint16_t i;
4759         uint32_t ret = I40E_SUCCESS;
4760         struct i40e_tx_queue *txq;
4761
4762         for (i = 0; i < data->nb_tx_queues; i++) {
4763                 txq = data->tx_queues[i];
4764                 if (!txq || !txq->q_set)
4765                         continue;
4766                 ret = i40e_tx_queue_init(txq);
4767                 if (ret != I40E_SUCCESS)
4768                         break;
4769         }
4770         if (ret == I40E_SUCCESS)
4771                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4772                                      ->eth_dev);
4773
4774         return ret;
4775 }
4776
4777 /* Initialize VSI for RX */
4778 static int
4779 i40e_dev_rx_init(struct i40e_pf *pf)
4780 {
4781         struct rte_eth_dev_data *data = pf->dev_data;
4782         int ret = I40E_SUCCESS;
4783         uint16_t i;
4784         struct i40e_rx_queue *rxq;
4785
4786         i40e_pf_config_mq_rx(pf);
4787         for (i = 0; i < data->nb_rx_queues; i++) {
4788                 rxq = data->rx_queues[i];
4789                 if (!rxq || !rxq->q_set)
4790                         continue;
4791
4792                 ret = i40e_rx_queue_init(rxq);
4793                 if (ret != I40E_SUCCESS) {
4794                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4795                                     "initialization");
4796                         break;
4797                 }
4798         }
4799         if (ret == I40E_SUCCESS)
4800                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4801                                      ->eth_dev);
4802
4803         return ret;
4804 }
4805
4806 static int
4807 i40e_dev_rxtx_init(struct i40e_pf *pf)
4808 {
4809         int err;
4810
4811         err = i40e_dev_tx_init(pf);
4812         if (err) {
4813                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4814                 return err;
4815         }
4816         err = i40e_dev_rx_init(pf);
4817         if (err) {
4818                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4819                 return err;
4820         }
4821
4822         return err;
4823 }
4824
4825 static int
4826 i40e_vmdq_setup(struct rte_eth_dev *dev)
4827 {
4828         struct rte_eth_conf *conf = &dev->data->dev_conf;
4829         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4830         int i, err, conf_vsis, j, loop;
4831         struct i40e_vsi *vsi;
4832         struct i40e_vmdq_info *vmdq_info;
4833         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4834         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4835
4836         /*
4837          * Disable interrupt to avoid message from VF. Furthermore, it will
4838          * avoid race condition in VSI creation/destroy.
4839          */
4840         i40e_pf_disable_irq0(hw);
4841
4842         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4843                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4844                 return -ENOTSUP;
4845         }
4846
4847         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4848         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4849                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4850                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4851                         pf->max_nb_vmdq_vsi);
4852                 return -ENOTSUP;
4853         }
4854
4855         if (pf->vmdq != NULL) {
4856                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4857                 return 0;
4858         }
4859
4860         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4861                                 sizeof(*vmdq_info) * conf_vsis, 0);
4862
4863         if (pf->vmdq == NULL) {
4864                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4865                 return -ENOMEM;
4866         }
4867
4868         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4869
4870         /* Create VMDQ VSI */
4871         for (i = 0; i < conf_vsis; i++) {
4872                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4873                                 vmdq_conf->enable_loop_back);
4874                 if (vsi == NULL) {
4875                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4876                         err = -1;
4877                         goto err_vsi_setup;
4878                 }
4879                 vmdq_info = &pf->vmdq[i];
4880                 vmdq_info->pf = pf;
4881                 vmdq_info->vsi = vsi;
4882         }
4883         pf->nb_cfg_vmdq_vsi = conf_vsis;
4884
4885         /* Configure Vlan */
4886         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4887         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4888                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4889                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4890                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4891                                         vmdq_conf->pool_map[i].vlan_id, j);
4892
4893                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4894                                                 vmdq_conf->pool_map[i].vlan_id);
4895                                 if (err) {
4896                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4897                                         err = -1;
4898                                         goto err_vsi_setup;
4899                                 }
4900                         }
4901                 }
4902         }
4903
4904         i40e_pf_enable_irq0(hw);
4905
4906         return 0;
4907
4908 err_vsi_setup:
4909         for (i = 0; i < conf_vsis; i++)
4910                 if (pf->vmdq[i].vsi == NULL)
4911                         break;
4912                 else
4913                         i40e_vsi_release(pf->vmdq[i].vsi);
4914
4915         rte_free(pf->vmdq);
4916         pf->vmdq = NULL;
4917         i40e_pf_enable_irq0(hw);
4918         return err;
4919 }
4920
4921 static void
4922 i40e_stat_update_32(struct i40e_hw *hw,
4923                    uint32_t reg,
4924                    bool offset_loaded,
4925                    uint64_t *offset,
4926                    uint64_t *stat)
4927 {
4928         uint64_t new_data;
4929
4930         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4931         if (!offset_loaded)
4932                 *offset = new_data;
4933
4934         if (new_data >= *offset)
4935                 *stat = (uint64_t)(new_data - *offset);
4936         else
4937                 *stat = (uint64_t)((new_data +
4938                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4939 }
4940
4941 static void
4942 i40e_stat_update_48(struct i40e_hw *hw,
4943                    uint32_t hireg,
4944                    uint32_t loreg,
4945                    bool offset_loaded,
4946                    uint64_t *offset,
4947                    uint64_t *stat)
4948 {
4949         uint64_t new_data;
4950
4951         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4952         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4953                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4954
4955         if (!offset_loaded)
4956                 *offset = new_data;
4957
4958         if (new_data >= *offset)
4959                 *stat = new_data - *offset;
4960         else
4961                 *stat = (uint64_t)((new_data +
4962                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4963
4964         *stat &= I40E_48_BIT_MASK;
4965 }
4966
4967 /* Disable IRQ0 */
4968 void
4969 i40e_pf_disable_irq0(struct i40e_hw *hw)
4970 {
4971         /* Disable all interrupt types */
4972         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4973         I40E_WRITE_FLUSH(hw);
4974 }
4975
4976 /* Enable IRQ0 */
4977 void
4978 i40e_pf_enable_irq0(struct i40e_hw *hw)
4979 {
4980         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4981                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4982                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4983                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4984         I40E_WRITE_FLUSH(hw);
4985 }
4986
4987 static void
4988 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4989 {
4990         /* read pending request and disable first */
4991         i40e_pf_disable_irq0(hw);
4992         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4993         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4994                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4995
4996         if (no_queue)
4997                 /* Link no queues with irq0 */
4998                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4999                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5000 }
5001
5002 static void
5003 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5004 {
5005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5007         int i;
5008         uint16_t abs_vf_id;
5009         uint32_t index, offset, val;
5010
5011         if (!pf->vfs)
5012                 return;
5013         /**
5014          * Try to find which VF trigger a reset, use absolute VF id to access
5015          * since the reg is global register.
5016          */
5017         for (i = 0; i < pf->vf_num; i++) {
5018                 abs_vf_id = hw->func_caps.vf_base_id + i;
5019                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5020                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5021                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5022                 /* VFR event occured */
5023                 if (val & (0x1 << offset)) {
5024                         int ret;
5025
5026                         /* Clear the event first */
5027                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5028                                                         (0x1 << offset));
5029                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5030                         /**
5031                          * Only notify a VF reset event occured,
5032                          * don't trigger another SW reset
5033                          */
5034                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5035                         if (ret != I40E_SUCCESS)
5036                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5037                 }
5038         }
5039 }
5040
5041 static void
5042 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5043 {
5044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         struct i40e_arq_event_info info;
5046         uint16_t pending, opcode;
5047         int ret;
5048
5049         info.buf_len = I40E_AQ_BUF_SZ;
5050         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5051         if (!info.msg_buf) {
5052                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5053                 return;
5054         }
5055
5056         pending = 1;
5057         while (pending) {
5058                 ret = i40e_clean_arq_element(hw, &info, &pending);
5059
5060                 if (ret != I40E_SUCCESS) {
5061                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5062                                     "aq_err: %u", hw->aq.asq_last_status);
5063                         break;
5064                 }
5065                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5066
5067                 switch (opcode) {
5068                 case i40e_aqc_opc_send_msg_to_pf:
5069                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5070                         i40e_pf_host_handle_vf_msg(dev,
5071                                         rte_le_to_cpu_16(info.desc.retval),
5072                                         rte_le_to_cpu_32(info.desc.cookie_high),
5073                                         rte_le_to_cpu_32(info.desc.cookie_low),
5074                                         info.msg_buf,
5075                                         info.msg_len);
5076                         break;
5077                 default:
5078                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5079                                     opcode);
5080                         break;
5081                 }
5082         }
5083         rte_free(info.msg_buf);
5084 }
5085
5086 /*
5087  * Interrupt handler is registered as the alarm callback for handling LSC
5088  * interrupt in a definite of time, in order to wait the NIC into a stable
5089  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5090  * no need for link down interrupt.
5091  */
5092 static void
5093 i40e_dev_interrupt_delayed_handler(void *param)
5094 {
5095         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5097         uint32_t icr0;
5098
5099         /* read interrupt causes again */
5100         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5101
5102 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5103         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5104                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5105         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5106                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5107         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5108                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5109         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5110                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5111         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5112                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5113                                                                 "state\n");
5114         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5115                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5116         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5117                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5118 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5119
5120         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5121                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5122                 i40e_dev_handle_vfr_event(dev);
5123         }
5124         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5125                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5126                 i40e_dev_handle_aq_msg(dev);
5127         }
5128
5129         /* handle the link up interrupt in an alarm callback */
5130         i40e_dev_link_update(dev, 0);
5131         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5132
5133         i40e_pf_enable_irq0(hw);
5134         rte_intr_enable(&(dev->pci_dev->intr_handle));
5135 }
5136
5137 /**
5138  * Interrupt handler triggered by NIC  for handling
5139  * specific interrupt.
5140  *
5141  * @param handle
5142  *  Pointer to interrupt handle.
5143  * @param param
5144  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5145  *
5146  * @return
5147  *  void
5148  */
5149 static void
5150 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5151                            void *param)
5152 {
5153         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         uint32_t icr0;
5156
5157         /* Disable interrupt */
5158         i40e_pf_disable_irq0(hw);
5159
5160         /* read out interrupt causes */
5161         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5162
5163         /* No interrupt event indicated */
5164         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5165                 PMD_DRV_LOG(INFO, "No interrupt event");
5166                 goto done;
5167         }
5168 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5169         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5170                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5171         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5172                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5173         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5174                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5175         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5176                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5177         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5178                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5179         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5180                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5181         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5182                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5183 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5184
5185         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5186                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5187                 i40e_dev_handle_vfr_event(dev);
5188         }
5189         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5190                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5191                 i40e_dev_handle_aq_msg(dev);
5192         }
5193
5194         /* Link Status Change interrupt */
5195         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5196 #define I40E_US_PER_SECOND 1000000
5197                 struct rte_eth_link link;
5198
5199                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5200                 memset(&link, 0, sizeof(link));
5201                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5202                 i40e_dev_link_update(dev, 0);
5203
5204                 /*
5205                  * For link up interrupt, it needs to wait 1 second to let the
5206                  * hardware be a stable state. Otherwise several consecutive
5207                  * interrupts can be observed.
5208                  * For link down interrupt, no need to wait.
5209                  */
5210                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5211                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5212                         return;
5213                 else
5214                         _rte_eth_dev_callback_process(dev,
5215                                 RTE_ETH_EVENT_INTR_LSC);
5216         }
5217
5218 done:
5219         /* Enable interrupt */
5220         i40e_pf_enable_irq0(hw);
5221         rte_intr_enable(&(dev->pci_dev->intr_handle));
5222 }
5223
5224 static int
5225 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5226                          struct i40e_macvlan_filter *filter,
5227                          int total)
5228 {
5229         int ele_num, ele_buff_size;
5230         int num, actual_num, i;
5231         uint16_t flags;
5232         int ret = I40E_SUCCESS;
5233         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5234         struct i40e_aqc_add_macvlan_element_data *req_list;
5235
5236         if (filter == NULL  || total == 0)
5237                 return I40E_ERR_PARAM;
5238         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5239         ele_buff_size = hw->aq.asq_buf_size;
5240
5241         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5242         if (req_list == NULL) {
5243                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5244                 return I40E_ERR_NO_MEMORY;
5245         }
5246
5247         num = 0;
5248         do {
5249                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5250                 memset(req_list, 0, ele_buff_size);
5251
5252                 for (i = 0; i < actual_num; i++) {
5253                         (void)rte_memcpy(req_list[i].mac_addr,
5254                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5255                         req_list[i].vlan_tag =
5256                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5257
5258                         switch (filter[num + i].filter_type) {
5259                         case RTE_MAC_PERFECT_MATCH:
5260                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5261                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5262                                 break;
5263                         case RTE_MACVLAN_PERFECT_MATCH:
5264                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5265                                 break;
5266                         case RTE_MAC_HASH_MATCH:
5267                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5268                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5269                                 break;
5270                         case RTE_MACVLAN_HASH_MATCH:
5271                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5272                                 break;
5273                         default:
5274                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5275                                 ret = I40E_ERR_PARAM;
5276                                 goto DONE;
5277                         }
5278
5279                         req_list[i].queue_number = 0;
5280
5281                         req_list[i].flags = rte_cpu_to_le_16(flags);
5282                 }
5283
5284                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5285                                                 actual_num, NULL);
5286                 if (ret != I40E_SUCCESS) {
5287                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5288                         goto DONE;
5289                 }
5290                 num += actual_num;
5291         } while (num < total);
5292
5293 DONE:
5294         rte_free(req_list);
5295         return ret;
5296 }
5297
5298 static int
5299 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5300                             struct i40e_macvlan_filter *filter,
5301                             int total)
5302 {
5303         int ele_num, ele_buff_size;
5304         int num, actual_num, i;
5305         uint16_t flags;
5306         int ret = I40E_SUCCESS;
5307         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5308         struct i40e_aqc_remove_macvlan_element_data *req_list;
5309
5310         if (filter == NULL  || total == 0)
5311                 return I40E_ERR_PARAM;
5312
5313         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5314         ele_buff_size = hw->aq.asq_buf_size;
5315
5316         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5317         if (req_list == NULL) {
5318                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5319                 return I40E_ERR_NO_MEMORY;
5320         }
5321
5322         num = 0;
5323         do {
5324                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5325                 memset(req_list, 0, ele_buff_size);
5326
5327                 for (i = 0; i < actual_num; i++) {
5328                         (void)rte_memcpy(req_list[i].mac_addr,
5329                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5330                         req_list[i].vlan_tag =
5331                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5332
5333                         switch (filter[num + i].filter_type) {
5334                         case RTE_MAC_PERFECT_MATCH:
5335                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5336                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5337                                 break;
5338                         case RTE_MACVLAN_PERFECT_MATCH:
5339                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5340                                 break;
5341                         case RTE_MAC_HASH_MATCH:
5342                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5343                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5344                                 break;
5345                         case RTE_MACVLAN_HASH_MATCH:
5346                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5347                                 break;
5348                         default:
5349                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5350                                 ret = I40E_ERR_PARAM;
5351                                 goto DONE;
5352                         }
5353                         req_list[i].flags = rte_cpu_to_le_16(flags);
5354                 }
5355
5356                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5357                                                 actual_num, NULL);
5358                 if (ret != I40E_SUCCESS) {
5359                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5360                         goto DONE;
5361                 }
5362                 num += actual_num;
5363         } while (num < total);
5364
5365 DONE:
5366         rte_free(req_list);
5367         return ret;
5368 }
5369
5370 /* Find out specific MAC filter */
5371 static struct i40e_mac_filter *
5372 i40e_find_mac_filter(struct i40e_vsi *vsi,
5373                          struct ether_addr *macaddr)
5374 {
5375         struct i40e_mac_filter *f;
5376
5377         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5378                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5379                         return f;
5380         }
5381
5382         return NULL;
5383 }
5384
5385 static bool
5386 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5387                          uint16_t vlan_id)
5388 {
5389         uint32_t vid_idx, vid_bit;
5390
5391         if (vlan_id > ETH_VLAN_ID_MAX)
5392                 return 0;
5393
5394         vid_idx = I40E_VFTA_IDX(vlan_id);
5395         vid_bit = I40E_VFTA_BIT(vlan_id);
5396
5397         if (vsi->vfta[vid_idx] & vid_bit)
5398                 return 1;
5399         else
5400                 return 0;
5401 }
5402
5403 static void
5404 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5405                          uint16_t vlan_id, bool on)
5406 {
5407         uint32_t vid_idx, vid_bit;
5408
5409         if (vlan_id > ETH_VLAN_ID_MAX)
5410                 return;
5411
5412         vid_idx = I40E_VFTA_IDX(vlan_id);
5413         vid_bit = I40E_VFTA_BIT(vlan_id);
5414
5415         if (on)
5416                 vsi->vfta[vid_idx] |= vid_bit;
5417         else
5418                 vsi->vfta[vid_idx] &= ~vid_bit;
5419 }
5420
5421 /**
5422  * Find all vlan options for specific mac addr,
5423  * return with actual vlan found.
5424  */
5425 static inline int
5426 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5427                            struct i40e_macvlan_filter *mv_f,
5428                            int num, struct ether_addr *addr)
5429 {
5430         int i;
5431         uint32_t j, k;
5432
5433         /**
5434          * Not to use i40e_find_vlan_filter to decrease the loop time,
5435          * although the code looks complex.
5436           */
5437         if (num < vsi->vlan_num)
5438                 return I40E_ERR_PARAM;
5439
5440         i = 0;
5441         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5442                 if (vsi->vfta[j]) {
5443                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5444                                 if (vsi->vfta[j] & (1 << k)) {
5445                                         if (i > num - 1) {
5446                                                 PMD_DRV_LOG(ERR, "vlan number "
5447                                                             "not match");
5448                                                 return I40E_ERR_PARAM;
5449                                         }
5450                                         (void)rte_memcpy(&mv_f[i].macaddr,
5451                                                         addr, ETH_ADDR_LEN);
5452                                         mv_f[i].vlan_id =
5453                                                 j * I40E_UINT32_BIT_SIZE + k;
5454                                         i++;
5455                                 }
5456                         }
5457                 }
5458         }
5459         return I40E_SUCCESS;
5460 }
5461
5462 static inline int
5463 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5464                            struct i40e_macvlan_filter *mv_f,
5465                            int num,
5466                            uint16_t vlan)
5467 {
5468         int i = 0;
5469         struct i40e_mac_filter *f;
5470
5471         if (num < vsi->mac_num)
5472                 return I40E_ERR_PARAM;
5473
5474         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5475                 if (i > num - 1) {
5476                         PMD_DRV_LOG(ERR, "buffer number not match");
5477                         return I40E_ERR_PARAM;
5478                 }
5479                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5480                                 ETH_ADDR_LEN);
5481                 mv_f[i].vlan_id = vlan;
5482                 mv_f[i].filter_type = f->mac_info.filter_type;
5483                 i++;
5484         }
5485
5486         return I40E_SUCCESS;
5487 }
5488
5489 static int
5490 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5491 {
5492         int i, num;
5493         struct i40e_mac_filter *f;
5494         struct i40e_macvlan_filter *mv_f;
5495         int ret = I40E_SUCCESS;
5496
5497         if (vsi == NULL || vsi->mac_num == 0)
5498                 return I40E_ERR_PARAM;
5499
5500         /* Case that no vlan is set */
5501         if (vsi->vlan_num == 0)
5502                 num = vsi->mac_num;
5503         else
5504                 num = vsi->mac_num * vsi->vlan_num;
5505
5506         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5507         if (mv_f == NULL) {
5508                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5509                 return I40E_ERR_NO_MEMORY;
5510         }
5511
5512         i = 0;
5513         if (vsi->vlan_num == 0) {
5514                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5515                         (void)rte_memcpy(&mv_f[i].macaddr,
5516                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5517                         mv_f[i].vlan_id = 0;
5518                         i++;
5519                 }
5520         } else {
5521                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5522                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5523                                         vsi->vlan_num, &f->mac_info.mac_addr);
5524                         if (ret != I40E_SUCCESS)
5525                                 goto DONE;
5526                         i += vsi->vlan_num;
5527                 }
5528         }
5529
5530         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5531 DONE:
5532         rte_free(mv_f);
5533
5534         return ret;
5535 }
5536
5537 int
5538 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5539 {
5540         struct i40e_macvlan_filter *mv_f;
5541         int mac_num;
5542         int ret = I40E_SUCCESS;
5543
5544         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5545                 return I40E_ERR_PARAM;
5546
5547         /* If it's already set, just return */
5548         if (i40e_find_vlan_filter(vsi,vlan))
5549                 return I40E_SUCCESS;
5550
5551         mac_num = vsi->mac_num;
5552
5553         if (mac_num == 0) {
5554                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5555                 return I40E_ERR_PARAM;
5556         }
5557
5558         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5559
5560         if (mv_f == NULL) {
5561                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5562                 return I40E_ERR_NO_MEMORY;
5563         }
5564
5565         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5566
5567         if (ret != I40E_SUCCESS)
5568                 goto DONE;
5569
5570         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5571
5572         if (ret != I40E_SUCCESS)
5573                 goto DONE;
5574
5575         i40e_set_vlan_filter(vsi, vlan, 1);
5576
5577         vsi->vlan_num++;
5578         ret = I40E_SUCCESS;
5579 DONE:
5580         rte_free(mv_f);
5581         return ret;
5582 }
5583
5584 int
5585 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5586 {
5587         struct i40e_macvlan_filter *mv_f;
5588         int mac_num;
5589         int ret = I40E_SUCCESS;
5590
5591         /**
5592          * Vlan 0 is the generic filter for untagged packets
5593          * and can't be removed.
5594          */
5595         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5596                 return I40E_ERR_PARAM;
5597
5598         /* If can't find it, just return */
5599         if (!i40e_find_vlan_filter(vsi, vlan))
5600                 return I40E_ERR_PARAM;
5601
5602         mac_num = vsi->mac_num;
5603
5604         if (mac_num == 0) {
5605                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5606                 return I40E_ERR_PARAM;
5607         }
5608
5609         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5610
5611         if (mv_f == NULL) {
5612                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5613                 return I40E_ERR_NO_MEMORY;
5614         }
5615
5616         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5617
5618         if (ret != I40E_SUCCESS)
5619                 goto DONE;
5620
5621         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5622
5623         if (ret != I40E_SUCCESS)
5624                 goto DONE;
5625
5626         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5627         if (vsi->vlan_num == 1) {
5628                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5629                 if (ret != I40E_SUCCESS)
5630                         goto DONE;
5631
5632                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5633                 if (ret != I40E_SUCCESS)
5634                         goto DONE;
5635         }
5636
5637         i40e_set_vlan_filter(vsi, vlan, 0);
5638
5639         vsi->vlan_num--;
5640         ret = I40E_SUCCESS;
5641 DONE:
5642         rte_free(mv_f);
5643         return ret;
5644 }
5645
5646 int
5647 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5648 {
5649         struct i40e_mac_filter *f;
5650         struct i40e_macvlan_filter *mv_f;
5651         int i, vlan_num = 0;
5652         int ret = I40E_SUCCESS;
5653
5654         /* If it's add and we've config it, return */
5655         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5656         if (f != NULL)
5657                 return I40E_SUCCESS;
5658         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5659                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5660
5661                 /**
5662                  * If vlan_num is 0, that's the first time to add mac,
5663                  * set mask for vlan_id 0.
5664                  */
5665                 if (vsi->vlan_num == 0) {
5666                         i40e_set_vlan_filter(vsi, 0, 1);
5667                         vsi->vlan_num = 1;
5668                 }
5669                 vlan_num = vsi->vlan_num;
5670         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5671                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5672                 vlan_num = 1;
5673
5674         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5675         if (mv_f == NULL) {
5676                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5677                 return I40E_ERR_NO_MEMORY;
5678         }
5679
5680         for (i = 0; i < vlan_num; i++) {
5681                 mv_f[i].filter_type = mac_filter->filter_type;
5682                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5683                                 ETH_ADDR_LEN);
5684         }
5685
5686         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5687                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5688                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5689                                         &mac_filter->mac_addr);
5690                 if (ret != I40E_SUCCESS)
5691                         goto DONE;
5692         }
5693
5694         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5695         if (ret != I40E_SUCCESS)
5696                 goto DONE;
5697
5698         /* Add the mac addr into mac list */
5699         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5700         if (f == NULL) {
5701                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5702                 ret = I40E_ERR_NO_MEMORY;
5703                 goto DONE;
5704         }
5705         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5706                         ETH_ADDR_LEN);
5707         f->mac_info.filter_type = mac_filter->filter_type;
5708         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5709         vsi->mac_num++;
5710
5711         ret = I40E_SUCCESS;
5712 DONE:
5713         rte_free(mv_f);
5714
5715         return ret;
5716 }
5717
5718 int
5719 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5720 {
5721         struct i40e_mac_filter *f;
5722         struct i40e_macvlan_filter *mv_f;
5723         int i, vlan_num;
5724         enum rte_mac_filter_type filter_type;
5725         int ret = I40E_SUCCESS;
5726
5727         /* Can't find it, return an error */
5728         f = i40e_find_mac_filter(vsi, addr);
5729         if (f == NULL)
5730                 return I40E_ERR_PARAM;
5731
5732         vlan_num = vsi->vlan_num;
5733         filter_type = f->mac_info.filter_type;
5734         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5735                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5736                 if (vlan_num == 0) {
5737                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5738                         return I40E_ERR_PARAM;
5739                 }
5740         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5741                         filter_type == RTE_MAC_HASH_MATCH)
5742                 vlan_num = 1;
5743
5744         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5745         if (mv_f == NULL) {
5746                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5747                 return I40E_ERR_NO_MEMORY;
5748         }
5749
5750         for (i = 0; i < vlan_num; i++) {
5751                 mv_f[i].filter_type = filter_type;
5752                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5753                                 ETH_ADDR_LEN);
5754         }
5755         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5756                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5757                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5758                 if (ret != I40E_SUCCESS)
5759                         goto DONE;
5760         }
5761
5762         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5763         if (ret != I40E_SUCCESS)
5764                 goto DONE;
5765
5766         /* Remove the mac addr into mac list */
5767         TAILQ_REMOVE(&vsi->mac_list, f, next);
5768         rte_free(f);
5769         vsi->mac_num--;
5770
5771         ret = I40E_SUCCESS;
5772 DONE:
5773         rte_free(mv_f);
5774         return ret;
5775 }
5776
5777 /* Configure hash enable flags for RSS */
5778 uint64_t
5779 i40e_config_hena(uint64_t flags)
5780 {
5781         uint64_t hena = 0;
5782
5783         if (!flags)
5784                 return hena;
5785
5786         if (flags & ETH_RSS_FRAG_IPV4)
5787                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5788         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5789                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5790         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5791                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5792         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5793                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5794         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5795                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5796         if (flags & ETH_RSS_FRAG_IPV6)
5797                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5798         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5799                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5800         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5801                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5802         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5803                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5804         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5805                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5806         if (flags & ETH_RSS_L2_PAYLOAD)
5807                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5808
5809         return hena;
5810 }
5811
5812 /* Parse the hash enable flags */
5813 uint64_t
5814 i40e_parse_hena(uint64_t flags)
5815 {
5816         uint64_t rss_hf = 0;
5817
5818         if (!flags)
5819                 return rss_hf;
5820         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5821                 rss_hf |= ETH_RSS_FRAG_IPV4;
5822         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5823                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5824         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5825                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5826         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5827                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5828         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5829                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5830         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5831                 rss_hf |= ETH_RSS_FRAG_IPV6;
5832         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5833                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5834         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5835                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5836         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5837                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5838         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5839                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5840         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5841                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5842
5843         return rss_hf;
5844 }
5845
5846 /* Disable RSS */
5847 static void
5848 i40e_pf_disable_rss(struct i40e_pf *pf)
5849 {
5850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5851         uint64_t hena;
5852
5853         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5854         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5855         hena &= ~I40E_RSS_HENA_ALL;
5856         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5857         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5858         I40E_WRITE_FLUSH(hw);
5859 }
5860
5861 static int
5862 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5863 {
5864         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5865         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5866         int ret = 0;
5867
5868         if (!key || key_len == 0) {
5869                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5870                 return 0;
5871         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5872                 sizeof(uint32_t)) {
5873                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5874                 return -EINVAL;
5875         }
5876
5877         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5878                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5879                         (struct i40e_aqc_get_set_rss_key_data *)key;
5880
5881                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5882                 if (ret)
5883                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5884                                      "via AQ");
5885         } else {
5886                 uint32_t *hash_key = (uint32_t *)key;
5887                 uint16_t i;
5888
5889                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5890                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5891                 I40E_WRITE_FLUSH(hw);
5892         }
5893
5894         return ret;
5895 }
5896
5897 static int
5898 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5899 {
5900         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5901         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5902         int ret;
5903
5904         if (!key || !key_len)
5905                 return -EINVAL;
5906
5907         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5908                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5909                         (struct i40e_aqc_get_set_rss_key_data *)key);
5910                 if (ret) {
5911                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5912                         return ret;
5913                 }
5914         } else {
5915                 uint32_t *key_dw = (uint32_t *)key;
5916                 uint16_t i;
5917
5918                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5919                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5920         }
5921         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5922
5923         return 0;
5924 }
5925
5926 static int
5927 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5928 {
5929         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5930         uint64_t rss_hf;
5931         uint64_t hena;
5932         int ret;
5933
5934         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5935                                rss_conf->rss_key_len);
5936         if (ret)
5937                 return ret;
5938
5939         rss_hf = rss_conf->rss_hf;
5940         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5941         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5942         hena &= ~I40E_RSS_HENA_ALL;
5943         hena |= i40e_config_hena(rss_hf);
5944         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5945         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5946         I40E_WRITE_FLUSH(hw);
5947
5948         return 0;
5949 }
5950
5951 static int
5952 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5953                          struct rte_eth_rss_conf *rss_conf)
5954 {
5955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5958         uint64_t hena;
5959
5960         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5961         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5962         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5963                 if (rss_hf != 0) /* Enable RSS */
5964                         return -EINVAL;
5965                 return 0; /* Nothing to do */
5966         }
5967         /* RSS enabled */
5968         if (rss_hf == 0) /* Disable RSS */
5969                 return -EINVAL;
5970
5971         return i40e_hw_rss_hash_set(pf, rss_conf);
5972 }
5973
5974 static int
5975 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5976                            struct rte_eth_rss_conf *rss_conf)
5977 {
5978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980         uint64_t hena;
5981
5982         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5983                          &rss_conf->rss_key_len);
5984
5985         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5986         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5987         rss_conf->rss_hf = i40e_parse_hena(hena);
5988
5989         return 0;
5990 }
5991
5992 static int
5993 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5994 {
5995         switch (filter_type) {
5996         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5997                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5998                 break;
5999         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6000                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6001                 break;
6002         case RTE_TUNNEL_FILTER_IMAC_TENID:
6003                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6004                 break;
6005         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6006                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6007                 break;
6008         case ETH_TUNNEL_FILTER_IMAC:
6009                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6010                 break;
6011         case ETH_TUNNEL_FILTER_OIP:
6012                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6013                 break;
6014         case ETH_TUNNEL_FILTER_IIP:
6015                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6016                 break;
6017         default:
6018                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6019                 return -EINVAL;
6020         }
6021
6022         return 0;
6023 }
6024
6025 static int
6026 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6027                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6028                         uint8_t add)
6029 {
6030         uint16_t ip_type;
6031         uint8_t i, tun_type = 0;
6032         /* internal varialbe to convert ipv6 byte order */
6033         uint32_t convert_ipv6[4];
6034         int val, ret = 0;
6035         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6036         struct i40e_vsi *vsi = pf->main_vsi;
6037         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6038         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6039
6040         cld_filter = rte_zmalloc("tunnel_filter",
6041                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6042                 0);
6043
6044         if (NULL == cld_filter) {
6045                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6046                 return -EINVAL;
6047         }
6048         pfilter = cld_filter;
6049
6050         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6051         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6052
6053         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6054         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6055                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6056                 rte_memcpy(&pfilter->ipaddr.v4.data,
6057                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6058                                 sizeof(pfilter->ipaddr.v4.data));
6059         } else {
6060                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6061                 for (i = 0; i < 4; i++) {
6062                         convert_ipv6[i] =
6063                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6064                 }
6065                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6066                                 sizeof(pfilter->ipaddr.v6.data));
6067         }
6068
6069         /* check tunneled type */
6070         switch (tunnel_filter->tunnel_type) {
6071         case RTE_TUNNEL_TYPE_VXLAN:
6072                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6073                 break;
6074         case RTE_TUNNEL_TYPE_NVGRE:
6075                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6076                 break;
6077         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6078                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6079                 break;
6080         default:
6081                 /* Other tunnel types is not supported. */
6082                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6083                 rte_free(cld_filter);
6084                 return -EINVAL;
6085         }
6086
6087         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6088                                                 &pfilter->flags);
6089         if (val < 0) {
6090                 rte_free(cld_filter);
6091                 return -EINVAL;
6092         }
6093
6094         pfilter->flags |= rte_cpu_to_le_16(
6095                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6096                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6097         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6098         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6099
6100         if (add)
6101                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6102         else
6103                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6104                                                 cld_filter, 1);
6105
6106         rte_free(cld_filter);
6107         return ret;
6108 }
6109
6110 static int
6111 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6112 {
6113         uint8_t i;
6114
6115         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6116                 if (pf->vxlan_ports[i] == port)
6117                         return i;
6118         }
6119
6120         return -1;
6121 }
6122
6123 static int
6124 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6125 {
6126         int  idx, ret;
6127         uint8_t filter_idx;
6128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6129
6130         idx = i40e_get_vxlan_port_idx(pf, port);
6131
6132         /* Check if port already exists */
6133         if (idx >= 0) {
6134                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6135                 return -EINVAL;
6136         }
6137
6138         /* Now check if there is space to add the new port */
6139         idx = i40e_get_vxlan_port_idx(pf, 0);
6140         if (idx < 0) {
6141                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6142                         "not adding port %d", port);
6143                 return -ENOSPC;
6144         }
6145
6146         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6147                                         &filter_idx, NULL);
6148         if (ret < 0) {
6149                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6150                 return -1;
6151         }
6152
6153         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6154                          port,  filter_idx);
6155
6156         /* New port: add it and mark its index in the bitmap */
6157         pf->vxlan_ports[idx] = port;
6158         pf->vxlan_bitmap |= (1 << idx);
6159
6160         if (!(pf->flags & I40E_FLAG_VXLAN))
6161                 pf->flags |= I40E_FLAG_VXLAN;
6162
6163         return 0;
6164 }
6165
6166 static int
6167 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6168 {
6169         int idx;
6170         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6171
6172         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6173                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6174                 return -EINVAL;
6175         }
6176
6177         idx = i40e_get_vxlan_port_idx(pf, port);
6178
6179         if (idx < 0) {
6180                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6181                 return -EINVAL;
6182         }
6183
6184         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6185                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6186                 return -1;
6187         }
6188
6189         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6190                         port, idx);
6191
6192         pf->vxlan_ports[idx] = 0;
6193         pf->vxlan_bitmap &= ~(1 << idx);
6194
6195         if (!pf->vxlan_bitmap)
6196                 pf->flags &= ~I40E_FLAG_VXLAN;
6197
6198         return 0;
6199 }
6200
6201 /* Add UDP tunneling port */
6202 static int
6203 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6204                              struct rte_eth_udp_tunnel *udp_tunnel)
6205 {
6206         int ret = 0;
6207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6208
6209         if (udp_tunnel == NULL)
6210                 return -EINVAL;
6211
6212         switch (udp_tunnel->prot_type) {
6213         case RTE_TUNNEL_TYPE_VXLAN:
6214                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6215                 break;
6216
6217         case RTE_TUNNEL_TYPE_GENEVE:
6218         case RTE_TUNNEL_TYPE_TEREDO:
6219                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6220                 ret = -1;
6221                 break;
6222
6223         default:
6224                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6225                 ret = -1;
6226                 break;
6227         }
6228
6229         return ret;
6230 }
6231
6232 /* Remove UDP tunneling port */
6233 static int
6234 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6235                              struct rte_eth_udp_tunnel *udp_tunnel)
6236 {
6237         int ret = 0;
6238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6239
6240         if (udp_tunnel == NULL)
6241                 return -EINVAL;
6242
6243         switch (udp_tunnel->prot_type) {
6244         case RTE_TUNNEL_TYPE_VXLAN:
6245                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6246                 break;
6247         case RTE_TUNNEL_TYPE_GENEVE:
6248         case RTE_TUNNEL_TYPE_TEREDO:
6249                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6250                 ret = -1;
6251                 break;
6252         default:
6253                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6254                 ret = -1;
6255                 break;
6256         }
6257
6258         return ret;
6259 }
6260
6261 /* Calculate the maximum number of contiguous PF queues that are configured */
6262 static int
6263 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6264 {
6265         struct rte_eth_dev_data *data = pf->dev_data;
6266         int i, num;
6267         struct i40e_rx_queue *rxq;
6268
6269         num = 0;
6270         for (i = 0; i < pf->lan_nb_qps; i++) {
6271                 rxq = data->rx_queues[i];
6272                 if (rxq && rxq->q_set)
6273                         num++;
6274                 else
6275                         break;
6276         }
6277
6278         return num;
6279 }
6280
6281 /* Configure RSS */
6282 static int
6283 i40e_pf_config_rss(struct i40e_pf *pf)
6284 {
6285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6286         struct rte_eth_rss_conf rss_conf;
6287         uint32_t i, lut = 0;
6288         uint16_t j, num;
6289
6290         /*
6291          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6292          * It's necessary to calulate the actual PF queues that are configured.
6293          */
6294         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6295                 num = i40e_pf_calc_configured_queues_num(pf);
6296         else
6297                 num = pf->dev_data->nb_rx_queues;
6298
6299         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6300         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6301                         num);
6302
6303         if (num == 0) {
6304                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6305                 return -ENOTSUP;
6306         }
6307
6308         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6309                 if (j == num)
6310                         j = 0;
6311                 lut = (lut << 8) | (j & ((0x1 <<
6312                         hw->func_caps.rss_table_entry_width) - 1));
6313                 if ((i & 3) == 3)
6314                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6315         }
6316
6317         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6318         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6319                 i40e_pf_disable_rss(pf);
6320                 return 0;
6321         }
6322         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6323                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6324                 /* Random default keys */
6325                 static uint32_t rss_key_default[] = {0x6b793944,
6326                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6327                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6328                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6329
6330                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6331                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6332                                                         sizeof(uint32_t);
6333         }
6334
6335         return i40e_hw_rss_hash_set(pf, &rss_conf);
6336 }
6337
6338 static int
6339 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6340                                struct rte_eth_tunnel_filter_conf *filter)
6341 {
6342         if (pf == NULL || filter == NULL) {
6343                 PMD_DRV_LOG(ERR, "Invalid parameter");
6344                 return -EINVAL;
6345         }
6346
6347         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6348                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6349                 return -EINVAL;
6350         }
6351
6352         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6353                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6354                 return -EINVAL;
6355         }
6356
6357         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6358                 (is_zero_ether_addr(&filter->outer_mac))) {
6359                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6360                 return -EINVAL;
6361         }
6362
6363         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6364                 (is_zero_ether_addr(&filter->inner_mac))) {
6365                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6366                 return -EINVAL;
6367         }
6368
6369         return 0;
6370 }
6371
6372 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6373 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6374 static int
6375 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6376 {
6377         uint32_t val, reg;
6378         int ret = -EINVAL;
6379
6380         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6381         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6382
6383         if (len == 3) {
6384                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6385         } else if (len == 4) {
6386                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6387         } else {
6388                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6389                 return ret;
6390         }
6391
6392         if (reg != val) {
6393                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6394                                                    reg, NULL);
6395                 if (ret != 0)
6396                         return ret;
6397         } else {
6398                 ret = 0;
6399         }
6400         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6401                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6402
6403         return ret;
6404 }
6405
6406 static int
6407 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6408 {
6409         int ret = -EINVAL;
6410
6411         if (!hw || !cfg)
6412                 return -EINVAL;
6413
6414         switch (cfg->cfg_type) {
6415         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6416                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6417                 break;
6418         default:
6419                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6420                 break;
6421         }
6422
6423         return ret;
6424 }
6425
6426 static int
6427 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6428                                enum rte_filter_op filter_op,
6429                                void *arg)
6430 {
6431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432         int ret = I40E_ERR_PARAM;
6433
6434         switch (filter_op) {
6435         case RTE_ETH_FILTER_SET:
6436                 ret = i40e_dev_global_config_set(hw,
6437                         (struct rte_eth_global_cfg *)arg);
6438                 break;
6439         default:
6440                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6441                 break;
6442         }
6443
6444         return ret;
6445 }
6446
6447 static int
6448 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6449                           enum rte_filter_op filter_op,
6450                           void *arg)
6451 {
6452         struct rte_eth_tunnel_filter_conf *filter;
6453         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6454         int ret = I40E_SUCCESS;
6455
6456         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6457
6458         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6459                 return I40E_ERR_PARAM;
6460
6461         switch (filter_op) {
6462         case RTE_ETH_FILTER_NOP:
6463                 if (!(pf->flags & I40E_FLAG_VXLAN))
6464                         ret = I40E_NOT_SUPPORTED;
6465                 break;
6466         case RTE_ETH_FILTER_ADD:
6467                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6468                 break;
6469         case RTE_ETH_FILTER_DELETE:
6470                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6471                 break;
6472         default:
6473                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6474                 ret = I40E_ERR_PARAM;
6475                 break;
6476         }
6477
6478         return ret;
6479 }
6480
6481 static int
6482 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6483 {
6484         int ret = 0;
6485         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6486
6487         /* RSS setup */
6488         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6489                 ret = i40e_pf_config_rss(pf);
6490         else
6491                 i40e_pf_disable_rss(pf);
6492
6493         return ret;
6494 }
6495
6496 /* Get the symmetric hash enable configurations per port */
6497 static void
6498 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6499 {
6500         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6501
6502         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6503 }
6504
6505 /* Set the symmetric hash enable configurations per port */
6506 static void
6507 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6508 {
6509         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6510
6511         if (enable > 0) {
6512                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6513                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6514                                                         "been enabled");
6515                         return;
6516                 }
6517                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6518         } else {
6519                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6520                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6521                                                         "been disabled");
6522                         return;
6523                 }
6524                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6525         }
6526         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6527         I40E_WRITE_FLUSH(hw);
6528 }
6529
6530 /*
6531  * Get global configurations of hash function type and symmetric hash enable
6532  * per flow type (pctype). Note that global configuration means it affects all
6533  * the ports on the same NIC.
6534  */
6535 static int
6536 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6537                                    struct rte_eth_hash_global_conf *g_cfg)
6538 {
6539         uint32_t reg, mask = I40E_FLOW_TYPES;
6540         uint16_t i;
6541         enum i40e_filter_pctype pctype;
6542
6543         memset(g_cfg, 0, sizeof(*g_cfg));
6544         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6545         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6546                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6547         else
6548                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6549         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6550                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6551
6552         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6553                 if (!(mask & (1UL << i)))
6554                         continue;
6555                 mask &= ~(1UL << i);
6556                 /* Bit set indicats the coresponding flow type is supported */
6557                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6558                 pctype = i40e_flowtype_to_pctype(i);
6559                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6560                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6561                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6562         }
6563
6564         return 0;
6565 }
6566
6567 static int
6568 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6569 {
6570         uint32_t i;
6571         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6572
6573         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6574                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6575                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6576                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6577                                                 g_cfg->hash_func);
6578                 return -EINVAL;
6579         }
6580
6581         /*
6582          * As i40e supports less than 32 flow types, only first 32 bits need to
6583          * be checked.
6584          */
6585         mask0 = g_cfg->valid_bit_mask[0];
6586         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6587                 if (i == 0) {
6588                         /* Check if any unsupported flow type configured */
6589                         if ((mask0 | i40e_mask) ^ i40e_mask)
6590                                 goto mask_err;
6591                 } else {
6592                         if (g_cfg->valid_bit_mask[i])
6593                                 goto mask_err;
6594                 }
6595         }
6596
6597         return 0;
6598
6599 mask_err:
6600         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6601
6602         return -EINVAL;
6603 }
6604
6605 /*
6606  * Set global configurations of hash function type and symmetric hash enable
6607  * per flow type (pctype). Note any modifying global configuration will affect
6608  * all the ports on the same NIC.
6609  */
6610 static int
6611 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6612                                    struct rte_eth_hash_global_conf *g_cfg)
6613 {
6614         int ret;
6615         uint16_t i;
6616         uint32_t reg;
6617         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6618         enum i40e_filter_pctype pctype;
6619
6620         /* Check the input parameters */
6621         ret = i40e_hash_global_config_check(g_cfg);
6622         if (ret < 0)
6623                 return ret;
6624
6625         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6626                 if (!(mask0 & (1UL << i)))
6627                         continue;
6628                 mask0 &= ~(1UL << i);
6629                 pctype = i40e_flowtype_to_pctype(i);
6630                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6631                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6632                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6633         }
6634
6635         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6636         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6637                 /* Toeplitz */
6638                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6639                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6640                                                                 "Toeplitz");
6641                         goto out;
6642                 }
6643                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6644         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6645                 /* Simple XOR */
6646                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6647                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6648                                                         "Simple XOR");
6649                         goto out;
6650                 }
6651                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6652         } else
6653                 /* Use the default, and keep it as it is */
6654                 goto out;
6655
6656         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6657
6658 out:
6659         I40E_WRITE_FLUSH(hw);
6660
6661         return 0;
6662 }
6663
6664 /**
6665  * Valid input sets for hash and flow director filters per PCTYPE
6666  */
6667 static uint64_t
6668 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6669                 enum rte_filter_type filter)
6670 {
6671         uint64_t valid;
6672
6673         static const uint64_t valid_hash_inset_table[] = {
6674                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6675                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6676                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6677                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6678                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6679                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6680                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6681                         I40E_INSET_FLEX_PAYLOAD,
6682                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6683                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6684                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6685                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6686                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6687                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6688                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6689                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6690                         I40E_INSET_FLEX_PAYLOAD,
6691                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6692                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6693                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6694                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6695                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6696                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6697                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6698                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6699                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6700                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6701                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6702                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6703                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6704                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6705                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6706                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6707                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6708                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6709                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6710                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6711                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6712                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6713                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6714                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6715                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6716                         I40E_INSET_FLEX_PAYLOAD,
6717                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6718                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6719                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6720                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6721                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6722                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6723                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6724                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6725                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6726                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6727                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6728                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6729                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6730                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6731                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6732                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6733                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6734                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6735                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6736                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6737                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6738                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6739                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6740                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6741                         I40E_INSET_FLEX_PAYLOAD,
6742                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6743                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6744                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6745                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6746                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6747                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6748                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6749                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6750                         I40E_INSET_FLEX_PAYLOAD,
6751                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6752                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6753                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6754                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6755                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6756                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6757                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6758                         I40E_INSET_FLEX_PAYLOAD,
6759                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6760                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6761                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6762                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6763                         I40E_INSET_FLEX_PAYLOAD,
6764         };
6765
6766         /**
6767          * Flow director supports only fields defined in
6768          * union rte_eth_fdir_flow.
6769          */
6770         static const uint64_t valid_fdir_inset_table[] = {
6771                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6772                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6773                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6774                 I40E_INSET_IPV4_TTL,
6775                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6776                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6777                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6778                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6779                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6780                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6781                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6782                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6783                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6784                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6785                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6786                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6787                 I40E_INSET_SCTP_VT,
6788                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6789                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6790                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6791                 I40E_INSET_IPV4_TTL,
6792                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6793                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6794                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6795                 I40E_INSET_IPV6_HOP_LIMIT,
6796                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6797                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6798                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6799                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6800                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6801                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6802                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6803                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6804                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6805                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6806                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6807                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6808                 I40E_INSET_SCTP_VT,
6809                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6810                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6811                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6812                 I40E_INSET_IPV6_HOP_LIMIT,
6813                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6814                 I40E_INSET_LAST_ETHER_TYPE,
6815         };
6816
6817         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6818                 return 0;
6819         if (filter == RTE_ETH_FILTER_HASH)
6820                 valid = valid_hash_inset_table[pctype];
6821         else
6822                 valid = valid_fdir_inset_table[pctype];
6823
6824         return valid;
6825 }
6826
6827 /**
6828  * Validate if the input set is allowed for a specific PCTYPE
6829  */
6830 static int
6831 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6832                 enum rte_filter_type filter, uint64_t inset)
6833 {
6834         uint64_t valid;
6835
6836         valid = i40e_get_valid_input_set(pctype, filter);
6837         if (inset & (~valid))
6838                 return -EINVAL;
6839
6840         return 0;
6841 }
6842
6843 /* default input set fields combination per pctype */
6844 static uint64_t
6845 i40e_get_default_input_set(uint16_t pctype)
6846 {
6847         static const uint64_t default_inset_table[] = {
6848                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6849                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6850                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6851                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6852                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6853                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6854                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6855                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6856                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6857                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6858                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6859                         I40E_INSET_SCTP_VT,
6860                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6861                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6862                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6863                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6864                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6865                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6866                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6867                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6868                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6869                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6870                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6871                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6872                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6873                         I40E_INSET_SCTP_VT,
6874                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6875                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6876                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6877                         I40E_INSET_LAST_ETHER_TYPE,
6878         };
6879
6880         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6881                 return 0;
6882
6883         return default_inset_table[pctype];
6884 }
6885
6886 /**
6887  * Parse the input set from index to logical bit masks
6888  */
6889 static int
6890 i40e_parse_input_set(uint64_t *inset,
6891                      enum i40e_filter_pctype pctype,
6892                      enum rte_eth_input_set_field *field,
6893                      uint16_t size)
6894 {
6895         uint16_t i, j;
6896         int ret = -EINVAL;
6897
6898         static const struct {
6899                 enum rte_eth_input_set_field field;
6900                 uint64_t inset;
6901         } inset_convert_table[] = {
6902                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6903                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6904                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6905                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6906                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6907                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6908                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6909                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6910                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6911                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6912                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6913                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6914                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6915                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6916                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6917                         I40E_INSET_IPV6_NEXT_HDR},
6918                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6919                         I40E_INSET_IPV6_HOP_LIMIT},
6920                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6921                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6922                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6923                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6924                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6925                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6926                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6927                         I40E_INSET_SCTP_VT},
6928                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6929                         I40E_INSET_TUNNEL_DMAC},
6930                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6931                         I40E_INSET_VLAN_TUNNEL},
6932                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6933                         I40E_INSET_TUNNEL_ID},
6934                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6935                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6936                         I40E_INSET_FLEX_PAYLOAD_W1},
6937                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6938                         I40E_INSET_FLEX_PAYLOAD_W2},
6939                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6940                         I40E_INSET_FLEX_PAYLOAD_W3},
6941                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6942                         I40E_INSET_FLEX_PAYLOAD_W4},
6943                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6944                         I40E_INSET_FLEX_PAYLOAD_W5},
6945                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6946                         I40E_INSET_FLEX_PAYLOAD_W6},
6947                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6948                         I40E_INSET_FLEX_PAYLOAD_W7},
6949                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6950                         I40E_INSET_FLEX_PAYLOAD_W8},
6951         };
6952
6953         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6954                 return ret;
6955
6956         /* Only one item allowed for default or all */
6957         if (size == 1) {
6958                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6959                         *inset = i40e_get_default_input_set(pctype);
6960                         return 0;
6961                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6962                         *inset = I40E_INSET_NONE;
6963                         return 0;
6964                 }
6965         }
6966
6967         for (i = 0, *inset = 0; i < size; i++) {
6968                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6969                         if (field[i] == inset_convert_table[j].field) {
6970                                 *inset |= inset_convert_table[j].inset;
6971                                 break;
6972                         }
6973                 }
6974
6975                 /* It contains unsupported input set, return immediately */
6976                 if (j == RTE_DIM(inset_convert_table))
6977                         return ret;
6978         }
6979
6980         return 0;
6981 }
6982
6983 /**
6984  * Translate the input set from bit masks to register aware bit masks
6985  * and vice versa
6986  */
6987 static uint64_t
6988 i40e_translate_input_set_reg(uint64_t input)
6989 {
6990         uint64_t val = 0;
6991         uint16_t i;
6992
6993         static const struct {
6994                 uint64_t inset;
6995                 uint64_t inset_reg;
6996         } inset_map[] = {
6997                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6998                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6999                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7000                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7001                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7002                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7003                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7004                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7005                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7006                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7007                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7008                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7009                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7010                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7011                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7012                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7013                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7014                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7015                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7016                 {I40E_INSET_TUNNEL_DMAC,
7017                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7018                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7019                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7020                 {I40E_INSET_TUNNEL_SRC_PORT,
7021                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7022                 {I40E_INSET_TUNNEL_DST_PORT,
7023                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7024                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7025                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7026                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7027                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7028                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7029                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7030                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7031                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7032                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7033         };
7034
7035         if (input == 0)
7036                 return val;
7037
7038         /* Translate input set to register aware inset */
7039         for (i = 0; i < RTE_DIM(inset_map); i++) {
7040                 if (input & inset_map[i].inset)
7041                         val |= inset_map[i].inset_reg;
7042         }
7043
7044         return val;
7045 }
7046
7047 static int
7048 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7049 {
7050         uint8_t i, idx = 0;
7051         uint64_t inset_need_mask = inset;
7052
7053         static const struct {
7054                 uint64_t inset;
7055                 uint32_t mask;
7056         } inset_mask_map[] = {
7057                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7058                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7059                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7060                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7061                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7062                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7063                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7064                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7065         };
7066
7067         if (!inset || !mask || !nb_elem)
7068                 return 0;
7069
7070         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7071                 /* Clear the inset bit, if no MASK is required,
7072                  * for example proto + ttl
7073                  */
7074                 if ((inset & inset_mask_map[i].inset) ==
7075                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7076                         inset_need_mask &= ~inset_mask_map[i].inset;
7077                 if (!inset_need_mask)
7078                         return 0;
7079         }
7080         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7081                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7082                     inset_mask_map[i].inset) {
7083                         if (idx >= nb_elem) {
7084                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7085                                 return -EINVAL;
7086                         }
7087                         mask[idx] = inset_mask_map[i].mask;
7088                         idx++;
7089                 }
7090         }
7091
7092         return idx;
7093 }
7094
7095 static void
7096 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7097 {
7098         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7099
7100         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7101         if (reg != val)
7102                 i40e_write_rx_ctl(hw, addr, val);
7103         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7104                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7105 }
7106
7107 static void
7108 i40e_filter_input_set_init(struct i40e_pf *pf)
7109 {
7110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111         enum i40e_filter_pctype pctype;
7112         uint64_t input_set, inset_reg;
7113         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7114         int num, i;
7115
7116         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7117              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7118                 if (!I40E_VALID_PCTYPE(pctype))
7119                         continue;
7120                 input_set = i40e_get_default_input_set(pctype);
7121
7122                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7123                                                    I40E_INSET_MASK_NUM_REG);
7124                 if (num < 0)
7125                         return;
7126                 inset_reg = i40e_translate_input_set_reg(input_set);
7127
7128                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7129                                       (uint32_t)(inset_reg & UINT32_MAX));
7130                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7131                                      (uint32_t)((inset_reg >>
7132                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7133                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7134                                       (uint32_t)(inset_reg & UINT32_MAX));
7135                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7136                                      (uint32_t)((inset_reg >>
7137                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7138
7139                 for (i = 0; i < num; i++) {
7140                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7141                                              mask_reg[i]);
7142                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7143                                              mask_reg[i]);
7144                 }
7145                 /*clear unused mask registers of the pctype */
7146                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7147                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7148                                              0);
7149                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7150                                              0);
7151                 }
7152                 I40E_WRITE_FLUSH(hw);
7153
7154                 /* store the default input set */
7155                 pf->hash_input_set[pctype] = input_set;
7156                 pf->fdir.input_set[pctype] = input_set;
7157         }
7158 }
7159
7160 int
7161 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7162                          struct rte_eth_input_set_conf *conf)
7163 {
7164         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7165         enum i40e_filter_pctype pctype;
7166         uint64_t input_set, inset_reg = 0;
7167         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7168         int ret, i, num;
7169
7170         if (!conf) {
7171                 PMD_DRV_LOG(ERR, "Invalid pointer");
7172                 return -EFAULT;
7173         }
7174         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7175             conf->op != RTE_ETH_INPUT_SET_ADD) {
7176                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7177                 return -EINVAL;
7178         }
7179
7180         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7181         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7182                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7183                             conf->flow_type);
7184                 return -EINVAL;
7185         }
7186
7187         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7188                                    conf->inset_size);
7189         if (ret) {
7190                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7191                 return -EINVAL;
7192         }
7193         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7194                                     input_set) != 0) {
7195                 PMD_DRV_LOG(ERR, "Invalid input set");
7196                 return -EINVAL;
7197         }
7198         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7199                 /* get inset value in register */
7200                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7201                 inset_reg <<= I40E_32_BIT_WIDTH;
7202                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7203                 input_set |= pf->hash_input_set[pctype];
7204         }
7205         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7206                                            I40E_INSET_MASK_NUM_REG);
7207         if (num < 0)
7208                 return -EINVAL;
7209
7210         inset_reg |= i40e_translate_input_set_reg(input_set);
7211
7212         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7213                               (uint32_t)(inset_reg & UINT32_MAX));
7214         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7215                              (uint32_t)((inset_reg >>
7216                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7217
7218         for (i = 0; i < num; i++)
7219                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7220                                      mask_reg[i]);
7221         /*clear unused mask registers of the pctype */
7222         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7223                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7224                                      0);
7225         I40E_WRITE_FLUSH(hw);
7226
7227         pf->hash_input_set[pctype] = input_set;
7228         return 0;
7229 }
7230
7231 int
7232 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7233                          struct rte_eth_input_set_conf *conf)
7234 {
7235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7236         enum i40e_filter_pctype pctype;
7237         uint64_t input_set, inset_reg = 0;
7238         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7239         int ret, i, num;
7240
7241         if (!hw || !conf) {
7242                 PMD_DRV_LOG(ERR, "Invalid pointer");
7243                 return -EFAULT;
7244         }
7245         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7246             conf->op != RTE_ETH_INPUT_SET_ADD) {
7247                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7248                 return -EINVAL;
7249         }
7250
7251         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7252         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7253                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7254                             conf->flow_type);
7255                 return -EINVAL;
7256         }
7257         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7258                                    conf->inset_size);
7259         if (ret) {
7260                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7261                 return -EINVAL;
7262         }
7263         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7264                                     input_set) != 0) {
7265                 PMD_DRV_LOG(ERR, "Invalid input set");
7266                 return -EINVAL;
7267         }
7268
7269         /* get inset value in register */
7270         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7271         inset_reg <<= I40E_32_BIT_WIDTH;
7272         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7273
7274         /* Can not change the inset reg for flex payload for fdir,
7275          * it is done by writing I40E_PRTQF_FD_FLXINSET
7276          * in i40e_set_flex_mask_on_pctype.
7277          */
7278         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7279                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7280         else
7281                 input_set |= pf->fdir.input_set[pctype];
7282         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7283                                            I40E_INSET_MASK_NUM_REG);
7284         if (num < 0)
7285                 return -EINVAL;
7286
7287         inset_reg |= i40e_translate_input_set_reg(input_set);
7288
7289         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7290                               (uint32_t)(inset_reg & UINT32_MAX));
7291         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7292                              (uint32_t)((inset_reg >>
7293                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7294
7295         for (i = 0; i < num; i++)
7296                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7297                                      mask_reg[i]);
7298         /*clear unused mask registers of the pctype */
7299         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7300                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7301                                      0);
7302         I40E_WRITE_FLUSH(hw);
7303
7304         pf->fdir.input_set[pctype] = input_set;
7305         return 0;
7306 }
7307
7308 static int
7309 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7310 {
7311         int ret = 0;
7312
7313         if (!hw || !info) {
7314                 PMD_DRV_LOG(ERR, "Invalid pointer");
7315                 return -EFAULT;
7316         }
7317
7318         switch (info->info_type) {
7319         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7320                 i40e_get_symmetric_hash_enable_per_port(hw,
7321                                         &(info->info.enable));
7322                 break;
7323         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7324                 ret = i40e_get_hash_filter_global_config(hw,
7325                                 &(info->info.global_conf));
7326                 break;
7327         default:
7328                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7329                                                         info->info_type);
7330                 ret = -EINVAL;
7331                 break;
7332         }
7333
7334         return ret;
7335 }
7336
7337 static int
7338 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7339 {
7340         int ret = 0;
7341
7342         if (!hw || !info) {
7343                 PMD_DRV_LOG(ERR, "Invalid pointer");
7344                 return -EFAULT;
7345         }
7346
7347         switch (info->info_type) {
7348         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7349                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7350                 break;
7351         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7352                 ret = i40e_set_hash_filter_global_config(hw,
7353                                 &(info->info.global_conf));
7354                 break;
7355         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7356                 ret = i40e_hash_filter_inset_select(hw,
7357                                                &(info->info.input_set_conf));
7358                 break;
7359
7360         default:
7361                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7362                                                         info->info_type);
7363                 ret = -EINVAL;
7364                 break;
7365         }
7366
7367         return ret;
7368 }
7369
7370 /* Operations for hash function */
7371 static int
7372 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7373                       enum rte_filter_op filter_op,
7374                       void *arg)
7375 {
7376         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7377         int ret = 0;
7378
7379         switch (filter_op) {
7380         case RTE_ETH_FILTER_NOP:
7381                 break;
7382         case RTE_ETH_FILTER_GET:
7383                 ret = i40e_hash_filter_get(hw,
7384                         (struct rte_eth_hash_filter_info *)arg);
7385                 break;
7386         case RTE_ETH_FILTER_SET:
7387                 ret = i40e_hash_filter_set(hw,
7388                         (struct rte_eth_hash_filter_info *)arg);
7389                 break;
7390         default:
7391                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7392                                                                 filter_op);
7393                 ret = -ENOTSUP;
7394                 break;
7395         }
7396
7397         return ret;
7398 }
7399
7400 /*
7401  * Configure ethertype filter, which can director packet by filtering
7402  * with mac address and ether_type or only ether_type
7403  */
7404 static int
7405 i40e_ethertype_filter_set(struct i40e_pf *pf,
7406                         struct rte_eth_ethertype_filter *filter,
7407                         bool add)
7408 {
7409         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7410         struct i40e_control_filter_stats stats;
7411         uint16_t flags = 0;
7412         int ret;
7413
7414         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7415                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7416                 return -EINVAL;
7417         }
7418         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7419                 filter->ether_type == ETHER_TYPE_IPv6) {
7420                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7421                         " control packet filter.", filter->ether_type);
7422                 return -EINVAL;
7423         }
7424         if (filter->ether_type == ETHER_TYPE_VLAN)
7425                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7426                         " not supported.");
7427
7428         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7429                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7430         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7431                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7432         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7433
7434         memset(&stats, 0, sizeof(stats));
7435         ret = i40e_aq_add_rem_control_packet_filter(hw,
7436                         filter->mac_addr.addr_bytes,
7437                         filter->ether_type, flags,
7438                         pf->main_vsi->seid,
7439                         filter->queue, add, &stats, NULL);
7440
7441         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7442                          " mac_etype_used = %u, etype_used = %u,"
7443                          " mac_etype_free = %u, etype_free = %u\n",
7444                          ret, stats.mac_etype_used, stats.etype_used,
7445                          stats.mac_etype_free, stats.etype_free);
7446         if (ret < 0)
7447                 return -ENOSYS;
7448         return 0;
7449 }
7450
7451 /*
7452  * Handle operations for ethertype filter.
7453  */
7454 static int
7455 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7456                                 enum rte_filter_op filter_op,
7457                                 void *arg)
7458 {
7459         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7460         int ret = 0;
7461
7462         if (filter_op == RTE_ETH_FILTER_NOP)
7463                 return ret;
7464
7465         if (arg == NULL) {
7466                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7467                             filter_op);
7468                 return -EINVAL;
7469         }
7470
7471         switch (filter_op) {
7472         case RTE_ETH_FILTER_ADD:
7473                 ret = i40e_ethertype_filter_set(pf,
7474                         (struct rte_eth_ethertype_filter *)arg,
7475                         TRUE);
7476                 break;
7477         case RTE_ETH_FILTER_DELETE:
7478                 ret = i40e_ethertype_filter_set(pf,
7479                         (struct rte_eth_ethertype_filter *)arg,
7480                         FALSE);
7481                 break;
7482         default:
7483                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7484                 ret = -ENOSYS;
7485                 break;
7486         }
7487         return ret;
7488 }
7489
7490 static int
7491 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7492                      enum rte_filter_type filter_type,
7493                      enum rte_filter_op filter_op,
7494                      void *arg)
7495 {
7496         int ret = 0;
7497
7498         if (dev == NULL)
7499                 return -EINVAL;
7500
7501         switch (filter_type) {
7502         case RTE_ETH_FILTER_NONE:
7503                 /* For global configuration */
7504                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7505                 break;
7506         case RTE_ETH_FILTER_HASH:
7507                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7508                 break;
7509         case RTE_ETH_FILTER_MACVLAN:
7510                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7511                 break;
7512         case RTE_ETH_FILTER_ETHERTYPE:
7513                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7514                 break;
7515         case RTE_ETH_FILTER_TUNNEL:
7516                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7517                 break;
7518         case RTE_ETH_FILTER_FDIR:
7519                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7520                 break;
7521         default:
7522                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7523                                                         filter_type);
7524                 ret = -EINVAL;
7525                 break;
7526         }
7527
7528         return ret;
7529 }
7530
7531 /*
7532  * Check and enable Extended Tag.
7533  * Enabling Extended Tag is important for 40G performance.
7534  */
7535 static void
7536 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7537 {
7538         uint32_t buf = 0;
7539         int ret;
7540
7541         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7542                                       PCI_DEV_CAP_REG);
7543         if (ret < 0) {
7544                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7545                             PCI_DEV_CAP_REG);
7546                 return;
7547         }
7548         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7549                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7550                 return;
7551         }
7552
7553         buf = 0;
7554         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7555                                       PCI_DEV_CTRL_REG);
7556         if (ret < 0) {
7557                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7558                             PCI_DEV_CTRL_REG);
7559                 return;
7560         }
7561         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7562                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7563                 return;
7564         }
7565         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7566         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7567                                        PCI_DEV_CTRL_REG);
7568         if (ret < 0) {
7569                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7570                             PCI_DEV_CTRL_REG);
7571                 return;
7572         }
7573 }
7574
7575 /*
7576  * As some registers wouldn't be reset unless a global hardware reset,
7577  * hardware initialization is needed to put those registers into an
7578  * expected initial state.
7579  */
7580 static void
7581 i40e_hw_init(struct rte_eth_dev *dev)
7582 {
7583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7584
7585         i40e_enable_extended_tag(dev);
7586
7587         /* clear the PF Queue Filter control register */
7588         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7589
7590         /* Disable symmetric hash per port */
7591         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7592 }
7593
7594 enum i40e_filter_pctype
7595 i40e_flowtype_to_pctype(uint16_t flow_type)
7596 {
7597         static const enum i40e_filter_pctype pctype_table[] = {
7598                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7599                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7600                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7601                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7602                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7603                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7604                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7605                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7606                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7607                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7608                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7609                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7610                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7611                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7612                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7613                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7614                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7615                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7616                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7617         };
7618
7619         return pctype_table[flow_type];
7620 }
7621
7622 uint16_t
7623 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7624 {
7625         static const uint16_t flowtype_table[] = {
7626                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7627                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7628                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7629                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7630                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7631                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7632                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7633                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7634                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7635                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7636                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7637                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7638                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7639                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7641                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7642                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7643                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7644                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7645         };
7646
7647         return flowtype_table[pctype];
7648 }
7649
7650 /*
7651  * On X710, performance number is far from the expectation on recent firmware
7652  * versions; on XL710, performance number is also far from the expectation on
7653  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7654  * mode is enabled and port MAC address is equal to the packet destination MAC
7655  * address. The fix for this issue may not be integrated in the following
7656  * firmware version. So the workaround in software driver is needed. It needs
7657  * to modify the initial values of 3 internal only registers for both X710 and
7658  * XL710. Note that the values for X710 or XL710 could be different, and the
7659  * workaround can be removed when it is fixed in firmware in the future.
7660  */
7661
7662 /* For both X710 and XL710 */
7663 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7664 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7665
7666 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7667 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7668
7669 /* For X710 */
7670 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7671 /* For XL710 */
7672 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7673 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7674
7675 static void
7676 i40e_configure_registers(struct i40e_hw *hw)
7677 {
7678         static struct {
7679                 uint32_t addr;
7680                 uint64_t val;
7681         } reg_table[] = {
7682                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7683                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7684                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7685         };
7686         uint64_t reg;
7687         uint32_t i;
7688         int ret;
7689
7690         for (i = 0; i < RTE_DIM(reg_table); i++) {
7691                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7692                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7693                                 reg_table[i].val =
7694                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7695                         else /* For X710 */
7696                                 reg_table[i].val =
7697                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7698                 }
7699
7700                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7701                                                         &reg, NULL);
7702                 if (ret < 0) {
7703                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7704                                                         reg_table[i].addr);
7705                         break;
7706                 }
7707                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7708                                                 reg_table[i].addr, reg);
7709                 if (reg == reg_table[i].val)
7710                         continue;
7711
7712                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7713                                                 reg_table[i].val, NULL);
7714                 if (ret < 0) {
7715                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7716                                 "address of 0x%"PRIx32, reg_table[i].val,
7717                                                         reg_table[i].addr);
7718                         break;
7719                 }
7720                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7721                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7722         }
7723 }
7724
7725 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7726 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7727 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7728 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7729 static int
7730 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7731 {
7732         uint32_t reg;
7733         int ret;
7734
7735         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7736                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7737                 return -EINVAL;
7738         }
7739
7740         /* Configure for double VLAN RX stripping */
7741         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7742         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7743                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7744                 ret = i40e_aq_debug_write_register(hw,
7745                                                    I40E_VSI_TSR(vsi->vsi_id),
7746                                                    reg, NULL);
7747                 if (ret < 0) {
7748                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7749                                     vsi->vsi_id);
7750                         return I40E_ERR_CONFIG;
7751                 }
7752         }
7753
7754         /* Configure for double VLAN TX insertion */
7755         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7756         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7757                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7758                 ret = i40e_aq_debug_write_register(hw,
7759                                                    I40E_VSI_L2TAGSTXVALID(
7760                                                    vsi->vsi_id), reg, NULL);
7761                 if (ret < 0) {
7762                         PMD_DRV_LOG(ERR, "Failed to update "
7763                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7764                         return I40E_ERR_CONFIG;
7765                 }
7766         }
7767
7768         return 0;
7769 }
7770
7771 /**
7772  * i40e_aq_add_mirror_rule
7773  * @hw: pointer to the hardware structure
7774  * @seid: VEB seid to add mirror rule to
7775  * @dst_id: destination vsi seid
7776  * @entries: Buffer which contains the entities to be mirrored
7777  * @count: number of entities contained in the buffer
7778  * @rule_id:the rule_id of the rule to be added
7779  *
7780  * Add a mirror rule for a given veb.
7781  *
7782  **/
7783 static enum i40e_status_code
7784 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7785                         uint16_t seid, uint16_t dst_id,
7786                         uint16_t rule_type, uint16_t *entries,
7787                         uint16_t count, uint16_t *rule_id)
7788 {
7789         struct i40e_aq_desc desc;
7790         struct i40e_aqc_add_delete_mirror_rule cmd;
7791         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7792                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7793                 &desc.params.raw;
7794         uint16_t buff_len;
7795         enum i40e_status_code status;
7796
7797         i40e_fill_default_direct_cmd_desc(&desc,
7798                                           i40e_aqc_opc_add_mirror_rule);
7799         memset(&cmd, 0, sizeof(cmd));
7800
7801         buff_len = sizeof(uint16_t) * count;
7802         desc.datalen = rte_cpu_to_le_16(buff_len);
7803         if (buff_len > 0)
7804                 desc.flags |= rte_cpu_to_le_16(
7805                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7806         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7807                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7808         cmd.num_entries = rte_cpu_to_le_16(count);
7809         cmd.seid = rte_cpu_to_le_16(seid);
7810         cmd.destination = rte_cpu_to_le_16(dst_id);
7811
7812         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7813         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7814         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7815                          "rule_id = %u"
7816                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7817                          hw->aq.asq_last_status, resp->rule_id,
7818                          resp->mirror_rules_used, resp->mirror_rules_free);
7819         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7820
7821         return status;
7822 }
7823
7824 /**
7825  * i40e_aq_del_mirror_rule
7826  * @hw: pointer to the hardware structure
7827  * @seid: VEB seid to add mirror rule to
7828  * @entries: Buffer which contains the entities to be mirrored
7829  * @count: number of entities contained in the buffer
7830  * @rule_id:the rule_id of the rule to be delete
7831  *
7832  * Delete a mirror rule for a given veb.
7833  *
7834  **/
7835 static enum i40e_status_code
7836 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7837                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7838                 uint16_t count, uint16_t rule_id)
7839 {
7840         struct i40e_aq_desc desc;
7841         struct i40e_aqc_add_delete_mirror_rule cmd;
7842         uint16_t buff_len = 0;
7843         enum i40e_status_code status;
7844         void *buff = NULL;
7845
7846         i40e_fill_default_direct_cmd_desc(&desc,
7847                                           i40e_aqc_opc_delete_mirror_rule);
7848         memset(&cmd, 0, sizeof(cmd));
7849         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7850                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7851                                                           I40E_AQ_FLAG_RD));
7852                 cmd.num_entries = count;
7853                 buff_len = sizeof(uint16_t) * count;
7854                 desc.datalen = rte_cpu_to_le_16(buff_len);
7855                 buff = (void *)entries;
7856         } else
7857                 /* rule id is filled in destination field for deleting mirror rule */
7858                 cmd.destination = rte_cpu_to_le_16(rule_id);
7859
7860         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7861                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7862         cmd.seid = rte_cpu_to_le_16(seid);
7863
7864         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7865         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7866
7867         return status;
7868 }
7869
7870 /**
7871  * i40e_mirror_rule_set
7872  * @dev: pointer to the hardware structure
7873  * @mirror_conf: mirror rule info
7874  * @sw_id: mirror rule's sw_id
7875  * @on: enable/disable
7876  *
7877  * set a mirror rule.
7878  *
7879  **/
7880 static int
7881 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7882                         struct rte_eth_mirror_conf *mirror_conf,
7883                         uint8_t sw_id, uint8_t on)
7884 {
7885         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7888         struct i40e_mirror_rule *parent = NULL;
7889         uint16_t seid, dst_seid, rule_id;
7890         uint16_t i, j = 0;
7891         int ret;
7892
7893         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7894
7895         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7896                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7897                         " without veb or vfs.");
7898                 return -ENOSYS;
7899         }
7900         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7901                 PMD_DRV_LOG(ERR, "mirror table is full.");
7902                 return -ENOSPC;
7903         }
7904         if (mirror_conf->dst_pool > pf->vf_num) {
7905                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7906                                  mirror_conf->dst_pool);
7907                 return -EINVAL;
7908         }
7909
7910         seid = pf->main_vsi->veb->seid;
7911
7912         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7913                 if (sw_id <= it->index) {
7914                         mirr_rule = it;
7915                         break;
7916                 }
7917                 parent = it;
7918         }
7919         if (mirr_rule && sw_id == mirr_rule->index) {
7920                 if (on) {
7921                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7922                         return -EEXIST;
7923                 } else {
7924                         ret = i40e_aq_del_mirror_rule(hw, seid,
7925                                         mirr_rule->rule_type,
7926                                         mirr_rule->entries,
7927                                         mirr_rule->num_entries, mirr_rule->id);
7928                         if (ret < 0) {
7929                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7930                                                    " ret = %d, aq_err = %d.",
7931                                                    ret, hw->aq.asq_last_status);
7932                                 return -ENOSYS;
7933                         }
7934                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7935                         rte_free(mirr_rule);
7936                         pf->nb_mirror_rule--;
7937                         return 0;
7938                 }
7939         } else if (!on) {
7940                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7941                 return -ENOENT;
7942         }
7943
7944         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7945                                 sizeof(struct i40e_mirror_rule) , 0);
7946         if (!mirr_rule) {
7947                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7948                 return I40E_ERR_NO_MEMORY;
7949         }
7950         switch (mirror_conf->rule_type) {
7951         case ETH_MIRROR_VLAN:
7952                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7953                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7954                                 mirr_rule->entries[j] =
7955                                         mirror_conf->vlan.vlan_id[i];
7956                                 j++;
7957                         }
7958                 }
7959                 if (j == 0) {
7960                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7961                         rte_free(mirr_rule);
7962                         return -EINVAL;
7963                 }
7964                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7965                 break;
7966         case ETH_MIRROR_VIRTUAL_POOL_UP:
7967         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7968                 /* check if the specified pool bit is out of range */
7969                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7970                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7971                         rte_free(mirr_rule);
7972                         return -EINVAL;
7973                 }
7974                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7975                         if (mirror_conf->pool_mask & (1ULL << i)) {
7976                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7977                                 j++;
7978                         }
7979                 }
7980                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7981                         /* add pf vsi to entries */
7982                         mirr_rule->entries[j] = pf->main_vsi_seid;
7983                         j++;
7984                 }
7985                 if (j == 0) {
7986                         PMD_DRV_LOG(ERR, "pool is not specified.");
7987                         rte_free(mirr_rule);
7988                         return -EINVAL;
7989                 }
7990                 /* egress and ingress in aq commands means from switch but not port */
7991                 mirr_rule->rule_type =
7992                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7993                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7994                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7995                 break;
7996         case ETH_MIRROR_UPLINK_PORT:
7997                 /* egress and ingress in aq commands means from switch but not port*/
7998                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7999                 break;
8000         case ETH_MIRROR_DOWNLINK_PORT:
8001                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8002                 break;
8003         default:
8004                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8005                         mirror_conf->rule_type);
8006                 rte_free(mirr_rule);
8007                 return -EINVAL;
8008         }
8009
8010         /* If the dst_pool is equal to vf_num, consider it as PF */
8011         if (mirror_conf->dst_pool == pf->vf_num)
8012                 dst_seid = pf->main_vsi_seid;
8013         else
8014                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8015
8016         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8017                                       mirr_rule->rule_type, mirr_rule->entries,
8018                                       j, &rule_id);
8019         if (ret < 0) {
8020                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8021                                    " ret = %d, aq_err = %d.",
8022                                    ret, hw->aq.asq_last_status);
8023                 rte_free(mirr_rule);
8024                 return -ENOSYS;
8025         }
8026
8027         mirr_rule->index = sw_id;
8028         mirr_rule->num_entries = j;
8029         mirr_rule->id = rule_id;
8030         mirr_rule->dst_vsi_seid = dst_seid;
8031
8032         if (parent)
8033                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8034         else
8035                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8036
8037         pf->nb_mirror_rule++;
8038         return 0;
8039 }
8040
8041 /**
8042  * i40e_mirror_rule_reset
8043  * @dev: pointer to the device
8044  * @sw_id: mirror rule's sw_id
8045  *
8046  * reset a mirror rule.
8047  *
8048  **/
8049 static int
8050 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8051 {
8052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8054         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8055         uint16_t seid;
8056         int ret;
8057
8058         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8059
8060         seid = pf->main_vsi->veb->seid;
8061
8062         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8063                 if (sw_id == it->index) {
8064                         mirr_rule = it;
8065                         break;
8066                 }
8067         }
8068         if (mirr_rule) {
8069                 ret = i40e_aq_del_mirror_rule(hw, seid,
8070                                 mirr_rule->rule_type,
8071                                 mirr_rule->entries,
8072                                 mirr_rule->num_entries, mirr_rule->id);
8073                 if (ret < 0) {
8074                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8075                                            " status = %d, aq_err = %d.",
8076                                            ret, hw->aq.asq_last_status);
8077                         return -ENOSYS;
8078                 }
8079                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8080                 rte_free(mirr_rule);
8081                 pf->nb_mirror_rule--;
8082         } else {
8083                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8084                 return -ENOENT;
8085         }
8086         return 0;
8087 }
8088
8089 static uint64_t
8090 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8091 {
8092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093         uint64_t systim_cycles;
8094
8095         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8096         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8097                         << 32;
8098
8099         return systim_cycles;
8100 }
8101
8102 static uint64_t
8103 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8104 {
8105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106         uint64_t rx_tstamp;
8107
8108         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8109         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8110                         << 32;
8111
8112         return rx_tstamp;
8113 }
8114
8115 static uint64_t
8116 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8117 {
8118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119         uint64_t tx_tstamp;
8120
8121         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8122         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8123                         << 32;
8124
8125         return tx_tstamp;
8126 }
8127
8128 static void
8129 i40e_start_timecounters(struct rte_eth_dev *dev)
8130 {
8131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132         struct i40e_adapter *adapter =
8133                         (struct i40e_adapter *)dev->data->dev_private;
8134         struct rte_eth_link link;
8135         uint32_t tsync_inc_l;
8136         uint32_t tsync_inc_h;
8137
8138         /* Get current link speed. */
8139         memset(&link, 0, sizeof(link));
8140         i40e_dev_link_update(dev, 1);
8141         rte_i40e_dev_atomic_read_link_status(dev, &link);
8142
8143         switch (link.link_speed) {
8144         case ETH_LINK_SPEED_40G:
8145                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8146                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8147                 break;
8148         case ETH_LINK_SPEED_10G:
8149                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8150                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8151                 break;
8152         case ETH_LINK_SPEED_1000:
8153                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8154                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8155                 break;
8156         default:
8157                 tsync_inc_l = 0x0;
8158                 tsync_inc_h = 0x0;
8159         }
8160
8161         /* Set the timesync increment value. */
8162         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8163         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8164
8165         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8166         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8167         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8168
8169         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8170         adapter->systime_tc.cc_shift = 0;
8171         adapter->systime_tc.nsec_mask = 0;
8172
8173         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8174         adapter->rx_tstamp_tc.cc_shift = 0;
8175         adapter->rx_tstamp_tc.nsec_mask = 0;
8176
8177         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8178         adapter->tx_tstamp_tc.cc_shift = 0;
8179         adapter->tx_tstamp_tc.nsec_mask = 0;
8180 }
8181
8182 static int
8183 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8184 {
8185         struct i40e_adapter *adapter =
8186                         (struct i40e_adapter *)dev->data->dev_private;
8187
8188         adapter->systime_tc.nsec += delta;
8189         adapter->rx_tstamp_tc.nsec += delta;
8190         adapter->tx_tstamp_tc.nsec += delta;
8191
8192         return 0;
8193 }
8194
8195 static int
8196 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8197 {
8198         uint64_t ns;
8199         struct i40e_adapter *adapter =
8200                         (struct i40e_adapter *)dev->data->dev_private;
8201
8202         ns = rte_timespec_to_ns(ts);
8203
8204         /* Set the timecounters to a new value. */
8205         adapter->systime_tc.nsec = ns;
8206         adapter->rx_tstamp_tc.nsec = ns;
8207         adapter->tx_tstamp_tc.nsec = ns;
8208
8209         return 0;
8210 }
8211
8212 static int
8213 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8214 {
8215         uint64_t ns, systime_cycles;
8216         struct i40e_adapter *adapter =
8217                         (struct i40e_adapter *)dev->data->dev_private;
8218
8219         systime_cycles = i40e_read_systime_cyclecounter(dev);
8220         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8221         *ts = rte_ns_to_timespec(ns);
8222
8223         return 0;
8224 }
8225
8226 static int
8227 i40e_timesync_enable(struct rte_eth_dev *dev)
8228 {
8229         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8230         uint32_t tsync_ctl_l;
8231         uint32_t tsync_ctl_h;
8232
8233         /* Stop the timesync system time. */
8234         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8235         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8236         /* Reset the timesync system time value. */
8237         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8238         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8239
8240         i40e_start_timecounters(dev);
8241
8242         /* Clear timesync registers. */
8243         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8244         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8245         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8246         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8247         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8248         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8249
8250         /* Enable timestamping of PTP packets. */
8251         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8252         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8253
8254         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8255         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8256         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8257
8258         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8259         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8260
8261         return 0;
8262 }
8263
8264 static int
8265 i40e_timesync_disable(struct rte_eth_dev *dev)
8266 {
8267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8268         uint32_t tsync_ctl_l;
8269         uint32_t tsync_ctl_h;
8270
8271         /* Disable timestamping of transmitted PTP packets. */
8272         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8273         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8274
8275         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8276         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8277
8278         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8279         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8280
8281         /* Reset the timesync increment value. */
8282         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8283         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8284
8285         return 0;
8286 }
8287
8288 static int
8289 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8290                                 struct timespec *timestamp, uint32_t flags)
8291 {
8292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8293         struct i40e_adapter *adapter =
8294                 (struct i40e_adapter *)dev->data->dev_private;
8295
8296         uint32_t sync_status;
8297         uint32_t index = flags & 0x03;
8298         uint64_t rx_tstamp_cycles;
8299         uint64_t ns;
8300
8301         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8302         if ((sync_status & (1 << index)) == 0)
8303                 return -EINVAL;
8304
8305         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8306         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8307         *timestamp = rte_ns_to_timespec(ns);
8308
8309         return 0;
8310 }
8311
8312 static int
8313 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8314                                 struct timespec *timestamp)
8315 {
8316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8317         struct i40e_adapter *adapter =
8318                 (struct i40e_adapter *)dev->data->dev_private;
8319
8320         uint32_t sync_status;
8321         uint64_t tx_tstamp_cycles;
8322         uint64_t ns;
8323
8324         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8325         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8326                 return -EINVAL;
8327
8328         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8329         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8330         *timestamp = rte_ns_to_timespec(ns);
8331
8332         return 0;
8333 }
8334
8335 /*
8336  * i40e_parse_dcb_configure - parse dcb configure from user
8337  * @dev: the device being configured
8338  * @dcb_cfg: pointer of the result of parse
8339  * @*tc_map: bit map of enabled traffic classes
8340  *
8341  * Returns 0 on success, negative value on failure
8342  */
8343 static int
8344 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8345                          struct i40e_dcbx_config *dcb_cfg,
8346                          uint8_t *tc_map)
8347 {
8348         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8349         uint8_t i, tc_bw, bw_lf;
8350
8351         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8352
8353         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8354         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8355                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8356                 return -EINVAL;
8357         }
8358
8359         /* assume each tc has the same bw */
8360         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8361         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8362                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8363         /* to ensure the sum of tcbw is equal to 100 */
8364         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8365         for (i = 0; i < bw_lf; i++)
8366                 dcb_cfg->etscfg.tcbwtable[i]++;
8367
8368         /* assume each tc has the same Transmission Selection Algorithm */
8369         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8370                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8371
8372         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8373                 dcb_cfg->etscfg.prioritytable[i] =
8374                                 dcb_rx_conf->dcb_tc[i];
8375
8376         /* FW needs one App to configure HW */
8377         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8378         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8379         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8380         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8381
8382         if (dcb_rx_conf->nb_tcs == 0)
8383                 *tc_map = 1; /* tc0 only */
8384         else
8385                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8386
8387         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8388                 dcb_cfg->pfc.willing = 0;
8389                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8390                 dcb_cfg->pfc.pfcenable = *tc_map;
8391         }
8392         return 0;
8393 }
8394
8395
8396 static enum i40e_status_code
8397 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8398                               struct i40e_aqc_vsi_properties_data *info,
8399                               uint8_t enabled_tcmap)
8400 {
8401         enum i40e_status_code ret;
8402         int i, total_tc = 0;
8403         uint16_t qpnum_per_tc, bsf, qp_idx;
8404         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8405         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8406         uint16_t used_queues;
8407
8408         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8409         if (ret != I40E_SUCCESS)
8410                 return ret;
8411
8412         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8413                 if (enabled_tcmap & (1 << i))
8414                         total_tc++;
8415         }
8416         if (total_tc == 0)
8417                 total_tc = 1;
8418         vsi->enabled_tc = enabled_tcmap;
8419
8420         /* different VSI has different queues assigned */
8421         if (vsi->type == I40E_VSI_MAIN)
8422                 used_queues = dev_data->nb_rx_queues -
8423                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8424         else if (vsi->type == I40E_VSI_VMDQ2)
8425                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8426         else {
8427                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8428                 return I40E_ERR_NO_AVAILABLE_VSI;
8429         }
8430
8431         qpnum_per_tc = used_queues / total_tc;
8432         /* Number of queues per enabled TC */
8433         if (qpnum_per_tc == 0) {
8434                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8435                 return I40E_ERR_INVALID_QP_ID;
8436         }
8437         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8438                                 I40E_MAX_Q_PER_TC);
8439         bsf = rte_bsf32(qpnum_per_tc);
8440
8441         /**
8442          * Configure TC and queue mapping parameters, for enabled TC,
8443          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8444          * default queue will serve it.
8445          */
8446         qp_idx = 0;
8447         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8448                 if (vsi->enabled_tc & (1 << i)) {
8449                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8450                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8451                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8452                         qp_idx += qpnum_per_tc;
8453                 } else
8454                         info->tc_mapping[i] = 0;
8455         }
8456
8457         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8458         if (vsi->type == I40E_VSI_SRIOV) {
8459                 info->mapping_flags |=
8460                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8461                 for (i = 0; i < vsi->nb_qps; i++)
8462                         info->queue_mapping[i] =
8463                                 rte_cpu_to_le_16(vsi->base_queue + i);
8464         } else {
8465                 info->mapping_flags |=
8466                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8467                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8468         }
8469         info->valid_sections |=
8470                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8471
8472         return I40E_SUCCESS;
8473 }
8474
8475 /*
8476  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8477  * @veb: VEB to be configured
8478  * @tc_map: enabled TC bitmap
8479  *
8480  * Returns 0 on success, negative value on failure
8481  */
8482 static enum i40e_status_code
8483 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8484 {
8485         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8486         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8487         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8488         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8489         enum i40e_status_code ret = I40E_SUCCESS;
8490         int i;
8491         uint32_t bw_max;
8492
8493         /* Check if enabled_tc is same as existing or new TCs */
8494         if (veb->enabled_tc == tc_map)
8495                 return ret;
8496
8497         /* configure tc bandwidth */
8498         memset(&veb_bw, 0, sizeof(veb_bw));
8499         veb_bw.tc_valid_bits = tc_map;
8500         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8501         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8502                 if (tc_map & BIT_ULL(i))
8503                         veb_bw.tc_bw_share_credits[i] = 1;
8504         }
8505         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8506                                                    &veb_bw, NULL);
8507         if (ret) {
8508                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8509                                   " per TC failed = %d",
8510                                   hw->aq.asq_last_status);
8511                 return ret;
8512         }
8513
8514         memset(&ets_query, 0, sizeof(ets_query));
8515         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8516                                                    &ets_query, NULL);
8517         if (ret != I40E_SUCCESS) {
8518                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8519                                  " configuration %u", hw->aq.asq_last_status);
8520                 return ret;
8521         }
8522         memset(&bw_query, 0, sizeof(bw_query));
8523         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8524                                                   &bw_query, NULL);
8525         if (ret != I40E_SUCCESS) {
8526                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8527                                  " configuration %u", hw->aq.asq_last_status);
8528                 return ret;
8529         }
8530
8531         /* store and print out BW info */
8532         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8533         veb->bw_info.bw_max = ets_query.tc_bw_max;
8534         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8535         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8536         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8537                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8538                      I40E_16_BIT_WIDTH);
8539         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8540                 veb->bw_info.bw_ets_share_credits[i] =
8541                                 bw_query.tc_bw_share_credits[i];
8542                 veb->bw_info.bw_ets_credits[i] =
8543                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8544                 /* 4 bits per TC, 4th bit is reserved */
8545                 veb->bw_info.bw_ets_max[i] =
8546                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8547                                   RTE_LEN2MASK(3, uint8_t));
8548                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8549                             veb->bw_info.bw_ets_share_credits[i]);
8550                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8551                             veb->bw_info.bw_ets_credits[i]);
8552                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8553                             veb->bw_info.bw_ets_max[i]);
8554         }
8555
8556         veb->enabled_tc = tc_map;
8557
8558         return ret;
8559 }
8560
8561
8562 /*
8563  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8564  * @vsi: VSI to be configured
8565  * @tc_map: enabled TC bitmap
8566  *
8567  * Returns 0 on success, negative value on failure
8568  */
8569 static enum i40e_status_code
8570 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8571 {
8572         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8573         struct i40e_vsi_context ctxt;
8574         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8575         enum i40e_status_code ret = I40E_SUCCESS;
8576         int i;
8577
8578         /* Check if enabled_tc is same as existing or new TCs */
8579         if (vsi->enabled_tc == tc_map)
8580                 return ret;
8581
8582         /* configure tc bandwidth */
8583         memset(&bw_data, 0, sizeof(bw_data));
8584         bw_data.tc_valid_bits = tc_map;
8585         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8586         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8587                 if (tc_map & BIT_ULL(i))
8588                         bw_data.tc_bw_credits[i] = 1;
8589         }
8590         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8591         if (ret) {
8592                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8593                         " per TC failed = %d",
8594                         hw->aq.asq_last_status);
8595                 goto out;
8596         }
8597         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8598                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8599
8600         /* Update Queue Pairs Mapping for currently enabled UPs */
8601         ctxt.seid = vsi->seid;
8602         ctxt.pf_num = hw->pf_id;
8603         ctxt.vf_num = 0;
8604         ctxt.uplink_seid = vsi->uplink_seid;
8605         ctxt.info = vsi->info;
8606         i40e_get_cap(hw);
8607         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8608         if (ret)
8609                 goto out;
8610
8611         /* Update the VSI after updating the VSI queue-mapping information */
8612         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8613         if (ret) {
8614                 PMD_INIT_LOG(ERR, "Failed to configure "
8615                             "TC queue mapping = %d",
8616                             hw->aq.asq_last_status);
8617                 goto out;
8618         }
8619         /* update the local VSI info with updated queue map */
8620         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8621                                         sizeof(vsi->info.tc_mapping));
8622         (void)rte_memcpy(&vsi->info.queue_mapping,
8623                         &ctxt.info.queue_mapping,
8624                 sizeof(vsi->info.queue_mapping));
8625         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8626         vsi->info.valid_sections = 0;
8627
8628         /* query and update current VSI BW information */
8629         ret = i40e_vsi_get_bw_config(vsi);
8630         if (ret) {
8631                 PMD_INIT_LOG(ERR,
8632                          "Failed updating vsi bw info, err %s aq_err %s",
8633                          i40e_stat_str(hw, ret),
8634                          i40e_aq_str(hw, hw->aq.asq_last_status));
8635                 goto out;
8636         }
8637
8638         vsi->enabled_tc = tc_map;
8639
8640 out:
8641         return ret;
8642 }
8643
8644 /*
8645  * i40e_dcb_hw_configure - program the dcb setting to hw
8646  * @pf: pf the configuration is taken on
8647  * @new_cfg: new configuration
8648  * @tc_map: enabled TC bitmap
8649  *
8650  * Returns 0 on success, negative value on failure
8651  */
8652 static enum i40e_status_code
8653 i40e_dcb_hw_configure(struct i40e_pf *pf,
8654                       struct i40e_dcbx_config *new_cfg,
8655                       uint8_t tc_map)
8656 {
8657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8658         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8659         struct i40e_vsi *main_vsi = pf->main_vsi;
8660         struct i40e_vsi_list *vsi_list;
8661         enum i40e_status_code ret;
8662         int i;
8663         uint32_t val;
8664
8665         /* Use the FW API if FW > v4.4*/
8666         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8667               (hw->aq.fw_maj_ver >= 5))) {
8668                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8669                                   " to configure DCB");
8670                 return I40E_ERR_FIRMWARE_API_VERSION;
8671         }
8672
8673         /* Check if need reconfiguration */
8674         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8675                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8676                 return I40E_SUCCESS;
8677         }
8678
8679         /* Copy the new config to the current config */
8680         *old_cfg = *new_cfg;
8681         old_cfg->etsrec = old_cfg->etscfg;
8682         ret = i40e_set_dcb_config(hw);
8683         if (ret) {
8684                 PMD_INIT_LOG(ERR,
8685                          "Set DCB Config failed, err %s aq_err %s\n",
8686                          i40e_stat_str(hw, ret),
8687                          i40e_aq_str(hw, hw->aq.asq_last_status));
8688                 return ret;
8689         }
8690         /* set receive Arbiter to RR mode and ETS scheme by default */
8691         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8692                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8693                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8694                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8695                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8696                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8697                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8698                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8699                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8700                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8701                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8702                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8703                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8704         }
8705         /* get local mib to check whether it is configured correctly */
8706         /* IEEE mode */
8707         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8708         /* Get Local DCB Config */
8709         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8710                                      &hw->local_dcbx_config);
8711
8712         /* if Veb is created, need to update TC of it at first */
8713         if (main_vsi->veb) {
8714                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8715                 if (ret)
8716                         PMD_INIT_LOG(WARNING,
8717                                  "Failed configuring TC for VEB seid=%d\n",
8718                                  main_vsi->veb->seid);
8719         }
8720         /* Update each VSI */
8721         i40e_vsi_config_tc(main_vsi, tc_map);
8722         if (main_vsi->veb) {
8723                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8724                         /* Beside main VSI and VMDQ VSIs, only enable default
8725                          * TC for other VSIs
8726                          */
8727                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8728                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8729                                                          tc_map);
8730                         else
8731                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8732                                                          I40E_DEFAULT_TCMAP);
8733                         if (ret)
8734                                 PMD_INIT_LOG(WARNING,
8735                                          "Failed configuring TC for VSI seid=%d\n",
8736                                          vsi_list->vsi->seid);
8737                         /* continue */
8738                 }
8739         }
8740         return I40E_SUCCESS;
8741 }
8742
8743 /*
8744  * i40e_dcb_init_configure - initial dcb config
8745  * @dev: device being configured
8746  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8747  *
8748  * Returns 0 on success, negative value on failure
8749  */
8750 static int
8751 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8752 {
8753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8755         int ret = 0;
8756
8757         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8758                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8759                 return -ENOTSUP;
8760         }
8761
8762         /* DCB initialization:
8763          * Update DCB configuration from the Firmware and configure
8764          * LLDP MIB change event.
8765          */
8766         if (sw_dcb == TRUE) {
8767                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8768                 if (ret != I40E_SUCCESS)
8769                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8770
8771                 ret = i40e_init_dcb(hw);
8772                 /* if sw_dcb, lldp agent is stopped, the return from
8773                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8774                  * adminq status.
8775                  */
8776                 if (ret != I40E_SUCCESS &&
8777                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8778                         memset(&hw->local_dcbx_config, 0,
8779                                 sizeof(struct i40e_dcbx_config));
8780                         /* set dcb default configuration */
8781                         hw->local_dcbx_config.etscfg.willing = 0;
8782                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8783                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8784                         hw->local_dcbx_config.etscfg.tsatable[0] =
8785                                                 I40E_IEEE_TSA_ETS;
8786                         hw->local_dcbx_config.etsrec =
8787                                 hw->local_dcbx_config.etscfg;
8788                         hw->local_dcbx_config.pfc.willing = 0;
8789                         hw->local_dcbx_config.pfc.pfccap =
8790                                                 I40E_MAX_TRAFFIC_CLASS;
8791                         /* FW needs one App to configure HW */
8792                         hw->local_dcbx_config.numapps = 1;
8793                         hw->local_dcbx_config.app[0].selector =
8794                                                 I40E_APP_SEL_ETHTYPE;
8795                         hw->local_dcbx_config.app[0].priority = 3;
8796                         hw->local_dcbx_config.app[0].protocolid =
8797                                                 I40E_APP_PROTOID_FCOE;
8798                         ret = i40e_set_dcb_config(hw);
8799                         if (ret) {
8800                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8801                                         " err = %d, aq_err = %d.", ret,
8802                                           hw->aq.asq_last_status);
8803                                 return -ENOSYS;
8804                         }
8805                 } else {
8806                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8807                                           " aq_err = %d.", ret,
8808                                           hw->aq.asq_last_status);
8809                         return -ENOTSUP;
8810                 }
8811         } else {
8812                 ret = i40e_aq_start_lldp(hw, NULL);
8813                 if (ret != I40E_SUCCESS)
8814                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8815
8816                 ret = i40e_init_dcb(hw);
8817                 if (!ret) {
8818                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8819                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8820                                                   " DCBX offload.");
8821                                 return -ENOTSUP;
8822                         }
8823                 } else {
8824                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8825                                           " aq_err = %d.", ret,
8826                                           hw->aq.asq_last_status);
8827                         return -ENOTSUP;
8828                 }
8829         }
8830         return 0;
8831 }
8832
8833 /*
8834  * i40e_dcb_setup - setup dcb related config
8835  * @dev: device being configured
8836  *
8837  * Returns 0 on success, negative value on failure
8838  */
8839 static int
8840 i40e_dcb_setup(struct rte_eth_dev *dev)
8841 {
8842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8843         struct i40e_dcbx_config dcb_cfg;
8844         uint8_t tc_map = 0;
8845         int ret = 0;
8846
8847         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8848                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8849                 return -ENOTSUP;
8850         }
8851
8852         if (pf->vf_num != 0)
8853                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8854
8855         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8856         if (ret) {
8857                 PMD_INIT_LOG(ERR, "invalid dcb config");
8858                 return -EINVAL;
8859         }
8860         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8861         if (ret) {
8862                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8863                 return -ENOSYS;
8864         }
8865
8866         return 0;
8867 }
8868
8869 static int
8870 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8871                       struct rte_eth_dcb_info *dcb_info)
8872 {
8873         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8875         struct i40e_vsi *vsi = pf->main_vsi;
8876         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8877         uint16_t bsf, tc_mapping;
8878         int i, j;
8879
8880         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8881                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8882         else
8883                 dcb_info->nb_tcs = 1;
8884         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8885                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8886         for (i = 0; i < dcb_info->nb_tcs; i++)
8887                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8888
8889         j = 0;
8890         do {
8891                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8892                         if (!(vsi->enabled_tc & (1 << i)))
8893                                 continue;
8894                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8895                         /* only main vsi support multi TCs */
8896                         dcb_info->tc_queue.tc_rxq[j][i].base =
8897                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8898                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8899                         dcb_info->tc_queue.tc_txq[j][i].base =
8900                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8901                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8902                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8903                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8904                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8905                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8906                 }
8907                 vsi = pf->vmdq[j].vsi;
8908                 j++;
8909         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8910         return 0;
8911 }
8912
8913 static int
8914 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8915 {
8916         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8918         uint16_t interval =
8919                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8920         uint16_t msix_intr;
8921
8922         msix_intr = intr_handle->intr_vec[queue_id];
8923         if (msix_intr == I40E_MISC_VEC_ID)
8924                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8925                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8926                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8927                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8928                                (interval <<
8929                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8930         else
8931                 I40E_WRITE_REG(hw,
8932                                I40E_PFINT_DYN_CTLN(msix_intr -
8933                                                    I40E_RX_VEC_START),
8934                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8935                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8936                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8937                                (interval <<
8938                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8939
8940         I40E_WRITE_FLUSH(hw);
8941         rte_intr_enable(&dev->pci_dev->intr_handle);
8942
8943         return 0;
8944 }
8945
8946 static int
8947 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8948 {
8949         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8951         uint16_t msix_intr;
8952
8953         msix_intr = intr_handle->intr_vec[queue_id];
8954         if (msix_intr == I40E_MISC_VEC_ID)
8955                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8956         else
8957                 I40E_WRITE_REG(hw,
8958                                I40E_PFINT_DYN_CTLN(msix_intr -
8959                                                    I40E_RX_VEC_START),
8960                                0);
8961         I40E_WRITE_FLUSH(hw);
8962
8963         return 0;
8964 }
8965
8966 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
8967 {
8968         /* Highest base addr + 32-bit word */
8969         return I40E_GLGEN_STAT_CLEAR + 4;
8970 }
8971
8972 static int i40e_get_regs(struct rte_eth_dev *dev,
8973                          struct rte_dev_reg_info *regs)
8974 {
8975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8976         uint32_t *ptr_data = regs->data;
8977         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
8978         const struct i40e_reg_info *reg_info;
8979
8980         /* The first few registers have to be read using AQ operations */
8981         reg_idx = 0;
8982         while (i40e_regs_adminq[reg_idx].name) {
8983                 reg_info = &i40e_regs_adminq[reg_idx++];
8984                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8985                         for (arr_idx2 = 0;
8986                                         arr_idx2 <= reg_info->count2;
8987                                         arr_idx2++) {
8988                                 reg_offset = arr_idx * reg_info->stride1 +
8989                                         arr_idx2 * reg_info->stride2;
8990                                 ptr_data[reg_offset >> 2] =
8991                                         i40e_read_rx_ctl(hw, reg_offset);
8992                         }
8993         }
8994
8995         /* The remaining registers can be read using primitives */
8996         reg_idx = 0;
8997         while (i40e_regs_others[reg_idx].name) {
8998                 reg_info = &i40e_regs_others[reg_idx++];
8999                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9000                         for (arr_idx2 = 0;
9001                                         arr_idx2 <= reg_info->count2;
9002                                         arr_idx2++) {
9003                                 reg_offset = arr_idx * reg_info->stride1 +
9004                                         arr_idx2 * reg_info->stride2;
9005                                 ptr_data[reg_offset >> 2] =
9006                                         I40E_READ_REG(hw, reg_offset);
9007                         }
9008         }
9009
9010         return 0;
9011 }
9012
9013 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9014 {
9015         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9016
9017         /* Convert word count to byte count */
9018         return hw->nvm.sr_size << 1;
9019 }
9020
9021 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9022                            struct rte_dev_eeprom_info *eeprom)
9023 {
9024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9025         uint16_t *data = eeprom->data;
9026         uint16_t offset, length, cnt_words;
9027         int ret_code;
9028
9029         offset = eeprom->offset >> 1;
9030         length = eeprom->length >> 1;
9031         cnt_words = length;
9032
9033         if (offset > hw->nvm.sr_size ||
9034                 offset + length > hw->nvm.sr_size) {
9035                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9036                 return -EINVAL;
9037         }
9038
9039         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9040
9041         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9042         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9043                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9044                 return -EIO;
9045         }
9046
9047         return 0;
9048 }
9049
9050 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9051                                       struct ether_addr *mac_addr)
9052 {
9053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9054
9055         if (!is_valid_assigned_ether_addr(mac_addr)) {
9056                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9057                 return;
9058         }
9059
9060         /* Flags: 0x3 updates port address */
9061         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9062 }