drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 483         .tx_queue_release             = i40e_dev_tx_queue_release,
 484         .dev_led_on                   = i40e_dev_led_on,
 485         .dev_led_off                  = i40e_dev_led_off,
 486         .flow_ctrl_get                = i40e_flow_ctrl_get,
 487         .flow_ctrl_set                = i40e_flow_ctrl_set,
 488         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 489         .mac_addr_add                 = i40e_macaddr_add,
 490         .mac_addr_remove              = i40e_macaddr_remove,
 491         .reta_update                  = i40e_dev_rss_reta_update,
 492         .reta_query                   = i40e_dev_rss_reta_query,
 493         .rss_hash_update              = i40e_dev_rss_hash_update,
 494         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 495         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 496         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 497         .filter_ctrl                  = i40e_dev_filter_ctrl,
 498         .rxq_info_get                 = i40e_rxq_info_get,
 499         .txq_info_get                 = i40e_txq_info_get,
 500         .mirror_rule_set              = i40e_mirror_rule_set,
 501         .mirror_rule_reset            = i40e_mirror_rule_reset,
 502         .timesync_enable              = i40e_timesync_enable,
 503         .timesync_disable             = i40e_timesync_disable,
 504         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 505         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 506         .get_dcb_info                 = i40e_dev_get_dcb_info,
 507         .timesync_adjust_time         = i40e_timesync_adjust_time,
 508         .timesync_read_time           = i40e_timesync_read_time,
 509         .timesync_write_time          = i40e_timesync_write_time,
 510         .get_reg                      = i40e_get_regs,
 511         .get_eeprom_length            = i40e_get_eeprom_length,
 512         .get_eeprom                   = i40e_get_eeprom,
 513         .mac_addr_set                 = i40e_set_default_mac_addr,
 514         .mtu_set                      = i40e_dev_mtu_set,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static struct eth_driver rte_i40e_pmd = {
 631         .pci_drv = {
 632                 .id_table = pci_id_i40e_map,
 633                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 634                 .probe = rte_eth_dev_pci_probe,
 635                 .remove = rte_eth_dev_pci_remove,
 636         },
 637         .eth_dev_init = eth_i40e_dev_init,
 638         .eth_dev_uninit = eth_i40e_dev_uninit,
 639         .dev_private_size = sizeof(struct i40e_adapter),
 640 };
 641
 642 static inline int
 643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 644                                      struct rte_eth_link *link)
 645 {
 646         struct rte_eth_link *dst = link;
 647         struct rte_eth_link *src = &(dev->data->dev_link);
 648
 649         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 650                                         *(uint64_t *)src) == 0)
 651                 return -1;
 652
 653         return 0;
 654 }
 655
 656 static inline int
 657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 658                                       struct rte_eth_link *link)
 659 {
 660         struct rte_eth_link *dst = &(dev->data->dev_link);
 661         struct rte_eth_link *src = link;
 662
 663         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 664                                         *(uint64_t *)src) == 0)
 665                 return -1;
 666
 667         return 0;
 668 }
 669
 670 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 671 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 672 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 673
 674 #ifndef I40E_GLQF_ORT
 675 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 676 #endif
 677 #ifndef I40E_GLQF_PIT
 678 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 679 #endif
 680
 681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 682 {
 683         /*
 684          * Initialize registers for flexible payload, which should be set by NVM.
 685          * This should be removed from code once it is fixed in NVM.
 686          */
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 698         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 699
 700         /* Initialize registers for parsing packet type of QinQ */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 702         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 703 }
 704
 705 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 706
 707 /*
 708  * Add a ethertype filter to drop all flow control frames transmitted
 709  * from VSIs.
 710 */
 711 static void
 712 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 713 {
 714         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 715         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 716                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 717                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 718         int ret;
 719
 720         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 721                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 722                                 pf->main_vsi_seid, 0,
 723                                 TRUE, NULL, NULL);
 724         if (ret)
 725                 PMD_INIT_LOG(ERR,
 726                         "Failed to add filter to drop flow control frames from VSIs.");
 727 }
 728
 729 static int
 730 floating_veb_list_handler(__rte_unused const char *key,
 731                           const char *floating_veb_value,
 732                           void *opaque)
 733 {
 734         int idx = 0;
 735         unsigned int count = 0;
 736         char *end = NULL;
 737         int min, max;
 738         bool *vf_floating_veb = opaque;
 739
 740         while (isblank(*floating_veb_value))
 741                 floating_veb_value++;
 742
 743         /* Reset floating VEB configuration for VFs */
 744         for (idx = 0; idx < I40E_MAX_VF; idx++)
 745                 vf_floating_veb[idx] = false;
 746
 747         min = I40E_MAX_VF;
 748         do {
 749                 while (isblank(*floating_veb_value))
 750                         floating_veb_value++;
 751                 if (*floating_veb_value == '\0')
 752                         return -1;
 753                 errno = 0;
 754                 idx = strtoul(floating_veb_value, &end, 10);
 755                 if (errno || end == NULL)
 756                         return -1;
 757                 while (isblank(*end))
 758                         end++;
 759                 if (*end == '-') {
 760                         min = idx;
 761                 } else if ((*end == ';') || (*end == '\0')) {
 762                         max = idx;
 763                         if (min == I40E_MAX_VF)
 764                                 min = idx;
 765                         if (max >= I40E_MAX_VF)
 766                                 max = I40E_MAX_VF - 1;
 767                         for (idx = min; idx <= max; idx++) {
 768                                 vf_floating_veb[idx] = true;
 769                                 count++;
 770                         }
 771                         min = I40E_MAX_VF;
 772                 } else {
 773                         return -1;
 774                 }
 775                 floating_veb_value = end + 1;
 776         } while (*end != '\0');
 777
 778         if (count == 0)
 779                 return -1;
 780
 781         return 0;
 782 }
 783
 784 static void
 785 config_vf_floating_veb(struct rte_devargs *devargs,
 786                        uint16_t floating_veb,
 787                        bool *vf_floating_veb)
 788 {
 789         struct rte_kvargs *kvlist;
 790         int i;
 791         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 792
 793         if (!floating_veb)
 794                 return;
 795         /* All the VFs attach to the floating VEB by default
 796          * when the floating VEB is enabled.
 797          */
 798         for (i = 0; i < I40E_MAX_VF; i++)
 799                 vf_floating_veb[i] = true;
 800
 801         if (devargs == NULL)
 802                 return;
 803
 804         kvlist = rte_kvargs_parse(devargs->args, NULL);
 805         if (kvlist == NULL)
 806                 return;
 807
 808         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 809                 rte_kvargs_free(kvlist);
 810                 return;
 811         }
 812         /* When the floating_veb_list parameter exists, all the VFs
 813          * will attach to the legacy VEB firstly, then configure VFs
 814          * to the floating VEB according to the floating_veb_list.
 815          */
 816         if (rte_kvargs_process(kvlist, floating_veb_list,
 817                                floating_veb_list_handler,
 818                                vf_floating_veb) < 0) {
 819                 rte_kvargs_free(kvlist);
 820                 return;
 821         }
 822         rte_kvargs_free(kvlist);
 823 }
 824
 825 static int
 826 i40e_check_floating_handler(__rte_unused const char *key,
 827                             const char *value,
 828                             __rte_unused void *opaque)
 829 {
 830         if (strcmp(value, "1"))
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 static int
 837 is_floating_veb_supported(struct rte_devargs *devargs)
 838 {
 839         struct rte_kvargs *kvlist;
 840         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 841
 842         if (devargs == NULL)
 843                 return 0;
 844
 845         kvlist = rte_kvargs_parse(devargs->args, NULL);
 846         if (kvlist == NULL)
 847                 return 0;
 848
 849         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 850                 rte_kvargs_free(kvlist);
 851                 return 0;
 852         }
 853         /* Floating VEB is enabled when there's key-value:
 854          * enable_floating_veb=1
 855          */
 856         if (rte_kvargs_process(kvlist, floating_veb_key,
 857                                i40e_check_floating_handler, NULL) < 0) {
 858                 rte_kvargs_free(kvlist);
 859                 return 0;
 860         }
 861         rte_kvargs_free(kvlist);
 862
 863         return 1;
 864 }
 865
 866 static void
 867 config_floating_veb(struct rte_eth_dev *dev)
 868 {
 869         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 872
 873         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 874
 875         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 876                 pf->floating_veb =
 877                         is_floating_veb_supported(pci_dev->device.devargs);
 878                 config_vf_floating_veb(pci_dev->device.devargs,
 879                                        pf->floating_veb,
 880                                        pf->floating_veb_list);
 881         } else {
 882                 pf->floating_veb = false;
 883         }
 884 }
 885
 886 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 887 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 888
 889 static int
 890 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 891 {
 892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 893         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 894         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 895         int ret;
 896
 897         struct rte_hash_parameters ethertype_hash_params = {
 898                 .name = ethertype_hash_name,
 899                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 900                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 901                 .hash_func = rte_hash_crc,
 902         };
 903
 904         /* Initialize ethertype filter rule list and hash */
 905         TAILQ_INIT(&ethertype_rule->ethertype_list);
 906         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 907                  "ethertype_%s", dev->data->name);
 908         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 909         if (!ethertype_rule->hash_table) {
 910                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 911                 return -EINVAL;
 912         }
 913         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 914                                        sizeof(struct i40e_ethertype_filter *) *
 915                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 916                                        0);
 917         if (!ethertype_rule->hash_map) {
 918                 PMD_INIT_LOG(ERR,
 919                              "Failed to allocate memory for ethertype hash map!");
 920                 ret = -ENOMEM;
 921                 goto err_ethertype_hash_map_alloc;
 922         }
 923
 924         return 0;
 925
 926 err_ethertype_hash_map_alloc:
 927         rte_hash_free(ethertype_rule->hash_table);
 928
 929         return ret;
 930 }
 931
 932 static int
 933 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 934 {
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 937         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 938         int ret;
 939
 940         struct rte_hash_parameters tunnel_hash_params = {
 941                 .name = tunnel_hash_name,
 942                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 943                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 944                 .hash_func = rte_hash_crc,
 945         };
 946
 947         /* Initialize tunnel filter rule list and hash */
 948         TAILQ_INIT(&tunnel_rule->tunnel_list);
 949         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 950                  "tunnel_%s", dev->data->name);
 951         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 952         if (!tunnel_rule->hash_table) {
 953                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 954                 return -EINVAL;
 955         }
 956         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 957                                     sizeof(struct i40e_tunnel_filter *) *
 958                                     I40E_MAX_TUNNEL_FILTER_NUM,
 959                                     0);
 960         if (!tunnel_rule->hash_map) {
 961                 PMD_INIT_LOG(ERR,
 962                              "Failed to allocate memory for tunnel hash map!");
 963                 ret = -ENOMEM;
 964                 goto err_tunnel_hash_map_alloc;
 965         }
 966
 967         return 0;
 968
 969 err_tunnel_hash_map_alloc:
 970         rte_hash_free(tunnel_rule->hash_table);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 977 {
 978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 979         struct i40e_fdir_info *fdir_info = &pf->fdir;
 980         char fdir_hash_name[RTE_HASH_NAMESIZE];
 981         int ret;
 982
 983         struct rte_hash_parameters fdir_hash_params = {
 984                 .name = fdir_hash_name,
 985                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 986                 .key_len = sizeof(struct rte_eth_fdir_input),
 987                 .hash_func = rte_hash_crc,
 988         };
 989
 990         /* Initialize flow director filter rule list and hash */
 991         TAILQ_INIT(&fdir_info->fdir_list);
 992         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 993                  "fdir_%s", dev->data->name);
 994         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 995         if (!fdir_info->hash_table) {
 996                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 997                 return -EINVAL;
 998         }
 999         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1000                                           sizeof(struct i40e_fdir_filter *) *
1001                                           I40E_MAX_FDIR_FILTER_NUM,
1002                                           0);
1003         if (!fdir_info->hash_map) {
1004                 PMD_INIT_LOG(ERR,
1005                              "Failed to allocate memory for fdir hash map!");
1006                 ret = -ENOMEM;
1007                 goto err_fdir_hash_map_alloc;
1008         }
1009         return 0;
1010
1011 err_fdir_hash_map_alloc:
1012         rte_hash_free(fdir_info->hash_table);
1013
1014         return ret;
1015 }
1016
1017 static int
1018 eth_i40e_dev_init(struct rte_eth_dev *dev)
1019 {
1020         struct rte_pci_device *pci_dev;
1021         struct rte_intr_handle *intr_handle;
1022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         struct i40e_vsi *vsi;
1025         int ret;
1026         uint32_t len;
1027         uint8_t aq_fail = 0;
1028
1029         PMD_INIT_FUNC_TRACE();
1030
1031         dev->dev_ops = &i40e_eth_dev_ops;
1032         dev->rx_pkt_burst = i40e_recv_pkts;
1033         dev->tx_pkt_burst = i40e_xmit_pkts;
1034         dev->tx_pkt_prepare = i40e_prep_pkts;
1035
1036         /* for secondary processes, we don't initialise any further as primary
1037          * has already done this work. Only check we don't need a different
1038          * RX function */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 i40e_set_rx_function(dev);
1041                 i40e_set_tx_function(dev);
1042                 return 0;
1043         }
1044         pci_dev = I40E_DEV_TO_PCI(dev);
1045         intr_handle = &pci_dev->intr_handle;
1046
1047         rte_eth_copy_pci_info(dev, pci_dev);
1048         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1049
1050         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1051         pf->adapter->eth_dev = dev;
1052         pf->dev_data = dev->data;
1053
1054         hw->back = I40E_PF_TO_ADAPTER(pf);
1055         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1056         if (!hw->hw_addr) {
1057                 PMD_INIT_LOG(ERR,
1058                         "Hardware is not available, as address is NULL");
1059                 return -ENODEV;
1060         }
1061
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->device_id = pci_dev->id.device_id;
1064         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1065         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1066         hw->bus.device = pci_dev->addr.devid;
1067         hw->bus.func = pci_dev->addr.function;
1068         hw->adapter_stopped = 0;
1069
1070         /* Make sure all is clean before doing PF reset */
1071         i40e_clear_hw(hw);
1072
1073         /* Initialize the hardware */
1074         i40e_hw_init(dev);
1075
1076         /* Reset here to make sure all is clean for each PF */
1077         ret = i40e_pf_reset(hw);
1078         if (ret) {
1079                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1080                 return ret;
1081         }
1082
1083         /* Initialize the shared code (base driver) */
1084         ret = i40e_init_shared_code(hw);
1085         if (ret) {
1086                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1087                 return ret;
1088         }
1089
1090         /*
1091          * To work around the NVM issue, initialize registers
1092          * for flexible payload and packet type of QinQ by
1093          * software. It should be removed once issues are fixed
1094          * in NVM.
1095          */
1096         i40e_GLQF_reg_init(hw);
1097
1098         /* Initialize the input set for filters (hash and fd) to default value */
1099         i40e_filter_input_set_init(pf);
1100
1101         /* Initialize the parameters for adminq */
1102         i40e_init_adminq_parameter(hw);
1103         ret = i40e_init_adminq(hw);
1104         if (ret != I40E_SUCCESS) {
1105                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1106                 return -EIO;
1107         }
1108         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1109                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1110                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1111                      ((hw->nvm.version >> 12) & 0xf),
1112                      ((hw->nvm.version >> 4) & 0xff),
1113                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1114
1115         /* Need the special FW version to support floating VEB */
1116         config_floating_veb(dev);
1117         /* Clear PXE mode */
1118         i40e_clear_pxe_mode(hw);
1119         ret = i40e_dev_sync_phy_type(hw);
1120         if (ret) {
1121                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1122                 goto err_sync_phy_type;
1123         }
1124         /*
1125          * On X710, performance number is far from the expectation on recent
1126          * firmware versions. The fix for this issue may not be integrated in
1127          * the following firmware version. So the workaround in software driver
1128          * is needed. It needs to modify the initial values of 3 internal only
1129          * registers. Note that the workaround can be removed when it is fixed
1130          * in firmware in the future.
1131          */
1132         i40e_configure_registers(hw);
1133
1134         /* Get hw capabilities */
1135         ret = i40e_get_cap(hw);
1136         if (ret != I40E_SUCCESS) {
1137                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1138                 goto err_get_capabilities;
1139         }
1140
1141         /* Initialize parameters for PF */
1142         ret = i40e_pf_parameter_init(dev);
1143         if (ret != 0) {
1144                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1145                 goto err_parameter_init;
1146         }
1147
1148         /* Initialize the queue management */
1149         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1150         if (ret < 0) {
1151                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1152                 goto err_qp_pool_init;
1153         }
1154         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1155                                 hw->func_caps.num_msix_vectors - 1);
1156         if (ret < 0) {
1157                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1158                 goto err_msix_pool_init;
1159         }
1160
1161         /* Initialize lan hmc */
1162         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1163                                 hw->func_caps.num_rx_qp, 0, 0);
1164         if (ret != I40E_SUCCESS) {
1165                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1166                 goto err_init_lan_hmc;
1167         }
1168
1169         /* Configure lan hmc */
1170         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1171         if (ret != I40E_SUCCESS) {
1172                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1173                 goto err_configure_lan_hmc;
1174         }
1175
1176         /* Get and check the mac address */
1177         i40e_get_mac_addr(hw, hw->mac.addr);
1178         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "mac address is not valid");
1180                 ret = -EIO;
1181                 goto err_get_mac_addr;
1182         }
1183         /* Copy the permanent MAC address */
1184         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1185                         (struct ether_addr *) hw->mac.perm_addr);
1186
1187         /* Disable flow control */
1188         hw->fc.requested_mode = I40E_FC_NONE;
1189         i40e_set_fc(hw, &aq_fail, TRUE);
1190
1191         /* Set the global registers with default ether type value */
1192         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR,
1195                         "Failed to set the default outer VLAN ether type");
1196                 goto err_setup_pf_switch;
1197         }
1198
1199         /* PF setup, which includes VSI setup */
1200         ret = i40e_pf_setup(pf);
1201         if (ret) {
1202                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1203                 goto err_setup_pf_switch;
1204         }
1205
1206         /* reset all stats of the device, including pf and main vsi */
1207         i40e_dev_stats_reset(dev);
1208
1209         vsi = pf->main_vsi;
1210
1211         /* Disable double vlan by default */
1212         i40e_vsi_config_double_vlan(vsi, FALSE);
1213
1214         /* Disable S-TAG identification when floating_veb is disabled */
1215         if (!pf->floating_veb) {
1216                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1217                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1218                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1219                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1220                 }
1221         }
1222
1223         if (!vsi->max_macaddrs)
1224                 len = ETHER_ADDR_LEN;
1225         else
1226                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1227
1228         /* Should be after VSI initialized */
1229         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1230         if (!dev->data->mac_addrs) {
1231                 PMD_INIT_LOG(ERR,
1232                         "Failed to allocated memory for storing mac address");
1233                 goto err_mac_alloc;
1234         }
1235         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1236                                         &dev->data->mac_addrs[0]);
1237
1238         /* initialize pf host driver to setup SRIOV resource if applicable */
1239         i40e_pf_host_init(dev);
1240
1241         /* register callback func to eal lib */
1242         rte_intr_callback_register(intr_handle,
1243                                    i40e_dev_interrupt_handler, dev);
1244
1245         /* configure and enable device interrupt */
1246         i40e_pf_config_irq0(hw, TRUE);
1247         i40e_pf_enable_irq0(hw);
1248
1249         /* enable uio intr after callback register */
1250         rte_intr_enable(intr_handle);
1251         /*
1252          * Add an ethertype filter to drop all flow control frames transmitted
1253          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1254          * frames to wire.
1255          */
1256         i40e_add_tx_flow_control_drop_filter(pf);
1257
1258         /* Set the max frame size to 0x2600 by default,
1259          * in case other drivers changed the default value.
1260          */
1261         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1262
1263         /* initialize mirror rule list */
1264         TAILQ_INIT(&pf->mirror_list);
1265
1266         /* Init dcb to sw mode by default */
1267         ret = i40e_dcb_init_configure(dev, TRUE);
1268         if (ret != I40E_SUCCESS) {
1269                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1270                 pf->flags &= ~I40E_FLAG_DCB;
1271         }
1272
1273         ret = i40e_init_ethtype_filter_list(dev);
1274         if (ret < 0)
1275                 goto err_init_ethtype_filter_list;
1276         ret = i40e_init_tunnel_filter_list(dev);
1277         if (ret < 0)
1278                 goto err_init_tunnel_filter_list;
1279         ret = i40e_init_fdir_filter_list(dev);
1280         if (ret < 0)
1281                 goto err_init_fdir_filter_list;
1282
1283         return 0;
1284
1285 err_init_fdir_filter_list:
1286         rte_free(pf->tunnel.hash_table);
1287         rte_free(pf->tunnel.hash_map);
1288 err_init_tunnel_filter_list:
1289         rte_free(pf->ethertype.hash_table);
1290         rte_free(pf->ethertype.hash_map);
1291 err_init_ethtype_filter_list:
1292         rte_free(dev->data->mac_addrs);
1293 err_mac_alloc:
1294         i40e_vsi_release(pf->main_vsi);
1295 err_setup_pf_switch:
1296 err_get_mac_addr:
1297 err_configure_lan_hmc:
1298         (void)i40e_shutdown_lan_hmc(hw);
1299 err_init_lan_hmc:
1300         i40e_res_pool_destroy(&pf->msix_pool);
1301 err_msix_pool_init:
1302         i40e_res_pool_destroy(&pf->qp_pool);
1303 err_qp_pool_init:
1304 err_parameter_init:
1305 err_get_capabilities:
1306 err_sync_phy_type:
1307         (void)i40e_shutdown_adminq(hw);
1308
1309         return ret;
1310 }
1311
1312 static void
1313 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1314 {
1315         struct i40e_ethertype_filter *p_ethertype;
1316         struct i40e_ethertype_rule *ethertype_rule;
1317
1318         ethertype_rule = &pf->ethertype;
1319         /* Remove all ethertype filter rules and hash */
1320         if (ethertype_rule->hash_map)
1321                 rte_free(ethertype_rule->hash_map);
1322         if (ethertype_rule->hash_table)
1323                 rte_hash_free(ethertype_rule->hash_table);
1324
1325         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1326                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1327                              p_ethertype, rules);
1328                 rte_free(p_ethertype);
1329         }
1330 }
1331
1332 static void
1333 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1334 {
1335         struct i40e_tunnel_filter *p_tunnel;
1336         struct i40e_tunnel_rule *tunnel_rule;
1337
1338         tunnel_rule = &pf->tunnel;
1339         /* Remove all tunnel director rules and hash */
1340         if (tunnel_rule->hash_map)
1341                 rte_free(tunnel_rule->hash_map);
1342         if (tunnel_rule->hash_table)
1343                 rte_hash_free(tunnel_rule->hash_table);
1344
1345         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1346                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1347                 rte_free(p_tunnel);
1348         }
1349 }
1350
1351 static void
1352 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1353 {
1354         struct i40e_fdir_filter *p_fdir;
1355         struct i40e_fdir_info *fdir_info;
1356
1357         fdir_info = &pf->fdir;
1358         /* Remove all flow director rules and hash */
1359         if (fdir_info->hash_map)
1360                 rte_free(fdir_info->hash_map);
1361         if (fdir_info->hash_table)
1362                 rte_hash_free(fdir_info->hash_table);
1363
1364         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1366                 rte_free(p_fdir);
1367         }
1368 }
1369
1370 static int
1371 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1372 {
1373         struct i40e_pf *pf;
1374         struct rte_pci_device *pci_dev;
1375         struct rte_intr_handle *intr_handle;
1376         struct i40e_hw *hw;
1377         struct i40e_filter_control_settings settings;
1378         struct rte_flow *p_flow;
1379         int ret;
1380         uint8_t aq_fail = 0;
1381
1382         PMD_INIT_FUNC_TRACE();
1383
1384         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1385                 return 0;
1386
1387         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1388         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389         pci_dev = I40E_DEV_TO_PCI(dev);
1390         intr_handle = &pci_dev->intr_handle;
1391
1392         if (hw->adapter_stopped == 0)
1393                 i40e_dev_close(dev);
1394
1395         dev->dev_ops = NULL;
1396         dev->rx_pkt_burst = NULL;
1397         dev->tx_pkt_burst = NULL;
1398
1399         /* Clear PXE mode */
1400         i40e_clear_pxe_mode(hw);
1401
1402         /* Unconfigure filter control */
1403         memset(&settings, 0, sizeof(settings));
1404         ret = i40e_set_filter_control(hw, &settings);
1405         if (ret)
1406                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1407                                         ret);
1408
1409         /* Disable flow control */
1410         hw->fc.requested_mode = I40E_FC_NONE;
1411         i40e_set_fc(hw, &aq_fail, TRUE);
1412
1413         /* uninitialize pf host driver */
1414         i40e_pf_host_uninit(dev);
1415
1416         rte_free(dev->data->mac_addrs);
1417         dev->data->mac_addrs = NULL;
1418
1419         /* disable uio intr before callback unregister */
1420         rte_intr_disable(intr_handle);
1421
1422         /* register callback func to eal lib */
1423         rte_intr_callback_unregister(intr_handle,
1424                                      i40e_dev_interrupt_handler, dev);
1425
1426         i40e_rm_ethtype_filter_list(pf);
1427         i40e_rm_tunnel_filter_list(pf);
1428         i40e_rm_fdir_filter_list(pf);
1429
1430         /* Remove all flows */
1431         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1432                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1433                 rte_free(p_flow);
1434         }
1435
1436         return 0;
1437 }
1438
1439 static int
1440 i40e_dev_configure(struct rte_eth_dev *dev)
1441 {
1442         struct i40e_adapter *ad =
1443                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1446         int i, ret;
1447
1448         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1449          * bulk allocation or vector Rx preconditions we will reset it.
1450          */
1451         ad->rx_bulk_alloc_allowed = true;
1452         ad->rx_vec_allowed = true;
1453         ad->tx_simple_allowed = true;
1454         ad->tx_vec_allowed = true;
1455
1456         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1457                 ret = i40e_fdir_setup(pf);
1458                 if (ret != I40E_SUCCESS) {
1459                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1460                         return -ENOTSUP;
1461                 }
1462                 ret = i40e_fdir_configure(dev);
1463                 if (ret < 0) {
1464                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1465                         goto err;
1466                 }
1467         } else
1468                 i40e_fdir_teardown(pf);
1469
1470         ret = i40e_dev_init_vlan(dev);
1471         if (ret < 0)
1472                 goto err;
1473
1474         /* VMDQ setup.
1475          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1476          *  RSS setting have different requirements.
1477          *  General PMD driver call sequence are NIC init, configure,
1478          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1479          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1480          *  applicable. So, VMDQ setting has to be done before
1481          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1482          *  For RSS setting, it will try to calculate actual configured RX queue
1483          *  number, which will be available after rx_queue_setup(). dev_start()
1484          *  function is good to place RSS setup.
1485          */
1486         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1487                 ret = i40e_vmdq_setup(dev);
1488                 if (ret)
1489                         goto err;
1490         }
1491
1492         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1493                 ret = i40e_dcb_setup(dev);
1494                 if (ret) {
1495                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1496                         goto err_dcb;
1497                 }
1498         }
1499
1500         TAILQ_INIT(&pf->flow_list);
1501
1502         return 0;
1503
1504 err_dcb:
1505         /* need to release vmdq resource if exists */
1506         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507                 i40e_vsi_release(pf->vmdq[i].vsi);
1508                 pf->vmdq[i].vsi = NULL;
1509         }
1510         rte_free(pf->vmdq);
1511         pf->vmdq = NULL;
1512 err:
1513         /* need to release fdir resource if exists */
1514         i40e_fdir_teardown(pf);
1515         return ret;
1516 }
1517
1518 void
1519 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1520 {
1521         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1523         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525         uint16_t msix_vect = vsi->msix_intr;
1526         uint16_t i;
1527
1528         for (i = 0; i < vsi->nb_qps; i++) {
1529                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1530                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1531                 rte_wmb();
1532         }
1533
1534         if (vsi->type != I40E_VSI_SRIOV) {
1535                 if (!rte_intr_allow_others(intr_handle)) {
1536                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1537                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1538                         I40E_WRITE_REG(hw,
1539                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1540                                        0);
1541                 } else {
1542                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1543                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1544                         I40E_WRITE_REG(hw,
1545                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1546                                                        msix_vect - 1), 0);
1547                 }
1548         } else {
1549                 uint32_t reg;
1550                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1551                         vsi->user_param + (msix_vect - 1);
1552
1553                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1554                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1555         }
1556         I40E_WRITE_FLUSH(hw);
1557 }
1558
1559 static void
1560 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1561                        int base_queue, int nb_queue)
1562 {
1563         int i;
1564         uint32_t val;
1565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1566
1567         /* Bind all RX queues to allocated MSIX interrupt */
1568         for (i = 0; i < nb_queue; i++) {
1569                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1570                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1571                         ((base_queue + i + 1) <<
1572                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1573                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1574                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1575
1576                 if (i == nb_queue - 1)
1577                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1578                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1579         }
1580
1581         /* Write first RX queue to Link list register as the head element */
1582         if (vsi->type != I40E_VSI_SRIOV) {
1583                 uint16_t interval =
1584                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1585
1586                 if (msix_vect == I40E_MISC_VEC_ID) {
1587                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1588                                        (base_queue <<
1589                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1590                                        (0x0 <<
1591                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1592                         I40E_WRITE_REG(hw,
1593                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1594                                        interval);
1595                 } else {
1596                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1597                                        (base_queue <<
1598                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1599                                        (0x0 <<
1600                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1601                         I40E_WRITE_REG(hw,
1602                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1603                                                        msix_vect - 1),
1604                                        interval);
1605                 }
1606         } else {
1607                 uint32_t reg;
1608
1609                 if (msix_vect == I40E_MISC_VEC_ID) {
1610                         I40E_WRITE_REG(hw,
1611                                        I40E_VPINT_LNKLST0(vsi->user_param),
1612                                        (base_queue <<
1613                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1614                                        (0x0 <<
1615                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1616                 } else {
1617                         /* num_msix_vectors_vf needs to minus irq0 */
1618                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1619                                 vsi->user_param + (msix_vect - 1);
1620
1621                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1622                                        (base_queue <<
1623                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1624                                        (0x0 <<
1625                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1626                 }
1627         }
1628
1629         I40E_WRITE_FLUSH(hw);
1630 }
1631
1632 void
1633 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1634 {
1635         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1637         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1639         uint16_t msix_vect = vsi->msix_intr;
1640         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1641         uint16_t queue_idx = 0;
1642         int record = 0;
1643         uint32_t val;
1644         int i;
1645
1646         for (i = 0; i < vsi->nb_qps; i++) {
1647                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1648                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1649         }
1650
1651         /* INTENA flag is not auto-cleared for interrupt */
1652         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1653         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1654                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1655                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1656         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1657
1658         /* VF bind interrupt */
1659         if (vsi->type == I40E_VSI_SRIOV) {
1660                 __vsi_queues_bind_intr(vsi, msix_vect,
1661                                        vsi->base_queue, vsi->nb_qps);
1662                 return;
1663         }
1664
1665         /* PF & VMDq bind interrupt */
1666         if (rte_intr_dp_is_en(intr_handle)) {
1667                 if (vsi->type == I40E_VSI_MAIN) {
1668                         queue_idx = 0;
1669                         record = 1;
1670                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1671                         struct i40e_vsi *main_vsi =
1672                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1673                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1674                         record = 1;
1675                 }
1676         }
1677
1678         for (i = 0; i < vsi->nb_used_qps; i++) {
1679                 if (nb_msix <= 1) {
1680                         if (!rte_intr_allow_others(intr_handle))
1681                                 /* allow to share MISC_VEC_ID */
1682                                 msix_vect = I40E_MISC_VEC_ID;
1683
1684                         /* no enough msix_vect, map all to one */
1685                         __vsi_queues_bind_intr(vsi, msix_vect,
1686                                                vsi->base_queue + i,
1687                                                vsi->nb_used_qps - i);
1688                         for (; !!record && i < vsi->nb_used_qps; i++)
1689                                 intr_handle->intr_vec[queue_idx + i] =
1690                                         msix_vect;
1691                         break;
1692                 }
1693                 /* 1:1 queue/msix_vect mapping */
1694                 __vsi_queues_bind_intr(vsi, msix_vect,
1695                                        vsi->base_queue + i, 1);
1696                 if (!!record)
1697                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1698
1699                 msix_vect++;
1700                 nb_msix--;
1701         }
1702 }
1703
1704 static void
1705 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1706 {
1707         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1708         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1709         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1711         uint16_t interval = i40e_calc_itr_interval(\
1712                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1713         uint16_t msix_intr, i;
1714
1715         if (rte_intr_allow_others(intr_handle))
1716                 for (i = 0; i < vsi->nb_msix; i++) {
1717                         msix_intr = vsi->msix_intr + i;
1718                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1719                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1720                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1721                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1722                                 (interval <<
1723                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1724                 }
1725         else
1726                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1727                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1728                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1729                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1730                                (interval <<
1731                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1732
1733         I40E_WRITE_FLUSH(hw);
1734 }
1735
1736 static void
1737 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1738 {
1739         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743         uint16_t msix_intr, i;
1744
1745         if (rte_intr_allow_others(intr_handle))
1746                 for (i = 0; i < vsi->nb_msix; i++) {
1747                         msix_intr = vsi->msix_intr + i;
1748                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1749                                        0);
1750                 }
1751         else
1752                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1753
1754         I40E_WRITE_FLUSH(hw);
1755 }
1756
1757 static inline uint8_t
1758 i40e_parse_link_speeds(uint16_t link_speeds)
1759 {
1760         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1761
1762         if (link_speeds & ETH_LINK_SPEED_40G)
1763                 link_speed |= I40E_LINK_SPEED_40GB;
1764         if (link_speeds & ETH_LINK_SPEED_25G)
1765                 link_speed |= I40E_LINK_SPEED_25GB;
1766         if (link_speeds & ETH_LINK_SPEED_20G)
1767                 link_speed |= I40E_LINK_SPEED_20GB;
1768         if (link_speeds & ETH_LINK_SPEED_10G)
1769                 link_speed |= I40E_LINK_SPEED_10GB;
1770         if (link_speeds & ETH_LINK_SPEED_1G)
1771                 link_speed |= I40E_LINK_SPEED_1GB;
1772         if (link_speeds & ETH_LINK_SPEED_100M)
1773                 link_speed |= I40E_LINK_SPEED_100MB;
1774
1775         return link_speed;
1776 }
1777
1778 static int
1779 i40e_phy_conf_link(struct i40e_hw *hw,
1780                    uint8_t abilities,
1781                    uint8_t force_speed)
1782 {
1783         enum i40e_status_code status;
1784         struct i40e_aq_get_phy_abilities_resp phy_ab;
1785         struct i40e_aq_set_phy_config phy_conf;
1786         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1787                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1788                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1789                         I40E_AQ_PHY_FLAG_LOW_POWER;
1790         const uint8_t advt = I40E_LINK_SPEED_40GB |
1791                         I40E_LINK_SPEED_25GB |
1792                         I40E_LINK_SPEED_10GB |
1793                         I40E_LINK_SPEED_1GB |
1794                         I40E_LINK_SPEED_100MB;
1795         int ret = -ENOTSUP;
1796
1797
1798         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1799                                               NULL);
1800         if (status)
1801                 return ret;
1802
1803         memset(&phy_conf, 0, sizeof(phy_conf));
1804
1805         /* bits 0-2 use the values from get_phy_abilities_resp */
1806         abilities &= ~mask;
1807         abilities |= phy_ab.abilities & mask;
1808
1809         /* update ablities and speed */
1810         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1811                 phy_conf.link_speed = advt;
1812         else
1813                 phy_conf.link_speed = force_speed;
1814
1815         phy_conf.abilities = abilities;
1816
1817         /* use get_phy_abilities_resp value for the rest */
1818         phy_conf.phy_type = phy_ab.phy_type;
1819         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1820         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1821         phy_conf.eee_capability = phy_ab.eee_capability;
1822         phy_conf.eeer = phy_ab.eeer_val;
1823         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1824
1825         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1826                     phy_ab.abilities, phy_ab.link_speed);
1827         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1828                     phy_conf.abilities, phy_conf.link_speed);
1829
1830         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1831         if (status)
1832                 return ret;
1833
1834         return I40E_SUCCESS;
1835 }
1836
1837 static int
1838 i40e_apply_link_speed(struct rte_eth_dev *dev)
1839 {
1840         uint8_t speed;
1841         uint8_t abilities = 0;
1842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         struct rte_eth_conf *conf = &dev->data->dev_conf;
1844
1845         speed = i40e_parse_link_speeds(conf->link_speeds);
1846         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1847         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1848                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1849         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1850
1851         /* Skip changing speed on 40G interfaces, FW does not support */
1852         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1853                 speed =  I40E_LINK_SPEED_UNKNOWN;
1854                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1855         }
1856
1857         return i40e_phy_conf_link(hw, abilities, speed);
1858 }
1859
1860 static int
1861 i40e_dev_start(struct rte_eth_dev *dev)
1862 {
1863         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         struct i40e_vsi *main_vsi = pf->main_vsi;
1866         int ret, i;
1867         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869         uint32_t intr_vector = 0;
1870
1871         hw->adapter_stopped = 0;
1872
1873         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1874                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1875                              dev->data->port_id);
1876                 return -EINVAL;
1877         }
1878
1879         rte_intr_disable(intr_handle);
1880
1881         if ((rte_intr_cap_multiple(intr_handle) ||
1882              !RTE_ETH_DEV_SRIOV(dev).active) &&
1883             dev->data->dev_conf.intr_conf.rxq != 0) {
1884                 intr_vector = dev->data->nb_rx_queues;
1885                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1886                 if (ret)
1887                         return ret;
1888         }
1889
1890         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1891                 intr_handle->intr_vec =
1892                         rte_zmalloc("intr_vec",
1893                                     dev->data->nb_rx_queues * sizeof(int),
1894                                     0);
1895                 if (!intr_handle->intr_vec) {
1896                         PMD_INIT_LOG(ERR,
1897                                 "Failed to allocate %d rx_queues intr_vec",
1898                                 dev->data->nb_rx_queues);
1899                         return -ENOMEM;
1900                 }
1901         }
1902
1903         /* Initialize VSI */
1904         ret = i40e_dev_rxtx_init(pf);
1905         if (ret != I40E_SUCCESS) {
1906                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1907                 goto err_up;
1908         }
1909
1910         /* Map queues with MSIX interrupt */
1911         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1912                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1913         i40e_vsi_queues_bind_intr(main_vsi);
1914         i40e_vsi_enable_queues_intr(main_vsi);
1915
1916         /* Map VMDQ VSI queues with MSIX interrupt */
1917         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1918                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1919                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1920                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1921         }
1922
1923         /* enable FDIR MSIX interrupt */
1924         if (pf->fdir.fdir_vsi) {
1925                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1926                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1927         }
1928
1929         /* Enable all queues which have been configured */
1930         ret = i40e_dev_switch_queues(pf, TRUE);
1931         if (ret != I40E_SUCCESS) {
1932                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1933                 goto err_up;
1934         }
1935
1936         /* Enable receiving broadcast packets */
1937         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1938         if (ret != I40E_SUCCESS)
1939                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1940
1941         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1943                                                 true, NULL);
1944                 if (ret != I40E_SUCCESS)
1945                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1946         }
1947
1948         /* Apply link configure */
1949         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1950                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1951                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1952                                 ETH_LINK_SPEED_40G)) {
1953                 PMD_DRV_LOG(ERR, "Invalid link setting");
1954                 goto err_up;
1955         }
1956         ret = i40e_apply_link_speed(dev);
1957         if (I40E_SUCCESS != ret) {
1958                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1959                 goto err_up;
1960         }
1961
1962         if (!rte_intr_allow_others(intr_handle)) {
1963                 rte_intr_callback_unregister(intr_handle,
1964                                              i40e_dev_interrupt_handler,
1965                                              (void *)dev);
1966                 /* configure and enable device interrupt */
1967                 i40e_pf_config_irq0(hw, FALSE);
1968                 i40e_pf_enable_irq0(hw);
1969
1970                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1971                         PMD_INIT_LOG(INFO,
1972                                 "lsc won't enable because of no intr multiplex");
1973         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1974                 ret = i40e_aq_set_phy_int_mask(hw,
1975                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1976                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1977                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1978                 if (ret != I40E_SUCCESS)
1979                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1980
1981                 /* Call get_link_info aq commond to enable LSE */
1982                 i40e_dev_link_update(dev, 0);
1983         }
1984
1985         /* enable uio intr after callback register */
1986         rte_intr_enable(intr_handle);
1987
1988         i40e_filter_restore(pf);
1989
1990         return I40E_SUCCESS;
1991
1992 err_up:
1993         i40e_dev_switch_queues(pf, FALSE);
1994         i40e_dev_clear_queues(dev);
1995
1996         return ret;
1997 }
1998
1999 static void
2000 i40e_dev_stop(struct rte_eth_dev *dev)
2001 {
2002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003         struct i40e_vsi *main_vsi = pf->main_vsi;
2004         struct i40e_mirror_rule *p_mirror;
2005         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2007         int i;
2008
2009         /* Disable all queues */
2010         i40e_dev_switch_queues(pf, FALSE);
2011
2012         /* un-map queues with interrupt registers */
2013         i40e_vsi_disable_queues_intr(main_vsi);
2014         i40e_vsi_queues_unbind_intr(main_vsi);
2015
2016         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2018                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2019         }
2020
2021         if (pf->fdir.fdir_vsi) {
2022                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2023                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2024         }
2025         /* Clear all queues and release memory */
2026         i40e_dev_clear_queues(dev);
2027
2028         /* Set link down */
2029         i40e_dev_set_link_down(dev);
2030
2031         /* Remove all mirror rules */
2032         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2033                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2034                 rte_free(p_mirror);
2035         }
2036         pf->nb_mirror_rule = 0;
2037
2038         if (!rte_intr_allow_others(intr_handle))
2039                 /* resume to the default handler */
2040                 rte_intr_callback_register(intr_handle,
2041                                            i40e_dev_interrupt_handler,
2042                                            (void *)dev);
2043
2044         /* Clean datapath event and queue/vec mapping */
2045         rte_intr_efd_disable(intr_handle);
2046         if (intr_handle->intr_vec) {
2047                 rte_free(intr_handle->intr_vec);
2048                 intr_handle->intr_vec = NULL;
2049         }
2050 }
2051
2052 static void
2053 i40e_dev_close(struct rte_eth_dev *dev)
2054 {
2055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2059         uint32_t reg;
2060         int i;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         i40e_dev_stop(dev);
2065         hw->adapter_stopped = 1;
2066         i40e_dev_free_queues(dev);
2067
2068         /* Disable interrupt */
2069         i40e_pf_disable_irq0(hw);
2070         rte_intr_disable(intr_handle);
2071
2072         /* shutdown and destroy the HMC */
2073         i40e_shutdown_lan_hmc(hw);
2074
2075         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2076                 i40e_vsi_release(pf->vmdq[i].vsi);
2077                 pf->vmdq[i].vsi = NULL;
2078         }
2079         rte_free(pf->vmdq);
2080         pf->vmdq = NULL;
2081
2082         /* release all the existing VSIs and VEBs */
2083         i40e_fdir_teardown(pf);
2084         i40e_vsi_release(pf->main_vsi);
2085
2086         /* shutdown the adminq */
2087         i40e_aq_queue_shutdown(hw, true);
2088         i40e_shutdown_adminq(hw);
2089
2090         i40e_res_pool_destroy(&pf->qp_pool);
2091         i40e_res_pool_destroy(&pf->msix_pool);
2092
2093         /* force a PF reset to clean anything leftover */
2094         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2095         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2096                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static void
2101 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2102 {
2103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct i40e_vsi *vsi = pf->main_vsi;
2106         int status;
2107
2108         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2109                                                      true, NULL, true);
2110         if (status != I40E_SUCCESS)
2111                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2112
2113         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2114                                                         TRUE, NULL);
2115         if (status != I40E_SUCCESS)
2116                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2117
2118 }
2119
2120 static void
2121 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2122 {
2123         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct i40e_vsi *vsi = pf->main_vsi;
2126         int status;
2127
2128         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2129                                                      false, NULL, true);
2130         if (status != I40E_SUCCESS)
2131                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2132
2133         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2134                                                         false, NULL);
2135         if (status != I40E_SUCCESS)
2136                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2137 }
2138
2139 static void
2140 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2141 {
2142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct i40e_vsi *vsi = pf->main_vsi;
2145         int ret;
2146
2147         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2148         if (ret != I40E_SUCCESS)
2149                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2150 }
2151
2152 static void
2153 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2154 {
2155         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         struct i40e_vsi *vsi = pf->main_vsi;
2158         int ret;
2159
2160         if (dev->data->promiscuous == 1)
2161                 return; /* must remain in all_multicast mode */
2162
2163         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2164                                 vsi->seid, FALSE, NULL);
2165         if (ret != I40E_SUCCESS)
2166                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2167 }
2168
2169 /*
2170  * Set device link up.
2171  */
2172 static int
2173 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2174 {
2175         /* re-apply link speed setting */
2176         return i40e_apply_link_speed(dev);
2177 }
2178
2179 /*
2180  * Set device link down.
2181  */
2182 static int
2183 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2184 {
2185         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2186         uint8_t abilities = 0;
2187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188
2189         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2190         return i40e_phy_conf_link(hw, abilities, speed);
2191 }
2192
2193 int
2194 i40e_dev_link_update(struct rte_eth_dev *dev,
2195                      int wait_to_complete)
2196 {
2197 #define CHECK_INTERVAL 100  /* 100ms */
2198 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct i40e_link_status link_status;
2201         struct rte_eth_link link, old;
2202         int status;
2203         unsigned rep_cnt = MAX_REPEAT_TIME;
2204         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2205
2206         memset(&link, 0, sizeof(link));
2207         memset(&old, 0, sizeof(old));
2208         memset(&link_status, 0, sizeof(link_status));
2209         rte_i40e_dev_atomic_read_link_status(dev, &old);
2210
2211         do {
2212                 /* Get link status information from hardware */
2213                 status = i40e_aq_get_link_info(hw, enable_lse,
2214                                                 &link_status, NULL);
2215                 if (status != I40E_SUCCESS) {
2216                         link.link_speed = ETH_SPEED_NUM_100M;
2217                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2218                         PMD_DRV_LOG(ERR, "Failed to get link info");
2219                         goto out;
2220                 }
2221
2222                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2223                 if (!wait_to_complete)
2224                         break;
2225
2226                 rte_delay_ms(CHECK_INTERVAL);
2227         } while (!link.link_status && rep_cnt--);
2228
2229         if (!link.link_status)
2230                 goto out;
2231
2232         /* i40e uses full duplex only */
2233         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2234
2235         /* Parse the link status */
2236         switch (link_status.link_speed) {
2237         case I40E_LINK_SPEED_100MB:
2238                 link.link_speed = ETH_SPEED_NUM_100M;
2239                 break;
2240         case I40E_LINK_SPEED_1GB:
2241                 link.link_speed = ETH_SPEED_NUM_1G;
2242                 break;
2243         case I40E_LINK_SPEED_10GB:
2244                 link.link_speed = ETH_SPEED_NUM_10G;
2245                 break;
2246         case I40E_LINK_SPEED_20GB:
2247                 link.link_speed = ETH_SPEED_NUM_20G;
2248                 break;
2249         case I40E_LINK_SPEED_25GB:
2250                 link.link_speed = ETH_SPEED_NUM_25G;
2251                 break;
2252         case I40E_LINK_SPEED_40GB:
2253                 link.link_speed = ETH_SPEED_NUM_40G;
2254                 break;
2255         default:
2256                 link.link_speed = ETH_SPEED_NUM_100M;
2257                 break;
2258         }
2259
2260         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2261                         ETH_LINK_SPEED_FIXED);
2262
2263 out:
2264         rte_i40e_dev_atomic_write_link_status(dev, &link);
2265         if (link.link_status == old.link_status)
2266                 return -1;
2267
2268         return 0;
2269 }
2270
2271 /* Get all the statistics of a VSI */
2272 void
2273 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2274 {
2275         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2276         struct i40e_eth_stats *nes = &vsi->eth_stats;
2277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2278         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2279
2280         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2281                             vsi->offset_loaded, &oes->rx_bytes,
2282                             &nes->rx_bytes);
2283         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2284                             vsi->offset_loaded, &oes->rx_unicast,
2285                             &nes->rx_unicast);
2286         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2287                             vsi->offset_loaded, &oes->rx_multicast,
2288                             &nes->rx_multicast);
2289         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2290                             vsi->offset_loaded, &oes->rx_broadcast,
2291                             &nes->rx_broadcast);
2292         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2293                             &oes->rx_discards, &nes->rx_discards);
2294         /* GLV_REPC not supported */
2295         /* GLV_RMPC not supported */
2296         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2297                             &oes->rx_unknown_protocol,
2298                             &nes->rx_unknown_protocol);
2299         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2300                             vsi->offset_loaded, &oes->tx_bytes,
2301                             &nes->tx_bytes);
2302         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2303                             vsi->offset_loaded, &oes->tx_unicast,
2304                             &nes->tx_unicast);
2305         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2306                             vsi->offset_loaded, &oes->tx_multicast,
2307                             &nes->tx_multicast);
2308         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2309                             vsi->offset_loaded,  &oes->tx_broadcast,
2310                             &nes->tx_broadcast);
2311         /* GLV_TDPC not supported */
2312         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2313                             &oes->tx_errors, &nes->tx_errors);
2314         vsi->offset_loaded = true;
2315
2316         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2317                     vsi->vsi_id);
2318         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2319         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2320         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2321         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2322         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2323         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2324                     nes->rx_unknown_protocol);
2325         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2326         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2327         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2328         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2329         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2330         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2331         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2332                     vsi->vsi_id);
2333 }
2334
2335 static void
2336 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2337 {
2338         unsigned int i;
2339         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2340         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2341
2342         /* Get statistics of struct i40e_eth_stats */
2343         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2344                             I40E_GLPRT_GORCL(hw->port),
2345                             pf->offset_loaded, &os->eth.rx_bytes,
2346                             &ns->eth.rx_bytes);
2347         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2348                             I40E_GLPRT_UPRCL(hw->port),
2349                             pf->offset_loaded, &os->eth.rx_unicast,
2350                             &ns->eth.rx_unicast);
2351         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2352                             I40E_GLPRT_MPRCL(hw->port),
2353                             pf->offset_loaded, &os->eth.rx_multicast,
2354                             &ns->eth.rx_multicast);
2355         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2356                             I40E_GLPRT_BPRCL(hw->port),
2357                             pf->offset_loaded, &os->eth.rx_broadcast,
2358                             &ns->eth.rx_broadcast);
2359         /* Workaround: CRC size should not be included in byte statistics,
2360          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2361          */
2362         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2363                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2364
2365         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2366                             pf->offset_loaded, &os->eth.rx_discards,
2367                             &ns->eth.rx_discards);
2368         /* GLPRT_REPC not supported */
2369         /* GLPRT_RMPC not supported */
2370         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2371                             pf->offset_loaded,
2372                             &os->eth.rx_unknown_protocol,
2373                             &ns->eth.rx_unknown_protocol);
2374         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2375                             I40E_GLPRT_GOTCL(hw->port),
2376                             pf->offset_loaded, &os->eth.tx_bytes,
2377                             &ns->eth.tx_bytes);
2378         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2379                             I40E_GLPRT_UPTCL(hw->port),
2380                             pf->offset_loaded, &os->eth.tx_unicast,
2381                             &ns->eth.tx_unicast);
2382         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2383                             I40E_GLPRT_MPTCL(hw->port),
2384                             pf->offset_loaded, &os->eth.tx_multicast,
2385                             &ns->eth.tx_multicast);
2386         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2387                             I40E_GLPRT_BPTCL(hw->port),
2388                             pf->offset_loaded, &os->eth.tx_broadcast,
2389                             &ns->eth.tx_broadcast);
2390         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2391                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2392         /* GLPRT_TEPC not supported */
2393
2394         /* additional port specific stats */
2395         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2396                             pf->offset_loaded, &os->tx_dropped_link_down,
2397                             &ns->tx_dropped_link_down);
2398         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2399                             pf->offset_loaded, &os->crc_errors,
2400                             &ns->crc_errors);
2401         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2402                             pf->offset_loaded, &os->illegal_bytes,
2403                             &ns->illegal_bytes);
2404         /* GLPRT_ERRBC not supported */
2405         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2406                             pf->offset_loaded, &os->mac_local_faults,
2407                             &ns->mac_local_faults);
2408         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2409                             pf->offset_loaded, &os->mac_remote_faults,
2410                             &ns->mac_remote_faults);
2411         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2412                             pf->offset_loaded, &os->rx_length_errors,
2413                             &ns->rx_length_errors);
2414         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2415                             pf->offset_loaded, &os->link_xon_rx,
2416                             &ns->link_xon_rx);
2417         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2418                             pf->offset_loaded, &os->link_xoff_rx,
2419                             &ns->link_xoff_rx);
2420         for (i = 0; i < 8; i++) {
2421                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2422                                     pf->offset_loaded,
2423                                     &os->priority_xon_rx[i],
2424                                     &ns->priority_xon_rx[i]);
2425                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2426                                     pf->offset_loaded,
2427                                     &os->priority_xoff_rx[i],
2428                                     &ns->priority_xoff_rx[i]);
2429         }
2430         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2431                             pf->offset_loaded, &os->link_xon_tx,
2432                             &ns->link_xon_tx);
2433         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2434                             pf->offset_loaded, &os->link_xoff_tx,
2435                             &ns->link_xoff_tx);
2436         for (i = 0; i < 8; i++) {
2437                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2438                                     pf->offset_loaded,
2439                                     &os->priority_xon_tx[i],
2440                                     &ns->priority_xon_tx[i]);
2441                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2442                                     pf->offset_loaded,
2443                                     &os->priority_xoff_tx[i],
2444                                     &ns->priority_xoff_tx[i]);
2445                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2446                                     pf->offset_loaded,
2447                                     &os->priority_xon_2_xoff[i],
2448                                     &ns->priority_xon_2_xoff[i]);
2449         }
2450         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2451                             I40E_GLPRT_PRC64L(hw->port),
2452                             pf->offset_loaded, &os->rx_size_64,
2453                             &ns->rx_size_64);
2454         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2455                             I40E_GLPRT_PRC127L(hw->port),
2456                             pf->offset_loaded, &os->rx_size_127,
2457                             &ns->rx_size_127);
2458         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2459                             I40E_GLPRT_PRC255L(hw->port),
2460                             pf->offset_loaded, &os->rx_size_255,
2461                             &ns->rx_size_255);
2462         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2463                             I40E_GLPRT_PRC511L(hw->port),
2464                             pf->offset_loaded, &os->rx_size_511,
2465                             &ns->rx_size_511);
2466         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2467                             I40E_GLPRT_PRC1023L(hw->port),
2468                             pf->offset_loaded, &os->rx_size_1023,
2469                             &ns->rx_size_1023);
2470         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2471                             I40E_GLPRT_PRC1522L(hw->port),
2472                             pf->offset_loaded, &os->rx_size_1522,
2473                             &ns->rx_size_1522);
2474         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2475                             I40E_GLPRT_PRC9522L(hw->port),
2476                             pf->offset_loaded, &os->rx_size_big,
2477                             &ns->rx_size_big);
2478         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2479                             pf->offset_loaded, &os->rx_undersize,
2480                             &ns->rx_undersize);
2481         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2482                             pf->offset_loaded, &os->rx_fragments,
2483                             &ns->rx_fragments);
2484         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2485                             pf->offset_loaded, &os->rx_oversize,
2486                             &ns->rx_oversize);
2487         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2488                             pf->offset_loaded, &os->rx_jabber,
2489                             &ns->rx_jabber);
2490         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2491                             I40E_GLPRT_PTC64L(hw->port),
2492                             pf->offset_loaded, &os->tx_size_64,
2493                             &ns->tx_size_64);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2495                             I40E_GLPRT_PTC127L(hw->port),
2496                             pf->offset_loaded, &os->tx_size_127,
2497                             &ns->tx_size_127);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2499                             I40E_GLPRT_PTC255L(hw->port),
2500                             pf->offset_loaded, &os->tx_size_255,
2501                             &ns->tx_size_255);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2503                             I40E_GLPRT_PTC511L(hw->port),
2504                             pf->offset_loaded, &os->tx_size_511,
2505                             &ns->tx_size_511);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2507                             I40E_GLPRT_PTC1023L(hw->port),
2508                             pf->offset_loaded, &os->tx_size_1023,
2509                             &ns->tx_size_1023);
2510         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2511                             I40E_GLPRT_PTC1522L(hw->port),
2512                             pf->offset_loaded, &os->tx_size_1522,
2513                             &ns->tx_size_1522);
2514         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2515                             I40E_GLPRT_PTC9522L(hw->port),
2516                             pf->offset_loaded, &os->tx_size_big,
2517                             &ns->tx_size_big);
2518         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2519                            pf->offset_loaded,
2520                            &os->fd_sb_match, &ns->fd_sb_match);
2521         /* GLPRT_MSPDC not supported */
2522         /* GLPRT_XEC not supported */
2523
2524         pf->offset_loaded = true;
2525
2526         if (pf->main_vsi)
2527                 i40e_update_vsi_stats(pf->main_vsi);
2528 }
2529
2530 /* Get all statistics of a port */
2531 static void
2532 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2533 {
2534         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2537         unsigned i;
2538
2539         /* call read registers - updates values, now write them to struct */
2540         i40e_read_stats_registers(pf, hw);
2541
2542         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2543                         pf->main_vsi->eth_stats.rx_multicast +
2544                         pf->main_vsi->eth_stats.rx_broadcast -
2545                         pf->main_vsi->eth_stats.rx_discards;
2546         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2547                         pf->main_vsi->eth_stats.tx_multicast +
2548                         pf->main_vsi->eth_stats.tx_broadcast;
2549         stats->ibytes   = ns->eth.rx_bytes;
2550         stats->obytes   = ns->eth.tx_bytes;
2551         stats->oerrors  = ns->eth.tx_errors +
2552                         pf->main_vsi->eth_stats.tx_errors;
2553
2554         /* Rx Errors */
2555         stats->imissed  = ns->eth.rx_discards +
2556                         pf->main_vsi->eth_stats.rx_discards;
2557         stats->ierrors  = ns->crc_errors +
2558                         ns->rx_length_errors + ns->rx_undersize +
2559                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2560
2561         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2562         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2563         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2564         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2565         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2566         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2567         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2568                     ns->eth.rx_unknown_protocol);
2569         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2570         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2571         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2572         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2573         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2574         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2575
2576         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2577                     ns->tx_dropped_link_down);
2578         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2579         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2580                     ns->illegal_bytes);
2581         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2582         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2583                     ns->mac_local_faults);
2584         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2585                     ns->mac_remote_faults);
2586         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2587                     ns->rx_length_errors);
2588         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2589         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2590         for (i = 0; i < 8; i++) {
2591                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2592                                 i, ns->priority_xon_rx[i]);
2593                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2594                                 i, ns->priority_xoff_rx[i]);
2595         }
2596         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2597         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2598         for (i = 0; i < 8; i++) {
2599                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2600                                 i, ns->priority_xon_tx[i]);
2601                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2602                                 i, ns->priority_xoff_tx[i]);
2603                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2604                                 i, ns->priority_xon_2_xoff[i]);
2605         }
2606         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2607         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2608         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2609         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2610         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2611         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2612         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2613         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2614         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2615         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2616         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2617         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2618         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2619         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2620         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2621         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2622         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2623         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2624         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2625                         ns->mac_short_packet_dropped);
2626         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2627                     ns->checksum_error);
2628         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2629         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2630 }
2631
2632 /* Reset the statistics */
2633 static void
2634 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2635 {
2636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638
2639         /* Mark PF and VSI stats to update the offset, aka "reset" */
2640         pf->offset_loaded = false;
2641         if (pf->main_vsi)
2642                 pf->main_vsi->offset_loaded = false;
2643
2644         /* read the stats, reading current register values into offset */
2645         i40e_read_stats_registers(pf, hw);
2646 }
2647
2648 static uint32_t
2649 i40e_xstats_calc_num(void)
2650 {
2651         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2652                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2653                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2654 }
2655
2656 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2657                                      struct rte_eth_xstat_name *xstats_names,
2658                                      __rte_unused unsigned limit)
2659 {
2660         unsigned count = 0;
2661         unsigned i, prio;
2662
2663         if (xstats_names == NULL)
2664                 return i40e_xstats_calc_num();
2665
2666         /* Note: limit checked in rte_eth_xstats_names() */
2667
2668         /* Get stats from i40e_eth_stats struct */
2669         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2670                 snprintf(xstats_names[count].name,
2671                          sizeof(xstats_names[count].name),
2672                          "%s", rte_i40e_stats_strings[i].name);
2673                 count++;
2674         }
2675
2676         /* Get individiual stats from i40e_hw_port struct */
2677         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2678                 snprintf(xstats_names[count].name,
2679                         sizeof(xstats_names[count].name),
2680                          "%s", rte_i40e_hw_port_strings[i].name);
2681                 count++;
2682         }
2683
2684         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2685                 for (prio = 0; prio < 8; prio++) {
2686                         snprintf(xstats_names[count].name,
2687                                  sizeof(xstats_names[count].name),
2688                                  "rx_priority%u_%s", prio,
2689                                  rte_i40e_rxq_prio_strings[i].name);
2690                         count++;
2691                 }
2692         }
2693
2694         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2695                 for (prio = 0; prio < 8; prio++) {
2696                         snprintf(xstats_names[count].name,
2697                                  sizeof(xstats_names[count].name),
2698                                  "tx_priority%u_%s", prio,
2699                                  rte_i40e_txq_prio_strings[i].name);
2700                         count++;
2701                 }
2702         }
2703         return count;
2704 }
2705
2706 static int
2707 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2708                     unsigned n)
2709 {
2710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         unsigned i, count, prio;
2713         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2714
2715         count = i40e_xstats_calc_num();
2716         if (n < count)
2717                 return count;
2718
2719         i40e_read_stats_registers(pf, hw);
2720
2721         if (xstats == NULL)
2722                 return 0;
2723
2724         count = 0;
2725
2726         /* Get stats from i40e_eth_stats struct */
2727         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2728                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2729                         rte_i40e_stats_strings[i].offset);
2730                 xstats[count].id = count;
2731                 count++;
2732         }
2733
2734         /* Get individiual stats from i40e_hw_port struct */
2735         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2736                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2737                         rte_i40e_hw_port_strings[i].offset);
2738                 xstats[count].id = count;
2739                 count++;
2740         }
2741
2742         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2743                 for (prio = 0; prio < 8; prio++) {
2744                         xstats[count].value =
2745                                 *(uint64_t *)(((char *)hw_stats) +
2746                                 rte_i40e_rxq_prio_strings[i].offset +
2747                                 (sizeof(uint64_t) * prio));
2748                         xstats[count].id = count;
2749                         count++;
2750                 }
2751         }
2752
2753         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2754                 for (prio = 0; prio < 8; prio++) {
2755                         xstats[count].value =
2756                                 *(uint64_t *)(((char *)hw_stats) +
2757                                 rte_i40e_txq_prio_strings[i].offset +
2758                                 (sizeof(uint64_t) * prio));
2759                         xstats[count].id = count;
2760                         count++;
2761                 }
2762         }
2763
2764         return count;
2765 }
2766
2767 static int
2768 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2769                                  __rte_unused uint16_t queue_id,
2770                                  __rte_unused uint8_t stat_idx,
2771                                  __rte_unused uint8_t is_rx)
2772 {
2773         PMD_INIT_FUNC_TRACE();
2774
2775         return -ENOSYS;
2776 }
2777
2778 static int
2779 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         u32 full_ver;
2783         u8 ver, patch;
2784         u16 build;
2785         int ret;
2786
2787         full_ver = hw->nvm.oem_ver;
2788         ver = (u8)(full_ver >> 24);
2789         build = (u16)((full_ver >> 8) & 0xffff);
2790         patch = (u8)(full_ver & 0xff);
2791
2792         ret = snprintf(fw_version, fw_size,
2793                  "%d.%d%d 0x%08x %d.%d.%d",
2794                  ((hw->nvm.version >> 12) & 0xf),
2795                  ((hw->nvm.version >> 4) & 0xff),
2796                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2797                  ver, build, patch);
2798
2799         ret += 1; /* add the size of '\0' */
2800         if (fw_size < (u32)ret)
2801                 return ret;
2802         else
2803                 return 0;
2804 }
2805
2806 static void
2807 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2808 {
2809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct i40e_vsi *vsi = pf->main_vsi;
2812         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2813
2814         dev_info->pci_dev = pci_dev;
2815         dev_info->max_rx_queues = vsi->nb_qps;
2816         dev_info->max_tx_queues = vsi->nb_qps;
2817         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2818         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2819         dev_info->max_mac_addrs = vsi->max_macaddrs;
2820         dev_info->max_vfs = pci_dev->max_vfs;
2821         dev_info->rx_offload_capa =
2822                 DEV_RX_OFFLOAD_VLAN_STRIP |
2823                 DEV_RX_OFFLOAD_QINQ_STRIP |
2824                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2825                 DEV_RX_OFFLOAD_UDP_CKSUM |
2826                 DEV_RX_OFFLOAD_TCP_CKSUM;
2827         dev_info->tx_offload_capa =
2828                 DEV_TX_OFFLOAD_VLAN_INSERT |
2829                 DEV_TX_OFFLOAD_QINQ_INSERT |
2830                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2831                 DEV_TX_OFFLOAD_UDP_CKSUM |
2832                 DEV_TX_OFFLOAD_TCP_CKSUM |
2833                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2834                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2835                 DEV_TX_OFFLOAD_TCP_TSO |
2836                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2837                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2838                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2839                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2840         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2841                                                 sizeof(uint32_t);
2842         dev_info->reta_size = pf->hash_lut_size;
2843         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2844
2845         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2846                 .rx_thresh = {
2847                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2848                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2849                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2850                 },
2851                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2852                 .rx_drop_en = 0,
2853         };
2854
2855         dev_info->default_txconf = (struct rte_eth_txconf) {
2856                 .tx_thresh = {
2857                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2858                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2859                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2860                 },
2861                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2862                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2863                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2864                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2865         };
2866
2867         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2868                 .nb_max = I40E_MAX_RING_DESC,
2869                 .nb_min = I40E_MIN_RING_DESC,
2870                 .nb_align = I40E_ALIGN_RING_DESC,
2871         };
2872
2873         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2874                 .nb_max = I40E_MAX_RING_DESC,
2875                 .nb_min = I40E_MIN_RING_DESC,
2876                 .nb_align = I40E_ALIGN_RING_DESC,
2877                 .nb_seg_max = I40E_TX_MAX_SEG,
2878                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2879         };
2880
2881         if (pf->flags & I40E_FLAG_VMDQ) {
2882                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2883                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2884                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2885                                                 pf->max_nb_vmdq_vsi;
2886                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2887                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2888                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2889         }
2890
2891         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2892                 /* For XL710 */
2893                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2894         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2895                 /* For XXV710 */
2896                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2897         else
2898                 /* For X710 */
2899                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2900 }
2901
2902 static int
2903 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2904 {
2905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2906         struct i40e_vsi *vsi = pf->main_vsi;
2907         PMD_INIT_FUNC_TRACE();
2908
2909         if (on)
2910                 return i40e_vsi_add_vlan(vsi, vlan_id);
2911         else
2912                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2913 }
2914
2915 static int
2916 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2917                    enum rte_vlan_type vlan_type,
2918                    uint16_t tpid)
2919 {
2920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint64_t reg_r = 0, reg_w = 0;
2922         uint16_t reg_id = 0;
2923         int ret = 0;
2924         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2925
2926         switch (vlan_type) {
2927         case ETH_VLAN_TYPE_OUTER:
2928                 if (qinq)
2929                         reg_id = 2;
2930                 else
2931                         reg_id = 3;
2932                 break;
2933         case ETH_VLAN_TYPE_INNER:
2934                 if (qinq)
2935                         reg_id = 3;
2936                 else {
2937                         ret = -EINVAL;
2938                         PMD_DRV_LOG(ERR,
2939                                 "Unsupported vlan type in single vlan.");
2940                         return ret;
2941                 }
2942                 break;
2943         default:
2944                 ret = -EINVAL;
2945                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2946                 return ret;
2947         }
2948         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2949                                           &reg_r, NULL);
2950         if (ret != I40E_SUCCESS) {
2951                 PMD_DRV_LOG(ERR,
2952                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2953                            reg_id);
2954                 ret = -EIO;
2955                 return ret;
2956         }
2957         PMD_DRV_LOG(DEBUG,
2958                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2959                 reg_id, reg_r);
2960
2961         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2962         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2963         if (reg_r == reg_w) {
2964                 ret = 0;
2965                 PMD_DRV_LOG(DEBUG, "No need to write");
2966                 return ret;
2967         }
2968
2969         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2970                                            reg_w, NULL);
2971         if (ret != I40E_SUCCESS) {
2972                 ret = -EIO;
2973                 PMD_DRV_LOG(ERR,
2974                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2975                         reg_id);
2976                 return ret;
2977         }
2978         PMD_DRV_LOG(DEBUG,
2979                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2980                 reg_w, reg_id);
2981
2982         return ret;
2983 }
2984
2985 static void
2986 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2987 {
2988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2989         struct i40e_vsi *vsi = pf->main_vsi;
2990
2991         if (mask & ETH_VLAN_FILTER_MASK) {
2992                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2993                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2994                 else
2995                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2996         }
2997
2998         if (mask & ETH_VLAN_STRIP_MASK) {
2999                 /* Enable or disable VLAN stripping */
3000                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3001                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3002                 else
3003                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3004         }
3005
3006         if (mask & ETH_VLAN_EXTEND_MASK) {
3007                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3008                         i40e_vsi_config_double_vlan(vsi, TRUE);
3009                         /* Set global registers with default ether type value */
3010                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3011                                            ETHER_TYPE_VLAN);
3012                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3013                                            ETHER_TYPE_VLAN);
3014                 }
3015                 else
3016                         i40e_vsi_config_double_vlan(vsi, FALSE);
3017         }
3018 }
3019
3020 static void
3021 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3022                           __rte_unused uint16_t queue,
3023                           __rte_unused int on)
3024 {
3025         PMD_INIT_FUNC_TRACE();
3026 }
3027
3028 static int
3029 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3030 {
3031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032         struct i40e_vsi *vsi = pf->main_vsi;
3033         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3034         struct i40e_vsi_vlan_pvid_info info;
3035
3036         memset(&info, 0, sizeof(info));
3037         info.on = on;
3038         if (info.on)
3039                 info.config.pvid = pvid;
3040         else {
3041                 info.config.reject.tagged =
3042                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3043                 info.config.reject.untagged =
3044                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3045         }
3046
3047         return i40e_vsi_vlan_pvid_set(vsi, &info);
3048 }
3049
3050 static int
3051 i40e_dev_led_on(struct rte_eth_dev *dev)
3052 {
3053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         uint32_t mode = i40e_led_get(hw);
3055
3056         if (mode == 0)
3057                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3058
3059         return 0;
3060 }
3061
3062 static int
3063 i40e_dev_led_off(struct rte_eth_dev *dev)
3064 {
3065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         uint32_t mode = i40e_led_get(hw);
3067
3068         if (mode != 0)
3069                 i40e_led_set(hw, 0, false);
3070
3071         return 0;
3072 }
3073
3074 static int
3075 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3076 {
3077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3079
3080         fc_conf->pause_time = pf->fc_conf.pause_time;
3081         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3082         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3083
3084          /* Return current mode according to actual setting*/
3085         switch (hw->fc.current_mode) {
3086         case I40E_FC_FULL:
3087                 fc_conf->mode = RTE_FC_FULL;
3088                 break;
3089         case I40E_FC_TX_PAUSE:
3090                 fc_conf->mode = RTE_FC_TX_PAUSE;
3091                 break;
3092         case I40E_FC_RX_PAUSE:
3093                 fc_conf->mode = RTE_FC_RX_PAUSE;
3094                 break;
3095         case I40E_FC_NONE:
3096         default:
3097                 fc_conf->mode = RTE_FC_NONE;
3098         };
3099
3100         return 0;
3101 }
3102
3103 static int
3104 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3105 {
3106         uint32_t mflcn_reg, fctrl_reg, reg;
3107         uint32_t max_high_water;
3108         uint8_t i, aq_failure;
3109         int err;
3110         struct i40e_hw *hw;
3111         struct i40e_pf *pf;
3112         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3113                 [RTE_FC_NONE] = I40E_FC_NONE,
3114                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3115                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3116                 [RTE_FC_FULL] = I40E_FC_FULL
3117         };
3118
3119         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3120
3121         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3122         if ((fc_conf->high_water > max_high_water) ||
3123                         (fc_conf->high_water < fc_conf->low_water)) {
3124                 PMD_INIT_LOG(ERR,
3125                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3126                         max_high_water);
3127                 return -EINVAL;
3128         }
3129
3130         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3133
3134         pf->fc_conf.pause_time = fc_conf->pause_time;
3135         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3136         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3137
3138         PMD_INIT_FUNC_TRACE();
3139
3140         /* All the link flow control related enable/disable register
3141          * configuration is handle by the F/W
3142          */
3143         err = i40e_set_fc(hw, &aq_failure, true);
3144         if (err < 0)
3145                 return -ENOSYS;
3146
3147         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3148                 /* Configure flow control refresh threshold,
3149                  * the value for stat_tx_pause_refresh_timer[8]
3150                  * is used for global pause operation.
3151                  */
3152
3153                 I40E_WRITE_REG(hw,
3154                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3155                                pf->fc_conf.pause_time);
3156
3157                 /* configure the timer value included in transmitted pause
3158                  * frame,
3159                  * the value for stat_tx_pause_quanta[8] is used for global
3160                  * pause operation
3161                  */
3162                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3163                                pf->fc_conf.pause_time);
3164
3165                 fctrl_reg = I40E_READ_REG(hw,
3166                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3167
3168                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3169                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3170                 else
3171                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3172
3173                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3174                                fctrl_reg);
3175         } else {
3176                 /* Configure pause time (2 TCs per register) */
3177                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3178                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3179                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3180
3181                 /* Configure flow control refresh threshold value */
3182                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3183                                pf->fc_conf.pause_time / 2);
3184
3185                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3186
3187                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3188                  *depending on configuration
3189                  */
3190                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3191                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3192                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3193                 } else {
3194                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3195                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3196                 }
3197
3198                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3199         }
3200
3201         /* config the water marker both based on the packets and bytes */
3202         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3203                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3204                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3205         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3206                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3207                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3208         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3209                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3210                        << I40E_KILOSHIFT);
3211         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3212                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3213                        << I40E_KILOSHIFT);
3214
3215         I40E_WRITE_FLUSH(hw);
3216
3217         return 0;
3218 }
3219
3220 static int
3221 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3222                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3223 {
3224         PMD_INIT_FUNC_TRACE();
3225
3226         return -ENOSYS;
3227 }
3228
3229 /* Add a MAC address, and update filters */
3230 static void
3231 i40e_macaddr_add(struct rte_eth_dev *dev,
3232                  struct ether_addr *mac_addr,
3233                  __rte_unused uint32_t index,
3234                  uint32_t pool)
3235 {
3236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         struct i40e_mac_filter_info mac_filter;
3238         struct i40e_vsi *vsi;
3239         int ret;
3240
3241         /* If VMDQ not enabled or configured, return */
3242         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3243                           !pf->nb_cfg_vmdq_vsi)) {
3244                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3245                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3246                         pool);
3247                 return;
3248         }
3249
3250         if (pool > pf->nb_cfg_vmdq_vsi) {
3251                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3252                                 pool, pf->nb_cfg_vmdq_vsi);
3253                 return;
3254         }
3255
3256         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3257         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3258                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3259         else
3260                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3261
3262         if (pool == 0)
3263                 vsi = pf->main_vsi;
3264         else
3265                 vsi = pf->vmdq[pool - 1].vsi;
3266
3267         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3268         if (ret != I40E_SUCCESS) {
3269                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3270                 return;
3271         }
3272 }
3273
3274 /* Remove a MAC address, and update filters */
3275 static void
3276 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3277 {
3278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279         struct i40e_vsi *vsi;
3280         struct rte_eth_dev_data *data = dev->data;
3281         struct ether_addr *macaddr;
3282         int ret;
3283         uint32_t i;
3284         uint64_t pool_sel;
3285
3286         macaddr = &(data->mac_addrs[index]);
3287
3288         pool_sel = dev->data->mac_pool_sel[index];
3289
3290         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3291                 if (pool_sel & (1ULL << i)) {
3292                         if (i == 0)
3293                                 vsi = pf->main_vsi;
3294                         else {
3295                                 /* No VMDQ pool enabled or configured */
3296                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3297                                         (i > pf->nb_cfg_vmdq_vsi)) {
3298                                         PMD_DRV_LOG(ERR,
3299                                                 "No VMDQ pool enabled/configured");
3300                                         return;
3301                                 }
3302                                 vsi = pf->vmdq[i - 1].vsi;
3303                         }
3304                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3305
3306                         if (ret) {
3307                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3308                                 return;
3309                         }
3310                 }
3311         }
3312 }
3313
3314 /* Set perfect match or hash match of MAC and VLAN for a VF */
3315 static int
3316 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3317                  struct rte_eth_mac_filter *filter,
3318                  bool add)
3319 {
3320         struct i40e_hw *hw;
3321         struct i40e_mac_filter_info mac_filter;
3322         struct ether_addr old_mac;
3323         struct ether_addr *new_mac;
3324         struct i40e_pf_vf *vf = NULL;
3325         uint16_t vf_id;
3326         int ret;
3327
3328         if (pf == NULL) {
3329                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3330                 return -EINVAL;
3331         }
3332         hw = I40E_PF_TO_HW(pf);
3333
3334         if (filter == NULL) {
3335                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3336                 return -EINVAL;
3337         }
3338
3339         new_mac = &filter->mac_addr;
3340
3341         if (is_zero_ether_addr(new_mac)) {
3342                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3343                 return -EINVAL;
3344         }
3345
3346         vf_id = filter->dst_id;
3347
3348         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3349                 PMD_DRV_LOG(ERR, "Invalid argument.");
3350                 return -EINVAL;
3351         }
3352         vf = &pf->vfs[vf_id];
3353
3354         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3355                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3356                 return -EINVAL;
3357         }
3358
3359         if (add) {
3360                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3361                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3362                                 ETHER_ADDR_LEN);
3363                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3364                                  ETHER_ADDR_LEN);
3365
3366                 mac_filter.filter_type = filter->filter_type;
3367                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3368                 if (ret != I40E_SUCCESS) {
3369                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3370                         return -1;
3371                 }
3372                 ether_addr_copy(new_mac, &pf->dev_addr);
3373         } else {
3374                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3375                                 ETHER_ADDR_LEN);
3376                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3377                 if (ret != I40E_SUCCESS) {
3378                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3379                         return -1;
3380                 }
3381
3382                 /* Clear device address as it has been removed */
3383                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3384                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3385         }
3386
3387         return 0;
3388 }
3389
3390 /* MAC filter handle */
3391 static int
3392 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3393                 void *arg)
3394 {
3395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396         struct rte_eth_mac_filter *filter;
3397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3398         int ret = I40E_NOT_SUPPORTED;
3399
3400         filter = (struct rte_eth_mac_filter *)(arg);
3401
3402         switch (filter_op) {
3403         case RTE_ETH_FILTER_NOP:
3404                 ret = I40E_SUCCESS;
3405                 break;
3406         case RTE_ETH_FILTER_ADD:
3407                 i40e_pf_disable_irq0(hw);
3408                 if (filter->is_vf)
3409                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3410                 i40e_pf_enable_irq0(hw);
3411                 break;
3412         case RTE_ETH_FILTER_DELETE:
3413                 i40e_pf_disable_irq0(hw);
3414                 if (filter->is_vf)
3415                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3416                 i40e_pf_enable_irq0(hw);
3417                 break;
3418         default:
3419                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3420                 ret = I40E_ERR_PARAM;
3421                 break;
3422         }
3423
3424         return ret;
3425 }
3426
3427 static int
3428 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3429 {
3430         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3431         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3432         int ret;
3433
3434         if (!lut)
3435                 return -EINVAL;
3436
3437         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3438                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3439                                           lut, lut_size);
3440                 if (ret) {
3441                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3442                         return ret;
3443                 }
3444         } else {
3445                 uint32_t *lut_dw = (uint32_t *)lut;
3446                 uint16_t i, lut_size_dw = lut_size / 4;
3447
3448                 for (i = 0; i < lut_size_dw; i++)
3449                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3450         }
3451
3452         return 0;
3453 }
3454
3455 static int
3456 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3457 {
3458         struct i40e_pf *pf;
3459         struct i40e_hw *hw;
3460         int ret;
3461
3462         if (!vsi || !lut)
3463                 return -EINVAL;
3464
3465         pf = I40E_VSI_TO_PF(vsi);
3466         hw = I40E_VSI_TO_HW(vsi);
3467
3468         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3469                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3470                                           lut, lut_size);
3471                 if (ret) {
3472                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3473                         return ret;
3474                 }
3475         } else {
3476                 uint32_t *lut_dw = (uint32_t *)lut;
3477                 uint16_t i, lut_size_dw = lut_size / 4;
3478
3479                 for (i = 0; i < lut_size_dw; i++)
3480                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3481                 I40E_WRITE_FLUSH(hw);
3482         }
3483
3484         return 0;
3485 }
3486
3487 static int
3488 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3489                          struct rte_eth_rss_reta_entry64 *reta_conf,
3490                          uint16_t reta_size)
3491 {
3492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493         uint16_t i, lut_size = pf->hash_lut_size;
3494         uint16_t idx, shift;
3495         uint8_t *lut;
3496         int ret;
3497
3498         if (reta_size != lut_size ||
3499                 reta_size > ETH_RSS_RETA_SIZE_512) {
3500                 PMD_DRV_LOG(ERR,
3501                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3502                         reta_size, lut_size);
3503                 return -EINVAL;
3504         }
3505
3506         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3507         if (!lut) {
3508                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3509                 return -ENOMEM;
3510         }
3511         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3512         if (ret)
3513                 goto out;
3514         for (i = 0; i < reta_size; i++) {
3515                 idx = i / RTE_RETA_GROUP_SIZE;
3516                 shift = i % RTE_RETA_GROUP_SIZE;
3517                 if (reta_conf[idx].mask & (1ULL << shift))
3518                         lut[i] = reta_conf[idx].reta[shift];
3519         }
3520         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3521
3522 out:
3523         rte_free(lut);
3524
3525         return ret;
3526 }
3527
3528 static int
3529 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3530                         struct rte_eth_rss_reta_entry64 *reta_conf,
3531                         uint16_t reta_size)
3532 {
3533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534         uint16_t i, lut_size = pf->hash_lut_size;
3535         uint16_t idx, shift;
3536         uint8_t *lut;
3537         int ret;
3538
3539         if (reta_size != lut_size ||
3540                 reta_size > ETH_RSS_RETA_SIZE_512) {
3541                 PMD_DRV_LOG(ERR,
3542                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3543                         reta_size, lut_size);
3544                 return -EINVAL;
3545         }
3546
3547         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3548         if (!lut) {
3549                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3550                 return -ENOMEM;
3551         }
3552
3553         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3554         if (ret)
3555                 goto out;
3556         for (i = 0; i < reta_size; i++) {
3557                 idx = i / RTE_RETA_GROUP_SIZE;
3558                 shift = i % RTE_RETA_GROUP_SIZE;
3559                 if (reta_conf[idx].mask & (1ULL << shift))
3560                         reta_conf[idx].reta[shift] = lut[i];
3561         }
3562
3563 out:
3564         rte_free(lut);
3565
3566         return ret;
3567 }
3568
3569 /**
3570  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3571  * @hw:   pointer to the HW structure
3572  * @mem:  pointer to mem struct to fill out
3573  * @size: size of memory requested
3574  * @alignment: what to align the allocation to
3575  **/
3576 enum i40e_status_code
3577 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3578                         struct i40e_dma_mem *mem,
3579                         u64 size,
3580                         u32 alignment)
3581 {
3582         const struct rte_memzone *mz = NULL;
3583         char z_name[RTE_MEMZONE_NAMESIZE];
3584
3585         if (!mem)
3586                 return I40E_ERR_PARAM;
3587
3588         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3589         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3590                                          alignment, RTE_PGSIZE_2M);
3591         if (!mz)
3592                 return I40E_ERR_NO_MEMORY;
3593
3594         mem->size = size;
3595         mem->va = mz->addr;
3596         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3597         mem->zone = (const void *)mz;
3598         PMD_DRV_LOG(DEBUG,
3599                 "memzone %s allocated with physical address: %"PRIu64,
3600                 mz->name, mem->pa);
3601
3602         return I40E_SUCCESS;
3603 }
3604
3605 /**
3606  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3607  * @hw:   pointer to the HW structure
3608  * @mem:  ptr to mem struct to free
3609  **/
3610 enum i40e_status_code
3611 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3612                     struct i40e_dma_mem *mem)
3613 {
3614         if (!mem)
3615                 return I40E_ERR_PARAM;
3616
3617         PMD_DRV_LOG(DEBUG,
3618                 "memzone %s to be freed with physical address: %"PRIu64,
3619                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3620         rte_memzone_free((const struct rte_memzone *)mem->zone);
3621         mem->zone = NULL;
3622         mem->va = NULL;
3623         mem->pa = (u64)0;
3624
3625         return I40E_SUCCESS;
3626 }
3627
3628 /**
3629  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3630  * @hw:   pointer to the HW structure
3631  * @mem:  pointer to mem struct to fill out
3632  * @size: size of memory requested
3633  **/
3634 enum i40e_status_code
3635 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3636                          struct i40e_virt_mem *mem,
3637                          u32 size)
3638 {
3639         if (!mem)
3640                 return I40E_ERR_PARAM;
3641
3642         mem->size = size;
3643         mem->va = rte_zmalloc("i40e", size, 0);
3644
3645         if (mem->va)
3646                 return I40E_SUCCESS;
3647         else
3648                 return I40E_ERR_NO_MEMORY;
3649 }
3650
3651 /**
3652  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3653  * @hw:   pointer to the HW structure
3654  * @mem:  pointer to mem struct to free
3655  **/
3656 enum i40e_status_code
3657 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3658                      struct i40e_virt_mem *mem)
3659 {
3660         if (!mem)
3661                 return I40E_ERR_PARAM;
3662
3663         rte_free(mem->va);
3664         mem->va = NULL;
3665
3666         return I40E_SUCCESS;
3667 }
3668
3669 void
3670 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3671 {
3672         rte_spinlock_init(&sp->spinlock);
3673 }
3674
3675 void
3676 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3677 {
3678         rte_spinlock_lock(&sp->spinlock);
3679 }
3680
3681 void
3682 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3683 {
3684         rte_spinlock_unlock(&sp->spinlock);
3685 }
3686
3687 void
3688 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3689 {
3690         return;
3691 }
3692
3693 /**
3694  * Get the hardware capabilities, which will be parsed
3695  * and saved into struct i40e_hw.
3696  */
3697 static int
3698 i40e_get_cap(struct i40e_hw *hw)
3699 {
3700         struct i40e_aqc_list_capabilities_element_resp *buf;
3701         uint16_t len, size = 0;
3702         int ret;
3703
3704         /* Calculate a huge enough buff for saving response data temporarily */
3705         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3706                                                 I40E_MAX_CAP_ELE_NUM;
3707         buf = rte_zmalloc("i40e", len, 0);
3708         if (!buf) {
3709                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3710                 return I40E_ERR_NO_MEMORY;
3711         }
3712
3713         /* Get, parse the capabilities and save it to hw */
3714         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3715                         i40e_aqc_opc_list_func_capabilities, NULL);
3716         if (ret != I40E_SUCCESS)
3717                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3718
3719         /* Free the temporary buffer after being used */
3720         rte_free(buf);
3721
3722         return ret;
3723 }
3724
3725 static int
3726 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3727 {
3728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3730         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3731         uint16_t qp_count = 0, vsi_count = 0;
3732
3733         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3734                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3735                 return -EINVAL;
3736         }
3737         /* Add the parameter init for LFC */
3738         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3739         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3740         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3741
3742         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3743         pf->max_num_vsi = hw->func_caps.num_vsis;
3744         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3745         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3746         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3747
3748         /* FDir queue/VSI allocation */
3749         pf->fdir_qp_offset = 0;
3750         if (hw->func_caps.fd) {
3751                 pf->flags |= I40E_FLAG_FDIR;
3752                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3753         } else {
3754                 pf->fdir_nb_qps = 0;
3755         }
3756         qp_count += pf->fdir_nb_qps;
3757         vsi_count += 1;
3758
3759         /* LAN queue/VSI allocation */
3760         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3761         if (!hw->func_caps.rss) {
3762                 pf->lan_nb_qps = 1;
3763         } else {
3764                 pf->flags |= I40E_FLAG_RSS;
3765                 if (hw->mac.type == I40E_MAC_X722)
3766                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3767                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3768         }
3769         qp_count += pf->lan_nb_qps;
3770         vsi_count += 1;
3771
3772         /* VF queue/VSI allocation */
3773         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3774         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3775                 pf->flags |= I40E_FLAG_SRIOV;
3776                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3777                 pf->vf_num = pci_dev->max_vfs;
3778                 PMD_DRV_LOG(DEBUG,
3779                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3780                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3781         } else {
3782                 pf->vf_nb_qps = 0;
3783                 pf->vf_num = 0;
3784         }
3785         qp_count += pf->vf_nb_qps * pf->vf_num;
3786         vsi_count += pf->vf_num;
3787
3788         /* VMDq queue/VSI allocation */
3789         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3790         pf->vmdq_nb_qps = 0;
3791         pf->max_nb_vmdq_vsi = 0;
3792         if (hw->func_caps.vmdq) {
3793                 if (qp_count < hw->func_caps.num_tx_qp &&
3794                         vsi_count < hw->func_caps.num_vsis) {
3795                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3796                                 qp_count) / pf->vmdq_nb_qp_max;
3797
3798                         /* Limit the maximum number of VMDq vsi to the maximum
3799                          * ethdev can support
3800                          */
3801                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3802                                 hw->func_caps.num_vsis - vsi_count);
3803                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3804                                 ETH_64_POOLS);
3805                         if (pf->max_nb_vmdq_vsi) {
3806                                 pf->flags |= I40E_FLAG_VMDQ;
3807                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3808                                 PMD_DRV_LOG(DEBUG,
3809                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3810                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3811                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3812                         } else {
3813                                 PMD_DRV_LOG(INFO,
3814                                         "No enough queues left for VMDq");
3815                         }
3816                 } else {
3817                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3818                 }
3819         }
3820         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3821         vsi_count += pf->max_nb_vmdq_vsi;
3822
3823         if (hw->func_caps.dcb)
3824                 pf->flags |= I40E_FLAG_DCB;
3825
3826         if (qp_count > hw->func_caps.num_tx_qp) {
3827                 PMD_DRV_LOG(ERR,
3828                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3829                         qp_count, hw->func_caps.num_tx_qp);
3830                 return -EINVAL;
3831         }
3832         if (vsi_count > hw->func_caps.num_vsis) {
3833                 PMD_DRV_LOG(ERR,
3834                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3835                         vsi_count, hw->func_caps.num_vsis);
3836                 return -EINVAL;
3837         }
3838
3839         return 0;
3840 }
3841
3842 static int
3843 i40e_pf_get_switch_config(struct i40e_pf *pf)
3844 {
3845         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3846         struct i40e_aqc_get_switch_config_resp *switch_config;
3847         struct i40e_aqc_switch_config_element_resp *element;
3848         uint16_t start_seid = 0, num_reported;
3849         int ret;
3850
3851         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3852                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3853         if (!switch_config) {
3854                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3855                 return -ENOMEM;
3856         }
3857
3858         /* Get the switch configurations */
3859         ret = i40e_aq_get_switch_config(hw, switch_config,
3860                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3861         if (ret != I40E_SUCCESS) {
3862                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3863                 goto fail;
3864         }
3865         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3866         if (num_reported != 1) { /* The number should be 1 */
3867                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3868                 goto fail;
3869         }
3870
3871         /* Parse the switch configuration elements */
3872         element = &(switch_config->element[0]);
3873         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3874                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3875                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3876         } else
3877                 PMD_DRV_LOG(INFO, "Unknown element type");
3878
3879 fail:
3880         rte_free(switch_config);
3881
3882         return ret;
3883 }
3884
3885 static int
3886 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3887                         uint32_t num)
3888 {
3889         struct pool_entry *entry;
3890
3891         if (pool == NULL || num == 0)
3892                 return -EINVAL;
3893
3894         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3895         if (entry == NULL) {
3896                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3897                 return -ENOMEM;
3898         }
3899
3900         /* queue heap initialize */
3901         pool->num_free = num;
3902         pool->num_alloc = 0;
3903         pool->base = base;
3904         LIST_INIT(&pool->alloc_list);
3905         LIST_INIT(&pool->free_list);
3906
3907         /* Initialize element  */
3908         entry->base = 0;
3909         entry->len = num;
3910
3911         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3912         return 0;
3913 }
3914
3915 static void
3916 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3917 {
3918         struct pool_entry *entry, *next_entry;
3919
3920         if (pool == NULL)
3921                 return;
3922
3923         for (entry = LIST_FIRST(&pool->alloc_list);
3924                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3925                         entry = next_entry) {
3926                 LIST_REMOVE(entry, next);
3927                 rte_free(entry);
3928         }
3929
3930         for (entry = LIST_FIRST(&pool->free_list);
3931                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3932                         entry = next_entry) {
3933                 LIST_REMOVE(entry, next);
3934                 rte_free(entry);
3935         }
3936
3937         pool->num_free = 0;
3938         pool->num_alloc = 0;
3939         pool->base = 0;
3940         LIST_INIT(&pool->alloc_list);
3941         LIST_INIT(&pool->free_list);
3942 }
3943
3944 static int
3945 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3946                        uint32_t base)
3947 {
3948         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3949         uint32_t pool_offset;
3950         int insert;
3951
3952         if (pool == NULL) {
3953                 PMD_DRV_LOG(ERR, "Invalid parameter");
3954                 return -EINVAL;
3955         }
3956
3957         pool_offset = base - pool->base;
3958         /* Lookup in alloc list */
3959         LIST_FOREACH(entry, &pool->alloc_list, next) {
3960                 if (entry->base == pool_offset) {
3961                         valid_entry = entry;
3962                         LIST_REMOVE(entry, next);
3963                         break;
3964                 }
3965         }
3966
3967         /* Not find, return */
3968         if (valid_entry == NULL) {
3969                 PMD_DRV_LOG(ERR, "Failed to find entry");
3970                 return -EINVAL;
3971         }
3972
3973         /**
3974          * Found it, move it to free list  and try to merge.
3975          * In order to make merge easier, always sort it by qbase.
3976          * Find adjacent prev and last entries.
3977          */
3978         prev = next = NULL;
3979         LIST_FOREACH(entry, &pool->free_list, next) {
3980                 if (entry->base > valid_entry->base) {
3981                         next = entry;
3982                         break;
3983                 }
3984                 prev = entry;
3985         }
3986
3987         insert = 0;
3988         /* Try to merge with next one*/
3989         if (next != NULL) {
3990                 /* Merge with next one */
3991                 if (valid_entry->base + valid_entry->len == next->base) {
3992                         next->base = valid_entry->base;
3993                         next->len += valid_entry->len;
3994                         rte_free(valid_entry);
3995                         valid_entry = next;
3996                         insert = 1;
3997                 }
3998         }
3999
4000         if (prev != NULL) {
4001                 /* Merge with previous one */
4002                 if (prev->base + prev->len == valid_entry->base) {
4003                         prev->len += valid_entry->len;
4004                         /* If it merge with next one, remove next node */
4005                         if (insert == 1) {
4006                                 LIST_REMOVE(valid_entry, next);
4007                                 rte_free(valid_entry);
4008                         } else {
4009                                 rte_free(valid_entry);
4010                                 insert = 1;
4011                         }
4012                 }
4013         }
4014
4015         /* Not find any entry to merge, insert */
4016         if (insert == 0) {
4017                 if (prev != NULL)
4018                         LIST_INSERT_AFTER(prev, valid_entry, next);
4019                 else if (next != NULL)
4020                         LIST_INSERT_BEFORE(next, valid_entry, next);
4021                 else /* It's empty list, insert to head */
4022                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4023         }
4024
4025         pool->num_free += valid_entry->len;
4026         pool->num_alloc -= valid_entry->len;
4027
4028         return 0;
4029 }
4030
4031 static int
4032 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4033                        uint16_t num)
4034 {
4035         struct pool_entry *entry, *valid_entry;
4036
4037         if (pool == NULL || num == 0) {
4038                 PMD_DRV_LOG(ERR, "Invalid parameter");
4039                 return -EINVAL;
4040         }
4041
4042         if (pool->num_free < num) {
4043                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4044                             num, pool->num_free);
4045                 return -ENOMEM;
4046         }
4047
4048         valid_entry = NULL;
4049         /* Lookup  in free list and find most fit one */
4050         LIST_FOREACH(entry, &pool->free_list, next) {
4051                 if (entry->len >= num) {
4052                         /* Find best one */
4053                         if (entry->len == num) {
4054                                 valid_entry = entry;
4055                                 break;
4056                         }
4057                         if (valid_entry == NULL || valid_entry->len > entry->len)
4058                                 valid_entry = entry;
4059                 }
4060         }
4061
4062         /* Not find one to satisfy the request, return */
4063         if (valid_entry == NULL) {
4064                 PMD_DRV_LOG(ERR, "No valid entry found");
4065                 return -ENOMEM;
4066         }
4067         /**
4068          * The entry have equal queue number as requested,
4069          * remove it from alloc_list.
4070          */
4071         if (valid_entry->len == num) {
4072                 LIST_REMOVE(valid_entry, next);
4073         } else {
4074                 /**
4075                  * The entry have more numbers than requested,
4076                  * create a new entry for alloc_list and minus its
4077                  * queue base and number in free_list.
4078                  */
4079                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4080                 if (entry == NULL) {
4081                         PMD_DRV_LOG(ERR,
4082                                 "Failed to allocate memory for resource pool");
4083                         return -ENOMEM;
4084                 }
4085                 entry->base = valid_entry->base;
4086                 entry->len = num;
4087                 valid_entry->base += num;
4088                 valid_entry->len -= num;
4089                 valid_entry = entry;
4090         }
4091
4092         /* Insert it into alloc list, not sorted */
4093         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4094
4095         pool->num_free -= valid_entry->len;
4096         pool->num_alloc += valid_entry->len;
4097
4098         return valid_entry->base + pool->base;
4099 }
4100
4101 /**
4102  * bitmap_is_subset - Check whether src2 is subset of src1
4103  **/
4104 static inline int
4105 bitmap_is_subset(uint8_t src1, uint8_t src2)
4106 {
4107         return !((src1 ^ src2) & src2);
4108 }
4109
4110 static enum i40e_status_code
4111 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4112 {
4113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4114
4115         /* If DCB is not supported, only default TC is supported */
4116         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4117                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4118                 return I40E_NOT_SUPPORTED;
4119         }
4120
4121         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4122                 PMD_DRV_LOG(ERR,
4123                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4124                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4125                 return I40E_NOT_SUPPORTED;
4126         }
4127         return I40E_SUCCESS;
4128 }
4129
4130 int
4131 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4132                                 struct i40e_vsi_vlan_pvid_info *info)
4133 {
4134         struct i40e_hw *hw;
4135         struct i40e_vsi_context ctxt;
4136         uint8_t vlan_flags = 0;
4137         int ret;
4138
4139         if (vsi == NULL || info == NULL) {
4140                 PMD_DRV_LOG(ERR, "invalid parameters");
4141                 return I40E_ERR_PARAM;
4142         }
4143
4144         if (info->on) {
4145                 vsi->info.pvid = info->config.pvid;
4146                 /**
4147                  * If insert pvid is enabled, only tagged pkts are
4148                  * allowed to be sent out.
4149                  */
4150                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4151                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4152         } else {
4153                 vsi->info.pvid = 0;
4154                 if (info->config.reject.tagged == 0)
4155                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4156
4157                 if (info->config.reject.untagged == 0)
4158                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4159         }
4160         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4161                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4162         vsi->info.port_vlan_flags |= vlan_flags;
4163         vsi->info.valid_sections =
4164                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4165         memset(&ctxt, 0, sizeof(ctxt));
4166         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4167         ctxt.seid = vsi->seid;
4168
4169         hw = I40E_VSI_TO_HW(vsi);
4170         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4171         if (ret != I40E_SUCCESS)
4172                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4173
4174         return ret;
4175 }
4176
4177 static int
4178 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4179 {
4180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4181         int i, ret;
4182         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4183
4184         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4185         if (ret != I40E_SUCCESS)
4186                 return ret;
4187
4188         if (!vsi->seid) {
4189                 PMD_DRV_LOG(ERR, "seid not valid");
4190                 return -EINVAL;
4191         }
4192
4193         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4194         tc_bw_data.tc_valid_bits = enabled_tcmap;
4195         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4196                 tc_bw_data.tc_bw_credits[i] =
4197                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4198
4199         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4200         if (ret != I40E_SUCCESS) {
4201                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4202                 return ret;
4203         }
4204
4205         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4206                                         sizeof(vsi->info.qs_handle));
4207         return I40E_SUCCESS;
4208 }
4209
4210 static enum i40e_status_code
4211 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4212                                  struct i40e_aqc_vsi_properties_data *info,
4213                                  uint8_t enabled_tcmap)
4214 {
4215         enum i40e_status_code ret;
4216         int i, total_tc = 0;
4217         uint16_t qpnum_per_tc, bsf, qp_idx;
4218
4219         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4220         if (ret != I40E_SUCCESS)
4221                 return ret;
4222
4223         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4224                 if (enabled_tcmap & (1 << i))
4225                         total_tc++;
4226         vsi->enabled_tc = enabled_tcmap;
4227
4228         /* Number of queues per enabled TC */
4229         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4230         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4231         bsf = rte_bsf32(qpnum_per_tc);
4232
4233         /* Adjust the queue number to actual queues that can be applied */
4234         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4235                 vsi->nb_qps = qpnum_per_tc * total_tc;
4236
4237         /**
4238          * Configure TC and queue mapping parameters, for enabled TC,
4239          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4240          * default queue will serve it.
4241          */
4242         qp_idx = 0;
4243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4244                 if (vsi->enabled_tc & (1 << i)) {
4245                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4246                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4247                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4248                         qp_idx += qpnum_per_tc;
4249                 } else
4250                         info->tc_mapping[i] = 0;
4251         }
4252
4253         /* Associate queue number with VSI */
4254         if (vsi->type == I40E_VSI_SRIOV) {
4255                 info->mapping_flags |=
4256                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4257                 for (i = 0; i < vsi->nb_qps; i++)
4258                         info->queue_mapping[i] =
4259                                 rte_cpu_to_le_16(vsi->base_queue + i);
4260         } else {
4261                 info->mapping_flags |=
4262                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4263                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4264         }
4265         info->valid_sections |=
4266                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4267
4268         return I40E_SUCCESS;
4269 }
4270
4271 static int
4272 i40e_veb_release(struct i40e_veb *veb)
4273 {
4274         struct i40e_vsi *vsi;
4275         struct i40e_hw *hw;
4276
4277         if (veb == NULL)
4278                 return -EINVAL;
4279
4280         if (!TAILQ_EMPTY(&veb->head)) {
4281                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4282                 return -EACCES;
4283         }
4284         /* associate_vsi field is NULL for floating VEB */
4285         if (veb->associate_vsi != NULL) {
4286                 vsi = veb->associate_vsi;
4287                 hw = I40E_VSI_TO_HW(vsi);
4288
4289                 vsi->uplink_seid = veb->uplink_seid;
4290                 vsi->veb = NULL;
4291         } else {
4292                 veb->associate_pf->main_vsi->floating_veb = NULL;
4293                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4294         }
4295
4296         i40e_aq_delete_element(hw, veb->seid, NULL);
4297         rte_free(veb);
4298         return I40E_SUCCESS;
4299 }
4300
4301 /* Setup a veb */
4302 static struct i40e_veb *
4303 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4304 {
4305         struct i40e_veb *veb;
4306         int ret;
4307         struct i40e_hw *hw;
4308
4309         if (pf == NULL) {
4310                 PMD_DRV_LOG(ERR,
4311                             "veb setup failed, associated PF shouldn't null");
4312                 return NULL;
4313         }
4314         hw = I40E_PF_TO_HW(pf);
4315
4316         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4317         if (!veb) {
4318                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4319                 goto fail;
4320         }
4321
4322         veb->associate_vsi = vsi;
4323         veb->associate_pf = pf;
4324         TAILQ_INIT(&veb->head);
4325         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4326
4327         /* create floating veb if vsi is NULL */
4328         if (vsi != NULL) {
4329                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4330                                       I40E_DEFAULT_TCMAP, false,
4331                                       &veb->seid, false, NULL);
4332         } else {
4333                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4334                                       true, &veb->seid, false, NULL);
4335         }
4336
4337         if (ret != I40E_SUCCESS) {
4338                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4339                             hw->aq.asq_last_status);
4340                 goto fail;
4341         }
4342
4343         /* get statistics index */
4344         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4345                                 &veb->stats_idx, NULL, NULL, NULL);
4346         if (ret != I40E_SUCCESS) {
4347                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4348                             hw->aq.asq_last_status);
4349                 goto fail;
4350         }
4351         /* Get VEB bandwidth, to be implemented */
4352         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4353         if (vsi)
4354                 vsi->uplink_seid = veb->seid;
4355
4356         return veb;
4357 fail:
4358         rte_free(veb);
4359         return NULL;
4360 }
4361
4362 int
4363 i40e_vsi_release(struct i40e_vsi *vsi)
4364 {
4365         struct i40e_pf *pf;
4366         struct i40e_hw *hw;
4367         struct i40e_vsi_list *vsi_list;
4368         void *temp;
4369         int ret;
4370         struct i40e_mac_filter *f;
4371         uint16_t user_param;
4372
4373         if (!vsi)
4374                 return I40E_SUCCESS;
4375
4376         if (!vsi->adapter)
4377                 return -EFAULT;
4378
4379         user_param = vsi->user_param;
4380
4381         pf = I40E_VSI_TO_PF(vsi);
4382         hw = I40E_VSI_TO_HW(vsi);
4383
4384         /* VSI has child to attach, release child first */
4385         if (vsi->veb) {
4386                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4387                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4388                                 return -1;
4389                 }
4390                 i40e_veb_release(vsi->veb);
4391         }
4392
4393         if (vsi->floating_veb) {
4394                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4395                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4396                                 return -1;
4397                 }
4398         }
4399
4400         /* Remove all macvlan filters of the VSI */
4401         i40e_vsi_remove_all_macvlan_filter(vsi);
4402         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4403                 rte_free(f);
4404
4405         if (vsi->type != I40E_VSI_MAIN &&
4406             ((vsi->type != I40E_VSI_SRIOV) ||
4407             !pf->floating_veb_list[user_param])) {
4408                 /* Remove vsi from parent's sibling list */
4409                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4410                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4411                         return I40E_ERR_PARAM;
4412                 }
4413                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4414                                 &vsi->sib_vsi_list, list);
4415
4416                 /* Remove all switch element of the VSI */
4417                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4418                 if (ret != I40E_SUCCESS)
4419                         PMD_DRV_LOG(ERR, "Failed to delete element");
4420         }
4421
4422         if ((vsi->type == I40E_VSI_SRIOV) &&
4423             pf->floating_veb_list[user_param]) {
4424                 /* Remove vsi from parent's sibling list */
4425                 if (vsi->parent_vsi == NULL ||
4426                     vsi->parent_vsi->floating_veb == NULL) {
4427                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4428                         return I40E_ERR_PARAM;
4429                 }
4430                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4431                              &vsi->sib_vsi_list, list);
4432
4433                 /* Remove all switch element of the VSI */
4434                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4435                 if (ret != I40E_SUCCESS)
4436                         PMD_DRV_LOG(ERR, "Failed to delete element");
4437         }
4438
4439         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4440
4441         if (vsi->type != I40E_VSI_SRIOV)
4442                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4443         rte_free(vsi);
4444
4445         return I40E_SUCCESS;
4446 }
4447
4448 static int
4449 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4450 {
4451         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4452         struct i40e_aqc_remove_macvlan_element_data def_filter;
4453         struct i40e_mac_filter_info filter;
4454         int ret;
4455
4456         if (vsi->type != I40E_VSI_MAIN)
4457                 return I40E_ERR_CONFIG;
4458         memset(&def_filter, 0, sizeof(def_filter));
4459         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4460                                         ETH_ADDR_LEN);
4461         def_filter.vlan_tag = 0;
4462         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4463                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4464         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4465         if (ret != I40E_SUCCESS) {
4466                 struct i40e_mac_filter *f;
4467                 struct ether_addr *mac;
4468
4469                 PMD_DRV_LOG(WARNING,
4470                         "Cannot remove the default macvlan filter");
4471                 /* It needs to add the permanent mac into mac list */
4472                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4473                 if (f == NULL) {
4474                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4475                         return I40E_ERR_NO_MEMORY;
4476                 }
4477                 mac = &f->mac_info.mac_addr;
4478                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4479                                 ETH_ADDR_LEN);
4480                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4481                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4482                 vsi->mac_num++;
4483
4484                 return ret;
4485         }
4486         (void)rte_memcpy(&filter.mac_addr,
4487                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4488         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4489         return i40e_vsi_add_mac(vsi, &filter);
4490 }
4491
4492 /*
4493  * i40e_vsi_get_bw_config - Query VSI BW Information
4494  * @vsi: the VSI to be queried
4495  *
4496  * Returns 0 on success, negative value on failure
4497  */
4498 static enum i40e_status_code
4499 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4500 {
4501         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4502         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4503         struct i40e_hw *hw = &vsi->adapter->hw;
4504         i40e_status ret;
4505         int i;
4506         uint32_t bw_max;
4507
4508         memset(&bw_config, 0, sizeof(bw_config));
4509         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4510         if (ret != I40E_SUCCESS) {
4511                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4512                             hw->aq.asq_last_status);
4513                 return ret;
4514         }
4515
4516         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4517         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4518                                         &ets_sla_config, NULL);
4519         if (ret != I40E_SUCCESS) {
4520                 PMD_DRV_LOG(ERR,
4521                         "VSI failed to get TC bandwdith configuration %u",
4522                         hw->aq.asq_last_status);
4523                 return ret;
4524         }
4525
4526         /* store and print out BW info */
4527         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4528         vsi->bw_info.bw_max = bw_config.max_bw;
4529         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4530         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4531         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4532                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4533                      I40E_16_BIT_WIDTH);
4534         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4535                 vsi->bw_info.bw_ets_share_credits[i] =
4536                                 ets_sla_config.share_credits[i];
4537                 vsi->bw_info.bw_ets_credits[i] =
4538                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4539                 /* 4 bits per TC, 4th bit is reserved */
4540                 vsi->bw_info.bw_ets_max[i] =
4541                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4542                                   RTE_LEN2MASK(3, uint8_t));
4543                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4544                             vsi->bw_info.bw_ets_share_credits[i]);
4545                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4546                             vsi->bw_info.bw_ets_credits[i]);
4547                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4548                             vsi->bw_info.bw_ets_max[i]);
4549         }
4550
4551         return I40E_SUCCESS;
4552 }
4553
4554 /* i40e_enable_pf_lb
4555  * @pf: pointer to the pf structure
4556  *
4557  * allow loopback on pf
4558  */
4559 static inline void
4560 i40e_enable_pf_lb(struct i40e_pf *pf)
4561 {
4562         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4563         struct i40e_vsi_context ctxt;
4564         int ret;
4565
4566         /* Use the FW API if FW >= v5.0 */
4567         if (hw->aq.fw_maj_ver < 5) {
4568                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4569                 return;
4570         }
4571
4572         memset(&ctxt, 0, sizeof(ctxt));
4573         ctxt.seid = pf->main_vsi_seid;
4574         ctxt.pf_num = hw->pf_id;
4575         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4576         if (ret) {
4577                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4578                             ret, hw->aq.asq_last_status);
4579                 return;
4580         }
4581         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4582         ctxt.info.valid_sections =
4583                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4584         ctxt.info.switch_id |=
4585                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4586
4587         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4588         if (ret)
4589                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4590                             hw->aq.asq_last_status);
4591 }
4592
4593 /* Setup a VSI */
4594 struct i40e_vsi *
4595 i40e_vsi_setup(struct i40e_pf *pf,
4596                enum i40e_vsi_type type,
4597                struct i40e_vsi *uplink_vsi,
4598                uint16_t user_param)
4599 {
4600         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4601         struct i40e_vsi *vsi;
4602         struct i40e_mac_filter_info filter;
4603         int ret;
4604         struct i40e_vsi_context ctxt;
4605         struct ether_addr broadcast =
4606                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4607
4608         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4609             uplink_vsi == NULL) {
4610                 PMD_DRV_LOG(ERR,
4611                         "VSI setup failed, VSI link shouldn't be NULL");
4612                 return NULL;
4613         }
4614
4615         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4616                 PMD_DRV_LOG(ERR,
4617                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4618                 return NULL;
4619         }
4620
4621         /* two situations
4622          * 1.type is not MAIN and uplink vsi is not NULL
4623          * If uplink vsi didn't setup VEB, create one first under veb field
4624          * 2.type is SRIOV and the uplink is NULL
4625          * If floating VEB is NULL, create one veb under floating veb field
4626          */
4627
4628         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4629             uplink_vsi->veb == NULL) {
4630                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4631
4632                 if (uplink_vsi->veb == NULL) {
4633                         PMD_DRV_LOG(ERR, "VEB setup failed");
4634                         return NULL;
4635                 }
4636                 /* set ALLOWLOOPBACk on pf, when veb is created */
4637                 i40e_enable_pf_lb(pf);
4638         }
4639
4640         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4641             pf->main_vsi->floating_veb == NULL) {
4642                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4643
4644                 if (pf->main_vsi->floating_veb == NULL) {
4645                         PMD_DRV_LOG(ERR, "VEB setup failed");
4646                         return NULL;
4647                 }
4648         }
4649
4650         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4651         if (!vsi) {
4652                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4653                 return NULL;
4654         }
4655         TAILQ_INIT(&vsi->mac_list);
4656         vsi->type = type;
4657         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4658         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4659         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4660         vsi->user_param = user_param;
4661         vsi->vlan_anti_spoof_on = 0;
4662         /* Allocate queues */
4663         switch (vsi->type) {
4664         case I40E_VSI_MAIN  :
4665                 vsi->nb_qps = pf->lan_nb_qps;
4666                 break;
4667         case I40E_VSI_SRIOV :
4668                 vsi->nb_qps = pf->vf_nb_qps;
4669                 break;
4670         case I40E_VSI_VMDQ2:
4671                 vsi->nb_qps = pf->vmdq_nb_qps;
4672                 break;
4673         case I40E_VSI_FDIR:
4674                 vsi->nb_qps = pf->fdir_nb_qps;
4675                 break;
4676         default:
4677                 goto fail_mem;
4678         }
4679         /*
4680          * The filter status descriptor is reported in rx queue 0,
4681          * while the tx queue for fdir filter programming has no
4682          * such constraints, can be non-zero queues.
4683          * To simplify it, choose FDIR vsi use queue 0 pair.
4684          * To make sure it will use queue 0 pair, queue allocation
4685          * need be done before this function is called
4686          */
4687         if (type != I40E_VSI_FDIR) {
4688                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4689                         if (ret < 0) {
4690                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4691                                                 vsi->seid, ret);
4692                                 goto fail_mem;
4693                         }
4694                         vsi->base_queue = ret;
4695         } else
4696                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4697
4698         /* VF has MSIX interrupt in VF range, don't allocate here */
4699         if (type == I40E_VSI_MAIN) {
4700                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4701                                           RTE_MIN(vsi->nb_qps,
4702                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4703                 if (ret < 0) {
4704                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4705                                     vsi->seid, ret);
4706                         goto fail_queue_alloc;
4707                 }
4708                 vsi->msix_intr = ret;
4709                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4710         } else if (type != I40E_VSI_SRIOV) {
4711                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4712                 if (ret < 0) {
4713                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4714                         goto fail_queue_alloc;
4715                 }
4716                 vsi->msix_intr = ret;
4717                 vsi->nb_msix = 1;
4718         } else {
4719                 vsi->msix_intr = 0;
4720                 vsi->nb_msix = 0;
4721         }
4722
4723         /* Add VSI */
4724         if (type == I40E_VSI_MAIN) {
4725                 /* For main VSI, no need to add since it's default one */
4726                 vsi->uplink_seid = pf->mac_seid;
4727                 vsi->seid = pf->main_vsi_seid;
4728                 /* Bind queues with specific MSIX interrupt */
4729                 /**
4730                  * Needs 2 interrupt at least, one for misc cause which will
4731                  * enabled from OS side, Another for queues binding the
4732                  * interrupt from device side only.
4733                  */
4734
4735                 /* Get default VSI parameters from hardware */
4736                 memset(&ctxt, 0, sizeof(ctxt));
4737                 ctxt.seid = vsi->seid;
4738                 ctxt.pf_num = hw->pf_id;
4739                 ctxt.uplink_seid = vsi->uplink_seid;
4740                 ctxt.vf_num = 0;
4741                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4742                 if (ret != I40E_SUCCESS) {
4743                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4744                         goto fail_msix_alloc;
4745                 }
4746                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4747                         sizeof(struct i40e_aqc_vsi_properties_data));
4748                 vsi->vsi_id = ctxt.vsi_number;
4749                 vsi->info.valid_sections = 0;
4750
4751                 /* Configure tc, enabled TC0 only */
4752                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4753                         I40E_SUCCESS) {
4754                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4755                         goto fail_msix_alloc;
4756                 }
4757
4758                 /* TC, queue mapping */
4759                 memset(&ctxt, 0, sizeof(ctxt));
4760                 vsi->info.valid_sections |=
4761                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4762                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4763                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4764                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4765                         sizeof(struct i40e_aqc_vsi_properties_data));
4766                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4767                                                 I40E_DEFAULT_TCMAP);
4768                 if (ret != I40E_SUCCESS) {
4769                         PMD_DRV_LOG(ERR,
4770                                 "Failed to configure TC queue mapping");
4771                         goto fail_msix_alloc;
4772                 }
4773                 ctxt.seid = vsi->seid;
4774                 ctxt.pf_num = hw->pf_id;
4775                 ctxt.uplink_seid = vsi->uplink_seid;
4776                 ctxt.vf_num = 0;
4777
4778                 /* Update VSI parameters */
4779                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4780                 if (ret != I40E_SUCCESS) {
4781                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4782                         goto fail_msix_alloc;
4783                 }
4784
4785                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4786                                                 sizeof(vsi->info.tc_mapping));
4787                 (void)rte_memcpy(&vsi->info.queue_mapping,
4788                                 &ctxt.info.queue_mapping,
4789                         sizeof(vsi->info.queue_mapping));
4790                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4791                 vsi->info.valid_sections = 0;
4792
4793                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4794                                 ETH_ADDR_LEN);
4795
4796                 /**
4797                  * Updating default filter settings are necessary to prevent
4798                  * reception of tagged packets.
4799                  * Some old firmware configurations load a default macvlan
4800                  * filter which accepts both tagged and untagged packets.
4801                  * The updating is to use a normal filter instead if needed.
4802                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4803                  * The firmware with correct configurations load the default
4804                  * macvlan filter which is expected and cannot be removed.
4805                  */
4806                 i40e_update_default_filter_setting(vsi);
4807                 i40e_config_qinq(hw, vsi);
4808         } else if (type == I40E_VSI_SRIOV) {
4809                 memset(&ctxt, 0, sizeof(ctxt));
4810                 /**
4811                  * For other VSI, the uplink_seid equals to uplink VSI's
4812                  * uplink_seid since they share same VEB
4813                  */
4814                 if (uplink_vsi == NULL)
4815                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4816                 else
4817                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4818                 ctxt.pf_num = hw->pf_id;
4819                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4820                 ctxt.uplink_seid = vsi->uplink_seid;
4821                 ctxt.connection_type = 0x1;
4822                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4823
4824                 /* Use the VEB configuration if FW >= v5.0 */
4825                 if (hw->aq.fw_maj_ver >= 5) {
4826                         /* Configure switch ID */
4827                         ctxt.info.valid_sections |=
4828                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4829                         ctxt.info.switch_id =
4830                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4831                 }
4832
4833                 /* Configure port/vlan */
4834                 ctxt.info.valid_sections |=
4835                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4836                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4837                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4838                                                 I40E_DEFAULT_TCMAP);
4839                 if (ret != I40E_SUCCESS) {
4840                         PMD_DRV_LOG(ERR,
4841                                 "Failed to configure TC queue mapping");
4842                         goto fail_msix_alloc;
4843                 }
4844                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4845                 ctxt.info.valid_sections |=
4846                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4847                 /**
4848                  * Since VSI is not created yet, only configure parameter,
4849                  * will add vsi below.
4850                  */
4851
4852                 i40e_config_qinq(hw, vsi);
4853         } else if (type == I40E_VSI_VMDQ2) {
4854                 memset(&ctxt, 0, sizeof(ctxt));
4855                 /*
4856                  * For other VSI, the uplink_seid equals to uplink VSI's
4857                  * uplink_seid since they share same VEB
4858                  */
4859                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4860                 ctxt.pf_num = hw->pf_id;
4861                 ctxt.vf_num = 0;
4862                 ctxt.uplink_seid = vsi->uplink_seid;
4863                 ctxt.connection_type = 0x1;
4864                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4865
4866                 ctxt.info.valid_sections |=
4867                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4868                 /* user_param carries flag to enable loop back */
4869                 if (user_param) {
4870                         ctxt.info.switch_id =
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4872                         ctxt.info.switch_id |=
4873                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4874                 }
4875
4876                 /* Configure port/vlan */
4877                 ctxt.info.valid_sections |=
4878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4879                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4880                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4881                                                 I40E_DEFAULT_TCMAP);
4882                 if (ret != I40E_SUCCESS) {
4883                         PMD_DRV_LOG(ERR,
4884                                 "Failed to configure TC queue mapping");
4885                         goto fail_msix_alloc;
4886                 }
4887                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4888                 ctxt.info.valid_sections |=
4889                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4890         } else if (type == I40E_VSI_FDIR) {
4891                 memset(&ctxt, 0, sizeof(ctxt));
4892                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4893                 ctxt.pf_num = hw->pf_id;
4894                 ctxt.vf_num = 0;
4895                 ctxt.uplink_seid = vsi->uplink_seid;
4896                 ctxt.connection_type = 0x1;     /* regular data port */
4897                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4898                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4899                                                 I40E_DEFAULT_TCMAP);
4900                 if (ret != I40E_SUCCESS) {
4901                         PMD_DRV_LOG(ERR,
4902                                 "Failed to configure TC queue mapping.");
4903                         goto fail_msix_alloc;
4904                 }
4905                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4906                 ctxt.info.valid_sections |=
4907                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4908         } else {
4909                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4910                 goto fail_msix_alloc;
4911         }
4912
4913         if (vsi->type != I40E_VSI_MAIN) {
4914                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4915                 if (ret != I40E_SUCCESS) {
4916                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4917                                     hw->aq.asq_last_status);
4918                         goto fail_msix_alloc;
4919                 }
4920                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4921                 vsi->info.valid_sections = 0;
4922                 vsi->seid = ctxt.seid;
4923                 vsi->vsi_id = ctxt.vsi_number;
4924                 vsi->sib_vsi_list.vsi = vsi;
4925                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4926                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4927                                           &vsi->sib_vsi_list, list);
4928                 } else {
4929                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4930                                           &vsi->sib_vsi_list, list);
4931                 }
4932         }
4933
4934         /* MAC/VLAN configuration */
4935         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4936         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4937
4938         ret = i40e_vsi_add_mac(vsi, &filter);
4939         if (ret != I40E_SUCCESS) {
4940                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4941                 goto fail_msix_alloc;
4942         }
4943
4944         /* Get VSI BW information */
4945         i40e_vsi_get_bw_config(vsi);
4946         return vsi;
4947 fail_msix_alloc:
4948         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4949 fail_queue_alloc:
4950         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4951 fail_mem:
4952         rte_free(vsi);
4953         return NULL;
4954 }
4955
4956 /* Configure vlan filter on or off */
4957 int
4958 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4959 {
4960         int i, num;
4961         struct i40e_mac_filter *f;
4962         void *temp;
4963         struct i40e_mac_filter_info *mac_filter;
4964         enum rte_mac_filter_type desired_filter;
4965         int ret = I40E_SUCCESS;
4966
4967         if (on) {
4968                 /* Filter to match MAC and VLAN */
4969                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4970         } else {
4971                 /* Filter to match only MAC */
4972                 desired_filter = RTE_MAC_PERFECT_MATCH;
4973         }
4974
4975         num = vsi->mac_num;
4976
4977         mac_filter = rte_zmalloc("mac_filter_info_data",
4978                                  num * sizeof(*mac_filter), 0);
4979         if (mac_filter == NULL) {
4980                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4981                 return I40E_ERR_NO_MEMORY;
4982         }
4983
4984         i = 0;
4985
4986         /* Remove all existing mac */
4987         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4988                 mac_filter[i] = f->mac_info;
4989                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4990                 if (ret) {
4991                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4992                                     on ? "enable" : "disable");
4993                         goto DONE;
4994                 }
4995                 i++;
4996         }
4997
4998         /* Override with new filter */
4999         for (i = 0; i < num; i++) {
5000                 mac_filter[i].filter_type = desired_filter;
5001                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5002                 if (ret) {
5003                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5004                                     on ? "enable" : "disable");
5005                         goto DONE;
5006                 }
5007         }
5008
5009 DONE:
5010         rte_free(mac_filter);
5011         return ret;
5012 }
5013
5014 /* Configure vlan stripping on or off */
5015 int
5016 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5017 {
5018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5019         struct i40e_vsi_context ctxt;
5020         uint8_t vlan_flags;
5021         int ret = I40E_SUCCESS;
5022
5023         /* Check if it has been already on or off */
5024         if (vsi->info.valid_sections &
5025                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5026                 if (on) {
5027                         if ((vsi->info.port_vlan_flags &
5028                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5029                                 return 0; /* already on */
5030                 } else {
5031                         if ((vsi->info.port_vlan_flags &
5032                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5033                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5034                                 return 0; /* already off */
5035                 }
5036         }
5037
5038         if (on)
5039                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5040         else
5041                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5042         vsi->info.valid_sections =
5043                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5044         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5045         vsi->info.port_vlan_flags |= vlan_flags;
5046         ctxt.seid = vsi->seid;
5047         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5048         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5049         if (ret)
5050                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5051                             on ? "enable" : "disable");
5052
5053         return ret;
5054 }
5055
5056 static int
5057 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5058 {
5059         struct rte_eth_dev_data *data = dev->data;
5060         int ret;
5061         int mask = 0;
5062
5063         /* Apply vlan offload setting */
5064         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5065         i40e_vlan_offload_set(dev, mask);
5066
5067         /* Apply double-vlan setting, not implemented yet */
5068
5069         /* Apply pvid setting */
5070         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5071                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5072         if (ret)
5073                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5074
5075         return ret;
5076 }
5077
5078 static int
5079 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5080 {
5081         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5082
5083         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5084 }
5085
5086 static int
5087 i40e_update_flow_control(struct i40e_hw *hw)
5088 {
5089 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5090         struct i40e_link_status link_status;
5091         uint32_t rxfc = 0, txfc = 0, reg;
5092         uint8_t an_info;
5093         int ret;
5094
5095         memset(&link_status, 0, sizeof(link_status));
5096         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5097         if (ret != I40E_SUCCESS) {
5098                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5099                 goto write_reg; /* Disable flow control */
5100         }
5101
5102         an_info = hw->phy.link_info.an_info;
5103         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5104                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5105                 ret = I40E_ERR_NOT_READY;
5106                 goto write_reg; /* Disable flow control */
5107         }
5108         /**
5109          * If link auto negotiation is enabled, flow control needs to
5110          * be configured according to it
5111          */
5112         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5113         case I40E_LINK_PAUSE_RXTX:
5114                 rxfc = 1;
5115                 txfc = 1;
5116                 hw->fc.current_mode = I40E_FC_FULL;
5117                 break;
5118         case I40E_AQ_LINK_PAUSE_RX:
5119                 rxfc = 1;
5120                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5121                 break;
5122         case I40E_AQ_LINK_PAUSE_TX:
5123                 txfc = 1;
5124                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5125                 break;
5126         default:
5127                 hw->fc.current_mode = I40E_FC_NONE;
5128                 break;
5129         }
5130
5131 write_reg:
5132         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5133                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5134         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5135         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5136         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5137         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5138
5139         return ret;
5140 }
5141
5142 /* PF setup */
5143 static int
5144 i40e_pf_setup(struct i40e_pf *pf)
5145 {
5146         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5147         struct i40e_filter_control_settings settings;
5148         struct i40e_vsi *vsi;
5149         int ret;
5150
5151         /* Clear all stats counters */
5152         pf->offset_loaded = FALSE;
5153         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5154         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5155
5156         ret = i40e_pf_get_switch_config(pf);
5157         if (ret != I40E_SUCCESS) {
5158                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5159                 return ret;
5160         }
5161         if (pf->flags & I40E_FLAG_FDIR) {
5162                 /* make queue allocated first, let FDIR use queue pair 0*/
5163                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5164                 if (ret != I40E_FDIR_QUEUE_ID) {
5165                         PMD_DRV_LOG(ERR,
5166                                 "queue allocation fails for FDIR: ret =%d",
5167                                 ret);
5168                         pf->flags &= ~I40E_FLAG_FDIR;
5169                 }
5170         }
5171         /*  main VSI setup */
5172         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5173         if (!vsi) {
5174                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5175                 return I40E_ERR_NOT_READY;
5176         }
5177         pf->main_vsi = vsi;
5178
5179         /* Configure filter control */
5180         memset(&settings, 0, sizeof(settings));
5181         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5182                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5183         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5184                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5185         else {
5186                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5187                         hw->func_caps.rss_table_size);
5188                 return I40E_ERR_PARAM;
5189         }
5190         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5191                 hw->func_caps.rss_table_size);
5192         pf->hash_lut_size = hw->func_caps.rss_table_size;
5193
5194         /* Enable ethtype and macvlan filters */
5195         settings.enable_ethtype = TRUE;
5196         settings.enable_macvlan = TRUE;
5197         ret = i40e_set_filter_control(hw, &settings);
5198         if (ret)
5199                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5200                                                                 ret);
5201
5202         /* Update flow control according to the auto negotiation */
5203         i40e_update_flow_control(hw);
5204
5205         return I40E_SUCCESS;
5206 }
5207
5208 int
5209 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5210 {
5211         uint32_t reg;
5212         uint16_t j;
5213
5214         /**
5215          * Set or clear TX Queue Disable flags,
5216          * which is required by hardware.
5217          */
5218         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5219         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5220
5221         /* Wait until the request is finished */
5222         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5223                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5224                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5225                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5226                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5227                                                         & 0x1))) {
5228                         break;
5229                 }
5230         }
5231         if (on) {
5232                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5233                         return I40E_SUCCESS; /* already on, skip next steps */
5234
5235                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5236                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5237         } else {
5238                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5239                         return I40E_SUCCESS; /* already off, skip next steps */
5240                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5241         }
5242         /* Write the register */
5243         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5244         /* Check the result */
5245         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5246                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5247                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5248                 if (on) {
5249                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5250                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5251                                 break;
5252                 } else {
5253                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5254                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5255                                 break;
5256                 }
5257         }
5258         /* Check if it is timeout */
5259         if (j >= I40E_CHK_Q_ENA_COUNT) {
5260                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5261                             (on ? "enable" : "disable"), q_idx);
5262                 return I40E_ERR_TIMEOUT;
5263         }
5264
5265         return I40E_SUCCESS;
5266 }
5267
5268 /* Swith on or off the tx queues */
5269 static int
5270 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5271 {
5272         struct rte_eth_dev_data *dev_data = pf->dev_data;
5273         struct i40e_tx_queue *txq;
5274         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5275         uint16_t i;
5276         int ret;
5277
5278         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5279                 txq = dev_data->tx_queues[i];
5280                 /* Don't operate the queue if not configured or
5281                  * if starting only per queue */
5282                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5283                         continue;
5284                 if (on)
5285                         ret = i40e_dev_tx_queue_start(dev, i);
5286                 else
5287                         ret = i40e_dev_tx_queue_stop(dev, i);
5288                 if ( ret != I40E_SUCCESS)
5289                         return ret;
5290         }
5291
5292         return I40E_SUCCESS;
5293 }
5294
5295 int
5296 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5297 {
5298         uint32_t reg;
5299         uint16_t j;
5300
5301         /* Wait until the request is finished */
5302         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5303                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5304                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5305                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5306                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5307                         break;
5308         }
5309
5310         if (on) {
5311                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5312                         return I40E_SUCCESS; /* Already on, skip next steps */
5313                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5314         } else {
5315                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5316                         return I40E_SUCCESS; /* Already off, skip next steps */
5317                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5318         }
5319
5320         /* Write the register */
5321         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5322         /* Check the result */
5323         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5324                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5325                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5326                 if (on) {
5327                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5328                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5329                                 break;
5330                 } else {
5331                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5332                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5333                                 break;
5334                 }
5335         }
5336
5337         /* Check if it is timeout */
5338         if (j >= I40E_CHK_Q_ENA_COUNT) {
5339                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5340                             (on ? "enable" : "disable"), q_idx);
5341                 return I40E_ERR_TIMEOUT;
5342         }
5343
5344         return I40E_SUCCESS;
5345 }
5346 /* Switch on or off the rx queues */
5347 static int
5348 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5349 {
5350         struct rte_eth_dev_data *dev_data = pf->dev_data;
5351         struct i40e_rx_queue *rxq;
5352         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5353         uint16_t i;
5354         int ret;
5355
5356         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5357                 rxq = dev_data->rx_queues[i];
5358                 /* Don't operate the queue if not configured or
5359                  * if starting only per queue */
5360                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5361                         continue;
5362                 if (on)
5363                         ret = i40e_dev_rx_queue_start(dev, i);
5364                 else
5365                         ret = i40e_dev_rx_queue_stop(dev, i);
5366                 if (ret != I40E_SUCCESS)
5367                         return ret;
5368         }
5369
5370         return I40E_SUCCESS;
5371 }
5372
5373 /* Switch on or off all the rx/tx queues */
5374 int
5375 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5376 {
5377         int ret;
5378
5379         if (on) {
5380                 /* enable rx queues before enabling tx queues */
5381                 ret = i40e_dev_switch_rx_queues(pf, on);
5382                 if (ret) {
5383                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5384                         return ret;
5385                 }
5386                 ret = i40e_dev_switch_tx_queues(pf, on);
5387         } else {
5388                 /* Stop tx queues before stopping rx queues */
5389                 ret = i40e_dev_switch_tx_queues(pf, on);
5390                 if (ret) {
5391                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5392                         return ret;
5393                 }
5394                 ret = i40e_dev_switch_rx_queues(pf, on);
5395         }
5396
5397         return ret;
5398 }
5399
5400 /* Initialize VSI for TX */
5401 static int
5402 i40e_dev_tx_init(struct i40e_pf *pf)
5403 {
5404         struct rte_eth_dev_data *data = pf->dev_data;
5405         uint16_t i;
5406         uint32_t ret = I40E_SUCCESS;
5407         struct i40e_tx_queue *txq;
5408
5409         for (i = 0; i < data->nb_tx_queues; i++) {
5410                 txq = data->tx_queues[i];
5411                 if (!txq || !txq->q_set)
5412                         continue;
5413                 ret = i40e_tx_queue_init(txq);
5414                 if (ret != I40E_SUCCESS)
5415                         break;
5416         }
5417         if (ret == I40E_SUCCESS)
5418                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5419                                      ->eth_dev);
5420
5421         return ret;
5422 }
5423
5424 /* Initialize VSI for RX */
5425 static int
5426 i40e_dev_rx_init(struct i40e_pf *pf)
5427 {
5428         struct rte_eth_dev_data *data = pf->dev_data;
5429         int ret = I40E_SUCCESS;
5430         uint16_t i;
5431         struct i40e_rx_queue *rxq;
5432
5433         i40e_pf_config_mq_rx(pf);
5434         for (i = 0; i < data->nb_rx_queues; i++) {
5435                 rxq = data->rx_queues[i];
5436                 if (!rxq || !rxq->q_set)
5437                         continue;
5438
5439                 ret = i40e_rx_queue_init(rxq);
5440                 if (ret != I40E_SUCCESS) {
5441                         PMD_DRV_LOG(ERR,
5442                                 "Failed to do RX queue initialization");
5443                         break;
5444                 }
5445         }
5446         if (ret == I40E_SUCCESS)
5447                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5448                                      ->eth_dev);
5449
5450         return ret;
5451 }
5452
5453 static int
5454 i40e_dev_rxtx_init(struct i40e_pf *pf)
5455 {
5456         int err;
5457
5458         err = i40e_dev_tx_init(pf);
5459         if (err) {
5460                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5461                 return err;
5462         }
5463         err = i40e_dev_rx_init(pf);
5464         if (err) {
5465                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5466                 return err;
5467         }
5468
5469         return err;
5470 }
5471
5472 static int
5473 i40e_vmdq_setup(struct rte_eth_dev *dev)
5474 {
5475         struct rte_eth_conf *conf = &dev->data->dev_conf;
5476         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5477         int i, err, conf_vsis, j, loop;
5478         struct i40e_vsi *vsi;
5479         struct i40e_vmdq_info *vmdq_info;
5480         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5481         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5482
5483         /*
5484          * Disable interrupt to avoid message from VF. Furthermore, it will
5485          * avoid race condition in VSI creation/destroy.
5486          */
5487         i40e_pf_disable_irq0(hw);
5488
5489         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5490                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5491                 return -ENOTSUP;
5492         }
5493
5494         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5495         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5496                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5497                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5498                         pf->max_nb_vmdq_vsi);
5499                 return -ENOTSUP;
5500         }
5501
5502         if (pf->vmdq != NULL) {
5503                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5504                 return 0;
5505         }
5506
5507         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5508                                 sizeof(*vmdq_info) * conf_vsis, 0);
5509
5510         if (pf->vmdq == NULL) {
5511                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5512                 return -ENOMEM;
5513         }
5514
5515         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5516
5517         /* Create VMDQ VSI */
5518         for (i = 0; i < conf_vsis; i++) {
5519                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5520                                 vmdq_conf->enable_loop_back);
5521                 if (vsi == NULL) {
5522                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5523                         err = -1;
5524                         goto err_vsi_setup;
5525                 }
5526                 vmdq_info = &pf->vmdq[i];
5527                 vmdq_info->pf = pf;
5528                 vmdq_info->vsi = vsi;
5529         }
5530         pf->nb_cfg_vmdq_vsi = conf_vsis;
5531
5532         /* Configure Vlan */
5533         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5534         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5535                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5536                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5537                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5538                                         vmdq_conf->pool_map[i].vlan_id, j);
5539
5540                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5541                                                 vmdq_conf->pool_map[i].vlan_id);
5542                                 if (err) {
5543                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5544                                         err = -1;
5545                                         goto err_vsi_setup;
5546                                 }
5547                         }
5548                 }
5549         }
5550
5551         i40e_pf_enable_irq0(hw);
5552
5553         return 0;
5554
5555 err_vsi_setup:
5556         for (i = 0; i < conf_vsis; i++)
5557                 if (pf->vmdq[i].vsi == NULL)
5558                         break;
5559                 else
5560                         i40e_vsi_release(pf->vmdq[i].vsi);
5561
5562         rte_free(pf->vmdq);
5563         pf->vmdq = NULL;
5564         i40e_pf_enable_irq0(hw);
5565         return err;
5566 }
5567
5568 static void
5569 i40e_stat_update_32(struct i40e_hw *hw,
5570                    uint32_t reg,
5571                    bool offset_loaded,
5572                    uint64_t *offset,
5573                    uint64_t *stat)
5574 {
5575         uint64_t new_data;
5576
5577         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5578         if (!offset_loaded)
5579                 *offset = new_data;
5580
5581         if (new_data >= *offset)
5582                 *stat = (uint64_t)(new_data - *offset);
5583         else
5584                 *stat = (uint64_t)((new_data +
5585                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5586 }
5587
5588 static void
5589 i40e_stat_update_48(struct i40e_hw *hw,
5590                    uint32_t hireg,
5591                    uint32_t loreg,
5592                    bool offset_loaded,
5593                    uint64_t *offset,
5594                    uint64_t *stat)
5595 {
5596         uint64_t new_data;
5597
5598         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5599         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5600                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5601
5602         if (!offset_loaded)
5603                 *offset = new_data;
5604
5605         if (new_data >= *offset)
5606                 *stat = new_data - *offset;
5607         else
5608                 *stat = (uint64_t)((new_data +
5609                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5610
5611         *stat &= I40E_48_BIT_MASK;
5612 }
5613
5614 /* Disable IRQ0 */
5615 void
5616 i40e_pf_disable_irq0(struct i40e_hw *hw)
5617 {
5618         /* Disable all interrupt types */
5619         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5620         I40E_WRITE_FLUSH(hw);
5621 }
5622
5623 /* Enable IRQ0 */
5624 void
5625 i40e_pf_enable_irq0(struct i40e_hw *hw)
5626 {
5627         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5628                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5629                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5630                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5631         I40E_WRITE_FLUSH(hw);
5632 }
5633
5634 static void
5635 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5636 {
5637         /* read pending request and disable first */
5638         i40e_pf_disable_irq0(hw);
5639         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5640         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5641                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5642
5643         if (no_queue)
5644                 /* Link no queues with irq0 */
5645                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5646                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5647 }
5648
5649 static void
5650 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5651 {
5652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5654         int i;
5655         uint16_t abs_vf_id;
5656         uint32_t index, offset, val;
5657
5658         if (!pf->vfs)
5659                 return;
5660         /**
5661          * Try to find which VF trigger a reset, use absolute VF id to access
5662          * since the reg is global register.
5663          */
5664         for (i = 0; i < pf->vf_num; i++) {
5665                 abs_vf_id = hw->func_caps.vf_base_id + i;
5666                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5667                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5668                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5669                 /* VFR event occured */
5670                 if (val & (0x1 << offset)) {
5671                         int ret;
5672
5673                         /* Clear the event first */
5674                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5675                                                         (0x1 << offset));
5676                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5677                         /**
5678                          * Only notify a VF reset event occured,
5679                          * don't trigger another SW reset
5680                          */
5681                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5682                         if (ret != I40E_SUCCESS)
5683                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5684                 }
5685         }
5686 }
5687
5688 static void
5689 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5690 {
5691         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5692         struct i40e_virtchnl_pf_event event;
5693         int i;
5694
5695         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5696         event.event_data.link_event.link_status =
5697                 dev->data->dev_link.link_status;
5698         event.event_data.link_event.link_speed =
5699                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5700
5701         for (i = 0; i < pf->vf_num; i++)
5702                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5703                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5704 }
5705
5706 static void
5707 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5708 {
5709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5710         struct i40e_arq_event_info info;
5711         uint16_t pending, opcode;
5712         int ret;
5713
5714         info.buf_len = I40E_AQ_BUF_SZ;
5715         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5716         if (!info.msg_buf) {
5717                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5718                 return;
5719         }
5720
5721         pending = 1;
5722         while (pending) {
5723                 ret = i40e_clean_arq_element(hw, &info, &pending);
5724
5725                 if (ret != I40E_SUCCESS) {
5726                         PMD_DRV_LOG(INFO,
5727                                 "Failed to read msg from AdminQ, aq_err: %u",
5728                                 hw->aq.asq_last_status);
5729                         break;
5730                 }
5731                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5732
5733                 switch (opcode) {
5734                 case i40e_aqc_opc_send_msg_to_pf:
5735                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5736                         i40e_pf_host_handle_vf_msg(dev,
5737                                         rte_le_to_cpu_16(info.desc.retval),
5738                                         rte_le_to_cpu_32(info.desc.cookie_high),
5739                                         rte_le_to_cpu_32(info.desc.cookie_low),
5740                                         info.msg_buf,
5741                                         info.msg_len);
5742                         break;
5743                 case i40e_aqc_opc_get_link_status:
5744                         ret = i40e_dev_link_update(dev, 0);
5745                         if (!ret) {
5746                                 i40e_notify_all_vfs_link_status(dev);
5747                                 _rte_eth_dev_callback_process(dev,
5748                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5749                         }
5750                         break;
5751                 default:
5752                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5753                                     opcode);
5754                         break;
5755                 }
5756         }
5757         rte_free(info.msg_buf);
5758 }
5759
5760 /**
5761  * Interrupt handler triggered by NIC  for handling
5762  * specific interrupt.
5763  *
5764  * @param handle
5765  *  Pointer to interrupt handle.
5766  * @param param
5767  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5768  *
5769  * @return
5770  *  void
5771  */
5772 static void
5773 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5774                            void *param)
5775 {
5776         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778         uint32_t icr0;
5779
5780         /* Disable interrupt */
5781         i40e_pf_disable_irq0(hw);
5782
5783         /* read out interrupt causes */
5784         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5785
5786         /* No interrupt event indicated */
5787         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5788                 PMD_DRV_LOG(INFO, "No interrupt event");
5789                 goto done;
5790         }
5791 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5792         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5793                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5794         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5795                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5796         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5797                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5798         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5799                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5800         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5801                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5802         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5803                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5804         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5805                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5806 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5807
5808         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5809                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5810                 i40e_dev_handle_vfr_event(dev);
5811         }
5812         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5813                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5814                 i40e_dev_handle_aq_msg(dev);
5815         }
5816
5817 done:
5818         /* Enable interrupt */
5819         i40e_pf_enable_irq0(hw);
5820         rte_intr_enable(intr_handle);
5821 }
5822
5823 static int
5824 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5825                          struct i40e_macvlan_filter *filter,
5826                          int total)
5827 {
5828         int ele_num, ele_buff_size;
5829         int num, actual_num, i;
5830         uint16_t flags;
5831         int ret = I40E_SUCCESS;
5832         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5833         struct i40e_aqc_add_macvlan_element_data *req_list;
5834
5835         if (filter == NULL  || total == 0)
5836                 return I40E_ERR_PARAM;
5837         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5838         ele_buff_size = hw->aq.asq_buf_size;
5839
5840         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5841         if (req_list == NULL) {
5842                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5843                 return I40E_ERR_NO_MEMORY;
5844         }
5845
5846         num = 0;
5847         do {
5848                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5849                 memset(req_list, 0, ele_buff_size);
5850
5851                 for (i = 0; i < actual_num; i++) {
5852                         (void)rte_memcpy(req_list[i].mac_addr,
5853                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5854                         req_list[i].vlan_tag =
5855                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5856
5857                         switch (filter[num + i].filter_type) {
5858                         case RTE_MAC_PERFECT_MATCH:
5859                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5860                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5861                                 break;
5862                         case RTE_MACVLAN_PERFECT_MATCH:
5863                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5864                                 break;
5865                         case RTE_MAC_HASH_MATCH:
5866                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5867                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5868                                 break;
5869                         case RTE_MACVLAN_HASH_MATCH:
5870                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5871                                 break;
5872                         default:
5873                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5874                                 ret = I40E_ERR_PARAM;
5875                                 goto DONE;
5876                         }
5877
5878                         req_list[i].queue_number = 0;
5879
5880                         req_list[i].flags = rte_cpu_to_le_16(flags);
5881                 }
5882
5883                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5884                                                 actual_num, NULL);
5885                 if (ret != I40E_SUCCESS) {
5886                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5887                         goto DONE;
5888                 }
5889                 num += actual_num;
5890         } while (num < total);
5891
5892 DONE:
5893         rte_free(req_list);
5894         return ret;
5895 }
5896
5897 static int
5898 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5899                             struct i40e_macvlan_filter *filter,
5900                             int total)
5901 {
5902         int ele_num, ele_buff_size;
5903         int num, actual_num, i;
5904         uint16_t flags;
5905         int ret = I40E_SUCCESS;
5906         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5907         struct i40e_aqc_remove_macvlan_element_data *req_list;
5908
5909         if (filter == NULL  || total == 0)
5910                 return I40E_ERR_PARAM;
5911
5912         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5913         ele_buff_size = hw->aq.asq_buf_size;
5914
5915         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5916         if (req_list == NULL) {
5917                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5918                 return I40E_ERR_NO_MEMORY;
5919         }
5920
5921         num = 0;
5922         do {
5923                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5924                 memset(req_list, 0, ele_buff_size);
5925
5926                 for (i = 0; i < actual_num; i++) {
5927                         (void)rte_memcpy(req_list[i].mac_addr,
5928                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5929                         req_list[i].vlan_tag =
5930                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5931
5932                         switch (filter[num + i].filter_type) {
5933                         case RTE_MAC_PERFECT_MATCH:
5934                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5935                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5936                                 break;
5937                         case RTE_MACVLAN_PERFECT_MATCH:
5938                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5939                                 break;
5940                         case RTE_MAC_HASH_MATCH:
5941                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5942                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5943                                 break;
5944                         case RTE_MACVLAN_HASH_MATCH:
5945                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5946                                 break;
5947                         default:
5948                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5949                                 ret = I40E_ERR_PARAM;
5950                                 goto DONE;
5951                         }
5952                         req_list[i].flags = rte_cpu_to_le_16(flags);
5953                 }
5954
5955                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5956                                                 actual_num, NULL);
5957                 if (ret != I40E_SUCCESS) {
5958                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5959                         goto DONE;
5960                 }
5961                 num += actual_num;
5962         } while (num < total);
5963
5964 DONE:
5965         rte_free(req_list);
5966         return ret;
5967 }
5968
5969 /* Find out specific MAC filter */
5970 static struct i40e_mac_filter *
5971 i40e_find_mac_filter(struct i40e_vsi *vsi,
5972                          struct ether_addr *macaddr)
5973 {
5974         struct i40e_mac_filter *f;
5975
5976         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5977                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5978                         return f;
5979         }
5980
5981         return NULL;
5982 }
5983
5984 static bool
5985 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5986                          uint16_t vlan_id)
5987 {
5988         uint32_t vid_idx, vid_bit;
5989
5990         if (vlan_id > ETH_VLAN_ID_MAX)
5991                 return 0;
5992
5993         vid_idx = I40E_VFTA_IDX(vlan_id);
5994         vid_bit = I40E_VFTA_BIT(vlan_id);
5995
5996         if (vsi->vfta[vid_idx] & vid_bit)
5997                 return 1;
5998         else
5999                 return 0;
6000 }
6001
6002 static void
6003 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6004                        uint16_t vlan_id, bool on)
6005 {
6006         uint32_t vid_idx, vid_bit;
6007
6008         vid_idx = I40E_VFTA_IDX(vlan_id);
6009         vid_bit = I40E_VFTA_BIT(vlan_id);
6010
6011         if (on)
6012                 vsi->vfta[vid_idx] |= vid_bit;
6013         else
6014                 vsi->vfta[vid_idx] &= ~vid_bit;
6015 }
6016
6017 static void
6018 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6019                      uint16_t vlan_id, bool on)
6020 {
6021         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6022         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6023         int ret;
6024
6025         if (vlan_id > ETH_VLAN_ID_MAX)
6026                 return;
6027
6028         i40e_store_vlan_filter(vsi, vlan_id, on);
6029
6030         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6031                 return;
6032
6033         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6034
6035         if (on) {
6036                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6037                                        &vlan_data, 1, NULL);
6038                 if (ret != I40E_SUCCESS)
6039                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6040         } else {
6041                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6042                                           &vlan_data, 1, NULL);
6043                 if (ret != I40E_SUCCESS)
6044                         PMD_DRV_LOG(ERR,
6045                                     "Failed to remove vlan filter");
6046         }
6047 }
6048
6049 /**
6050  * Find all vlan options for specific mac addr,
6051  * return with actual vlan found.
6052  */
6053 static inline int
6054 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6055                            struct i40e_macvlan_filter *mv_f,
6056                            int num, struct ether_addr *addr)
6057 {
6058         int i;
6059         uint32_t j, k;
6060
6061         /**
6062          * Not to use i40e_find_vlan_filter to decrease the loop time,
6063          * although the code looks complex.
6064           */
6065         if (num < vsi->vlan_num)
6066                 return I40E_ERR_PARAM;
6067
6068         i = 0;
6069         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6070                 if (vsi->vfta[j]) {
6071                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6072                                 if (vsi->vfta[j] & (1 << k)) {
6073                                         if (i > num - 1) {
6074                                                 PMD_DRV_LOG(ERR,
6075                                                         "vlan number doesn't match");
6076                                                 return I40E_ERR_PARAM;
6077                                         }
6078                                         (void)rte_memcpy(&mv_f[i].macaddr,
6079                                                         addr, ETH_ADDR_LEN);
6080                                         mv_f[i].vlan_id =
6081                                                 j * I40E_UINT32_BIT_SIZE + k;
6082                                         i++;
6083                                 }
6084                         }
6085                 }
6086         }
6087         return I40E_SUCCESS;
6088 }
6089
6090 static inline int
6091 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6092                            struct i40e_macvlan_filter *mv_f,
6093                            int num,
6094                            uint16_t vlan)
6095 {
6096         int i = 0;
6097         struct i40e_mac_filter *f;
6098
6099         if (num < vsi->mac_num)
6100                 return I40E_ERR_PARAM;
6101
6102         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6103                 if (i > num - 1) {
6104                         PMD_DRV_LOG(ERR, "buffer number not match");
6105                         return I40E_ERR_PARAM;
6106                 }
6107                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6108                                 ETH_ADDR_LEN);
6109                 mv_f[i].vlan_id = vlan;
6110                 mv_f[i].filter_type = f->mac_info.filter_type;
6111                 i++;
6112         }
6113
6114         return I40E_SUCCESS;
6115 }
6116
6117 static int
6118 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6119 {
6120         int i, j, num;
6121         struct i40e_mac_filter *f;
6122         struct i40e_macvlan_filter *mv_f;
6123         int ret = I40E_SUCCESS;
6124
6125         if (vsi == NULL || vsi->mac_num == 0)
6126                 return I40E_ERR_PARAM;
6127
6128         /* Case that no vlan is set */
6129         if (vsi->vlan_num == 0)
6130                 num = vsi->mac_num;
6131         else
6132                 num = vsi->mac_num * vsi->vlan_num;
6133
6134         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6135         if (mv_f == NULL) {
6136                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6137                 return I40E_ERR_NO_MEMORY;
6138         }
6139
6140         i = 0;
6141         if (vsi->vlan_num == 0) {
6142                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6143                         (void)rte_memcpy(&mv_f[i].macaddr,
6144                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6145                         mv_f[i].filter_type = f->mac_info.filter_type;
6146                         mv_f[i].vlan_id = 0;
6147                         i++;
6148                 }
6149         } else {
6150                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6151                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6152                                         vsi->vlan_num, &f->mac_info.mac_addr);
6153                         if (ret != I40E_SUCCESS)
6154                                 goto DONE;
6155                         for (j = i; j < i + vsi->vlan_num; j++)
6156                                 mv_f[j].filter_type = f->mac_info.filter_type;
6157                         i += vsi->vlan_num;
6158                 }
6159         }
6160
6161         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6162 DONE:
6163         rte_free(mv_f);
6164
6165         return ret;
6166 }
6167
6168 int
6169 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6170 {
6171         struct i40e_macvlan_filter *mv_f;
6172         int mac_num;
6173         int ret = I40E_SUCCESS;
6174
6175         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6176                 return I40E_ERR_PARAM;
6177
6178         /* If it's already set, just return */
6179         if (i40e_find_vlan_filter(vsi,vlan))
6180                 return I40E_SUCCESS;
6181
6182         mac_num = vsi->mac_num;
6183
6184         if (mac_num == 0) {
6185                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6186                 return I40E_ERR_PARAM;
6187         }
6188
6189         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6190
6191         if (mv_f == NULL) {
6192                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6193                 return I40E_ERR_NO_MEMORY;
6194         }
6195
6196         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6197
6198         if (ret != I40E_SUCCESS)
6199                 goto DONE;
6200
6201         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6202
6203         if (ret != I40E_SUCCESS)
6204                 goto DONE;
6205
6206         i40e_set_vlan_filter(vsi, vlan, 1);
6207
6208         vsi->vlan_num++;
6209         ret = I40E_SUCCESS;
6210 DONE:
6211         rte_free(mv_f);
6212         return ret;
6213 }
6214
6215 int
6216 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6217 {
6218         struct i40e_macvlan_filter *mv_f;
6219         int mac_num;
6220         int ret = I40E_SUCCESS;
6221
6222         /**
6223          * Vlan 0 is the generic filter for untagged packets
6224          * and can't be removed.
6225          */
6226         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6227                 return I40E_ERR_PARAM;
6228
6229         /* If can't find it, just return */
6230         if (!i40e_find_vlan_filter(vsi, vlan))
6231                 return I40E_ERR_PARAM;
6232
6233         mac_num = vsi->mac_num;
6234
6235         if (mac_num == 0) {
6236                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6237                 return I40E_ERR_PARAM;
6238         }
6239
6240         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6241
6242         if (mv_f == NULL) {
6243                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6244                 return I40E_ERR_NO_MEMORY;
6245         }
6246
6247         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6248
6249         if (ret != I40E_SUCCESS)
6250                 goto DONE;
6251
6252         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6253
6254         if (ret != I40E_SUCCESS)
6255                 goto DONE;
6256
6257         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6258         if (vsi->vlan_num == 1) {
6259                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6260                 if (ret != I40E_SUCCESS)
6261                         goto DONE;
6262
6263                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6264                 if (ret != I40E_SUCCESS)
6265                         goto DONE;
6266         }
6267
6268         i40e_set_vlan_filter(vsi, vlan, 0);
6269
6270         vsi->vlan_num--;
6271         ret = I40E_SUCCESS;
6272 DONE:
6273         rte_free(mv_f);
6274         return ret;
6275 }
6276
6277 int
6278 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6279 {
6280         struct i40e_mac_filter *f;
6281         struct i40e_macvlan_filter *mv_f;
6282         int i, vlan_num = 0;
6283         int ret = I40E_SUCCESS;
6284
6285         /* If it's add and we've config it, return */
6286         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6287         if (f != NULL)
6288                 return I40E_SUCCESS;
6289         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6290                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6291
6292                 /**
6293                  * If vlan_num is 0, that's the first time to add mac,
6294                  * set mask for vlan_id 0.
6295                  */
6296                 if (vsi->vlan_num == 0) {
6297                         i40e_set_vlan_filter(vsi, 0, 1);
6298                         vsi->vlan_num = 1;
6299                 }
6300                 vlan_num = vsi->vlan_num;
6301         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6302                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6303                 vlan_num = 1;
6304
6305         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6306         if (mv_f == NULL) {
6307                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6308                 return I40E_ERR_NO_MEMORY;
6309         }
6310
6311         for (i = 0; i < vlan_num; i++) {
6312                 mv_f[i].filter_type = mac_filter->filter_type;
6313                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6314                                 ETH_ADDR_LEN);
6315         }
6316
6317         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6318                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6319                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6320                                         &mac_filter->mac_addr);
6321                 if (ret != I40E_SUCCESS)
6322                         goto DONE;
6323         }
6324
6325         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6326         if (ret != I40E_SUCCESS)
6327                 goto DONE;
6328
6329         /* Add the mac addr into mac list */
6330         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6331         if (f == NULL) {
6332                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6333                 ret = I40E_ERR_NO_MEMORY;
6334                 goto DONE;
6335         }
6336         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6337                         ETH_ADDR_LEN);
6338         f->mac_info.filter_type = mac_filter->filter_type;
6339         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6340         vsi->mac_num++;
6341
6342         ret = I40E_SUCCESS;
6343 DONE:
6344         rte_free(mv_f);
6345
6346         return ret;
6347 }
6348
6349 int
6350 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6351 {
6352         struct i40e_mac_filter *f;
6353         struct i40e_macvlan_filter *mv_f;
6354         int i, vlan_num;
6355         enum rte_mac_filter_type filter_type;
6356         int ret = I40E_SUCCESS;
6357
6358         /* Can't find it, return an error */
6359         f = i40e_find_mac_filter(vsi, addr);
6360         if (f == NULL)
6361                 return I40E_ERR_PARAM;
6362
6363         vlan_num = vsi->vlan_num;
6364         filter_type = f->mac_info.filter_type;
6365         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6366                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6367                 if (vlan_num == 0) {
6368                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6369                         return I40E_ERR_PARAM;
6370                 }
6371         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6372                         filter_type == RTE_MAC_HASH_MATCH)
6373                 vlan_num = 1;
6374
6375         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6376         if (mv_f == NULL) {
6377                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6378                 return I40E_ERR_NO_MEMORY;
6379         }
6380
6381         for (i = 0; i < vlan_num; i++) {
6382                 mv_f[i].filter_type = filter_type;
6383                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6384                                 ETH_ADDR_LEN);
6385         }
6386         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6387                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6388                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6389                 if (ret != I40E_SUCCESS)
6390                         goto DONE;
6391         }
6392
6393         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6394         if (ret != I40E_SUCCESS)
6395                 goto DONE;
6396
6397         /* Remove the mac addr into mac list */
6398         TAILQ_REMOVE(&vsi->mac_list, f, next);
6399         rte_free(f);
6400         vsi->mac_num--;
6401
6402         ret = I40E_SUCCESS;
6403 DONE:
6404         rte_free(mv_f);
6405         return ret;
6406 }
6407
6408 /* Configure hash enable flags for RSS */
6409 uint64_t
6410 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6411 {
6412         uint64_t hena = 0;
6413
6414         if (!flags)
6415                 return hena;
6416
6417         if (flags & ETH_RSS_FRAG_IPV4)
6418                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6419         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6420                 if (type == I40E_MAC_X722) {
6421                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6422                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6423                 } else
6424                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6425         }
6426         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6427                 if (type == I40E_MAC_X722) {
6428                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6429                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6430                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6431                 } else
6432                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6433         }
6434         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6435                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6436         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6437                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6438         if (flags & ETH_RSS_FRAG_IPV6)
6439                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6440         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6441                 if (type == I40E_MAC_X722) {
6442                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6443                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6444                 } else
6445                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6446         }
6447         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6448                 if (type == I40E_MAC_X722) {
6449                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6450                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6451                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6452                 } else
6453                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6454         }
6455         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6456                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6457         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6458                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6459         if (flags & ETH_RSS_L2_PAYLOAD)
6460                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6461
6462         return hena;
6463 }
6464
6465 /* Parse the hash enable flags */
6466 uint64_t
6467 i40e_parse_hena(uint64_t flags)
6468 {
6469         uint64_t rss_hf = 0;
6470
6471         if (!flags)
6472                 return rss_hf;
6473         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6474                 rss_hf |= ETH_RSS_FRAG_IPV4;
6475         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6476                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6477         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6478                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6479         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6480                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6481         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6482                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6483         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6484                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6485         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6486                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6487         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6488                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6490                 rss_hf |= ETH_RSS_FRAG_IPV6;
6491         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6492                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6493         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6494                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6495         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6496                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6497         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6498                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6499         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6500                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6502                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6506                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6507
6508         return rss_hf;
6509 }
6510
6511 /* Disable RSS */
6512 static void
6513 i40e_pf_disable_rss(struct i40e_pf *pf)
6514 {
6515         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6516         uint64_t hena;
6517
6518         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6519         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6520         if (hw->mac.type == I40E_MAC_X722)
6521                 hena &= ~I40E_RSS_HENA_ALL_X722;
6522         else
6523                 hena &= ~I40E_RSS_HENA_ALL;
6524         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6525         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6526         I40E_WRITE_FLUSH(hw);
6527 }
6528
6529 static int
6530 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6531 {
6532         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6533         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6534         int ret = 0;
6535
6536         if (!key || key_len == 0) {
6537                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6538                 return 0;
6539         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6540                 sizeof(uint32_t)) {
6541                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6542                 return -EINVAL;
6543         }
6544
6545         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6546                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6547                         (struct i40e_aqc_get_set_rss_key_data *)key;
6548
6549                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6550                 if (ret)
6551                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6552         } else {
6553                 uint32_t *hash_key = (uint32_t *)key;
6554                 uint16_t i;
6555
6556                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6557                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6558                 I40E_WRITE_FLUSH(hw);
6559         }
6560
6561         return ret;
6562 }
6563
6564 static int
6565 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6566 {
6567         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6569         int ret;
6570
6571         if (!key || !key_len)
6572                 return -EINVAL;
6573
6574         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6575                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6576                         (struct i40e_aqc_get_set_rss_key_data *)key);
6577                 if (ret) {
6578                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6579                         return ret;
6580                 }
6581         } else {
6582                 uint32_t *key_dw = (uint32_t *)key;
6583                 uint16_t i;
6584
6585                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6586                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6587         }
6588         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6589
6590         return 0;
6591 }
6592
6593 static int
6594 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6595 {
6596         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6597         uint64_t rss_hf;
6598         uint64_t hena;
6599         int ret;
6600
6601         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6602                                rss_conf->rss_key_len);
6603         if (ret)
6604                 return ret;
6605
6606         rss_hf = rss_conf->rss_hf;
6607         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6608         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6609         if (hw->mac.type == I40E_MAC_X722)
6610                 hena &= ~I40E_RSS_HENA_ALL_X722;
6611         else
6612                 hena &= ~I40E_RSS_HENA_ALL;
6613         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6614         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6615         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6616         I40E_WRITE_FLUSH(hw);
6617
6618         return 0;
6619 }
6620
6621 static int
6622 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6623                          struct rte_eth_rss_conf *rss_conf)
6624 {
6625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6626         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6627         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6628         uint64_t hena;
6629
6630         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6631         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6632         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6633                  ? I40E_RSS_HENA_ALL_X722
6634                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6635                 if (rss_hf != 0) /* Enable RSS */
6636                         return -EINVAL;
6637                 return 0; /* Nothing to do */
6638         }
6639         /* RSS enabled */
6640         if (rss_hf == 0) /* Disable RSS */
6641                 return -EINVAL;
6642
6643         return i40e_hw_rss_hash_set(pf, rss_conf);
6644 }
6645
6646 static int
6647 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6648                            struct rte_eth_rss_conf *rss_conf)
6649 {
6650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6652         uint64_t hena;
6653
6654         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6655                          &rss_conf->rss_key_len);
6656
6657         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6658         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6659         rss_conf->rss_hf = i40e_parse_hena(hena);
6660
6661         return 0;
6662 }
6663
6664 static int
6665 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6666 {
6667         switch (filter_type) {
6668         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6669                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6670                 break;
6671         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6672                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6673                 break;
6674         case RTE_TUNNEL_FILTER_IMAC_TENID:
6675                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6676                 break;
6677         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6678                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6679                 break;
6680         case ETH_TUNNEL_FILTER_IMAC:
6681                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6682                 break;
6683         case ETH_TUNNEL_FILTER_OIP:
6684                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6685                 break;
6686         case ETH_TUNNEL_FILTER_IIP:
6687                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6688                 break;
6689         default:
6690                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6691                 return -EINVAL;
6692         }
6693
6694         return 0;
6695 }
6696
6697 /* Convert tunnel filter structure */
6698 static int
6699 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6700                            *cld_filter,
6701                            struct i40e_tunnel_filter *tunnel_filter)
6702 {
6703         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6704                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6705         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6706                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6707         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6708         if ((rte_le_to_cpu_16(cld_filter->flags) &
6709              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6710             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6711                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6712         else
6713                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6714         tunnel_filter->input.flags = cld_filter->flags;
6715         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6716         tunnel_filter->queue = cld_filter->queue_number;
6717
6718         return 0;
6719 }
6720
6721 /* Check if there exists the tunnel filter */
6722 struct i40e_tunnel_filter *
6723 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6724                              const struct i40e_tunnel_filter_input *input)
6725 {
6726         int ret;
6727
6728         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6729         if (ret < 0)
6730                 return NULL;
6731
6732         return tunnel_rule->hash_map[ret];
6733 }
6734
6735 /* Add a tunnel filter into the SW list */
6736 static int
6737 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6738                              struct i40e_tunnel_filter *tunnel_filter)
6739 {
6740         struct i40e_tunnel_rule *rule = &pf->tunnel;
6741         int ret;
6742
6743         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6744         if (ret < 0) {
6745                 PMD_DRV_LOG(ERR,
6746                             "Failed to insert tunnel filter to hash table %d!",
6747                             ret);
6748                 return ret;
6749         }
6750         rule->hash_map[ret] = tunnel_filter;
6751
6752         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6753
6754         return 0;
6755 }
6756
6757 /* Delete a tunnel filter from the SW list */
6758 int
6759 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6760                           struct i40e_tunnel_filter_input *input)
6761 {
6762         struct i40e_tunnel_rule *rule = &pf->tunnel;
6763         struct i40e_tunnel_filter *tunnel_filter;
6764         int ret;
6765
6766         ret = rte_hash_del_key(rule->hash_table, input);
6767         if (ret < 0) {
6768                 PMD_DRV_LOG(ERR,
6769                             "Failed to delete tunnel filter to hash table %d!",
6770                             ret);
6771                 return ret;
6772         }
6773         tunnel_filter = rule->hash_map[ret];
6774         rule->hash_map[ret] = NULL;
6775
6776         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6777         rte_free(tunnel_filter);
6778
6779         return 0;
6780 }
6781
6782 int
6783 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6784                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6785                         uint8_t add)
6786 {
6787         uint16_t ip_type;
6788         uint32_t ipv4_addr;
6789         uint8_t i, tun_type = 0;
6790         /* internal varialbe to convert ipv6 byte order */
6791         uint32_t convert_ipv6[4];
6792         int val, ret = 0;
6793         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6794         struct i40e_vsi *vsi = pf->main_vsi;
6795         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6796         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6797         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6798         struct i40e_tunnel_filter *tunnel, *node;
6799         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6800
6801         cld_filter = rte_zmalloc("tunnel_filter",
6802                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6803                 0);
6804
6805         if (NULL == cld_filter) {
6806                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6807                 return -EINVAL;
6808         }
6809         pfilter = cld_filter;
6810
6811         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6812         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6813
6814         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6815         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6816                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6817                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6818                 rte_memcpy(&pfilter->ipaddr.v4.data,
6819                                 &rte_cpu_to_le_32(ipv4_addr),
6820                                 sizeof(pfilter->ipaddr.v4.data));
6821         } else {
6822                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6823                 for (i = 0; i < 4; i++) {
6824                         convert_ipv6[i] =
6825                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6826                 }
6827                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6828                                 sizeof(pfilter->ipaddr.v6.data));
6829         }
6830
6831         /* check tunneled type */
6832         switch (tunnel_filter->tunnel_type) {
6833         case RTE_TUNNEL_TYPE_VXLAN:
6834                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6835                 break;
6836         case RTE_TUNNEL_TYPE_NVGRE:
6837                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6838                 break;
6839         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6840                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6841                 break;
6842         default:
6843                 /* Other tunnel types is not supported. */
6844                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6845                 rte_free(cld_filter);
6846                 return -EINVAL;
6847         }
6848
6849         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6850                                                 &pfilter->flags);
6851         if (val < 0) {
6852                 rte_free(cld_filter);
6853                 return -EINVAL;
6854         }
6855
6856         pfilter->flags |= rte_cpu_to_le_16(
6857                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6858                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6859         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6860         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6861
6862         /* Check if there is the filter in SW list */
6863         memset(&check_filter, 0, sizeof(check_filter));
6864         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6865         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6866         if (add && node) {
6867                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6868                 return -EINVAL;
6869         }
6870
6871         if (!add && !node) {
6872                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6873                 return -EINVAL;
6874         }
6875
6876         if (add) {
6877                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6878                 if (ret < 0) {
6879                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6880                         return ret;
6881                 }
6882                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6883                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6884                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6885         } else {
6886                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6887                                                    cld_filter, 1);
6888                 if (ret < 0) {
6889                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6890                         return ret;
6891                 }
6892                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6893         }
6894
6895         rte_free(cld_filter);
6896         return ret;
6897 }
6898
6899 static int
6900 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6901 {
6902         uint8_t i;
6903
6904         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6905                 if (pf->vxlan_ports[i] == port)
6906                         return i;
6907         }
6908
6909         return -1;
6910 }
6911
6912 static int
6913 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6914 {
6915         int  idx, ret;
6916         uint8_t filter_idx;
6917         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6918
6919         idx = i40e_get_vxlan_port_idx(pf, port);
6920
6921         /* Check if port already exists */
6922         if (idx >= 0) {
6923                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6924                 return -EINVAL;
6925         }
6926
6927         /* Now check if there is space to add the new port */
6928         idx = i40e_get_vxlan_port_idx(pf, 0);
6929         if (idx < 0) {
6930                 PMD_DRV_LOG(ERR,
6931                         "Maximum number of UDP ports reached, not adding port %d",
6932                         port);
6933                 return -ENOSPC;
6934         }
6935
6936         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6937                                         &filter_idx, NULL);
6938         if (ret < 0) {
6939                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6940                 return -1;
6941         }
6942
6943         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6944                          port,  filter_idx);
6945
6946         /* New port: add it and mark its index in the bitmap */
6947         pf->vxlan_ports[idx] = port;
6948         pf->vxlan_bitmap |= (1 << idx);
6949
6950         if (!(pf->flags & I40E_FLAG_VXLAN))
6951                 pf->flags |= I40E_FLAG_VXLAN;
6952
6953         return 0;
6954 }
6955
6956 static int
6957 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6958 {
6959         int idx;
6960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6961
6962         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6963                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6964                 return -EINVAL;
6965         }
6966
6967         idx = i40e_get_vxlan_port_idx(pf, port);
6968
6969         if (idx < 0) {
6970                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6971                 return -EINVAL;
6972         }
6973
6974         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6975                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6976                 return -1;
6977         }
6978
6979         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6980                         port, idx);
6981
6982         pf->vxlan_ports[idx] = 0;
6983         pf->vxlan_bitmap &= ~(1 << idx);
6984
6985         if (!pf->vxlan_bitmap)
6986                 pf->flags &= ~I40E_FLAG_VXLAN;
6987
6988         return 0;
6989 }
6990
6991 /* Add UDP tunneling port */
6992 static int
6993 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6994                              struct rte_eth_udp_tunnel *udp_tunnel)
6995 {
6996         int ret = 0;
6997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6998
6999         if (udp_tunnel == NULL)
7000                 return -EINVAL;
7001
7002         switch (udp_tunnel->prot_type) {
7003         case RTE_TUNNEL_TYPE_VXLAN:
7004                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7005                 break;
7006
7007         case RTE_TUNNEL_TYPE_GENEVE:
7008         case RTE_TUNNEL_TYPE_TEREDO:
7009                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7010                 ret = -1;
7011                 break;
7012
7013         default:
7014                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7015                 ret = -1;
7016                 break;
7017         }
7018
7019         return ret;
7020 }
7021
7022 /* Remove UDP tunneling port */
7023 static int
7024 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7025                              struct rte_eth_udp_tunnel *udp_tunnel)
7026 {
7027         int ret = 0;
7028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7029
7030         if (udp_tunnel == NULL)
7031                 return -EINVAL;
7032
7033         switch (udp_tunnel->prot_type) {
7034         case RTE_TUNNEL_TYPE_VXLAN:
7035                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7036                 break;
7037         case RTE_TUNNEL_TYPE_GENEVE:
7038         case RTE_TUNNEL_TYPE_TEREDO:
7039                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7040                 ret = -1;
7041                 break;
7042         default:
7043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7044                 ret = -1;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 /* Calculate the maximum number of contiguous PF queues that are configured */
7052 static int
7053 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7054 {
7055         struct rte_eth_dev_data *data = pf->dev_data;
7056         int i, num;
7057         struct i40e_rx_queue *rxq;
7058
7059         num = 0;
7060         for (i = 0; i < pf->lan_nb_qps; i++) {
7061                 rxq = data->rx_queues[i];
7062                 if (rxq && rxq->q_set)
7063                         num++;
7064                 else
7065                         break;
7066         }
7067
7068         return num;
7069 }
7070
7071 /* Configure RSS */
7072 static int
7073 i40e_pf_config_rss(struct i40e_pf *pf)
7074 {
7075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7076         struct rte_eth_rss_conf rss_conf;
7077         uint32_t i, lut = 0;
7078         uint16_t j, num;
7079
7080         /*
7081          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7082          * It's necessary to calulate the actual PF queues that are configured.
7083          */
7084         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7085                 num = i40e_pf_calc_configured_queues_num(pf);
7086         else
7087                 num = pf->dev_data->nb_rx_queues;
7088
7089         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7090         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7091                         num);
7092
7093         if (num == 0) {
7094                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7095                 return -ENOTSUP;
7096         }
7097
7098         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7099                 if (j == num)
7100                         j = 0;
7101                 lut = (lut << 8) | (j & ((0x1 <<
7102                         hw->func_caps.rss_table_entry_width) - 1));
7103                 if ((i & 3) == 3)
7104                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7105         }
7106
7107         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7108         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7109                 i40e_pf_disable_rss(pf);
7110                 return 0;
7111         }
7112         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7113                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7114                 /* Random default keys */
7115                 static uint32_t rss_key_default[] = {0x6b793944,
7116                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7117                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7118                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7119
7120                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7121                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7122                                                         sizeof(uint32_t);
7123         }
7124
7125         return i40e_hw_rss_hash_set(pf, &rss_conf);
7126 }
7127
7128 static int
7129 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7130                                struct rte_eth_tunnel_filter_conf *filter)
7131 {
7132         if (pf == NULL || filter == NULL) {
7133                 PMD_DRV_LOG(ERR, "Invalid parameter");
7134                 return -EINVAL;
7135         }
7136
7137         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7138                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7139                 return -EINVAL;
7140         }
7141
7142         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7143                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7144                 return -EINVAL;
7145         }
7146
7147         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7148                 (is_zero_ether_addr(&filter->outer_mac))) {
7149                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7150                 return -EINVAL;
7151         }
7152
7153         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7154                 (is_zero_ether_addr(&filter->inner_mac))) {
7155                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7156                 return -EINVAL;
7157         }
7158
7159         return 0;
7160 }
7161
7162 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7163 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7164 static int
7165 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7166 {
7167         uint32_t val, reg;
7168         int ret = -EINVAL;
7169
7170         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7171         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7172
7173         if (len == 3) {
7174                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7175         } else if (len == 4) {
7176                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7177         } else {
7178                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7179                 return ret;
7180         }
7181
7182         if (reg != val) {
7183                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7184                                                    reg, NULL);
7185                 if (ret != 0)
7186                         return ret;
7187         } else {
7188                 ret = 0;
7189         }
7190         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7191                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7192
7193         return ret;
7194 }
7195
7196 static int
7197 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7198 {
7199         int ret = -EINVAL;
7200
7201         if (!hw || !cfg)
7202                 return -EINVAL;
7203
7204         switch (cfg->cfg_type) {
7205         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7206                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7207                 break;
7208         default:
7209                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7210                 break;
7211         }
7212
7213         return ret;
7214 }
7215
7216 static int
7217 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7218                                enum rte_filter_op filter_op,
7219                                void *arg)
7220 {
7221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222         int ret = I40E_ERR_PARAM;
7223
7224         switch (filter_op) {
7225         case RTE_ETH_FILTER_SET:
7226                 ret = i40e_dev_global_config_set(hw,
7227                         (struct rte_eth_global_cfg *)arg);
7228                 break;
7229         default:
7230                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7231                 break;
7232         }
7233
7234         return ret;
7235 }
7236
7237 static int
7238 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7239                           enum rte_filter_op filter_op,
7240                           void *arg)
7241 {
7242         struct rte_eth_tunnel_filter_conf *filter;
7243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7244         int ret = I40E_SUCCESS;
7245
7246         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7247
7248         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7249                 return I40E_ERR_PARAM;
7250
7251         switch (filter_op) {
7252         case RTE_ETH_FILTER_NOP:
7253                 if (!(pf->flags & I40E_FLAG_VXLAN))
7254                         ret = I40E_NOT_SUPPORTED;
7255                 break;
7256         case RTE_ETH_FILTER_ADD:
7257                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7258                 break;
7259         case RTE_ETH_FILTER_DELETE:
7260                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7261                 break;
7262         default:
7263                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7264                 ret = I40E_ERR_PARAM;
7265                 break;
7266         }
7267
7268         return ret;
7269 }
7270
7271 static int
7272 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7273 {
7274         int ret = 0;
7275         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7276
7277         /* RSS setup */
7278         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7279                 ret = i40e_pf_config_rss(pf);
7280         else
7281                 i40e_pf_disable_rss(pf);
7282
7283         return ret;
7284 }
7285
7286 /* Get the symmetric hash enable configurations per port */
7287 static void
7288 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7289 {
7290         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7291
7292         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7293 }
7294
7295 /* Set the symmetric hash enable configurations per port */
7296 static void
7297 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7298 {
7299         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7300
7301         if (enable > 0) {
7302                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7303                         PMD_DRV_LOG(INFO,
7304                                 "Symmetric hash has already been enabled");
7305                         return;
7306                 }
7307                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7308         } else {
7309                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7310                         PMD_DRV_LOG(INFO,
7311                                 "Symmetric hash has already been disabled");
7312                         return;
7313                 }
7314                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7315         }
7316         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7317         I40E_WRITE_FLUSH(hw);
7318 }
7319
7320 /*
7321  * Get global configurations of hash function type and symmetric hash enable
7322  * per flow type (pctype). Note that global configuration means it affects all
7323  * the ports on the same NIC.
7324  */
7325 static int
7326 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7327                                    struct rte_eth_hash_global_conf *g_cfg)
7328 {
7329         uint32_t reg, mask = I40E_FLOW_TYPES;
7330         uint16_t i;
7331         enum i40e_filter_pctype pctype;
7332
7333         memset(g_cfg, 0, sizeof(*g_cfg));
7334         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7335         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7336                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7337         else
7338                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7339         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7340                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7341
7342         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7343                 if (!(mask & (1UL << i)))
7344                         continue;
7345                 mask &= ~(1UL << i);
7346                 /* Bit set indicats the coresponding flow type is supported */
7347                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7348                 /* if flowtype is invalid, continue */
7349                 if (!I40E_VALID_FLOW(i))
7350                         continue;
7351                 pctype = i40e_flowtype_to_pctype(i);
7352                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7353                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7354                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7355         }
7356
7357         return 0;
7358 }
7359
7360 static int
7361 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7362 {
7363         uint32_t i;
7364         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7365
7366         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7367                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7368                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7369                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7370                                                 g_cfg->hash_func);
7371                 return -EINVAL;
7372         }
7373
7374         /*
7375          * As i40e supports less than 32 flow types, only first 32 bits need to
7376          * be checked.
7377          */
7378         mask0 = g_cfg->valid_bit_mask[0];
7379         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7380                 if (i == 0) {
7381                         /* Check if any unsupported flow type configured */
7382                         if ((mask0 | i40e_mask) ^ i40e_mask)
7383                                 goto mask_err;
7384                 } else {
7385                         if (g_cfg->valid_bit_mask[i])
7386                                 goto mask_err;
7387                 }
7388         }
7389
7390         return 0;
7391
7392 mask_err:
7393         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7394
7395         return -EINVAL;
7396 }
7397
7398 /*
7399  * Set global configurations of hash function type and symmetric hash enable
7400  * per flow type (pctype). Note any modifying global configuration will affect
7401  * all the ports on the same NIC.
7402  */
7403 static int
7404 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7405                                    struct rte_eth_hash_global_conf *g_cfg)
7406 {
7407         int ret;
7408         uint16_t i;
7409         uint32_t reg;
7410         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7411         enum i40e_filter_pctype pctype;
7412
7413         /* Check the input parameters */
7414         ret = i40e_hash_global_config_check(g_cfg);
7415         if (ret < 0)
7416                 return ret;
7417
7418         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7419                 if (!(mask0 & (1UL << i)))
7420                         continue;
7421                 mask0 &= ~(1UL << i);
7422                 /* if flowtype is invalid, continue */
7423                 if (!I40E_VALID_FLOW(i))
7424                         continue;
7425                 pctype = i40e_flowtype_to_pctype(i);
7426                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7427                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7428                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7429         }
7430
7431         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7432         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7433                 /* Toeplitz */
7434                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7435                         PMD_DRV_LOG(DEBUG,
7436                                 "Hash function already set to Toeplitz");
7437                         goto out;
7438                 }
7439                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7440         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7441                 /* Simple XOR */
7442                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7443                         PMD_DRV_LOG(DEBUG,
7444                                 "Hash function already set to Simple XOR");
7445                         goto out;
7446                 }
7447                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7448         } else
7449                 /* Use the default, and keep it as it is */
7450                 goto out;
7451
7452         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7453
7454 out:
7455         I40E_WRITE_FLUSH(hw);
7456
7457         return 0;
7458 }
7459
7460 /**
7461  * Valid input sets for hash and flow director filters per PCTYPE
7462  */
7463 static uint64_t
7464 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7465                 enum rte_filter_type filter)
7466 {
7467         uint64_t valid;
7468
7469         static const uint64_t valid_hash_inset_table[] = {
7470                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7471                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7472                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7473                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7474                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7477                         I40E_INSET_FLEX_PAYLOAD,
7478                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7479                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7480                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7481                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7482                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7483                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7484                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7485                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7486                         I40E_INSET_FLEX_PAYLOAD,
7487                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7491                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7492                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7493                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7495                         I40E_INSET_FLEX_PAYLOAD,
7496                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7500                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7501                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7502                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7503                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7504                         I40E_INSET_FLEX_PAYLOAD,
7505                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7509                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7510                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7511                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7512                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7513                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7514                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7518                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7519                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7520                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7521                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7522                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7523                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7527                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7528                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7529                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7530                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7531                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7536                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7537                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7538                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7539                         I40E_INSET_FLEX_PAYLOAD,
7540                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7544                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7545                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7546                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7547                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7548                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7549                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7550                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7551                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7552                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7553                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7554                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7555                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7556                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7560                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7561                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7562                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7563                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7564                         I40E_INSET_FLEX_PAYLOAD,
7565                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7569                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7570                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7571                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7572                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7573                         I40E_INSET_FLEX_PAYLOAD,
7574                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7578                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7579                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7580                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7581                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7582                         I40E_INSET_FLEX_PAYLOAD,
7583                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7584                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7585                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7587                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7588                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7589                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7590                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7591                         I40E_INSET_FLEX_PAYLOAD,
7592                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7596                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7597                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7598                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7599                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7600                         I40E_INSET_FLEX_PAYLOAD,
7601                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7605                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7606                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7607                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7608                         I40E_INSET_FLEX_PAYLOAD,
7609                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7610                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7611                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7613                         I40E_INSET_FLEX_PAYLOAD,
7614         };
7615
7616         /**
7617          * Flow director supports only fields defined in
7618          * union rte_eth_fdir_flow.
7619          */
7620         static const uint64_t valid_fdir_inset_table[] = {
7621                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7622                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7624                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7625                 I40E_INSET_IPV4_TTL,
7626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7627                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7629                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7630                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7632                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7634                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7635                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7637                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7639                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7640                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7642                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7644                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7645                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7647                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7649                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7650                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7651                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7652                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7654                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7655                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7656                 I40E_INSET_SCTP_VT,
7657                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7658                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7659                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7660                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7661                 I40E_INSET_IPV4_TTL,
7662                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7663                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7664                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7665                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7666                 I40E_INSET_IPV6_HOP_LIMIT,
7667                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7668                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7669                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7670                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7671                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7672                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7673                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7674                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7675                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7676                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7677                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7678                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7679                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7680                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7681                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7682                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7683                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7684                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7685                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7686                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7687                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7688                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7689                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7690                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7691                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7692                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7693                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7694                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7695                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7696                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7697                 I40E_INSET_SCTP_VT,
7698                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7699                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7700                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7701                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7702                 I40E_INSET_IPV6_HOP_LIMIT,
7703                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7704                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7705                 I40E_INSET_LAST_ETHER_TYPE,
7706         };
7707
7708         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7709                 return 0;
7710         if (filter == RTE_ETH_FILTER_HASH)
7711                 valid = valid_hash_inset_table[pctype];
7712         else
7713                 valid = valid_fdir_inset_table[pctype];
7714
7715         return valid;
7716 }
7717
7718 /**
7719  * Validate if the input set is allowed for a specific PCTYPE
7720  */
7721 static int
7722 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7723                 enum rte_filter_type filter, uint64_t inset)
7724 {
7725         uint64_t valid;
7726
7727         valid = i40e_get_valid_input_set(pctype, filter);
7728         if (inset & (~valid))
7729                 return -EINVAL;
7730
7731         return 0;
7732 }
7733
7734 /* default input set fields combination per pctype */
7735 uint64_t
7736 i40e_get_default_input_set(uint16_t pctype)
7737 {
7738         static const uint64_t default_inset_table[] = {
7739                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7740                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7741                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7742                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7743                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7744                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7745                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7747                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7750                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7759                         I40E_INSET_SCTP_VT,
7760                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7761                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7762                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7763                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7764                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7765                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7766                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7767                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7768                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7770                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7771                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7773                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7782                         I40E_INSET_SCTP_VT,
7783                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7784                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7785                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7786                         I40E_INSET_LAST_ETHER_TYPE,
7787         };
7788
7789         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7790                 return 0;
7791
7792         return default_inset_table[pctype];
7793 }
7794
7795 /**
7796  * Parse the input set from index to logical bit masks
7797  */
7798 static int
7799 i40e_parse_input_set(uint64_t *inset,
7800                      enum i40e_filter_pctype pctype,
7801                      enum rte_eth_input_set_field *field,
7802                      uint16_t size)
7803 {
7804         uint16_t i, j;
7805         int ret = -EINVAL;
7806
7807         static const struct {
7808                 enum rte_eth_input_set_field field;
7809                 uint64_t inset;
7810         } inset_convert_table[] = {
7811                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7812                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7813                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7814                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7815                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7816                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7817                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7818                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7819                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7820                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7821                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7822                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7823                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7824                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7825                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7826                         I40E_INSET_IPV6_NEXT_HDR},
7827                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7828                         I40E_INSET_IPV6_HOP_LIMIT},
7829                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7830                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7831                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7832                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7833                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7834                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7835                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7836                         I40E_INSET_SCTP_VT},
7837                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7838                         I40E_INSET_TUNNEL_DMAC},
7839                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7840                         I40E_INSET_VLAN_TUNNEL},
7841                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7842                         I40E_INSET_TUNNEL_ID},
7843                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7844                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7845                         I40E_INSET_FLEX_PAYLOAD_W1},
7846                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7847                         I40E_INSET_FLEX_PAYLOAD_W2},
7848                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7849                         I40E_INSET_FLEX_PAYLOAD_W3},
7850                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7851                         I40E_INSET_FLEX_PAYLOAD_W4},
7852                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7853                         I40E_INSET_FLEX_PAYLOAD_W5},
7854                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7855                         I40E_INSET_FLEX_PAYLOAD_W6},
7856                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7857                         I40E_INSET_FLEX_PAYLOAD_W7},
7858                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7859                         I40E_INSET_FLEX_PAYLOAD_W8},
7860         };
7861
7862         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7863                 return ret;
7864
7865         /* Only one item allowed for default or all */
7866         if (size == 1) {
7867                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7868                         *inset = i40e_get_default_input_set(pctype);
7869                         return 0;
7870                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7871                         *inset = I40E_INSET_NONE;
7872                         return 0;
7873                 }
7874         }
7875
7876         for (i = 0, *inset = 0; i < size; i++) {
7877                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7878                         if (field[i] == inset_convert_table[j].field) {
7879                                 *inset |= inset_convert_table[j].inset;
7880                                 break;
7881                         }
7882                 }
7883
7884                 /* It contains unsupported input set, return immediately */
7885                 if (j == RTE_DIM(inset_convert_table))
7886                         return ret;
7887         }
7888
7889         return 0;
7890 }
7891
7892 /**
7893  * Translate the input set from bit masks to register aware bit masks
7894  * and vice versa
7895  */
7896 static uint64_t
7897 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7898 {
7899         uint64_t val = 0;
7900         uint16_t i;
7901
7902         struct inset_map {
7903                 uint64_t inset;
7904                 uint64_t inset_reg;
7905         };
7906
7907         static const struct inset_map inset_map_common[] = {
7908                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7909                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7910                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7911                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7912                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7913                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7914                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7915                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7916                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7917                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7918                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7919                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7920                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7921                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7922                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7923                 {I40E_INSET_TUNNEL_DMAC,
7924                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7925                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7926                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7927                 {I40E_INSET_TUNNEL_SRC_PORT,
7928                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7929                 {I40E_INSET_TUNNEL_DST_PORT,
7930                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7931                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7932                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7933                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7934                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7935                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7936                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7937                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7938                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7939                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7940         };
7941
7942     /* some different registers map in x722*/
7943         static const struct inset_map inset_map_diff_x722[] = {
7944                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7945                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7946                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7947                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7948         };
7949
7950         static const struct inset_map inset_map_diff_not_x722[] = {
7951                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7952                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7953                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7954                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7955         };
7956
7957         if (input == 0)
7958                 return val;
7959
7960         /* Translate input set to register aware inset */
7961         if (type == I40E_MAC_X722) {
7962                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7963                         if (input & inset_map_diff_x722[i].inset)
7964                                 val |= inset_map_diff_x722[i].inset_reg;
7965                 }
7966         } else {
7967                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7968                         if (input & inset_map_diff_not_x722[i].inset)
7969                                 val |= inset_map_diff_not_x722[i].inset_reg;
7970                 }
7971         }
7972
7973         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7974                 if (input & inset_map_common[i].inset)
7975                         val |= inset_map_common[i].inset_reg;
7976         }
7977
7978         return val;
7979 }
7980
7981 static int
7982 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7983 {
7984         uint8_t i, idx = 0;
7985         uint64_t inset_need_mask = inset;
7986
7987         static const struct {
7988                 uint64_t inset;
7989                 uint32_t mask;
7990         } inset_mask_map[] = {
7991                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7992                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7993                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7994                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7995                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7996                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7997                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7998                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7999         };
8000
8001         if (!inset || !mask || !nb_elem)
8002                 return 0;
8003
8004         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8005                 /* Clear the inset bit, if no MASK is required,
8006                  * for example proto + ttl
8007                  */
8008                 if ((inset & inset_mask_map[i].inset) ==
8009                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8010                         inset_need_mask &= ~inset_mask_map[i].inset;
8011                 if (!inset_need_mask)
8012                         return 0;
8013         }
8014         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8015                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8016                     inset_mask_map[i].inset) {
8017                         if (idx >= nb_elem) {
8018                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8019                                 return -EINVAL;
8020                         }
8021                         mask[idx] = inset_mask_map[i].mask;
8022                         idx++;
8023                 }
8024         }
8025
8026         return idx;
8027 }
8028
8029 static void
8030 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8031 {
8032         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8033
8034         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8035         if (reg != val)
8036                 i40e_write_rx_ctl(hw, addr, val);
8037         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8038                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8039 }
8040
8041 static void
8042 i40e_filter_input_set_init(struct i40e_pf *pf)
8043 {
8044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8045         enum i40e_filter_pctype pctype;
8046         uint64_t input_set, inset_reg;
8047         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8048         int num, i;
8049
8050         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8051              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8052                 if (hw->mac.type == I40E_MAC_X722) {
8053                         if (!I40E_VALID_PCTYPE_X722(pctype))
8054                                 continue;
8055                 } else {
8056                         if (!I40E_VALID_PCTYPE(pctype))
8057                                 continue;
8058                 }
8059
8060                 input_set = i40e_get_default_input_set(pctype);
8061
8062                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8063                                                    I40E_INSET_MASK_NUM_REG);
8064                 if (num < 0)
8065                         return;
8066                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8067                                         input_set);
8068
8069                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8070                                       (uint32_t)(inset_reg & UINT32_MAX));
8071                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8072                                      (uint32_t)((inset_reg >>
8073                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8074                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8075                                       (uint32_t)(inset_reg & UINT32_MAX));
8076                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8077                                      (uint32_t)((inset_reg >>
8078                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8079
8080                 for (i = 0; i < num; i++) {
8081                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8082                                              mask_reg[i]);
8083                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8084                                              mask_reg[i]);
8085                 }
8086                 /*clear unused mask registers of the pctype */
8087                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8088                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8089                                              0);
8090                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8091                                              0);
8092                 }
8093                 I40E_WRITE_FLUSH(hw);
8094
8095                 /* store the default input set */
8096                 pf->hash_input_set[pctype] = input_set;
8097                 pf->fdir.input_set[pctype] = input_set;
8098         }
8099 }
8100
8101 int
8102 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8103                          struct rte_eth_input_set_conf *conf)
8104 {
8105         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8106         enum i40e_filter_pctype pctype;
8107         uint64_t input_set, inset_reg = 0;
8108         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8109         int ret, i, num;
8110
8111         if (!conf) {
8112                 PMD_DRV_LOG(ERR, "Invalid pointer");
8113                 return -EFAULT;
8114         }
8115         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8116             conf->op != RTE_ETH_INPUT_SET_ADD) {
8117                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8118                 return -EINVAL;
8119         }
8120
8121         if (!I40E_VALID_FLOW(conf->flow_type)) {
8122                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8123                 return -EINVAL;
8124         }
8125
8126         if (hw->mac.type == I40E_MAC_X722) {
8127                 /* get translated pctype value in fd pctype register */
8128                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8129                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8130                         conf->flow_type)));
8131         } else
8132                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8133
8134         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8135                                    conf->inset_size);
8136         if (ret) {
8137                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8138                 return -EINVAL;
8139         }
8140         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8141                                     input_set) != 0) {
8142                 PMD_DRV_LOG(ERR, "Invalid input set");
8143                 return -EINVAL;
8144         }
8145         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8146                 /* get inset value in register */
8147                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8148                 inset_reg <<= I40E_32_BIT_WIDTH;
8149                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8150                 input_set |= pf->hash_input_set[pctype];
8151         }
8152         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8153                                            I40E_INSET_MASK_NUM_REG);
8154         if (num < 0)
8155                 return -EINVAL;
8156
8157         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8158
8159         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8160                               (uint32_t)(inset_reg & UINT32_MAX));
8161         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8162                              (uint32_t)((inset_reg >>
8163                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8164
8165         for (i = 0; i < num; i++)
8166                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8167                                      mask_reg[i]);
8168         /*clear unused mask registers of the pctype */
8169         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8170                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8171                                      0);
8172         I40E_WRITE_FLUSH(hw);
8173
8174         pf->hash_input_set[pctype] = input_set;
8175         return 0;
8176 }
8177
8178 int
8179 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8180                          struct rte_eth_input_set_conf *conf)
8181 {
8182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8183         enum i40e_filter_pctype pctype;
8184         uint64_t input_set, inset_reg = 0;
8185         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8186         int ret, i, num;
8187
8188         if (!hw || !conf) {
8189                 PMD_DRV_LOG(ERR, "Invalid pointer");
8190                 return -EFAULT;
8191         }
8192         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8193             conf->op != RTE_ETH_INPUT_SET_ADD) {
8194                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8195                 return -EINVAL;
8196         }
8197
8198         if (!I40E_VALID_FLOW(conf->flow_type)) {
8199                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8200                 return -EINVAL;
8201         }
8202
8203         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8204
8205         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8206                                    conf->inset_size);
8207         if (ret) {
8208                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8209                 return -EINVAL;
8210         }
8211         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8212                                     input_set) != 0) {
8213                 PMD_DRV_LOG(ERR, "Invalid input set");
8214                 return -EINVAL;
8215         }
8216
8217         /* get inset value in register */
8218         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8219         inset_reg <<= I40E_32_BIT_WIDTH;
8220         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8221
8222         /* Can not change the inset reg for flex payload for fdir,
8223          * it is done by writing I40E_PRTQF_FD_FLXINSET
8224          * in i40e_set_flex_mask_on_pctype.
8225          */
8226         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8227                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8228         else
8229                 input_set |= pf->fdir.input_set[pctype];
8230         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8231                                            I40E_INSET_MASK_NUM_REG);
8232         if (num < 0)
8233                 return -EINVAL;
8234
8235         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8236
8237         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8238                               (uint32_t)(inset_reg & UINT32_MAX));
8239         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8240                              (uint32_t)((inset_reg >>
8241                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8242
8243         for (i = 0; i < num; i++)
8244                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8245                                      mask_reg[i]);
8246         /*clear unused mask registers of the pctype */
8247         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8248                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8249                                      0);
8250         I40E_WRITE_FLUSH(hw);
8251
8252         pf->fdir.input_set[pctype] = input_set;
8253         return 0;
8254 }
8255
8256 static int
8257 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8258 {
8259         int ret = 0;
8260
8261         if (!hw || !info) {
8262                 PMD_DRV_LOG(ERR, "Invalid pointer");
8263                 return -EFAULT;
8264         }
8265
8266         switch (info->info_type) {
8267         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8268                 i40e_get_symmetric_hash_enable_per_port(hw,
8269                                         &(info->info.enable));
8270                 break;
8271         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8272                 ret = i40e_get_hash_filter_global_config(hw,
8273                                 &(info->info.global_conf));
8274                 break;
8275         default:
8276                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8277                                                         info->info_type);
8278                 ret = -EINVAL;
8279                 break;
8280         }
8281
8282         return ret;
8283 }
8284
8285 static int
8286 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8287 {
8288         int ret = 0;
8289
8290         if (!hw || !info) {
8291                 PMD_DRV_LOG(ERR, "Invalid pointer");
8292                 return -EFAULT;
8293         }
8294
8295         switch (info->info_type) {
8296         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8297                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8298                 break;
8299         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8300                 ret = i40e_set_hash_filter_global_config(hw,
8301                                 &(info->info.global_conf));
8302                 break;
8303         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8304                 ret = i40e_hash_filter_inset_select(hw,
8305                                                &(info->info.input_set_conf));
8306                 break;
8307
8308         default:
8309                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8310                                                         info->info_type);
8311                 ret = -EINVAL;
8312                 break;
8313         }
8314
8315         return ret;
8316 }
8317
8318 /* Operations for hash function */
8319 static int
8320 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8321                       enum rte_filter_op filter_op,
8322                       void *arg)
8323 {
8324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8325         int ret = 0;
8326
8327         switch (filter_op) {
8328         case RTE_ETH_FILTER_NOP:
8329                 break;
8330         case RTE_ETH_FILTER_GET:
8331                 ret = i40e_hash_filter_get(hw,
8332                         (struct rte_eth_hash_filter_info *)arg);
8333                 break;
8334         case RTE_ETH_FILTER_SET:
8335                 ret = i40e_hash_filter_set(hw,
8336                         (struct rte_eth_hash_filter_info *)arg);
8337                 break;
8338         default:
8339                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8340                                                                 filter_op);
8341                 ret = -ENOTSUP;
8342                 break;
8343         }
8344
8345         return ret;
8346 }
8347
8348 /* Convert ethertype filter structure */
8349 static int
8350 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8351                               struct i40e_ethertype_filter *filter)
8352 {
8353         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8354         filter->input.ether_type = input->ether_type;
8355         filter->flags = input->flags;
8356         filter->queue = input->queue;
8357
8358         return 0;
8359 }
8360
8361 /* Check if there exists the ehtertype filter */
8362 struct i40e_ethertype_filter *
8363 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8364                                 const struct i40e_ethertype_filter_input *input)
8365 {
8366         int ret;
8367
8368         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8369         if (ret < 0)
8370                 return NULL;
8371
8372         return ethertype_rule->hash_map[ret];
8373 }
8374
8375 /* Add ethertype filter in SW list */
8376 static int
8377 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8378                                 struct i40e_ethertype_filter *filter)
8379 {
8380         struct i40e_ethertype_rule *rule = &pf->ethertype;
8381         int ret;
8382
8383         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8384         if (ret < 0) {
8385                 PMD_DRV_LOG(ERR,
8386                             "Failed to insert ethertype filter"
8387                             " to hash table %d!",
8388                             ret);
8389                 return ret;
8390         }
8391         rule->hash_map[ret] = filter;
8392
8393         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8394
8395         return 0;
8396 }
8397
8398 /* Delete ethertype filter in SW list */
8399 int
8400 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8401                              struct i40e_ethertype_filter_input *input)
8402 {
8403         struct i40e_ethertype_rule *rule = &pf->ethertype;
8404         struct i40e_ethertype_filter *filter;
8405         int ret;
8406
8407         ret = rte_hash_del_key(rule->hash_table, input);
8408         if (ret < 0) {
8409                 PMD_DRV_LOG(ERR,
8410                             "Failed to delete ethertype filter"
8411                             " to hash table %d!",
8412                             ret);
8413                 return ret;
8414         }
8415         filter = rule->hash_map[ret];
8416         rule->hash_map[ret] = NULL;
8417
8418         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8419         rte_free(filter);
8420
8421         return 0;
8422 }
8423
8424 /*
8425  * Configure ethertype filter, which can director packet by filtering
8426  * with mac address and ether_type or only ether_type
8427  */
8428 int
8429 i40e_ethertype_filter_set(struct i40e_pf *pf,
8430                         struct rte_eth_ethertype_filter *filter,
8431                         bool add)
8432 {
8433         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8434         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8435         struct i40e_ethertype_filter *ethertype_filter, *node;
8436         struct i40e_ethertype_filter check_filter;
8437         struct i40e_control_filter_stats stats;
8438         uint16_t flags = 0;
8439         int ret;
8440
8441         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8442                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8443                 return -EINVAL;
8444         }
8445         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8446                 filter->ether_type == ETHER_TYPE_IPv6) {
8447                 PMD_DRV_LOG(ERR,
8448                         "unsupported ether_type(0x%04x) in control packet filter.",
8449                         filter->ether_type);
8450                 return -EINVAL;
8451         }
8452         if (filter->ether_type == ETHER_TYPE_VLAN)
8453                 PMD_DRV_LOG(WARNING,
8454                         "filter vlan ether_type in first tag is not supported.");
8455
8456         /* Check if there is the filter in SW list */
8457         memset(&check_filter, 0, sizeof(check_filter));
8458         i40e_ethertype_filter_convert(filter, &check_filter);
8459         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8460                                                &check_filter.input);
8461         if (add && node) {
8462                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8463                 return -EINVAL;
8464         }
8465
8466         if (!add && !node) {
8467                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8468                 return -EINVAL;
8469         }
8470
8471         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8472                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8473         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8474                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8475         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8476
8477         memset(&stats, 0, sizeof(stats));
8478         ret = i40e_aq_add_rem_control_packet_filter(hw,
8479                         filter->mac_addr.addr_bytes,
8480                         filter->ether_type, flags,
8481                         pf->main_vsi->seid,
8482                         filter->queue, add, &stats, NULL);
8483
8484         PMD_DRV_LOG(INFO,
8485                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8486                 ret, stats.mac_etype_used, stats.etype_used,
8487                 stats.mac_etype_free, stats.etype_free);
8488         if (ret < 0)
8489                 return -ENOSYS;
8490
8491         /* Add or delete a filter in SW list */
8492         if (add) {
8493                 ethertype_filter = rte_zmalloc("ethertype_filter",
8494                                        sizeof(*ethertype_filter), 0);
8495                 rte_memcpy(ethertype_filter, &check_filter,
8496                            sizeof(check_filter));
8497                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8498         } else {
8499                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8500         }
8501
8502         return ret;
8503 }
8504
8505 /*
8506  * Handle operations for ethertype filter.
8507  */
8508 static int
8509 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8510                                 enum rte_filter_op filter_op,
8511                                 void *arg)
8512 {
8513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8514         int ret = 0;
8515
8516         if (filter_op == RTE_ETH_FILTER_NOP)
8517                 return ret;
8518
8519         if (arg == NULL) {
8520                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8521                             filter_op);
8522                 return -EINVAL;
8523         }
8524
8525         switch (filter_op) {
8526         case RTE_ETH_FILTER_ADD:
8527                 ret = i40e_ethertype_filter_set(pf,
8528                         (struct rte_eth_ethertype_filter *)arg,
8529                         TRUE);
8530                 break;
8531         case RTE_ETH_FILTER_DELETE:
8532                 ret = i40e_ethertype_filter_set(pf,
8533                         (struct rte_eth_ethertype_filter *)arg,
8534                         FALSE);
8535                 break;
8536         default:
8537                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8538                 ret = -ENOSYS;
8539                 break;
8540         }
8541         return ret;
8542 }
8543
8544 static int
8545 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8546                      enum rte_filter_type filter_type,
8547                      enum rte_filter_op filter_op,
8548                      void *arg)
8549 {
8550         int ret = 0;
8551
8552         if (dev == NULL)
8553                 return -EINVAL;
8554
8555         switch (filter_type) {
8556         case RTE_ETH_FILTER_NONE:
8557                 /* For global configuration */
8558                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8559                 break;
8560         case RTE_ETH_FILTER_HASH:
8561                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8562                 break;
8563         case RTE_ETH_FILTER_MACVLAN:
8564                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8565                 break;
8566         case RTE_ETH_FILTER_ETHERTYPE:
8567                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8568                 break;
8569         case RTE_ETH_FILTER_TUNNEL:
8570                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8571                 break;
8572         case RTE_ETH_FILTER_FDIR:
8573                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8574                 break;
8575         case RTE_ETH_FILTER_GENERIC:
8576                 if (filter_op != RTE_ETH_FILTER_GET)
8577                         return -EINVAL;
8578                 *(const void **)arg = &i40e_flow_ops;
8579                 break;
8580         default:
8581                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8582                                                         filter_type);
8583                 ret = -EINVAL;
8584                 break;
8585         }
8586
8587         return ret;
8588 }
8589
8590 /*
8591  * Check and enable Extended Tag.
8592  * Enabling Extended Tag is important for 40G performance.
8593  */
8594 static void
8595 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8596 {
8597         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8598         uint32_t buf = 0;
8599         int ret;
8600
8601         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8602                                       PCI_DEV_CAP_REG);
8603         if (ret < 0) {
8604                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8605                             PCI_DEV_CAP_REG);
8606                 return;
8607         }
8608         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8609                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8610                 return;
8611         }
8612
8613         buf = 0;
8614         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8615                                       PCI_DEV_CTRL_REG);
8616         if (ret < 0) {
8617                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8618                             PCI_DEV_CTRL_REG);
8619                 return;
8620         }
8621         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8622                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8623                 return;
8624         }
8625         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8626         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8627                                        PCI_DEV_CTRL_REG);
8628         if (ret < 0) {
8629                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8630                             PCI_DEV_CTRL_REG);
8631                 return;
8632         }
8633 }
8634
8635 /*
8636  * As some registers wouldn't be reset unless a global hardware reset,
8637  * hardware initialization is needed to put those registers into an
8638  * expected initial state.
8639  */
8640 static void
8641 i40e_hw_init(struct rte_eth_dev *dev)
8642 {
8643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8644
8645         i40e_enable_extended_tag(dev);
8646
8647         /* clear the PF Queue Filter control register */
8648         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8649
8650         /* Disable symmetric hash per port */
8651         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8652 }
8653
8654 enum i40e_filter_pctype
8655 i40e_flowtype_to_pctype(uint16_t flow_type)
8656 {
8657         static const enum i40e_filter_pctype pctype_table[] = {
8658                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8659                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8660                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8661                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8662                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8663                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8664                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8665                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8666                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8667                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8668                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8669                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8670                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8671                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8672                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8673                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8674                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8675                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8676                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8677         };
8678
8679         return pctype_table[flow_type];
8680 }
8681
8682 uint16_t
8683 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8684 {
8685         static const uint16_t flowtype_table[] = {
8686                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8687                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8688                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8689                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8690                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8691                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8692                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8693                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8694                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8695                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8696                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8697                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8698                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8699                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8700                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8701                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8702                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8703                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8704                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8705                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8706                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8707                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8708                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8709                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8710                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8711                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8712                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8713                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8714                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8715                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8716                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8717         };
8718
8719         return flowtype_table[pctype];
8720 }
8721
8722 /*
8723  * On X710, performance number is far from the expectation on recent firmware
8724  * versions; on XL710, performance number is also far from the expectation on
8725  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8726  * mode is enabled and port MAC address is equal to the packet destination MAC
8727  * address. The fix for this issue may not be integrated in the following
8728  * firmware version. So the workaround in software driver is needed. It needs
8729  * to modify the initial values of 3 internal only registers for both X710 and
8730  * XL710. Note that the values for X710 or XL710 could be different, and the
8731  * workaround can be removed when it is fixed in firmware in the future.
8732  */
8733
8734 /* For both X710 and XL710 */
8735 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8736 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8737
8738 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8739 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8740
8741 /* For X710 */
8742 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8743 /* For XL710 */
8744 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8745 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8746
8747 static int
8748 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8749 {
8750         enum i40e_status_code status;
8751         struct i40e_aq_get_phy_abilities_resp phy_ab;
8752         int ret = -ENOTSUP;
8753
8754         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8755                                               NULL);
8756
8757         if (status)
8758                 return ret;
8759
8760         return 0;
8761 }
8762
8763
8764 static void
8765 i40e_configure_registers(struct i40e_hw *hw)
8766 {
8767         static struct {
8768                 uint32_t addr;
8769                 uint64_t val;
8770         } reg_table[] = {
8771                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8772                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8773                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8774         };
8775         uint64_t reg;
8776         uint32_t i;
8777         int ret;
8778
8779         for (i = 0; i < RTE_DIM(reg_table); i++) {
8780                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8781                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8782                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8783                                 reg_table[i].val =
8784                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8785                         else /* For X710 */
8786                                 reg_table[i].val =
8787                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8788                 }
8789
8790                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8791                                                         &reg, NULL);
8792                 if (ret < 0) {
8793                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8794                                                         reg_table[i].addr);
8795                         break;
8796                 }
8797                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8798                                                 reg_table[i].addr, reg);
8799                 if (reg == reg_table[i].val)
8800                         continue;
8801
8802                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8803                                                 reg_table[i].val, NULL);
8804                 if (ret < 0) {
8805                         PMD_DRV_LOG(ERR,
8806                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8807                                 reg_table[i].val, reg_table[i].addr);
8808                         break;
8809                 }
8810                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8811                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8812         }
8813 }
8814
8815 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8816 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8817 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8818 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8819 static int
8820 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8821 {
8822         uint32_t reg;
8823         int ret;
8824
8825         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8826                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8827                 return -EINVAL;
8828         }
8829
8830         /* Configure for double VLAN RX stripping */
8831         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8832         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8833                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8834                 ret = i40e_aq_debug_write_register(hw,
8835                                                    I40E_VSI_TSR(vsi->vsi_id),
8836                                                    reg, NULL);
8837                 if (ret < 0) {
8838                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8839                                     vsi->vsi_id);
8840                         return I40E_ERR_CONFIG;
8841                 }
8842         }
8843
8844         /* Configure for double VLAN TX insertion */
8845         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8846         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8847                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8848                 ret = i40e_aq_debug_write_register(hw,
8849                                                    I40E_VSI_L2TAGSTXVALID(
8850                                                    vsi->vsi_id), reg, NULL);
8851                 if (ret < 0) {
8852                         PMD_DRV_LOG(ERR,
8853                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8854                                 vsi->vsi_id);
8855                         return I40E_ERR_CONFIG;
8856                 }
8857         }
8858
8859         return 0;
8860 }
8861
8862 /**
8863  * i40e_aq_add_mirror_rule
8864  * @hw: pointer to the hardware structure
8865  * @seid: VEB seid to add mirror rule to
8866  * @dst_id: destination vsi seid
8867  * @entries: Buffer which contains the entities to be mirrored
8868  * @count: number of entities contained in the buffer
8869  * @rule_id:the rule_id of the rule to be added
8870  *
8871  * Add a mirror rule for a given veb.
8872  *
8873  **/
8874 static enum i40e_status_code
8875 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8876                         uint16_t seid, uint16_t dst_id,
8877                         uint16_t rule_type, uint16_t *entries,
8878                         uint16_t count, uint16_t *rule_id)
8879 {
8880         struct i40e_aq_desc desc;
8881         struct i40e_aqc_add_delete_mirror_rule cmd;
8882         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8883                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8884                 &desc.params.raw;
8885         uint16_t buff_len;
8886         enum i40e_status_code status;
8887
8888         i40e_fill_default_direct_cmd_desc(&desc,
8889                                           i40e_aqc_opc_add_mirror_rule);
8890         memset(&cmd, 0, sizeof(cmd));
8891
8892         buff_len = sizeof(uint16_t) * count;
8893         desc.datalen = rte_cpu_to_le_16(buff_len);
8894         if (buff_len > 0)
8895                 desc.flags |= rte_cpu_to_le_16(
8896                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8897         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8898                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8899         cmd.num_entries = rte_cpu_to_le_16(count);
8900         cmd.seid = rte_cpu_to_le_16(seid);
8901         cmd.destination = rte_cpu_to_le_16(dst_id);
8902
8903         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8904         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8905         PMD_DRV_LOG(INFO,
8906                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8907                 hw->aq.asq_last_status, resp->rule_id,
8908                 resp->mirror_rules_used, resp->mirror_rules_free);
8909         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8910
8911         return status;
8912 }
8913
8914 /**
8915  * i40e_aq_del_mirror_rule
8916  * @hw: pointer to the hardware structure
8917  * @seid: VEB seid to add mirror rule to
8918  * @entries: Buffer which contains the entities to be mirrored
8919  * @count: number of entities contained in the buffer
8920  * @rule_id:the rule_id of the rule to be delete
8921  *
8922  * Delete a mirror rule for a given veb.
8923  *
8924  **/
8925 static enum i40e_status_code
8926 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8927                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8928                 uint16_t count, uint16_t rule_id)
8929 {
8930         struct i40e_aq_desc desc;
8931         struct i40e_aqc_add_delete_mirror_rule cmd;
8932         uint16_t buff_len = 0;
8933         enum i40e_status_code status;
8934         void *buff = NULL;
8935
8936         i40e_fill_default_direct_cmd_desc(&desc,
8937                                           i40e_aqc_opc_delete_mirror_rule);
8938         memset(&cmd, 0, sizeof(cmd));
8939         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8940                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8941                                                           I40E_AQ_FLAG_RD));
8942                 cmd.num_entries = count;
8943                 buff_len = sizeof(uint16_t) * count;
8944                 desc.datalen = rte_cpu_to_le_16(buff_len);
8945                 buff = (void *)entries;
8946         } else
8947                 /* rule id is filled in destination field for deleting mirror rule */
8948                 cmd.destination = rte_cpu_to_le_16(rule_id);
8949
8950         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8951                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8952         cmd.seid = rte_cpu_to_le_16(seid);
8953
8954         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8955         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8956
8957         return status;
8958 }
8959
8960 /**
8961  * i40e_mirror_rule_set
8962  * @dev: pointer to the hardware structure
8963  * @mirror_conf: mirror rule info
8964  * @sw_id: mirror rule's sw_id
8965  * @on: enable/disable
8966  *
8967  * set a mirror rule.
8968  *
8969  **/
8970 static int
8971 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8972                         struct rte_eth_mirror_conf *mirror_conf,
8973                         uint8_t sw_id, uint8_t on)
8974 {
8975         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8976         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8977         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8978         struct i40e_mirror_rule *parent = NULL;
8979         uint16_t seid, dst_seid, rule_id;
8980         uint16_t i, j = 0;
8981         int ret;
8982
8983         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8984
8985         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8986                 PMD_DRV_LOG(ERR,
8987                         "mirror rule can not be configured without veb or vfs.");
8988                 return -ENOSYS;
8989         }
8990         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8991                 PMD_DRV_LOG(ERR, "mirror table is full.");
8992                 return -ENOSPC;
8993         }
8994         if (mirror_conf->dst_pool > pf->vf_num) {
8995                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8996                                  mirror_conf->dst_pool);
8997                 return -EINVAL;
8998         }
8999
9000         seid = pf->main_vsi->veb->seid;
9001
9002         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9003                 if (sw_id <= it->index) {
9004                         mirr_rule = it;
9005                         break;
9006                 }
9007                 parent = it;
9008         }
9009         if (mirr_rule && sw_id == mirr_rule->index) {
9010                 if (on) {
9011                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9012                         return -EEXIST;
9013                 } else {
9014                         ret = i40e_aq_del_mirror_rule(hw, seid,
9015                                         mirr_rule->rule_type,
9016                                         mirr_rule->entries,
9017                                         mirr_rule->num_entries, mirr_rule->id);
9018                         if (ret < 0) {
9019                                 PMD_DRV_LOG(ERR,
9020                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9021                                         ret, hw->aq.asq_last_status);
9022                                 return -ENOSYS;
9023                         }
9024                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9025                         rte_free(mirr_rule);
9026                         pf->nb_mirror_rule--;
9027                         return 0;
9028                 }
9029         } else if (!on) {
9030                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9031                 return -ENOENT;
9032         }
9033
9034         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9035                                 sizeof(struct i40e_mirror_rule) , 0);
9036         if (!mirr_rule) {
9037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9038                 return I40E_ERR_NO_MEMORY;
9039         }
9040         switch (mirror_conf->rule_type) {
9041         case ETH_MIRROR_VLAN:
9042                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9043                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9044                                 mirr_rule->entries[j] =
9045                                         mirror_conf->vlan.vlan_id[i];
9046                                 j++;
9047                         }
9048                 }
9049                 if (j == 0) {
9050                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9051                         rte_free(mirr_rule);
9052                         return -EINVAL;
9053                 }
9054                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9055                 break;
9056         case ETH_MIRROR_VIRTUAL_POOL_UP:
9057         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9058                 /* check if the specified pool bit is out of range */
9059                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9060                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9061                         rte_free(mirr_rule);
9062                         return -EINVAL;
9063                 }
9064                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9065                         if (mirror_conf->pool_mask & (1ULL << i)) {
9066                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9067                                 j++;
9068                         }
9069                 }
9070                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9071                         /* add pf vsi to entries */
9072                         mirr_rule->entries[j] = pf->main_vsi_seid;
9073                         j++;
9074                 }
9075                 if (j == 0) {
9076                         PMD_DRV_LOG(ERR, "pool is not specified.");
9077                         rte_free(mirr_rule);
9078                         return -EINVAL;
9079                 }
9080                 /* egress and ingress in aq commands means from switch but not port */
9081                 mirr_rule->rule_type =
9082                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9083                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9084                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9085                 break;
9086         case ETH_MIRROR_UPLINK_PORT:
9087                 /* egress and ingress in aq commands means from switch but not port*/
9088                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9089                 break;
9090         case ETH_MIRROR_DOWNLINK_PORT:
9091                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9092                 break;
9093         default:
9094                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9095                         mirror_conf->rule_type);
9096                 rte_free(mirr_rule);
9097                 return -EINVAL;
9098         }
9099
9100         /* If the dst_pool is equal to vf_num, consider it as PF */
9101         if (mirror_conf->dst_pool == pf->vf_num)
9102                 dst_seid = pf->main_vsi_seid;
9103         else
9104                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9105
9106         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9107                                       mirr_rule->rule_type, mirr_rule->entries,
9108                                       j, &rule_id);
9109         if (ret < 0) {
9110                 PMD_DRV_LOG(ERR,
9111                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9112                         ret, hw->aq.asq_last_status);
9113                 rte_free(mirr_rule);
9114                 return -ENOSYS;
9115         }
9116
9117         mirr_rule->index = sw_id;
9118         mirr_rule->num_entries = j;
9119         mirr_rule->id = rule_id;
9120         mirr_rule->dst_vsi_seid = dst_seid;
9121
9122         if (parent)
9123                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9124         else
9125                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9126
9127         pf->nb_mirror_rule++;
9128         return 0;
9129 }
9130
9131 /**
9132  * i40e_mirror_rule_reset
9133  * @dev: pointer to the device
9134  * @sw_id: mirror rule's sw_id
9135  *
9136  * reset a mirror rule.
9137  *
9138  **/
9139 static int
9140 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9141 {
9142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9144         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9145         uint16_t seid;
9146         int ret;
9147
9148         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9149
9150         seid = pf->main_vsi->veb->seid;
9151
9152         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9153                 if (sw_id == it->index) {
9154                         mirr_rule = it;
9155                         break;
9156                 }
9157         }
9158         if (mirr_rule) {
9159                 ret = i40e_aq_del_mirror_rule(hw, seid,
9160                                 mirr_rule->rule_type,
9161                                 mirr_rule->entries,
9162                                 mirr_rule->num_entries, mirr_rule->id);
9163                 if (ret < 0) {
9164                         PMD_DRV_LOG(ERR,
9165                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9166                                 ret, hw->aq.asq_last_status);
9167                         return -ENOSYS;
9168                 }
9169                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9170                 rte_free(mirr_rule);
9171                 pf->nb_mirror_rule--;
9172         } else {
9173                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9174                 return -ENOENT;
9175         }
9176         return 0;
9177 }
9178
9179 static uint64_t
9180 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9181 {
9182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9183         uint64_t systim_cycles;
9184
9185         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9186         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9187                         << 32;
9188
9189         return systim_cycles;
9190 }
9191
9192 static uint64_t
9193 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9194 {
9195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9196         uint64_t rx_tstamp;
9197
9198         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9199         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9200                         << 32;
9201
9202         return rx_tstamp;
9203 }
9204
9205 static uint64_t
9206 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9207 {
9208         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9209         uint64_t tx_tstamp;
9210
9211         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9212         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9213                         << 32;
9214
9215         return tx_tstamp;
9216 }
9217
9218 static void
9219 i40e_start_timecounters(struct rte_eth_dev *dev)
9220 {
9221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9222         struct i40e_adapter *adapter =
9223                         (struct i40e_adapter *)dev->data->dev_private;
9224         struct rte_eth_link link;
9225         uint32_t tsync_inc_l;
9226         uint32_t tsync_inc_h;
9227
9228         /* Get current link speed. */
9229         memset(&link, 0, sizeof(link));
9230         i40e_dev_link_update(dev, 1);
9231         rte_i40e_dev_atomic_read_link_status(dev, &link);
9232
9233         switch (link.link_speed) {
9234         case ETH_SPEED_NUM_40G:
9235                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9236                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9237                 break;
9238         case ETH_SPEED_NUM_10G:
9239                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9240                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9241                 break;
9242         case ETH_SPEED_NUM_1G:
9243                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9244                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9245                 break;
9246         default:
9247                 tsync_inc_l = 0x0;
9248                 tsync_inc_h = 0x0;
9249         }
9250
9251         /* Set the timesync increment value. */
9252         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9253         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9254
9255         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9256         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9257         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9258
9259         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9260         adapter->systime_tc.cc_shift = 0;
9261         adapter->systime_tc.nsec_mask = 0;
9262
9263         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9264         adapter->rx_tstamp_tc.cc_shift = 0;
9265         adapter->rx_tstamp_tc.nsec_mask = 0;
9266
9267         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9268         adapter->tx_tstamp_tc.cc_shift = 0;
9269         adapter->tx_tstamp_tc.nsec_mask = 0;
9270 }
9271
9272 static int
9273 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9274 {
9275         struct i40e_adapter *adapter =
9276                         (struct i40e_adapter *)dev->data->dev_private;
9277
9278         adapter->systime_tc.nsec += delta;
9279         adapter->rx_tstamp_tc.nsec += delta;
9280         adapter->tx_tstamp_tc.nsec += delta;
9281
9282         return 0;
9283 }
9284
9285 static int
9286 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9287 {
9288         uint64_t ns;
9289         struct i40e_adapter *adapter =
9290                         (struct i40e_adapter *)dev->data->dev_private;
9291
9292         ns = rte_timespec_to_ns(ts);
9293
9294         /* Set the timecounters to a new value. */
9295         adapter->systime_tc.nsec = ns;
9296         adapter->rx_tstamp_tc.nsec = ns;
9297         adapter->tx_tstamp_tc.nsec = ns;
9298
9299         return 0;
9300 }
9301
9302 static int
9303 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9304 {
9305         uint64_t ns, systime_cycles;
9306         struct i40e_adapter *adapter =
9307                         (struct i40e_adapter *)dev->data->dev_private;
9308
9309         systime_cycles = i40e_read_systime_cyclecounter(dev);
9310         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9311         *ts = rte_ns_to_timespec(ns);
9312
9313         return 0;
9314 }
9315
9316 static int
9317 i40e_timesync_enable(struct rte_eth_dev *dev)
9318 {
9319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9320         uint32_t tsync_ctl_l;
9321         uint32_t tsync_ctl_h;
9322
9323         /* Stop the timesync system time. */
9324         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9325         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9326         /* Reset the timesync system time value. */
9327         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9328         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9329
9330         i40e_start_timecounters(dev);
9331
9332         /* Clear timesync registers. */
9333         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9334         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9335         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9336         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9337         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9338         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9339
9340         /* Enable timestamping of PTP packets. */
9341         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9342         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9343
9344         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9345         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9346         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9347
9348         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9349         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9350
9351         return 0;
9352 }
9353
9354 static int
9355 i40e_timesync_disable(struct rte_eth_dev *dev)
9356 {
9357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9358         uint32_t tsync_ctl_l;
9359         uint32_t tsync_ctl_h;
9360
9361         /* Disable timestamping of transmitted PTP packets. */
9362         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9363         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9364
9365         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9366         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9367
9368         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9369         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9370
9371         /* Reset the timesync increment value. */
9372         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9373         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9374
9375         return 0;
9376 }
9377
9378 static int
9379 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9380                                 struct timespec *timestamp, uint32_t flags)
9381 {
9382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9383         struct i40e_adapter *adapter =
9384                 (struct i40e_adapter *)dev->data->dev_private;
9385
9386         uint32_t sync_status;
9387         uint32_t index = flags & 0x03;
9388         uint64_t rx_tstamp_cycles;
9389         uint64_t ns;
9390
9391         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9392         if ((sync_status & (1 << index)) == 0)
9393                 return -EINVAL;
9394
9395         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9396         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9397         *timestamp = rte_ns_to_timespec(ns);
9398
9399         return 0;
9400 }
9401
9402 static int
9403 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9404                                 struct timespec *timestamp)
9405 {
9406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9407         struct i40e_adapter *adapter =
9408                 (struct i40e_adapter *)dev->data->dev_private;
9409
9410         uint32_t sync_status;
9411         uint64_t tx_tstamp_cycles;
9412         uint64_t ns;
9413
9414         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9415         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9416                 return -EINVAL;
9417
9418         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9419         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9420         *timestamp = rte_ns_to_timespec(ns);
9421
9422         return 0;
9423 }
9424
9425 /*
9426  * i40e_parse_dcb_configure - parse dcb configure from user
9427  * @dev: the device being configured
9428  * @dcb_cfg: pointer of the result of parse
9429  * @*tc_map: bit map of enabled traffic classes
9430  *
9431  * Returns 0 on success, negative value on failure
9432  */
9433 static int
9434 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9435                          struct i40e_dcbx_config *dcb_cfg,
9436                          uint8_t *tc_map)
9437 {
9438         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9439         uint8_t i, tc_bw, bw_lf;
9440
9441         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9442
9443         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9444         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9445                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9446                 return -EINVAL;
9447         }
9448
9449         /* assume each tc has the same bw */
9450         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9451         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9452                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9453         /* to ensure the sum of tcbw is equal to 100 */
9454         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9455         for (i = 0; i < bw_lf; i++)
9456                 dcb_cfg->etscfg.tcbwtable[i]++;
9457
9458         /* assume each tc has the same Transmission Selection Algorithm */
9459         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9460                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9461
9462         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9463                 dcb_cfg->etscfg.prioritytable[i] =
9464                                 dcb_rx_conf->dcb_tc[i];
9465
9466         /* FW needs one App to configure HW */
9467         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9468         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9469         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9470         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9471
9472         if (dcb_rx_conf->nb_tcs == 0)
9473                 *tc_map = 1; /* tc0 only */
9474         else
9475                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9476
9477         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9478                 dcb_cfg->pfc.willing = 0;
9479                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9480                 dcb_cfg->pfc.pfcenable = *tc_map;
9481         }
9482         return 0;
9483 }
9484
9485
9486 static enum i40e_status_code
9487 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9488                               struct i40e_aqc_vsi_properties_data *info,
9489                               uint8_t enabled_tcmap)
9490 {
9491         enum i40e_status_code ret;
9492         int i, total_tc = 0;
9493         uint16_t qpnum_per_tc, bsf, qp_idx;
9494         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9495         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9496         uint16_t used_queues;
9497
9498         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9499         if (ret != I40E_SUCCESS)
9500                 return ret;
9501
9502         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9503                 if (enabled_tcmap & (1 << i))
9504                         total_tc++;
9505         }
9506         if (total_tc == 0)
9507                 total_tc = 1;
9508         vsi->enabled_tc = enabled_tcmap;
9509
9510         /* different VSI has different queues assigned */
9511         if (vsi->type == I40E_VSI_MAIN)
9512                 used_queues = dev_data->nb_rx_queues -
9513                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9514         else if (vsi->type == I40E_VSI_VMDQ2)
9515                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9516         else {
9517                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9518                 return I40E_ERR_NO_AVAILABLE_VSI;
9519         }
9520
9521         qpnum_per_tc = used_queues / total_tc;
9522         /* Number of queues per enabled TC */
9523         if (qpnum_per_tc == 0) {
9524                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9525                 return I40E_ERR_INVALID_QP_ID;
9526         }
9527         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9528                                 I40E_MAX_Q_PER_TC);
9529         bsf = rte_bsf32(qpnum_per_tc);
9530
9531         /**
9532          * Configure TC and queue mapping parameters, for enabled TC,
9533          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9534          * default queue will serve it.
9535          */
9536         qp_idx = 0;
9537         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9538                 if (vsi->enabled_tc & (1 << i)) {
9539                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9540                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9541                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9542                         qp_idx += qpnum_per_tc;
9543                 } else
9544                         info->tc_mapping[i] = 0;
9545         }
9546
9547         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9548         if (vsi->type == I40E_VSI_SRIOV) {
9549                 info->mapping_flags |=
9550                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9551                 for (i = 0; i < vsi->nb_qps; i++)
9552                         info->queue_mapping[i] =
9553                                 rte_cpu_to_le_16(vsi->base_queue + i);
9554         } else {
9555                 info->mapping_flags |=
9556                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9557                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9558         }
9559         info->valid_sections |=
9560                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9561
9562         return I40E_SUCCESS;
9563 }
9564
9565 /*
9566  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9567  * @veb: VEB to be configured
9568  * @tc_map: enabled TC bitmap
9569  *
9570  * Returns 0 on success, negative value on failure
9571  */
9572 static enum i40e_status_code
9573 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9574 {
9575         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9576         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9577         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9578         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9579         enum i40e_status_code ret = I40E_SUCCESS;
9580         int i;
9581         uint32_t bw_max;
9582
9583         /* Check if enabled_tc is same as existing or new TCs */
9584         if (veb->enabled_tc == tc_map)
9585                 return ret;
9586
9587         /* configure tc bandwidth */
9588         memset(&veb_bw, 0, sizeof(veb_bw));
9589         veb_bw.tc_valid_bits = tc_map;
9590         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9592                 if (tc_map & BIT_ULL(i))
9593                         veb_bw.tc_bw_share_credits[i] = 1;
9594         }
9595         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9596                                                    &veb_bw, NULL);
9597         if (ret) {
9598                 PMD_INIT_LOG(ERR,
9599                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9600                         hw->aq.asq_last_status);
9601                 return ret;
9602         }
9603
9604         memset(&ets_query, 0, sizeof(ets_query));
9605         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9606                                                    &ets_query, NULL);
9607         if (ret != I40E_SUCCESS) {
9608                 PMD_DRV_LOG(ERR,
9609                         "Failed to get switch_comp ETS configuration %u",
9610                         hw->aq.asq_last_status);
9611                 return ret;
9612         }
9613         memset(&bw_query, 0, sizeof(bw_query));
9614         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9615                                                   &bw_query, NULL);
9616         if (ret != I40E_SUCCESS) {
9617                 PMD_DRV_LOG(ERR,
9618                         "Failed to get switch_comp bandwidth configuration %u",
9619                         hw->aq.asq_last_status);
9620                 return ret;
9621         }
9622
9623         /* store and print out BW info */
9624         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9625         veb->bw_info.bw_max = ets_query.tc_bw_max;
9626         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9627         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9628         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9629                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9630                      I40E_16_BIT_WIDTH);
9631         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9632                 veb->bw_info.bw_ets_share_credits[i] =
9633                                 bw_query.tc_bw_share_credits[i];
9634                 veb->bw_info.bw_ets_credits[i] =
9635                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9636                 /* 4 bits per TC, 4th bit is reserved */
9637                 veb->bw_info.bw_ets_max[i] =
9638                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9639                                   RTE_LEN2MASK(3, uint8_t));
9640                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9641                             veb->bw_info.bw_ets_share_credits[i]);
9642                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9643                             veb->bw_info.bw_ets_credits[i]);
9644                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9645                             veb->bw_info.bw_ets_max[i]);
9646         }
9647
9648         veb->enabled_tc = tc_map;
9649
9650         return ret;
9651 }
9652
9653
9654 /*
9655  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9656  * @vsi: VSI to be configured
9657  * @tc_map: enabled TC bitmap
9658  *
9659  * Returns 0 on success, negative value on failure
9660  */
9661 static enum i40e_status_code
9662 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9663 {
9664         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9665         struct i40e_vsi_context ctxt;
9666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9667         enum i40e_status_code ret = I40E_SUCCESS;
9668         int i;
9669
9670         /* Check if enabled_tc is same as existing or new TCs */
9671         if (vsi->enabled_tc == tc_map)
9672                 return ret;
9673
9674         /* configure tc bandwidth */
9675         memset(&bw_data, 0, sizeof(bw_data));
9676         bw_data.tc_valid_bits = tc_map;
9677         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9678         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9679                 if (tc_map & BIT_ULL(i))
9680                         bw_data.tc_bw_credits[i] = 1;
9681         }
9682         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9683         if (ret) {
9684                 PMD_INIT_LOG(ERR,
9685                         "AQ command Config VSI BW allocation per TC failed = %d",
9686                         hw->aq.asq_last_status);
9687                 goto out;
9688         }
9689         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9690                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9691
9692         /* Update Queue Pairs Mapping for currently enabled UPs */
9693         ctxt.seid = vsi->seid;
9694         ctxt.pf_num = hw->pf_id;
9695         ctxt.vf_num = 0;
9696         ctxt.uplink_seid = vsi->uplink_seid;
9697         ctxt.info = vsi->info;
9698         i40e_get_cap(hw);
9699         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9700         if (ret)
9701                 goto out;
9702
9703         /* Update the VSI after updating the VSI queue-mapping information */
9704         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9705         if (ret) {
9706                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9707                         hw->aq.asq_last_status);
9708                 goto out;
9709         }
9710         /* update the local VSI info with updated queue map */
9711         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9712                                         sizeof(vsi->info.tc_mapping));
9713         (void)rte_memcpy(&vsi->info.queue_mapping,
9714                         &ctxt.info.queue_mapping,
9715                 sizeof(vsi->info.queue_mapping));
9716         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9717         vsi->info.valid_sections = 0;
9718
9719         /* query and update current VSI BW information */
9720         ret = i40e_vsi_get_bw_config(vsi);
9721         if (ret) {
9722                 PMD_INIT_LOG(ERR,
9723                          "Failed updating vsi bw info, err %s aq_err %s",
9724                          i40e_stat_str(hw, ret),
9725                          i40e_aq_str(hw, hw->aq.asq_last_status));
9726                 goto out;
9727         }
9728
9729         vsi->enabled_tc = tc_map;
9730
9731 out:
9732         return ret;
9733 }
9734
9735 /*
9736  * i40e_dcb_hw_configure - program the dcb setting to hw
9737  * @pf: pf the configuration is taken on
9738  * @new_cfg: new configuration
9739  * @tc_map: enabled TC bitmap
9740  *
9741  * Returns 0 on success, negative value on failure
9742  */
9743 static enum i40e_status_code
9744 i40e_dcb_hw_configure(struct i40e_pf *pf,
9745                       struct i40e_dcbx_config *new_cfg,
9746                       uint8_t tc_map)
9747 {
9748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9749         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9750         struct i40e_vsi *main_vsi = pf->main_vsi;
9751         struct i40e_vsi_list *vsi_list;
9752         enum i40e_status_code ret;
9753         int i;
9754         uint32_t val;
9755
9756         /* Use the FW API if FW > v4.4*/
9757         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9758               (hw->aq.fw_maj_ver >= 5))) {
9759                 PMD_INIT_LOG(ERR,
9760                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9761                 return I40E_ERR_FIRMWARE_API_VERSION;
9762         }
9763
9764         /* Check if need reconfiguration */
9765         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9766                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9767                 return I40E_SUCCESS;
9768         }
9769
9770         /* Copy the new config to the current config */
9771         *old_cfg = *new_cfg;
9772         old_cfg->etsrec = old_cfg->etscfg;
9773         ret = i40e_set_dcb_config(hw);
9774         if (ret) {
9775                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9776                          i40e_stat_str(hw, ret),
9777                          i40e_aq_str(hw, hw->aq.asq_last_status));
9778                 return ret;
9779         }
9780         /* set receive Arbiter to RR mode and ETS scheme by default */
9781         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9782                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9783                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9784                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9785                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9786                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9787                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9788                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9789                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9790                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9791                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9792                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9793                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9794         }
9795         /* get local mib to check whether it is configured correctly */
9796         /* IEEE mode */
9797         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9798         /* Get Local DCB Config */
9799         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9800                                      &hw->local_dcbx_config);
9801
9802         /* if Veb is created, need to update TC of it at first */
9803         if (main_vsi->veb) {
9804                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9805                 if (ret)
9806                         PMD_INIT_LOG(WARNING,
9807                                  "Failed configuring TC for VEB seid=%d",
9808                                  main_vsi->veb->seid);
9809         }
9810         /* Update each VSI */
9811         i40e_vsi_config_tc(main_vsi, tc_map);
9812         if (main_vsi->veb) {
9813                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9814                         /* Beside main VSI and VMDQ VSIs, only enable default
9815                          * TC for other VSIs
9816                          */
9817                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9818                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9819                                                          tc_map);
9820                         else
9821                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9822                                                          I40E_DEFAULT_TCMAP);
9823                         if (ret)
9824                                 PMD_INIT_LOG(WARNING,
9825                                         "Failed configuring TC for VSI seid=%d",
9826                                         vsi_list->vsi->seid);
9827                         /* continue */
9828                 }
9829         }
9830         return I40E_SUCCESS;
9831 }
9832
9833 /*
9834  * i40e_dcb_init_configure - initial dcb config
9835  * @dev: device being configured
9836  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9837  *
9838  * Returns 0 on success, negative value on failure
9839  */
9840 static int
9841 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9842 {
9843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9845         int ret = 0;
9846
9847         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9848                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9849                 return -ENOTSUP;
9850         }
9851
9852         /* DCB initialization:
9853          * Update DCB configuration from the Firmware and configure
9854          * LLDP MIB change event.
9855          */
9856         if (sw_dcb == TRUE) {
9857                 ret = i40e_init_dcb(hw);
9858                 /* If lldp agent is stopped, the return value from
9859                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9860                  * adminq status. Otherwise, it should return success.
9861                  */
9862                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9863                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9864                         memset(&hw->local_dcbx_config, 0,
9865                                 sizeof(struct i40e_dcbx_config));
9866                         /* set dcb default configuration */
9867                         hw->local_dcbx_config.etscfg.willing = 0;
9868                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9869                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9870                         hw->local_dcbx_config.etscfg.tsatable[0] =
9871                                                 I40E_IEEE_TSA_ETS;
9872                         hw->local_dcbx_config.etsrec =
9873                                 hw->local_dcbx_config.etscfg;
9874                         hw->local_dcbx_config.pfc.willing = 0;
9875                         hw->local_dcbx_config.pfc.pfccap =
9876                                                 I40E_MAX_TRAFFIC_CLASS;
9877                         /* FW needs one App to configure HW */
9878                         hw->local_dcbx_config.numapps = 1;
9879                         hw->local_dcbx_config.app[0].selector =
9880                                                 I40E_APP_SEL_ETHTYPE;
9881                         hw->local_dcbx_config.app[0].priority = 3;
9882                         hw->local_dcbx_config.app[0].protocolid =
9883                                                 I40E_APP_PROTOID_FCOE;
9884                         ret = i40e_set_dcb_config(hw);
9885                         if (ret) {
9886                                 PMD_INIT_LOG(ERR,
9887                                         "default dcb config fails. err = %d, aq_err = %d.",
9888                                         ret, hw->aq.asq_last_status);
9889                                 return -ENOSYS;
9890                         }
9891                 } else {
9892                         PMD_INIT_LOG(ERR,
9893                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9894                                 ret, hw->aq.asq_last_status);
9895                         return -ENOTSUP;
9896                 }
9897         } else {
9898                 ret = i40e_aq_start_lldp(hw, NULL);
9899                 if (ret != I40E_SUCCESS)
9900                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9901
9902                 ret = i40e_init_dcb(hw);
9903                 if (!ret) {
9904                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9905                                 PMD_INIT_LOG(ERR,
9906                                         "HW doesn't support DCBX offload.");
9907                                 return -ENOTSUP;
9908                         }
9909                 } else {
9910                         PMD_INIT_LOG(ERR,
9911                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9912                                 ret, hw->aq.asq_last_status);
9913                         return -ENOTSUP;
9914                 }
9915         }
9916         return 0;
9917 }
9918
9919 /*
9920  * i40e_dcb_setup - setup dcb related config
9921  * @dev: device being configured
9922  *
9923  * Returns 0 on success, negative value on failure
9924  */
9925 static int
9926 i40e_dcb_setup(struct rte_eth_dev *dev)
9927 {
9928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9929         struct i40e_dcbx_config dcb_cfg;
9930         uint8_t tc_map = 0;
9931         int ret = 0;
9932
9933         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9934                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9935                 return -ENOTSUP;
9936         }
9937
9938         if (pf->vf_num != 0)
9939                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9940
9941         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9942         if (ret) {
9943                 PMD_INIT_LOG(ERR, "invalid dcb config");
9944                 return -EINVAL;
9945         }
9946         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9947         if (ret) {
9948                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9949                 return -ENOSYS;
9950         }
9951
9952         return 0;
9953 }
9954
9955 static int
9956 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9957                       struct rte_eth_dcb_info *dcb_info)
9958 {
9959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9961         struct i40e_vsi *vsi = pf->main_vsi;
9962         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9963         uint16_t bsf, tc_mapping;
9964         int i, j = 0;
9965
9966         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9967                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9968         else
9969                 dcb_info->nb_tcs = 1;
9970         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9971                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9972         for (i = 0; i < dcb_info->nb_tcs; i++)
9973                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9974
9975         /* get queue mapping if vmdq is disabled */
9976         if (!pf->nb_cfg_vmdq_vsi) {
9977                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9978                         if (!(vsi->enabled_tc & (1 << i)))
9979                                 continue;
9980                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9981                         dcb_info->tc_queue.tc_rxq[j][i].base =
9982                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9983                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9984                         dcb_info->tc_queue.tc_txq[j][i].base =
9985                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9986                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9987                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9988                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9989                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9990                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9991                 }
9992                 return 0;
9993         }
9994
9995         /* get queue mapping if vmdq is enabled */
9996         do {
9997                 vsi = pf->vmdq[j].vsi;
9998                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9999                         if (!(vsi->enabled_tc & (1 << i)))
10000                                 continue;
10001                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10002                         dcb_info->tc_queue.tc_rxq[j][i].base =
10003                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10004                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10005                         dcb_info->tc_queue.tc_txq[j][i].base =
10006                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10007                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10008                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10009                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10010                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10011                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10012                 }
10013                 j++;
10014         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10015         return 0;
10016 }
10017
10018 static int
10019 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10020 {
10021         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10022         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10024         uint16_t interval =
10025                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10026         uint16_t msix_intr;
10027
10028         msix_intr = intr_handle->intr_vec[queue_id];
10029         if (msix_intr == I40E_MISC_VEC_ID)
10030                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10031                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10032                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10033                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10034                                (interval <<
10035                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10036         else
10037                 I40E_WRITE_REG(hw,
10038                                I40E_PFINT_DYN_CTLN(msix_intr -
10039                                                    I40E_RX_VEC_START),
10040                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10041                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10042                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10043                                (interval <<
10044                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10045
10046         I40E_WRITE_FLUSH(hw);
10047         rte_intr_enable(&pci_dev->intr_handle);
10048
10049         return 0;
10050 }
10051
10052 static int
10053 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10054 {
10055         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10057         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10058         uint16_t msix_intr;
10059
10060         msix_intr = intr_handle->intr_vec[queue_id];
10061         if (msix_intr == I40E_MISC_VEC_ID)
10062                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10063         else
10064                 I40E_WRITE_REG(hw,
10065                                I40E_PFINT_DYN_CTLN(msix_intr -
10066                                                    I40E_RX_VEC_START),
10067                                0);
10068         I40E_WRITE_FLUSH(hw);
10069
10070         return 0;
10071 }
10072
10073 static int i40e_get_regs(struct rte_eth_dev *dev,
10074                          struct rte_dev_reg_info *regs)
10075 {
10076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10077         uint32_t *ptr_data = regs->data;
10078         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10079         const struct i40e_reg_info *reg_info;
10080
10081         if (ptr_data == NULL) {
10082                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10083                 regs->width = sizeof(uint32_t);
10084                 return 0;
10085         }
10086
10087         /* The first few registers have to be read using AQ operations */
10088         reg_idx = 0;
10089         while (i40e_regs_adminq[reg_idx].name) {
10090                 reg_info = &i40e_regs_adminq[reg_idx++];
10091                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10092                         for (arr_idx2 = 0;
10093                                         arr_idx2 <= reg_info->count2;
10094                                         arr_idx2++) {
10095                                 reg_offset = arr_idx * reg_info->stride1 +
10096                                         arr_idx2 * reg_info->stride2;
10097                                 reg_offset += reg_info->base_addr;
10098                                 ptr_data[reg_offset >> 2] =
10099                                         i40e_read_rx_ctl(hw, reg_offset);
10100                         }
10101         }
10102
10103         /* The remaining registers can be read using primitives */
10104         reg_idx = 0;
10105         while (i40e_regs_others[reg_idx].name) {
10106                 reg_info = &i40e_regs_others[reg_idx++];
10107                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10108                         for (arr_idx2 = 0;
10109                                         arr_idx2 <= reg_info->count2;
10110                                         arr_idx2++) {
10111                                 reg_offset = arr_idx * reg_info->stride1 +
10112                                         arr_idx2 * reg_info->stride2;
10113                                 reg_offset += reg_info->base_addr;
10114                                 ptr_data[reg_offset >> 2] =
10115                                         I40E_READ_REG(hw, reg_offset);
10116                         }
10117         }
10118
10119         return 0;
10120 }
10121
10122 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10123 {
10124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10125
10126         /* Convert word count to byte count */
10127         return hw->nvm.sr_size << 1;
10128 }
10129
10130 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10131                            struct rte_dev_eeprom_info *eeprom)
10132 {
10133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10134         uint16_t *data = eeprom->data;
10135         uint16_t offset, length, cnt_words;
10136         int ret_code;
10137
10138         offset = eeprom->offset >> 1;
10139         length = eeprom->length >> 1;
10140         cnt_words = length;
10141
10142         if (offset > hw->nvm.sr_size ||
10143                 offset + length > hw->nvm.sr_size) {
10144                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10145                 return -EINVAL;
10146         }
10147
10148         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10149
10150         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10151         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10152                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10153                 return -EIO;
10154         }
10155
10156         return 0;
10157 }
10158
10159 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10160                                       struct ether_addr *mac_addr)
10161 {
10162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10163
10164         if (!is_valid_assigned_ether_addr(mac_addr)) {
10165                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10166                 return;
10167         }
10168
10169         /* Flags: 0x3 updates port address */
10170         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10171 }
10172
10173 static int
10174 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10175 {
10176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10177         struct rte_eth_dev_data *dev_data = pf->dev_data;
10178         uint32_t frame_size = mtu + ETHER_HDR_LEN
10179                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10180         int ret = 0;
10181
10182         /* check if mtu is within the allowed range */
10183         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10184                 return -EINVAL;
10185
10186         /* mtu setting is forbidden if port is start */
10187         if (dev_data->dev_started) {
10188                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10189                             dev_data->port_id);
10190                 return -EBUSY;
10191         }
10192
10193         if (frame_size > ETHER_MAX_LEN)
10194                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10195         else
10196                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10197
10198         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10199
10200         return ret;
10201 }
10202
10203 /* Restore ethertype filter */
10204 static void
10205 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10206 {
10207         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10208         struct i40e_ethertype_filter_list
10209                 *ethertype_list = &pf->ethertype.ethertype_list;
10210         struct i40e_ethertype_filter *f;
10211         struct i40e_control_filter_stats stats;
10212         uint16_t flags;
10213
10214         TAILQ_FOREACH(f, ethertype_list, rules) {
10215                 flags = 0;
10216                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10217                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10218                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10219                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10220                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10221
10222                 memset(&stats, 0, sizeof(stats));
10223                 i40e_aq_add_rem_control_packet_filter(hw,
10224                                             f->input.mac_addr.addr_bytes,
10225                                             f->input.ether_type,
10226                                             flags, pf->main_vsi->seid,
10227                                             f->queue, 1, &stats, NULL);
10228         }
10229         PMD_DRV_LOG(INFO, "Ethertype filter:"
10230                     " mac_etype_used = %u, etype_used = %u,"
10231                     " mac_etype_free = %u, etype_free = %u",
10232                     stats.mac_etype_used, stats.etype_used,
10233                     stats.mac_etype_free, stats.etype_free);
10234 }
10235
10236 /* Restore tunnel filter */
10237 static void
10238 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10239 {
10240         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10241         struct i40e_vsi *vsi = pf->main_vsi;
10242         struct i40e_tunnel_filter_list
10243                 *tunnel_list = &pf->tunnel.tunnel_list;
10244         struct i40e_tunnel_filter *f;
10245         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10246
10247         TAILQ_FOREACH(f, tunnel_list, rules) {
10248                 memset(&cld_filter, 0, sizeof(cld_filter));
10249                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10250                 cld_filter.queue_number = f->queue;
10251                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10252         }
10253 }
10254
10255 static void
10256 i40e_filter_restore(struct i40e_pf *pf)
10257 {
10258         i40e_ethertype_filter_restore(pf);
10259         i40e_tunnel_filter_restore(pf);
10260         i40e_fdir_filter_restore(pf);
10261 }
10262
10263 static int
10264 is_i40e_pmd(const char *driver_name)
10265 {
10266         if (!strstr(driver_name, "i40e"))
10267                 return -ENOTSUP;
10268
10269         if (strstr(driver_name, "i40e_vf"))
10270                 return -ENOTSUP;
10271
10272         return 0;
10273 }
10274
10275 int
10276 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10277 {
10278         struct rte_eth_dev *dev;
10279         struct i40e_pf *pf;
10280
10281         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10282
10283         dev = &rte_eth_devices[port];
10284
10285         if (is_i40e_pmd(dev->data->drv_name))
10286                 return -ENOTSUP;
10287
10288         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10289
10290         if (vf >= pf->vf_num || !pf->vfs) {
10291                 PMD_DRV_LOG(ERR, "Invalid argument.");
10292                 return -EINVAL;
10293         }
10294
10295         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10296
10297         return 0;
10298 }
10299
10300 int
10301 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10302 {
10303         struct rte_eth_dev *dev;
10304         struct i40e_pf *pf;
10305         struct i40e_vsi *vsi;
10306         struct i40e_hw *hw;
10307         struct i40e_vsi_context ctxt;
10308         int ret;
10309
10310         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10311
10312         dev = &rte_eth_devices[port];
10313
10314         if (is_i40e_pmd(dev->data->drv_name))
10315                 return -ENOTSUP;
10316
10317         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10318
10319         if (vf_id >= pf->vf_num || !pf->vfs) {
10320                 PMD_DRV_LOG(ERR, "Invalid argument.");
10321                 return -EINVAL;
10322         }
10323
10324         vsi = pf->vfs[vf_id].vsi;
10325         if (!vsi) {
10326                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10327                 return -EINVAL;
10328         }
10329
10330         /* Check if it has been already on or off */
10331         if (vsi->info.valid_sections &
10332                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10333                 if (on) {
10334                         if ((vsi->info.sec_flags &
10335                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10336                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10337                                 return 0; /* already on */
10338                 } else {
10339                         if ((vsi->info.sec_flags &
10340                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10341                                 return 0; /* already off */
10342                 }
10343         }
10344
10345         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10346         if (on)
10347                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10348         else
10349                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10350
10351         memset(&ctxt, 0, sizeof(ctxt));
10352         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10353         ctxt.seid = vsi->seid;
10354
10355         hw = I40E_VSI_TO_HW(vsi);
10356         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10357         if (ret != I40E_SUCCESS) {
10358                 ret = -ENOTSUP;
10359                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10360         }
10361
10362         return ret;
10363 }
10364
10365 static int
10366 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10367 {
10368         uint32_t j, k;
10369         uint16_t vlan_id;
10370         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10371         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10372         int ret;
10373
10374         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10375                 if (!vsi->vfta[j])
10376                         continue;
10377
10378                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10379                         if (!(vsi->vfta[j] & (1 << k)))
10380                                 continue;
10381
10382                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10383                         if (!vlan_id)
10384                                 continue;
10385
10386                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10387                         if (add)
10388                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10389                                                        &vlan_data, 1, NULL);
10390                         else
10391                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10392                                                           &vlan_data, 1, NULL);
10393                         if (ret != I40E_SUCCESS) {
10394                                 PMD_DRV_LOG(ERR,
10395                                             "Failed to add/rm vlan filter");
10396                                 return ret;
10397                         }
10398                 }
10399         }
10400
10401         return I40E_SUCCESS;
10402 }
10403
10404 int
10405 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10406 {
10407         struct rte_eth_dev *dev;
10408         struct i40e_pf *pf;
10409         struct i40e_vsi *vsi;
10410         struct i40e_hw *hw;
10411         struct i40e_vsi_context ctxt;
10412         int ret;
10413
10414         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10415
10416         dev = &rte_eth_devices[port];
10417
10418         if (is_i40e_pmd(dev->data->drv_name))
10419                 return -ENOTSUP;
10420
10421         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10422
10423         if (vf_id >= pf->vf_num || !pf->vfs) {
10424                 PMD_DRV_LOG(ERR, "Invalid argument.");
10425                 return -EINVAL;
10426         }
10427
10428         vsi = pf->vfs[vf_id].vsi;
10429         if (!vsi) {
10430                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10431                 return -EINVAL;
10432         }
10433
10434         /* Check if it has been already on or off */
10435         if (vsi->vlan_anti_spoof_on == on)
10436                 return 0; /* already on or off */
10437
10438         vsi->vlan_anti_spoof_on = on;
10439         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10440         if (ret) {
10441                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10442                 return -ENOTSUP;
10443         }
10444
10445         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10446         if (on)
10447                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10448         else
10449                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10450
10451         memset(&ctxt, 0, sizeof(ctxt));
10452         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10453         ctxt.seid = vsi->seid;
10454
10455         hw = I40E_VSI_TO_HW(vsi);
10456         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10457         if (ret != I40E_SUCCESS) {
10458                 ret = -ENOTSUP;
10459                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10460         }
10461
10462         return ret;
10463 }
10464
10465 static int
10466 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10467 {
10468         struct i40e_mac_filter *f;
10469         struct i40e_macvlan_filter *mv_f;
10470         int i, vlan_num;
10471         enum rte_mac_filter_type filter_type;
10472         int ret = I40E_SUCCESS;
10473         void *temp;
10474
10475         /* remove all the MACs */
10476         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10477                 vlan_num = vsi->vlan_num;
10478                 filter_type = f->mac_info.filter_type;
10479                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10480                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10481                         if (vlan_num == 0) {
10482                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10483                                 return I40E_ERR_PARAM;
10484                         }
10485                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10486                            filter_type == RTE_MAC_HASH_MATCH)
10487                         vlan_num = 1;
10488
10489                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10490                 if (!mv_f) {
10491                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10492                         return I40E_ERR_NO_MEMORY;
10493                 }
10494
10495                 for (i = 0; i < vlan_num; i++) {
10496                         mv_f[i].filter_type = filter_type;
10497                         (void)rte_memcpy(&mv_f[i].macaddr,
10498                                          &f->mac_info.mac_addr,
10499                                          ETH_ADDR_LEN);
10500                 }
10501                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10502                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10503                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10504                                                          &f->mac_info.mac_addr);
10505                         if (ret != I40E_SUCCESS) {
10506                                 rte_free(mv_f);
10507                                 return ret;
10508                         }
10509                 }
10510
10511                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10512                 if (ret != I40E_SUCCESS) {
10513                         rte_free(mv_f);
10514                         return ret;
10515                 }
10516
10517                 rte_free(mv_f);
10518                 ret = I40E_SUCCESS;
10519         }
10520
10521         return ret;
10522 }
10523
10524 static int
10525 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10526 {
10527         struct i40e_mac_filter *f;
10528         struct i40e_macvlan_filter *mv_f;
10529         int i, vlan_num = 0;
10530         int ret = I40E_SUCCESS;
10531         void *temp;
10532
10533         /* restore all the MACs */
10534         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10535                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10536                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10537                         /**
10538                          * If vlan_num is 0, that's the first time to add mac,
10539                          * set mask for vlan_id 0.
10540                          */
10541                         if (vsi->vlan_num == 0) {
10542                                 i40e_set_vlan_filter(vsi, 0, 1);
10543                                 vsi->vlan_num = 1;
10544                         }
10545                         vlan_num = vsi->vlan_num;
10546                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10547                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10548                         vlan_num = 1;
10549
10550                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10551                 if (!mv_f) {
10552                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10553                         return I40E_ERR_NO_MEMORY;
10554                 }
10555
10556                 for (i = 0; i < vlan_num; i++) {
10557                         mv_f[i].filter_type = f->mac_info.filter_type;
10558                         (void)rte_memcpy(&mv_f[i].macaddr,
10559                                          &f->mac_info.mac_addr,
10560                                          ETH_ADDR_LEN);
10561                 }
10562
10563                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10564                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10565                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10566                                                          &f->mac_info.mac_addr);
10567                         if (ret != I40E_SUCCESS) {
10568                                 rte_free(mv_f);
10569                                 return ret;
10570                         }
10571                 }
10572
10573                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10574                 if (ret != I40E_SUCCESS) {
10575                         rte_free(mv_f);
10576                         return ret;
10577                 }
10578
10579                 rte_free(mv_f);
10580                 ret = I40E_SUCCESS;
10581         }
10582
10583         return ret;
10584 }
10585
10586 static int
10587 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10588 {
10589         struct i40e_vsi_context ctxt;
10590         struct i40e_hw *hw;
10591         int ret;
10592
10593         if (!vsi)
10594                 return -EINVAL;
10595
10596         hw = I40E_VSI_TO_HW(vsi);
10597
10598         /* Use the FW API if FW >= v5.0 */
10599         if (hw->aq.fw_maj_ver < 5) {
10600                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10601                 return -ENOTSUP;
10602         }
10603
10604         /* Check if it has been already on or off */
10605         if (vsi->info.valid_sections &
10606                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10607                 if (on) {
10608                         if ((vsi->info.switch_id &
10609                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10610                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10611                                 return 0; /* already on */
10612                 } else {
10613                         if ((vsi->info.switch_id &
10614                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10615                                 return 0; /* already off */
10616                 }
10617         }
10618
10619         /* remove all the MAC and VLAN first */
10620         ret = i40e_vsi_rm_mac_filter(vsi);
10621         if (ret) {
10622                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10623                 return ret;
10624         }
10625         if (vsi->vlan_anti_spoof_on) {
10626                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10627                 if (ret) {
10628                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10629                         return ret;
10630                 }
10631         }
10632
10633         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10634         if (on)
10635                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10636         else
10637                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10638
10639         memset(&ctxt, 0, sizeof(ctxt));
10640         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10641         ctxt.seid = vsi->seid;
10642
10643         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10644         if (ret != I40E_SUCCESS) {
10645                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10646                 return ret;
10647         }
10648
10649         /* add all the MAC and VLAN back */
10650         ret = i40e_vsi_restore_mac_filter(vsi);
10651         if (ret)
10652                 return ret;
10653         if (vsi->vlan_anti_spoof_on) {
10654                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10655                 if (ret)
10656                         return ret;
10657         }
10658
10659         return ret;
10660 }
10661
10662 int
10663 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10664 {
10665         struct rte_eth_dev *dev;
10666         struct i40e_pf *pf;
10667         struct i40e_pf_vf *vf;
10668         struct i40e_vsi *vsi;
10669         uint16_t vf_id;
10670         int ret;
10671
10672         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10673
10674         dev = &rte_eth_devices[port];
10675
10676         if (is_i40e_pmd(dev->data->drv_name))
10677                 return -ENOTSUP;
10678
10679         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10680
10681         /* setup PF TX loopback */
10682         vsi = pf->main_vsi;
10683         ret = i40e_vsi_set_tx_loopback(vsi, on);
10684         if (ret)
10685                 return -ENOTSUP;
10686
10687         /* setup TX loopback for all the VFs */
10688         if (!pf->vfs) {
10689                 /* if no VF, do nothing. */
10690                 return 0;
10691         }
10692
10693         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10694                 vf = &pf->vfs[vf_id];
10695                 vsi = vf->vsi;
10696
10697                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10698                 if (ret)
10699                         return -ENOTSUP;
10700         }
10701
10702         return ret;
10703 }
10704
10705 int
10706 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10707 {
10708         struct rte_eth_dev *dev;
10709         struct i40e_pf *pf;
10710         struct i40e_vsi *vsi;
10711         struct i40e_hw *hw;
10712         int ret;
10713
10714         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10715
10716         dev = &rte_eth_devices[port];
10717
10718         if (is_i40e_pmd(dev->data->drv_name))
10719                 return -ENOTSUP;
10720
10721         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10722
10723         if (vf_id >= pf->vf_num || !pf->vfs) {
10724                 PMD_DRV_LOG(ERR, "Invalid argument.");
10725                 return -EINVAL;
10726         }
10727
10728         vsi = pf->vfs[vf_id].vsi;
10729         if (!vsi) {
10730                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10731                 return -EINVAL;
10732         }
10733
10734         hw = I40E_VSI_TO_HW(vsi);
10735
10736         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10737                                                   on, NULL, true);
10738         if (ret != I40E_SUCCESS) {
10739                 ret = -ENOTSUP;
10740                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10741         }
10742
10743         return ret;
10744 }
10745
10746 int
10747 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10748 {
10749         struct rte_eth_dev *dev;
10750         struct i40e_pf *pf;
10751         struct i40e_vsi *vsi;
10752         struct i40e_hw *hw;
10753         int ret;
10754
10755         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10756
10757         dev = &rte_eth_devices[port];
10758
10759         if (is_i40e_pmd(dev->data->drv_name))
10760                 return -ENOTSUP;
10761
10762         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10763
10764         if (vf_id >= pf->vf_num || !pf->vfs) {
10765                 PMD_DRV_LOG(ERR, "Invalid argument.");
10766                 return -EINVAL;
10767         }
10768
10769         vsi = pf->vfs[vf_id].vsi;
10770         if (!vsi) {
10771                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10772                 return -EINVAL;
10773         }
10774
10775         hw = I40E_VSI_TO_HW(vsi);
10776
10777         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10778                                                     on, NULL);
10779         if (ret != I40E_SUCCESS) {
10780                 ret = -ENOTSUP;
10781                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10782         }
10783
10784         return ret;
10785 }
10786
10787 int
10788 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10789                              struct ether_addr *mac_addr)
10790 {
10791         struct i40e_mac_filter *f;
10792         struct rte_eth_dev *dev;
10793         struct i40e_pf_vf *vf;
10794         struct i40e_vsi *vsi;
10795         struct i40e_pf *pf;
10796         void *temp;
10797
10798         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10799                 return -EINVAL;
10800
10801         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10802
10803         dev = &rte_eth_devices[port];
10804
10805         if (is_i40e_pmd(dev->data->drv_name))
10806                 return -ENOTSUP;
10807
10808         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10809
10810         if (vf_id >= pf->vf_num || !pf->vfs)
10811                 return -EINVAL;
10812
10813         vf = &pf->vfs[vf_id];
10814         vsi = vf->vsi;
10815         if (!vsi) {
10816                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10817                 return -EINVAL;
10818         }
10819
10820         ether_addr_copy(mac_addr, &vf->mac_addr);
10821
10822         /* Remove all existing mac */
10823         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10824                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10825
10826         return 0;
10827 }
10828
10829 /* Set vlan strip on/off for specific VF from host */
10830 int
10831 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10832 {
10833         struct rte_eth_dev *dev;
10834         struct i40e_pf *pf;
10835         struct i40e_vsi *vsi;
10836         int ret;
10837
10838         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10839
10840         dev = &rte_eth_devices[port];
10841
10842         if (is_i40e_pmd(dev->data->drv_name))
10843                 return -ENOTSUP;
10844
10845         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10846
10847         if (vf_id >= pf->vf_num || !pf->vfs) {
10848                 PMD_DRV_LOG(ERR, "Invalid argument.");
10849                 return -EINVAL;
10850         }
10851
10852         vsi = pf->vfs[vf_id].vsi;
10853
10854         if (!vsi)
10855                 return -EINVAL;
10856
10857         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10858         if (ret != I40E_SUCCESS) {
10859                 ret = -ENOTSUP;
10860                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10861         }
10862
10863         return ret;
10864 }
10865
10866 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10867                                     uint16_t vlan_id)
10868 {
10869         struct rte_eth_dev *dev;
10870         struct i40e_pf *pf;
10871         struct i40e_hw *hw;
10872         struct i40e_vsi *vsi;
10873         struct i40e_vsi_context ctxt;
10874         int ret;
10875
10876         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10877
10878         if (vlan_id > ETHER_MAX_VLAN_ID) {
10879                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10880                 return -EINVAL;
10881         }
10882
10883         dev = &rte_eth_devices[port];
10884
10885         if (is_i40e_pmd(dev->data->drv_name))
10886                 return -ENOTSUP;
10887
10888         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10889         hw = I40E_PF_TO_HW(pf);
10890
10891         /**
10892          * return -ENODEV if SRIOV not enabled, VF number not configured
10893          * or no queue assigned.
10894          */
10895         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10896             pf->vf_nb_qps == 0)
10897                 return -ENODEV;
10898
10899         if (vf_id >= pf->vf_num || !pf->vfs) {
10900                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10901                 return -EINVAL;
10902         }
10903
10904         vsi = pf->vfs[vf_id].vsi;
10905         if (!vsi) {
10906                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10907                 return -EINVAL;
10908         }
10909
10910         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10911         vsi->info.pvid = vlan_id;
10912         if (vlan_id > 0)
10913                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10914         else
10915                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10916
10917         memset(&ctxt, 0, sizeof(ctxt));
10918         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10919         ctxt.seid = vsi->seid;
10920
10921         hw = I40E_VSI_TO_HW(vsi);
10922         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10923         if (ret != I40E_SUCCESS) {
10924                 ret = -ENOTSUP;
10925                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10926         }
10927
10928         return ret;
10929 }
10930
10931 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10932                                   uint8_t on)
10933 {
10934         struct rte_eth_dev *dev;
10935         struct i40e_pf *pf;
10936         struct i40e_vsi *vsi;
10937         struct i40e_hw *hw;
10938         int ret;
10939
10940         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10941
10942         if (on > 1) {
10943                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10944                 return -EINVAL;
10945         }
10946
10947         dev = &rte_eth_devices[port];
10948
10949         if (is_i40e_pmd(dev->data->drv_name))
10950                 return -ENOTSUP;
10951
10952         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10953         hw = I40E_PF_TO_HW(pf);
10954
10955         if (vf_id >= pf->vf_num || !pf->vfs) {
10956                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10957                 return -EINVAL;
10958         }
10959
10960         /**
10961          * return -ENODEV if SRIOV not enabled, VF number not configured
10962          * or no queue assigned.
10963          */
10964         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10965             pf->vf_nb_qps == 0) {
10966                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10967                 return -ENODEV;
10968         }
10969
10970         vsi = pf->vfs[vf_id].vsi;
10971         if (!vsi) {
10972                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10973                 return -EINVAL;
10974         }
10975
10976         hw = I40E_VSI_TO_HW(vsi);
10977
10978         ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
10979         if (ret != I40E_SUCCESS) {
10980                 ret = -ENOTSUP;
10981                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
10982         }
10983
10984         return ret;
10985 }
10986
10987 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
10988 {
10989         struct rte_eth_dev *dev;
10990         struct i40e_pf *pf;
10991         struct i40e_hw *hw;
10992         struct i40e_vsi *vsi;
10993         struct i40e_vsi_context ctxt;
10994         int ret;
10995
10996         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10997
10998         if (on > 1) {
10999                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11000                 return -EINVAL;
11001         }
11002
11003         dev = &rte_eth_devices[port];
11004
11005         if (is_i40e_pmd(dev->data->drv_name))
11006                 return -ENOTSUP;
11007
11008         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11009         hw = I40E_PF_TO_HW(pf);
11010
11011         /**
11012          * return -ENODEV if SRIOV not enabled, VF number not configured
11013          * or no queue assigned.
11014          */
11015         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11016             pf->vf_nb_qps == 0) {
11017                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11018                 return -ENODEV;
11019         }
11020
11021         if (vf_id >= pf->vf_num || !pf->vfs) {
11022                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11023                 return -EINVAL;
11024         }
11025
11026         vsi = pf->vfs[vf_id].vsi;
11027         if (!vsi) {
11028                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11029                 return -EINVAL;
11030         }
11031
11032         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11033         if (on) {
11034                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11035                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11036         } else {
11037                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11038                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11039         }
11040
11041         memset(&ctxt, 0, sizeof(ctxt));
11042         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11043         ctxt.seid = vsi->seid;
11044
11045         hw = I40E_VSI_TO_HW(vsi);
11046         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11047         if (ret != I40E_SUCCESS) {
11048                 ret = -ENOTSUP;
11049                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11050         }
11051
11052         return ret;
11053 }
11054
11055 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11056                                     uint64_t vf_mask, uint8_t on)
11057 {
11058         struct rte_eth_dev *dev;
11059         struct i40e_pf *pf;
11060         struct i40e_hw *hw;
11061         uint16_t vf_idx;
11062         int ret = I40E_SUCCESS;
11063
11064         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11065
11066         dev = &rte_eth_devices[port];
11067
11068         if (is_i40e_pmd(dev->data->drv_name))
11069                 return -ENOTSUP;
11070
11071         if (vlan_id > ETHER_MAX_VLAN_ID) {
11072                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11073                 return -EINVAL;
11074         }
11075
11076         if (vf_mask == 0) {
11077                 PMD_DRV_LOG(ERR, "No VF.");
11078                 return -EINVAL;
11079         }
11080
11081         if (on > 1) {
11082                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11083                 return -EINVAL;
11084         }
11085
11086         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11087         hw = I40E_PF_TO_HW(pf);
11088
11089         /**
11090          * return -ENODEV if SRIOV not enabled, VF number not configured
11091          * or no queue assigned.
11092          */
11093         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11094             pf->vf_nb_qps == 0) {
11095                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11096                 return -ENODEV;
11097         }
11098
11099         for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11100                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11101                         if (on)
11102                                 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11103                                                         vlan_id);
11104                         else
11105                                 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11106                                                            vlan_id);
11107                 }
11108         }
11109
11110         if (ret != I40E_SUCCESS) {
11111                 ret = -ENOTSUP;
11112                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11113         }
11114
11115         return ret;
11116 }
11117
11118 int
11119 rte_pmd_i40e_get_vf_stats(uint8_t port,
11120                           uint16_t vf_id,
11121                           struct rte_eth_stats *stats)
11122 {
11123         struct rte_eth_dev *dev;
11124         struct i40e_pf *pf;
11125         struct i40e_vsi *vsi;
11126
11127         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11128
11129         dev = &rte_eth_devices[port];
11130
11131         if (is_i40e_pmd(dev->data->drv_name))
11132                 return -ENOTSUP;
11133
11134         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11135
11136         if (vf_id >= pf->vf_num || !pf->vfs) {
11137                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11138                 return -EINVAL;
11139         }
11140
11141         vsi = pf->vfs[vf_id].vsi;
11142         if (!vsi) {
11143                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11144                 return -EINVAL;
11145         }
11146
11147         i40e_update_vsi_stats(vsi);
11148
11149         stats->ipackets = vsi->eth_stats.rx_unicast +
11150                         vsi->eth_stats.rx_multicast +
11151                         vsi->eth_stats.rx_broadcast;
11152         stats->opackets = vsi->eth_stats.tx_unicast +
11153                         vsi->eth_stats.tx_multicast +
11154                         vsi->eth_stats.tx_broadcast;
11155         stats->ibytes   = vsi->eth_stats.rx_bytes;
11156         stats->obytes   = vsi->eth_stats.tx_bytes;
11157         stats->ierrors  = vsi->eth_stats.rx_discards;
11158         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11159
11160         return 0;
11161 }
11162
11163 int
11164 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11165                             uint16_t vf_id)
11166 {
11167         struct rte_eth_dev *dev;
11168         struct i40e_pf *pf;
11169         struct i40e_vsi *vsi;
11170
11171         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11172
11173         dev = &rte_eth_devices[port];
11174
11175         if (is_i40e_pmd(dev->data->drv_name))
11176                 return -ENOTSUP;
11177
11178         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11179
11180         if (vf_id >= pf->vf_num || !pf->vfs) {
11181                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11182                 return -EINVAL;
11183         }
11184
11185         vsi = pf->vfs[vf_id].vsi;
11186         if (!vsi) {
11187                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11188                 return -EINVAL;
11189         }
11190
11191         vsi->offset_loaded = false;
11192         i40e_update_vsi_stats(vsi);
11193
11194         return 0;
11195 }