drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb =
 909                         is_floating_veb_supported(pci_dev->device.devargs);
 910                 config_vf_floating_veb(pci_dev->device.devargs,
 911                                        pf->floating_veb,
 912                                        pf->floating_veb_list);
 913         } else {
 914                 pf->floating_veb = false;
 915         }
 916 }
 917
 918 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 919 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 920
 921 static int
 922 eth_i40e_dev_init(struct rte_eth_dev *dev)
 923 {
 924         struct rte_pci_device *pci_dev;
 925         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927         struct i40e_vsi *vsi;
 928         int ret;
 929         uint32_t len;
 930         uint8_t aq_fail = 0;
 931
 932         PMD_INIT_FUNC_TRACE();
 933
 934         dev->dev_ops = &i40e_eth_dev_ops;
 935         dev->rx_pkt_burst = i40e_recv_pkts;
 936         dev->tx_pkt_burst = i40e_xmit_pkts;
 937
 938         /* for secondary processes, we don't initialise any further as primary
 939          * has already done this work. Only check we don't need a different
 940          * RX function */
 941         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 942                 i40e_set_rx_function(dev);
 943                 i40e_set_tx_function(dev);
 944                 return 0;
 945         }
 946         pci_dev = dev->pci_dev;
 947
 948         rte_eth_copy_pci_info(dev, pci_dev);
 949
 950         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 951         pf->adapter->eth_dev = dev;
 952         pf->dev_data = dev->data;
 953
 954         hw->back = I40E_PF_TO_ADAPTER(pf);
 955         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 956         if (!hw->hw_addr) {
 957                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 958                              "as address is NULL");
 959                 return -ENODEV;
 960         }
 961
 962         hw->vendor_id = pci_dev->id.vendor_id;
 963         hw->device_id = pci_dev->id.device_id;
 964         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 965         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 966         hw->bus.device = pci_dev->addr.devid;
 967         hw->bus.func = pci_dev->addr.function;
 968         hw->adapter_stopped = 0;
 969
 970         /* Make sure all is clean before doing PF reset */
 971         i40e_clear_hw(hw);
 972
 973         /* Initialize the hardware */
 974         i40e_hw_init(dev);
 975
 976         /* Reset here to make sure all is clean for each PF */
 977         ret = i40e_pf_reset(hw);
 978         if (ret) {
 979                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 980                 return ret;
 981         }
 982
 983         /* Initialize the shared code (base driver) */
 984         ret = i40e_init_shared_code(hw);
 985         if (ret) {
 986                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 987                 return ret;
 988         }
 989
 990         /*
 991          * To work around the NVM issue,initialize registers
 992          * for flexible payload by software.
 993          * It should be removed once issues are fixed in NVM.
 994          */
 995         i40e_flex_payload_reg_init(hw);
 996
 997         /* Initialize the input set for filters (hash and fd) to default value */
 998         i40e_filter_input_set_init(pf);
 999
1000         /* Initialize the parameters for adminq */
1001         i40e_init_adminq_parameter(hw);
1002         ret = i40e_init_adminq(hw);
1003         if (ret != I40E_SUCCESS) {
1004                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1005                 return -EIO;
1006         }
1007         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1008                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1009                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1010                      ((hw->nvm.version >> 12) & 0xf),
1011                      ((hw->nvm.version >> 4) & 0xff),
1012                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1013
1014         /* Need the special FW version to support floating VEB */
1015         config_floating_veb(dev);
1016         /* Clear PXE mode */
1017         i40e_clear_pxe_mode(hw);
1018
1019         /*
1020          * On X710, performance number is far from the expectation on recent
1021          * firmware versions. The fix for this issue may not be integrated in
1022          * the following firmware version. So the workaround in software driver
1023          * is needed. It needs to modify the initial values of 3 internal only
1024          * registers. Note that the workaround can be removed when it is fixed
1025          * in firmware in the future.
1026          */
1027         i40e_configure_registers(hw);
1028
1029         /* Get hw capabilities */
1030         ret = i40e_get_cap(hw);
1031         if (ret != I40E_SUCCESS) {
1032                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1033                 goto err_get_capabilities;
1034         }
1035
1036         /* Initialize parameters for PF */
1037         ret = i40e_pf_parameter_init(dev);
1038         if (ret != 0) {
1039                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1040                 goto err_parameter_init;
1041         }
1042
1043         /* Initialize the queue management */
1044         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1045         if (ret < 0) {
1046                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1047                 goto err_qp_pool_init;
1048         }
1049         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1050                                 hw->func_caps.num_msix_vectors - 1);
1051         if (ret < 0) {
1052                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1053                 goto err_msix_pool_init;
1054         }
1055
1056         /* Initialize lan hmc */
1057         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1058                                 hw->func_caps.num_rx_qp, 0, 0);
1059         if (ret != I40E_SUCCESS) {
1060                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1061                 goto err_init_lan_hmc;
1062         }
1063
1064         /* Configure lan hmc */
1065         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1066         if (ret != I40E_SUCCESS) {
1067                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1068                 goto err_configure_lan_hmc;
1069         }
1070
1071         /* Get and check the mac address */
1072         i40e_get_mac_addr(hw, hw->mac.addr);
1073         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "mac address is not valid");
1075                 ret = -EIO;
1076                 goto err_get_mac_addr;
1077         }
1078         /* Copy the permanent MAC address */
1079         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1080                         (struct ether_addr *) hw->mac.perm_addr);
1081
1082         /* Disable flow control */
1083         hw->fc.requested_mode = I40E_FC_NONE;
1084         i40e_set_fc(hw, &aq_fail, TRUE);
1085
1086         /* Set the global registers with default ether type value */
1087         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1088         if (ret != I40E_SUCCESS) {
1089                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1090                              "VLAN ether type");
1091                 goto err_setup_pf_switch;
1092         }
1093
1094         /* PF setup, which includes VSI setup */
1095         ret = i40e_pf_setup(pf);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1098                 goto err_setup_pf_switch;
1099         }
1100
1101         /* reset all stats of the device, including pf and main vsi */
1102         i40e_dev_stats_reset(dev);
1103
1104         vsi = pf->main_vsi;
1105
1106         /* Disable double vlan by default */
1107         i40e_vsi_config_double_vlan(vsi, FALSE);
1108
1109         /* Disable S-TAG identification by default */
1110         ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1111         if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1112                 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1113                 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1114         }
1115
1116         if (!vsi->max_macaddrs)
1117                 len = ETHER_ADDR_LEN;
1118         else
1119                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1120
1121         /* Should be after VSI initialized */
1122         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1123         if (!dev->data->mac_addrs) {
1124                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1125                                         "for storing mac address");
1126                 goto err_mac_alloc;
1127         }
1128         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1129                                         &dev->data->mac_addrs[0]);
1130
1131         /* initialize pf host driver to setup SRIOV resource if applicable */
1132         i40e_pf_host_init(dev);
1133
1134         /* register callback func to eal lib */
1135         rte_intr_callback_register(&(pci_dev->intr_handle),
1136                 i40e_dev_interrupt_handler, (void *)dev);
1137
1138         /* configure and enable device interrupt */
1139         i40e_pf_config_irq0(hw, TRUE);
1140         i40e_pf_enable_irq0(hw);
1141
1142         /* enable uio intr after callback register */
1143         rte_intr_enable(&(pci_dev->intr_handle));
1144         /*
1145          * Add an ethertype filter to drop all flow control frames transmitted
1146          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1147          * frames to wire.
1148          */
1149         i40e_add_tx_flow_control_drop_filter(pf);
1150
1151         /* Set the max frame size to 0x2600 by default,
1152          * in case other drivers changed the default value.
1153          */
1154         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1155
1156         /* initialize mirror rule list */
1157         TAILQ_INIT(&pf->mirror_list);
1158
1159         /* Init dcb to sw mode by default */
1160         ret = i40e_dcb_init_configure(dev, TRUE);
1161         if (ret != I40E_SUCCESS) {
1162                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1163                 pf->flags &= ~I40E_FLAG_DCB;
1164         }
1165
1166         return 0;
1167
1168 err_mac_alloc:
1169         i40e_vsi_release(pf->main_vsi);
1170 err_setup_pf_switch:
1171 err_get_mac_addr:
1172 err_configure_lan_hmc:
1173         (void)i40e_shutdown_lan_hmc(hw);
1174 err_init_lan_hmc:
1175         i40e_res_pool_destroy(&pf->msix_pool);
1176 err_msix_pool_init:
1177         i40e_res_pool_destroy(&pf->qp_pool);
1178 err_qp_pool_init:
1179 err_parameter_init:
1180 err_get_capabilities:
1181         (void)i40e_shutdown_adminq(hw);
1182
1183         return ret;
1184 }
1185
1186 static int
1187 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1188 {
1189         struct rte_pci_device *pci_dev;
1190         struct i40e_hw *hw;
1191         struct i40e_filter_control_settings settings;
1192         int ret;
1193         uint8_t aq_fail = 0;
1194
1195         PMD_INIT_FUNC_TRACE();
1196
1197         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1198                 return 0;
1199
1200         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201         pci_dev = dev->pci_dev;
1202
1203         if (hw->adapter_stopped == 0)
1204                 i40e_dev_close(dev);
1205
1206         dev->dev_ops = NULL;
1207         dev->rx_pkt_burst = NULL;
1208         dev->tx_pkt_burst = NULL;
1209
1210         /* Disable LLDP */
1211         ret = i40e_aq_stop_lldp(hw, true, NULL);
1212         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1213                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1214
1215         /* Clear PXE mode */
1216         i40e_clear_pxe_mode(hw);
1217
1218         /* Unconfigure filter control */
1219         memset(&settings, 0, sizeof(settings));
1220         ret = i40e_set_filter_control(hw, &settings);
1221         if (ret)
1222                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1223                                         ret);
1224
1225         /* Disable flow control */
1226         hw->fc.requested_mode = I40E_FC_NONE;
1227         i40e_set_fc(hw, &aq_fail, TRUE);
1228
1229         /* uninitialize pf host driver */
1230         i40e_pf_host_uninit(dev);
1231
1232         rte_free(dev->data->mac_addrs);
1233         dev->data->mac_addrs = NULL;
1234
1235         /* disable uio intr before callback unregister */
1236         rte_intr_disable(&(pci_dev->intr_handle));
1237
1238         /* register callback func to eal lib */
1239         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1240                 i40e_dev_interrupt_handler, (void *)dev);
1241
1242         return 0;
1243 }
1244
1245 static int
1246 i40e_dev_configure(struct rte_eth_dev *dev)
1247 {
1248         struct i40e_adapter *ad =
1249                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1251         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1252         int i, ret;
1253
1254         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1255          * bulk allocation or vector Rx preconditions we will reset it.
1256          */
1257         ad->rx_bulk_alloc_allowed = true;
1258         ad->rx_vec_allowed = true;
1259         ad->tx_simple_allowed = true;
1260         ad->tx_vec_allowed = true;
1261
1262         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1263                 ret = i40e_fdir_setup(pf);
1264                 if (ret != I40E_SUCCESS) {
1265                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1266                         return -ENOTSUP;
1267                 }
1268                 ret = i40e_fdir_configure(dev);
1269                 if (ret < 0) {
1270                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1271                         goto err;
1272                 }
1273         } else
1274                 i40e_fdir_teardown(pf);
1275
1276         ret = i40e_dev_init_vlan(dev);
1277         if (ret < 0)
1278                 goto err;
1279
1280         /* VMDQ setup.
1281          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1282          *  RSS setting have different requirements.
1283          *  General PMD driver call sequence are NIC init, configure,
1284          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1285          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1286          *  applicable. So, VMDQ setting has to be done before
1287          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1288          *  For RSS setting, it will try to calculate actual configured RX queue
1289          *  number, which will be available after rx_queue_setup(). dev_start()
1290          *  function is good to place RSS setup.
1291          */
1292         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1293                 ret = i40e_vmdq_setup(dev);
1294                 if (ret)
1295                         goto err;
1296         }
1297
1298         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1299                 ret = i40e_dcb_setup(dev);
1300                 if (ret) {
1301                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1302                         goto err_dcb;
1303                 }
1304         }
1305
1306         return 0;
1307
1308 err_dcb:
1309         /* need to release vmdq resource if exists */
1310         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1311                 i40e_vsi_release(pf->vmdq[i].vsi);
1312                 pf->vmdq[i].vsi = NULL;
1313         }
1314         rte_free(pf->vmdq);
1315         pf->vmdq = NULL;
1316 err:
1317         /* need to release fdir resource if exists */
1318         i40e_fdir_teardown(pf);
1319         return ret;
1320 }
1321
1322 void
1323 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1324 {
1325         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1326         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1327         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1328         uint16_t msix_vect = vsi->msix_intr;
1329         uint16_t i;
1330
1331         for (i = 0; i < vsi->nb_qps; i++) {
1332                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1333                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1334                 rte_wmb();
1335         }
1336
1337         if (vsi->type != I40E_VSI_SRIOV) {
1338                 if (!rte_intr_allow_others(intr_handle)) {
1339                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1340                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1341                         I40E_WRITE_REG(hw,
1342                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1343                                        0);
1344                 } else {
1345                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1346                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1347                         I40E_WRITE_REG(hw,
1348                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1349                                                        msix_vect - 1), 0);
1350                 }
1351         } else {
1352                 uint32_t reg;
1353                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1354                         vsi->user_param + (msix_vect - 1);
1355
1356                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1357                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1358         }
1359         I40E_WRITE_FLUSH(hw);
1360 }
1361
1362 static void
1363 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1364                        int base_queue, int nb_queue)
1365 {
1366         int i;
1367         uint32_t val;
1368         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1369
1370         /* Bind all RX queues to allocated MSIX interrupt */
1371         for (i = 0; i < nb_queue; i++) {
1372                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1373                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1374                         ((base_queue + i + 1) <<
1375                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1376                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1377                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1378
1379                 if (i == nb_queue - 1)
1380                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1381                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1382         }
1383
1384         /* Write first RX queue to Link list register as the head element */
1385         if (vsi->type != I40E_VSI_SRIOV) {
1386                 uint16_t interval =
1387                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1388
1389                 if (msix_vect == I40E_MISC_VEC_ID) {
1390                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1391                                        (base_queue <<
1392                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1393                                        (0x0 <<
1394                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1395                         I40E_WRITE_REG(hw,
1396                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1397                                        interval);
1398                 } else {
1399                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1400                                        (base_queue <<
1401                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1402                                        (0x0 <<
1403                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1404                         I40E_WRITE_REG(hw,
1405                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1406                                                        msix_vect - 1),
1407                                        interval);
1408                 }
1409         } else {
1410                 uint32_t reg;
1411
1412                 if (msix_vect == I40E_MISC_VEC_ID) {
1413                         I40E_WRITE_REG(hw,
1414                                        I40E_VPINT_LNKLST0(vsi->user_param),
1415                                        (base_queue <<
1416                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1417                                        (0x0 <<
1418                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1419                 } else {
1420                         /* num_msix_vectors_vf needs to minus irq0 */
1421                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1422                                 vsi->user_param + (msix_vect - 1);
1423
1424                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1425                                        (base_queue <<
1426                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1427                                        (0x0 <<
1428                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1429                 }
1430         }
1431
1432         I40E_WRITE_FLUSH(hw);
1433 }
1434
1435 void
1436 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1437 {
1438         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1439         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1440         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1441         uint16_t msix_vect = vsi->msix_intr;
1442         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1443         uint16_t queue_idx = 0;
1444         int record = 0;
1445         uint32_t val;
1446         int i;
1447
1448         for (i = 0; i < vsi->nb_qps; i++) {
1449                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1450                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1451         }
1452
1453         /* INTENA flag is not auto-cleared for interrupt */
1454         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1455         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1456                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1457                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1458         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1459
1460         /* VF bind interrupt */
1461         if (vsi->type == I40E_VSI_SRIOV) {
1462                 __vsi_queues_bind_intr(vsi, msix_vect,
1463                                        vsi->base_queue, vsi->nb_qps);
1464                 return;
1465         }
1466
1467         /* PF & VMDq bind interrupt */
1468         if (rte_intr_dp_is_en(intr_handle)) {
1469                 if (vsi->type == I40E_VSI_MAIN) {
1470                         queue_idx = 0;
1471                         record = 1;
1472                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1473                         struct i40e_vsi *main_vsi =
1474                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1475                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1476                         record = 1;
1477                 }
1478         }
1479
1480         for (i = 0; i < vsi->nb_used_qps; i++) {
1481                 if (nb_msix <= 1) {
1482                         if (!rte_intr_allow_others(intr_handle))
1483                                 /* allow to share MISC_VEC_ID */
1484                                 msix_vect = I40E_MISC_VEC_ID;
1485
1486                         /* no enough msix_vect, map all to one */
1487                         __vsi_queues_bind_intr(vsi, msix_vect,
1488                                                vsi->base_queue + i,
1489                                                vsi->nb_used_qps - i);
1490                         for (; !!record && i < vsi->nb_used_qps; i++)
1491                                 intr_handle->intr_vec[queue_idx + i] =
1492                                         msix_vect;
1493                         break;
1494                 }
1495                 /* 1:1 queue/msix_vect mapping */
1496                 __vsi_queues_bind_intr(vsi, msix_vect,
1497                                        vsi->base_queue + i, 1);
1498                 if (!!record)
1499                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1500
1501                 msix_vect++;
1502                 nb_msix--;
1503         }
1504 }
1505
1506 static void
1507 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1508 {
1509         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1510         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1511         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1512         uint16_t interval = i40e_calc_itr_interval(\
1513                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1514         uint16_t msix_intr, i;
1515
1516         if (rte_intr_allow_others(intr_handle))
1517                 for (i = 0; i < vsi->nb_msix; i++) {
1518                         msix_intr = vsi->msix_intr + i;
1519                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1520                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1521                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1522                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1523                                 (interval <<
1524                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1525                 }
1526         else
1527                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1528                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1529                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1530                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1531                                (interval <<
1532                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1533
1534         I40E_WRITE_FLUSH(hw);
1535 }
1536
1537 static void
1538 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1539 {
1540         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1541         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1542         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1543         uint16_t msix_intr, i;
1544
1545         if (rte_intr_allow_others(intr_handle))
1546                 for (i = 0; i < vsi->nb_msix; i++) {
1547                         msix_intr = vsi->msix_intr + i;
1548                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1549                                        0);
1550                 }
1551         else
1552                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1553
1554         I40E_WRITE_FLUSH(hw);
1555 }
1556
1557 static inline uint8_t
1558 i40e_parse_link_speeds(uint16_t link_speeds)
1559 {
1560         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1561
1562         if (link_speeds & ETH_LINK_SPEED_40G)
1563                 link_speed |= I40E_LINK_SPEED_40GB;
1564         if (link_speeds & ETH_LINK_SPEED_20G)
1565                 link_speed |= I40E_LINK_SPEED_20GB;
1566         if (link_speeds & ETH_LINK_SPEED_10G)
1567                 link_speed |= I40E_LINK_SPEED_10GB;
1568         if (link_speeds & ETH_LINK_SPEED_1G)
1569                 link_speed |= I40E_LINK_SPEED_1GB;
1570         if (link_speeds & ETH_LINK_SPEED_100M)
1571                 link_speed |= I40E_LINK_SPEED_100MB;
1572
1573         return link_speed;
1574 }
1575
1576 static int
1577 i40e_phy_conf_link(struct i40e_hw *hw,
1578                    uint8_t abilities,
1579                    uint8_t force_speed)
1580 {
1581         enum i40e_status_code status;
1582         struct i40e_aq_get_phy_abilities_resp phy_ab;
1583         struct i40e_aq_set_phy_config phy_conf;
1584         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1585                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1586                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1587                         I40E_AQ_PHY_FLAG_LOW_POWER;
1588         const uint8_t advt = I40E_LINK_SPEED_40GB |
1589                         I40E_LINK_SPEED_10GB |
1590                         I40E_LINK_SPEED_1GB |
1591                         I40E_LINK_SPEED_100MB;
1592         int ret = -ENOTSUP;
1593
1594
1595         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1596                                               NULL);
1597         if (status)
1598                 return ret;
1599
1600         memset(&phy_conf, 0, sizeof(phy_conf));
1601
1602         /* bits 0-2 use the values from get_phy_abilities_resp */
1603         abilities &= ~mask;
1604         abilities |= phy_ab.abilities & mask;
1605
1606         /* update ablities and speed */
1607         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1608                 phy_conf.link_speed = advt;
1609         else
1610                 phy_conf.link_speed = force_speed;
1611
1612         phy_conf.abilities = abilities;
1613
1614         /* use get_phy_abilities_resp value for the rest */
1615         phy_conf.phy_type = phy_ab.phy_type;
1616         phy_conf.eee_capability = phy_ab.eee_capability;
1617         phy_conf.eeer = phy_ab.eeer_val;
1618         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1619
1620         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1621                     phy_ab.abilities, phy_ab.link_speed);
1622         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1623                     phy_conf.abilities, phy_conf.link_speed);
1624
1625         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1626         if (status)
1627                 return ret;
1628
1629         return I40E_SUCCESS;
1630 }
1631
1632 static int
1633 i40e_apply_link_speed(struct rte_eth_dev *dev)
1634 {
1635         uint8_t speed;
1636         uint8_t abilities = 0;
1637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         struct rte_eth_conf *conf = &dev->data->dev_conf;
1639
1640         speed = i40e_parse_link_speeds(conf->link_speeds);
1641         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1642         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1643                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1644         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1645
1646         /* Skip changing speed on 40G interfaces, FW does not support */
1647         if (i40e_is_40G_device(hw->device_id)) {
1648                 speed =  I40E_LINK_SPEED_UNKNOWN;
1649                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1650         }
1651
1652         return i40e_phy_conf_link(hw, abilities, speed);
1653 }
1654
1655 static int
1656 i40e_dev_start(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         struct i40e_vsi *main_vsi = pf->main_vsi;
1661         int ret, i;
1662         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1663         uint32_t intr_vector = 0;
1664
1665         hw->adapter_stopped = 0;
1666
1667         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1668                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1669                              dev->data->port_id);
1670                 return -EINVAL;
1671         }
1672
1673         rte_intr_disable(intr_handle);
1674
1675         if ((rte_intr_cap_multiple(intr_handle) ||
1676              !RTE_ETH_DEV_SRIOV(dev).active) &&
1677             dev->data->dev_conf.intr_conf.rxq != 0) {
1678                 intr_vector = dev->data->nb_rx_queues;
1679                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1680                         return -1;
1681         }
1682
1683         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1684                 intr_handle->intr_vec =
1685                         rte_zmalloc("intr_vec",
1686                                     dev->data->nb_rx_queues * sizeof(int),
1687                                     0);
1688                 if (!intr_handle->intr_vec) {
1689                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1690                                      " intr_vec\n", dev->data->nb_rx_queues);
1691                         return -ENOMEM;
1692                 }
1693         }
1694
1695         /* Initialize VSI */
1696         ret = i40e_dev_rxtx_init(pf);
1697         if (ret != I40E_SUCCESS) {
1698                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1699                 goto err_up;
1700         }
1701
1702         /* Map queues with MSIX interrupt */
1703         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1704                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1705         i40e_vsi_queues_bind_intr(main_vsi);
1706         i40e_vsi_enable_queues_intr(main_vsi);
1707
1708         /* Map VMDQ VSI queues with MSIX interrupt */
1709         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1710                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1711                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1712                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1713         }
1714
1715         /* enable FDIR MSIX interrupt */
1716         if (pf->fdir.fdir_vsi) {
1717                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1718                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1719         }
1720
1721         /* Enable all queues which have been configured */
1722         ret = i40e_dev_switch_queues(pf, TRUE);
1723         if (ret != I40E_SUCCESS) {
1724                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1725                 goto err_up;
1726         }
1727
1728         /* Enable receiving broadcast packets */
1729         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1730         if (ret != I40E_SUCCESS)
1731                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1732
1733         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1734                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1735                                                 true, NULL);
1736                 if (ret != I40E_SUCCESS)
1737                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1738         }
1739
1740         /* Apply link configure */
1741         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1742                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1743                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1744                 PMD_DRV_LOG(ERR, "Invalid link setting");
1745                 goto err_up;
1746         }
1747         ret = i40e_apply_link_speed(dev);
1748         if (I40E_SUCCESS != ret) {
1749                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1750                 goto err_up;
1751         }
1752
1753         if (!rte_intr_allow_others(intr_handle)) {
1754                 rte_intr_callback_unregister(intr_handle,
1755                                              i40e_dev_interrupt_handler,
1756                                              (void *)dev);
1757                 /* configure and enable device interrupt */
1758                 i40e_pf_config_irq0(hw, FALSE);
1759                 i40e_pf_enable_irq0(hw);
1760
1761                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1762                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1763                                      " no intr multiplex\n");
1764         }
1765
1766         /* enable uio intr after callback register */
1767         rte_intr_enable(intr_handle);
1768
1769         return I40E_SUCCESS;
1770
1771 err_up:
1772         i40e_dev_switch_queues(pf, FALSE);
1773         i40e_dev_clear_queues(dev);
1774
1775         return ret;
1776 }
1777
1778 static void
1779 i40e_dev_stop(struct rte_eth_dev *dev)
1780 {
1781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1782         struct i40e_vsi *main_vsi = pf->main_vsi;
1783         struct i40e_mirror_rule *p_mirror;
1784         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1785         int i;
1786
1787         /* Disable all queues */
1788         i40e_dev_switch_queues(pf, FALSE);
1789
1790         /* un-map queues with interrupt registers */
1791         i40e_vsi_disable_queues_intr(main_vsi);
1792         i40e_vsi_queues_unbind_intr(main_vsi);
1793
1794         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1795                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1796                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1797         }
1798
1799         if (pf->fdir.fdir_vsi) {
1800                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1801                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1802         }
1803         /* Clear all queues and release memory */
1804         i40e_dev_clear_queues(dev);
1805
1806         /* Set link down */
1807         i40e_dev_set_link_down(dev);
1808
1809         /* Remove all mirror rules */
1810         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1811                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1812                 rte_free(p_mirror);
1813         }
1814         pf->nb_mirror_rule = 0;
1815
1816         if (!rte_intr_allow_others(intr_handle))
1817                 /* resume to the default handler */
1818                 rte_intr_callback_register(intr_handle,
1819                                            i40e_dev_interrupt_handler,
1820                                            (void *)dev);
1821
1822         /* Clean datapath event and queue/vec mapping */
1823         rte_intr_efd_disable(intr_handle);
1824         if (intr_handle->intr_vec) {
1825                 rte_free(intr_handle->intr_vec);
1826                 intr_handle->intr_vec = NULL;
1827         }
1828 }
1829
1830 static void
1831 i40e_dev_close(struct rte_eth_dev *dev)
1832 {
1833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         uint32_t reg;
1836         int i;
1837
1838         PMD_INIT_FUNC_TRACE();
1839
1840         i40e_dev_stop(dev);
1841         hw->adapter_stopped = 1;
1842         i40e_dev_free_queues(dev);
1843
1844         /* Disable interrupt */
1845         i40e_pf_disable_irq0(hw);
1846         rte_intr_disable(&(dev->pci_dev->intr_handle));
1847
1848         /* shutdown and destroy the HMC */
1849         i40e_shutdown_lan_hmc(hw);
1850
1851         /* release all the existing VSIs and VEBs */
1852         i40e_fdir_teardown(pf);
1853         i40e_vsi_release(pf->main_vsi);
1854
1855         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1856                 i40e_vsi_release(pf->vmdq[i].vsi);
1857                 pf->vmdq[i].vsi = NULL;
1858         }
1859
1860         rte_free(pf->vmdq);
1861         pf->vmdq = NULL;
1862
1863         /* shutdown the adminq */
1864         i40e_aq_queue_shutdown(hw, true);
1865         i40e_shutdown_adminq(hw);
1866
1867         i40e_res_pool_destroy(&pf->qp_pool);
1868         i40e_res_pool_destroy(&pf->msix_pool);
1869
1870         /* force a PF reset to clean anything leftover */
1871         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1872         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1873                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1874         I40E_WRITE_FLUSH(hw);
1875 }
1876
1877 static void
1878 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1879 {
1880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1881         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         struct i40e_vsi *vsi = pf->main_vsi;
1883         int status;
1884
1885         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1886                                                      true, NULL, true);
1887         if (status != I40E_SUCCESS)
1888                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1889
1890         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1891                                                         TRUE, NULL);
1892         if (status != I40E_SUCCESS)
1893                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1894
1895 }
1896
1897 static void
1898 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1899 {
1900         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902         struct i40e_vsi *vsi = pf->main_vsi;
1903         int status;
1904
1905         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1906                                                      false, NULL, true);
1907         if (status != I40E_SUCCESS)
1908                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1909
1910         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1911                                                         false, NULL);
1912         if (status != I40E_SUCCESS)
1913                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1914 }
1915
1916 static void
1917 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1918 {
1919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921         struct i40e_vsi *vsi = pf->main_vsi;
1922         int ret;
1923
1924         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1925         if (ret != I40E_SUCCESS)
1926                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1927 }
1928
1929 static void
1930 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1931 {
1932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct i40e_vsi *vsi = pf->main_vsi;
1935         int ret;
1936
1937         if (dev->data->promiscuous == 1)
1938                 return; /* must remain in all_multicast mode */
1939
1940         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1941                                 vsi->seid, FALSE, NULL);
1942         if (ret != I40E_SUCCESS)
1943                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1944 }
1945
1946 /*
1947  * Set device link up.
1948  */
1949 static int
1950 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1951 {
1952         /* re-apply link speed setting */
1953         return i40e_apply_link_speed(dev);
1954 }
1955
1956 /*
1957  * Set device link down.
1958  */
1959 static int
1960 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1961 {
1962         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1963         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965
1966         return i40e_phy_conf_link(hw, abilities, speed);
1967 }
1968
1969 int
1970 i40e_dev_link_update(struct rte_eth_dev *dev,
1971                      int wait_to_complete)
1972 {
1973 #define CHECK_INTERVAL 100  /* 100ms */
1974 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         struct i40e_link_status link_status;
1977         struct rte_eth_link link, old;
1978         int status;
1979         unsigned rep_cnt = MAX_REPEAT_TIME;
1980
1981         memset(&link, 0, sizeof(link));
1982         memset(&old, 0, sizeof(old));
1983         memset(&link_status, 0, sizeof(link_status));
1984         rte_i40e_dev_atomic_read_link_status(dev, &old);
1985
1986         do {
1987                 /* Get link status information from hardware */
1988                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1989                 if (status != I40E_SUCCESS) {
1990                         link.link_speed = ETH_SPEED_NUM_100M;
1991                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1992                         PMD_DRV_LOG(ERR, "Failed to get link info");
1993                         goto out;
1994                 }
1995
1996                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1997                 if (!wait_to_complete)
1998                         break;
1999
2000                 rte_delay_ms(CHECK_INTERVAL);
2001         } while (!link.link_status && rep_cnt--);
2002
2003         if (!link.link_status)
2004                 goto out;
2005
2006         /* i40e uses full duplex only */
2007         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2008
2009         /* Parse the link status */
2010         switch (link_status.link_speed) {
2011         case I40E_LINK_SPEED_100MB:
2012                 link.link_speed = ETH_SPEED_NUM_100M;
2013                 break;
2014         case I40E_LINK_SPEED_1GB:
2015                 link.link_speed = ETH_SPEED_NUM_1G;
2016                 break;
2017         case I40E_LINK_SPEED_10GB:
2018                 link.link_speed = ETH_SPEED_NUM_10G;
2019                 break;
2020         case I40E_LINK_SPEED_20GB:
2021                 link.link_speed = ETH_SPEED_NUM_20G;
2022                 break;
2023         case I40E_LINK_SPEED_40GB:
2024                 link.link_speed = ETH_SPEED_NUM_40G;
2025                 break;
2026         default:
2027                 link.link_speed = ETH_SPEED_NUM_100M;
2028                 break;
2029         }
2030
2031         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2032                         ETH_LINK_SPEED_FIXED);
2033
2034 out:
2035         rte_i40e_dev_atomic_write_link_status(dev, &link);
2036         if (link.link_status == old.link_status)
2037                 return -1;
2038
2039         return 0;
2040 }
2041
2042 /* Get all the statistics of a VSI */
2043 void
2044 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2045 {
2046         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2047         struct i40e_eth_stats *nes = &vsi->eth_stats;
2048         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2049         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2050
2051         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2052                             vsi->offset_loaded, &oes->rx_bytes,
2053                             &nes->rx_bytes);
2054         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2055                             vsi->offset_loaded, &oes->rx_unicast,
2056                             &nes->rx_unicast);
2057         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2058                             vsi->offset_loaded, &oes->rx_multicast,
2059                             &nes->rx_multicast);
2060         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2061                             vsi->offset_loaded, &oes->rx_broadcast,
2062                             &nes->rx_broadcast);
2063         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2064                             &oes->rx_discards, &nes->rx_discards);
2065         /* GLV_REPC not supported */
2066         /* GLV_RMPC not supported */
2067         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2068                             &oes->rx_unknown_protocol,
2069                             &nes->rx_unknown_protocol);
2070         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2071                             vsi->offset_loaded, &oes->tx_bytes,
2072                             &nes->tx_bytes);
2073         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2074                             vsi->offset_loaded, &oes->tx_unicast,
2075                             &nes->tx_unicast);
2076         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2077                             vsi->offset_loaded, &oes->tx_multicast,
2078                             &nes->tx_multicast);
2079         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2080                             vsi->offset_loaded,  &oes->tx_broadcast,
2081                             &nes->tx_broadcast);
2082         /* GLV_TDPC not supported */
2083         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2084                             &oes->tx_errors, &nes->tx_errors);
2085         vsi->offset_loaded = true;
2086
2087         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2088                     vsi->vsi_id);
2089         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2090         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2091         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2092         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2093         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2094         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2095                     nes->rx_unknown_protocol);
2096         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2097         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2098         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2099         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2100         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2101         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2102         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2103                     vsi->vsi_id);
2104 }
2105
2106 static void
2107 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2108 {
2109         unsigned int i;
2110         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2111         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2112
2113         /* Get statistics of struct i40e_eth_stats */
2114         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2115                             I40E_GLPRT_GORCL(hw->port),
2116                             pf->offset_loaded, &os->eth.rx_bytes,
2117                             &ns->eth.rx_bytes);
2118         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2119                             I40E_GLPRT_UPRCL(hw->port),
2120                             pf->offset_loaded, &os->eth.rx_unicast,
2121                             &ns->eth.rx_unicast);
2122         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2123                             I40E_GLPRT_MPRCL(hw->port),
2124                             pf->offset_loaded, &os->eth.rx_multicast,
2125                             &ns->eth.rx_multicast);
2126         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2127                             I40E_GLPRT_BPRCL(hw->port),
2128                             pf->offset_loaded, &os->eth.rx_broadcast,
2129                             &ns->eth.rx_broadcast);
2130         /* Workaround: CRC size should not be included in byte statistics,
2131          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2132          */
2133         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2134                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2135
2136         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2137                             pf->offset_loaded, &os->eth.rx_discards,
2138                             &ns->eth.rx_discards);
2139         /* GLPRT_REPC not supported */
2140         /* GLPRT_RMPC not supported */
2141         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2142                             pf->offset_loaded,
2143                             &os->eth.rx_unknown_protocol,
2144                             &ns->eth.rx_unknown_protocol);
2145         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2146                             I40E_GLPRT_GOTCL(hw->port),
2147                             pf->offset_loaded, &os->eth.tx_bytes,
2148                             &ns->eth.tx_bytes);
2149         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2150                             I40E_GLPRT_UPTCL(hw->port),
2151                             pf->offset_loaded, &os->eth.tx_unicast,
2152                             &ns->eth.tx_unicast);
2153         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2154                             I40E_GLPRT_MPTCL(hw->port),
2155                             pf->offset_loaded, &os->eth.tx_multicast,
2156                             &ns->eth.tx_multicast);
2157         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2158                             I40E_GLPRT_BPTCL(hw->port),
2159                             pf->offset_loaded, &os->eth.tx_broadcast,
2160                             &ns->eth.tx_broadcast);
2161         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2162                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2163         /* GLPRT_TEPC not supported */
2164
2165         /* additional port specific stats */
2166         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2167                             pf->offset_loaded, &os->tx_dropped_link_down,
2168                             &ns->tx_dropped_link_down);
2169         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2170                             pf->offset_loaded, &os->crc_errors,
2171                             &ns->crc_errors);
2172         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2173                             pf->offset_loaded, &os->illegal_bytes,
2174                             &ns->illegal_bytes);
2175         /* GLPRT_ERRBC not supported */
2176         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2177                             pf->offset_loaded, &os->mac_local_faults,
2178                             &ns->mac_local_faults);
2179         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2180                             pf->offset_loaded, &os->mac_remote_faults,
2181                             &ns->mac_remote_faults);
2182         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2183                             pf->offset_loaded, &os->rx_length_errors,
2184                             &ns->rx_length_errors);
2185         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2186                             pf->offset_loaded, &os->link_xon_rx,
2187                             &ns->link_xon_rx);
2188         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2189                             pf->offset_loaded, &os->link_xoff_rx,
2190                             &ns->link_xoff_rx);
2191         for (i = 0; i < 8; i++) {
2192                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2193                                     pf->offset_loaded,
2194                                     &os->priority_xon_rx[i],
2195                                     &ns->priority_xon_rx[i]);
2196                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2197                                     pf->offset_loaded,
2198                                     &os->priority_xoff_rx[i],
2199                                     &ns->priority_xoff_rx[i]);
2200         }
2201         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2202                             pf->offset_loaded, &os->link_xon_tx,
2203                             &ns->link_xon_tx);
2204         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2205                             pf->offset_loaded, &os->link_xoff_tx,
2206                             &ns->link_xoff_tx);
2207         for (i = 0; i < 8; i++) {
2208                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2209                                     pf->offset_loaded,
2210                                     &os->priority_xon_tx[i],
2211                                     &ns->priority_xon_tx[i]);
2212                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2213                                     pf->offset_loaded,
2214                                     &os->priority_xoff_tx[i],
2215                                     &ns->priority_xoff_tx[i]);
2216                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2217                                     pf->offset_loaded,
2218                                     &os->priority_xon_2_xoff[i],
2219                                     &ns->priority_xon_2_xoff[i]);
2220         }
2221         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2222                             I40E_GLPRT_PRC64L(hw->port),
2223                             pf->offset_loaded, &os->rx_size_64,
2224                             &ns->rx_size_64);
2225         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2226                             I40E_GLPRT_PRC127L(hw->port),
2227                             pf->offset_loaded, &os->rx_size_127,
2228                             &ns->rx_size_127);
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2230                             I40E_GLPRT_PRC255L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_255,
2232                             &ns->rx_size_255);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2234                             I40E_GLPRT_PRC511L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_511,
2236                             &ns->rx_size_511);
2237         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2238                             I40E_GLPRT_PRC1023L(hw->port),
2239                             pf->offset_loaded, &os->rx_size_1023,
2240                             &ns->rx_size_1023);
2241         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2242                             I40E_GLPRT_PRC1522L(hw->port),
2243                             pf->offset_loaded, &os->rx_size_1522,
2244                             &ns->rx_size_1522);
2245         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2246                             I40E_GLPRT_PRC9522L(hw->port),
2247                             pf->offset_loaded, &os->rx_size_big,
2248                             &ns->rx_size_big);
2249         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2250                             pf->offset_loaded, &os->rx_undersize,
2251                             &ns->rx_undersize);
2252         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2253                             pf->offset_loaded, &os->rx_fragments,
2254                             &ns->rx_fragments);
2255         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2256                             pf->offset_loaded, &os->rx_oversize,
2257                             &ns->rx_oversize);
2258         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2259                             pf->offset_loaded, &os->rx_jabber,
2260                             &ns->rx_jabber);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2262                             I40E_GLPRT_PTC64L(hw->port),
2263                             pf->offset_loaded, &os->tx_size_64,
2264                             &ns->tx_size_64);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2266                             I40E_GLPRT_PTC127L(hw->port),
2267                             pf->offset_loaded, &os->tx_size_127,
2268                             &ns->tx_size_127);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2270                             I40E_GLPRT_PTC255L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_255,
2272                             &ns->tx_size_255);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2274                             I40E_GLPRT_PTC511L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_511,
2276                             &ns->tx_size_511);
2277         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2278                             I40E_GLPRT_PTC1023L(hw->port),
2279                             pf->offset_loaded, &os->tx_size_1023,
2280                             &ns->tx_size_1023);
2281         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2282                             I40E_GLPRT_PTC1522L(hw->port),
2283                             pf->offset_loaded, &os->tx_size_1522,
2284                             &ns->tx_size_1522);
2285         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2286                             I40E_GLPRT_PTC9522L(hw->port),
2287                             pf->offset_loaded, &os->tx_size_big,
2288                             &ns->tx_size_big);
2289         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2290                            pf->offset_loaded,
2291                            &os->fd_sb_match, &ns->fd_sb_match);
2292         /* GLPRT_MSPDC not supported */
2293         /* GLPRT_XEC not supported */
2294
2295         pf->offset_loaded = true;
2296
2297         if (pf->main_vsi)
2298                 i40e_update_vsi_stats(pf->main_vsi);
2299 }
2300
2301 /* Get all statistics of a port */
2302 static void
2303 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2304 {
2305         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2308         unsigned i;
2309
2310         /* call read registers - updates values, now write them to struct */
2311         i40e_read_stats_registers(pf, hw);
2312
2313         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2314                         pf->main_vsi->eth_stats.rx_multicast +
2315                         pf->main_vsi->eth_stats.rx_broadcast -
2316                         pf->main_vsi->eth_stats.rx_discards;
2317         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2318                         pf->main_vsi->eth_stats.tx_multicast +
2319                         pf->main_vsi->eth_stats.tx_broadcast;
2320         stats->ibytes   = ns->eth.rx_bytes;
2321         stats->obytes   = ns->eth.tx_bytes;
2322         stats->oerrors  = ns->eth.tx_errors +
2323                         pf->main_vsi->eth_stats.tx_errors;
2324
2325         /* Rx Errors */
2326         stats->imissed  = ns->eth.rx_discards +
2327                         pf->main_vsi->eth_stats.rx_discards;
2328         stats->ierrors  = ns->crc_errors +
2329                         ns->rx_length_errors + ns->rx_undersize +
2330                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2331
2332         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2333         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2334         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2335         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2336         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2337         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2338         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2339                     ns->eth.rx_unknown_protocol);
2340         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2341         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2342         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2343         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2344         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2345         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2346
2347         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2348                     ns->tx_dropped_link_down);
2349         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2350         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2351                     ns->illegal_bytes);
2352         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2353         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2354                     ns->mac_local_faults);
2355         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2356                     ns->mac_remote_faults);
2357         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2358                     ns->rx_length_errors);
2359         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2360         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2361         for (i = 0; i < 8; i++) {
2362                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2363                                 i, ns->priority_xon_rx[i]);
2364                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2365                                 i, ns->priority_xoff_rx[i]);
2366         }
2367         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2368         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2369         for (i = 0; i < 8; i++) {
2370                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2371                                 i, ns->priority_xon_tx[i]);
2372                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2373                                 i, ns->priority_xoff_tx[i]);
2374                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2375                                 i, ns->priority_xon_2_xoff[i]);
2376         }
2377         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2378         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2379         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2380         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2381         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2382         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2383         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2384         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2385         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2386         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2387         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2388         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2389         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2390         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2391         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2392         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2393         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2394         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2395         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2396                         ns->mac_short_packet_dropped);
2397         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2398                     ns->checksum_error);
2399         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2400         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2401 }
2402
2403 /* Reset the statistics */
2404 static void
2405 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2406 {
2407         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409
2410         /* Mark PF and VSI stats to update the offset, aka "reset" */
2411         pf->offset_loaded = false;
2412         if (pf->main_vsi)
2413                 pf->main_vsi->offset_loaded = false;
2414
2415         /* read the stats, reading current register values into offset */
2416         i40e_read_stats_registers(pf, hw);
2417 }
2418
2419 static uint32_t
2420 i40e_xstats_calc_num(void)
2421 {
2422         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2423                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2424                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2425 }
2426
2427 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2428                                      struct rte_eth_xstat_name *xstats_names,
2429                                      __rte_unused unsigned limit)
2430 {
2431         unsigned count = 0;
2432         unsigned i, prio;
2433
2434         if (xstats_names == NULL)
2435                 return i40e_xstats_calc_num();
2436
2437         /* Note: limit checked in rte_eth_xstats_names() */
2438
2439         /* Get stats from i40e_eth_stats struct */
2440         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2441                 snprintf(xstats_names[count].name,
2442                          sizeof(xstats_names[count].name),
2443                          "%s", rte_i40e_stats_strings[i].name);
2444                 count++;
2445         }
2446
2447         /* Get individiual stats from i40e_hw_port struct */
2448         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2449                 snprintf(xstats_names[count].name,
2450                         sizeof(xstats_names[count].name),
2451                          "%s", rte_i40e_hw_port_strings[i].name);
2452                 count++;
2453         }
2454
2455         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2456                 for (prio = 0; prio < 8; prio++) {
2457                         snprintf(xstats_names[count].name,
2458                                  sizeof(xstats_names[count].name),
2459                                  "rx_priority%u_%s", prio,
2460                                  rte_i40e_rxq_prio_strings[i].name);
2461                         count++;
2462                 }
2463         }
2464
2465         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2466                 for (prio = 0; prio < 8; prio++) {
2467                         snprintf(xstats_names[count].name,
2468                                  sizeof(xstats_names[count].name),
2469                                  "tx_priority%u_%s", prio,
2470                                  rte_i40e_txq_prio_strings[i].name);
2471                         count++;
2472                 }
2473         }
2474         return count;
2475 }
2476
2477 static int
2478 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2479                     unsigned n)
2480 {
2481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483         unsigned i, count, prio;
2484         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2485
2486         count = i40e_xstats_calc_num();
2487         if (n < count)
2488                 return count;
2489
2490         i40e_read_stats_registers(pf, hw);
2491
2492         if (xstats == NULL)
2493                 return 0;
2494
2495         count = 0;
2496
2497         /* Get stats from i40e_eth_stats struct */
2498         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2499                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2500                         rte_i40e_stats_strings[i].offset);
2501                 count++;
2502         }
2503
2504         /* Get individiual stats from i40e_hw_port struct */
2505         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2506                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2507                         rte_i40e_hw_port_strings[i].offset);
2508                 count++;
2509         }
2510
2511         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2512                 for (prio = 0; prio < 8; prio++) {
2513                         xstats[count].value =
2514                                 *(uint64_t *)(((char *)hw_stats) +
2515                                 rte_i40e_rxq_prio_strings[i].offset +
2516                                 (sizeof(uint64_t) * prio));
2517                         count++;
2518                 }
2519         }
2520
2521         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2522                 for (prio = 0; prio < 8; prio++) {
2523                         xstats[count].value =
2524                                 *(uint64_t *)(((char *)hw_stats) +
2525                                 rte_i40e_txq_prio_strings[i].offset +
2526                                 (sizeof(uint64_t) * prio));
2527                         count++;
2528                 }
2529         }
2530
2531         return count;
2532 }
2533
2534 static int
2535 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2536                                  __rte_unused uint16_t queue_id,
2537                                  __rte_unused uint8_t stat_idx,
2538                                  __rte_unused uint8_t is_rx)
2539 {
2540         PMD_INIT_FUNC_TRACE();
2541
2542         return -ENOSYS;
2543 }
2544
2545 static void
2546 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2547 {
2548         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550         struct i40e_vsi *vsi = pf->main_vsi;
2551
2552         dev_info->max_rx_queues = vsi->nb_qps;
2553         dev_info->max_tx_queues = vsi->nb_qps;
2554         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2555         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2556         dev_info->max_mac_addrs = vsi->max_macaddrs;
2557         dev_info->max_vfs = dev->pci_dev->max_vfs;
2558         dev_info->rx_offload_capa =
2559                 DEV_RX_OFFLOAD_VLAN_STRIP |
2560                 DEV_RX_OFFLOAD_QINQ_STRIP |
2561                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2562                 DEV_RX_OFFLOAD_UDP_CKSUM |
2563                 DEV_RX_OFFLOAD_TCP_CKSUM;
2564         dev_info->tx_offload_capa =
2565                 DEV_TX_OFFLOAD_VLAN_INSERT |
2566                 DEV_TX_OFFLOAD_QINQ_INSERT |
2567                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2568                 DEV_TX_OFFLOAD_UDP_CKSUM |
2569                 DEV_TX_OFFLOAD_TCP_CKSUM |
2570                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2571                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2572                 DEV_TX_OFFLOAD_TCP_TSO;
2573         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2574                                                 sizeof(uint32_t);
2575         dev_info->reta_size = pf->hash_lut_size;
2576         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2577
2578         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2579                 .rx_thresh = {
2580                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2581                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2582                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2583                 },
2584                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2585                 .rx_drop_en = 0,
2586         };
2587
2588         dev_info->default_txconf = (struct rte_eth_txconf) {
2589                 .tx_thresh = {
2590                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2591                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2592                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2593                 },
2594                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2595                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2596                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2597                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2598         };
2599
2600         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2601                 .nb_max = I40E_MAX_RING_DESC,
2602                 .nb_min = I40E_MIN_RING_DESC,
2603                 .nb_align = I40E_ALIGN_RING_DESC,
2604         };
2605
2606         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2607                 .nb_max = I40E_MAX_RING_DESC,
2608                 .nb_min = I40E_MIN_RING_DESC,
2609                 .nb_align = I40E_ALIGN_RING_DESC,
2610         };
2611
2612         if (pf->flags & I40E_FLAG_VMDQ) {
2613                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2614                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2615                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2616                                                 pf->max_nb_vmdq_vsi;
2617                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2618                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2619                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2620         }
2621
2622         if (i40e_is_40G_device(hw->device_id))
2623                 /* For XL710 */
2624                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2625         else
2626                 /* For X710 */
2627                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2628 }
2629
2630 static int
2631 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2632 {
2633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2634         struct i40e_vsi *vsi = pf->main_vsi;
2635         PMD_INIT_FUNC_TRACE();
2636
2637         if (on)
2638                 return i40e_vsi_add_vlan(vsi, vlan_id);
2639         else
2640                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2641 }
2642
2643 static int
2644 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2645                    enum rte_vlan_type vlan_type,
2646                    uint16_t tpid)
2647 {
2648         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649         uint64_t reg_r = 0, reg_w = 0;
2650         uint16_t reg_id = 0;
2651         int ret = 0;
2652         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2653
2654         switch (vlan_type) {
2655         case ETH_VLAN_TYPE_OUTER:
2656                 if (qinq)
2657                         reg_id = 2;
2658                 else
2659                         reg_id = 3;
2660                 break;
2661         case ETH_VLAN_TYPE_INNER:
2662                 if (qinq)
2663                         reg_id = 3;
2664                 else {
2665                         ret = -EINVAL;
2666                         PMD_DRV_LOG(ERR,
2667                                 "Unsupported vlan type in single vlan.\n");
2668                         return ret;
2669                 }
2670                 break;
2671         default:
2672                 ret = -EINVAL;
2673                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2674                 return ret;
2675         }
2676         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2677                                           &reg_r, NULL);
2678         if (ret != I40E_SUCCESS) {
2679                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2680                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2681                 ret = -EIO;
2682                 return ret;
2683         }
2684         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2685                     "0x%08"PRIx64"", reg_id, reg_r);
2686
2687         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2688         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2689         if (reg_r == reg_w) {
2690                 ret = 0;
2691                 PMD_DRV_LOG(DEBUG, "No need to write");
2692                 return ret;
2693         }
2694
2695         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2696                                            reg_w, NULL);
2697         if (ret != I40E_SUCCESS) {
2698                 ret = -EIO;
2699                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2700                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2701                 return ret;
2702         }
2703         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2704                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2705
2706         return ret;
2707 }
2708
2709 static void
2710 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2711 {
2712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2713         struct i40e_vsi *vsi = pf->main_vsi;
2714
2715         if (mask & ETH_VLAN_FILTER_MASK) {
2716                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2717                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2718                 else
2719                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2720         }
2721
2722         if (mask & ETH_VLAN_STRIP_MASK) {
2723                 /* Enable or disable VLAN stripping */
2724                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2725                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2726                 else
2727                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2728         }
2729
2730         if (mask & ETH_VLAN_EXTEND_MASK) {
2731                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2732                         i40e_vsi_config_double_vlan(vsi, TRUE);
2733                         /* Set global registers with default ether type value */
2734                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2735                                            ETHER_TYPE_VLAN);
2736                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2737                                            ETHER_TYPE_VLAN);
2738                 }
2739                 else
2740                         i40e_vsi_config_double_vlan(vsi, FALSE);
2741         }
2742 }
2743
2744 static void
2745 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2746                           __rte_unused uint16_t queue,
2747                           __rte_unused int on)
2748 {
2749         PMD_INIT_FUNC_TRACE();
2750 }
2751
2752 static int
2753 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2754 {
2755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2756         struct i40e_vsi *vsi = pf->main_vsi;
2757         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2758         struct i40e_vsi_vlan_pvid_info info;
2759
2760         memset(&info, 0, sizeof(info));
2761         info.on = on;
2762         if (info.on)
2763                 info.config.pvid = pvid;
2764         else {
2765                 info.config.reject.tagged =
2766                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2767                 info.config.reject.untagged =
2768                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2769         }
2770
2771         return i40e_vsi_vlan_pvid_set(vsi, &info);
2772 }
2773
2774 static int
2775 i40e_dev_led_on(struct rte_eth_dev *dev)
2776 {
2777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         uint32_t mode = i40e_led_get(hw);
2779
2780         if (mode == 0)
2781                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2782
2783         return 0;
2784 }
2785
2786 static int
2787 i40e_dev_led_off(struct rte_eth_dev *dev)
2788 {
2789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         uint32_t mode = i40e_led_get(hw);
2791
2792         if (mode != 0)
2793                 i40e_led_set(hw, 0, false);
2794
2795         return 0;
2796 }
2797
2798 static int
2799 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2800 {
2801         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2803
2804         fc_conf->pause_time = pf->fc_conf.pause_time;
2805         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2806         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2807
2808          /* Return current mode according to actual setting*/
2809         switch (hw->fc.current_mode) {
2810         case I40E_FC_FULL:
2811                 fc_conf->mode = RTE_FC_FULL;
2812                 break;
2813         case I40E_FC_TX_PAUSE:
2814                 fc_conf->mode = RTE_FC_TX_PAUSE;
2815                 break;
2816         case I40E_FC_RX_PAUSE:
2817                 fc_conf->mode = RTE_FC_RX_PAUSE;
2818                 break;
2819         case I40E_FC_NONE:
2820         default:
2821                 fc_conf->mode = RTE_FC_NONE;
2822         };
2823
2824         return 0;
2825 }
2826
2827 static int
2828 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2829 {
2830         uint32_t mflcn_reg, fctrl_reg, reg;
2831         uint32_t max_high_water;
2832         uint8_t i, aq_failure;
2833         int err;
2834         struct i40e_hw *hw;
2835         struct i40e_pf *pf;
2836         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2837                 [RTE_FC_NONE] = I40E_FC_NONE,
2838                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2839                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2840                 [RTE_FC_FULL] = I40E_FC_FULL
2841         };
2842
2843         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2844
2845         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2846         if ((fc_conf->high_water > max_high_water) ||
2847                         (fc_conf->high_water < fc_conf->low_water)) {
2848                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2849                         "High_water must <= %d.", max_high_water);
2850                 return -EINVAL;
2851         }
2852
2853         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2856
2857         pf->fc_conf.pause_time = fc_conf->pause_time;
2858         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2859         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2860
2861         PMD_INIT_FUNC_TRACE();
2862
2863         /* All the link flow control related enable/disable register
2864          * configuration is handle by the F/W
2865          */
2866         err = i40e_set_fc(hw, &aq_failure, true);
2867         if (err < 0)
2868                 return -ENOSYS;
2869
2870         if (i40e_is_40G_device(hw->device_id)) {
2871                 /* Configure flow control refresh threshold,
2872                  * the value for stat_tx_pause_refresh_timer[8]
2873                  * is used for global pause operation.
2874                  */
2875
2876                 I40E_WRITE_REG(hw,
2877                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2878                                pf->fc_conf.pause_time);
2879
2880                 /* configure the timer value included in transmitted pause
2881                  * frame,
2882                  * the value for stat_tx_pause_quanta[8] is used for global
2883                  * pause operation
2884                  */
2885                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2886                                pf->fc_conf.pause_time);
2887
2888                 fctrl_reg = I40E_READ_REG(hw,
2889                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2890
2891                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2892                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2893                 else
2894                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2895
2896                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2897                                fctrl_reg);
2898         } else {
2899                 /* Configure pause time (2 TCs per register) */
2900                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2901                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2902                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2903
2904                 /* Configure flow control refresh threshold value */
2905                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2906                                pf->fc_conf.pause_time / 2);
2907
2908                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2909
2910                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2911                  *depending on configuration
2912                  */
2913                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2914                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2915                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2916                 } else {
2917                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2918                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2919                 }
2920
2921                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2922         }
2923
2924         /* config the water marker both based on the packets and bytes */
2925         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2926                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2927                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2928         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2929                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2930                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2931         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2932                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2933                        << I40E_KILOSHIFT);
2934         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2935                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2936                        << I40E_KILOSHIFT);
2937
2938         I40E_WRITE_FLUSH(hw);
2939
2940         return 0;
2941 }
2942
2943 static int
2944 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2945                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2946 {
2947         PMD_INIT_FUNC_TRACE();
2948
2949         return -ENOSYS;
2950 }
2951
2952 /* Add a MAC address, and update filters */
2953 static void
2954 i40e_macaddr_add(struct rte_eth_dev *dev,
2955                  struct ether_addr *mac_addr,
2956                  __rte_unused uint32_t index,
2957                  uint32_t pool)
2958 {
2959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2960         struct i40e_mac_filter_info mac_filter;
2961         struct i40e_vsi *vsi;
2962         int ret;
2963
2964         /* If VMDQ not enabled or configured, return */
2965         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2966                           !pf->nb_cfg_vmdq_vsi)) {
2967                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2968                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2969                         pool);
2970                 return;
2971         }
2972
2973         if (pool > pf->nb_cfg_vmdq_vsi) {
2974                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2975                                 pool, pf->nb_cfg_vmdq_vsi);
2976                 return;
2977         }
2978
2979         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2980         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2981                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2982         else
2983                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2984
2985         if (pool == 0)
2986                 vsi = pf->main_vsi;
2987         else
2988                 vsi = pf->vmdq[pool - 1].vsi;
2989
2990         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2991         if (ret != I40E_SUCCESS) {
2992                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2993                 return;
2994         }
2995 }
2996
2997 /* Remove a MAC address, and update filters */
2998 static void
2999 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3000 {
3001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002         struct i40e_vsi *vsi;
3003         struct rte_eth_dev_data *data = dev->data;
3004         struct ether_addr *macaddr;
3005         int ret;
3006         uint32_t i;
3007         uint64_t pool_sel;
3008
3009         macaddr = &(data->mac_addrs[index]);
3010
3011         pool_sel = dev->data->mac_pool_sel[index];
3012
3013         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3014                 if (pool_sel & (1ULL << i)) {
3015                         if (i == 0)
3016                                 vsi = pf->main_vsi;
3017                         else {
3018                                 /* No VMDQ pool enabled or configured */
3019                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3020                                         (i > pf->nb_cfg_vmdq_vsi)) {
3021                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3022                                                         "/configured");
3023                                         return;
3024                                 }
3025                                 vsi = pf->vmdq[i - 1].vsi;
3026                         }
3027                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3028
3029                         if (ret) {
3030                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3031                                 return;
3032                         }
3033                 }
3034         }
3035 }
3036
3037 /* Set perfect match or hash match of MAC and VLAN for a VF */
3038 static int
3039 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3040                  struct rte_eth_mac_filter *filter,
3041                  bool add)
3042 {
3043         struct i40e_hw *hw;
3044         struct i40e_mac_filter_info mac_filter;
3045         struct ether_addr old_mac;
3046         struct ether_addr *new_mac;
3047         struct i40e_pf_vf *vf = NULL;
3048         uint16_t vf_id;
3049         int ret;
3050
3051         if (pf == NULL) {
3052                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3053                 return -EINVAL;
3054         }
3055         hw = I40E_PF_TO_HW(pf);
3056
3057         if (filter == NULL) {
3058                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3059                 return -EINVAL;
3060         }
3061
3062         new_mac = &filter->mac_addr;
3063
3064         if (is_zero_ether_addr(new_mac)) {
3065                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3066                 return -EINVAL;
3067         }
3068
3069         vf_id = filter->dst_id;
3070
3071         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3072                 PMD_DRV_LOG(ERR, "Invalid argument.");
3073                 return -EINVAL;
3074         }
3075         vf = &pf->vfs[vf_id];
3076
3077         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3078                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3079                 return -EINVAL;
3080         }
3081
3082         if (add) {
3083                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3084                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3085                                 ETHER_ADDR_LEN);
3086                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3087                                  ETHER_ADDR_LEN);
3088
3089                 mac_filter.filter_type = filter->filter_type;
3090                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3091                 if (ret != I40E_SUCCESS) {
3092                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3093                         return -1;
3094                 }
3095                 ether_addr_copy(new_mac, &pf->dev_addr);
3096         } else {
3097                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3098                                 ETHER_ADDR_LEN);
3099                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3100                 if (ret != I40E_SUCCESS) {
3101                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3102                         return -1;
3103                 }
3104
3105                 /* Clear device address as it has been removed */
3106                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3107                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3108         }
3109
3110         return 0;
3111 }
3112
3113 /* MAC filter handle */
3114 static int
3115 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3116                 void *arg)
3117 {
3118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119         struct rte_eth_mac_filter *filter;
3120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3121         int ret = I40E_NOT_SUPPORTED;
3122
3123         filter = (struct rte_eth_mac_filter *)(arg);
3124
3125         switch (filter_op) {
3126         case RTE_ETH_FILTER_NOP:
3127                 ret = I40E_SUCCESS;
3128                 break;
3129         case RTE_ETH_FILTER_ADD:
3130                 i40e_pf_disable_irq0(hw);
3131                 if (filter->is_vf)
3132                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3133                 i40e_pf_enable_irq0(hw);
3134                 break;
3135         case RTE_ETH_FILTER_DELETE:
3136                 i40e_pf_disable_irq0(hw);
3137                 if (filter->is_vf)
3138                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3139                 i40e_pf_enable_irq0(hw);
3140                 break;
3141         default:
3142                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3143                 ret = I40E_ERR_PARAM;
3144                 break;
3145         }
3146
3147         return ret;
3148 }
3149
3150 static int
3151 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3152 {
3153         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3154         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3155         int ret;
3156
3157         if (!lut)
3158                 return -EINVAL;
3159
3160         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3161                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3162                                           lut, lut_size);
3163                 if (ret) {
3164                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3165                         return ret;
3166                 }
3167         } else {
3168                 uint32_t *lut_dw = (uint32_t *)lut;
3169                 uint16_t i, lut_size_dw = lut_size / 4;
3170
3171                 for (i = 0; i < lut_size_dw; i++)
3172                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3173         }
3174
3175         return 0;
3176 }
3177
3178 static int
3179 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3180 {
3181         struct i40e_pf *pf;
3182         struct i40e_hw *hw;
3183         int ret;
3184
3185         if (!vsi || !lut)
3186                 return -EINVAL;
3187
3188         pf = I40E_VSI_TO_PF(vsi);
3189         hw = I40E_VSI_TO_HW(vsi);
3190
3191         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3192                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3193                                           lut, lut_size);
3194                 if (ret) {
3195                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3196                         return ret;
3197                 }
3198         } else {
3199                 uint32_t *lut_dw = (uint32_t *)lut;
3200                 uint16_t i, lut_size_dw = lut_size / 4;
3201
3202                 for (i = 0; i < lut_size_dw; i++)
3203                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3204                 I40E_WRITE_FLUSH(hw);
3205         }
3206
3207         return 0;
3208 }
3209
3210 static int
3211 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3212                          struct rte_eth_rss_reta_entry64 *reta_conf,
3213                          uint16_t reta_size)
3214 {
3215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3216         uint16_t i, lut_size = pf->hash_lut_size;
3217         uint16_t idx, shift;
3218         uint8_t *lut;
3219         int ret;
3220
3221         if (reta_size != lut_size ||
3222                 reta_size > ETH_RSS_RETA_SIZE_512) {
3223                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3224                         "(%d) doesn't match the number hardware can supported "
3225                                         "(%d)\n", reta_size, lut_size);
3226                 return -EINVAL;
3227         }
3228
3229         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3230         if (!lut) {
3231                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3232                 return -ENOMEM;
3233         }
3234         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3235         if (ret)
3236                 goto out;
3237         for (i = 0; i < reta_size; i++) {
3238                 idx = i / RTE_RETA_GROUP_SIZE;
3239                 shift = i % RTE_RETA_GROUP_SIZE;
3240                 if (reta_conf[idx].mask & (1ULL << shift))
3241                         lut[i] = reta_conf[idx].reta[shift];
3242         }
3243         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3244
3245 out:
3246         rte_free(lut);
3247
3248         return ret;
3249 }
3250
3251 static int
3252 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3253                         struct rte_eth_rss_reta_entry64 *reta_conf,
3254                         uint16_t reta_size)
3255 {
3256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3257         uint16_t i, lut_size = pf->hash_lut_size;
3258         uint16_t idx, shift;
3259         uint8_t *lut;
3260         int ret;
3261
3262         if (reta_size != lut_size ||
3263                 reta_size > ETH_RSS_RETA_SIZE_512) {
3264                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3265                         "(%d) doesn't match the number hardware can supported "
3266                                         "(%d)\n", reta_size, lut_size);
3267                 return -EINVAL;
3268         }
3269
3270         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3271         if (!lut) {
3272                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3273                 return -ENOMEM;
3274         }
3275
3276         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3277         if (ret)
3278                 goto out;
3279         for (i = 0; i < reta_size; i++) {
3280                 idx = i / RTE_RETA_GROUP_SIZE;
3281                 shift = i % RTE_RETA_GROUP_SIZE;
3282                 if (reta_conf[idx].mask & (1ULL << shift))
3283                         reta_conf[idx].reta[shift] = lut[i];
3284         }
3285
3286 out:
3287         rte_free(lut);
3288
3289         return ret;
3290 }
3291
3292 /**
3293  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3294  * @hw:   pointer to the HW structure
3295  * @mem:  pointer to mem struct to fill out
3296  * @size: size of memory requested
3297  * @alignment: what to align the allocation to
3298  **/
3299 enum i40e_status_code
3300 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3301                         struct i40e_dma_mem *mem,
3302                         u64 size,
3303                         u32 alignment)
3304 {
3305         const struct rte_memzone *mz = NULL;
3306         char z_name[RTE_MEMZONE_NAMESIZE];
3307
3308         if (!mem)
3309                 return I40E_ERR_PARAM;
3310
3311         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3312         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3313                                          alignment, RTE_PGSIZE_2M);
3314         if (!mz)
3315                 return I40E_ERR_NO_MEMORY;
3316
3317         mem->size = size;
3318         mem->va = mz->addr;
3319         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3320         mem->zone = (const void *)mz;
3321         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3322                     "%"PRIu64, mz->name, mem->pa);
3323
3324         return I40E_SUCCESS;
3325 }
3326
3327 /**
3328  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3329  * @hw:   pointer to the HW structure
3330  * @mem:  ptr to mem struct to free
3331  **/
3332 enum i40e_status_code
3333 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3334                     struct i40e_dma_mem *mem)
3335 {
3336         if (!mem)
3337                 return I40E_ERR_PARAM;
3338
3339         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3340                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3341                     mem->pa);
3342         rte_memzone_free((const struct rte_memzone *)mem->zone);
3343         mem->zone = NULL;
3344         mem->va = NULL;
3345         mem->pa = (u64)0;
3346
3347         return I40E_SUCCESS;
3348 }
3349
3350 /**
3351  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3352  * @hw:   pointer to the HW structure
3353  * @mem:  pointer to mem struct to fill out
3354  * @size: size of memory requested
3355  **/
3356 enum i40e_status_code
3357 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3358                          struct i40e_virt_mem *mem,
3359                          u32 size)
3360 {
3361         if (!mem)
3362                 return I40E_ERR_PARAM;
3363
3364         mem->size = size;
3365         mem->va = rte_zmalloc("i40e", size, 0);
3366
3367         if (mem->va)
3368                 return I40E_SUCCESS;
3369         else
3370                 return I40E_ERR_NO_MEMORY;
3371 }
3372
3373 /**
3374  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3375  * @hw:   pointer to the HW structure
3376  * @mem:  pointer to mem struct to free
3377  **/
3378 enum i40e_status_code
3379 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3380                      struct i40e_virt_mem *mem)
3381 {
3382         if (!mem)
3383                 return I40E_ERR_PARAM;
3384
3385         rte_free(mem->va);
3386         mem->va = NULL;
3387
3388         return I40E_SUCCESS;
3389 }
3390
3391 void
3392 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3393 {
3394         rte_spinlock_init(&sp->spinlock);
3395 }
3396
3397 void
3398 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3399 {
3400         rte_spinlock_lock(&sp->spinlock);
3401 }
3402
3403 void
3404 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3405 {
3406         rte_spinlock_unlock(&sp->spinlock);
3407 }
3408
3409 void
3410 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3411 {
3412         return;
3413 }
3414
3415 /**
3416  * Get the hardware capabilities, which will be parsed
3417  * and saved into struct i40e_hw.
3418  */
3419 static int
3420 i40e_get_cap(struct i40e_hw *hw)
3421 {
3422         struct i40e_aqc_list_capabilities_element_resp *buf;
3423         uint16_t len, size = 0;
3424         int ret;
3425
3426         /* Calculate a huge enough buff for saving response data temporarily */
3427         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3428                                                 I40E_MAX_CAP_ELE_NUM;
3429         buf = rte_zmalloc("i40e", len, 0);
3430         if (!buf) {
3431                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3432                 return I40E_ERR_NO_MEMORY;
3433         }
3434
3435         /* Get, parse the capabilities and save it to hw */
3436         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3437                         i40e_aqc_opc_list_func_capabilities, NULL);
3438         if (ret != I40E_SUCCESS)
3439                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3440
3441         /* Free the temporary buffer after being used */
3442         rte_free(buf);
3443
3444         return ret;
3445 }
3446
3447 static int
3448 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3449 {
3450         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3452         uint16_t qp_count = 0, vsi_count = 0;
3453
3454         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3455                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3456                 return -EINVAL;
3457         }
3458         /* Add the parameter init for LFC */
3459         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3460         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3461         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3462
3463         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3464         pf->max_num_vsi = hw->func_caps.num_vsis;
3465         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3466         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3467         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3468
3469         /* FDir queue/VSI allocation */
3470         pf->fdir_qp_offset = 0;
3471         if (hw->func_caps.fd) {
3472                 pf->flags |= I40E_FLAG_FDIR;
3473                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3474         } else {
3475                 pf->fdir_nb_qps = 0;
3476         }
3477         qp_count += pf->fdir_nb_qps;
3478         vsi_count += 1;
3479
3480         /* LAN queue/VSI allocation */
3481         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3482         if (!hw->func_caps.rss) {
3483                 pf->lan_nb_qps = 1;
3484         } else {
3485                 pf->flags |= I40E_FLAG_RSS;
3486                 if (hw->mac.type == I40E_MAC_X722)
3487                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3488                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3489         }
3490         qp_count += pf->lan_nb_qps;
3491         vsi_count += 1;
3492
3493         /* VF queue/VSI allocation */
3494         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3495         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3496                 pf->flags |= I40E_FLAG_SRIOV;
3497                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3498                 pf->vf_num = dev->pci_dev->max_vfs;
3499                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3500                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3501                             pf->vf_nb_qps * pf->vf_num);
3502         } else {
3503                 pf->vf_nb_qps = 0;
3504                 pf->vf_num = 0;
3505         }
3506         qp_count += pf->vf_nb_qps * pf->vf_num;
3507         vsi_count += pf->vf_num;
3508
3509         /* VMDq queue/VSI allocation */
3510         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3511         pf->vmdq_nb_qps = 0;
3512         pf->max_nb_vmdq_vsi = 0;
3513         if (hw->func_caps.vmdq) {
3514                 if (qp_count < hw->func_caps.num_tx_qp &&
3515                         vsi_count < hw->func_caps.num_vsis) {
3516                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3517                                 qp_count) / pf->vmdq_nb_qp_max;
3518
3519                         /* Limit the maximum number of VMDq vsi to the maximum
3520                          * ethdev can support
3521                          */
3522                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3523                                 hw->func_caps.num_vsis - vsi_count);
3524                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3525                                 ETH_64_POOLS);
3526                         if (pf->max_nb_vmdq_vsi) {
3527                                 pf->flags |= I40E_FLAG_VMDQ;
3528                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3529                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3530                                             "per VMDQ VSI, in total %u queues",
3531                                             pf->max_nb_vmdq_vsi,
3532                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3533                                             pf->max_nb_vmdq_vsi);
3534                         } else {
3535                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3536                                             "VMDq");
3537                         }
3538                 } else {
3539                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3540                 }
3541         }
3542         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3543         vsi_count += pf->max_nb_vmdq_vsi;
3544
3545         if (hw->func_caps.dcb)
3546                 pf->flags |= I40E_FLAG_DCB;
3547
3548         if (qp_count > hw->func_caps.num_tx_qp) {
3549                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3550                             "the hardware maximum %u", qp_count,
3551                             hw->func_caps.num_tx_qp);
3552                 return -EINVAL;
3553         }
3554         if (vsi_count > hw->func_caps.num_vsis) {
3555                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3556                             "the hardware maximum %u", vsi_count,
3557                             hw->func_caps.num_vsis);
3558                 return -EINVAL;
3559         }
3560
3561         return 0;
3562 }
3563
3564 static int
3565 i40e_pf_get_switch_config(struct i40e_pf *pf)
3566 {
3567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3568         struct i40e_aqc_get_switch_config_resp *switch_config;
3569         struct i40e_aqc_switch_config_element_resp *element;
3570         uint16_t start_seid = 0, num_reported;
3571         int ret;
3572
3573         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3574                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3575         if (!switch_config) {
3576                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3577                 return -ENOMEM;
3578         }
3579
3580         /* Get the switch configurations */
3581         ret = i40e_aq_get_switch_config(hw, switch_config,
3582                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3583         if (ret != I40E_SUCCESS) {
3584                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3585                 goto fail;
3586         }
3587         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3588         if (num_reported != 1) { /* The number should be 1 */
3589                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3590                 goto fail;
3591         }
3592
3593         /* Parse the switch configuration elements */
3594         element = &(switch_config->element[0]);
3595         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3596                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3597                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3598         } else
3599                 PMD_DRV_LOG(INFO, "Unknown element type");
3600
3601 fail:
3602         rte_free(switch_config);
3603
3604         return ret;
3605 }
3606
3607 static int
3608 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3609                         uint32_t num)
3610 {
3611         struct pool_entry *entry;
3612
3613         if (pool == NULL || num == 0)
3614                 return -EINVAL;
3615
3616         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3617         if (entry == NULL) {
3618                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3619                 return -ENOMEM;
3620         }
3621
3622         /* queue heap initialize */
3623         pool->num_free = num;
3624         pool->num_alloc = 0;
3625         pool->base = base;
3626         LIST_INIT(&pool->alloc_list);
3627         LIST_INIT(&pool->free_list);
3628
3629         /* Initialize element  */
3630         entry->base = 0;
3631         entry->len = num;
3632
3633         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3634         return 0;
3635 }
3636
3637 static void
3638 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3639 {
3640         struct pool_entry *entry, *next_entry;
3641
3642         if (pool == NULL)
3643                 return;
3644
3645         for (entry = LIST_FIRST(&pool->alloc_list);
3646                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3647                         entry = next_entry) {
3648                 LIST_REMOVE(entry, next);
3649                 rte_free(entry);
3650         }
3651
3652         for (entry = LIST_FIRST(&pool->free_list);
3653                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3654                         entry = next_entry) {
3655                 LIST_REMOVE(entry, next);
3656                 rte_free(entry);
3657         }
3658
3659         pool->num_free = 0;
3660         pool->num_alloc = 0;
3661         pool->base = 0;
3662         LIST_INIT(&pool->alloc_list);
3663         LIST_INIT(&pool->free_list);
3664 }
3665
3666 static int
3667 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3668                        uint32_t base)
3669 {
3670         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3671         uint32_t pool_offset;
3672         int insert;
3673
3674         if (pool == NULL) {
3675                 PMD_DRV_LOG(ERR, "Invalid parameter");
3676                 return -EINVAL;
3677         }
3678
3679         pool_offset = base - pool->base;
3680         /* Lookup in alloc list */
3681         LIST_FOREACH(entry, &pool->alloc_list, next) {
3682                 if (entry->base == pool_offset) {
3683                         valid_entry = entry;
3684                         LIST_REMOVE(entry, next);
3685                         break;
3686                 }
3687         }
3688
3689         /* Not find, return */
3690         if (valid_entry == NULL) {
3691                 PMD_DRV_LOG(ERR, "Failed to find entry");
3692                 return -EINVAL;
3693         }
3694
3695         /**
3696          * Found it, move it to free list  and try to merge.
3697          * In order to make merge easier, always sort it by qbase.
3698          * Find adjacent prev and last entries.
3699          */
3700         prev = next = NULL;
3701         LIST_FOREACH(entry, &pool->free_list, next) {
3702                 if (entry->base > valid_entry->base) {
3703                         next = entry;
3704                         break;
3705                 }
3706                 prev = entry;
3707         }
3708
3709         insert = 0;
3710         /* Try to merge with next one*/
3711         if (next != NULL) {
3712                 /* Merge with next one */
3713                 if (valid_entry->base + valid_entry->len == next->base) {
3714                         next->base = valid_entry->base;
3715                         next->len += valid_entry->len;
3716                         rte_free(valid_entry);
3717                         valid_entry = next;
3718                         insert = 1;
3719                 }
3720         }
3721
3722         if (prev != NULL) {
3723                 /* Merge with previous one */
3724                 if (prev->base + prev->len == valid_entry->base) {
3725                         prev->len += valid_entry->len;
3726                         /* If it merge with next one, remove next node */
3727                         if (insert == 1) {
3728                                 LIST_REMOVE(valid_entry, next);
3729                                 rte_free(valid_entry);
3730                         } else {
3731                                 rte_free(valid_entry);
3732                                 insert = 1;
3733                         }
3734                 }
3735         }
3736
3737         /* Not find any entry to merge, insert */
3738         if (insert == 0) {
3739                 if (prev != NULL)
3740                         LIST_INSERT_AFTER(prev, valid_entry, next);
3741                 else if (next != NULL)
3742                         LIST_INSERT_BEFORE(next, valid_entry, next);
3743                 else /* It's empty list, insert to head */
3744                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3745         }
3746
3747         pool->num_free += valid_entry->len;
3748         pool->num_alloc -= valid_entry->len;
3749
3750         return 0;
3751 }
3752
3753 static int
3754 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3755                        uint16_t num)
3756 {
3757         struct pool_entry *entry, *valid_entry;
3758
3759         if (pool == NULL || num == 0) {
3760                 PMD_DRV_LOG(ERR, "Invalid parameter");
3761                 return -EINVAL;
3762         }
3763
3764         if (pool->num_free < num) {
3765                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3766                             num, pool->num_free);
3767                 return -ENOMEM;
3768         }
3769
3770         valid_entry = NULL;
3771         /* Lookup  in free list and find most fit one */
3772         LIST_FOREACH(entry, &pool->free_list, next) {
3773                 if (entry->len >= num) {
3774                         /* Find best one */
3775                         if (entry->len == num) {
3776                                 valid_entry = entry;
3777                                 break;
3778                         }
3779                         if (valid_entry == NULL || valid_entry->len > entry->len)
3780                                 valid_entry = entry;
3781                 }
3782         }
3783
3784         /* Not find one to satisfy the request, return */
3785         if (valid_entry == NULL) {
3786                 PMD_DRV_LOG(ERR, "No valid entry found");
3787                 return -ENOMEM;
3788         }
3789         /**
3790          * The entry have equal queue number as requested,
3791          * remove it from alloc_list.
3792          */
3793         if (valid_entry->len == num) {
3794                 LIST_REMOVE(valid_entry, next);
3795         } else {
3796                 /**
3797                  * The entry have more numbers than requested,
3798                  * create a new entry for alloc_list and minus its
3799                  * queue base and number in free_list.
3800                  */
3801                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3802                 if (entry == NULL) {
3803                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3804                                     "resource pool");
3805                         return -ENOMEM;
3806                 }
3807                 entry->base = valid_entry->base;
3808                 entry->len = num;
3809                 valid_entry->base += num;
3810                 valid_entry->len -= num;
3811                 valid_entry = entry;
3812         }
3813
3814         /* Insert it into alloc list, not sorted */
3815         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3816
3817         pool->num_free -= valid_entry->len;
3818         pool->num_alloc += valid_entry->len;
3819
3820         return valid_entry->base + pool->base;
3821 }
3822
3823 /**
3824  * bitmap_is_subset - Check whether src2 is subset of src1
3825  **/
3826 static inline int
3827 bitmap_is_subset(uint8_t src1, uint8_t src2)
3828 {
3829         return !((src1 ^ src2) & src2);
3830 }
3831
3832 static enum i40e_status_code
3833 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3834 {
3835         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3836
3837         /* If DCB is not supported, only default TC is supported */
3838         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3839                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3840                 return I40E_NOT_SUPPORTED;
3841         }
3842
3843         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3844                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3845                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3846                             enabled_tcmap);
3847                 return I40E_NOT_SUPPORTED;
3848         }
3849         return I40E_SUCCESS;
3850 }
3851
3852 int
3853 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3854                                 struct i40e_vsi_vlan_pvid_info *info)
3855 {
3856         struct i40e_hw *hw;
3857         struct i40e_vsi_context ctxt;
3858         uint8_t vlan_flags = 0;
3859         int ret;
3860
3861         if (vsi == NULL || info == NULL) {
3862                 PMD_DRV_LOG(ERR, "invalid parameters");
3863                 return I40E_ERR_PARAM;
3864         }
3865
3866         if (info->on) {
3867                 vsi->info.pvid = info->config.pvid;
3868                 /**
3869                  * If insert pvid is enabled, only tagged pkts are
3870                  * allowed to be sent out.
3871                  */
3872                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3873                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3874         } else {
3875                 vsi->info.pvid = 0;
3876                 if (info->config.reject.tagged == 0)
3877                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3878
3879                 if (info->config.reject.untagged == 0)
3880                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3881         }
3882         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3883                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3884         vsi->info.port_vlan_flags |= vlan_flags;
3885         vsi->info.valid_sections =
3886                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3887         memset(&ctxt, 0, sizeof(ctxt));
3888         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3889         ctxt.seid = vsi->seid;
3890
3891         hw = I40E_VSI_TO_HW(vsi);
3892         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3893         if (ret != I40E_SUCCESS)
3894                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3895
3896         return ret;
3897 }
3898
3899 static int
3900 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3901 {
3902         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3903         int i, ret;
3904         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3905
3906         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3907         if (ret != I40E_SUCCESS)
3908                 return ret;
3909
3910         if (!vsi->seid) {
3911                 PMD_DRV_LOG(ERR, "seid not valid");
3912                 return -EINVAL;
3913         }
3914
3915         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3916         tc_bw_data.tc_valid_bits = enabled_tcmap;
3917         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3918                 tc_bw_data.tc_bw_credits[i] =
3919                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3920
3921         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3922         if (ret != I40E_SUCCESS) {
3923                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3924                 return ret;
3925         }
3926
3927         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3928                                         sizeof(vsi->info.qs_handle));
3929         return I40E_SUCCESS;
3930 }
3931
3932 static enum i40e_status_code
3933 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3934                                  struct i40e_aqc_vsi_properties_data *info,
3935                                  uint8_t enabled_tcmap)
3936 {
3937         enum i40e_status_code ret;
3938         int i, total_tc = 0;
3939         uint16_t qpnum_per_tc, bsf, qp_idx;
3940
3941         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3942         if (ret != I40E_SUCCESS)
3943                 return ret;
3944
3945         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3946                 if (enabled_tcmap & (1 << i))
3947                         total_tc++;
3948         vsi->enabled_tc = enabled_tcmap;
3949
3950         /* Number of queues per enabled TC */
3951         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3952         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3953         bsf = rte_bsf32(qpnum_per_tc);
3954
3955         /* Adjust the queue number to actual queues that can be applied */
3956         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3957                 vsi->nb_qps = qpnum_per_tc * total_tc;
3958
3959         /**
3960          * Configure TC and queue mapping parameters, for enabled TC,
3961          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3962          * default queue will serve it.
3963          */
3964         qp_idx = 0;
3965         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3966                 if (vsi->enabled_tc & (1 << i)) {
3967                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3968                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3969                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3970                         qp_idx += qpnum_per_tc;
3971                 } else
3972                         info->tc_mapping[i] = 0;
3973         }
3974
3975         /* Associate queue number with VSI */
3976         if (vsi->type == I40E_VSI_SRIOV) {
3977                 info->mapping_flags |=
3978                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3979                 for (i = 0; i < vsi->nb_qps; i++)
3980                         info->queue_mapping[i] =
3981                                 rte_cpu_to_le_16(vsi->base_queue + i);
3982         } else {
3983                 info->mapping_flags |=
3984                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3985                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3986         }
3987         info->valid_sections |=
3988                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3989
3990         return I40E_SUCCESS;
3991 }
3992
3993 static int
3994 i40e_veb_release(struct i40e_veb *veb)
3995 {
3996         struct i40e_vsi *vsi;
3997         struct i40e_hw *hw;
3998
3999         if (veb == NULL)
4000                 return -EINVAL;
4001
4002         if (!TAILQ_EMPTY(&veb->head)) {
4003                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4004                 return -EACCES;
4005         }
4006         /* associate_vsi field is NULL for floating VEB */
4007         if (veb->associate_vsi != NULL) {
4008                 vsi = veb->associate_vsi;
4009                 hw = I40E_VSI_TO_HW(vsi);
4010
4011                 vsi->uplink_seid = veb->uplink_seid;
4012                 vsi->veb = NULL;
4013         } else {
4014                 veb->associate_pf->main_vsi->floating_veb = NULL;
4015                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4016         }
4017
4018         i40e_aq_delete_element(hw, veb->seid, NULL);
4019         rte_free(veb);
4020         return I40E_SUCCESS;
4021 }
4022
4023 /* Setup a veb */
4024 static struct i40e_veb *
4025 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4026 {
4027         struct i40e_veb *veb;
4028         int ret;
4029         struct i40e_hw *hw;
4030
4031         if (pf == NULL) {
4032                 PMD_DRV_LOG(ERR,
4033                             "veb setup failed, associated PF shouldn't null");
4034                 return NULL;
4035         }
4036         hw = I40E_PF_TO_HW(pf);
4037
4038         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4039         if (!veb) {
4040                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4041                 goto fail;
4042         }
4043
4044         veb->associate_vsi = vsi;
4045         veb->associate_pf = pf;
4046         TAILQ_INIT(&veb->head);
4047         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4048
4049         /* create floating veb if vsi is NULL */
4050         if (vsi != NULL) {
4051                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4052                                       I40E_DEFAULT_TCMAP, false,
4053                                       &veb->seid, false, NULL);
4054         } else {
4055                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4056                                       true, &veb->seid, false, NULL);
4057         }
4058
4059         if (ret != I40E_SUCCESS) {
4060                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4061                             hw->aq.asq_last_status);
4062                 goto fail;
4063         }
4064
4065         /* get statistics index */
4066         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4067                                 &veb->stats_idx, NULL, NULL, NULL);
4068         if (ret != I40E_SUCCESS) {
4069                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4070                             hw->aq.asq_last_status);
4071                 goto fail;
4072         }
4073         /* Get VEB bandwidth, to be implemented */
4074         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4075         if (vsi)
4076                 vsi->uplink_seid = veb->seid;
4077
4078         return veb;
4079 fail:
4080         rte_free(veb);
4081         return NULL;
4082 }
4083
4084 int
4085 i40e_vsi_release(struct i40e_vsi *vsi)
4086 {
4087         struct i40e_pf *pf;
4088         struct i40e_hw *hw;
4089         struct i40e_vsi_list *vsi_list;
4090         void *temp;
4091         int ret;
4092         struct i40e_mac_filter *f;
4093         uint16_t user_param = vsi->user_param;
4094
4095         if (!vsi)
4096                 return I40E_SUCCESS;
4097
4098         pf = I40E_VSI_TO_PF(vsi);
4099         hw = I40E_VSI_TO_HW(vsi);
4100
4101         /* VSI has child to attach, release child first */
4102         if (vsi->veb) {
4103                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4104                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4105                                 return -1;
4106                 }
4107                 i40e_veb_release(vsi->veb);
4108         }
4109
4110         if (vsi->floating_veb) {
4111                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4112                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4113                                 return -1;
4114                 }
4115         }
4116
4117         /* Remove all macvlan filters of the VSI */
4118         i40e_vsi_remove_all_macvlan_filter(vsi);
4119         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4120                 rte_free(f);
4121
4122         if (vsi->type != I40E_VSI_MAIN &&
4123             ((vsi->type != I40E_VSI_SRIOV) ||
4124             !pf->floating_veb_list[user_param])) {
4125                 /* Remove vsi from parent's sibling list */
4126                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4127                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4128                         return I40E_ERR_PARAM;
4129                 }
4130                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4131                                 &vsi->sib_vsi_list, list);
4132
4133                 /* Remove all switch element of the VSI */
4134                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4135                 if (ret != I40E_SUCCESS)
4136                         PMD_DRV_LOG(ERR, "Failed to delete element");
4137         }
4138
4139         if ((vsi->type == I40E_VSI_SRIOV) &&
4140             pf->floating_veb_list[user_param]) {
4141                 /* Remove vsi from parent's sibling list */
4142                 if (vsi->parent_vsi == NULL ||
4143                     vsi->parent_vsi->floating_veb == NULL) {
4144                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4145                         return I40E_ERR_PARAM;
4146                 }
4147                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4148                              &vsi->sib_vsi_list, list);
4149
4150                 /* Remove all switch element of the VSI */
4151                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4152                 if (ret != I40E_SUCCESS)
4153                         PMD_DRV_LOG(ERR, "Failed to delete element");
4154         }
4155
4156         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4157
4158         if (vsi->type != I40E_VSI_SRIOV)
4159                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4160         rte_free(vsi);
4161
4162         return I40E_SUCCESS;
4163 }
4164
4165 static int
4166 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4167 {
4168         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4169         struct i40e_aqc_remove_macvlan_element_data def_filter;
4170         struct i40e_mac_filter_info filter;
4171         int ret;
4172
4173         if (vsi->type != I40E_VSI_MAIN)
4174                 return I40E_ERR_CONFIG;
4175         memset(&def_filter, 0, sizeof(def_filter));
4176         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4177                                         ETH_ADDR_LEN);
4178         def_filter.vlan_tag = 0;
4179         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4180                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4181         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4182         if (ret != I40E_SUCCESS) {
4183                 struct i40e_mac_filter *f;
4184                 struct ether_addr *mac;
4185
4186                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4187                             "macvlan filter");
4188                 /* It needs to add the permanent mac into mac list */
4189                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4190                 if (f == NULL) {
4191                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4192                         return I40E_ERR_NO_MEMORY;
4193                 }
4194                 mac = &f->mac_info.mac_addr;
4195                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4196                                 ETH_ADDR_LEN);
4197                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4198                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4199                 vsi->mac_num++;
4200
4201                 return ret;
4202         }
4203         (void)rte_memcpy(&filter.mac_addr,
4204                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4205         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4206         return i40e_vsi_add_mac(vsi, &filter);
4207 }
4208
4209 /*
4210  * i40e_vsi_get_bw_config - Query VSI BW Information
4211  * @vsi: the VSI to be queried
4212  *
4213  * Returns 0 on success, negative value on failure
4214  */
4215 static enum i40e_status_code
4216 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4217 {
4218         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4219         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4220         struct i40e_hw *hw = &vsi->adapter->hw;
4221         i40e_status ret;
4222         int i;
4223         uint32_t bw_max;
4224
4225         memset(&bw_config, 0, sizeof(bw_config));
4226         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4227         if (ret != I40E_SUCCESS) {
4228                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4229                             hw->aq.asq_last_status);
4230                 return ret;
4231         }
4232
4233         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4234         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4235                                         &ets_sla_config, NULL);
4236         if (ret != I40E_SUCCESS) {
4237                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4238                             "configuration %u", hw->aq.asq_last_status);
4239                 return ret;
4240         }
4241
4242         /* store and print out BW info */
4243         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4244         vsi->bw_info.bw_max = bw_config.max_bw;
4245         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4246         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4247         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4248                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4249                      I40E_16_BIT_WIDTH);
4250         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4251                 vsi->bw_info.bw_ets_share_credits[i] =
4252                                 ets_sla_config.share_credits[i];
4253                 vsi->bw_info.bw_ets_credits[i] =
4254                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4255                 /* 4 bits per TC, 4th bit is reserved */
4256                 vsi->bw_info.bw_ets_max[i] =
4257                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4258                                   RTE_LEN2MASK(3, uint8_t));
4259                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4260                             vsi->bw_info.bw_ets_share_credits[i]);
4261                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4262                             vsi->bw_info.bw_ets_credits[i]);
4263                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4264                             vsi->bw_info.bw_ets_max[i]);
4265         }
4266
4267         return I40E_SUCCESS;
4268 }
4269
4270 /* i40e_enable_pf_lb
4271  * @pf: pointer to the pf structure
4272  *
4273  * allow loopback on pf
4274  */
4275 static inline void
4276 i40e_enable_pf_lb(struct i40e_pf *pf)
4277 {
4278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4279         struct i40e_vsi_context ctxt;
4280         int ret;
4281
4282         /* Use the FW API if FW >= v5.0 */
4283         if (hw->aq.fw_maj_ver < 5) {
4284                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4285                 return;
4286         }
4287
4288         memset(&ctxt, 0, sizeof(ctxt));
4289         ctxt.seid = pf->main_vsi_seid;
4290         ctxt.pf_num = hw->pf_id;
4291         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4292         if (ret) {
4293                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4294                             ret, hw->aq.asq_last_status);
4295                 return;
4296         }
4297         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4298         ctxt.info.valid_sections =
4299                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4300         ctxt.info.switch_id |=
4301                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4302
4303         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4304         if (ret)
4305                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4306                             hw->aq.asq_last_status);
4307 }
4308
4309 /* Setup a VSI */
4310 struct i40e_vsi *
4311 i40e_vsi_setup(struct i40e_pf *pf,
4312                enum i40e_vsi_type type,
4313                struct i40e_vsi *uplink_vsi,
4314                uint16_t user_param)
4315 {
4316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4317         struct i40e_vsi *vsi;
4318         struct i40e_mac_filter_info filter;
4319         int ret;
4320         struct i40e_vsi_context ctxt;
4321         struct ether_addr broadcast =
4322                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4323
4324         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4325             uplink_vsi == NULL) {
4326                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4327                             "VSI link shouldn't be NULL");
4328                 return NULL;
4329         }
4330
4331         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4332                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4333                             "uplink VSI should be NULL");
4334                 return NULL;
4335         }
4336
4337         /* two situations
4338          * 1.type is not MAIN and uplink vsi is not NULL
4339          * If uplink vsi didn't setup VEB, create one first under veb field
4340          * 2.type is SRIOV and the uplink is NULL
4341          * If floating VEB is NULL, create one veb under floating veb field
4342          */
4343
4344         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4345             uplink_vsi->veb == NULL) {
4346                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4347
4348                 if (uplink_vsi->veb == NULL) {
4349                         PMD_DRV_LOG(ERR, "VEB setup failed");
4350                         return NULL;
4351                 }
4352                 /* set ALLOWLOOPBACk on pf, when veb is created */
4353                 i40e_enable_pf_lb(pf);
4354         }
4355
4356         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4357             pf->main_vsi->floating_veb == NULL) {
4358                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4359
4360                 if (pf->main_vsi->floating_veb == NULL) {
4361                         PMD_DRV_LOG(ERR, "VEB setup failed");
4362                         return NULL;
4363                 }
4364         }
4365
4366         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4367         if (!vsi) {
4368                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4369                 return NULL;
4370         }
4371         TAILQ_INIT(&vsi->mac_list);
4372         vsi->type = type;
4373         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4374         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4375         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4376         vsi->user_param = user_param;
4377         /* Allocate queues */
4378         switch (vsi->type) {
4379         case I40E_VSI_MAIN  :
4380                 vsi->nb_qps = pf->lan_nb_qps;
4381                 break;
4382         case I40E_VSI_SRIOV :
4383                 vsi->nb_qps = pf->vf_nb_qps;
4384                 break;
4385         case I40E_VSI_VMDQ2:
4386                 vsi->nb_qps = pf->vmdq_nb_qps;
4387                 break;
4388         case I40E_VSI_FDIR:
4389                 vsi->nb_qps = pf->fdir_nb_qps;
4390                 break;
4391         default:
4392                 goto fail_mem;
4393         }
4394         /*
4395          * The filter status descriptor is reported in rx queue 0,
4396          * while the tx queue for fdir filter programming has no
4397          * such constraints, can be non-zero queues.
4398          * To simplify it, choose FDIR vsi use queue 0 pair.
4399          * To make sure it will use queue 0 pair, queue allocation
4400          * need be done before this function is called
4401          */
4402         if (type != I40E_VSI_FDIR) {
4403                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4404                         if (ret < 0) {
4405                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4406                                                 vsi->seid, ret);
4407                                 goto fail_mem;
4408                         }
4409                         vsi->base_queue = ret;
4410         } else
4411                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4412
4413         /* VF has MSIX interrupt in VF range, don't allocate here */
4414         if (type == I40E_VSI_MAIN) {
4415                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4416                                           RTE_MIN(vsi->nb_qps,
4417                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4418                 if (ret < 0) {
4419                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4420                                     vsi->seid, ret);
4421                         goto fail_queue_alloc;
4422                 }
4423                 vsi->msix_intr = ret;
4424                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4425         } else if (type != I40E_VSI_SRIOV) {
4426                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4427                 if (ret < 0) {
4428                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4429                         goto fail_queue_alloc;
4430                 }
4431                 vsi->msix_intr = ret;
4432                 vsi->nb_msix = 1;
4433         } else {
4434                 vsi->msix_intr = 0;
4435                 vsi->nb_msix = 0;
4436         }
4437
4438         /* Add VSI */
4439         if (type == I40E_VSI_MAIN) {
4440                 /* For main VSI, no need to add since it's default one */
4441                 vsi->uplink_seid = pf->mac_seid;
4442                 vsi->seid = pf->main_vsi_seid;
4443                 /* Bind queues with specific MSIX interrupt */
4444                 /**
4445                  * Needs 2 interrupt at least, one for misc cause which will
4446                  * enabled from OS side, Another for queues binding the
4447                  * interrupt from device side only.
4448                  */
4449
4450                 /* Get default VSI parameters from hardware */
4451                 memset(&ctxt, 0, sizeof(ctxt));
4452                 ctxt.seid = vsi->seid;
4453                 ctxt.pf_num = hw->pf_id;
4454                 ctxt.uplink_seid = vsi->uplink_seid;
4455                 ctxt.vf_num = 0;
4456                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4457                 if (ret != I40E_SUCCESS) {
4458                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4459                         goto fail_msix_alloc;
4460                 }
4461                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4462                         sizeof(struct i40e_aqc_vsi_properties_data));
4463                 vsi->vsi_id = ctxt.vsi_number;
4464                 vsi->info.valid_sections = 0;
4465
4466                 /* Configure tc, enabled TC0 only */
4467                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4468                         I40E_SUCCESS) {
4469                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4470                         goto fail_msix_alloc;
4471                 }
4472
4473                 /* TC, queue mapping */
4474                 memset(&ctxt, 0, sizeof(ctxt));
4475                 vsi->info.valid_sections |=
4476                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4477                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4478                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4479                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4480                         sizeof(struct i40e_aqc_vsi_properties_data));
4481                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4482                                                 I40E_DEFAULT_TCMAP);
4483                 if (ret != I40E_SUCCESS) {
4484                         PMD_DRV_LOG(ERR, "Failed to configure "
4485                                     "TC queue mapping");
4486                         goto fail_msix_alloc;
4487                 }
4488                 ctxt.seid = vsi->seid;
4489                 ctxt.pf_num = hw->pf_id;
4490                 ctxt.uplink_seid = vsi->uplink_seid;
4491                 ctxt.vf_num = 0;
4492
4493                 /* Update VSI parameters */
4494                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4495                 if (ret != I40E_SUCCESS) {
4496                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4497                         goto fail_msix_alloc;
4498                 }
4499
4500                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4501                                                 sizeof(vsi->info.tc_mapping));
4502                 (void)rte_memcpy(&vsi->info.queue_mapping,
4503                                 &ctxt.info.queue_mapping,
4504                         sizeof(vsi->info.queue_mapping));
4505                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4506                 vsi->info.valid_sections = 0;
4507
4508                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4509                                 ETH_ADDR_LEN);
4510
4511                 /**
4512                  * Updating default filter settings are necessary to prevent
4513                  * reception of tagged packets.
4514                  * Some old firmware configurations load a default macvlan
4515                  * filter which accepts both tagged and untagged packets.
4516                  * The updating is to use a normal filter instead if needed.
4517                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4518                  * The firmware with correct configurations load the default
4519                  * macvlan filter which is expected and cannot be removed.
4520                  */
4521                 i40e_update_default_filter_setting(vsi);
4522                 i40e_config_qinq(hw, vsi);
4523         } else if (type == I40E_VSI_SRIOV) {
4524                 memset(&ctxt, 0, sizeof(ctxt));
4525                 /**
4526                  * For other VSI, the uplink_seid equals to uplink VSI's
4527                  * uplink_seid since they share same VEB
4528                  */
4529                 if (uplink_vsi == NULL)
4530                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4531                 else
4532                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4533                 ctxt.pf_num = hw->pf_id;
4534                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4535                 ctxt.uplink_seid = vsi->uplink_seid;
4536                 ctxt.connection_type = 0x1;
4537                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4538
4539                 /* Use the VEB configuration if FW >= v5.0 */
4540                 if (hw->aq.fw_maj_ver >= 5) {
4541                         /* Configure switch ID */
4542                         ctxt.info.valid_sections |=
4543                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4544                         ctxt.info.switch_id =
4545                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4546                 }
4547
4548                 /* Configure port/vlan */
4549                 ctxt.info.valid_sections |=
4550                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4551                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4552                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4553                                                 I40E_DEFAULT_TCMAP);
4554                 if (ret != I40E_SUCCESS) {
4555                         PMD_DRV_LOG(ERR, "Failed to configure "
4556                                     "TC queue mapping");
4557                         goto fail_msix_alloc;
4558                 }
4559                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4560                 ctxt.info.valid_sections |=
4561                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4562                 /**
4563                  * Since VSI is not created yet, only configure parameter,
4564                  * will add vsi below.
4565                  */
4566
4567                 i40e_config_qinq(hw, vsi);
4568         } else if (type == I40E_VSI_VMDQ2) {
4569                 memset(&ctxt, 0, sizeof(ctxt));
4570                 /*
4571                  * For other VSI, the uplink_seid equals to uplink VSI's
4572                  * uplink_seid since they share same VEB
4573                  */
4574                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4575                 ctxt.pf_num = hw->pf_id;
4576                 ctxt.vf_num = 0;
4577                 ctxt.uplink_seid = vsi->uplink_seid;
4578                 ctxt.connection_type = 0x1;
4579                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4580
4581                 ctxt.info.valid_sections |=
4582                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4583                 /* user_param carries flag to enable loop back */
4584                 if (user_param) {
4585                         ctxt.info.switch_id =
4586                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4587                         ctxt.info.switch_id |=
4588                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4589                 }
4590
4591                 /* Configure port/vlan */
4592                 ctxt.info.valid_sections |=
4593                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4594                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4595                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4596                                                 I40E_DEFAULT_TCMAP);
4597                 if (ret != I40E_SUCCESS) {
4598                         PMD_DRV_LOG(ERR, "Failed to configure "
4599                                         "TC queue mapping");
4600                         goto fail_msix_alloc;
4601                 }
4602                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4603                 ctxt.info.valid_sections |=
4604                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4605         } else if (type == I40E_VSI_FDIR) {
4606                 memset(&ctxt, 0, sizeof(ctxt));
4607                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4608                 ctxt.pf_num = hw->pf_id;
4609                 ctxt.vf_num = 0;
4610                 ctxt.uplink_seid = vsi->uplink_seid;
4611                 ctxt.connection_type = 0x1;     /* regular data port */
4612                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4613                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4614                                                 I40E_DEFAULT_TCMAP);
4615                 if (ret != I40E_SUCCESS) {
4616                         PMD_DRV_LOG(ERR, "Failed to configure "
4617                                         "TC queue mapping.");
4618                         goto fail_msix_alloc;
4619                 }
4620                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4621                 ctxt.info.valid_sections |=
4622                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4623         } else {
4624                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4625                 goto fail_msix_alloc;
4626         }
4627
4628         if (vsi->type != I40E_VSI_MAIN) {
4629                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4630                 if (ret != I40E_SUCCESS) {
4631                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4632                                     hw->aq.asq_last_status);
4633                         goto fail_msix_alloc;
4634                 }
4635                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4636                 vsi->info.valid_sections = 0;
4637                 vsi->seid = ctxt.seid;
4638                 vsi->vsi_id = ctxt.vsi_number;
4639                 vsi->sib_vsi_list.vsi = vsi;
4640                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4641                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4642                                           &vsi->sib_vsi_list, list);
4643                 } else {
4644                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4645                                           &vsi->sib_vsi_list, list);
4646                 }
4647         }
4648
4649         /* MAC/VLAN configuration */
4650         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4651         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4652
4653         ret = i40e_vsi_add_mac(vsi, &filter);
4654         if (ret != I40E_SUCCESS) {
4655                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4656                 goto fail_msix_alloc;
4657         }
4658
4659         /* Get VSI BW information */
4660         i40e_vsi_get_bw_config(vsi);
4661         return vsi;
4662 fail_msix_alloc:
4663         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4664 fail_queue_alloc:
4665         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4666 fail_mem:
4667         rte_free(vsi);
4668         return NULL;
4669 }
4670
4671 /* Configure vlan filter on or off */
4672 int
4673 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4674 {
4675         int i, num;
4676         struct i40e_mac_filter *f;
4677         void *temp;
4678         struct i40e_mac_filter_info *mac_filter;
4679         enum rte_mac_filter_type desired_filter;
4680         int ret = I40E_SUCCESS;
4681
4682         if (on) {
4683                 /* Filter to match MAC and VLAN */
4684                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4685         } else {
4686                 /* Filter to match only MAC */
4687                 desired_filter = RTE_MAC_PERFECT_MATCH;
4688         }
4689
4690         num = vsi->mac_num;
4691
4692         mac_filter = rte_zmalloc("mac_filter_info_data",
4693                                  num * sizeof(*mac_filter), 0);
4694         if (mac_filter == NULL) {
4695                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4696                 return I40E_ERR_NO_MEMORY;
4697         }
4698
4699         i = 0;
4700
4701         /* Remove all existing mac */
4702         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4703                 mac_filter[i] = f->mac_info;
4704                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4705                 if (ret) {
4706                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4707                                     on ? "enable" : "disable");
4708                         goto DONE;
4709                 }
4710                 i++;
4711         }
4712
4713         /* Override with new filter */
4714         for (i = 0; i < num; i++) {
4715                 mac_filter[i].filter_type = desired_filter;
4716                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4717                 if (ret) {
4718                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4719                                     on ? "enable" : "disable");
4720                         goto DONE;
4721                 }
4722         }
4723
4724 DONE:
4725         rte_free(mac_filter);
4726         return ret;
4727 }
4728
4729 /* Configure vlan stripping on or off */
4730 int
4731 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4732 {
4733         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4734         struct i40e_vsi_context ctxt;
4735         uint8_t vlan_flags;
4736         int ret = I40E_SUCCESS;
4737
4738         /* Check if it has been already on or off */
4739         if (vsi->info.valid_sections &
4740                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4741                 if (on) {
4742                         if ((vsi->info.port_vlan_flags &
4743                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4744                                 return 0; /* already on */
4745                 } else {
4746                         if ((vsi->info.port_vlan_flags &
4747                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4748                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4749                                 return 0; /* already off */
4750                 }
4751         }
4752
4753         if (on)
4754                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4755         else
4756                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4757         vsi->info.valid_sections =
4758                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4759         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4760         vsi->info.port_vlan_flags |= vlan_flags;
4761         ctxt.seid = vsi->seid;
4762         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4763         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4764         if (ret)
4765                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4766                             on ? "enable" : "disable");
4767
4768         return ret;
4769 }
4770
4771 static int
4772 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4773 {
4774         struct rte_eth_dev_data *data = dev->data;
4775         int ret;
4776         int mask = 0;
4777
4778         /* Apply vlan offload setting */
4779         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4780         i40e_vlan_offload_set(dev, mask);
4781
4782         /* Apply double-vlan setting, not implemented yet */
4783
4784         /* Apply pvid setting */
4785         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4786                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4787         if (ret)
4788                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4789
4790         return ret;
4791 }
4792
4793 static int
4794 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4795 {
4796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4797
4798         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4799 }
4800
4801 static int
4802 i40e_update_flow_control(struct i40e_hw *hw)
4803 {
4804 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4805         struct i40e_link_status link_status;
4806         uint32_t rxfc = 0, txfc = 0, reg;
4807         uint8_t an_info;
4808         int ret;
4809
4810         memset(&link_status, 0, sizeof(link_status));
4811         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4812         if (ret != I40E_SUCCESS) {
4813                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4814                 goto write_reg; /* Disable flow control */
4815         }
4816
4817         an_info = hw->phy.link_info.an_info;
4818         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4819                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4820                 ret = I40E_ERR_NOT_READY;
4821                 goto write_reg; /* Disable flow control */
4822         }
4823         /**
4824          * If link auto negotiation is enabled, flow control needs to
4825          * be configured according to it
4826          */
4827         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4828         case I40E_LINK_PAUSE_RXTX:
4829                 rxfc = 1;
4830                 txfc = 1;
4831                 hw->fc.current_mode = I40E_FC_FULL;
4832                 break;
4833         case I40E_AQ_LINK_PAUSE_RX:
4834                 rxfc = 1;
4835                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4836                 break;
4837         case I40E_AQ_LINK_PAUSE_TX:
4838                 txfc = 1;
4839                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4840                 break;
4841         default:
4842                 hw->fc.current_mode = I40E_FC_NONE;
4843                 break;
4844         }
4845
4846 write_reg:
4847         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4848                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4849         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4850         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4851         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4852         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4853
4854         return ret;
4855 }
4856
4857 /* PF setup */
4858 static int
4859 i40e_pf_setup(struct i40e_pf *pf)
4860 {
4861         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4862         struct i40e_filter_control_settings settings;
4863         struct i40e_vsi *vsi;
4864         int ret;
4865
4866         /* Clear all stats counters */
4867         pf->offset_loaded = FALSE;
4868         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4869         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4870
4871         ret = i40e_pf_get_switch_config(pf);
4872         if (ret != I40E_SUCCESS) {
4873                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4874                 return ret;
4875         }
4876         if (pf->flags & I40E_FLAG_FDIR) {
4877                 /* make queue allocated first, let FDIR use queue pair 0*/
4878                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4879                 if (ret != I40E_FDIR_QUEUE_ID) {
4880                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4881                                     " ret =%d", ret);
4882                         pf->flags &= ~I40E_FLAG_FDIR;
4883                 }
4884         }
4885         /*  main VSI setup */
4886         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4887         if (!vsi) {
4888                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4889                 return I40E_ERR_NOT_READY;
4890         }
4891         pf->main_vsi = vsi;
4892
4893         /* Configure filter control */
4894         memset(&settings, 0, sizeof(settings));
4895         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4896                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4897         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4898                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4899         else {
4900                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4901                                                 hw->func_caps.rss_table_size);
4902                 return I40E_ERR_PARAM;
4903         }
4904         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4905                         "size: %u\n", hw->func_caps.rss_table_size);
4906         pf->hash_lut_size = hw->func_caps.rss_table_size;
4907
4908         /* Enable ethtype and macvlan filters */
4909         settings.enable_ethtype = TRUE;
4910         settings.enable_macvlan = TRUE;
4911         ret = i40e_set_filter_control(hw, &settings);
4912         if (ret)
4913                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4914                                                                 ret);
4915
4916         /* Update flow control according to the auto negotiation */
4917         i40e_update_flow_control(hw);
4918
4919         return I40E_SUCCESS;
4920 }
4921
4922 int
4923 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4924 {
4925         uint32_t reg;
4926         uint16_t j;
4927
4928         /**
4929          * Set or clear TX Queue Disable flags,
4930          * which is required by hardware.
4931          */
4932         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4933         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4934
4935         /* Wait until the request is finished */
4936         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4937                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4938                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4939                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4940                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4941                                                         & 0x1))) {
4942                         break;
4943                 }
4944         }
4945         if (on) {
4946                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4947                         return I40E_SUCCESS; /* already on, skip next steps */
4948
4949                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4950                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4951         } else {
4952                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4953                         return I40E_SUCCESS; /* already off, skip next steps */
4954                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4955         }
4956         /* Write the register */
4957         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4958         /* Check the result */
4959         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4960                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4961                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4962                 if (on) {
4963                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4964                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4965                                 break;
4966                 } else {
4967                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4968                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4969                                 break;
4970                 }
4971         }
4972         /* Check if it is timeout */
4973         if (j >= I40E_CHK_Q_ENA_COUNT) {
4974                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4975                             (on ? "enable" : "disable"), q_idx);
4976                 return I40E_ERR_TIMEOUT;
4977         }
4978
4979         return I40E_SUCCESS;
4980 }
4981
4982 /* Swith on or off the tx queues */
4983 static int
4984 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4985 {
4986         struct rte_eth_dev_data *dev_data = pf->dev_data;
4987         struct i40e_tx_queue *txq;
4988         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4989         uint16_t i;
4990         int ret;
4991
4992         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4993                 txq = dev_data->tx_queues[i];
4994                 /* Don't operate the queue if not configured or
4995                  * if starting only per queue */
4996                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4997                         continue;
4998                 if (on)
4999                         ret = i40e_dev_tx_queue_start(dev, i);
5000                 else
5001                         ret = i40e_dev_tx_queue_stop(dev, i);
5002                 if ( ret != I40E_SUCCESS)
5003                         return ret;
5004         }
5005
5006         return I40E_SUCCESS;
5007 }
5008
5009 int
5010 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5011 {
5012         uint32_t reg;
5013         uint16_t j;
5014
5015         /* Wait until the request is finished */
5016         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5017                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5018                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5019                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5020                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5021                         break;
5022         }
5023
5024         if (on) {
5025                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5026                         return I40E_SUCCESS; /* Already on, skip next steps */
5027                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5028         } else {
5029                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5030                         return I40E_SUCCESS; /* Already off, skip next steps */
5031                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5032         }
5033
5034         /* Write the register */
5035         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5036         /* Check the result */
5037         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5038                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5039                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5040                 if (on) {
5041                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5042                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5043                                 break;
5044                 } else {
5045                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5046                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5047                                 break;
5048                 }
5049         }
5050
5051         /* Check if it is timeout */
5052         if (j >= I40E_CHK_Q_ENA_COUNT) {
5053                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5054                             (on ? "enable" : "disable"), q_idx);
5055                 return I40E_ERR_TIMEOUT;
5056         }
5057
5058         return I40E_SUCCESS;
5059 }
5060 /* Switch on or off the rx queues */
5061 static int
5062 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5063 {
5064         struct rte_eth_dev_data *dev_data = pf->dev_data;
5065         struct i40e_rx_queue *rxq;
5066         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5067         uint16_t i;
5068         int ret;
5069
5070         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5071                 rxq = dev_data->rx_queues[i];
5072                 /* Don't operate the queue if not configured or
5073                  * if starting only per queue */
5074                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5075                         continue;
5076                 if (on)
5077                         ret = i40e_dev_rx_queue_start(dev, i);
5078                 else
5079                         ret = i40e_dev_rx_queue_stop(dev, i);
5080                 if (ret != I40E_SUCCESS)
5081                         return ret;
5082         }
5083
5084         return I40E_SUCCESS;
5085 }
5086
5087 /* Switch on or off all the rx/tx queues */
5088 int
5089 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5090 {
5091         int ret;
5092
5093         if (on) {
5094                 /* enable rx queues before enabling tx queues */
5095                 ret = i40e_dev_switch_rx_queues(pf, on);
5096                 if (ret) {
5097                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5098                         return ret;
5099                 }
5100                 ret = i40e_dev_switch_tx_queues(pf, on);
5101         } else {
5102                 /* Stop tx queues before stopping rx queues */
5103                 ret = i40e_dev_switch_tx_queues(pf, on);
5104                 if (ret) {
5105                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5106                         return ret;
5107                 }
5108                 ret = i40e_dev_switch_rx_queues(pf, on);
5109         }
5110
5111         return ret;
5112 }
5113
5114 /* Initialize VSI for TX */
5115 static int
5116 i40e_dev_tx_init(struct i40e_pf *pf)
5117 {
5118         struct rte_eth_dev_data *data = pf->dev_data;
5119         uint16_t i;
5120         uint32_t ret = I40E_SUCCESS;
5121         struct i40e_tx_queue *txq;
5122
5123         for (i = 0; i < data->nb_tx_queues; i++) {
5124                 txq = data->tx_queues[i];
5125                 if (!txq || !txq->q_set)
5126                         continue;
5127                 ret = i40e_tx_queue_init(txq);
5128                 if (ret != I40E_SUCCESS)
5129                         break;
5130         }
5131         if (ret == I40E_SUCCESS)
5132                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5133                                      ->eth_dev);
5134
5135         return ret;
5136 }
5137
5138 /* Initialize VSI for RX */
5139 static int
5140 i40e_dev_rx_init(struct i40e_pf *pf)
5141 {
5142         struct rte_eth_dev_data *data = pf->dev_data;
5143         int ret = I40E_SUCCESS;
5144         uint16_t i;
5145         struct i40e_rx_queue *rxq;
5146
5147         i40e_pf_config_mq_rx(pf);
5148         for (i = 0; i < data->nb_rx_queues; i++) {
5149                 rxq = data->rx_queues[i];
5150                 if (!rxq || !rxq->q_set)
5151                         continue;
5152
5153                 ret = i40e_rx_queue_init(rxq);
5154                 if (ret != I40E_SUCCESS) {
5155                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5156                                     "initialization");
5157                         break;
5158                 }
5159         }
5160         if (ret == I40E_SUCCESS)
5161                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5162                                      ->eth_dev);
5163
5164         return ret;
5165 }
5166
5167 static int
5168 i40e_dev_rxtx_init(struct i40e_pf *pf)
5169 {
5170         int err;
5171
5172         err = i40e_dev_tx_init(pf);
5173         if (err) {
5174                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5175                 return err;
5176         }
5177         err = i40e_dev_rx_init(pf);
5178         if (err) {
5179                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5180                 return err;
5181         }
5182
5183         return err;
5184 }
5185
5186 static int
5187 i40e_vmdq_setup(struct rte_eth_dev *dev)
5188 {
5189         struct rte_eth_conf *conf = &dev->data->dev_conf;
5190         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5191         int i, err, conf_vsis, j, loop;
5192         struct i40e_vsi *vsi;
5193         struct i40e_vmdq_info *vmdq_info;
5194         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5195         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5196
5197         /*
5198          * Disable interrupt to avoid message from VF. Furthermore, it will
5199          * avoid race condition in VSI creation/destroy.
5200          */
5201         i40e_pf_disable_irq0(hw);
5202
5203         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5204                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5205                 return -ENOTSUP;
5206         }
5207
5208         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5209         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5210                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5211                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5212                         pf->max_nb_vmdq_vsi);
5213                 return -ENOTSUP;
5214         }
5215
5216         if (pf->vmdq != NULL) {
5217                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5218                 return 0;
5219         }
5220
5221         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5222                                 sizeof(*vmdq_info) * conf_vsis, 0);
5223
5224         if (pf->vmdq == NULL) {
5225                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5226                 return -ENOMEM;
5227         }
5228
5229         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5230
5231         /* Create VMDQ VSI */
5232         for (i = 0; i < conf_vsis; i++) {
5233                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5234                                 vmdq_conf->enable_loop_back);
5235                 if (vsi == NULL) {
5236                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5237                         err = -1;
5238                         goto err_vsi_setup;
5239                 }
5240                 vmdq_info = &pf->vmdq[i];
5241                 vmdq_info->pf = pf;
5242                 vmdq_info->vsi = vsi;
5243         }
5244         pf->nb_cfg_vmdq_vsi = conf_vsis;
5245
5246         /* Configure Vlan */
5247         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5248         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5249                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5250                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5251                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5252                                         vmdq_conf->pool_map[i].vlan_id, j);
5253
5254                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5255                                                 vmdq_conf->pool_map[i].vlan_id);
5256                                 if (err) {
5257                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5258                                         err = -1;
5259                                         goto err_vsi_setup;
5260                                 }
5261                         }
5262                 }
5263         }
5264
5265         i40e_pf_enable_irq0(hw);
5266
5267         return 0;
5268
5269 err_vsi_setup:
5270         for (i = 0; i < conf_vsis; i++)
5271                 if (pf->vmdq[i].vsi == NULL)
5272                         break;
5273                 else
5274                         i40e_vsi_release(pf->vmdq[i].vsi);
5275
5276         rte_free(pf->vmdq);
5277         pf->vmdq = NULL;
5278         i40e_pf_enable_irq0(hw);
5279         return err;
5280 }
5281
5282 static void
5283 i40e_stat_update_32(struct i40e_hw *hw,
5284                    uint32_t reg,
5285                    bool offset_loaded,
5286                    uint64_t *offset,
5287                    uint64_t *stat)
5288 {
5289         uint64_t new_data;
5290
5291         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5292         if (!offset_loaded)
5293                 *offset = new_data;
5294
5295         if (new_data >= *offset)
5296                 *stat = (uint64_t)(new_data - *offset);
5297         else
5298                 *stat = (uint64_t)((new_data +
5299                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5300 }
5301
5302 static void
5303 i40e_stat_update_48(struct i40e_hw *hw,
5304                    uint32_t hireg,
5305                    uint32_t loreg,
5306                    bool offset_loaded,
5307                    uint64_t *offset,
5308                    uint64_t *stat)
5309 {
5310         uint64_t new_data;
5311
5312         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5313         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5314                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5315
5316         if (!offset_loaded)
5317                 *offset = new_data;
5318
5319         if (new_data >= *offset)
5320                 *stat = new_data - *offset;
5321         else
5322                 *stat = (uint64_t)((new_data +
5323                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5324
5325         *stat &= I40E_48_BIT_MASK;
5326 }
5327
5328 /* Disable IRQ0 */
5329 void
5330 i40e_pf_disable_irq0(struct i40e_hw *hw)
5331 {
5332         /* Disable all interrupt types */
5333         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5334         I40E_WRITE_FLUSH(hw);
5335 }
5336
5337 /* Enable IRQ0 */
5338 void
5339 i40e_pf_enable_irq0(struct i40e_hw *hw)
5340 {
5341         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5342                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5343                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5344                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5345         I40E_WRITE_FLUSH(hw);
5346 }
5347
5348 static void
5349 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5350 {
5351         /* read pending request and disable first */
5352         i40e_pf_disable_irq0(hw);
5353         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5354         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5355                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5356
5357         if (no_queue)
5358                 /* Link no queues with irq0 */
5359                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5360                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5361 }
5362
5363 static void
5364 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5365 {
5366         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5368         int i;
5369         uint16_t abs_vf_id;
5370         uint32_t index, offset, val;
5371
5372         if (!pf->vfs)
5373                 return;
5374         /**
5375          * Try to find which VF trigger a reset, use absolute VF id to access
5376          * since the reg is global register.
5377          */
5378         for (i = 0; i < pf->vf_num; i++) {
5379                 abs_vf_id = hw->func_caps.vf_base_id + i;
5380                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5381                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5382                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5383                 /* VFR event occured */
5384                 if (val & (0x1 << offset)) {
5385                         int ret;
5386
5387                         /* Clear the event first */
5388                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5389                                                         (0x1 << offset));
5390                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5391                         /**
5392                          * Only notify a VF reset event occured,
5393                          * don't trigger another SW reset
5394                          */
5395                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5396                         if (ret != I40E_SUCCESS)
5397                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5398                 }
5399         }
5400 }
5401
5402 static void
5403 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5404 {
5405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         struct i40e_arq_event_info info;
5407         uint16_t pending, opcode;
5408         int ret;
5409
5410         info.buf_len = I40E_AQ_BUF_SZ;
5411         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5412         if (!info.msg_buf) {
5413                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5414                 return;
5415         }
5416
5417         pending = 1;
5418         while (pending) {
5419                 ret = i40e_clean_arq_element(hw, &info, &pending);
5420
5421                 if (ret != I40E_SUCCESS) {
5422                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5423                                     "aq_err: %u", hw->aq.asq_last_status);
5424                         break;
5425                 }
5426                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5427
5428                 switch (opcode) {
5429                 case i40e_aqc_opc_send_msg_to_pf:
5430                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5431                         i40e_pf_host_handle_vf_msg(dev,
5432                                         rte_le_to_cpu_16(info.desc.retval),
5433                                         rte_le_to_cpu_32(info.desc.cookie_high),
5434                                         rte_le_to_cpu_32(info.desc.cookie_low),
5435                                         info.msg_buf,
5436                                         info.msg_len);
5437                         break;
5438                 default:
5439                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5440                                     opcode);
5441                         break;
5442                 }
5443         }
5444         rte_free(info.msg_buf);
5445 }
5446
5447 /*
5448  * Interrupt handler is registered as the alarm callback for handling LSC
5449  * interrupt in a definite of time, in order to wait the NIC into a stable
5450  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5451  * no need for link down interrupt.
5452  */
5453 static void
5454 i40e_dev_interrupt_delayed_handler(void *param)
5455 {
5456         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5457         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458         uint32_t icr0;
5459
5460         /* read interrupt causes again */
5461         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5462
5463 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5464         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5465                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5466         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5467                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5468         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5469                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5470         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5471                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5472         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5473                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5474                                                                 "state\n");
5475         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5476                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5477         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5478                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5479 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5480
5481         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5482                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5483                 i40e_dev_handle_vfr_event(dev);
5484         }
5485         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5486                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5487                 i40e_dev_handle_aq_msg(dev);
5488         }
5489
5490         /* handle the link up interrupt in an alarm callback */
5491         i40e_dev_link_update(dev, 0);
5492         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5493
5494         i40e_pf_enable_irq0(hw);
5495         rte_intr_enable(&(dev->pci_dev->intr_handle));
5496 }
5497
5498 /**
5499  * Interrupt handler triggered by NIC  for handling
5500  * specific interrupt.
5501  *
5502  * @param handle
5503  *  Pointer to interrupt handle.
5504  * @param param
5505  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5506  *
5507  * @return
5508  *  void
5509  */
5510 static void
5511 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5512                            void *param)
5513 {
5514         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516         uint32_t icr0;
5517
5518         /* Disable interrupt */
5519         i40e_pf_disable_irq0(hw);
5520
5521         /* read out interrupt causes */
5522         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5523
5524         /* No interrupt event indicated */
5525         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5526                 PMD_DRV_LOG(INFO, "No interrupt event");
5527                 goto done;
5528         }
5529 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5530         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5531                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5532         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5533                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5534         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5535                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5536         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5537                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5538         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5539                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5540         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5541                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5542         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5543                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5544 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5545
5546         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5547                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5548                 i40e_dev_handle_vfr_event(dev);
5549         }
5550         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5551                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5552                 i40e_dev_handle_aq_msg(dev);
5553         }
5554
5555         /* Link Status Change interrupt */
5556         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5557 #define I40E_US_PER_SECOND 1000000
5558                 struct rte_eth_link link;
5559
5560                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5561                 memset(&link, 0, sizeof(link));
5562                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5563                 i40e_dev_link_update(dev, 0);
5564
5565                 /*
5566                  * For link up interrupt, it needs to wait 1 second to let the
5567                  * hardware be a stable state. Otherwise several consecutive
5568                  * interrupts can be observed.
5569                  * For link down interrupt, no need to wait.
5570                  */
5571                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5572                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5573                         return;
5574                 else
5575                         _rte_eth_dev_callback_process(dev,
5576                                 RTE_ETH_EVENT_INTR_LSC);
5577         }
5578
5579 done:
5580         /* Enable interrupt */
5581         i40e_pf_enable_irq0(hw);
5582         rte_intr_enable(&(dev->pci_dev->intr_handle));
5583 }
5584
5585 static int
5586 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5587                          struct i40e_macvlan_filter *filter,
5588                          int total)
5589 {
5590         int ele_num, ele_buff_size;
5591         int num, actual_num, i;
5592         uint16_t flags;
5593         int ret = I40E_SUCCESS;
5594         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5595         struct i40e_aqc_add_macvlan_element_data *req_list;
5596
5597         if (filter == NULL  || total == 0)
5598                 return I40E_ERR_PARAM;
5599         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5600         ele_buff_size = hw->aq.asq_buf_size;
5601
5602         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5603         if (req_list == NULL) {
5604                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5605                 return I40E_ERR_NO_MEMORY;
5606         }
5607
5608         num = 0;
5609         do {
5610                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5611                 memset(req_list, 0, ele_buff_size);
5612
5613                 for (i = 0; i < actual_num; i++) {
5614                         (void)rte_memcpy(req_list[i].mac_addr,
5615                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5616                         req_list[i].vlan_tag =
5617                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5618
5619                         switch (filter[num + i].filter_type) {
5620                         case RTE_MAC_PERFECT_MATCH:
5621                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5622                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5623                                 break;
5624                         case RTE_MACVLAN_PERFECT_MATCH:
5625                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5626                                 break;
5627                         case RTE_MAC_HASH_MATCH:
5628                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5629                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5630                                 break;
5631                         case RTE_MACVLAN_HASH_MATCH:
5632                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5633                                 break;
5634                         default:
5635                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5636                                 ret = I40E_ERR_PARAM;
5637                                 goto DONE;
5638                         }
5639
5640                         req_list[i].queue_number = 0;
5641
5642                         req_list[i].flags = rte_cpu_to_le_16(flags);
5643                 }
5644
5645                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5646                                                 actual_num, NULL);
5647                 if (ret != I40E_SUCCESS) {
5648                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5649                         goto DONE;
5650                 }
5651                 num += actual_num;
5652         } while (num < total);
5653
5654 DONE:
5655         rte_free(req_list);
5656         return ret;
5657 }
5658
5659 static int
5660 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5661                             struct i40e_macvlan_filter *filter,
5662                             int total)
5663 {
5664         int ele_num, ele_buff_size;
5665         int num, actual_num, i;
5666         uint16_t flags;
5667         int ret = I40E_SUCCESS;
5668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5669         struct i40e_aqc_remove_macvlan_element_data *req_list;
5670
5671         if (filter == NULL  || total == 0)
5672                 return I40E_ERR_PARAM;
5673
5674         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5675         ele_buff_size = hw->aq.asq_buf_size;
5676
5677         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5678         if (req_list == NULL) {
5679                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5680                 return I40E_ERR_NO_MEMORY;
5681         }
5682
5683         num = 0;
5684         do {
5685                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5686                 memset(req_list, 0, ele_buff_size);
5687
5688                 for (i = 0; i < actual_num; i++) {
5689                         (void)rte_memcpy(req_list[i].mac_addr,
5690                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5691                         req_list[i].vlan_tag =
5692                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5693
5694                         switch (filter[num + i].filter_type) {
5695                         case RTE_MAC_PERFECT_MATCH:
5696                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5697                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5698                                 break;
5699                         case RTE_MACVLAN_PERFECT_MATCH:
5700                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5701                                 break;
5702                         case RTE_MAC_HASH_MATCH:
5703                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5704                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5705                                 break;
5706                         case RTE_MACVLAN_HASH_MATCH:
5707                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5708                                 break;
5709                         default:
5710                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5711                                 ret = I40E_ERR_PARAM;
5712                                 goto DONE;
5713                         }
5714                         req_list[i].flags = rte_cpu_to_le_16(flags);
5715                 }
5716
5717                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5718                                                 actual_num, NULL);
5719                 if (ret != I40E_SUCCESS) {
5720                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5721                         goto DONE;
5722                 }
5723                 num += actual_num;
5724         } while (num < total);
5725
5726 DONE:
5727         rte_free(req_list);
5728         return ret;
5729 }
5730
5731 /* Find out specific MAC filter */
5732 static struct i40e_mac_filter *
5733 i40e_find_mac_filter(struct i40e_vsi *vsi,
5734                          struct ether_addr *macaddr)
5735 {
5736         struct i40e_mac_filter *f;
5737
5738         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5739                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5740                         return f;
5741         }
5742
5743         return NULL;
5744 }
5745
5746 static bool
5747 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5748                          uint16_t vlan_id)
5749 {
5750         uint32_t vid_idx, vid_bit;
5751
5752         if (vlan_id > ETH_VLAN_ID_MAX)
5753                 return 0;
5754
5755         vid_idx = I40E_VFTA_IDX(vlan_id);
5756         vid_bit = I40E_VFTA_BIT(vlan_id);
5757
5758         if (vsi->vfta[vid_idx] & vid_bit)
5759                 return 1;
5760         else
5761                 return 0;
5762 }
5763
5764 static void
5765 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5766                          uint16_t vlan_id, bool on)
5767 {
5768         uint32_t vid_idx, vid_bit;
5769
5770         if (vlan_id > ETH_VLAN_ID_MAX)
5771                 return;
5772
5773         vid_idx = I40E_VFTA_IDX(vlan_id);
5774         vid_bit = I40E_VFTA_BIT(vlan_id);
5775
5776         if (on)
5777                 vsi->vfta[vid_idx] |= vid_bit;
5778         else
5779                 vsi->vfta[vid_idx] &= ~vid_bit;
5780 }
5781
5782 /**
5783  * Find all vlan options for specific mac addr,
5784  * return with actual vlan found.
5785  */
5786 static inline int
5787 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5788                            struct i40e_macvlan_filter *mv_f,
5789                            int num, struct ether_addr *addr)
5790 {
5791         int i;
5792         uint32_t j, k;
5793
5794         /**
5795          * Not to use i40e_find_vlan_filter to decrease the loop time,
5796          * although the code looks complex.
5797           */
5798         if (num < vsi->vlan_num)
5799                 return I40E_ERR_PARAM;
5800
5801         i = 0;
5802         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5803                 if (vsi->vfta[j]) {
5804                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5805                                 if (vsi->vfta[j] & (1 << k)) {
5806                                         if (i > num - 1) {
5807                                                 PMD_DRV_LOG(ERR, "vlan number "
5808                                                             "not match");
5809                                                 return I40E_ERR_PARAM;
5810                                         }
5811                                         (void)rte_memcpy(&mv_f[i].macaddr,
5812                                                         addr, ETH_ADDR_LEN);
5813                                         mv_f[i].vlan_id =
5814                                                 j * I40E_UINT32_BIT_SIZE + k;
5815                                         i++;
5816                                 }
5817                         }
5818                 }
5819         }
5820         return I40E_SUCCESS;
5821 }
5822
5823 static inline int
5824 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5825                            struct i40e_macvlan_filter *mv_f,
5826                            int num,
5827                            uint16_t vlan)
5828 {
5829         int i = 0;
5830         struct i40e_mac_filter *f;
5831
5832         if (num < vsi->mac_num)
5833                 return I40E_ERR_PARAM;
5834
5835         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5836                 if (i > num - 1) {
5837                         PMD_DRV_LOG(ERR, "buffer number not match");
5838                         return I40E_ERR_PARAM;
5839                 }
5840                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5841                                 ETH_ADDR_LEN);
5842                 mv_f[i].vlan_id = vlan;
5843                 mv_f[i].filter_type = f->mac_info.filter_type;
5844                 i++;
5845         }
5846
5847         return I40E_SUCCESS;
5848 }
5849
5850 static int
5851 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5852 {
5853         int i, num;
5854         struct i40e_mac_filter *f;
5855         struct i40e_macvlan_filter *mv_f;
5856         int ret = I40E_SUCCESS;
5857
5858         if (vsi == NULL || vsi->mac_num == 0)
5859                 return I40E_ERR_PARAM;
5860
5861         /* Case that no vlan is set */
5862         if (vsi->vlan_num == 0)
5863                 num = vsi->mac_num;
5864         else
5865                 num = vsi->mac_num * vsi->vlan_num;
5866
5867         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5868         if (mv_f == NULL) {
5869                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5870                 return I40E_ERR_NO_MEMORY;
5871         }
5872
5873         i = 0;
5874         if (vsi->vlan_num == 0) {
5875                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5876                         (void)rte_memcpy(&mv_f[i].macaddr,
5877                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5878                         mv_f[i].vlan_id = 0;
5879                         i++;
5880                 }
5881         } else {
5882                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5883                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5884                                         vsi->vlan_num, &f->mac_info.mac_addr);
5885                         if (ret != I40E_SUCCESS)
5886                                 goto DONE;
5887                         i += vsi->vlan_num;
5888                 }
5889         }
5890
5891         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5892 DONE:
5893         rte_free(mv_f);
5894
5895         return ret;
5896 }
5897
5898 int
5899 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5900 {
5901         struct i40e_macvlan_filter *mv_f;
5902         int mac_num;
5903         int ret = I40E_SUCCESS;
5904
5905         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5906                 return I40E_ERR_PARAM;
5907
5908         /* If it's already set, just return */
5909         if (i40e_find_vlan_filter(vsi,vlan))
5910                 return I40E_SUCCESS;
5911
5912         mac_num = vsi->mac_num;
5913
5914         if (mac_num == 0) {
5915                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5916                 return I40E_ERR_PARAM;
5917         }
5918
5919         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5920
5921         if (mv_f == NULL) {
5922                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5923                 return I40E_ERR_NO_MEMORY;
5924         }
5925
5926         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5927
5928         if (ret != I40E_SUCCESS)
5929                 goto DONE;
5930
5931         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5932
5933         if (ret != I40E_SUCCESS)
5934                 goto DONE;
5935
5936         i40e_set_vlan_filter(vsi, vlan, 1);
5937
5938         vsi->vlan_num++;
5939         ret = I40E_SUCCESS;
5940 DONE:
5941         rte_free(mv_f);
5942         return ret;
5943 }
5944
5945 int
5946 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5947 {
5948         struct i40e_macvlan_filter *mv_f;
5949         int mac_num;
5950         int ret = I40E_SUCCESS;
5951
5952         /**
5953          * Vlan 0 is the generic filter for untagged packets
5954          * and can't be removed.
5955          */
5956         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5957                 return I40E_ERR_PARAM;
5958
5959         /* If can't find it, just return */
5960         if (!i40e_find_vlan_filter(vsi, vlan))
5961                 return I40E_ERR_PARAM;
5962
5963         mac_num = vsi->mac_num;
5964
5965         if (mac_num == 0) {
5966                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5967                 return I40E_ERR_PARAM;
5968         }
5969
5970         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5971
5972         if (mv_f == NULL) {
5973                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5974                 return I40E_ERR_NO_MEMORY;
5975         }
5976
5977         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5978
5979         if (ret != I40E_SUCCESS)
5980                 goto DONE;
5981
5982         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5983
5984         if (ret != I40E_SUCCESS)
5985                 goto DONE;
5986
5987         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5988         if (vsi->vlan_num == 1) {
5989                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5990                 if (ret != I40E_SUCCESS)
5991                         goto DONE;
5992
5993                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5994                 if (ret != I40E_SUCCESS)
5995                         goto DONE;
5996         }
5997
5998         i40e_set_vlan_filter(vsi, vlan, 0);
5999
6000         vsi->vlan_num--;
6001         ret = I40E_SUCCESS;
6002 DONE:
6003         rte_free(mv_f);
6004         return ret;
6005 }
6006
6007 int
6008 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6009 {
6010         struct i40e_mac_filter *f;
6011         struct i40e_macvlan_filter *mv_f;
6012         int i, vlan_num = 0;
6013         int ret = I40E_SUCCESS;
6014
6015         /* If it's add and we've config it, return */
6016         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6017         if (f != NULL)
6018                 return I40E_SUCCESS;
6019         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6020                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6021
6022                 /**
6023                  * If vlan_num is 0, that's the first time to add mac,
6024                  * set mask for vlan_id 0.
6025                  */
6026                 if (vsi->vlan_num == 0) {
6027                         i40e_set_vlan_filter(vsi, 0, 1);
6028                         vsi->vlan_num = 1;
6029                 }
6030                 vlan_num = vsi->vlan_num;
6031         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6032                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6033                 vlan_num = 1;
6034
6035         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6036         if (mv_f == NULL) {
6037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6038                 return I40E_ERR_NO_MEMORY;
6039         }
6040
6041         for (i = 0; i < vlan_num; i++) {
6042                 mv_f[i].filter_type = mac_filter->filter_type;
6043                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6044                                 ETH_ADDR_LEN);
6045         }
6046
6047         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6048                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6049                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6050                                         &mac_filter->mac_addr);
6051                 if (ret != I40E_SUCCESS)
6052                         goto DONE;
6053         }
6054
6055         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6056         if (ret != I40E_SUCCESS)
6057                 goto DONE;
6058
6059         /* Add the mac addr into mac list */
6060         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6061         if (f == NULL) {
6062                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6063                 ret = I40E_ERR_NO_MEMORY;
6064                 goto DONE;
6065         }
6066         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6067                         ETH_ADDR_LEN);
6068         f->mac_info.filter_type = mac_filter->filter_type;
6069         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6070         vsi->mac_num++;
6071
6072         ret = I40E_SUCCESS;
6073 DONE:
6074         rte_free(mv_f);
6075
6076         return ret;
6077 }
6078
6079 int
6080 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6081 {
6082         struct i40e_mac_filter *f;
6083         struct i40e_macvlan_filter *mv_f;
6084         int i, vlan_num;
6085         enum rte_mac_filter_type filter_type;
6086         int ret = I40E_SUCCESS;
6087
6088         /* Can't find it, return an error */
6089         f = i40e_find_mac_filter(vsi, addr);
6090         if (f == NULL)
6091                 return I40E_ERR_PARAM;
6092
6093         vlan_num = vsi->vlan_num;
6094         filter_type = f->mac_info.filter_type;
6095         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6096                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6097                 if (vlan_num == 0) {
6098                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6099                         return I40E_ERR_PARAM;
6100                 }
6101         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6102                         filter_type == RTE_MAC_HASH_MATCH)
6103                 vlan_num = 1;
6104
6105         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6106         if (mv_f == NULL) {
6107                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6108                 return I40E_ERR_NO_MEMORY;
6109         }
6110
6111         for (i = 0; i < vlan_num; i++) {
6112                 mv_f[i].filter_type = filter_type;
6113                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6114                                 ETH_ADDR_LEN);
6115         }
6116         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6117                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6118                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6119                 if (ret != I40E_SUCCESS)
6120                         goto DONE;
6121         }
6122
6123         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6124         if (ret != I40E_SUCCESS)
6125                 goto DONE;
6126
6127         /* Remove the mac addr into mac list */
6128         TAILQ_REMOVE(&vsi->mac_list, f, next);
6129         rte_free(f);
6130         vsi->mac_num--;
6131
6132         ret = I40E_SUCCESS;
6133 DONE:
6134         rte_free(mv_f);
6135         return ret;
6136 }
6137
6138 /* Configure hash enable flags for RSS */
6139 uint64_t
6140 i40e_config_hena(uint64_t flags)
6141 {
6142         uint64_t hena = 0;
6143
6144         if (!flags)
6145                 return hena;
6146
6147         if (flags & ETH_RSS_FRAG_IPV4)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6149         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6150 #ifdef X722_SUPPORT
6151                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6152                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6153 #else
6154                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6155 #endif
6156         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6157 #ifdef X722_SUPPORT
6158                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6159                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6160                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6161 #else
6162                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6163 #endif
6164         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6166         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6167                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6168         if (flags & ETH_RSS_FRAG_IPV6)
6169                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6170         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6171 #ifdef X722_SUPPORT
6172                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6173                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6174 #else
6175                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6176 #endif
6177         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6178 #ifdef X722_SUPPORT
6179                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6180                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6181                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6182 #else
6183                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6184 #endif
6185         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6186                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6187         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6188                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6189         if (flags & ETH_RSS_L2_PAYLOAD)
6190                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6191
6192         return hena;
6193 }
6194
6195 /* Parse the hash enable flags */
6196 uint64_t
6197 i40e_parse_hena(uint64_t flags)
6198 {
6199         uint64_t rss_hf = 0;
6200
6201         if (!flags)
6202                 return rss_hf;
6203         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6204                 rss_hf |= ETH_RSS_FRAG_IPV4;
6205         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6206                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6207 #ifdef X722_SUPPORT
6208         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6209                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6210 #endif
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6213 #ifdef X722_SUPPORT
6214         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6215                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6216         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6217                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6218 #endif
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6221         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6222                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6223         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6224                 rss_hf |= ETH_RSS_FRAG_IPV6;
6225         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6226                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6227 #ifdef X722_SUPPORT
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6230 #endif
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6233 #ifdef X722_SUPPORT
6234         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6235                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6236         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6237                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6238 #endif
6239         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6240                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6241         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6242                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6243         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6244                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6245
6246         return rss_hf;
6247 }
6248
6249 /* Disable RSS */
6250 static void
6251 i40e_pf_disable_rss(struct i40e_pf *pf)
6252 {
6253         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6254         uint64_t hena;
6255
6256         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6257         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6258         hena &= ~I40E_RSS_HENA_ALL;
6259         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6260         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6261         I40E_WRITE_FLUSH(hw);
6262 }
6263
6264 static int
6265 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6266 {
6267         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6268         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6269         int ret = 0;
6270
6271         if (!key || key_len == 0) {
6272                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6273                 return 0;
6274         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6275                 sizeof(uint32_t)) {
6276                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6277                 return -EINVAL;
6278         }
6279
6280         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6281                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6282                         (struct i40e_aqc_get_set_rss_key_data *)key;
6283
6284                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6285                 if (ret)
6286                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6287                                      "via AQ");
6288         } else {
6289                 uint32_t *hash_key = (uint32_t *)key;
6290                 uint16_t i;
6291
6292                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6293                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6294                 I40E_WRITE_FLUSH(hw);
6295         }
6296
6297         return ret;
6298 }
6299
6300 static int
6301 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6302 {
6303         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6304         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6305         int ret;
6306
6307         if (!key || !key_len)
6308                 return -EINVAL;
6309
6310         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6311                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6312                         (struct i40e_aqc_get_set_rss_key_data *)key);
6313                 if (ret) {
6314                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6315                         return ret;
6316                 }
6317         } else {
6318                 uint32_t *key_dw = (uint32_t *)key;
6319                 uint16_t i;
6320
6321                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6322                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6323         }
6324         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6325
6326         return 0;
6327 }
6328
6329 static int
6330 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6331 {
6332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6333         uint64_t rss_hf;
6334         uint64_t hena;
6335         int ret;
6336
6337         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6338                                rss_conf->rss_key_len);
6339         if (ret)
6340                 return ret;
6341
6342         rss_hf = rss_conf->rss_hf;
6343         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6344         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6345         hena &= ~I40E_RSS_HENA_ALL;
6346         hena |= i40e_config_hena(rss_hf);
6347         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6348         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6349         I40E_WRITE_FLUSH(hw);
6350
6351         return 0;
6352 }
6353
6354 static int
6355 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6356                          struct rte_eth_rss_conf *rss_conf)
6357 {
6358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6360         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6361         uint64_t hena;
6362
6363         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6364         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6365         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6366                 if (rss_hf != 0) /* Enable RSS */
6367                         return -EINVAL;
6368                 return 0; /* Nothing to do */
6369         }
6370         /* RSS enabled */
6371         if (rss_hf == 0) /* Disable RSS */
6372                 return -EINVAL;
6373
6374         return i40e_hw_rss_hash_set(pf, rss_conf);
6375 }
6376
6377 static int
6378 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6379                            struct rte_eth_rss_conf *rss_conf)
6380 {
6381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6383         uint64_t hena;
6384
6385         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6386                          &rss_conf->rss_key_len);
6387
6388         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6389         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6390         rss_conf->rss_hf = i40e_parse_hena(hena);
6391
6392         return 0;
6393 }
6394
6395 static int
6396 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6397 {
6398         switch (filter_type) {
6399         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6400                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6401                 break;
6402         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6403                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6404                 break;
6405         case RTE_TUNNEL_FILTER_IMAC_TENID:
6406                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6407                 break;
6408         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6409                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6410                 break;
6411         case ETH_TUNNEL_FILTER_IMAC:
6412                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6413                 break;
6414         case ETH_TUNNEL_FILTER_OIP:
6415                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6416                 break;
6417         case ETH_TUNNEL_FILTER_IIP:
6418                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6419                 break;
6420         default:
6421                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6422                 return -EINVAL;
6423         }
6424
6425         return 0;
6426 }
6427
6428 static int
6429 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6430                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6431                         uint8_t add)
6432 {
6433         uint16_t ip_type;
6434         uint32_t ipv4_addr;
6435         uint8_t i, tun_type = 0;
6436         /* internal varialbe to convert ipv6 byte order */
6437         uint32_t convert_ipv6[4];
6438         int val, ret = 0;
6439         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6440         struct i40e_vsi *vsi = pf->main_vsi;
6441         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6442         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6443
6444         cld_filter = rte_zmalloc("tunnel_filter",
6445                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6446                 0);
6447
6448         if (NULL == cld_filter) {
6449                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6450                 return -EINVAL;
6451         }
6452         pfilter = cld_filter;
6453
6454         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6455         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6456
6457         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6458         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6459                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6460                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6461                 rte_memcpy(&pfilter->ipaddr.v4.data,
6462                                 &rte_cpu_to_le_32(ipv4_addr),
6463                                 sizeof(pfilter->ipaddr.v4.data));
6464         } else {
6465                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6466                 for (i = 0; i < 4; i++) {
6467                         convert_ipv6[i] =
6468                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6469                 }
6470                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6471                                 sizeof(pfilter->ipaddr.v6.data));
6472         }
6473
6474         /* check tunneled type */
6475         switch (tunnel_filter->tunnel_type) {
6476         case RTE_TUNNEL_TYPE_VXLAN:
6477                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6478                 break;
6479         case RTE_TUNNEL_TYPE_NVGRE:
6480                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6481                 break;
6482         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6483                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6484                 break;
6485         default:
6486                 /* Other tunnel types is not supported. */
6487                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6488                 rte_free(cld_filter);
6489                 return -EINVAL;
6490         }
6491
6492         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6493                                                 &pfilter->flags);
6494         if (val < 0) {
6495                 rte_free(cld_filter);
6496                 return -EINVAL;
6497         }
6498
6499         pfilter->flags |= rte_cpu_to_le_16(
6500                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6501                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6502         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6503         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6504
6505         if (add)
6506                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6507         else
6508                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6509                                                 cld_filter, 1);
6510
6511         rte_free(cld_filter);
6512         return ret;
6513 }
6514
6515 static int
6516 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6517 {
6518         uint8_t i;
6519
6520         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6521                 if (pf->vxlan_ports[i] == port)
6522                         return i;
6523         }
6524
6525         return -1;
6526 }
6527
6528 static int
6529 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6530 {
6531         int  idx, ret;
6532         uint8_t filter_idx;
6533         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6534
6535         idx = i40e_get_vxlan_port_idx(pf, port);
6536
6537         /* Check if port already exists */
6538         if (idx >= 0) {
6539                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6540                 return -EINVAL;
6541         }
6542
6543         /* Now check if there is space to add the new port */
6544         idx = i40e_get_vxlan_port_idx(pf, 0);
6545         if (idx < 0) {
6546                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6547                         "not adding port %d", port);
6548                 return -ENOSPC;
6549         }
6550
6551         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6552                                         &filter_idx, NULL);
6553         if (ret < 0) {
6554                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6555                 return -1;
6556         }
6557
6558         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6559                          port,  filter_idx);
6560
6561         /* New port: add it and mark its index in the bitmap */
6562         pf->vxlan_ports[idx] = port;
6563         pf->vxlan_bitmap |= (1 << idx);
6564
6565         if (!(pf->flags & I40E_FLAG_VXLAN))
6566                 pf->flags |= I40E_FLAG_VXLAN;
6567
6568         return 0;
6569 }
6570
6571 static int
6572 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6573 {
6574         int idx;
6575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6576
6577         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6578                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6579                 return -EINVAL;
6580         }
6581
6582         idx = i40e_get_vxlan_port_idx(pf, port);
6583
6584         if (idx < 0) {
6585                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6586                 return -EINVAL;
6587         }
6588
6589         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6590                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6591                 return -1;
6592         }
6593
6594         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6595                         port, idx);
6596
6597         pf->vxlan_ports[idx] = 0;
6598         pf->vxlan_bitmap &= ~(1 << idx);
6599
6600         if (!pf->vxlan_bitmap)
6601                 pf->flags &= ~I40E_FLAG_VXLAN;
6602
6603         return 0;
6604 }
6605
6606 /* Add UDP tunneling port */
6607 static int
6608 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6609                              struct rte_eth_udp_tunnel *udp_tunnel)
6610 {
6611         int ret = 0;
6612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6613
6614         if (udp_tunnel == NULL)
6615                 return -EINVAL;
6616
6617         switch (udp_tunnel->prot_type) {
6618         case RTE_TUNNEL_TYPE_VXLAN:
6619                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6620                 break;
6621
6622         case RTE_TUNNEL_TYPE_GENEVE:
6623         case RTE_TUNNEL_TYPE_TEREDO:
6624                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6625                 ret = -1;
6626                 break;
6627
6628         default:
6629                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6630                 ret = -1;
6631                 break;
6632         }
6633
6634         return ret;
6635 }
6636
6637 /* Remove UDP tunneling port */
6638 static int
6639 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6640                              struct rte_eth_udp_tunnel *udp_tunnel)
6641 {
6642         int ret = 0;
6643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6644
6645         if (udp_tunnel == NULL)
6646                 return -EINVAL;
6647
6648         switch (udp_tunnel->prot_type) {
6649         case RTE_TUNNEL_TYPE_VXLAN:
6650                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6651                 break;
6652         case RTE_TUNNEL_TYPE_GENEVE:
6653         case RTE_TUNNEL_TYPE_TEREDO:
6654                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6655                 ret = -1;
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6659                 ret = -1;
6660                 break;
6661         }
6662
6663         return ret;
6664 }
6665
6666 /* Calculate the maximum number of contiguous PF queues that are configured */
6667 static int
6668 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6669 {
6670         struct rte_eth_dev_data *data = pf->dev_data;
6671         int i, num;
6672         struct i40e_rx_queue *rxq;
6673
6674         num = 0;
6675         for (i = 0; i < pf->lan_nb_qps; i++) {
6676                 rxq = data->rx_queues[i];
6677                 if (rxq && rxq->q_set)
6678                         num++;
6679                 else
6680                         break;
6681         }
6682
6683         return num;
6684 }
6685
6686 /* Configure RSS */
6687 static int
6688 i40e_pf_config_rss(struct i40e_pf *pf)
6689 {
6690         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6691         struct rte_eth_rss_conf rss_conf;
6692         uint32_t i, lut = 0;
6693         uint16_t j, num;
6694
6695         /*
6696          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6697          * It's necessary to calulate the actual PF queues that are configured.
6698          */
6699         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6700                 num = i40e_pf_calc_configured_queues_num(pf);
6701         else
6702                 num = pf->dev_data->nb_rx_queues;
6703
6704         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6705         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6706                         num);
6707
6708         if (num == 0) {
6709                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6710                 return -ENOTSUP;
6711         }
6712
6713         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6714                 if (j == num)
6715                         j = 0;
6716                 lut = (lut << 8) | (j & ((0x1 <<
6717                         hw->func_caps.rss_table_entry_width) - 1));
6718                 if ((i & 3) == 3)
6719                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6720         }
6721
6722         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6723         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6724                 i40e_pf_disable_rss(pf);
6725                 return 0;
6726         }
6727         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6728                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6729                 /* Random default keys */
6730                 static uint32_t rss_key_default[] = {0x6b793944,
6731                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6732                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6733                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6734
6735                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6736                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6737                                                         sizeof(uint32_t);
6738         }
6739
6740         return i40e_hw_rss_hash_set(pf, &rss_conf);
6741 }
6742
6743 static int
6744 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6745                                struct rte_eth_tunnel_filter_conf *filter)
6746 {
6747         if (pf == NULL || filter == NULL) {
6748                 PMD_DRV_LOG(ERR, "Invalid parameter");
6749                 return -EINVAL;
6750         }
6751
6752         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6753                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6754                 return -EINVAL;
6755         }
6756
6757         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6758                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6759                 return -EINVAL;
6760         }
6761
6762         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6763                 (is_zero_ether_addr(&filter->outer_mac))) {
6764                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6765                 return -EINVAL;
6766         }
6767
6768         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6769                 (is_zero_ether_addr(&filter->inner_mac))) {
6770                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6771                 return -EINVAL;
6772         }
6773
6774         return 0;
6775 }
6776
6777 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6778 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6779 static int
6780 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6781 {
6782         uint32_t val, reg;
6783         int ret = -EINVAL;
6784
6785         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6786         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6787
6788         if (len == 3) {
6789                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6790         } else if (len == 4) {
6791                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6792         } else {
6793                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6794                 return ret;
6795         }
6796
6797         if (reg != val) {
6798                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6799                                                    reg, NULL);
6800                 if (ret != 0)
6801                         return ret;
6802         } else {
6803                 ret = 0;
6804         }
6805         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6806                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6807
6808         return ret;
6809 }
6810
6811 static int
6812 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6813 {
6814         int ret = -EINVAL;
6815
6816         if (!hw || !cfg)
6817                 return -EINVAL;
6818
6819         switch (cfg->cfg_type) {
6820         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6821                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6822                 break;
6823         default:
6824                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6825                 break;
6826         }
6827
6828         return ret;
6829 }
6830
6831 static int
6832 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6833                                enum rte_filter_op filter_op,
6834                                void *arg)
6835 {
6836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837         int ret = I40E_ERR_PARAM;
6838
6839         switch (filter_op) {
6840         case RTE_ETH_FILTER_SET:
6841                 ret = i40e_dev_global_config_set(hw,
6842                         (struct rte_eth_global_cfg *)arg);
6843                 break;
6844         default:
6845                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6846                 break;
6847         }
6848
6849         return ret;
6850 }
6851
6852 static int
6853 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6854                           enum rte_filter_op filter_op,
6855                           void *arg)
6856 {
6857         struct rte_eth_tunnel_filter_conf *filter;
6858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6859         int ret = I40E_SUCCESS;
6860
6861         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6862
6863         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6864                 return I40E_ERR_PARAM;
6865
6866         switch (filter_op) {
6867         case RTE_ETH_FILTER_NOP:
6868                 if (!(pf->flags & I40E_FLAG_VXLAN))
6869                         ret = I40E_NOT_SUPPORTED;
6870                 break;
6871         case RTE_ETH_FILTER_ADD:
6872                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6873                 break;
6874         case RTE_ETH_FILTER_DELETE:
6875                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6876                 break;
6877         default:
6878                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6879                 ret = I40E_ERR_PARAM;
6880                 break;
6881         }
6882
6883         return ret;
6884 }
6885
6886 static int
6887 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6888 {
6889         int ret = 0;
6890         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6891
6892         /* RSS setup */
6893         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6894                 ret = i40e_pf_config_rss(pf);
6895         else
6896                 i40e_pf_disable_rss(pf);
6897
6898         return ret;
6899 }
6900
6901 /* Get the symmetric hash enable configurations per port */
6902 static void
6903 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6904 {
6905         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6906
6907         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6908 }
6909
6910 /* Set the symmetric hash enable configurations per port */
6911 static void
6912 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6913 {
6914         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6915
6916         if (enable > 0) {
6917                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6918                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6919                                                         "been enabled");
6920                         return;
6921                 }
6922                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6923         } else {
6924                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6925                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6926                                                         "been disabled");
6927                         return;
6928                 }
6929                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6930         }
6931         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6932         I40E_WRITE_FLUSH(hw);
6933 }
6934
6935 /*
6936  * Get global configurations of hash function type and symmetric hash enable
6937  * per flow type (pctype). Note that global configuration means it affects all
6938  * the ports on the same NIC.
6939  */
6940 static int
6941 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6942                                    struct rte_eth_hash_global_conf *g_cfg)
6943 {
6944         uint32_t reg, mask = I40E_FLOW_TYPES;
6945         uint16_t i;
6946         enum i40e_filter_pctype pctype;
6947
6948         memset(g_cfg, 0, sizeof(*g_cfg));
6949         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6950         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6951                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6952         else
6953                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6954         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6955                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6956
6957         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6958                 if (!(mask & (1UL << i)))
6959                         continue;
6960                 mask &= ~(1UL << i);
6961                 /* Bit set indicats the coresponding flow type is supported */
6962                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6963                 /* if flowtype is invalid, continue */
6964                 if (!I40E_VALID_FLOW(i))
6965                         continue;
6966                 pctype = i40e_flowtype_to_pctype(i);
6967                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6968                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6969                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6970         }
6971
6972         return 0;
6973 }
6974
6975 static int
6976 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6977 {
6978         uint32_t i;
6979         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6980
6981         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6982                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6983                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6984                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6985                                                 g_cfg->hash_func);
6986                 return -EINVAL;
6987         }
6988
6989         /*
6990          * As i40e supports less than 32 flow types, only first 32 bits need to
6991          * be checked.
6992          */
6993         mask0 = g_cfg->valid_bit_mask[0];
6994         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6995                 if (i == 0) {
6996                         /* Check if any unsupported flow type configured */
6997                         if ((mask0 | i40e_mask) ^ i40e_mask)
6998                                 goto mask_err;
6999                 } else {
7000                         if (g_cfg->valid_bit_mask[i])
7001                                 goto mask_err;
7002                 }
7003         }
7004
7005         return 0;
7006
7007 mask_err:
7008         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7009
7010         return -EINVAL;
7011 }
7012
7013 /*
7014  * Set global configurations of hash function type and symmetric hash enable
7015  * per flow type (pctype). Note any modifying global configuration will affect
7016  * all the ports on the same NIC.
7017  */
7018 static int
7019 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7020                                    struct rte_eth_hash_global_conf *g_cfg)
7021 {
7022         int ret;
7023         uint16_t i;
7024         uint32_t reg;
7025         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7026         enum i40e_filter_pctype pctype;
7027
7028         /* Check the input parameters */
7029         ret = i40e_hash_global_config_check(g_cfg);
7030         if (ret < 0)
7031                 return ret;
7032
7033         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7034                 if (!(mask0 & (1UL << i)))
7035                         continue;
7036                 mask0 &= ~(1UL << i);
7037                 /* if flowtype is invalid, continue */
7038                 if (!I40E_VALID_FLOW(i))
7039                         continue;
7040                 pctype = i40e_flowtype_to_pctype(i);
7041                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7042                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7043                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7044         }
7045
7046         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7047         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7048                 /* Toeplitz */
7049                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7050                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7051                                                                 "Toeplitz");
7052                         goto out;
7053                 }
7054                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7055         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7056                 /* Simple XOR */
7057                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7058                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7059                                                         "Simple XOR");
7060                         goto out;
7061                 }
7062                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7063         } else
7064                 /* Use the default, and keep it as it is */
7065                 goto out;
7066
7067         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7068
7069 out:
7070         I40E_WRITE_FLUSH(hw);
7071
7072         return 0;
7073 }
7074
7075 /**
7076  * Valid input sets for hash and flow director filters per PCTYPE
7077  */
7078 static uint64_t
7079 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7080                 enum rte_filter_type filter)
7081 {
7082         uint64_t valid;
7083
7084         static const uint64_t valid_hash_inset_table[] = {
7085                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7086                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7087                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7088                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7089                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7090                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7091                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7092                         I40E_INSET_FLEX_PAYLOAD,
7093                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7094                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7095                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7096                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7097                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7098                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7099                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7100                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7101                         I40E_INSET_FLEX_PAYLOAD,
7102 #ifdef X722_SUPPORT
7103                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7107                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7108                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7109                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7110                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7111                         I40E_INSET_FLEX_PAYLOAD,
7112                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7113                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7114                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7115                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7116                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7117                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7118                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7119                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7120                         I40E_INSET_FLEX_PAYLOAD,
7121 #endif
7122                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7123                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7124                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7125                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7126                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7127                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7128                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7129                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7130                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7131 #ifdef X722_SUPPORT
7132                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7138                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7139                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7140                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7141 #endif
7142                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7146                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7147                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7148                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7150                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7151                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7152                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7153                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7154                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7155                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7156                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7157                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7158                         I40E_INSET_FLEX_PAYLOAD,
7159                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7163                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7164                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7165                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7166                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7167                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7168                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7169                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7171                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7172                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7173                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7174                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7175 #ifdef X722_SUPPORT
7176                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7177                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7178                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7179                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7180                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7181                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7182                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7183                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7184                         I40E_INSET_FLEX_PAYLOAD,
7185                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7186                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7187                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7189                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7190                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7191                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7192                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7193                         I40E_INSET_FLEX_PAYLOAD,
7194 #endif
7195                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7196                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7197                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7198                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7199                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7200                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7201                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7202                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7203                         I40E_INSET_FLEX_PAYLOAD,
7204 #ifdef X722_SUPPORT
7205                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7206                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7207                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7208                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7209                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7210                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7211                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7212                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7213                         I40E_INSET_FLEX_PAYLOAD,
7214 #endif
7215                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7216                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7217                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7218                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7219                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7220                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7221                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7222                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7223                         I40E_INSET_FLEX_PAYLOAD,
7224                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7225                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7226                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7227                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7228                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7229                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7230                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7231                         I40E_INSET_FLEX_PAYLOAD,
7232                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7233                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7234                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7235                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7236                         I40E_INSET_FLEX_PAYLOAD,
7237         };
7238
7239         /**
7240          * Flow director supports only fields defined in
7241          * union rte_eth_fdir_flow.
7242          */
7243         static const uint64_t valid_fdir_inset_table[] = {
7244                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7246                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7247                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7248                 I40E_INSET_IPV4_TTL,
7249                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7251                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7252                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7253                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7254 #ifdef X722_SUPPORT
7255                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7259                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7260                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7264                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7265 #endif
7266                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7271 #ifdef X722_SUPPORT
7272                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7273                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7274                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7275                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7276                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7277 #endif
7278                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7279                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7280                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7281                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7282                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7283                 I40E_INSET_SCTP_VT,
7284                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7285                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7287                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7288                 I40E_INSET_IPV4_TTL,
7289                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7290                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7292                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7293                 I40E_INSET_IPV6_HOP_LIMIT,
7294                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7295                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7296                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7297                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7298                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7299 #ifdef X722_SUPPORT
7300                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7303                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7304                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7305                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7306                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7308                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7309                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7310 #endif
7311                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7315                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7316 #ifdef X722_SUPPORT
7317                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7321                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7322 #endif
7323                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7327                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7328                 I40E_INSET_SCTP_VT,
7329                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7330                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7331                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7332                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7333                 I40E_INSET_IPV6_HOP_LIMIT,
7334                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336                 I40E_INSET_LAST_ETHER_TYPE,
7337         };
7338
7339         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7340                 return 0;
7341         if (filter == RTE_ETH_FILTER_HASH)
7342                 valid = valid_hash_inset_table[pctype];
7343         else
7344                 valid = valid_fdir_inset_table[pctype];
7345
7346         return valid;
7347 }
7348
7349 /**
7350  * Validate if the input set is allowed for a specific PCTYPE
7351  */
7352 static int
7353 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7354                 enum rte_filter_type filter, uint64_t inset)
7355 {
7356         uint64_t valid;
7357
7358         valid = i40e_get_valid_input_set(pctype, filter);
7359         if (inset & (~valid))
7360                 return -EINVAL;
7361
7362         return 0;
7363 }
7364
7365 /* default input set fields combination per pctype */
7366 static uint64_t
7367 i40e_get_default_input_set(uint16_t pctype)
7368 {
7369         static const uint64_t default_inset_table[] = {
7370                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7371                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7372                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7373                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7374                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7375 #ifdef X722_SUPPORT
7376                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7377                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7378                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7379                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7380                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7381                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7382 #endif
7383                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7384                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7385                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7386 #ifdef X722_SUPPORT
7387                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7390 #endif
7391                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7392                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7393                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7394                         I40E_INSET_SCTP_VT,
7395                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7397                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7398                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7399                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7400                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7401                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7402 #ifdef X722_SUPPORT
7403                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7404                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7405                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7406                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7407                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7408                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7409 #endif
7410                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7411                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7413 #ifdef X722_SUPPORT
7414                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7417 #endif
7418                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7420                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7421                         I40E_INSET_SCTP_VT,
7422                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7423                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7424                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7425                         I40E_INSET_LAST_ETHER_TYPE,
7426         };
7427
7428         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7429                 return 0;
7430
7431         return default_inset_table[pctype];
7432 }
7433
7434 /**
7435  * Parse the input set from index to logical bit masks
7436  */
7437 static int
7438 i40e_parse_input_set(uint64_t *inset,
7439                      enum i40e_filter_pctype pctype,
7440                      enum rte_eth_input_set_field *field,
7441                      uint16_t size)
7442 {
7443         uint16_t i, j;
7444         int ret = -EINVAL;
7445
7446         static const struct {
7447                 enum rte_eth_input_set_field field;
7448                 uint64_t inset;
7449         } inset_convert_table[] = {
7450                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7451                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7452                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7453                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7454                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7455                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7456                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7457                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7458                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7459                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7460                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7461                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7462                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7463                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7464                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7465                         I40E_INSET_IPV6_NEXT_HDR},
7466                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7467                         I40E_INSET_IPV6_HOP_LIMIT},
7468                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7469                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7470                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7471                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7472                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7473                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7474                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7475                         I40E_INSET_SCTP_VT},
7476                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7477                         I40E_INSET_TUNNEL_DMAC},
7478                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7479                         I40E_INSET_VLAN_TUNNEL},
7480                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7481                         I40E_INSET_TUNNEL_ID},
7482                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7483                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7484                         I40E_INSET_FLEX_PAYLOAD_W1},
7485                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7486                         I40E_INSET_FLEX_PAYLOAD_W2},
7487                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7488                         I40E_INSET_FLEX_PAYLOAD_W3},
7489                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7490                         I40E_INSET_FLEX_PAYLOAD_W4},
7491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7492                         I40E_INSET_FLEX_PAYLOAD_W5},
7493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7494                         I40E_INSET_FLEX_PAYLOAD_W6},
7495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7496                         I40E_INSET_FLEX_PAYLOAD_W7},
7497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7498                         I40E_INSET_FLEX_PAYLOAD_W8},
7499         };
7500
7501         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7502                 return ret;
7503
7504         /* Only one item allowed for default or all */
7505         if (size == 1) {
7506                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7507                         *inset = i40e_get_default_input_set(pctype);
7508                         return 0;
7509                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7510                         *inset = I40E_INSET_NONE;
7511                         return 0;
7512                 }
7513         }
7514
7515         for (i = 0, *inset = 0; i < size; i++) {
7516                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7517                         if (field[i] == inset_convert_table[j].field) {
7518                                 *inset |= inset_convert_table[j].inset;
7519                                 break;
7520                         }
7521                 }
7522
7523                 /* It contains unsupported input set, return immediately */
7524                 if (j == RTE_DIM(inset_convert_table))
7525                         return ret;
7526         }
7527
7528         return 0;
7529 }
7530
7531 /**
7532  * Translate the input set from bit masks to register aware bit masks
7533  * and vice versa
7534  */
7535 static uint64_t
7536 i40e_translate_input_set_reg(uint64_t input)
7537 {
7538         uint64_t val = 0;
7539         uint16_t i;
7540
7541         static const struct {
7542                 uint64_t inset;
7543                 uint64_t inset_reg;
7544         } inset_map[] = {
7545                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7546                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7547                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7548                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7549                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7550                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7551                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7552                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7553                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7554                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7555                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7556                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7557                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7558                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7559                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7560                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7561                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7562                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7563                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7564                 {I40E_INSET_TUNNEL_DMAC,
7565                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7566                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7567                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7568                 {I40E_INSET_TUNNEL_SRC_PORT,
7569                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7570                 {I40E_INSET_TUNNEL_DST_PORT,
7571                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7572                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7573                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7574                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7575                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7576                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7577                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7578                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7579                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7580                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7581         };
7582
7583         if (input == 0)
7584                 return val;
7585
7586         /* Translate input set to register aware inset */
7587         for (i = 0; i < RTE_DIM(inset_map); i++) {
7588                 if (input & inset_map[i].inset)
7589                         val |= inset_map[i].inset_reg;
7590         }
7591
7592         return val;
7593 }
7594
7595 static int
7596 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7597 {
7598         uint8_t i, idx = 0;
7599         uint64_t inset_need_mask = inset;
7600
7601         static const struct {
7602                 uint64_t inset;
7603                 uint32_t mask;
7604         } inset_mask_map[] = {
7605                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7606                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7607                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7608                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7609                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7610                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7611                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7612                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7613         };
7614
7615         if (!inset || !mask || !nb_elem)
7616                 return 0;
7617
7618         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7619                 /* Clear the inset bit, if no MASK is required,
7620                  * for example proto + ttl
7621                  */
7622                 if ((inset & inset_mask_map[i].inset) ==
7623                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7624                         inset_need_mask &= ~inset_mask_map[i].inset;
7625                 if (!inset_need_mask)
7626                         return 0;
7627         }
7628         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7629                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7630                     inset_mask_map[i].inset) {
7631                         if (idx >= nb_elem) {
7632                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7633                                 return -EINVAL;
7634                         }
7635                         mask[idx] = inset_mask_map[i].mask;
7636                         idx++;
7637                 }
7638         }
7639
7640         return idx;
7641 }
7642
7643 static void
7644 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7645 {
7646         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7647
7648         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7649         if (reg != val)
7650                 i40e_write_rx_ctl(hw, addr, val);
7651         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7652                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7653 }
7654
7655 static void
7656 i40e_filter_input_set_init(struct i40e_pf *pf)
7657 {
7658         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7659         enum i40e_filter_pctype pctype;
7660         uint64_t input_set, inset_reg;
7661         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7662         int num, i;
7663
7664         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7665              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7666                 if (!I40E_VALID_PCTYPE(pctype))
7667                         continue;
7668                 input_set = i40e_get_default_input_set(pctype);
7669
7670                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7671                                                    I40E_INSET_MASK_NUM_REG);
7672                 if (num < 0)
7673                         return;
7674                 inset_reg = i40e_translate_input_set_reg(input_set);
7675
7676                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7677                                       (uint32_t)(inset_reg & UINT32_MAX));
7678                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7679                                      (uint32_t)((inset_reg >>
7680                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7681                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7682                                       (uint32_t)(inset_reg & UINT32_MAX));
7683                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7684                                      (uint32_t)((inset_reg >>
7685                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7686
7687                 for (i = 0; i < num; i++) {
7688                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7689                                              mask_reg[i]);
7690                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7691                                              mask_reg[i]);
7692                 }
7693                 /*clear unused mask registers of the pctype */
7694                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7695                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7696                                              0);
7697                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7698                                              0);
7699                 }
7700                 I40E_WRITE_FLUSH(hw);
7701
7702                 /* store the default input set */
7703                 pf->hash_input_set[pctype] = input_set;
7704                 pf->fdir.input_set[pctype] = input_set;
7705         }
7706 }
7707
7708 int
7709 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7710                          struct rte_eth_input_set_conf *conf)
7711 {
7712         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7713         enum i40e_filter_pctype pctype;
7714         uint64_t input_set, inset_reg = 0;
7715         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7716         int ret, i, num;
7717
7718         if (!conf) {
7719                 PMD_DRV_LOG(ERR, "Invalid pointer");
7720                 return -EFAULT;
7721         }
7722         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7723             conf->op != RTE_ETH_INPUT_SET_ADD) {
7724                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7725                 return -EINVAL;
7726         }
7727
7728         if (!I40E_VALID_FLOW(conf->flow_type)) {
7729                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7730                 return -EINVAL;
7731         }
7732
7733 #ifdef X722_SUPPORT
7734         /* get translated pctype value in fd pctype register */
7735         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7736                 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7737                 conf->flow_type)));
7738 #else
7739         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7740 #endif
7741
7742         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7743                                    conf->inset_size);
7744         if (ret) {
7745                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7746                 return -EINVAL;
7747         }
7748         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7749                                     input_set) != 0) {
7750                 PMD_DRV_LOG(ERR, "Invalid input set");
7751                 return -EINVAL;
7752         }
7753         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7754                 /* get inset value in register */
7755                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7756                 inset_reg <<= I40E_32_BIT_WIDTH;
7757                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7758                 input_set |= pf->hash_input_set[pctype];
7759         }
7760         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7761                                            I40E_INSET_MASK_NUM_REG);
7762         if (num < 0)
7763                 return -EINVAL;
7764
7765         inset_reg |= i40e_translate_input_set_reg(input_set);
7766
7767         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7768                               (uint32_t)(inset_reg & UINT32_MAX));
7769         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7770                              (uint32_t)((inset_reg >>
7771                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7772
7773         for (i = 0; i < num; i++)
7774                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7775                                      mask_reg[i]);
7776         /*clear unused mask registers of the pctype */
7777         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7778                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7779                                      0);
7780         I40E_WRITE_FLUSH(hw);
7781
7782         pf->hash_input_set[pctype] = input_set;
7783         return 0;
7784 }
7785
7786 int
7787 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7788                          struct rte_eth_input_set_conf *conf)
7789 {
7790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7791         enum i40e_filter_pctype pctype;
7792         uint64_t input_set, inset_reg = 0;
7793         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7794         int ret, i, num;
7795
7796         if (!hw || !conf) {
7797                 PMD_DRV_LOG(ERR, "Invalid pointer");
7798                 return -EFAULT;
7799         }
7800         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7801             conf->op != RTE_ETH_INPUT_SET_ADD) {
7802                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7803                 return -EINVAL;
7804         }
7805
7806         if (!I40E_VALID_FLOW(conf->flow_type)) {
7807                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7808                 return -EINVAL;
7809         }
7810
7811         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7812
7813         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7814                                    conf->inset_size);
7815         if (ret) {
7816                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7817                 return -EINVAL;
7818         }
7819         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7820                                     input_set) != 0) {
7821                 PMD_DRV_LOG(ERR, "Invalid input set");
7822                 return -EINVAL;
7823         }
7824
7825         /* get inset value in register */
7826         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7827         inset_reg <<= I40E_32_BIT_WIDTH;
7828         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7829
7830         /* Can not change the inset reg for flex payload for fdir,
7831          * it is done by writing I40E_PRTQF_FD_FLXINSET
7832          * in i40e_set_flex_mask_on_pctype.
7833          */
7834         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7835                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7836         else
7837                 input_set |= pf->fdir.input_set[pctype];
7838         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7839                                            I40E_INSET_MASK_NUM_REG);
7840         if (num < 0)
7841                 return -EINVAL;
7842
7843         inset_reg |= i40e_translate_input_set_reg(input_set);
7844
7845         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7846                               (uint32_t)(inset_reg & UINT32_MAX));
7847         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7848                              (uint32_t)((inset_reg >>
7849                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7850
7851         for (i = 0; i < num; i++)
7852                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7853                                      mask_reg[i]);
7854         /*clear unused mask registers of the pctype */
7855         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7856                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7857                                      0);
7858         I40E_WRITE_FLUSH(hw);
7859
7860         pf->fdir.input_set[pctype] = input_set;
7861         return 0;
7862 }
7863
7864 static int
7865 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7866 {
7867         int ret = 0;
7868
7869         if (!hw || !info) {
7870                 PMD_DRV_LOG(ERR, "Invalid pointer");
7871                 return -EFAULT;
7872         }
7873
7874         switch (info->info_type) {
7875         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7876                 i40e_get_symmetric_hash_enable_per_port(hw,
7877                                         &(info->info.enable));
7878                 break;
7879         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7880                 ret = i40e_get_hash_filter_global_config(hw,
7881                                 &(info->info.global_conf));
7882                 break;
7883         default:
7884                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7885                                                         info->info_type);
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 static int
7894 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7895 {
7896         int ret = 0;
7897
7898         if (!hw || !info) {
7899                 PMD_DRV_LOG(ERR, "Invalid pointer");
7900                 return -EFAULT;
7901         }
7902
7903         switch (info->info_type) {
7904         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7905                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7906                 break;
7907         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7908                 ret = i40e_set_hash_filter_global_config(hw,
7909                                 &(info->info.global_conf));
7910                 break;
7911         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7912                 ret = i40e_hash_filter_inset_select(hw,
7913                                                &(info->info.input_set_conf));
7914                 break;
7915
7916         default:
7917                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7918                                                         info->info_type);
7919                 ret = -EINVAL;
7920                 break;
7921         }
7922
7923         return ret;
7924 }
7925
7926 /* Operations for hash function */
7927 static int
7928 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7929                       enum rte_filter_op filter_op,
7930                       void *arg)
7931 {
7932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7933         int ret = 0;
7934
7935         switch (filter_op) {
7936         case RTE_ETH_FILTER_NOP:
7937                 break;
7938         case RTE_ETH_FILTER_GET:
7939                 ret = i40e_hash_filter_get(hw,
7940                         (struct rte_eth_hash_filter_info *)arg);
7941                 break;
7942         case RTE_ETH_FILTER_SET:
7943                 ret = i40e_hash_filter_set(hw,
7944                         (struct rte_eth_hash_filter_info *)arg);
7945                 break;
7946         default:
7947                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7948                                                                 filter_op);
7949                 ret = -ENOTSUP;
7950                 break;
7951         }
7952
7953         return ret;
7954 }
7955
7956 /*
7957  * Configure ethertype filter, which can director packet by filtering
7958  * with mac address and ether_type or only ether_type
7959  */
7960 static int
7961 i40e_ethertype_filter_set(struct i40e_pf *pf,
7962                         struct rte_eth_ethertype_filter *filter,
7963                         bool add)
7964 {
7965         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7966         struct i40e_control_filter_stats stats;
7967         uint16_t flags = 0;
7968         int ret;
7969
7970         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7971                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7972                 return -EINVAL;
7973         }
7974         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7975                 filter->ether_type == ETHER_TYPE_IPv6) {
7976                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7977                         " control packet filter.", filter->ether_type);
7978                 return -EINVAL;
7979         }
7980         if (filter->ether_type == ETHER_TYPE_VLAN)
7981                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7982                         " not supported.");
7983
7984         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7985                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7986         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7987                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7988         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7989
7990         memset(&stats, 0, sizeof(stats));
7991         ret = i40e_aq_add_rem_control_packet_filter(hw,
7992                         filter->mac_addr.addr_bytes,
7993                         filter->ether_type, flags,
7994                         pf->main_vsi->seid,
7995                         filter->queue, add, &stats, NULL);
7996
7997         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7998                          " mac_etype_used = %u, etype_used = %u,"
7999                          " mac_etype_free = %u, etype_free = %u\n",
8000                          ret, stats.mac_etype_used, stats.etype_used,
8001                          stats.mac_etype_free, stats.etype_free);
8002         if (ret < 0)
8003                 return -ENOSYS;
8004         return 0;
8005 }
8006
8007 /*
8008  * Handle operations for ethertype filter.
8009  */
8010 static int
8011 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8012                                 enum rte_filter_op filter_op,
8013                                 void *arg)
8014 {
8015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8016         int ret = 0;
8017
8018         if (filter_op == RTE_ETH_FILTER_NOP)
8019                 return ret;
8020
8021         if (arg == NULL) {
8022                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8023                             filter_op);
8024                 return -EINVAL;
8025         }
8026
8027         switch (filter_op) {
8028         case RTE_ETH_FILTER_ADD:
8029                 ret = i40e_ethertype_filter_set(pf,
8030                         (struct rte_eth_ethertype_filter *)arg,
8031                         TRUE);
8032                 break;
8033         case RTE_ETH_FILTER_DELETE:
8034                 ret = i40e_ethertype_filter_set(pf,
8035                         (struct rte_eth_ethertype_filter *)arg,
8036                         FALSE);
8037                 break;
8038         default:
8039                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8040                 ret = -ENOSYS;
8041                 break;
8042         }
8043         return ret;
8044 }
8045
8046 static int
8047 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8048                      enum rte_filter_type filter_type,
8049                      enum rte_filter_op filter_op,
8050                      void *arg)
8051 {
8052         int ret = 0;
8053
8054         if (dev == NULL)
8055                 return -EINVAL;
8056
8057         switch (filter_type) {
8058         case RTE_ETH_FILTER_NONE:
8059                 /* For global configuration */
8060                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8061                 break;
8062         case RTE_ETH_FILTER_HASH:
8063                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8064                 break;
8065         case RTE_ETH_FILTER_MACVLAN:
8066                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8067                 break;
8068         case RTE_ETH_FILTER_ETHERTYPE:
8069                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8070                 break;
8071         case RTE_ETH_FILTER_TUNNEL:
8072                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8073                 break;
8074         case RTE_ETH_FILTER_FDIR:
8075                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8076                 break;
8077         default:
8078                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8079                                                         filter_type);
8080                 ret = -EINVAL;
8081                 break;
8082         }
8083
8084         return ret;
8085 }
8086
8087 /*
8088  * Check and enable Extended Tag.
8089  * Enabling Extended Tag is important for 40G performance.
8090  */
8091 static void
8092 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8093 {
8094         uint32_t buf = 0;
8095         int ret;
8096
8097         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8098                                       PCI_DEV_CAP_REG);
8099         if (ret < 0) {
8100                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8101                             PCI_DEV_CAP_REG);
8102                 return;
8103         }
8104         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8105                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8106                 return;
8107         }
8108
8109         buf = 0;
8110         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8111                                       PCI_DEV_CTRL_REG);
8112         if (ret < 0) {
8113                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8114                             PCI_DEV_CTRL_REG);
8115                 return;
8116         }
8117         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8118                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8119                 return;
8120         }
8121         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8122         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8123                                        PCI_DEV_CTRL_REG);
8124         if (ret < 0) {
8125                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8126                             PCI_DEV_CTRL_REG);
8127                 return;
8128         }
8129 }
8130
8131 /*
8132  * As some registers wouldn't be reset unless a global hardware reset,
8133  * hardware initialization is needed to put those registers into an
8134  * expected initial state.
8135  */
8136 static void
8137 i40e_hw_init(struct rte_eth_dev *dev)
8138 {
8139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140
8141         i40e_enable_extended_tag(dev);
8142
8143         /* clear the PF Queue Filter control register */
8144         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8145
8146         /* Disable symmetric hash per port */
8147         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8148 }
8149
8150 enum i40e_filter_pctype
8151 i40e_flowtype_to_pctype(uint16_t flow_type)
8152 {
8153         static const enum i40e_filter_pctype pctype_table[] = {
8154                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8155                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8156                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8157                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8158                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8159                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8160                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8161                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8162                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8163                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8164                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8165                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8166                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8167                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8168                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8169                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8170                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8171                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8172                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8173         };
8174
8175         return pctype_table[flow_type];
8176 }
8177
8178 uint16_t
8179 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8180 {
8181         static const uint16_t flowtype_table[] = {
8182                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8183                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8184                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8185 #ifdef X722_SUPPORT
8186                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8187                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8188                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8189                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8190 #endif
8191                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8192                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8193 #ifdef X722_SUPPORT
8194                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8195                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8196 #endif
8197                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8198                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8199                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8200                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8201                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8202                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8203                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8204 #ifdef X722_SUPPORT
8205                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8206                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8207                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8208                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8209 #endif
8210                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8211                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8212 #ifdef X722_SUPPORT
8213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8214                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8215 #endif
8216                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8217                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8218                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8219                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8220                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8221         };
8222
8223         return flowtype_table[pctype];
8224 }
8225
8226 /*
8227  * On X710, performance number is far from the expectation on recent firmware
8228  * versions; on XL710, performance number is also far from the expectation on
8229  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8230  * mode is enabled and port MAC address is equal to the packet destination MAC
8231  * address. The fix for this issue may not be integrated in the following
8232  * firmware version. So the workaround in software driver is needed. It needs
8233  * to modify the initial values of 3 internal only registers for both X710 and
8234  * XL710. Note that the values for X710 or XL710 could be different, and the
8235  * workaround can be removed when it is fixed in firmware in the future.
8236  */
8237
8238 /* For both X710 and XL710 */
8239 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8240 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8241
8242 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8243 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8244
8245 /* For X710 */
8246 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8247 /* For XL710 */
8248 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8249 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8250
8251 static void
8252 i40e_configure_registers(struct i40e_hw *hw)
8253 {
8254         static struct {
8255                 uint32_t addr;
8256                 uint64_t val;
8257         } reg_table[] = {
8258                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8259                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8260                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8261         };
8262         uint64_t reg;
8263         uint32_t i;
8264         int ret;
8265
8266         for (i = 0; i < RTE_DIM(reg_table); i++) {
8267                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8268                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8269                                 reg_table[i].val =
8270                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8271                         else /* For X710 */
8272                                 reg_table[i].val =
8273                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8274                 }
8275
8276                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8277                                                         &reg, NULL);
8278                 if (ret < 0) {
8279                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8280                                                         reg_table[i].addr);
8281                         break;
8282                 }
8283                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8284                                                 reg_table[i].addr, reg);
8285                 if (reg == reg_table[i].val)
8286                         continue;
8287
8288                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8289                                                 reg_table[i].val, NULL);
8290                 if (ret < 0) {
8291                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8292                                 "address of 0x%"PRIx32, reg_table[i].val,
8293                                                         reg_table[i].addr);
8294                         break;
8295                 }
8296                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8297                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8298         }
8299 }
8300
8301 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8302 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8303 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8304 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8305 static int
8306 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8307 {
8308         uint32_t reg;
8309         int ret;
8310
8311         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8312                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8313                 return -EINVAL;
8314         }
8315
8316         /* Configure for double VLAN RX stripping */
8317         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8318         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8319                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8320                 ret = i40e_aq_debug_write_register(hw,
8321                                                    I40E_VSI_TSR(vsi->vsi_id),
8322                                                    reg, NULL);
8323                 if (ret < 0) {
8324                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8325                                     vsi->vsi_id);
8326                         return I40E_ERR_CONFIG;
8327                 }
8328         }
8329
8330         /* Configure for double VLAN TX insertion */
8331         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8332         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8333                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8334                 ret = i40e_aq_debug_write_register(hw,
8335                                                    I40E_VSI_L2TAGSTXVALID(
8336                                                    vsi->vsi_id), reg, NULL);
8337                 if (ret < 0) {
8338                         PMD_DRV_LOG(ERR, "Failed to update "
8339                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8340                         return I40E_ERR_CONFIG;
8341                 }
8342         }
8343
8344         return 0;
8345 }
8346
8347 /**
8348  * i40e_aq_add_mirror_rule
8349  * @hw: pointer to the hardware structure
8350  * @seid: VEB seid to add mirror rule to
8351  * @dst_id: destination vsi seid
8352  * @entries: Buffer which contains the entities to be mirrored
8353  * @count: number of entities contained in the buffer
8354  * @rule_id:the rule_id of the rule to be added
8355  *
8356  * Add a mirror rule for a given veb.
8357  *
8358  **/
8359 static enum i40e_status_code
8360 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8361                         uint16_t seid, uint16_t dst_id,
8362                         uint16_t rule_type, uint16_t *entries,
8363                         uint16_t count, uint16_t *rule_id)
8364 {
8365         struct i40e_aq_desc desc;
8366         struct i40e_aqc_add_delete_mirror_rule cmd;
8367         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8368                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8369                 &desc.params.raw;
8370         uint16_t buff_len;
8371         enum i40e_status_code status;
8372
8373         i40e_fill_default_direct_cmd_desc(&desc,
8374                                           i40e_aqc_opc_add_mirror_rule);
8375         memset(&cmd, 0, sizeof(cmd));
8376
8377         buff_len = sizeof(uint16_t) * count;
8378         desc.datalen = rte_cpu_to_le_16(buff_len);
8379         if (buff_len > 0)
8380                 desc.flags |= rte_cpu_to_le_16(
8381                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8382         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8383                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8384         cmd.num_entries = rte_cpu_to_le_16(count);
8385         cmd.seid = rte_cpu_to_le_16(seid);
8386         cmd.destination = rte_cpu_to_le_16(dst_id);
8387
8388         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8389         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8390         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8391                          "rule_id = %u"
8392                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8393                          hw->aq.asq_last_status, resp->rule_id,
8394                          resp->mirror_rules_used, resp->mirror_rules_free);
8395         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8396
8397         return status;
8398 }
8399
8400 /**
8401  * i40e_aq_del_mirror_rule
8402  * @hw: pointer to the hardware structure
8403  * @seid: VEB seid to add mirror rule to
8404  * @entries: Buffer which contains the entities to be mirrored
8405  * @count: number of entities contained in the buffer
8406  * @rule_id:the rule_id of the rule to be delete
8407  *
8408  * Delete a mirror rule for a given veb.
8409  *
8410  **/
8411 static enum i40e_status_code
8412 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8413                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8414                 uint16_t count, uint16_t rule_id)
8415 {
8416         struct i40e_aq_desc desc;
8417         struct i40e_aqc_add_delete_mirror_rule cmd;
8418         uint16_t buff_len = 0;
8419         enum i40e_status_code status;
8420         void *buff = NULL;
8421
8422         i40e_fill_default_direct_cmd_desc(&desc,
8423                                           i40e_aqc_opc_delete_mirror_rule);
8424         memset(&cmd, 0, sizeof(cmd));
8425         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8426                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8427                                                           I40E_AQ_FLAG_RD));
8428                 cmd.num_entries = count;
8429                 buff_len = sizeof(uint16_t) * count;
8430                 desc.datalen = rte_cpu_to_le_16(buff_len);
8431                 buff = (void *)entries;
8432         } else
8433                 /* rule id is filled in destination field for deleting mirror rule */
8434                 cmd.destination = rte_cpu_to_le_16(rule_id);
8435
8436         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8437                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8438         cmd.seid = rte_cpu_to_le_16(seid);
8439
8440         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8441         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8442
8443         return status;
8444 }
8445
8446 /**
8447  * i40e_mirror_rule_set
8448  * @dev: pointer to the hardware structure
8449  * @mirror_conf: mirror rule info
8450  * @sw_id: mirror rule's sw_id
8451  * @on: enable/disable
8452  *
8453  * set a mirror rule.
8454  *
8455  **/
8456 static int
8457 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8458                         struct rte_eth_mirror_conf *mirror_conf,
8459                         uint8_t sw_id, uint8_t on)
8460 {
8461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8462         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8464         struct i40e_mirror_rule *parent = NULL;
8465         uint16_t seid, dst_seid, rule_id;
8466         uint16_t i, j = 0;
8467         int ret;
8468
8469         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8470
8471         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8472                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8473                         " without veb or vfs.");
8474                 return -ENOSYS;
8475         }
8476         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8477                 PMD_DRV_LOG(ERR, "mirror table is full.");
8478                 return -ENOSPC;
8479         }
8480         if (mirror_conf->dst_pool > pf->vf_num) {
8481                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8482                                  mirror_conf->dst_pool);
8483                 return -EINVAL;
8484         }
8485
8486         seid = pf->main_vsi->veb->seid;
8487
8488         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8489                 if (sw_id <= it->index) {
8490                         mirr_rule = it;
8491                         break;
8492                 }
8493                 parent = it;
8494         }
8495         if (mirr_rule && sw_id == mirr_rule->index) {
8496                 if (on) {
8497                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8498                         return -EEXIST;
8499                 } else {
8500                         ret = i40e_aq_del_mirror_rule(hw, seid,
8501                                         mirr_rule->rule_type,
8502                                         mirr_rule->entries,
8503                                         mirr_rule->num_entries, mirr_rule->id);
8504                         if (ret < 0) {
8505                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8506                                                    " ret = %d, aq_err = %d.",
8507                                                    ret, hw->aq.asq_last_status);
8508                                 return -ENOSYS;
8509                         }
8510                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8511                         rte_free(mirr_rule);
8512                         pf->nb_mirror_rule--;
8513                         return 0;
8514                 }
8515         } else if (!on) {
8516                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8517                 return -ENOENT;
8518         }
8519
8520         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8521                                 sizeof(struct i40e_mirror_rule) , 0);
8522         if (!mirr_rule) {
8523                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8524                 return I40E_ERR_NO_MEMORY;
8525         }
8526         switch (mirror_conf->rule_type) {
8527         case ETH_MIRROR_VLAN:
8528                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8529                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8530                                 mirr_rule->entries[j] =
8531                                         mirror_conf->vlan.vlan_id[i];
8532                                 j++;
8533                         }
8534                 }
8535                 if (j == 0) {
8536                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8537                         rte_free(mirr_rule);
8538                         return -EINVAL;
8539                 }
8540                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8541                 break;
8542         case ETH_MIRROR_VIRTUAL_POOL_UP:
8543         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8544                 /* check if the specified pool bit is out of range */
8545                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8546                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8547                         rte_free(mirr_rule);
8548                         return -EINVAL;
8549                 }
8550                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8551                         if (mirror_conf->pool_mask & (1ULL << i)) {
8552                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8553                                 j++;
8554                         }
8555                 }
8556                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8557                         /* add pf vsi to entries */
8558                         mirr_rule->entries[j] = pf->main_vsi_seid;
8559                         j++;
8560                 }
8561                 if (j == 0) {
8562                         PMD_DRV_LOG(ERR, "pool is not specified.");
8563                         rte_free(mirr_rule);
8564                         return -EINVAL;
8565                 }
8566                 /* egress and ingress in aq commands means from switch but not port */
8567                 mirr_rule->rule_type =
8568                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8569                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8570                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8571                 break;
8572         case ETH_MIRROR_UPLINK_PORT:
8573                 /* egress and ingress in aq commands means from switch but not port*/
8574                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8575                 break;
8576         case ETH_MIRROR_DOWNLINK_PORT:
8577                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8578                 break;
8579         default:
8580                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8581                         mirror_conf->rule_type);
8582                 rte_free(mirr_rule);
8583                 return -EINVAL;
8584         }
8585
8586         /* If the dst_pool is equal to vf_num, consider it as PF */
8587         if (mirror_conf->dst_pool == pf->vf_num)
8588                 dst_seid = pf->main_vsi_seid;
8589         else
8590                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8591
8592         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8593                                       mirr_rule->rule_type, mirr_rule->entries,
8594                                       j, &rule_id);
8595         if (ret < 0) {
8596                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8597                                    " ret = %d, aq_err = %d.",
8598                                    ret, hw->aq.asq_last_status);
8599                 rte_free(mirr_rule);
8600                 return -ENOSYS;
8601         }
8602
8603         mirr_rule->index = sw_id;
8604         mirr_rule->num_entries = j;
8605         mirr_rule->id = rule_id;
8606         mirr_rule->dst_vsi_seid = dst_seid;
8607
8608         if (parent)
8609                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8610         else
8611                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8612
8613         pf->nb_mirror_rule++;
8614         return 0;
8615 }
8616
8617 /**
8618  * i40e_mirror_rule_reset
8619  * @dev: pointer to the device
8620  * @sw_id: mirror rule's sw_id
8621  *
8622  * reset a mirror rule.
8623  *
8624  **/
8625 static int
8626 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8627 {
8628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8630         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8631         uint16_t seid;
8632         int ret;
8633
8634         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8635
8636         seid = pf->main_vsi->veb->seid;
8637
8638         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8639                 if (sw_id == it->index) {
8640                         mirr_rule = it;
8641                         break;
8642                 }
8643         }
8644         if (mirr_rule) {
8645                 ret = i40e_aq_del_mirror_rule(hw, seid,
8646                                 mirr_rule->rule_type,
8647                                 mirr_rule->entries,
8648                                 mirr_rule->num_entries, mirr_rule->id);
8649                 if (ret < 0) {
8650                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8651                                            " status = %d, aq_err = %d.",
8652                                            ret, hw->aq.asq_last_status);
8653                         return -ENOSYS;
8654                 }
8655                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8656                 rte_free(mirr_rule);
8657                 pf->nb_mirror_rule--;
8658         } else {
8659                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8660                 return -ENOENT;
8661         }
8662         return 0;
8663 }
8664
8665 static uint64_t
8666 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8667 {
8668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8669         uint64_t systim_cycles;
8670
8671         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8672         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8673                         << 32;
8674
8675         return systim_cycles;
8676 }
8677
8678 static uint64_t
8679 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8680 {
8681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682         uint64_t rx_tstamp;
8683
8684         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8685         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8686                         << 32;
8687
8688         return rx_tstamp;
8689 }
8690
8691 static uint64_t
8692 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8693 {
8694         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8695         uint64_t tx_tstamp;
8696
8697         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8698         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8699                         << 32;
8700
8701         return tx_tstamp;
8702 }
8703
8704 static void
8705 i40e_start_timecounters(struct rte_eth_dev *dev)
8706 {
8707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8708         struct i40e_adapter *adapter =
8709                         (struct i40e_adapter *)dev->data->dev_private;
8710         struct rte_eth_link link;
8711         uint32_t tsync_inc_l;
8712         uint32_t tsync_inc_h;
8713
8714         /* Get current link speed. */
8715         memset(&link, 0, sizeof(link));
8716         i40e_dev_link_update(dev, 1);
8717         rte_i40e_dev_atomic_read_link_status(dev, &link);
8718
8719         switch (link.link_speed) {
8720         case ETH_SPEED_NUM_40G:
8721                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8722                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8723                 break;
8724         case ETH_SPEED_NUM_10G:
8725                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8726                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8727                 break;
8728         case ETH_SPEED_NUM_1G:
8729                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8730                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8731                 break;
8732         default:
8733                 tsync_inc_l = 0x0;
8734                 tsync_inc_h = 0x0;
8735         }
8736
8737         /* Set the timesync increment value. */
8738         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8739         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8740
8741         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8742         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8743         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8744
8745         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8746         adapter->systime_tc.cc_shift = 0;
8747         adapter->systime_tc.nsec_mask = 0;
8748
8749         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8750         adapter->rx_tstamp_tc.cc_shift = 0;
8751         adapter->rx_tstamp_tc.nsec_mask = 0;
8752
8753         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8754         adapter->tx_tstamp_tc.cc_shift = 0;
8755         adapter->tx_tstamp_tc.nsec_mask = 0;
8756 }
8757
8758 static int
8759 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8760 {
8761         struct i40e_adapter *adapter =
8762                         (struct i40e_adapter *)dev->data->dev_private;
8763
8764         adapter->systime_tc.nsec += delta;
8765         adapter->rx_tstamp_tc.nsec += delta;
8766         adapter->tx_tstamp_tc.nsec += delta;
8767
8768         return 0;
8769 }
8770
8771 static int
8772 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8773 {
8774         uint64_t ns;
8775         struct i40e_adapter *adapter =
8776                         (struct i40e_adapter *)dev->data->dev_private;
8777
8778         ns = rte_timespec_to_ns(ts);
8779
8780         /* Set the timecounters to a new value. */
8781         adapter->systime_tc.nsec = ns;
8782         adapter->rx_tstamp_tc.nsec = ns;
8783         adapter->tx_tstamp_tc.nsec = ns;
8784
8785         return 0;
8786 }
8787
8788 static int
8789 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8790 {
8791         uint64_t ns, systime_cycles;
8792         struct i40e_adapter *adapter =
8793                         (struct i40e_adapter *)dev->data->dev_private;
8794
8795         systime_cycles = i40e_read_systime_cyclecounter(dev);
8796         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8797         *ts = rte_ns_to_timespec(ns);
8798
8799         return 0;
8800 }
8801
8802 static int
8803 i40e_timesync_enable(struct rte_eth_dev *dev)
8804 {
8805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806         uint32_t tsync_ctl_l;
8807         uint32_t tsync_ctl_h;
8808
8809         /* Stop the timesync system time. */
8810         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8811         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8812         /* Reset the timesync system time value. */
8813         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8814         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8815
8816         i40e_start_timecounters(dev);
8817
8818         /* Clear timesync registers. */
8819         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8820         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8821         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8822         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8823         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8824         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8825
8826         /* Enable timestamping of PTP packets. */
8827         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8828         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8829
8830         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8831         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8832         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8833
8834         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8835         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8836
8837         return 0;
8838 }
8839
8840 static int
8841 i40e_timesync_disable(struct rte_eth_dev *dev)
8842 {
8843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8844         uint32_t tsync_ctl_l;
8845         uint32_t tsync_ctl_h;
8846
8847         /* Disable timestamping of transmitted PTP packets. */
8848         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8849         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8850
8851         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8852         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8853
8854         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8855         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8856
8857         /* Reset the timesync increment value. */
8858         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8859         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8860
8861         return 0;
8862 }
8863
8864 static int
8865 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8866                                 struct timespec *timestamp, uint32_t flags)
8867 {
8868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8869         struct i40e_adapter *adapter =
8870                 (struct i40e_adapter *)dev->data->dev_private;
8871
8872         uint32_t sync_status;
8873         uint32_t index = flags & 0x03;
8874         uint64_t rx_tstamp_cycles;
8875         uint64_t ns;
8876
8877         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8878         if ((sync_status & (1 << index)) == 0)
8879                 return -EINVAL;
8880
8881         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8882         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8883         *timestamp = rte_ns_to_timespec(ns);
8884
8885         return 0;
8886 }
8887
8888 static int
8889 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8890                                 struct timespec *timestamp)
8891 {
8892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8893         struct i40e_adapter *adapter =
8894                 (struct i40e_adapter *)dev->data->dev_private;
8895
8896         uint32_t sync_status;
8897         uint64_t tx_tstamp_cycles;
8898         uint64_t ns;
8899
8900         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8901         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8902                 return -EINVAL;
8903
8904         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8905         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8906         *timestamp = rte_ns_to_timespec(ns);
8907
8908         return 0;
8909 }
8910
8911 /*
8912  * i40e_parse_dcb_configure - parse dcb configure from user
8913  * @dev: the device being configured
8914  * @dcb_cfg: pointer of the result of parse
8915  * @*tc_map: bit map of enabled traffic classes
8916  *
8917  * Returns 0 on success, negative value on failure
8918  */
8919 static int
8920 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8921                          struct i40e_dcbx_config *dcb_cfg,
8922                          uint8_t *tc_map)
8923 {
8924         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8925         uint8_t i, tc_bw, bw_lf;
8926
8927         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8928
8929         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8930         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8931                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8932                 return -EINVAL;
8933         }
8934
8935         /* assume each tc has the same bw */
8936         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8937         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8938                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8939         /* to ensure the sum of tcbw is equal to 100 */
8940         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8941         for (i = 0; i < bw_lf; i++)
8942                 dcb_cfg->etscfg.tcbwtable[i]++;
8943
8944         /* assume each tc has the same Transmission Selection Algorithm */
8945         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8946                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8947
8948         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8949                 dcb_cfg->etscfg.prioritytable[i] =
8950                                 dcb_rx_conf->dcb_tc[i];
8951
8952         /* FW needs one App to configure HW */
8953         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8954         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8955         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8956         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8957
8958         if (dcb_rx_conf->nb_tcs == 0)
8959                 *tc_map = 1; /* tc0 only */
8960         else
8961                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8962
8963         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8964                 dcb_cfg->pfc.willing = 0;
8965                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8966                 dcb_cfg->pfc.pfcenable = *tc_map;
8967         }
8968         return 0;
8969 }
8970
8971
8972 static enum i40e_status_code
8973 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8974                               struct i40e_aqc_vsi_properties_data *info,
8975                               uint8_t enabled_tcmap)
8976 {
8977         enum i40e_status_code ret;
8978         int i, total_tc = 0;
8979         uint16_t qpnum_per_tc, bsf, qp_idx;
8980         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8981         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8982         uint16_t used_queues;
8983
8984         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8985         if (ret != I40E_SUCCESS)
8986                 return ret;
8987
8988         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8989                 if (enabled_tcmap & (1 << i))
8990                         total_tc++;
8991         }
8992         if (total_tc == 0)
8993                 total_tc = 1;
8994         vsi->enabled_tc = enabled_tcmap;
8995
8996         /* different VSI has different queues assigned */
8997         if (vsi->type == I40E_VSI_MAIN)
8998                 used_queues = dev_data->nb_rx_queues -
8999                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9000         else if (vsi->type == I40E_VSI_VMDQ2)
9001                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9002         else {
9003                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9004                 return I40E_ERR_NO_AVAILABLE_VSI;
9005         }
9006
9007         qpnum_per_tc = used_queues / total_tc;
9008         /* Number of queues per enabled TC */
9009         if (qpnum_per_tc == 0) {
9010                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9011                 return I40E_ERR_INVALID_QP_ID;
9012         }
9013         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9014                                 I40E_MAX_Q_PER_TC);
9015         bsf = rte_bsf32(qpnum_per_tc);
9016
9017         /**
9018          * Configure TC and queue mapping parameters, for enabled TC,
9019          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9020          * default queue will serve it.
9021          */
9022         qp_idx = 0;
9023         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9024                 if (vsi->enabled_tc & (1 << i)) {
9025                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9026                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9027                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9028                         qp_idx += qpnum_per_tc;
9029                 } else
9030                         info->tc_mapping[i] = 0;
9031         }
9032
9033         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9034         if (vsi->type == I40E_VSI_SRIOV) {
9035                 info->mapping_flags |=
9036                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9037                 for (i = 0; i < vsi->nb_qps; i++)
9038                         info->queue_mapping[i] =
9039                                 rte_cpu_to_le_16(vsi->base_queue + i);
9040         } else {
9041                 info->mapping_flags |=
9042                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9043                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9044         }
9045         info->valid_sections |=
9046                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9047
9048         return I40E_SUCCESS;
9049 }
9050
9051 /*
9052  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9053  * @veb: VEB to be configured
9054  * @tc_map: enabled TC bitmap
9055  *
9056  * Returns 0 on success, negative value on failure
9057  */
9058 static enum i40e_status_code
9059 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9060 {
9061         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9062         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9063         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9064         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9065         enum i40e_status_code ret = I40E_SUCCESS;
9066         int i;
9067         uint32_t bw_max;
9068
9069         /* Check if enabled_tc is same as existing or new TCs */
9070         if (veb->enabled_tc == tc_map)
9071                 return ret;
9072
9073         /* configure tc bandwidth */
9074         memset(&veb_bw, 0, sizeof(veb_bw));
9075         veb_bw.tc_valid_bits = tc_map;
9076         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9077         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9078                 if (tc_map & BIT_ULL(i))
9079                         veb_bw.tc_bw_share_credits[i] = 1;
9080         }
9081         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9082                                                    &veb_bw, NULL);
9083         if (ret) {
9084                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9085                                   " per TC failed = %d",
9086                                   hw->aq.asq_last_status);
9087                 return ret;
9088         }
9089
9090         memset(&ets_query, 0, sizeof(ets_query));
9091         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9092                                                    &ets_query, NULL);
9093         if (ret != I40E_SUCCESS) {
9094                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9095                                  " configuration %u", hw->aq.asq_last_status);
9096                 return ret;
9097         }
9098         memset(&bw_query, 0, sizeof(bw_query));
9099         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9100                                                   &bw_query, NULL);
9101         if (ret != I40E_SUCCESS) {
9102                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9103                                  " configuration %u", hw->aq.asq_last_status);
9104                 return ret;
9105         }
9106
9107         /* store and print out BW info */
9108         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9109         veb->bw_info.bw_max = ets_query.tc_bw_max;
9110         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9111         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9112         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9113                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9114                      I40E_16_BIT_WIDTH);
9115         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9116                 veb->bw_info.bw_ets_share_credits[i] =
9117                                 bw_query.tc_bw_share_credits[i];
9118                 veb->bw_info.bw_ets_credits[i] =
9119                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9120                 /* 4 bits per TC, 4th bit is reserved */
9121                 veb->bw_info.bw_ets_max[i] =
9122                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9123                                   RTE_LEN2MASK(3, uint8_t));
9124                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9125                             veb->bw_info.bw_ets_share_credits[i]);
9126                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9127                             veb->bw_info.bw_ets_credits[i]);
9128                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9129                             veb->bw_info.bw_ets_max[i]);
9130         }
9131
9132         veb->enabled_tc = tc_map;
9133
9134         return ret;
9135 }
9136
9137
9138 /*
9139  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9140  * @vsi: VSI to be configured
9141  * @tc_map: enabled TC bitmap
9142  *
9143  * Returns 0 on success, negative value on failure
9144  */
9145 static enum i40e_status_code
9146 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9147 {
9148         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9149         struct i40e_vsi_context ctxt;
9150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9151         enum i40e_status_code ret = I40E_SUCCESS;
9152         int i;
9153
9154         /* Check if enabled_tc is same as existing or new TCs */
9155         if (vsi->enabled_tc == tc_map)
9156                 return ret;
9157
9158         /* configure tc bandwidth */
9159         memset(&bw_data, 0, sizeof(bw_data));
9160         bw_data.tc_valid_bits = tc_map;
9161         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9162         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9163                 if (tc_map & BIT_ULL(i))
9164                         bw_data.tc_bw_credits[i] = 1;
9165         }
9166         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9167         if (ret) {
9168                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9169                         " per TC failed = %d",
9170                         hw->aq.asq_last_status);
9171                 goto out;
9172         }
9173         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9174                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9175
9176         /* Update Queue Pairs Mapping for currently enabled UPs */
9177         ctxt.seid = vsi->seid;
9178         ctxt.pf_num = hw->pf_id;
9179         ctxt.vf_num = 0;
9180         ctxt.uplink_seid = vsi->uplink_seid;
9181         ctxt.info = vsi->info;
9182         i40e_get_cap(hw);
9183         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9184         if (ret)
9185                 goto out;
9186
9187         /* Update the VSI after updating the VSI queue-mapping information */
9188         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9189         if (ret) {
9190                 PMD_INIT_LOG(ERR, "Failed to configure "
9191                             "TC queue mapping = %d",
9192                             hw->aq.asq_last_status);
9193                 goto out;
9194         }
9195         /* update the local VSI info with updated queue map */
9196         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9197                                         sizeof(vsi->info.tc_mapping));
9198         (void)rte_memcpy(&vsi->info.queue_mapping,
9199                         &ctxt.info.queue_mapping,
9200                 sizeof(vsi->info.queue_mapping));
9201         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9202         vsi->info.valid_sections = 0;
9203
9204         /* query and update current VSI BW information */
9205         ret = i40e_vsi_get_bw_config(vsi);
9206         if (ret) {
9207                 PMD_INIT_LOG(ERR,
9208                          "Failed updating vsi bw info, err %s aq_err %s",
9209                          i40e_stat_str(hw, ret),
9210                          i40e_aq_str(hw, hw->aq.asq_last_status));
9211                 goto out;
9212         }
9213
9214         vsi->enabled_tc = tc_map;
9215
9216 out:
9217         return ret;
9218 }
9219
9220 /*
9221  * i40e_dcb_hw_configure - program the dcb setting to hw
9222  * @pf: pf the configuration is taken on
9223  * @new_cfg: new configuration
9224  * @tc_map: enabled TC bitmap
9225  *
9226  * Returns 0 on success, negative value on failure
9227  */
9228 static enum i40e_status_code
9229 i40e_dcb_hw_configure(struct i40e_pf *pf,
9230                       struct i40e_dcbx_config *new_cfg,
9231                       uint8_t tc_map)
9232 {
9233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9234         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9235         struct i40e_vsi *main_vsi = pf->main_vsi;
9236         struct i40e_vsi_list *vsi_list;
9237         enum i40e_status_code ret;
9238         int i;
9239         uint32_t val;
9240
9241         /* Use the FW API if FW > v4.4*/
9242         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9243               (hw->aq.fw_maj_ver >= 5))) {
9244                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9245                                   " to configure DCB");
9246                 return I40E_ERR_FIRMWARE_API_VERSION;
9247         }
9248
9249         /* Check if need reconfiguration */
9250         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9251                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9252                 return I40E_SUCCESS;
9253         }
9254
9255         /* Copy the new config to the current config */
9256         *old_cfg = *new_cfg;
9257         old_cfg->etsrec = old_cfg->etscfg;
9258         ret = i40e_set_dcb_config(hw);
9259         if (ret) {
9260                 PMD_INIT_LOG(ERR,
9261                          "Set DCB Config failed, err %s aq_err %s\n",
9262                          i40e_stat_str(hw, ret),
9263                          i40e_aq_str(hw, hw->aq.asq_last_status));
9264                 return ret;
9265         }
9266         /* set receive Arbiter to RR mode and ETS scheme by default */
9267         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9268                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9269                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9270                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9271                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9272                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9273                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9274                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9275                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9276                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9277                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9278                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9279                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9280         }
9281         /* get local mib to check whether it is configured correctly */
9282         /* IEEE mode */
9283         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9284         /* Get Local DCB Config */
9285         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9286                                      &hw->local_dcbx_config);
9287
9288         /* if Veb is created, need to update TC of it at first */
9289         if (main_vsi->veb) {
9290                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9291                 if (ret)
9292                         PMD_INIT_LOG(WARNING,
9293                                  "Failed configuring TC for VEB seid=%d\n",
9294                                  main_vsi->veb->seid);
9295         }
9296         /* Update each VSI */
9297         i40e_vsi_config_tc(main_vsi, tc_map);
9298         if (main_vsi->veb) {
9299                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9300                         /* Beside main VSI and VMDQ VSIs, only enable default
9301                          * TC for other VSIs
9302                          */
9303                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9304                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9305                                                          tc_map);
9306                         else
9307                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9308                                                          I40E_DEFAULT_TCMAP);
9309                         if (ret)
9310                                 PMD_INIT_LOG(WARNING,
9311                                          "Failed configuring TC for VSI seid=%d\n",
9312                                          vsi_list->vsi->seid);
9313                         /* continue */
9314                 }
9315         }
9316         return I40E_SUCCESS;
9317 }
9318
9319 /*
9320  * i40e_dcb_init_configure - initial dcb config
9321  * @dev: device being configured
9322  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9323  *
9324  * Returns 0 on success, negative value on failure
9325  */
9326 static int
9327 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9328 {
9329         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9331         int ret = 0;
9332
9333         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9334                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9335                 return -ENOTSUP;
9336         }
9337
9338         /* DCB initialization:
9339          * Update DCB configuration from the Firmware and configure
9340          * LLDP MIB change event.
9341          */
9342         if (sw_dcb == TRUE) {
9343                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9344                 if (ret != I40E_SUCCESS)
9345                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9346
9347                 ret = i40e_init_dcb(hw);
9348                 /* if sw_dcb, lldp agent is stopped, the return from
9349                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9350                  * adminq status.
9351                  */
9352                 if (ret != I40E_SUCCESS &&
9353                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9354                         memset(&hw->local_dcbx_config, 0,
9355                                 sizeof(struct i40e_dcbx_config));
9356                         /* set dcb default configuration */
9357                         hw->local_dcbx_config.etscfg.willing = 0;
9358                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9359                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9360                         hw->local_dcbx_config.etscfg.tsatable[0] =
9361                                                 I40E_IEEE_TSA_ETS;
9362                         hw->local_dcbx_config.etsrec =
9363                                 hw->local_dcbx_config.etscfg;
9364                         hw->local_dcbx_config.pfc.willing = 0;
9365                         hw->local_dcbx_config.pfc.pfccap =
9366                                                 I40E_MAX_TRAFFIC_CLASS;
9367                         /* FW needs one App to configure HW */
9368                         hw->local_dcbx_config.numapps = 1;
9369                         hw->local_dcbx_config.app[0].selector =
9370                                                 I40E_APP_SEL_ETHTYPE;
9371                         hw->local_dcbx_config.app[0].priority = 3;
9372                         hw->local_dcbx_config.app[0].protocolid =
9373                                                 I40E_APP_PROTOID_FCOE;
9374                         ret = i40e_set_dcb_config(hw);
9375                         if (ret) {
9376                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9377                                         " err = %d, aq_err = %d.", ret,
9378                                           hw->aq.asq_last_status);
9379                                 return -ENOSYS;
9380                         }
9381                 } else {
9382                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9383                                           " aq_err = %d.", ret,
9384                                           hw->aq.asq_last_status);
9385                         return -ENOTSUP;
9386                 }
9387         } else {
9388                 ret = i40e_aq_start_lldp(hw, NULL);
9389                 if (ret != I40E_SUCCESS)
9390                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9391
9392                 ret = i40e_init_dcb(hw);
9393                 if (!ret) {
9394                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9395                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9396                                                   " DCBX offload.");
9397                                 return -ENOTSUP;
9398                         }
9399                 } else {
9400                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9401                                           " aq_err = %d.", ret,
9402                                           hw->aq.asq_last_status);
9403                         return -ENOTSUP;
9404                 }
9405         }
9406         return 0;
9407 }
9408
9409 /*
9410  * i40e_dcb_setup - setup dcb related config
9411  * @dev: device being configured
9412  *
9413  * Returns 0 on success, negative value on failure
9414  */
9415 static int
9416 i40e_dcb_setup(struct rte_eth_dev *dev)
9417 {
9418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9419         struct i40e_dcbx_config dcb_cfg;
9420         uint8_t tc_map = 0;
9421         int ret = 0;
9422
9423         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9424                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9425                 return -ENOTSUP;
9426         }
9427
9428         if (pf->vf_num != 0)
9429                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9430
9431         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9432         if (ret) {
9433                 PMD_INIT_LOG(ERR, "invalid dcb config");
9434                 return -EINVAL;
9435         }
9436         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9437         if (ret) {
9438                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9439                 return -ENOSYS;
9440         }
9441
9442         return 0;
9443 }
9444
9445 static int
9446 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9447                       struct rte_eth_dcb_info *dcb_info)
9448 {
9449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9451         struct i40e_vsi *vsi = pf->main_vsi;
9452         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9453         uint16_t bsf, tc_mapping;
9454         int i, j = 0;
9455
9456         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9457                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9458         else
9459                 dcb_info->nb_tcs = 1;
9460         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9461                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9462         for (i = 0; i < dcb_info->nb_tcs; i++)
9463                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9464
9465         /* get queue mapping if vmdq is disabled */
9466         if (!pf->nb_cfg_vmdq_vsi) {
9467                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9468                         if (!(vsi->enabled_tc & (1 << i)))
9469                                 continue;
9470                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9471                         dcb_info->tc_queue.tc_rxq[j][i].base =
9472                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9473                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9474                         dcb_info->tc_queue.tc_txq[j][i].base =
9475                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9476                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9477                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9478                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9479                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9480                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9481                 }
9482                 return 0;
9483         }
9484
9485         /* get queue mapping if vmdq is enabled */
9486         do {
9487                 vsi = pf->vmdq[j].vsi;
9488                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9489                         if (!(vsi->enabled_tc & (1 << i)))
9490                                 continue;
9491                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9492                         dcb_info->tc_queue.tc_rxq[j][i].base =
9493                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9494                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9495                         dcb_info->tc_queue.tc_txq[j][i].base =
9496                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9497                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9498                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9499                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9500                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9501                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9502                 }
9503                 j++;
9504         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9505         return 0;
9506 }
9507
9508 static int
9509 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9510 {
9511         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9513         uint16_t interval =
9514                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9515         uint16_t msix_intr;
9516
9517         msix_intr = intr_handle->intr_vec[queue_id];
9518         if (msix_intr == I40E_MISC_VEC_ID)
9519                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9520                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9521                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9522                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9523                                (interval <<
9524                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9525         else
9526                 I40E_WRITE_REG(hw,
9527                                I40E_PFINT_DYN_CTLN(msix_intr -
9528                                                    I40E_RX_VEC_START),
9529                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9530                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9531                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9532                                (interval <<
9533                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9534
9535         I40E_WRITE_FLUSH(hw);
9536         rte_intr_enable(&dev->pci_dev->intr_handle);
9537
9538         return 0;
9539 }
9540
9541 static int
9542 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9543 {
9544         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9546         uint16_t msix_intr;
9547
9548         msix_intr = intr_handle->intr_vec[queue_id];
9549         if (msix_intr == I40E_MISC_VEC_ID)
9550                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9551         else
9552                 I40E_WRITE_REG(hw,
9553                                I40E_PFINT_DYN_CTLN(msix_intr -
9554                                                    I40E_RX_VEC_START),
9555                                0);
9556         I40E_WRITE_FLUSH(hw);
9557
9558         return 0;
9559 }
9560
9561 static int i40e_get_regs(struct rte_eth_dev *dev,
9562                          struct rte_dev_reg_info *regs)
9563 {
9564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9565         uint32_t *ptr_data = regs->data;
9566         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9567         const struct i40e_reg_info *reg_info;
9568
9569         if (ptr_data == NULL) {
9570                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9571                 regs->width = sizeof(uint32_t);
9572                 return 0;
9573         }
9574
9575         /* The first few registers have to be read using AQ operations */
9576         reg_idx = 0;
9577         while (i40e_regs_adminq[reg_idx].name) {
9578                 reg_info = &i40e_regs_adminq[reg_idx++];
9579                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9580                         for (arr_idx2 = 0;
9581                                         arr_idx2 <= reg_info->count2;
9582                                         arr_idx2++) {
9583                                 reg_offset = arr_idx * reg_info->stride1 +
9584                                         arr_idx2 * reg_info->stride2;
9585                                 reg_offset += reg_info->base_addr;
9586                                 ptr_data[reg_offset >> 2] =
9587                                         i40e_read_rx_ctl(hw, reg_offset);
9588                         }
9589         }
9590
9591         /* The remaining registers can be read using primitives */
9592         reg_idx = 0;
9593         while (i40e_regs_others[reg_idx].name) {
9594                 reg_info = &i40e_regs_others[reg_idx++];
9595                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9596                         for (arr_idx2 = 0;
9597                                         arr_idx2 <= reg_info->count2;
9598                                         arr_idx2++) {
9599                                 reg_offset = arr_idx * reg_info->stride1 +
9600                                         arr_idx2 * reg_info->stride2;
9601                                 reg_offset += reg_info->base_addr;
9602                                 ptr_data[reg_offset >> 2] =
9603                                         I40E_READ_REG(hw, reg_offset);
9604                         }
9605         }
9606
9607         return 0;
9608 }
9609
9610 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9611 {
9612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9613
9614         /* Convert word count to byte count */
9615         return hw->nvm.sr_size << 1;
9616 }
9617
9618 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9619                            struct rte_dev_eeprom_info *eeprom)
9620 {
9621         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9622         uint16_t *data = eeprom->data;
9623         uint16_t offset, length, cnt_words;
9624         int ret_code;
9625
9626         offset = eeprom->offset >> 1;
9627         length = eeprom->length >> 1;
9628         cnt_words = length;
9629
9630         if (offset > hw->nvm.sr_size ||
9631                 offset + length > hw->nvm.sr_size) {
9632                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9633                 return -EINVAL;
9634         }
9635
9636         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9637
9638         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9639         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9640                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9641                 return -EIO;
9642         }
9643
9644         return 0;
9645 }
9646
9647 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9648                                       struct ether_addr *mac_addr)
9649 {
9650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9651
9652         if (!is_valid_assigned_ether_addr(mac_addr)) {
9653                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9654                 return;
9655         }
9656
9657         /* Flags: 0x3 updates port address */
9658         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9659 }
9660
9661 static int
9662 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9663 {
9664         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9665         struct rte_eth_dev_data *dev_data = pf->dev_data;
9666         uint32_t frame_size = mtu + ETHER_HDR_LEN
9667                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9668         int ret = 0;
9669
9670         /* check if mtu is within the allowed range */
9671         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9672                 return -EINVAL;
9673
9674         /* mtu setting is forbidden if port is start */
9675         if (dev_data->dev_started) {
9676                 PMD_DRV_LOG(ERR,
9677                             "port %d must be stopped before configuration\n",
9678                             dev_data->port_id);
9679                 return -EBUSY;
9680         }
9681
9682         if (frame_size > ETHER_MAX_LEN)
9683                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9684         else
9685                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9686
9687         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9688
9689         return ret;
9690 }