drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 144 static int i40e_dev_configure(struct rte_eth_dev *dev);
 145 static int i40e_dev_start(struct rte_eth_dev *dev);
 146 static void i40e_dev_stop(struct rte_eth_dev *dev);
 147 static void i40e_dev_close(struct rte_eth_dev *dev);
 148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_stats *stats);
 156 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 157                                struct rte_eth_xstats *xstats, unsigned n);
 158 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 161                                             uint16_t queue_id,
 162                                             uint8_t stat_idx,
 163                                             uint8_t is_rx);
 164 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 165                               struct rte_eth_dev_info *dev_info);
 166 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 167                                 uint16_t vlan_id,
 168                                 int on);
 169 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 170 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 171 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 172                                       uint16_t queue,
 173                                       int on);
 174 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 175 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 176 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 177 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 178                               struct rte_eth_fc_conf *fc_conf);
 179 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 180                               struct rte_eth_fc_conf *fc_conf);
 181 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                        struct rte_eth_pfc_conf *pfc_conf);
 183 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 184                           struct ether_addr *mac_addr,
 185                           uint32_t index,
 186                           uint32_t pool);
 187 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 188 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 189                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                     uint16_t reta_size);
 191 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 192                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 193                                    uint16_t reta_size);
 194
 195 static int i40e_get_cap(struct i40e_hw *hw);
 196 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 197 static int i40e_pf_setup(struct i40e_pf *pf);
 198 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 199 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 200 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 201 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 202 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 203                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 204 static void i40e_stat_update_48(struct i40e_hw *hw,
 205                                uint32_t hireg,
 206                                uint32_t loreg,
 207                                bool offset_loaded,
 208                                uint64_t *offset,
 209                                uint64_t *stat);
 210 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 211 static void i40e_dev_interrupt_handler(
 212                 __rte_unused struct rte_intr_handle *handle, void *param);
 213 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 214                                 uint32_t base, uint32_t num);
 215 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 216 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 217                         uint32_t base);
 218 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 219                         uint16_t num);
 220 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 221 static int i40e_veb_release(struct i40e_veb *veb);
 222 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 223                                                 struct i40e_vsi *vsi);
 224 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 225 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 226 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 227                                              struct i40e_macvlan_filter *mv_f,
 228                                              int num,
 229                                              struct ether_addr *addr);
 230 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 231                                              struct i40e_macvlan_filter *mv_f,
 232                                              int num,
 233                                              uint16_t vlan);
 234 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 235 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 236                                     struct rte_eth_rss_conf *rss_conf);
 237 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 238                                       struct rte_eth_rss_conf *rss_conf);
 239 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 240                                 struct rte_eth_udp_tunnel *udp_tunnel);
 241 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 242                                 struct rte_eth_udp_tunnel *udp_tunnel);
 243 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 244                         struct rte_eth_ethertype_filter *filter,
 245                         bool add);
 246 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 247                                 enum rte_filter_op filter_op,
 248                                 void *arg);
 249 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 250                                 enum rte_filter_type filter_type,
 251                                 enum rte_filter_op filter_op,
 252                                 void *arg);
 253 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 254                                   struct rte_eth_dcb_info *dcb_info);
 255 static void i40e_configure_registers(struct i40e_hw *hw);
 256 static void i40e_hw_init(struct i40e_hw *hw);
 257 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 258 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 259                         struct rte_eth_mirror_conf *mirror_conf,
 260                         uint8_t sw_id, uint8_t on);
 261 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 262
 263 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 264 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 265 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 266                                            struct timespec *timestamp,
 267                                            uint32_t flags);
 268 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 269                                            struct timespec *timestamp);
 270 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 271
 272
 273 static const struct rte_pci_id pci_id_i40e_map[] = {
 274 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 275 #include "rte_pci_dev_ids.h"
 276 { .vendor_id = 0, /* sentinel */ },
 277 };
 278
 279 static const struct eth_dev_ops i40e_eth_dev_ops = {
 280         .dev_configure                = i40e_dev_configure,
 281         .dev_start                    = i40e_dev_start,
 282         .dev_stop                     = i40e_dev_stop,
 283         .dev_close                    = i40e_dev_close,
 284         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 285         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 286         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 287         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 288         .dev_set_link_up              = i40e_dev_set_link_up,
 289         .dev_set_link_down            = i40e_dev_set_link_down,
 290         .link_update                  = i40e_dev_link_update,
 291         .stats_get                    = i40e_dev_stats_get,
 292         .xstats_get                   = i40e_dev_xstats_get,
 293         .stats_reset                  = i40e_dev_stats_reset,
 294         .xstats_reset                 = i40e_dev_xstats_reset,
 295         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 296         .dev_infos_get                = i40e_dev_info_get,
 297         .vlan_filter_set              = i40e_vlan_filter_set,
 298         .vlan_tpid_set                = i40e_vlan_tpid_set,
 299         .vlan_offload_set             = i40e_vlan_offload_set,
 300         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 301         .vlan_pvid_set                = i40e_vlan_pvid_set,
 302         .rx_queue_start               = i40e_dev_rx_queue_start,
 303         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 304         .tx_queue_start               = i40e_dev_tx_queue_start,
 305         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 306         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 307         .rx_queue_release             = i40e_dev_rx_queue_release,
 308         .rx_queue_count               = i40e_dev_rx_queue_count,
 309         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 310         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 311         .tx_queue_release             = i40e_dev_tx_queue_release,
 312         .dev_led_on                   = i40e_dev_led_on,
 313         .dev_led_off                  = i40e_dev_led_off,
 314         .flow_ctrl_get                = i40e_flow_ctrl_get,
 315         .flow_ctrl_set                = i40e_flow_ctrl_set,
 316         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 317         .mac_addr_add                 = i40e_macaddr_add,
 318         .mac_addr_remove              = i40e_macaddr_remove,
 319         .reta_update                  = i40e_dev_rss_reta_update,
 320         .reta_query                   = i40e_dev_rss_reta_query,
 321         .rss_hash_update              = i40e_dev_rss_hash_update,
 322         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 323         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 324         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 325         .filter_ctrl                  = i40e_dev_filter_ctrl,
 326         .rxq_info_get                 = i40e_rxq_info_get,
 327         .txq_info_get                 = i40e_txq_info_get,
 328         .mirror_rule_set              = i40e_mirror_rule_set,
 329         .mirror_rule_reset            = i40e_mirror_rule_reset,
 330         .timesync_enable              = i40e_timesync_enable,
 331         .timesync_disable             = i40e_timesync_disable,
 332         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 333         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 334         .get_dcb_info                 = i40e_dev_get_dcb_info,
 335 };
 336
 337 /* store statistics names and its offset in stats structure */
 338 struct rte_i40e_xstats_name_off {
 339         char name[RTE_ETH_XSTATS_NAME_SIZE];
 340         unsigned offset;
 341 };
 342
 343 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 344         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 345         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 346         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 347         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 348         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 349                 rx_unknown_protocol)},
 350         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 351         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 352         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 353         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 354 };
 355
 356 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 357         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 358                 tx_dropped_link_down)},
 359         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 360         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 361                 illegal_bytes)},
 362         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 363         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 364                 mac_local_faults)},
 365         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 366                 mac_remote_faults)},
 367         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 368                 rx_length_errors)},
 369         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 370         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 371         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 372         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 373         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 374         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 375                 rx_size_127)},
 376         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 377                 rx_size_255)},
 378         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 379                 rx_size_511)},
 380         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 381                 rx_size_1023)},
 382         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 383                 rx_size_1522)},
 384         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 385                 rx_size_big)},
 386         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 387                 rx_undersize)},
 388         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 389                 rx_oversize)},
 390         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 391                 mac_short_packet_dropped)},
 392         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 393                 rx_fragments)},
 394         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 395         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 396         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 397                 tx_size_127)},
 398         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 399                 tx_size_255)},
 400         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 401                 tx_size_511)},
 402         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 403                 tx_size_1023)},
 404         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 405                 tx_size_1522)},
 406         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 407                 tx_size_big)},
 408         {"rx_flow_director_atr_match_packets",
 409                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 410         {"rx_flow_director_sb_match_packets",
 411                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 412         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 413                 tx_lpi_status)},
 414         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 415                 rx_lpi_status)},
 416         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 417                 tx_lpi_count)},
 418         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 419                 rx_lpi_count)},
 420 };
 421
 422 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 423 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 424
 425 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 426                 sizeof(rte_i40e_stats_strings[0]))
 427 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 428                 sizeof(rte_i40e_hw_port_strings[0]))
 429 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 430                 I40E_NB_HW_PORT_Q_STATS)
 431
 432 static struct eth_driver rte_i40e_pmd = {
 433         .pci_drv = {
 434                 .name = "rte_i40e_pmd",
 435                 .id_table = pci_id_i40e_map,
 436                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 437                         RTE_PCI_DRV_DETACHABLE,
 438         },
 439         .eth_dev_init = eth_i40e_dev_init,
 440         .eth_dev_uninit = eth_i40e_dev_uninit,
 441         .dev_private_size = sizeof(struct i40e_adapter),
 442 };
 443
 444 static inline int
 445 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 446                                      struct rte_eth_link *link)
 447 {
 448         struct rte_eth_link *dst = link;
 449         struct rte_eth_link *src = &(dev->data->dev_link);
 450
 451         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 452                                         *(uint64_t *)src) == 0)
 453                 return -1;
 454
 455         return 0;
 456 }
 457
 458 static inline int
 459 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 460                                       struct rte_eth_link *link)
 461 {
 462         struct rte_eth_link *dst = &(dev->data->dev_link);
 463         struct rte_eth_link *src = link;
 464
 465         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 466                                         *(uint64_t *)src) == 0)
 467                 return -1;
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * Driver initialization routine.
 474  * Invoked once at EAL init time.
 475  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 476  */
 477 static int
 478 rte_i40e_pmd_init(const char *name __rte_unused,
 479                   const char *params __rte_unused)
 480 {
 481         PMD_INIT_FUNC_TRACE();
 482         rte_eth_driver_register(&rte_i40e_pmd);
 483
 484         return 0;
 485 }
 486
 487 static struct rte_driver rte_i40e_driver = {
 488         .type = PMD_PDEV,
 489         .init = rte_i40e_pmd_init,
 490 };
 491
 492 PMD_REGISTER_DRIVER(rte_i40e_driver);
 493
 494 /*
 495  * Initialize registers for flexible payload, which should be set by NVM.
 496  * This should be removed from code once it is fixed in NVM.
 497  */
 498 #ifndef I40E_GLQF_ORT
 499 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 500 #endif
 501 #ifndef I40E_GLQF_PIT
 502 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 503 #endif
 504
 505 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 506 {
 507         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 508         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 509         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 510         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 511         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 512         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 513         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 514         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 515         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 516         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 517
 518         /* GLQF_PIT Registers */
 519         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 520         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 521 }
 522
 523 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 524
 525 /*
 526  * Add a ethertype filter to drop all flow control frames transmitted
 527  * from VSIs.
 528 */
 529 static void
 530 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 531 {
 532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 533         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 534                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 535                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 536         int ret;
 537
 538         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 539                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 540                                 pf->main_vsi_seid, 0,
 541                                 TRUE, NULL, NULL);
 542         if (ret)
 543                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 544                                   " frames from VSIs.");
 545 }
 546
 547 static int
 548 eth_i40e_dev_init(struct rte_eth_dev *dev)
 549 {
 550         struct rte_pci_device *pci_dev;
 551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553         struct i40e_vsi *vsi;
 554         int ret;
 555         uint32_t len;
 556         uint8_t aq_fail = 0;
 557
 558         PMD_INIT_FUNC_TRACE();
 559
 560         dev->dev_ops = &i40e_eth_dev_ops;
 561         dev->rx_pkt_burst = i40e_recv_pkts;
 562         dev->tx_pkt_burst = i40e_xmit_pkts;
 563
 564         /* for secondary processes, we don't initialise any further as primary
 565          * has already done this work. Only check we don't need a different
 566          * RX function */
 567         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 568                 i40e_set_rx_function(dev);
 569                 i40e_set_tx_function(dev);
 570                 return 0;
 571         }
 572         pci_dev = dev->pci_dev;
 573
 574         rte_eth_copy_pci_info(dev, pci_dev);
 575
 576         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 577         pf->adapter->eth_dev = dev;
 578         pf->dev_data = dev->data;
 579
 580         hw->back = I40E_PF_TO_ADAPTER(pf);
 581         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 582         if (!hw->hw_addr) {
 583                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 584                              "as address is NULL");
 585                 return -ENODEV;
 586         }
 587
 588         hw->vendor_id = pci_dev->id.vendor_id;
 589         hw->device_id = pci_dev->id.device_id;
 590         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 591         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 592         hw->bus.device = pci_dev->addr.devid;
 593         hw->bus.func = pci_dev->addr.function;
 594         hw->adapter_stopped = 0;
 595
 596         /* Make sure all is clean before doing PF reset */
 597         i40e_clear_hw(hw);
 598
 599         /* Initialize the hardware */
 600         i40e_hw_init(hw);
 601
 602         /* Reset here to make sure all is clean for each PF */
 603         ret = i40e_pf_reset(hw);
 604         if (ret) {
 605                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 606                 return ret;
 607         }
 608
 609         /* Initialize the shared code (base driver) */
 610         ret = i40e_init_shared_code(hw);
 611         if (ret) {
 612                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 613                 return ret;
 614         }
 615
 616         /*
 617          * To work around the NVM issue,initialize registers
 618          * for flexible payload by software.
 619          * It should be removed once issues are fixed in NVM.
 620          */
 621         i40e_flex_payload_reg_init(hw);
 622
 623         /* Initialize the parameters for adminq */
 624         i40e_init_adminq_parameter(hw);
 625         ret = i40e_init_adminq(hw);
 626         if (ret != I40E_SUCCESS) {
 627                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 628                 return -EIO;
 629         }
 630         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 631                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 632                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 633                      ((hw->nvm.version >> 12) & 0xf),
 634                      ((hw->nvm.version >> 4) & 0xff),
 635                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 636
 637         /* Clear PXE mode */
 638         i40e_clear_pxe_mode(hw);
 639
 640         /*
 641          * On X710, performance number is far from the expectation on recent
 642          * firmware versions. The fix for this issue may not be integrated in
 643          * the following firmware version. So the workaround in software driver
 644          * is needed. It needs to modify the initial values of 3 internal only
 645          * registers. Note that the workaround can be removed when it is fixed
 646          * in firmware in the future.
 647          */
 648         i40e_configure_registers(hw);
 649
 650         /* Get hw capabilities */
 651         ret = i40e_get_cap(hw);
 652         if (ret != I40E_SUCCESS) {
 653                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 654                 goto err_get_capabilities;
 655         }
 656
 657         /* Initialize parameters for PF */
 658         ret = i40e_pf_parameter_init(dev);
 659         if (ret != 0) {
 660                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 661                 goto err_parameter_init;
 662         }
 663
 664         /* Initialize the queue management */
 665         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 666         if (ret < 0) {
 667                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 668                 goto err_qp_pool_init;
 669         }
 670         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 671                                 hw->func_caps.num_msix_vectors - 1);
 672         if (ret < 0) {
 673                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 674                 goto err_msix_pool_init;
 675         }
 676
 677         /* Initialize lan hmc */
 678         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 679                                 hw->func_caps.num_rx_qp, 0, 0);
 680         if (ret != I40E_SUCCESS) {
 681                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 682                 goto err_init_lan_hmc;
 683         }
 684
 685         /* Configure lan hmc */
 686         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 687         if (ret != I40E_SUCCESS) {
 688                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 689                 goto err_configure_lan_hmc;
 690         }
 691
 692         /* Get and check the mac address */
 693         i40e_get_mac_addr(hw, hw->mac.addr);
 694         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 695                 PMD_INIT_LOG(ERR, "mac address is not valid");
 696                 ret = -EIO;
 697                 goto err_get_mac_addr;
 698         }
 699         /* Copy the permanent MAC address */
 700         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 701                         (struct ether_addr *) hw->mac.perm_addr);
 702
 703         /* Disable flow control */
 704         hw->fc.requested_mode = I40E_FC_NONE;
 705         i40e_set_fc(hw, &aq_fail, TRUE);
 706
 707         /* PF setup, which includes VSI setup */
 708         ret = i40e_pf_setup(pf);
 709         if (ret) {
 710                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 711                 goto err_setup_pf_switch;
 712         }
 713
 714         vsi = pf->main_vsi;
 715
 716         /* Disable double vlan by default */
 717         i40e_vsi_config_double_vlan(vsi, FALSE);
 718
 719         if (!vsi->max_macaddrs)
 720                 len = ETHER_ADDR_LEN;
 721         else
 722                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 723
 724         /* Should be after VSI initialized */
 725         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 726         if (!dev->data->mac_addrs) {
 727                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 728                                         "for storing mac address");
 729                 goto err_mac_alloc;
 730         }
 731         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 732                                         &dev->data->mac_addrs[0]);
 733
 734         /* initialize pf host driver to setup SRIOV resource if applicable */
 735         i40e_pf_host_init(dev);
 736
 737         /* register callback func to eal lib */
 738         rte_intr_callback_register(&(pci_dev->intr_handle),
 739                 i40e_dev_interrupt_handler, (void *)dev);
 740
 741         /* configure and enable device interrupt */
 742         i40e_pf_config_irq0(hw);
 743         i40e_pf_enable_irq0(hw);
 744
 745         /* enable uio intr after callback register */
 746         rte_intr_enable(&(pci_dev->intr_handle));
 747         /*
 748          * Add an ethertype filter to drop all flow control frames transmitted
 749          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 750          * frames to wire.
 751          */
 752         i40e_add_tx_flow_control_drop_filter(pf);
 753
 754         /* initialize mirror rule list */
 755         TAILQ_INIT(&pf->mirror_list);
 756
 757         /* Init dcb to sw mode by default */
 758         ret = i40e_dcb_init_configure(dev, TRUE);
 759         if (ret != I40E_SUCCESS) {
 760                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 761                 pf->flags &= ~I40E_FLAG_DCB;
 762         }
 763
 764         return 0;
 765
 766 err_mac_alloc:
 767         i40e_vsi_release(pf->main_vsi);
 768 err_setup_pf_switch:
 769 err_get_mac_addr:
 770 err_configure_lan_hmc:
 771         (void)i40e_shutdown_lan_hmc(hw);
 772 err_init_lan_hmc:
 773         i40e_res_pool_destroy(&pf->msix_pool);
 774 err_msix_pool_init:
 775         i40e_res_pool_destroy(&pf->qp_pool);
 776 err_qp_pool_init:
 777 err_parameter_init:
 778 err_get_capabilities:
 779         (void)i40e_shutdown_adminq(hw);
 780
 781         return ret;
 782 }
 783
 784 static int
 785 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 786 {
 787         struct rte_pci_device *pci_dev;
 788         struct i40e_hw *hw;
 789         struct i40e_filter_control_settings settings;
 790         int ret;
 791         uint8_t aq_fail = 0;
 792
 793         PMD_INIT_FUNC_TRACE();
 794
 795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 796                 return 0;
 797
 798         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 799         pci_dev = dev->pci_dev;
 800
 801         if (hw->adapter_stopped == 0)
 802                 i40e_dev_close(dev);
 803
 804         dev->dev_ops = NULL;
 805         dev->rx_pkt_burst = NULL;
 806         dev->tx_pkt_burst = NULL;
 807
 808         /* Disable LLDP */
 809         ret = i40e_aq_stop_lldp(hw, true, NULL);
 810         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 811                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 812
 813         /* Clear PXE mode */
 814         i40e_clear_pxe_mode(hw);
 815
 816         /* Unconfigure filter control */
 817         memset(&settings, 0, sizeof(settings));
 818         ret = i40e_set_filter_control(hw, &settings);
 819         if (ret)
 820                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 821                                         ret);
 822
 823         /* Disable flow control */
 824         hw->fc.requested_mode = I40E_FC_NONE;
 825         i40e_set_fc(hw, &aq_fail, TRUE);
 826
 827         /* uninitialize pf host driver */
 828         i40e_pf_host_uninit(dev);
 829
 830         rte_free(dev->data->mac_addrs);
 831         dev->data->mac_addrs = NULL;
 832
 833         /* disable uio intr before callback unregister */
 834         rte_intr_disable(&(pci_dev->intr_handle));
 835
 836         /* register callback func to eal lib */
 837         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 838                 i40e_dev_interrupt_handler, (void *)dev);
 839
 840         return 0;
 841 }
 842
 843 static int
 844 i40e_dev_configure(struct rte_eth_dev *dev)
 845 {
 846         struct i40e_adapter *ad =
 847                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 850         int i, ret;
 851
 852         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 853          * bulk allocation or vector Rx preconditions we will reset it.
 854          */
 855         ad->rx_bulk_alloc_allowed = true;
 856         ad->rx_vec_allowed = true;
 857         ad->tx_simple_allowed = true;
 858         ad->tx_vec_allowed = true;
 859
 860         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 861                 ret = i40e_fdir_setup(pf);
 862                 if (ret != I40E_SUCCESS) {
 863                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 864                         return -ENOTSUP;
 865                 }
 866                 ret = i40e_fdir_configure(dev);
 867                 if (ret < 0) {
 868                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 869                         goto err;
 870                 }
 871         } else
 872                 i40e_fdir_teardown(pf);
 873
 874         ret = i40e_dev_init_vlan(dev);
 875         if (ret < 0)
 876                 goto err;
 877
 878         /* VMDQ setup.
 879          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 880          *  RSS setting have different requirements.
 881          *  General PMD driver call sequence are NIC init, configure,
 882          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 883          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 884          *  applicable. So, VMDQ setting has to be done before
 885          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 886          *  For RSS setting, it will try to calculate actual configured RX queue
 887          *  number, which will be available after rx_queue_setup(). dev_start()
 888          *  function is good to place RSS setup.
 889          */
 890         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 891                 ret = i40e_vmdq_setup(dev);
 892                 if (ret)
 893                         goto err;
 894         }
 895
 896         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
 897                 ret = i40e_dcb_setup(dev);
 898                 if (ret) {
 899                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
 900                         goto err_dcb;
 901                 }
 902         }
 903
 904         return 0;
 905
 906 err_dcb:
 907         /* need to release vmdq resource if exists */
 908         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 909                 i40e_vsi_release(pf->vmdq[i].vsi);
 910                 pf->vmdq[i].vsi = NULL;
 911         }
 912         rte_free(pf->vmdq);
 913         pf->vmdq = NULL;
 914 err:
 915         /* need to release fdir resource if exists */
 916         i40e_fdir_teardown(pf);
 917         return ret;
 918 }
 919
 920 void
 921 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 922 {
 923         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 924         uint16_t msix_vect = vsi->msix_intr;
 925         uint16_t i;
 926
 927         for (i = 0; i < vsi->nb_qps; i++) {
 928                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 930                 rte_wmb();
 931         }
 932
 933         if (vsi->type != I40E_VSI_SRIOV) {
 934                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 935                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 936                                 msix_vect - 1), 0);
 937         } else {
 938                 uint32_t reg;
 939                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 940                         vsi->user_param + (msix_vect - 1);
 941
 942                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 943         }
 944         I40E_WRITE_FLUSH(hw);
 945 }
 946
 947 static inline uint16_t
 948 i40e_calc_itr_interval(int16_t interval)
 949 {
 950         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 951                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 952
 953         /* Convert to hardware count, as writing each 1 represents 2 us */
 954         return (interval/2);
 955 }
 956
 957 void
 958 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 959 {
 960         uint32_t val;
 961         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 962         uint16_t msix_vect = vsi->msix_intr;
 963         int i;
 964
 965         for (i = 0; i < vsi->nb_qps; i++)
 966                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 967
 968         /* Bind all RX queues to allocated MSIX interrupt */
 969         for (i = 0; i < vsi->nb_qps; i++) {
 970                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 971                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 972                         ((vsi->base_queue + i + 1) <<
 973                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 974                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 975                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 976
 977                 if (i == vsi->nb_qps - 1)
 978                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 979                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 980         }
 981
 982         /* Write first RX queue to Link list register as the head element */
 983         if (vsi->type != I40E_VSI_SRIOV) {
 984                 uint16_t interval =
 985                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 986
 987                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 988                                                 (vsi->base_queue <<
 989                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 990                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 991
 992                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 993                                                 msix_vect - 1), interval);
 994
 995 #ifndef I40E_GLINT_CTL
 996 #define I40E_GLINT_CTL                     0x0003F800
 997 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 998 #endif
 999                 /* Disable auto-mask on enabling of all none-zero  interrupt */
1000                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
1001                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1002         } else {
1003                 uint32_t reg;
1004
1005                 /* num_msix_vectors_vf needs to minus irq0 */
1006                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1007                         vsi->user_param + (msix_vect - 1);
1008
1009                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1010                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1011                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1012         }
1013
1014         I40E_WRITE_FLUSH(hw);
1015 }
1016
1017 static void
1018 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1019 {
1020         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1021         uint16_t interval = i40e_calc_itr_interval(\
1022                         RTE_LIBRTE_I40E_ITR_INTERVAL);
1023
1024         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1025                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
1026                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1027                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1028                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1029 }
1030
1031 static void
1032 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1033 {
1034         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1035
1036         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1037 }
1038
1039 static inline uint8_t
1040 i40e_parse_link_speed(uint16_t eth_link_speed)
1041 {
1042         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1043
1044         switch (eth_link_speed) {
1045         case ETH_LINK_SPEED_40G:
1046                 link_speed = I40E_LINK_SPEED_40GB;
1047                 break;
1048         case ETH_LINK_SPEED_20G:
1049                 link_speed = I40E_LINK_SPEED_20GB;
1050                 break;
1051         case ETH_LINK_SPEED_10G:
1052                 link_speed = I40E_LINK_SPEED_10GB;
1053                 break;
1054         case ETH_LINK_SPEED_1000:
1055                 link_speed = I40E_LINK_SPEED_1GB;
1056                 break;
1057         case ETH_LINK_SPEED_100:
1058                 link_speed = I40E_LINK_SPEED_100MB;
1059                 break;
1060         }
1061
1062         return link_speed;
1063 }
1064
1065 static int
1066 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1067 {
1068         enum i40e_status_code status;
1069         struct i40e_aq_get_phy_abilities_resp phy_ab;
1070         struct i40e_aq_set_phy_config phy_conf;
1071         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1072                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1073                         I40E_AQ_PHY_FLAG_LOW_POWER;
1074         const uint8_t advt = I40E_LINK_SPEED_40GB |
1075                         I40E_LINK_SPEED_10GB |
1076                         I40E_LINK_SPEED_1GB |
1077                         I40E_LINK_SPEED_100MB;
1078         int ret = -ENOTSUP;
1079
1080         /* Skip it on 40G interfaces, as a workaround for the link issue */
1081         if (i40e_is_40G_device(hw->device_id))
1082                 return I40E_SUCCESS;
1083
1084         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1085                                               NULL);
1086         if (status)
1087                 return ret;
1088
1089         memset(&phy_conf, 0, sizeof(phy_conf));
1090
1091         /* bits 0-2 use the values from get_phy_abilities_resp */
1092         abilities &= ~mask;
1093         abilities |= phy_ab.abilities & mask;
1094
1095         /* update ablities and speed */
1096         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1097                 phy_conf.link_speed = advt;
1098         else
1099                 phy_conf.link_speed = force_speed;
1100
1101         phy_conf.abilities = abilities;
1102
1103         /* use get_phy_abilities_resp value for the rest */
1104         phy_conf.phy_type = phy_ab.phy_type;
1105         phy_conf.eee_capability = phy_ab.eee_capability;
1106         phy_conf.eeer = phy_ab.eeer_val;
1107         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1108
1109         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1110                     phy_ab.abilities, phy_ab.link_speed);
1111         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1112                     phy_conf.abilities, phy_conf.link_speed);
1113
1114         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1115         if (status)
1116                 return ret;
1117
1118         return I40E_SUCCESS;
1119 }
1120
1121 static int
1122 i40e_apply_link_speed(struct rte_eth_dev *dev)
1123 {
1124         uint8_t speed;
1125         uint8_t abilities = 0;
1126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct rte_eth_conf *conf = &dev->data->dev_conf;
1128
1129         speed = i40e_parse_link_speed(conf->link_speed);
1130         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1131         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1132                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1133         else
1134                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1135
1136         return i40e_phy_conf_link(hw, abilities, speed);
1137 }
1138
1139 static int
1140 i40e_dev_start(struct rte_eth_dev *dev)
1141 {
1142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1144         struct i40e_vsi *main_vsi = pf->main_vsi;
1145         int ret, i;
1146
1147         hw->adapter_stopped = 0;
1148
1149         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1150                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1151                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1152                              dev->data->dev_conf.link_duplex,
1153                              dev->data->port_id);
1154                 return -EINVAL;
1155         }
1156
1157         /* Initialize VSI */
1158         ret = i40e_dev_rxtx_init(pf);
1159         if (ret != I40E_SUCCESS) {
1160                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1161                 goto err_up;
1162         }
1163
1164         /* Map queues with MSIX interrupt */
1165         i40e_vsi_queues_bind_intr(main_vsi);
1166         i40e_vsi_enable_queues_intr(main_vsi);
1167
1168         /* Map VMDQ VSI queues with MSIX interrupt */
1169         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1170                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1171                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1172         }
1173
1174         /* enable FDIR MSIX interrupt */
1175         if (pf->fdir.fdir_vsi) {
1176                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1177                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1178         }
1179
1180         /* Enable all queues which have been configured */
1181         ret = i40e_dev_switch_queues(pf, TRUE);
1182         if (ret != I40E_SUCCESS) {
1183                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1184                 goto err_up;
1185         }
1186
1187         /* Enable receiving broadcast packets */
1188         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1189         if (ret != I40E_SUCCESS)
1190                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1191
1192         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1193                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1194                                                 true, NULL);
1195                 if (ret != I40E_SUCCESS)
1196                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1197         }
1198
1199         /* Apply link configure */
1200         ret = i40e_apply_link_speed(dev);
1201         if (I40E_SUCCESS != ret) {
1202                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1203                 goto err_up;
1204         }
1205
1206         return I40E_SUCCESS;
1207
1208 err_up:
1209         i40e_dev_switch_queues(pf, FALSE);
1210         i40e_dev_clear_queues(dev);
1211
1212         return ret;
1213 }
1214
1215 static void
1216 i40e_dev_stop(struct rte_eth_dev *dev)
1217 {
1218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1219         struct i40e_vsi *main_vsi = pf->main_vsi;
1220         struct i40e_mirror_rule *p_mirror;
1221         int i;
1222
1223         /* Disable all queues */
1224         i40e_dev_switch_queues(pf, FALSE);
1225
1226         /* un-map queues with interrupt registers */
1227         i40e_vsi_disable_queues_intr(main_vsi);
1228         i40e_vsi_queues_unbind_intr(main_vsi);
1229
1230         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1231                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1232                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1233         }
1234
1235         if (pf->fdir.fdir_vsi) {
1236                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1237                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1238         }
1239         /* Clear all queues and release memory */
1240         i40e_dev_clear_queues(dev);
1241
1242         /* Set link down */
1243         i40e_dev_set_link_down(dev);
1244
1245         /* Remove all mirror rules */
1246         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1247                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1248                 rte_free(p_mirror);
1249         }
1250         pf->nb_mirror_rule = 0;
1251
1252 }
1253
1254 static void
1255 i40e_dev_close(struct rte_eth_dev *dev)
1256 {
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259         uint32_t reg;
1260         int i;
1261
1262         PMD_INIT_FUNC_TRACE();
1263
1264         i40e_dev_stop(dev);
1265         hw->adapter_stopped = 1;
1266         i40e_dev_free_queues(dev);
1267
1268         /* Disable interrupt */
1269         i40e_pf_disable_irq0(hw);
1270         rte_intr_disable(&(dev->pci_dev->intr_handle));
1271
1272         /* shutdown and destroy the HMC */
1273         i40e_shutdown_lan_hmc(hw);
1274
1275         /* release all the existing VSIs and VEBs */
1276         i40e_fdir_teardown(pf);
1277         i40e_vsi_release(pf->main_vsi);
1278
1279         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1280                 i40e_vsi_release(pf->vmdq[i].vsi);
1281                 pf->vmdq[i].vsi = NULL;
1282         }
1283
1284         rte_free(pf->vmdq);
1285         pf->vmdq = NULL;
1286
1287         /* shutdown the adminq */
1288         i40e_aq_queue_shutdown(hw, true);
1289         i40e_shutdown_adminq(hw);
1290
1291         i40e_res_pool_destroy(&pf->qp_pool);
1292         i40e_res_pool_destroy(&pf->msix_pool);
1293
1294         /* force a PF reset to clean anything leftover */
1295         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1296         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1297                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1298         I40E_WRITE_FLUSH(hw);
1299 }
1300
1301 static void
1302 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1303 {
1304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306         struct i40e_vsi *vsi = pf->main_vsi;
1307         int status;
1308
1309         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1310                                                         true, NULL);
1311         if (status != I40E_SUCCESS)
1312                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1313
1314         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1315                                                         TRUE, NULL);
1316         if (status != I40E_SUCCESS)
1317                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1318
1319 }
1320
1321 static void
1322 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1323 {
1324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1325         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct i40e_vsi *vsi = pf->main_vsi;
1327         int status;
1328
1329         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1330                                                         false, NULL);
1331         if (status != I40E_SUCCESS)
1332                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1333
1334         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1335                                                         false, NULL);
1336         if (status != I40E_SUCCESS)
1337                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1338 }
1339
1340 static void
1341 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1342 {
1343         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1345         struct i40e_vsi *vsi = pf->main_vsi;
1346         int ret;
1347
1348         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1349         if (ret != I40E_SUCCESS)
1350                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1351 }
1352
1353 static void
1354 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1355 {
1356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1358         struct i40e_vsi *vsi = pf->main_vsi;
1359         int ret;
1360
1361         if (dev->data->promiscuous == 1)
1362                 return; /* must remain in all_multicast mode */
1363
1364         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1365                                 vsi->seid, FALSE, NULL);
1366         if (ret != I40E_SUCCESS)
1367                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1368 }
1369
1370 /*
1371  * Set device link up.
1372  */
1373 static int
1374 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1375 {
1376         /* re-apply link speed setting */
1377         return i40e_apply_link_speed(dev);
1378 }
1379
1380 /*
1381  * Set device link down.
1382  */
1383 static int
1384 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1385 {
1386         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1387         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389
1390         return i40e_phy_conf_link(hw, abilities, speed);
1391 }
1392
1393 int
1394 i40e_dev_link_update(struct rte_eth_dev *dev,
1395                      int wait_to_complete)
1396 {
1397 #define CHECK_INTERVAL 100  /* 100ms */
1398 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         struct i40e_link_status link_status;
1401         struct rte_eth_link link, old;
1402         int status;
1403         unsigned rep_cnt = MAX_REPEAT_TIME;
1404
1405         memset(&link, 0, sizeof(link));
1406         memset(&old, 0, sizeof(old));
1407         memset(&link_status, 0, sizeof(link_status));
1408         rte_i40e_dev_atomic_read_link_status(dev, &old);
1409
1410         do {
1411                 /* Get link status information from hardware */
1412                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1413                 if (status != I40E_SUCCESS) {
1414                         link.link_speed = ETH_LINK_SPEED_100;
1415                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1416                         PMD_DRV_LOG(ERR, "Failed to get link info");
1417                         goto out;
1418                 }
1419
1420                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1421                 if (!wait_to_complete)
1422                         break;
1423
1424                 rte_delay_ms(CHECK_INTERVAL);
1425         } while (!link.link_status && rep_cnt--);
1426
1427         if (!link.link_status)
1428                 goto out;
1429
1430         /* i40e uses full duplex only */
1431         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1432
1433         /* Parse the link status */
1434         switch (link_status.link_speed) {
1435         case I40E_LINK_SPEED_100MB:
1436                 link.link_speed = ETH_LINK_SPEED_100;
1437                 break;
1438         case I40E_LINK_SPEED_1GB:
1439                 link.link_speed = ETH_LINK_SPEED_1000;
1440                 break;
1441         case I40E_LINK_SPEED_10GB:
1442                 link.link_speed = ETH_LINK_SPEED_10G;
1443                 break;
1444         case I40E_LINK_SPEED_20GB:
1445                 link.link_speed = ETH_LINK_SPEED_20G;
1446                 break;
1447         case I40E_LINK_SPEED_40GB:
1448                 link.link_speed = ETH_LINK_SPEED_40G;
1449                 break;
1450         default:
1451                 link.link_speed = ETH_LINK_SPEED_100;
1452                 break;
1453         }
1454
1455 out:
1456         rte_i40e_dev_atomic_write_link_status(dev, &link);
1457         if (link.link_status == old.link_status)
1458                 return -1;
1459
1460         return 0;
1461 }
1462
1463 /* Get all the statistics of a VSI */
1464 void
1465 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1466 {
1467         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1468         struct i40e_eth_stats *nes = &vsi->eth_stats;
1469         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1470         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1471
1472         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1473                             vsi->offset_loaded, &oes->rx_bytes,
1474                             &nes->rx_bytes);
1475         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1476                             vsi->offset_loaded, &oes->rx_unicast,
1477                             &nes->rx_unicast);
1478         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1479                             vsi->offset_loaded, &oes->rx_multicast,
1480                             &nes->rx_multicast);
1481         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1482                             vsi->offset_loaded, &oes->rx_broadcast,
1483                             &nes->rx_broadcast);
1484         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1485                             &oes->rx_discards, &nes->rx_discards);
1486         /* GLV_REPC not supported */
1487         /* GLV_RMPC not supported */
1488         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1489                             &oes->rx_unknown_protocol,
1490                             &nes->rx_unknown_protocol);
1491         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1492                             vsi->offset_loaded, &oes->tx_bytes,
1493                             &nes->tx_bytes);
1494         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1495                             vsi->offset_loaded, &oes->tx_unicast,
1496                             &nes->tx_unicast);
1497         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1498                             vsi->offset_loaded, &oes->tx_multicast,
1499                             &nes->tx_multicast);
1500         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1501                             vsi->offset_loaded,  &oes->tx_broadcast,
1502                             &nes->tx_broadcast);
1503         /* GLV_TDPC not supported */
1504         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1505                             &oes->tx_errors, &nes->tx_errors);
1506         vsi->offset_loaded = true;
1507
1508         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1509                     vsi->vsi_id);
1510         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1511         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1512         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1513         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1514         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1515         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1516                     nes->rx_unknown_protocol);
1517         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1518         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1519         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1520         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1521         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1522         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1523         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1524                     vsi->vsi_id);
1525 }
1526
1527 static void
1528 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1529 {
1530         unsigned int i;
1531         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1532         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1533         /* Get statistics of struct i40e_eth_stats */
1534         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1535                             I40E_GLPRT_GORCL(hw->port),
1536                             pf->offset_loaded, &os->eth.rx_bytes,
1537                             &ns->eth.rx_bytes);
1538         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1539                             I40E_GLPRT_UPRCL(hw->port),
1540                             pf->offset_loaded, &os->eth.rx_unicast,
1541                             &ns->eth.rx_unicast);
1542         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1543                             I40E_GLPRT_MPRCL(hw->port),
1544                             pf->offset_loaded, &os->eth.rx_multicast,
1545                             &ns->eth.rx_multicast);
1546         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1547                             I40E_GLPRT_BPRCL(hw->port),
1548                             pf->offset_loaded, &os->eth.rx_broadcast,
1549                             &ns->eth.rx_broadcast);
1550         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1551                             pf->offset_loaded, &os->eth.rx_discards,
1552                             &ns->eth.rx_discards);
1553         /* GLPRT_REPC not supported */
1554         /* GLPRT_RMPC not supported */
1555         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1556                             pf->offset_loaded,
1557                             &os->eth.rx_unknown_protocol,
1558                             &ns->eth.rx_unknown_protocol);
1559         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1560                             I40E_GLPRT_GOTCL(hw->port),
1561                             pf->offset_loaded, &os->eth.tx_bytes,
1562                             &ns->eth.tx_bytes);
1563         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1564                             I40E_GLPRT_UPTCL(hw->port),
1565                             pf->offset_loaded, &os->eth.tx_unicast,
1566                             &ns->eth.tx_unicast);
1567         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1568                             I40E_GLPRT_MPTCL(hw->port),
1569                             pf->offset_loaded, &os->eth.tx_multicast,
1570                             &ns->eth.tx_multicast);
1571         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1572                             I40E_GLPRT_BPTCL(hw->port),
1573                             pf->offset_loaded, &os->eth.tx_broadcast,
1574                             &ns->eth.tx_broadcast);
1575         /* GLPRT_TEPC not supported */
1576
1577         /* additional port specific stats */
1578         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1579                             pf->offset_loaded, &os->tx_dropped_link_down,
1580                             &ns->tx_dropped_link_down);
1581         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1582                             pf->offset_loaded, &os->crc_errors,
1583                             &ns->crc_errors);
1584         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1585                             pf->offset_loaded, &os->illegal_bytes,
1586                             &ns->illegal_bytes);
1587         /* GLPRT_ERRBC not supported */
1588         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1589                             pf->offset_loaded, &os->mac_local_faults,
1590                             &ns->mac_local_faults);
1591         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1592                             pf->offset_loaded, &os->mac_remote_faults,
1593                             &ns->mac_remote_faults);
1594         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1595                             pf->offset_loaded, &os->rx_length_errors,
1596                             &ns->rx_length_errors);
1597         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1598                             pf->offset_loaded, &os->link_xon_rx,
1599                             &ns->link_xon_rx);
1600         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1601                             pf->offset_loaded, &os->link_xoff_rx,
1602                             &ns->link_xoff_rx);
1603         for (i = 0; i < 8; i++) {
1604                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1605                                     pf->offset_loaded,
1606                                     &os->priority_xon_rx[i],
1607                                     &ns->priority_xon_rx[i]);
1608                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1609                                     pf->offset_loaded,
1610                                     &os->priority_xoff_rx[i],
1611                                     &ns->priority_xoff_rx[i]);
1612         }
1613         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1614                             pf->offset_loaded, &os->link_xon_tx,
1615                             &ns->link_xon_tx);
1616         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1617                             pf->offset_loaded, &os->link_xoff_tx,
1618                             &ns->link_xoff_tx);
1619         for (i = 0; i < 8; i++) {
1620                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1621                                     pf->offset_loaded,
1622                                     &os->priority_xon_tx[i],
1623                                     &ns->priority_xon_tx[i]);
1624                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1625                                     pf->offset_loaded,
1626                                     &os->priority_xoff_tx[i],
1627                                     &ns->priority_xoff_tx[i]);
1628                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1629                                     pf->offset_loaded,
1630                                     &os->priority_xon_2_xoff[i],
1631                                     &ns->priority_xon_2_xoff[i]);
1632         }
1633         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1634                             I40E_GLPRT_PRC64L(hw->port),
1635                             pf->offset_loaded, &os->rx_size_64,
1636                             &ns->rx_size_64);
1637         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1638                             I40E_GLPRT_PRC127L(hw->port),
1639                             pf->offset_loaded, &os->rx_size_127,
1640                             &ns->rx_size_127);
1641         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1642                             I40E_GLPRT_PRC255L(hw->port),
1643                             pf->offset_loaded, &os->rx_size_255,
1644                             &ns->rx_size_255);
1645         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1646                             I40E_GLPRT_PRC511L(hw->port),
1647                             pf->offset_loaded, &os->rx_size_511,
1648                             &ns->rx_size_511);
1649         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1650                             I40E_GLPRT_PRC1023L(hw->port),
1651                             pf->offset_loaded, &os->rx_size_1023,
1652                             &ns->rx_size_1023);
1653         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1654                             I40E_GLPRT_PRC1522L(hw->port),
1655                             pf->offset_loaded, &os->rx_size_1522,
1656                             &ns->rx_size_1522);
1657         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1658                             I40E_GLPRT_PRC9522L(hw->port),
1659                             pf->offset_loaded, &os->rx_size_big,
1660                             &ns->rx_size_big);
1661         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1662                             pf->offset_loaded, &os->rx_undersize,
1663                             &ns->rx_undersize);
1664         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1665                             pf->offset_loaded, &os->rx_fragments,
1666                             &ns->rx_fragments);
1667         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1668                             pf->offset_loaded, &os->rx_oversize,
1669                             &ns->rx_oversize);
1670         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1671                             pf->offset_loaded, &os->rx_jabber,
1672                             &ns->rx_jabber);
1673         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1674                             I40E_GLPRT_PTC64L(hw->port),
1675                             pf->offset_loaded, &os->tx_size_64,
1676                             &ns->tx_size_64);
1677         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1678                             I40E_GLPRT_PTC127L(hw->port),
1679                             pf->offset_loaded, &os->tx_size_127,
1680                             &ns->tx_size_127);
1681         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1682                             I40E_GLPRT_PTC255L(hw->port),
1683                             pf->offset_loaded, &os->tx_size_255,
1684                             &ns->tx_size_255);
1685         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1686                             I40E_GLPRT_PTC511L(hw->port),
1687                             pf->offset_loaded, &os->tx_size_511,
1688                             &ns->tx_size_511);
1689         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1690                             I40E_GLPRT_PTC1023L(hw->port),
1691                             pf->offset_loaded, &os->tx_size_1023,
1692                             &ns->tx_size_1023);
1693         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1694                             I40E_GLPRT_PTC1522L(hw->port),
1695                             pf->offset_loaded, &os->tx_size_1522,
1696                             &ns->tx_size_1522);
1697         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1698                             I40E_GLPRT_PTC9522L(hw->port),
1699                             pf->offset_loaded, &os->tx_size_big,
1700                             &ns->tx_size_big);
1701         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1702                            pf->offset_loaded,
1703                            &os->fd_sb_match, &ns->fd_sb_match);
1704         /* GLPRT_MSPDC not supported */
1705         /* GLPRT_XEC not supported */
1706
1707         pf->offset_loaded = true;
1708
1709         if (pf->main_vsi)
1710                 i40e_update_vsi_stats(pf->main_vsi);
1711 }
1712
1713 /* Get all statistics of a port */
1714 static void
1715 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1716 {
1717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1720         unsigned i;
1721
1722         /* call read registers - updates values, now write them to struct */
1723         i40e_read_stats_registers(pf, hw);
1724
1725         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1726                                                 ns->eth.rx_broadcast;
1727         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1728                                                 ns->eth.tx_broadcast;
1729         stats->ibytes   = ns->eth.rx_bytes;
1730         stats->obytes   = ns->eth.tx_bytes;
1731         stats->oerrors  = ns->eth.tx_errors;
1732         stats->imcasts  = ns->eth.rx_multicast;
1733         stats->fdirmatch = ns->fd_sb_match;
1734
1735         /* Rx Errors */
1736         stats->ibadcrc  = ns->crc_errors;
1737         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1738                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1739         stats->imissed  = ns->eth.rx_discards;
1740         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1741
1742         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1743         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1744         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1745         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1746         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1747         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1748         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1749                     ns->eth.rx_unknown_protocol);
1750         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1751         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1752         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1753         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1754         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1755         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1756
1757         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1758                     ns->tx_dropped_link_down);
1759         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1760         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1761                     ns->illegal_bytes);
1762         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1763         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1764                     ns->mac_local_faults);
1765         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1766                     ns->mac_remote_faults);
1767         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1768                     ns->rx_length_errors);
1769         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1770         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1771         for (i = 0; i < 8; i++) {
1772                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1773                                 i, ns->priority_xon_rx[i]);
1774                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1775                                 i, ns->priority_xoff_rx[i]);
1776         }
1777         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1778         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1779         for (i = 0; i < 8; i++) {
1780                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1781                                 i, ns->priority_xon_tx[i]);
1782                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1783                                 i, ns->priority_xoff_tx[i]);
1784                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1785                                 i, ns->priority_xon_2_xoff[i]);
1786         }
1787         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1788         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1789         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1790         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1791         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1792         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1793         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1794         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1795         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1796         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1797         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1798         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1799         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1800         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1801         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1802         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1803         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1804         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1805         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1806                         ns->mac_short_packet_dropped);
1807         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1808                     ns->checksum_error);
1809         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1810         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1811 }
1812
1813 static void
1814 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1815 {
1816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1819
1820         /* The hw registers are cleared on read */
1821         pf->offset_loaded = false;
1822         i40e_read_stats_registers(pf, hw);
1823
1824         /* reset software counters */
1825         memset(hw_stats, 0, sizeof(*hw_stats));
1826 }
1827
1828 static int
1829 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1830                     unsigned n)
1831 {
1832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834         unsigned i, count = 0;
1835         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1836
1837         if (n < I40E_NB_XSTATS)
1838                 return I40E_NB_XSTATS;
1839
1840         i40e_read_stats_registers(pf, hw);
1841
1842         /* Reset */
1843         if (xstats == NULL)
1844                 return 0;
1845
1846         /* Get stats from i40e_eth_stats struct */
1847         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1848                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1849                          "%s", rte_i40e_stats_strings[i].name);
1850                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1851                         rte_i40e_stats_strings[i].offset);
1852                 count++;
1853         }
1854
1855         /* Get individiual stats from i40e_hw_port struct */
1856         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1857                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1858                          "%s", rte_i40e_hw_port_strings[i].name);
1859                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1860                                 rte_i40e_hw_port_strings[i].offset);
1861                 count++;
1862         }
1863
1864         /* Get per-queue stats from i40e_hw_port struct */
1865         for (i = 0; i < 8; i++) {
1866                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1867                          "rx_q%u_xon_priority_packets", i);
1868                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1869                                 offsetof(struct i40e_hw_port_stats,
1870                                          priority_xon_rx[i]));
1871                 count++;
1872
1873                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1874                          "rx_q%u_xoff_priority_packets", i);
1875                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1876                                 offsetof(struct i40e_hw_port_stats,
1877                                          priority_xoff_rx[i]));
1878                 count++;
1879
1880                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1881                          "tx_q%u_xon_priority_packets", i);
1882                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1883                                 offsetof(struct i40e_hw_port_stats,
1884                                          priority_xon_tx[i]));
1885                 count++;
1886
1887                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1888                          "tx_q%u_xoff_priority_packets", i);
1889                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1890                                 offsetof(struct i40e_hw_port_stats,
1891                                          priority_xoff_tx[i]));
1892                 count++;
1893
1894                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1895                          "xx_q%u_xon_to_xoff_priority_packets", i);
1896                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1897                                 offsetof(struct i40e_hw_port_stats,
1898                                          priority_xon_2_xoff[i]));
1899                 count++;
1900         }
1901
1902         return I40E_NB_XSTATS;
1903 }
1904
1905 /* Reset the statistics */
1906 static void
1907 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910
1911         /* It results in reloading the start point of each counter */
1912         pf->offset_loaded = false;
1913 }
1914
1915 static int
1916 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1917                                  __rte_unused uint16_t queue_id,
1918                                  __rte_unused uint8_t stat_idx,
1919                                  __rte_unused uint8_t is_rx)
1920 {
1921         PMD_INIT_FUNC_TRACE();
1922
1923         return -ENOSYS;
1924 }
1925
1926 static void
1927 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1928 {
1929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1930         struct i40e_vsi *vsi = pf->main_vsi;
1931
1932         dev_info->max_rx_queues = vsi->nb_qps;
1933         dev_info->max_tx_queues = vsi->nb_qps;
1934         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1935         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1936         dev_info->max_mac_addrs = vsi->max_macaddrs;
1937         dev_info->max_vfs = dev->pci_dev->max_vfs;
1938         dev_info->rx_offload_capa =
1939                 DEV_RX_OFFLOAD_VLAN_STRIP |
1940                 DEV_RX_OFFLOAD_QINQ_STRIP |
1941                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1942                 DEV_RX_OFFLOAD_UDP_CKSUM |
1943                 DEV_RX_OFFLOAD_TCP_CKSUM;
1944         dev_info->tx_offload_capa =
1945                 DEV_TX_OFFLOAD_VLAN_INSERT |
1946                 DEV_TX_OFFLOAD_QINQ_INSERT |
1947                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1948                 DEV_TX_OFFLOAD_UDP_CKSUM |
1949                 DEV_TX_OFFLOAD_TCP_CKSUM |
1950                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1951                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1952                 DEV_TX_OFFLOAD_TCP_TSO;
1953         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1954                                                 sizeof(uint32_t);
1955         dev_info->reta_size = pf->hash_lut_size;
1956         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1957
1958         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1959                 .rx_thresh = {
1960                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1961                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1962                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1963                 },
1964                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1965                 .rx_drop_en = 0,
1966         };
1967
1968         dev_info->default_txconf = (struct rte_eth_txconf) {
1969                 .tx_thresh = {
1970                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1971                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1972                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1973                 },
1974                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1975                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1976                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1977                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1978         };
1979
1980         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1981                 .nb_max = I40E_MAX_RING_DESC,
1982                 .nb_min = I40E_MIN_RING_DESC,
1983                 .nb_align = I40E_ALIGN_RING_DESC,
1984         };
1985
1986         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1987                 .nb_max = I40E_MAX_RING_DESC,
1988                 .nb_min = I40E_MIN_RING_DESC,
1989                 .nb_align = I40E_ALIGN_RING_DESC,
1990         };
1991
1992         if (pf->flags & I40E_FLAG_VMDQ) {
1993                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1994                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1995                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1996                                                 pf->max_nb_vmdq_vsi;
1997                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1998                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1999                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2000         }
2001 }
2002
2003 static int
2004 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2005 {
2006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2007         struct i40e_vsi *vsi = pf->main_vsi;
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (on)
2011                 return i40e_vsi_add_vlan(vsi, vlan_id);
2012         else
2013                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2014 }
2015
2016 static void
2017 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2018                    __rte_unused uint16_t tpid)
2019 {
2020         PMD_INIT_FUNC_TRACE();
2021 }
2022
2023 static void
2024 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2025 {
2026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027         struct i40e_vsi *vsi = pf->main_vsi;
2028
2029         if (mask & ETH_VLAN_STRIP_MASK) {
2030                 /* Enable or disable VLAN stripping */
2031                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2032                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2033                 else
2034                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2035         }
2036
2037         if (mask & ETH_VLAN_EXTEND_MASK) {
2038                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2039                         i40e_vsi_config_double_vlan(vsi, TRUE);
2040                 else
2041                         i40e_vsi_config_double_vlan(vsi, FALSE);
2042         }
2043 }
2044
2045 static void
2046 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2047                           __rte_unused uint16_t queue,
2048                           __rte_unused int on)
2049 {
2050         PMD_INIT_FUNC_TRACE();
2051 }
2052
2053 static int
2054 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2055 {
2056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2057         struct i40e_vsi *vsi = pf->main_vsi;
2058         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2059         struct i40e_vsi_vlan_pvid_info info;
2060
2061         memset(&info, 0, sizeof(info));
2062         info.on = on;
2063         if (info.on)
2064                 info.config.pvid = pvid;
2065         else {
2066                 info.config.reject.tagged =
2067                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2068                 info.config.reject.untagged =
2069                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2070         }
2071
2072         return i40e_vsi_vlan_pvid_set(vsi, &info);
2073 }
2074
2075 static int
2076 i40e_dev_led_on(struct rte_eth_dev *dev)
2077 {
2078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         uint32_t mode = i40e_led_get(hw);
2080
2081         if (mode == 0)
2082                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2083
2084         return 0;
2085 }
2086
2087 static int
2088 i40e_dev_led_off(struct rte_eth_dev *dev)
2089 {
2090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         uint32_t mode = i40e_led_get(hw);
2092
2093         if (mode != 0)
2094                 i40e_led_set(hw, 0, false);
2095
2096         return 0;
2097 }
2098
2099 static int
2100 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2101 {
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104
2105         fc_conf->pause_time = pf->fc_conf.pause_time;
2106         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2107         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2108
2109          /* Return current mode according to actual setting*/
2110         switch (hw->fc.current_mode) {
2111         case I40E_FC_FULL:
2112                 fc_conf->mode = RTE_FC_FULL;
2113                 break;
2114         case I40E_FC_TX_PAUSE:
2115                 fc_conf->mode = RTE_FC_TX_PAUSE;
2116                 break;
2117         case I40E_FC_RX_PAUSE:
2118                 fc_conf->mode = RTE_FC_RX_PAUSE;
2119                 break;
2120         case I40E_FC_NONE:
2121         default:
2122                 fc_conf->mode = RTE_FC_NONE;
2123         };
2124
2125         return 0;
2126 }
2127
2128 static int
2129 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2130 {
2131         uint32_t mflcn_reg, fctrl_reg, reg;
2132         uint32_t max_high_water;
2133         uint8_t i, aq_failure;
2134         int err;
2135         struct i40e_hw *hw;
2136         struct i40e_pf *pf;
2137         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2138                 [RTE_FC_NONE] = I40E_FC_NONE,
2139                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2140                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2141                 [RTE_FC_FULL] = I40E_FC_FULL
2142         };
2143
2144         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2145
2146         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2147         if ((fc_conf->high_water > max_high_water) ||
2148                         (fc_conf->high_water < fc_conf->low_water)) {
2149                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2150                         "High_water must <= %d.", max_high_water);
2151                 return -EINVAL;
2152         }
2153
2154         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2157
2158         pf->fc_conf.pause_time = fc_conf->pause_time;
2159         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2160         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2161
2162         PMD_INIT_FUNC_TRACE();
2163
2164         /* All the link flow control related enable/disable register
2165          * configuration is handle by the F/W
2166          */
2167         err = i40e_set_fc(hw, &aq_failure, true);
2168         if (err < 0)
2169                 return -ENOSYS;
2170
2171         if (i40e_is_40G_device(hw->device_id)) {
2172                 /* Configure flow control refresh threshold,
2173                  * the value for stat_tx_pause_refresh_timer[8]
2174                  * is used for global pause operation.
2175                  */
2176
2177                 I40E_WRITE_REG(hw,
2178                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2179                                pf->fc_conf.pause_time);
2180
2181                 /* configure the timer value included in transmitted pause
2182                  * frame,
2183                  * the value for stat_tx_pause_quanta[8] is used for global
2184                  * pause operation
2185                  */
2186                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2187                                pf->fc_conf.pause_time);
2188
2189                 fctrl_reg = I40E_READ_REG(hw,
2190                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2191
2192                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2193                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2194                 else
2195                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2196
2197                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2198                                fctrl_reg);
2199         } else {
2200                 /* Configure pause time (2 TCs per register) */
2201                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2202                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2203                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2204
2205                 /* Configure flow control refresh threshold value */
2206                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2207                                pf->fc_conf.pause_time / 2);
2208
2209                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2210
2211                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2212                  *depending on configuration
2213                  */
2214                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2215                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2216                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2217                 } else {
2218                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2219                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2220                 }
2221
2222                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2223         }
2224
2225         /* config the water marker both based on the packets and bytes */
2226         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2227                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2228                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2229         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2230                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2231                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2232         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2233                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2234                        << I40E_KILOSHIFT);
2235         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2236                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2237                        << I40E_KILOSHIFT);
2238
2239         I40E_WRITE_FLUSH(hw);
2240
2241         return 0;
2242 }
2243
2244 static int
2245 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2246                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2247 {
2248         PMD_INIT_FUNC_TRACE();
2249
2250         return -ENOSYS;
2251 }
2252
2253 /* Add a MAC address, and update filters */
2254 static void
2255 i40e_macaddr_add(struct rte_eth_dev *dev,
2256                  struct ether_addr *mac_addr,
2257                  __rte_unused uint32_t index,
2258                  uint32_t pool)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_mac_filter_info mac_filter;
2262         struct i40e_vsi *vsi;
2263         int ret;
2264
2265         /* If VMDQ not enabled or configured, return */
2266         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2267                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2268                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2269                         pool);
2270                 return;
2271         }
2272
2273         if (pool > pf->nb_cfg_vmdq_vsi) {
2274                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2275                                 pool, pf->nb_cfg_vmdq_vsi);
2276                 return;
2277         }
2278
2279         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2280         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2281
2282         if (pool == 0)
2283                 vsi = pf->main_vsi;
2284         else
2285                 vsi = pf->vmdq[pool - 1].vsi;
2286
2287         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2288         if (ret != I40E_SUCCESS) {
2289                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2290                 return;
2291         }
2292 }
2293
2294 /* Remove a MAC address, and update filters */
2295 static void
2296 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2297 {
2298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2299         struct i40e_vsi *vsi;
2300         struct rte_eth_dev_data *data = dev->data;
2301         struct ether_addr *macaddr;
2302         int ret;
2303         uint32_t i;
2304         uint64_t pool_sel;
2305
2306         macaddr = &(data->mac_addrs[index]);
2307
2308         pool_sel = dev->data->mac_pool_sel[index];
2309
2310         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2311                 if (pool_sel & (1ULL << i)) {
2312                         if (i == 0)
2313                                 vsi = pf->main_vsi;
2314                         else {
2315                                 /* No VMDQ pool enabled or configured */
2316                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2317                                         (i > pf->nb_cfg_vmdq_vsi)) {
2318                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2319                                                         "/configured");
2320                                         return;
2321                                 }
2322                                 vsi = pf->vmdq[i - 1].vsi;
2323                         }
2324                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2325
2326                         if (ret) {
2327                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2328                                 return;
2329                         }
2330                 }
2331         }
2332 }
2333
2334 /* Set perfect match or hash match of MAC and VLAN for a VF */
2335 static int
2336 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2337                  struct rte_eth_mac_filter *filter,
2338                  bool add)
2339 {
2340         struct i40e_hw *hw;
2341         struct i40e_mac_filter_info mac_filter;
2342         struct ether_addr old_mac;
2343         struct ether_addr *new_mac;
2344         struct i40e_pf_vf *vf = NULL;
2345         uint16_t vf_id;
2346         int ret;
2347
2348         if (pf == NULL) {
2349                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2350                 return -EINVAL;
2351         }
2352         hw = I40E_PF_TO_HW(pf);
2353
2354         if (filter == NULL) {
2355                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2356                 return -EINVAL;
2357         }
2358
2359         new_mac = &filter->mac_addr;
2360
2361         if (is_zero_ether_addr(new_mac)) {
2362                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2363                 return -EINVAL;
2364         }
2365
2366         vf_id = filter->dst_id;
2367
2368         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2369                 PMD_DRV_LOG(ERR, "Invalid argument.");
2370                 return -EINVAL;
2371         }
2372         vf = &pf->vfs[vf_id];
2373
2374         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2375                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2376                 return -EINVAL;
2377         }
2378
2379         if (add) {
2380                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2381                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2382                                 ETHER_ADDR_LEN);
2383                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2384                                  ETHER_ADDR_LEN);
2385
2386                 mac_filter.filter_type = filter->filter_type;
2387                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2388                 if (ret != I40E_SUCCESS) {
2389                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2390                         return -1;
2391                 }
2392                 ether_addr_copy(new_mac, &pf->dev_addr);
2393         } else {
2394                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2395                                 ETHER_ADDR_LEN);
2396                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2397                 if (ret != I40E_SUCCESS) {
2398                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2399                         return -1;
2400                 }
2401
2402                 /* Clear device address as it has been removed */
2403                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2404                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2405         }
2406
2407         return 0;
2408 }
2409
2410 /* MAC filter handle */
2411 static int
2412 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2413                 void *arg)
2414 {
2415         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2416         struct rte_eth_mac_filter *filter;
2417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2418         int ret = I40E_NOT_SUPPORTED;
2419
2420         filter = (struct rte_eth_mac_filter *)(arg);
2421
2422         switch (filter_op) {
2423         case RTE_ETH_FILTER_NOP:
2424                 ret = I40E_SUCCESS;
2425                 break;
2426         case RTE_ETH_FILTER_ADD:
2427                 i40e_pf_disable_irq0(hw);
2428                 if (filter->is_vf)
2429                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2430                 i40e_pf_enable_irq0(hw);
2431                 break;
2432         case RTE_ETH_FILTER_DELETE:
2433                 i40e_pf_disable_irq0(hw);
2434                 if (filter->is_vf)
2435                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2436                 i40e_pf_enable_irq0(hw);
2437                 break;
2438         default:
2439                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2440                 ret = I40E_ERR_PARAM;
2441                 break;
2442         }
2443
2444         return ret;
2445 }
2446
2447 static int
2448 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2449 {
2450         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2451         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2452         int ret;
2453
2454         if (!lut)
2455                 return -EINVAL;
2456
2457         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2458                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2459                                           lut, lut_size);
2460                 if (ret) {
2461                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2462                         return ret;
2463                 }
2464         } else {
2465                 uint32_t *lut_dw = (uint32_t *)lut;
2466                 uint16_t i, lut_size_dw = lut_size / 4;
2467
2468                 for (i = 0; i < lut_size_dw; i++)
2469                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int
2476 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2477 {
2478         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2479         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2480         int ret;
2481
2482         if (!vsi || !lut)
2483                 return -EINVAL;
2484
2485         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2486                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2487                                           lut, lut_size);
2488                 if (ret) {
2489                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2490                         return ret;
2491                 }
2492         } else {
2493                 uint32_t *lut_dw = (uint32_t *)lut;
2494                 uint16_t i, lut_size_dw = lut_size / 4;
2495
2496                 for (i = 0; i < lut_size_dw; i++)
2497                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2498                 I40E_WRITE_FLUSH(hw);
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int
2505 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2506                          struct rte_eth_rss_reta_entry64 *reta_conf,
2507                          uint16_t reta_size)
2508 {
2509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2510         uint16_t i, lut_size = pf->hash_lut_size;
2511         uint16_t idx, shift;
2512         uint8_t *lut;
2513         int ret;
2514
2515         if (reta_size != lut_size ||
2516                 reta_size > ETH_RSS_RETA_SIZE_512) {
2517                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2518                         "(%d) doesn't match the number hardware can supported "
2519                                         "(%d)\n", reta_size, lut_size);
2520                 return -EINVAL;
2521         }
2522
2523         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2524         if (!lut) {
2525                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2526                 return -ENOMEM;
2527         }
2528         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2529         if (ret)
2530                 goto out;
2531         for (i = 0; i < reta_size; i++) {
2532                 idx = i / RTE_RETA_GROUP_SIZE;
2533                 shift = i % RTE_RETA_GROUP_SIZE;
2534                 if (reta_conf[idx].mask & (1ULL << shift))
2535                         lut[i] = reta_conf[idx].reta[shift];
2536         }
2537         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2538
2539 out:
2540         rte_free(lut);
2541
2542         return ret;
2543 }
2544
2545 static int
2546 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2547                         struct rte_eth_rss_reta_entry64 *reta_conf,
2548                         uint16_t reta_size)
2549 {
2550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2551         uint16_t i, lut_size = pf->hash_lut_size;
2552         uint16_t idx, shift;
2553         uint8_t *lut;
2554         int ret;
2555
2556         if (reta_size != lut_size ||
2557                 reta_size > ETH_RSS_RETA_SIZE_512) {
2558                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2559                         "(%d) doesn't match the number hardware can supported "
2560                                         "(%d)\n", reta_size, lut_size);
2561                 return -EINVAL;
2562         }
2563
2564         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2565         if (!lut) {
2566                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2567                 return -ENOMEM;
2568         }
2569
2570         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2571         if (ret)
2572                 goto out;
2573         for (i = 0; i < reta_size; i++) {
2574                 idx = i / RTE_RETA_GROUP_SIZE;
2575                 shift = i % RTE_RETA_GROUP_SIZE;
2576                 if (reta_conf[idx].mask & (1ULL << shift))
2577                         reta_conf[idx].reta[shift] = lut[i];
2578         }
2579
2580 out:
2581         rte_free(lut);
2582
2583         return ret;
2584 }
2585
2586 /**
2587  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2588  * @hw:   pointer to the HW structure
2589  * @mem:  pointer to mem struct to fill out
2590  * @size: size of memory requested
2591  * @alignment: what to align the allocation to
2592  **/
2593 enum i40e_status_code
2594 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2595                         struct i40e_dma_mem *mem,
2596                         u64 size,
2597                         u32 alignment)
2598 {
2599         static uint64_t id = 0;
2600         const struct rte_memzone *mz = NULL;
2601         char z_name[RTE_MEMZONE_NAMESIZE];
2602
2603         if (!mem)
2604                 return I40E_ERR_PARAM;
2605
2606         id++;
2607         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2608 #ifdef RTE_LIBRTE_XEN_DOM0
2609         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2610                                          alignment, RTE_PGSIZE_2M);
2611 #else
2612         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2613                                          alignment);
2614 #endif
2615         if (!mz)
2616                 return I40E_ERR_NO_MEMORY;
2617
2618         mem->id = id;
2619         mem->size = size;
2620         mem->va = mz->addr;
2621 #ifdef RTE_LIBRTE_XEN_DOM0
2622         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2623 #else
2624         mem->pa = mz->phys_addr;
2625 #endif
2626
2627         return I40E_SUCCESS;
2628 }
2629
2630 /**
2631  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2632  * @hw:   pointer to the HW structure
2633  * @mem:  ptr to mem struct to free
2634  **/
2635 enum i40e_status_code
2636 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2637                     struct i40e_dma_mem *mem)
2638 {
2639         if (!mem || !mem->va)
2640                 return I40E_ERR_PARAM;
2641
2642         mem->va = NULL;
2643         mem->pa = (u64)0;
2644
2645         return I40E_SUCCESS;
2646 }
2647
2648 /**
2649  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2650  * @hw:   pointer to the HW structure
2651  * @mem:  pointer to mem struct to fill out
2652  * @size: size of memory requested
2653  **/
2654 enum i40e_status_code
2655 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2656                          struct i40e_virt_mem *mem,
2657                          u32 size)
2658 {
2659         if (!mem)
2660                 return I40E_ERR_PARAM;
2661
2662         mem->size = size;
2663         mem->va = rte_zmalloc("i40e", size, 0);
2664
2665         if (mem->va)
2666                 return I40E_SUCCESS;
2667         else
2668                 return I40E_ERR_NO_MEMORY;
2669 }
2670
2671 /**
2672  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2673  * @hw:   pointer to the HW structure
2674  * @mem:  pointer to mem struct to free
2675  **/
2676 enum i40e_status_code
2677 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2678                      struct i40e_virt_mem *mem)
2679 {
2680         if (!mem)
2681                 return I40E_ERR_PARAM;
2682
2683         rte_free(mem->va);
2684         mem->va = NULL;
2685
2686         return I40E_SUCCESS;
2687 }
2688
2689 void
2690 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2691 {
2692         rte_spinlock_init(&sp->spinlock);
2693 }
2694
2695 void
2696 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2697 {
2698         rte_spinlock_lock(&sp->spinlock);
2699 }
2700
2701 void
2702 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2703 {
2704         rte_spinlock_unlock(&sp->spinlock);
2705 }
2706
2707 void
2708 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2709 {
2710         return;
2711 }
2712
2713 /**
2714  * Get the hardware capabilities, which will be parsed
2715  * and saved into struct i40e_hw.
2716  */
2717 static int
2718 i40e_get_cap(struct i40e_hw *hw)
2719 {
2720         struct i40e_aqc_list_capabilities_element_resp *buf;
2721         uint16_t len, size = 0;
2722         int ret;
2723
2724         /* Calculate a huge enough buff for saving response data temporarily */
2725         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2726                                                 I40E_MAX_CAP_ELE_NUM;
2727         buf = rte_zmalloc("i40e", len, 0);
2728         if (!buf) {
2729                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2730                 return I40E_ERR_NO_MEMORY;
2731         }
2732
2733         /* Get, parse the capabilities and save it to hw */
2734         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2735                         i40e_aqc_opc_list_func_capabilities, NULL);
2736         if (ret != I40E_SUCCESS)
2737                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2738
2739         /* Free the temporary buffer after being used */
2740         rte_free(buf);
2741
2742         return ret;
2743 }
2744
2745 static int
2746 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2747 {
2748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2750         uint16_t sum_queues = 0, sum_vsis, left_queues;
2751
2752         /* First check if FW support SRIOV */
2753         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2754                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2755                 return -EINVAL;
2756         }
2757         /* Add the parameter init for LFC */
2758         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2759         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2760         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2761
2762         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2763         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2764         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2765         /* Allocate queues for pf */
2766         if (hw->func_caps.rss) {
2767                 pf->flags |= I40E_FLAG_RSS;
2768                 if (hw->mac.type == I40E_MAC_X722)
2769                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
2770                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2771                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2772                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2773         } else
2774                 pf->lan_nb_qps = 1;
2775         sum_queues = pf->lan_nb_qps;
2776         /* Default VSI is not counted in */
2777         sum_vsis = 0;
2778         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2779
2780         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2781                 pf->flags |= I40E_FLAG_SRIOV;
2782                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2783                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2784                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2785                                      "max supported %u.",
2786                                      dev->pci_dev->max_vfs,
2787                                      hw->func_caps.num_vfs);
2788                         return -EINVAL;
2789                 }
2790                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2791                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2792                                      "max support %u queues.",
2793                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2794                         return -EINVAL;
2795                 }
2796                 pf->vf_num = dev->pci_dev->max_vfs;
2797                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2798                 sum_vsis   += pf->vf_num;
2799                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2800                              pf->vf_num, pf->vf_nb_qps);
2801         } else
2802                 pf->vf_num = 0;
2803
2804         if (hw->func_caps.vmdq) {
2805                 pf->flags |= I40E_FLAG_VMDQ;
2806                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2807                 pf->max_nb_vmdq_vsi = 1;
2808                 /*
2809                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2810                  * later.
2811                  */
2812                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2813                 sum_vsis += pf->max_nb_vmdq_vsi;
2814         } else {
2815                 pf->vmdq_nb_qps = 0;
2816                 pf->max_nb_vmdq_vsi = 0;
2817         }
2818         pf->nb_cfg_vmdq_vsi = 0;
2819
2820         if (hw->func_caps.fd) {
2821                 pf->flags |= I40E_FLAG_FDIR;
2822                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2823                 /**
2824                  * Each flow director consumes one VSI and one queue,
2825                  * but can't calculate out predictably here.
2826                  */
2827         }
2828
2829         if (hw->func_caps.dcb)
2830                 pf->flags |= I40E_FLAG_DCB;
2831
2832         if (sum_vsis > pf->max_num_vsi ||
2833                 sum_queues > hw->func_caps.num_rx_qp) {
2834                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2835                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2836                              pf->max_num_vsi, sum_vsis);
2837                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2838                              hw->func_caps.num_rx_qp, sum_queues);
2839                 return -EINVAL;
2840         }
2841
2842         /* Adjust VMDQ setting to support as many VMs as possible */
2843         if (pf->flags & I40E_FLAG_VMDQ) {
2844                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2845
2846                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2847                                         pf->max_num_vsi - sum_vsis);
2848
2849                 /* Limit the max VMDQ number that rte_ether that can support  */
2850                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2851                                         ETH_64_POOLS - 1);
2852
2853                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2854                                 pf->max_nb_vmdq_vsi);
2855                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2856         }
2857
2858         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2859          * cause */
2860         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2861                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2862                              sum_vsis, hw->func_caps.num_msix_vectors);
2863                 return -EINVAL;
2864         }
2865         return I40E_SUCCESS;
2866 }
2867
2868 static int
2869 i40e_pf_get_switch_config(struct i40e_pf *pf)
2870 {
2871         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2872         struct i40e_aqc_get_switch_config_resp *switch_config;
2873         struct i40e_aqc_switch_config_element_resp *element;
2874         uint16_t start_seid = 0, num_reported;
2875         int ret;
2876
2877         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2878                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2879         if (!switch_config) {
2880                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2881                 return -ENOMEM;
2882         }
2883
2884         /* Get the switch configurations */
2885         ret = i40e_aq_get_switch_config(hw, switch_config,
2886                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2887         if (ret != I40E_SUCCESS) {
2888                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2889                 goto fail;
2890         }
2891         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2892         if (num_reported != 1) { /* The number should be 1 */
2893                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2894                 goto fail;
2895         }
2896
2897         /* Parse the switch configuration elements */
2898         element = &(switch_config->element[0]);
2899         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2900                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2901                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2902         } else
2903                 PMD_DRV_LOG(INFO, "Unknown element type");
2904
2905 fail:
2906         rte_free(switch_config);
2907
2908         return ret;
2909 }
2910
2911 static int
2912 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2913                         uint32_t num)
2914 {
2915         struct pool_entry *entry;
2916
2917         if (pool == NULL || num == 0)
2918                 return -EINVAL;
2919
2920         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2921         if (entry == NULL) {
2922                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2923                 return -ENOMEM;
2924         }
2925
2926         /* queue heap initialize */
2927         pool->num_free = num;
2928         pool->num_alloc = 0;
2929         pool->base = base;
2930         LIST_INIT(&pool->alloc_list);
2931         LIST_INIT(&pool->free_list);
2932
2933         /* Initialize element  */
2934         entry->base = 0;
2935         entry->len = num;
2936
2937         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2938         return 0;
2939 }
2940
2941 static void
2942 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2943 {
2944         struct pool_entry *entry;
2945
2946         if (pool == NULL)
2947                 return;
2948
2949         LIST_FOREACH(entry, &pool->alloc_list, next) {
2950                 LIST_REMOVE(entry, next);
2951                 rte_free(entry);
2952         }
2953
2954         LIST_FOREACH(entry, &pool->free_list, next) {
2955                 LIST_REMOVE(entry, next);
2956                 rte_free(entry);
2957         }
2958
2959         pool->num_free = 0;
2960         pool->num_alloc = 0;
2961         pool->base = 0;
2962         LIST_INIT(&pool->alloc_list);
2963         LIST_INIT(&pool->free_list);
2964 }
2965
2966 static int
2967 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2968                        uint32_t base)
2969 {
2970         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2971         uint32_t pool_offset;
2972         int insert;
2973
2974         if (pool == NULL) {
2975                 PMD_DRV_LOG(ERR, "Invalid parameter");
2976                 return -EINVAL;
2977         }
2978
2979         pool_offset = base - pool->base;
2980         /* Lookup in alloc list */
2981         LIST_FOREACH(entry, &pool->alloc_list, next) {
2982                 if (entry->base == pool_offset) {
2983                         valid_entry = entry;
2984                         LIST_REMOVE(entry, next);
2985                         break;
2986                 }
2987         }
2988
2989         /* Not find, return */
2990         if (valid_entry == NULL) {
2991                 PMD_DRV_LOG(ERR, "Failed to find entry");
2992                 return -EINVAL;
2993         }
2994
2995         /**
2996          * Found it, move it to free list  and try to merge.
2997          * In order to make merge easier, always sort it by qbase.
2998          * Find adjacent prev and last entries.
2999          */
3000         prev = next = NULL;
3001         LIST_FOREACH(entry, &pool->free_list, next) {
3002                 if (entry->base > valid_entry->base) {
3003                         next = entry;
3004                         break;
3005                 }
3006                 prev = entry;
3007         }
3008
3009         insert = 0;
3010         /* Try to merge with next one*/
3011         if (next != NULL) {
3012                 /* Merge with next one */
3013                 if (valid_entry->base + valid_entry->len == next->base) {
3014                         next->base = valid_entry->base;
3015                         next->len += valid_entry->len;
3016                         rte_free(valid_entry);
3017                         valid_entry = next;
3018                         insert = 1;
3019                 }
3020         }
3021
3022         if (prev != NULL) {
3023                 /* Merge with previous one */
3024                 if (prev->base + prev->len == valid_entry->base) {
3025                         prev->len += valid_entry->len;
3026                         /* If it merge with next one, remove next node */
3027                         if (insert == 1) {
3028                                 LIST_REMOVE(valid_entry, next);
3029                                 rte_free(valid_entry);
3030                         } else {
3031                                 rte_free(valid_entry);
3032                                 insert = 1;
3033                         }
3034                 }
3035         }
3036
3037         /* Not find any entry to merge, insert */
3038         if (insert == 0) {
3039                 if (prev != NULL)
3040                         LIST_INSERT_AFTER(prev, valid_entry, next);
3041                 else if (next != NULL)
3042                         LIST_INSERT_BEFORE(next, valid_entry, next);
3043                 else /* It's empty list, insert to head */
3044                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3045         }
3046
3047         pool->num_free += valid_entry->len;
3048         pool->num_alloc -= valid_entry->len;
3049
3050         return 0;
3051 }
3052
3053 static int
3054 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3055                        uint16_t num)
3056 {
3057         struct pool_entry *entry, *valid_entry;
3058
3059         if (pool == NULL || num == 0) {
3060                 PMD_DRV_LOG(ERR, "Invalid parameter");
3061                 return -EINVAL;
3062         }
3063
3064         if (pool->num_free < num) {
3065                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3066                             num, pool->num_free);
3067                 return -ENOMEM;
3068         }
3069
3070         valid_entry = NULL;
3071         /* Lookup  in free list and find most fit one */
3072         LIST_FOREACH(entry, &pool->free_list, next) {
3073                 if (entry->len >= num) {
3074                         /* Find best one */
3075                         if (entry->len == num) {
3076                                 valid_entry = entry;
3077                                 break;
3078                         }
3079                         if (valid_entry == NULL || valid_entry->len > entry->len)
3080                                 valid_entry = entry;
3081                 }
3082         }
3083
3084         /* Not find one to satisfy the request, return */
3085         if (valid_entry == NULL) {
3086                 PMD_DRV_LOG(ERR, "No valid entry found");
3087                 return -ENOMEM;
3088         }
3089         /**
3090          * The entry have equal queue number as requested,
3091          * remove it from alloc_list.
3092          */
3093         if (valid_entry->len == num) {
3094                 LIST_REMOVE(valid_entry, next);
3095         } else {
3096                 /**
3097                  * The entry have more numbers than requested,
3098                  * create a new entry for alloc_list and minus its
3099                  * queue base and number in free_list.
3100                  */
3101                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3102                 if (entry == NULL) {
3103                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3104                                     "resource pool");
3105                         return -ENOMEM;
3106                 }
3107                 entry->base = valid_entry->base;
3108                 entry->len = num;
3109                 valid_entry->base += num;
3110                 valid_entry->len -= num;
3111                 valid_entry = entry;
3112         }
3113
3114         /* Insert it into alloc list, not sorted */
3115         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3116
3117         pool->num_free -= valid_entry->len;
3118         pool->num_alloc += valid_entry->len;
3119
3120         return (valid_entry->base + pool->base);
3121 }
3122
3123 /**
3124  * bitmap_is_subset - Check whether src2 is subset of src1
3125  **/
3126 static inline int
3127 bitmap_is_subset(uint8_t src1, uint8_t src2)
3128 {
3129         return !((src1 ^ src2) & src2);
3130 }
3131
3132 static int
3133 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3134 {
3135         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3136
3137         /* If DCB is not supported, only default TC is supported */
3138         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3139                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3140                 return -EINVAL;
3141         }
3142
3143         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3144                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3145                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3146                             enabled_tcmap);
3147                 return -EINVAL;
3148         }
3149         return I40E_SUCCESS;
3150 }
3151
3152 int
3153 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3154                                 struct i40e_vsi_vlan_pvid_info *info)
3155 {
3156         struct i40e_hw *hw;
3157         struct i40e_vsi_context ctxt;
3158         uint8_t vlan_flags = 0;
3159         int ret;
3160
3161         if (vsi == NULL || info == NULL) {
3162                 PMD_DRV_LOG(ERR, "invalid parameters");
3163                 return I40E_ERR_PARAM;
3164         }
3165
3166         if (info->on) {
3167                 vsi->info.pvid = info->config.pvid;
3168                 /**
3169                  * If insert pvid is enabled, only tagged pkts are
3170                  * allowed to be sent out.
3171                  */
3172                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3173                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3174         } else {
3175                 vsi->info.pvid = 0;
3176                 if (info->config.reject.tagged == 0)
3177                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3178
3179                 if (info->config.reject.untagged == 0)
3180                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3181         }
3182         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3183                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3184         vsi->info.port_vlan_flags |= vlan_flags;
3185         vsi->info.valid_sections =
3186                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3187         memset(&ctxt, 0, sizeof(ctxt));
3188         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3189         ctxt.seid = vsi->seid;
3190
3191         hw = I40E_VSI_TO_HW(vsi);
3192         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3193         if (ret != I40E_SUCCESS)
3194                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3195
3196         return ret;
3197 }
3198
3199 static int
3200 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3201 {
3202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3203         int i, ret;
3204         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3205
3206         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3207         if (ret != I40E_SUCCESS)
3208                 return ret;
3209
3210         if (!vsi->seid) {
3211                 PMD_DRV_LOG(ERR, "seid not valid");
3212                 return -EINVAL;
3213         }
3214
3215         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3216         tc_bw_data.tc_valid_bits = enabled_tcmap;
3217         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3218                 tc_bw_data.tc_bw_credits[i] =
3219                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3220
3221         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3222         if (ret != I40E_SUCCESS) {
3223                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3224                 return ret;
3225         }
3226
3227         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3228                                         sizeof(vsi->info.qs_handle));
3229         return I40E_SUCCESS;
3230 }
3231
3232 static int
3233 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3234                                  struct i40e_aqc_vsi_properties_data *info,
3235                                  uint8_t enabled_tcmap)
3236 {
3237         int ret, i, total_tc = 0;
3238         uint16_t qpnum_per_tc, bsf, qp_idx;
3239
3240         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3241         if (ret != I40E_SUCCESS)
3242                 return ret;
3243
3244         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3245                 if (enabled_tcmap & (1 << i))
3246                         total_tc++;
3247         vsi->enabled_tc = enabled_tcmap;
3248
3249         /* Number of queues per enabled TC */
3250         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3251         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3252         bsf = rte_bsf32(qpnum_per_tc);
3253
3254         /* Adjust the queue number to actual queues that can be applied */
3255         vsi->nb_qps = qpnum_per_tc * total_tc;
3256
3257         /**
3258          * Configure TC and queue mapping parameters, for enabled TC,
3259          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3260          * default queue will serve it.
3261          */
3262         qp_idx = 0;
3263         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3264                 if (vsi->enabled_tc & (1 << i)) {
3265                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3266                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3267                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3268                         qp_idx += qpnum_per_tc;
3269                 } else
3270                         info->tc_mapping[i] = 0;
3271         }
3272
3273         /* Associate queue number with VSI */
3274         if (vsi->type == I40E_VSI_SRIOV) {
3275                 info->mapping_flags |=
3276                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3277                 for (i = 0; i < vsi->nb_qps; i++)
3278                         info->queue_mapping[i] =
3279                                 rte_cpu_to_le_16(vsi->base_queue + i);
3280         } else {
3281                 info->mapping_flags |=
3282                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3283                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3284         }
3285         info->valid_sections |=
3286                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3287
3288         return I40E_SUCCESS;
3289 }
3290
3291 static int
3292 i40e_veb_release(struct i40e_veb *veb)
3293 {
3294         struct i40e_vsi *vsi;
3295         struct i40e_hw *hw;
3296
3297         if (veb == NULL || veb->associate_vsi == NULL)
3298                 return -EINVAL;
3299
3300         if (!TAILQ_EMPTY(&veb->head)) {
3301                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3302                 return -EACCES;
3303         }
3304
3305         vsi = veb->associate_vsi;
3306         hw = I40E_VSI_TO_HW(vsi);
3307
3308         vsi->uplink_seid = veb->uplink_seid;
3309         i40e_aq_delete_element(hw, veb->seid, NULL);
3310         rte_free(veb);
3311         vsi->veb = NULL;
3312         return I40E_SUCCESS;
3313 }
3314
3315 /* Setup a veb */
3316 static struct i40e_veb *
3317 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3318 {
3319         struct i40e_veb *veb;
3320         int ret;
3321         struct i40e_hw *hw;
3322
3323         if (NULL == pf || vsi == NULL) {
3324                 PMD_DRV_LOG(ERR, "veb setup failed, "
3325                             "associated VSI shouldn't null");
3326                 return NULL;
3327         }
3328         hw = I40E_PF_TO_HW(pf);
3329
3330         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3331         if (!veb) {
3332                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3333                 goto fail;
3334         }
3335
3336         veb->associate_vsi = vsi;
3337         TAILQ_INIT(&veb->head);
3338         veb->uplink_seid = vsi->uplink_seid;
3339
3340         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3341                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3342
3343         if (ret != I40E_SUCCESS) {
3344                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3345                             hw->aq.asq_last_status);
3346                 goto fail;
3347         }
3348
3349         /* get statistics index */
3350         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3351                                 &veb->stats_idx, NULL, NULL, NULL);
3352         if (ret != I40E_SUCCESS) {
3353                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3354                             hw->aq.asq_last_status);
3355                 goto fail;
3356         }
3357
3358         /* Get VEB bandwidth, to be implemented */
3359         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3360         vsi->uplink_seid = veb->seid;
3361
3362         return veb;
3363 fail:
3364         rte_free(veb);
3365         return NULL;
3366 }
3367
3368 int
3369 i40e_vsi_release(struct i40e_vsi *vsi)
3370 {
3371         struct i40e_pf *pf;
3372         struct i40e_hw *hw;
3373         struct i40e_vsi_list *vsi_list;
3374         int ret;
3375         struct i40e_mac_filter *f;
3376
3377         if (!vsi)
3378                 return I40E_SUCCESS;
3379
3380         pf = I40E_VSI_TO_PF(vsi);
3381         hw = I40E_VSI_TO_HW(vsi);
3382
3383         /* VSI has child to attach, release child first */
3384         if (vsi->veb) {
3385                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3386                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3387                                 return -1;
3388                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3389                 }
3390                 i40e_veb_release(vsi->veb);
3391         }
3392
3393         /* Remove all macvlan filters of the VSI */
3394         i40e_vsi_remove_all_macvlan_filter(vsi);
3395         TAILQ_FOREACH(f, &vsi->mac_list, next)
3396                 rte_free(f);
3397
3398         if (vsi->type != I40E_VSI_MAIN) {
3399                 /* Remove vsi from parent's sibling list */
3400                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3401                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3402                         return I40E_ERR_PARAM;
3403                 }
3404                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3405                                 &vsi->sib_vsi_list, list);
3406
3407                 /* Remove all switch element of the VSI */
3408                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3409                 if (ret != I40E_SUCCESS)
3410                         PMD_DRV_LOG(ERR, "Failed to delete element");
3411         }
3412         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3413
3414         if (vsi->type != I40E_VSI_SRIOV)
3415                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3416         rte_free(vsi);
3417
3418         return I40E_SUCCESS;
3419 }
3420
3421 static int
3422 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3423 {
3424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3425         struct i40e_aqc_remove_macvlan_element_data def_filter;
3426         struct i40e_mac_filter_info filter;
3427         int ret;
3428
3429         if (vsi->type != I40E_VSI_MAIN)
3430                 return I40E_ERR_CONFIG;
3431         memset(&def_filter, 0, sizeof(def_filter));
3432         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3433                                         ETH_ADDR_LEN);
3434         def_filter.vlan_tag = 0;
3435         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3436                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3437         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3438         if (ret != I40E_SUCCESS) {
3439                 struct i40e_mac_filter *f;
3440                 struct ether_addr *mac;
3441
3442                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3443                             "macvlan filter");
3444                 /* It needs to add the permanent mac into mac list */
3445                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3446                 if (f == NULL) {
3447                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3448                         return I40E_ERR_NO_MEMORY;
3449                 }
3450                 mac = &f->mac_info.mac_addr;
3451                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3452                                 ETH_ADDR_LEN);
3453                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3454                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3455                 vsi->mac_num++;
3456
3457                 return ret;
3458         }
3459         (void)rte_memcpy(&filter.mac_addr,
3460                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3461         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3462         return i40e_vsi_add_mac(vsi, &filter);
3463 }
3464
3465 static int
3466 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3467 {
3468         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3469         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3470         struct i40e_hw *hw = &vsi->adapter->hw;
3471         i40e_status ret;
3472         int i;
3473
3474         memset(&bw_config, 0, sizeof(bw_config));
3475         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3476         if (ret != I40E_SUCCESS) {
3477                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3478                             hw->aq.asq_last_status);
3479                 return ret;
3480         }
3481
3482         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3483         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3484                                         &ets_sla_config, NULL);
3485         if (ret != I40E_SUCCESS) {
3486                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3487                             "configuration %u", hw->aq.asq_last_status);
3488                 return ret;
3489         }
3490
3491         /* Not store the info yet, just print out */
3492         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3493         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3494         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3495                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3496                             ets_sla_config.share_credits[i]);
3497                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3498                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3499                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3500                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3501                             (i * 4));
3502         }
3503
3504         return 0;
3505 }
3506
3507 /* Setup a VSI */
3508 struct i40e_vsi *
3509 i40e_vsi_setup(struct i40e_pf *pf,
3510                enum i40e_vsi_type type,
3511                struct i40e_vsi *uplink_vsi,
3512                uint16_t user_param)
3513 {
3514         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3515         struct i40e_vsi *vsi;
3516         struct i40e_mac_filter_info filter;
3517         int ret;
3518         struct i40e_vsi_context ctxt;
3519         struct ether_addr broadcast =
3520                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3521
3522         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3523                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3524                             "VSI link shouldn't be NULL");
3525                 return NULL;
3526         }
3527
3528         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3529                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3530                             "uplink VSI should be NULL");
3531                 return NULL;
3532         }
3533
3534         /* If uplink vsi didn't setup VEB, create one first */
3535         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3536                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3537
3538                 if (NULL == uplink_vsi->veb) {
3539                         PMD_DRV_LOG(ERR, "VEB setup failed");
3540                         return NULL;
3541                 }
3542         }
3543
3544         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3545         if (!vsi) {
3546                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3547                 return NULL;
3548         }
3549         TAILQ_INIT(&vsi->mac_list);
3550         vsi->type = type;
3551         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3552         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3553         vsi->parent_vsi = uplink_vsi;
3554         vsi->user_param = user_param;
3555         /* Allocate queues */
3556         switch (vsi->type) {
3557         case I40E_VSI_MAIN  :
3558                 vsi->nb_qps = pf->lan_nb_qps;
3559                 break;
3560         case I40E_VSI_SRIOV :
3561                 vsi->nb_qps = pf->vf_nb_qps;
3562                 break;
3563         case I40E_VSI_VMDQ2:
3564                 vsi->nb_qps = pf->vmdq_nb_qps;
3565                 break;
3566         case I40E_VSI_FDIR:
3567                 vsi->nb_qps = pf->fdir_nb_qps;
3568                 break;
3569         default:
3570                 goto fail_mem;
3571         }
3572         /*
3573          * The filter status descriptor is reported in rx queue 0,
3574          * while the tx queue for fdir filter programming has no
3575          * such constraints, can be non-zero queues.
3576          * To simplify it, choose FDIR vsi use queue 0 pair.
3577          * To make sure it will use queue 0 pair, queue allocation
3578          * need be done before this function is called
3579          */
3580         if (type != I40E_VSI_FDIR) {
3581                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3582                         if (ret < 0) {
3583                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3584                                                 vsi->seid, ret);
3585                                 goto fail_mem;
3586                         }
3587                         vsi->base_queue = ret;
3588         } else
3589                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3590
3591         /* VF has MSIX interrupt in VF range, don't allocate here */
3592         if (type != I40E_VSI_SRIOV) {
3593                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3594                 if (ret < 0) {
3595                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3596                         goto fail_queue_alloc;
3597                 }
3598                 vsi->msix_intr = ret;
3599         } else
3600                 vsi->msix_intr = 0;
3601         /* Add VSI */
3602         if (type == I40E_VSI_MAIN) {
3603                 /* For main VSI, no need to add since it's default one */
3604                 vsi->uplink_seid = pf->mac_seid;
3605                 vsi->seid = pf->main_vsi_seid;
3606                 /* Bind queues with specific MSIX interrupt */
3607                 /**
3608                  * Needs 2 interrupt at least, one for misc cause which will
3609                  * enabled from OS side, Another for queues binding the
3610                  * interrupt from device side only.
3611                  */
3612
3613                 /* Get default VSI parameters from hardware */
3614                 memset(&ctxt, 0, sizeof(ctxt));
3615                 ctxt.seid = vsi->seid;
3616                 ctxt.pf_num = hw->pf_id;
3617                 ctxt.uplink_seid = vsi->uplink_seid;
3618                 ctxt.vf_num = 0;
3619                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3620                 if (ret != I40E_SUCCESS) {
3621                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3622                         goto fail_msix_alloc;
3623                 }
3624                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3625                         sizeof(struct i40e_aqc_vsi_properties_data));
3626                 vsi->vsi_id = ctxt.vsi_number;
3627                 vsi->info.valid_sections = 0;
3628
3629                 /* Configure tc, enabled TC0 only */
3630                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3631                         I40E_SUCCESS) {
3632                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3633                         goto fail_msix_alloc;
3634                 }
3635
3636                 /* TC, queue mapping */
3637                 memset(&ctxt, 0, sizeof(ctxt));
3638                 vsi->info.valid_sections |=
3639                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3640                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3641                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3642                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3643                         sizeof(struct i40e_aqc_vsi_properties_data));
3644                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3645                                                 I40E_DEFAULT_TCMAP);
3646                 if (ret != I40E_SUCCESS) {
3647                         PMD_DRV_LOG(ERR, "Failed to configure "
3648                                     "TC queue mapping");
3649                         goto fail_msix_alloc;
3650                 }
3651                 ctxt.seid = vsi->seid;
3652                 ctxt.pf_num = hw->pf_id;
3653                 ctxt.uplink_seid = vsi->uplink_seid;
3654                 ctxt.vf_num = 0;
3655
3656                 /* Update VSI parameters */
3657                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3658                 if (ret != I40E_SUCCESS) {
3659                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3660                         goto fail_msix_alloc;
3661                 }
3662
3663                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3664                                                 sizeof(vsi->info.tc_mapping));
3665                 (void)rte_memcpy(&vsi->info.queue_mapping,
3666                                 &ctxt.info.queue_mapping,
3667                         sizeof(vsi->info.queue_mapping));
3668                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3669                 vsi->info.valid_sections = 0;
3670
3671                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3672                                 ETH_ADDR_LEN);
3673
3674                 /**
3675                  * Updating default filter settings are necessary to prevent
3676                  * reception of tagged packets.
3677                  * Some old firmware configurations load a default macvlan
3678                  * filter which accepts both tagged and untagged packets.
3679                  * The updating is to use a normal filter instead if needed.
3680                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3681                  * The firmware with correct configurations load the default
3682                  * macvlan filter which is expected and cannot be removed.
3683                  */
3684                 i40e_update_default_filter_setting(vsi);
3685                 i40e_config_qinq(hw, vsi);
3686         } else if (type == I40E_VSI_SRIOV) {
3687                 memset(&ctxt, 0, sizeof(ctxt));
3688                 /**
3689                  * For other VSI, the uplink_seid equals to uplink VSI's
3690                  * uplink_seid since they share same VEB
3691                  */
3692                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3693                 ctxt.pf_num = hw->pf_id;
3694                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3695                 ctxt.uplink_seid = vsi->uplink_seid;
3696                 ctxt.connection_type = 0x1;
3697                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3698
3699                 /**
3700                  * Do not configure switch ID to enable VEB switch by
3701                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3702                  * if the source mac address of packet sent from VF is not
3703                  * listed in the VEB's mac table, the VEB will switch the
3704                  * packet back to the VF. Need to enable it when HW issue
3705                  * is fixed.
3706                  */
3707
3708                 /* Configure port/vlan */
3709                 ctxt.info.valid_sections |=
3710                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3711                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3712                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3713                                                 I40E_DEFAULT_TCMAP);
3714                 if (ret != I40E_SUCCESS) {
3715                         PMD_DRV_LOG(ERR, "Failed to configure "
3716                                     "TC queue mapping");
3717                         goto fail_msix_alloc;
3718                 }
3719                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3720                 ctxt.info.valid_sections |=
3721                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3722                 /**
3723                  * Since VSI is not created yet, only configure parameter,
3724                  * will add vsi below.
3725                  */
3726
3727                 i40e_config_qinq(hw, vsi);
3728         } else if (type == I40E_VSI_VMDQ2) {
3729                 memset(&ctxt, 0, sizeof(ctxt));
3730                 /*
3731                  * For other VSI, the uplink_seid equals to uplink VSI's
3732                  * uplink_seid since they share same VEB
3733                  */
3734                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3735                 ctxt.pf_num = hw->pf_id;
3736                 ctxt.vf_num = 0;
3737                 ctxt.uplink_seid = vsi->uplink_seid;
3738                 ctxt.connection_type = 0x1;
3739                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3740
3741                 ctxt.info.valid_sections |=
3742                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3743                 /* user_param carries flag to enable loop back */
3744                 if (user_param) {
3745                         ctxt.info.switch_id =
3746                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3747                         ctxt.info.switch_id |=
3748                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3749                 }
3750
3751                 /* Configure port/vlan */
3752                 ctxt.info.valid_sections |=
3753                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3754                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3755                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3756                                                 I40E_DEFAULT_TCMAP);
3757                 if (ret != I40E_SUCCESS) {
3758                         PMD_DRV_LOG(ERR, "Failed to configure "
3759                                         "TC queue mapping");
3760                         goto fail_msix_alloc;
3761                 }
3762                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3763                 ctxt.info.valid_sections |=
3764                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3765         } else if (type == I40E_VSI_FDIR) {
3766                 memset(&ctxt, 0, sizeof(ctxt));
3767                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3768                 ctxt.pf_num = hw->pf_id;
3769                 ctxt.vf_num = 0;
3770                 ctxt.uplink_seid = vsi->uplink_seid;
3771                 ctxt.connection_type = 0x1;     /* regular data port */
3772                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3773                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3774                                                 I40E_DEFAULT_TCMAP);
3775                 if (ret != I40E_SUCCESS) {
3776                         PMD_DRV_LOG(ERR, "Failed to configure "
3777                                         "TC queue mapping.");
3778                         goto fail_msix_alloc;
3779                 }
3780                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3781                 ctxt.info.valid_sections |=
3782                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3783         } else {
3784                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3785                 goto fail_msix_alloc;
3786         }
3787
3788         if (vsi->type != I40E_VSI_MAIN) {
3789                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3790                 if (ret != I40E_SUCCESS) {
3791                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3792                                     hw->aq.asq_last_status);
3793                         goto fail_msix_alloc;
3794                 }
3795                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3796                 vsi->info.valid_sections = 0;
3797                 vsi->seid = ctxt.seid;
3798                 vsi->vsi_id = ctxt.vsi_number;
3799                 vsi->sib_vsi_list.vsi = vsi;
3800                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3801                                 &vsi->sib_vsi_list, list);
3802         }
3803
3804         /* MAC/VLAN configuration */
3805         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3806         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3807
3808         ret = i40e_vsi_add_mac(vsi, &filter);
3809         if (ret != I40E_SUCCESS) {
3810                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3811                 goto fail_msix_alloc;
3812         }
3813
3814         /* Get VSI BW information */
3815         i40e_vsi_dump_bw_config(vsi);
3816         return vsi;
3817 fail_msix_alloc:
3818         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3819 fail_queue_alloc:
3820         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3821 fail_mem:
3822         rte_free(vsi);
3823         return NULL;
3824 }
3825
3826 /* Configure vlan stripping on or off */
3827 int
3828 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3829 {
3830         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3831         struct i40e_vsi_context ctxt;
3832         uint8_t vlan_flags;
3833         int ret = I40E_SUCCESS;
3834
3835         /* Check if it has been already on or off */
3836         if (vsi->info.valid_sections &
3837                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3838                 if (on) {
3839                         if ((vsi->info.port_vlan_flags &
3840                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3841                                 return 0; /* already on */
3842                 } else {
3843                         if ((vsi->info.port_vlan_flags &
3844                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3845                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3846                                 return 0; /* already off */
3847                 }
3848         }
3849
3850         if (on)
3851                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3852         else
3853                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3854         vsi->info.valid_sections =
3855                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3856         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3857         vsi->info.port_vlan_flags |= vlan_flags;
3858         ctxt.seid = vsi->seid;
3859         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3860         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3861         if (ret)
3862                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3863                             on ? "enable" : "disable");
3864
3865         return ret;
3866 }
3867
3868 static int
3869 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3870 {
3871         struct rte_eth_dev_data *data = dev->data;
3872         int ret;
3873
3874         /* Apply vlan offload setting */
3875         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3876
3877         /* Apply double-vlan setting, not implemented yet */
3878
3879         /* Apply pvid setting */
3880         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3881                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3882         if (ret)
3883                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3884
3885         return ret;
3886 }
3887
3888 static int
3889 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3890 {
3891         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3892
3893         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3894 }
3895
3896 static int
3897 i40e_update_flow_control(struct i40e_hw *hw)
3898 {
3899 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3900         struct i40e_link_status link_status;
3901         uint32_t rxfc = 0, txfc = 0, reg;
3902         uint8_t an_info;
3903         int ret;
3904
3905         memset(&link_status, 0, sizeof(link_status));
3906         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3907         if (ret != I40E_SUCCESS) {
3908                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3909                 goto write_reg; /* Disable flow control */
3910         }
3911
3912         an_info = hw->phy.link_info.an_info;
3913         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3914                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3915                 ret = I40E_ERR_NOT_READY;
3916                 goto write_reg; /* Disable flow control */
3917         }
3918         /**
3919          * If link auto negotiation is enabled, flow control needs to
3920          * be configured according to it
3921          */
3922         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3923         case I40E_LINK_PAUSE_RXTX:
3924                 rxfc = 1;
3925                 txfc = 1;
3926                 hw->fc.current_mode = I40E_FC_FULL;
3927                 break;
3928         case I40E_AQ_LINK_PAUSE_RX:
3929                 rxfc = 1;
3930                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3931                 break;
3932         case I40E_AQ_LINK_PAUSE_TX:
3933                 txfc = 1;
3934                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3935                 break;
3936         default:
3937                 hw->fc.current_mode = I40E_FC_NONE;
3938                 break;
3939         }
3940
3941 write_reg:
3942         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3943                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3944         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3945         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3946         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3947         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3948
3949         return ret;
3950 }
3951
3952 /* PF setup */
3953 static int
3954 i40e_pf_setup(struct i40e_pf *pf)
3955 {
3956         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3957         struct i40e_filter_control_settings settings;
3958         struct i40e_vsi *vsi;
3959         int ret;
3960
3961         /* Clear all stats counters */
3962         pf->offset_loaded = FALSE;
3963         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3964         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3965
3966         ret = i40e_pf_get_switch_config(pf);
3967         if (ret != I40E_SUCCESS) {
3968                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3969                 return ret;
3970         }
3971         if (pf->flags & I40E_FLAG_FDIR) {
3972                 /* make queue allocated first, let FDIR use queue pair 0*/
3973                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3974                 if (ret != I40E_FDIR_QUEUE_ID) {
3975                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3976                                     " ret =%d", ret);
3977                         pf->flags &= ~I40E_FLAG_FDIR;
3978                 }
3979         }
3980         /*  main VSI setup */
3981         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3982         if (!vsi) {
3983                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3984                 return I40E_ERR_NOT_READY;
3985         }
3986         pf->main_vsi = vsi;
3987
3988         /* Configure filter control */
3989         memset(&settings, 0, sizeof(settings));
3990         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3991                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3992         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3993                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3994         else {
3995                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3996                                                 hw->func_caps.rss_table_size);
3997                 return I40E_ERR_PARAM;
3998         }
3999         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4000                         "size: %u\n", hw->func_caps.rss_table_size);
4001         pf->hash_lut_size = hw->func_caps.rss_table_size;
4002
4003         /* Enable ethtype and macvlan filters */
4004         settings.enable_ethtype = TRUE;
4005         settings.enable_macvlan = TRUE;
4006         ret = i40e_set_filter_control(hw, &settings);
4007         if (ret)
4008                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4009                                                                 ret);
4010
4011         /* Update flow control according to the auto negotiation */
4012         i40e_update_flow_control(hw);
4013
4014         return I40E_SUCCESS;
4015 }
4016
4017 int
4018 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4019 {
4020         uint32_t reg;
4021         uint16_t j;
4022
4023         /**
4024          * Set or clear TX Queue Disable flags,
4025          * which is required by hardware.
4026          */
4027         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4028         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4029
4030         /* Wait until the request is finished */
4031         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4032                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4033                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4034                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4035                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4036                                                         & 0x1))) {
4037                         break;
4038                 }
4039         }
4040         if (on) {
4041                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4042                         return I40E_SUCCESS; /* already on, skip next steps */
4043
4044                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4045                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4046         } else {
4047                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4048                         return I40E_SUCCESS; /* already off, skip next steps */
4049                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4050         }
4051         /* Write the register */
4052         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4053         /* Check the result */
4054         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4055                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4056                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4057                 if (on) {
4058                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4059                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4060                                 break;
4061                 } else {
4062                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4063                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4064                                 break;
4065                 }
4066         }
4067         /* Check if it is timeout */
4068         if (j >= I40E_CHK_Q_ENA_COUNT) {
4069                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4070                             (on ? "enable" : "disable"), q_idx);
4071                 return I40E_ERR_TIMEOUT;
4072         }
4073
4074         return I40E_SUCCESS;
4075 }
4076
4077 /* Swith on or off the tx queues */
4078 static int
4079 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4080 {
4081         struct rte_eth_dev_data *dev_data = pf->dev_data;
4082         struct i40e_tx_queue *txq;
4083         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4084         uint16_t i;
4085         int ret;
4086
4087         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4088                 txq = dev_data->tx_queues[i];
4089                 /* Don't operate the queue if not configured or
4090                  * if starting only per queue */
4091                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4092                         continue;
4093                 if (on)
4094                         ret = i40e_dev_tx_queue_start(dev, i);
4095                 else
4096                         ret = i40e_dev_tx_queue_stop(dev, i);
4097                 if ( ret != I40E_SUCCESS)
4098                         return ret;
4099         }
4100
4101         return I40E_SUCCESS;
4102 }
4103
4104 int
4105 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4106 {
4107         uint32_t reg;
4108         uint16_t j;
4109
4110         /* Wait until the request is finished */
4111         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4112                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4113                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4114                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4115                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4116                         break;
4117         }
4118
4119         if (on) {
4120                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4121                         return I40E_SUCCESS; /* Already on, skip next steps */
4122                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4123         } else {
4124                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4125                         return I40E_SUCCESS; /* Already off, skip next steps */
4126                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4127         }
4128
4129         /* Write the register */
4130         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4131         /* Check the result */
4132         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4133                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4134                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4135                 if (on) {
4136                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4137                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4138                                 break;
4139                 } else {
4140                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4141                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4142                                 break;
4143                 }
4144         }
4145
4146         /* Check if it is timeout */
4147         if (j >= I40E_CHK_Q_ENA_COUNT) {
4148                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4149                             (on ? "enable" : "disable"), q_idx);
4150                 return I40E_ERR_TIMEOUT;
4151         }
4152
4153         return I40E_SUCCESS;
4154 }
4155 /* Switch on or off the rx queues */
4156 static int
4157 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4158 {
4159         struct rte_eth_dev_data *dev_data = pf->dev_data;
4160         struct i40e_rx_queue *rxq;
4161         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4162         uint16_t i;
4163         int ret;
4164
4165         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4166                 rxq = dev_data->rx_queues[i];
4167                 /* Don't operate the queue if not configured or
4168                  * if starting only per queue */
4169                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4170                         continue;
4171                 if (on)
4172                         ret = i40e_dev_rx_queue_start(dev, i);
4173                 else
4174                         ret = i40e_dev_rx_queue_stop(dev, i);
4175                 if (ret != I40E_SUCCESS)
4176                         return ret;
4177         }
4178
4179         return I40E_SUCCESS;
4180 }
4181
4182 /* Switch on or off all the rx/tx queues */
4183 int
4184 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4185 {
4186         int ret;
4187
4188         if (on) {
4189                 /* enable rx queues before enabling tx queues */
4190                 ret = i40e_dev_switch_rx_queues(pf, on);
4191                 if (ret) {
4192                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4193                         return ret;
4194                 }
4195                 ret = i40e_dev_switch_tx_queues(pf, on);
4196         } else {
4197                 /* Stop tx queues before stopping rx queues */
4198                 ret = i40e_dev_switch_tx_queues(pf, on);
4199                 if (ret) {
4200                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4201                         return ret;
4202                 }
4203                 ret = i40e_dev_switch_rx_queues(pf, on);
4204         }
4205
4206         return ret;
4207 }
4208
4209 /* Initialize VSI for TX */
4210 static int
4211 i40e_dev_tx_init(struct i40e_pf *pf)
4212 {
4213         struct rte_eth_dev_data *data = pf->dev_data;
4214         uint16_t i;
4215         uint32_t ret = I40E_SUCCESS;
4216         struct i40e_tx_queue *txq;
4217
4218         for (i = 0; i < data->nb_tx_queues; i++) {
4219                 txq = data->tx_queues[i];
4220                 if (!txq || !txq->q_set)
4221                         continue;
4222                 ret = i40e_tx_queue_init(txq);
4223                 if (ret != I40E_SUCCESS)
4224                         break;
4225         }
4226         if (ret == I40E_SUCCESS)
4227                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4228                                      ->eth_dev);
4229
4230         return ret;
4231 }
4232
4233 /* Initialize VSI for RX */
4234 static int
4235 i40e_dev_rx_init(struct i40e_pf *pf)
4236 {
4237         struct rte_eth_dev_data *data = pf->dev_data;
4238         int ret = I40E_SUCCESS;
4239         uint16_t i;
4240         struct i40e_rx_queue *rxq;
4241
4242         i40e_pf_config_mq_rx(pf);
4243         for (i = 0; i < data->nb_rx_queues; i++) {
4244                 rxq = data->rx_queues[i];
4245                 if (!rxq || !rxq->q_set)
4246                         continue;
4247
4248                 ret = i40e_rx_queue_init(rxq);
4249                 if (ret != I40E_SUCCESS) {
4250                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4251                                     "initialization");
4252                         break;
4253                 }
4254         }
4255         if (ret == I40E_SUCCESS)
4256                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4257                                      ->eth_dev);
4258
4259         return ret;
4260 }
4261
4262 static int
4263 i40e_dev_rxtx_init(struct i40e_pf *pf)
4264 {
4265         int err;
4266
4267         err = i40e_dev_tx_init(pf);
4268         if (err) {
4269                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4270                 return err;
4271         }
4272         err = i40e_dev_rx_init(pf);
4273         if (err) {
4274                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4275                 return err;
4276         }
4277
4278         return err;
4279 }
4280
4281 static int
4282 i40e_vmdq_setup(struct rte_eth_dev *dev)
4283 {
4284         struct rte_eth_conf *conf = &dev->data->dev_conf;
4285         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4286         int i, err, conf_vsis, j, loop;
4287         struct i40e_vsi *vsi;
4288         struct i40e_vmdq_info *vmdq_info;
4289         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4291
4292         /*
4293          * Disable interrupt to avoid message from VF. Furthermore, it will
4294          * avoid race condition in VSI creation/destroy.
4295          */
4296         i40e_pf_disable_irq0(hw);
4297
4298         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4299                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4300                 return -ENOTSUP;
4301         }
4302
4303         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4304         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4305                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4306                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4307                         pf->max_nb_vmdq_vsi);
4308                 return -ENOTSUP;
4309         }
4310
4311         if (pf->vmdq != NULL) {
4312                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4313                 return 0;
4314         }
4315
4316         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4317                                 sizeof(*vmdq_info) * conf_vsis, 0);
4318
4319         if (pf->vmdq == NULL) {
4320                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4321                 return -ENOMEM;
4322         }
4323
4324         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4325
4326         /* Create VMDQ VSI */
4327         for (i = 0; i < conf_vsis; i++) {
4328                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4329                                 vmdq_conf->enable_loop_back);
4330                 if (vsi == NULL) {
4331                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4332                         err = -1;
4333                         goto err_vsi_setup;
4334                 }
4335                 vmdq_info = &pf->vmdq[i];
4336                 vmdq_info->pf = pf;
4337                 vmdq_info->vsi = vsi;
4338         }
4339         pf->nb_cfg_vmdq_vsi = conf_vsis;
4340
4341         /* Configure Vlan */
4342         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4343         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4344                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4345                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4346                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4347                                         vmdq_conf->pool_map[i].vlan_id, j);
4348
4349                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4350                                                 vmdq_conf->pool_map[i].vlan_id);
4351                                 if (err) {
4352                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4353                                         err = -1;
4354                                         goto err_vsi_setup;
4355                                 }
4356                         }
4357                 }
4358         }
4359
4360         i40e_pf_enable_irq0(hw);
4361
4362         return 0;
4363
4364 err_vsi_setup:
4365         for (i = 0; i < conf_vsis; i++)
4366                 if (pf->vmdq[i].vsi == NULL)
4367                         break;
4368                 else
4369                         i40e_vsi_release(pf->vmdq[i].vsi);
4370
4371         rte_free(pf->vmdq);
4372         pf->vmdq = NULL;
4373         i40e_pf_enable_irq0(hw);
4374         return err;
4375 }
4376
4377 static void
4378 i40e_stat_update_32(struct i40e_hw *hw,
4379                    uint32_t reg,
4380                    bool offset_loaded,
4381                    uint64_t *offset,
4382                    uint64_t *stat)
4383 {
4384         uint64_t new_data;
4385
4386         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4387         if (!offset_loaded)
4388                 *offset = new_data;
4389
4390         if (new_data >= *offset)
4391                 *stat = (uint64_t)(new_data - *offset);
4392         else
4393                 *stat = (uint64_t)((new_data +
4394                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4395 }
4396
4397 static void
4398 i40e_stat_update_48(struct i40e_hw *hw,
4399                    uint32_t hireg,
4400                    uint32_t loreg,
4401                    bool offset_loaded,
4402                    uint64_t *offset,
4403                    uint64_t *stat)
4404 {
4405         uint64_t new_data;
4406
4407         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4408         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4409                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4410
4411         if (!offset_loaded)
4412                 *offset = new_data;
4413
4414         if (new_data >= *offset)
4415                 *stat = new_data - *offset;
4416         else
4417                 *stat = (uint64_t)((new_data +
4418                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4419
4420         *stat &= I40E_48_BIT_MASK;
4421 }
4422
4423 /* Disable IRQ0 */
4424 void
4425 i40e_pf_disable_irq0(struct i40e_hw *hw)
4426 {
4427         /* Disable all interrupt types */
4428         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4429         I40E_WRITE_FLUSH(hw);
4430 }
4431
4432 /* Enable IRQ0 */
4433 void
4434 i40e_pf_enable_irq0(struct i40e_hw *hw)
4435 {
4436         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4437                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4438                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4439                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4440         I40E_WRITE_FLUSH(hw);
4441 }
4442
4443 static void
4444 i40e_pf_config_irq0(struct i40e_hw *hw)
4445 {
4446         /* read pending request and disable first */
4447         i40e_pf_disable_irq0(hw);
4448         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4449         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4450                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4451
4452         /* Link no queues with irq0 */
4453         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4454                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4455 }
4456
4457 static void
4458 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4459 {
4460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4462         int i;
4463         uint16_t abs_vf_id;
4464         uint32_t index, offset, val;
4465
4466         if (!pf->vfs)
4467                 return;
4468         /**
4469          * Try to find which VF trigger a reset, use absolute VF id to access
4470          * since the reg is global register.
4471          */
4472         for (i = 0; i < pf->vf_num; i++) {
4473                 abs_vf_id = hw->func_caps.vf_base_id + i;
4474                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4475                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4476                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4477                 /* VFR event occured */
4478                 if (val & (0x1 << offset)) {
4479                         int ret;
4480
4481                         /* Clear the event first */
4482                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4483                                                         (0x1 << offset));
4484                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4485                         /**
4486                          * Only notify a VF reset event occured,
4487                          * don't trigger another SW reset
4488                          */
4489                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4490                         if (ret != I40E_SUCCESS)
4491                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4492                 }
4493         }
4494 }
4495
4496 static void
4497 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4498 {
4499         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         struct i40e_arq_event_info info;
4501         uint16_t pending, opcode;
4502         int ret;
4503
4504         info.buf_len = I40E_AQ_BUF_SZ;
4505         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4506         if (!info.msg_buf) {
4507                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4508                 return;
4509         }
4510
4511         pending = 1;
4512         while (pending) {
4513                 ret = i40e_clean_arq_element(hw, &info, &pending);
4514
4515                 if (ret != I40E_SUCCESS) {
4516                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4517                                     "aq_err: %u", hw->aq.asq_last_status);
4518                         break;
4519                 }
4520                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4521
4522                 switch (opcode) {
4523                 case i40e_aqc_opc_send_msg_to_pf:
4524                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4525                         i40e_pf_host_handle_vf_msg(dev,
4526                                         rte_le_to_cpu_16(info.desc.retval),
4527                                         rte_le_to_cpu_32(info.desc.cookie_high),
4528                                         rte_le_to_cpu_32(info.desc.cookie_low),
4529                                         info.msg_buf,
4530                                         info.msg_len);
4531                         break;
4532                 default:
4533                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4534                                     opcode);
4535                         break;
4536                 }
4537         }
4538         rte_free(info.msg_buf);
4539 }
4540
4541 /*
4542  * Interrupt handler is registered as the alarm callback for handling LSC
4543  * interrupt in a definite of time, in order to wait the NIC into a stable
4544  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4545  * no need for link down interrupt.
4546  */
4547 static void
4548 i40e_dev_interrupt_delayed_handler(void *param)
4549 {
4550         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4552         uint32_t icr0;
4553
4554         /* read interrupt causes again */
4555         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4556
4557 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4558         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4559                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4560         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4561                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4562         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4563                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4564         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4565                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4566         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4567                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4568                                                                 "state\n");
4569         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4570                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4571         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4572                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4573 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4574
4575         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4576                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4577                 i40e_dev_handle_vfr_event(dev);
4578         }
4579         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4580                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4581                 i40e_dev_handle_aq_msg(dev);
4582         }
4583
4584         /* handle the link up interrupt in an alarm callback */
4585         i40e_dev_link_update(dev, 0);
4586         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4587
4588         i40e_pf_enable_irq0(hw);
4589         rte_intr_enable(&(dev->pci_dev->intr_handle));
4590 }
4591
4592 /**
4593  * Interrupt handler triggered by NIC  for handling
4594  * specific interrupt.
4595  *
4596  * @param handle
4597  *  Pointer to interrupt handle.
4598  * @param param
4599  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4600  *
4601  * @return
4602  *  void
4603  */
4604 static void
4605 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4606                            void *param)
4607 {
4608         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4609         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         uint32_t icr0;
4611
4612         /* Disable interrupt */
4613         i40e_pf_disable_irq0(hw);
4614
4615         /* read out interrupt causes */
4616         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4617
4618         /* No interrupt event indicated */
4619         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4620                 PMD_DRV_LOG(INFO, "No interrupt event");
4621                 goto done;
4622         }
4623 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4624         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4625                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4626         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4627                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4628         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4629                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4630         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4631                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4632         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4633                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4634         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4635                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4636         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4637                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4638 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4639
4640         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4641                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4642                 i40e_dev_handle_vfr_event(dev);
4643         }
4644         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4645                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4646                 i40e_dev_handle_aq_msg(dev);
4647         }
4648
4649         /* Link Status Change interrupt */
4650         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4651 #define I40E_US_PER_SECOND 1000000
4652                 struct rte_eth_link link;
4653
4654                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4655                 memset(&link, 0, sizeof(link));
4656                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4657                 i40e_dev_link_update(dev, 0);
4658
4659                 /*
4660                  * For link up interrupt, it needs to wait 1 second to let the
4661                  * hardware be a stable state. Otherwise several consecutive
4662                  * interrupts can be observed.
4663                  * For link down interrupt, no need to wait.
4664                  */
4665                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4666                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4667                         return;
4668                 else
4669                         _rte_eth_dev_callback_process(dev,
4670                                 RTE_ETH_EVENT_INTR_LSC);
4671         }
4672
4673 done:
4674         /* Enable interrupt */
4675         i40e_pf_enable_irq0(hw);
4676         rte_intr_enable(&(dev->pci_dev->intr_handle));
4677 }
4678
4679 static int
4680 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4681                          struct i40e_macvlan_filter *filter,
4682                          int total)
4683 {
4684         int ele_num, ele_buff_size;
4685         int num, actual_num, i;
4686         uint16_t flags;
4687         int ret = I40E_SUCCESS;
4688         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4689         struct i40e_aqc_add_macvlan_element_data *req_list;
4690
4691         if (filter == NULL  || total == 0)
4692                 return I40E_ERR_PARAM;
4693         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4694         ele_buff_size = hw->aq.asq_buf_size;
4695
4696         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4697         if (req_list == NULL) {
4698                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4699                 return I40E_ERR_NO_MEMORY;
4700         }
4701
4702         num = 0;
4703         do {
4704                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4705                 memset(req_list, 0, ele_buff_size);
4706
4707                 for (i = 0; i < actual_num; i++) {
4708                         (void)rte_memcpy(req_list[i].mac_addr,
4709                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4710                         req_list[i].vlan_tag =
4711                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4712
4713                         switch (filter[num + i].filter_type) {
4714                         case RTE_MAC_PERFECT_MATCH:
4715                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4716                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4717                                 break;
4718                         case RTE_MACVLAN_PERFECT_MATCH:
4719                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4720                                 break;
4721                         case RTE_MAC_HASH_MATCH:
4722                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4723                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4724                                 break;
4725                         case RTE_MACVLAN_HASH_MATCH:
4726                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4727                                 break;
4728                         default:
4729                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4730                                 ret = I40E_ERR_PARAM;
4731                                 goto DONE;
4732                         }
4733
4734                         req_list[i].queue_number = 0;
4735
4736                         req_list[i].flags = rte_cpu_to_le_16(flags);
4737                 }
4738
4739                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4740                                                 actual_num, NULL);
4741                 if (ret != I40E_SUCCESS) {
4742                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4743                         goto DONE;
4744                 }
4745                 num += actual_num;
4746         } while (num < total);
4747
4748 DONE:
4749         rte_free(req_list);
4750         return ret;
4751 }
4752
4753 static int
4754 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4755                             struct i40e_macvlan_filter *filter,
4756                             int total)
4757 {
4758         int ele_num, ele_buff_size;
4759         int num, actual_num, i;
4760         uint16_t flags;
4761         int ret = I40E_SUCCESS;
4762         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4763         struct i40e_aqc_remove_macvlan_element_data *req_list;
4764
4765         if (filter == NULL  || total == 0)
4766                 return I40E_ERR_PARAM;
4767
4768         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4769         ele_buff_size = hw->aq.asq_buf_size;
4770
4771         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4772         if (req_list == NULL) {
4773                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4774                 return I40E_ERR_NO_MEMORY;
4775         }
4776
4777         num = 0;
4778         do {
4779                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4780                 memset(req_list, 0, ele_buff_size);
4781
4782                 for (i = 0; i < actual_num; i++) {
4783                         (void)rte_memcpy(req_list[i].mac_addr,
4784                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4785                         req_list[i].vlan_tag =
4786                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4787
4788                         switch (filter[num + i].filter_type) {
4789                         case RTE_MAC_PERFECT_MATCH:
4790                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4791                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4792                                 break;
4793                         case RTE_MACVLAN_PERFECT_MATCH:
4794                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4795                                 break;
4796                         case RTE_MAC_HASH_MATCH:
4797                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4798                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4799                                 break;
4800                         case RTE_MACVLAN_HASH_MATCH:
4801                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4802                                 break;
4803                         default:
4804                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4805                                 ret = I40E_ERR_PARAM;
4806                                 goto DONE;
4807                         }
4808                         req_list[i].flags = rte_cpu_to_le_16(flags);
4809                 }
4810
4811                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4812                                                 actual_num, NULL);
4813                 if (ret != I40E_SUCCESS) {
4814                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4815                         goto DONE;
4816                 }
4817                 num += actual_num;
4818         } while (num < total);
4819
4820 DONE:
4821         rte_free(req_list);
4822         return ret;
4823 }
4824
4825 /* Find out specific MAC filter */
4826 static struct i40e_mac_filter *
4827 i40e_find_mac_filter(struct i40e_vsi *vsi,
4828                          struct ether_addr *macaddr)
4829 {
4830         struct i40e_mac_filter *f;
4831
4832         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4833                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4834                         return f;
4835         }
4836
4837         return NULL;
4838 }
4839
4840 static bool
4841 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4842                          uint16_t vlan_id)
4843 {
4844         uint32_t vid_idx, vid_bit;
4845
4846         if (vlan_id > ETH_VLAN_ID_MAX)
4847                 return 0;
4848
4849         vid_idx = I40E_VFTA_IDX(vlan_id);
4850         vid_bit = I40E_VFTA_BIT(vlan_id);
4851
4852         if (vsi->vfta[vid_idx] & vid_bit)
4853                 return 1;
4854         else
4855                 return 0;
4856 }
4857
4858 static void
4859 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4860                          uint16_t vlan_id, bool on)
4861 {
4862         uint32_t vid_idx, vid_bit;
4863
4864         if (vlan_id > ETH_VLAN_ID_MAX)
4865                 return;
4866
4867         vid_idx = I40E_VFTA_IDX(vlan_id);
4868         vid_bit = I40E_VFTA_BIT(vlan_id);
4869
4870         if (on)
4871                 vsi->vfta[vid_idx] |= vid_bit;
4872         else
4873                 vsi->vfta[vid_idx] &= ~vid_bit;
4874 }
4875
4876 /**
4877  * Find all vlan options for specific mac addr,
4878  * return with actual vlan found.
4879  */
4880 static inline int
4881 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4882                            struct i40e_macvlan_filter *mv_f,
4883                            int num, struct ether_addr *addr)
4884 {
4885         int i;
4886         uint32_t j, k;
4887
4888         /**
4889          * Not to use i40e_find_vlan_filter to decrease the loop time,
4890          * although the code looks complex.
4891           */
4892         if (num < vsi->vlan_num)
4893                 return I40E_ERR_PARAM;
4894
4895         i = 0;
4896         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4897                 if (vsi->vfta[j]) {
4898                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4899                                 if (vsi->vfta[j] & (1 << k)) {
4900                                         if (i > num - 1) {
4901                                                 PMD_DRV_LOG(ERR, "vlan number "
4902                                                             "not match");
4903                                                 return I40E_ERR_PARAM;
4904                                         }
4905                                         (void)rte_memcpy(&mv_f[i].macaddr,
4906                                                         addr, ETH_ADDR_LEN);
4907                                         mv_f[i].vlan_id =
4908                                                 j * I40E_UINT32_BIT_SIZE + k;
4909                                         i++;
4910                                 }
4911                         }
4912                 }
4913         }
4914         return I40E_SUCCESS;
4915 }
4916
4917 static inline int
4918 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4919                            struct i40e_macvlan_filter *mv_f,
4920                            int num,
4921                            uint16_t vlan)
4922 {
4923         int i = 0;
4924         struct i40e_mac_filter *f;
4925
4926         if (num < vsi->mac_num)
4927                 return I40E_ERR_PARAM;
4928
4929         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4930                 if (i > num - 1) {
4931                         PMD_DRV_LOG(ERR, "buffer number not match");
4932                         return I40E_ERR_PARAM;
4933                 }
4934                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4935                                 ETH_ADDR_LEN);
4936                 mv_f[i].vlan_id = vlan;
4937                 mv_f[i].filter_type = f->mac_info.filter_type;
4938                 i++;
4939         }
4940
4941         return I40E_SUCCESS;
4942 }
4943
4944 static int
4945 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4946 {
4947         int i, num;
4948         struct i40e_mac_filter *f;
4949         struct i40e_macvlan_filter *mv_f;
4950         int ret = I40E_SUCCESS;
4951
4952         if (vsi == NULL || vsi->mac_num == 0)
4953                 return I40E_ERR_PARAM;
4954
4955         /* Case that no vlan is set */
4956         if (vsi->vlan_num == 0)
4957                 num = vsi->mac_num;
4958         else
4959                 num = vsi->mac_num * vsi->vlan_num;
4960
4961         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4962         if (mv_f == NULL) {
4963                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4964                 return I40E_ERR_NO_MEMORY;
4965         }
4966
4967         i = 0;
4968         if (vsi->vlan_num == 0) {
4969                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4970                         (void)rte_memcpy(&mv_f[i].macaddr,
4971                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4972                         mv_f[i].vlan_id = 0;
4973                         i++;
4974                 }
4975         } else {
4976                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4977                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4978                                         vsi->vlan_num, &f->mac_info.mac_addr);
4979                         if (ret != I40E_SUCCESS)
4980                                 goto DONE;
4981                         i += vsi->vlan_num;
4982                 }
4983         }
4984
4985         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4986 DONE:
4987         rte_free(mv_f);
4988
4989         return ret;
4990 }
4991
4992 int
4993 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4994 {
4995         struct i40e_macvlan_filter *mv_f;
4996         int mac_num;
4997         int ret = I40E_SUCCESS;
4998
4999         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5000                 return I40E_ERR_PARAM;
5001
5002         /* If it's already set, just return */
5003         if (i40e_find_vlan_filter(vsi,vlan))
5004                 return I40E_SUCCESS;
5005
5006         mac_num = vsi->mac_num;
5007
5008         if (mac_num == 0) {
5009                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5010                 return I40E_ERR_PARAM;
5011         }
5012
5013         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5014
5015         if (mv_f == NULL) {
5016                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5017                 return I40E_ERR_NO_MEMORY;
5018         }
5019
5020         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5021
5022         if (ret != I40E_SUCCESS)
5023                 goto DONE;
5024
5025         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5026
5027         if (ret != I40E_SUCCESS)
5028                 goto DONE;
5029
5030         i40e_set_vlan_filter(vsi, vlan, 1);
5031
5032         vsi->vlan_num++;
5033         ret = I40E_SUCCESS;
5034 DONE:
5035         rte_free(mv_f);
5036         return ret;
5037 }
5038
5039 int
5040 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5041 {
5042         struct i40e_macvlan_filter *mv_f;
5043         int mac_num;
5044         int ret = I40E_SUCCESS;
5045
5046         /**
5047          * Vlan 0 is the generic filter for untagged packets
5048          * and can't be removed.
5049          */
5050         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5051                 return I40E_ERR_PARAM;
5052
5053         /* If can't find it, just return */
5054         if (!i40e_find_vlan_filter(vsi, vlan))
5055                 return I40E_ERR_PARAM;
5056
5057         mac_num = vsi->mac_num;
5058
5059         if (mac_num == 0) {
5060                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5061                 return I40E_ERR_PARAM;
5062         }
5063
5064         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5065
5066         if (mv_f == NULL) {
5067                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5068                 return I40E_ERR_NO_MEMORY;
5069         }
5070
5071         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5072
5073         if (ret != I40E_SUCCESS)
5074                 goto DONE;
5075
5076         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5077
5078         if (ret != I40E_SUCCESS)
5079                 goto DONE;
5080
5081         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5082         if (vsi->vlan_num == 1) {
5083                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5084                 if (ret != I40E_SUCCESS)
5085                         goto DONE;
5086
5087                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5088                 if (ret != I40E_SUCCESS)
5089                         goto DONE;
5090         }
5091
5092         i40e_set_vlan_filter(vsi, vlan, 0);
5093
5094         vsi->vlan_num--;
5095         ret = I40E_SUCCESS;
5096 DONE:
5097         rte_free(mv_f);
5098         return ret;
5099 }
5100
5101 int
5102 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5103 {
5104         struct i40e_mac_filter *f;
5105         struct i40e_macvlan_filter *mv_f;
5106         int i, vlan_num = 0;
5107         int ret = I40E_SUCCESS;
5108
5109         /* If it's add and we've config it, return */
5110         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5111         if (f != NULL)
5112                 return I40E_SUCCESS;
5113         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5114                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5115
5116                 /**
5117                  * If vlan_num is 0, that's the first time to add mac,
5118                  * set mask for vlan_id 0.
5119                  */
5120                 if (vsi->vlan_num == 0) {
5121                         i40e_set_vlan_filter(vsi, 0, 1);
5122                         vsi->vlan_num = 1;
5123                 }
5124                 vlan_num = vsi->vlan_num;
5125         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5126                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5127                 vlan_num = 1;
5128
5129         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5130         if (mv_f == NULL) {
5131                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5132                 return I40E_ERR_NO_MEMORY;
5133         }
5134
5135         for (i = 0; i < vlan_num; i++) {
5136                 mv_f[i].filter_type = mac_filter->filter_type;
5137                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5138                                 ETH_ADDR_LEN);
5139         }
5140
5141         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5142                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5143                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5144                                         &mac_filter->mac_addr);
5145                 if (ret != I40E_SUCCESS)
5146                         goto DONE;
5147         }
5148
5149         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5150         if (ret != I40E_SUCCESS)
5151                 goto DONE;
5152
5153         /* Add the mac addr into mac list */
5154         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5155         if (f == NULL) {
5156                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5157                 ret = I40E_ERR_NO_MEMORY;
5158                 goto DONE;
5159         }
5160         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5161                         ETH_ADDR_LEN);
5162         f->mac_info.filter_type = mac_filter->filter_type;
5163         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5164         vsi->mac_num++;
5165
5166         ret = I40E_SUCCESS;
5167 DONE:
5168         rte_free(mv_f);
5169
5170         return ret;
5171 }
5172
5173 int
5174 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5175 {
5176         struct i40e_mac_filter *f;
5177         struct i40e_macvlan_filter *mv_f;
5178         int i, vlan_num;
5179         enum rte_mac_filter_type filter_type;
5180         int ret = I40E_SUCCESS;
5181
5182         /* Can't find it, return an error */
5183         f = i40e_find_mac_filter(vsi, addr);
5184         if (f == NULL)
5185                 return I40E_ERR_PARAM;
5186
5187         vlan_num = vsi->vlan_num;
5188         filter_type = f->mac_info.filter_type;
5189         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5190                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5191                 if (vlan_num == 0) {
5192                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5193                         return I40E_ERR_PARAM;
5194                 }
5195         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5196                         filter_type == RTE_MAC_HASH_MATCH)
5197                 vlan_num = 1;
5198
5199         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5200         if (mv_f == NULL) {
5201                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5202                 return I40E_ERR_NO_MEMORY;
5203         }
5204
5205         for (i = 0; i < vlan_num; i++) {
5206                 mv_f[i].filter_type = filter_type;
5207                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5208                                 ETH_ADDR_LEN);
5209         }
5210         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5211                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5212                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5213                 if (ret != I40E_SUCCESS)
5214                         goto DONE;
5215         }
5216
5217         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5218         if (ret != I40E_SUCCESS)
5219                 goto DONE;
5220
5221         /* Remove the mac addr into mac list */
5222         TAILQ_REMOVE(&vsi->mac_list, f, next);
5223         rte_free(f);
5224         vsi->mac_num--;
5225
5226         ret = I40E_SUCCESS;
5227 DONE:
5228         rte_free(mv_f);
5229         return ret;
5230 }
5231
5232 /* Configure hash enable flags for RSS */
5233 uint64_t
5234 i40e_config_hena(uint64_t flags)
5235 {
5236         uint64_t hena = 0;
5237
5238         if (!flags)
5239                 return hena;
5240
5241         if (flags & ETH_RSS_FRAG_IPV4)
5242                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5243         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5244                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5245         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5246                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5247         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5248                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5249         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5250                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5251         if (flags & ETH_RSS_FRAG_IPV6)
5252                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5253         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5254                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5255         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5256                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5257         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5258                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5259         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5260                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5261         if (flags & ETH_RSS_L2_PAYLOAD)
5262                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5263
5264         return hena;
5265 }
5266
5267 /* Parse the hash enable flags */
5268 uint64_t
5269 i40e_parse_hena(uint64_t flags)
5270 {
5271         uint64_t rss_hf = 0;
5272
5273         if (!flags)
5274                 return rss_hf;
5275         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5276                 rss_hf |= ETH_RSS_FRAG_IPV4;
5277         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5278                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5279         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5280                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5281         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5282                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5283         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5284                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5285         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5286                 rss_hf |= ETH_RSS_FRAG_IPV6;
5287         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5288                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5289         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5290                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5291         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5292                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5293         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5294                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5295         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5296                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5297
5298         return rss_hf;
5299 }
5300
5301 /* Disable RSS */
5302 static void
5303 i40e_pf_disable_rss(struct i40e_pf *pf)
5304 {
5305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5306         uint64_t hena;
5307
5308         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5309         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5310         hena &= ~I40E_RSS_HENA_ALL;
5311         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5312         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5313         I40E_WRITE_FLUSH(hw);
5314 }
5315
5316 static int
5317 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5318 {
5319         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5321         int ret = 0;
5322
5323         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5324                 sizeof(uint32_t)))
5325                 return -EINVAL;
5326
5327         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5328                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5329                         (struct i40e_aqc_get_set_rss_key_data *)key;
5330
5331                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5332                 if (ret)
5333                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5334                                      "via AQ");
5335         } else {
5336                 uint32_t *hash_key = (uint32_t *)key;
5337                 uint16_t i;
5338
5339                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5340                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5341                 I40E_WRITE_FLUSH(hw);
5342         }
5343
5344         return ret;
5345 }
5346
5347 static int
5348 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5349 {
5350         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5351         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5352         int ret;
5353
5354         if (!key || !key_len)
5355                 return -EINVAL;
5356
5357         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5358                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5359                         (struct i40e_aqc_get_set_rss_key_data *)key);
5360                 if (ret) {
5361                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5362                         return ret;
5363                 }
5364         } else {
5365                 uint32_t *key_dw = (uint32_t *)key;
5366                 uint16_t i;
5367
5368                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5369                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5370         }
5371         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5372
5373         return 0;
5374 }
5375
5376 static int
5377 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5378 {
5379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5380         uint64_t rss_hf;
5381         uint64_t hena;
5382         int ret;
5383
5384         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5385                                rss_conf->rss_key_len);
5386         if (ret)
5387                 return ret;
5388
5389         rss_hf = rss_conf->rss_hf;
5390         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5391         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5392         hena &= ~I40E_RSS_HENA_ALL;
5393         hena |= i40e_config_hena(rss_hf);
5394         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5395         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5396         I40E_WRITE_FLUSH(hw);
5397
5398         return 0;
5399 }
5400
5401 static int
5402 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5403                          struct rte_eth_rss_conf *rss_conf)
5404 {
5405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5407         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5408         uint64_t hena;
5409
5410         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5411         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5412         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5413                 if (rss_hf != 0) /* Enable RSS */
5414                         return -EINVAL;
5415                 return 0; /* Nothing to do */
5416         }
5417         /* RSS enabled */
5418         if (rss_hf == 0) /* Disable RSS */
5419                 return -EINVAL;
5420
5421         return i40e_hw_rss_hash_set(pf, rss_conf);
5422 }
5423
5424 static int
5425 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5426                            struct rte_eth_rss_conf *rss_conf)
5427 {
5428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         uint64_t hena;
5431
5432         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5433                          &rss_conf->rss_key_len);
5434
5435         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5436         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5437         rss_conf->rss_hf = i40e_parse_hena(hena);
5438
5439         return 0;
5440 }
5441
5442 static int
5443 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5444 {
5445         switch (filter_type) {
5446         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5447                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5448                 break;
5449         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5450                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5451                 break;
5452         case RTE_TUNNEL_FILTER_IMAC_TENID:
5453                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5454                 break;
5455         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5456                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5457                 break;
5458         case ETH_TUNNEL_FILTER_IMAC:
5459                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5460                 break;
5461         default:
5462                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5463                 return -EINVAL;
5464         }
5465
5466         return 0;
5467 }
5468
5469 static int
5470 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5471                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5472                         uint8_t add)
5473 {
5474         uint16_t ip_type;
5475         uint8_t tun_type = 0;
5476         int val, ret = 0;
5477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5478         struct i40e_vsi *vsi = pf->main_vsi;
5479         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5480         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5481
5482         cld_filter = rte_zmalloc("tunnel_filter",
5483                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5484                 0);
5485
5486         if (NULL == cld_filter) {
5487                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5488                 return -EINVAL;
5489         }
5490         pfilter = cld_filter;
5491
5492         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5493                         sizeof(struct ether_addr));
5494         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5495                         sizeof(struct ether_addr));
5496
5497         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5498         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5499                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5500                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5501                                 &tunnel_filter->ip_addr,
5502                                 sizeof(pfilter->ipaddr.v4.data));
5503         } else {
5504                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5505                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5506                                 &tunnel_filter->ip_addr,
5507                                 sizeof(pfilter->ipaddr.v6.data));
5508         }
5509
5510         /* check tunneled type */
5511         switch (tunnel_filter->tunnel_type) {
5512         case RTE_TUNNEL_TYPE_VXLAN:
5513                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5514                 break;
5515         case RTE_TUNNEL_TYPE_NVGRE:
5516                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5517                 break;
5518         default:
5519                 /* Other tunnel types is not supported. */
5520                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5521                 rte_free(cld_filter);
5522                 return -EINVAL;
5523         }
5524
5525         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5526                                                 &pfilter->flags);
5527         if (val < 0) {
5528                 rte_free(cld_filter);
5529                 return -EINVAL;
5530         }
5531
5532         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5533                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5534         pfilter->tenant_id = tunnel_filter->tenant_id;
5535         pfilter->queue_number = tunnel_filter->queue_id;
5536
5537         if (add)
5538                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5539         else
5540                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5541                                                 cld_filter, 1);
5542
5543         rte_free(cld_filter);
5544         return ret;
5545 }
5546
5547 static int
5548 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5549 {
5550         uint8_t i;
5551
5552         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5553                 if (pf->vxlan_ports[i] == port)
5554                         return i;
5555         }
5556
5557         return -1;
5558 }
5559
5560 static int
5561 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5562 {
5563         int  idx, ret;
5564         uint8_t filter_idx;
5565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5566
5567         idx = i40e_get_vxlan_port_idx(pf, port);
5568
5569         /* Check if port already exists */
5570         if (idx >= 0) {
5571                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5572                 return -EINVAL;
5573         }
5574
5575         /* Now check if there is space to add the new port */
5576         idx = i40e_get_vxlan_port_idx(pf, 0);
5577         if (idx < 0) {
5578                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5579                         "not adding port %d", port);
5580                 return -ENOSPC;
5581         }
5582
5583         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5584                                         &filter_idx, NULL);
5585         if (ret < 0) {
5586                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5587                 return -1;
5588         }
5589
5590         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5591                          port,  filter_idx);
5592
5593         /* New port: add it and mark its index in the bitmap */
5594         pf->vxlan_ports[idx] = port;
5595         pf->vxlan_bitmap |= (1 << idx);
5596
5597         if (!(pf->flags & I40E_FLAG_VXLAN))
5598                 pf->flags |= I40E_FLAG_VXLAN;
5599
5600         return 0;
5601 }
5602
5603 static int
5604 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5605 {
5606         int idx;
5607         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5608
5609         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5610                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5611                 return -EINVAL;
5612         }
5613
5614         idx = i40e_get_vxlan_port_idx(pf, port);
5615
5616         if (idx < 0) {
5617                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5618                 return -EINVAL;
5619         }
5620
5621         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5622                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5623                 return -1;
5624         }
5625
5626         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5627                         port, idx);
5628
5629         pf->vxlan_ports[idx] = 0;
5630         pf->vxlan_bitmap &= ~(1 << idx);
5631
5632         if (!pf->vxlan_bitmap)
5633                 pf->flags &= ~I40E_FLAG_VXLAN;
5634
5635         return 0;
5636 }
5637
5638 /* Add UDP tunneling port */
5639 static int
5640 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5641                         struct rte_eth_udp_tunnel *udp_tunnel)
5642 {
5643         int ret = 0;
5644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5645
5646         if (udp_tunnel == NULL)
5647                 return -EINVAL;
5648
5649         switch (udp_tunnel->prot_type) {
5650         case RTE_TUNNEL_TYPE_VXLAN:
5651                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5652                 break;
5653
5654         case RTE_TUNNEL_TYPE_GENEVE:
5655         case RTE_TUNNEL_TYPE_TEREDO:
5656                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5657                 ret = -1;
5658                 break;
5659
5660         default:
5661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5662                 ret = -1;
5663                 break;
5664         }
5665
5666         return ret;
5667 }
5668
5669 /* Remove UDP tunneling port */
5670 static int
5671 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5672                         struct rte_eth_udp_tunnel *udp_tunnel)
5673 {
5674         int ret = 0;
5675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5676
5677         if (udp_tunnel == NULL)
5678                 return -EINVAL;
5679
5680         switch (udp_tunnel->prot_type) {
5681         case RTE_TUNNEL_TYPE_VXLAN:
5682                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5683                 break;
5684         case RTE_TUNNEL_TYPE_GENEVE:
5685         case RTE_TUNNEL_TYPE_TEREDO:
5686                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5687                 ret = -1;
5688                 break;
5689         default:
5690                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5691                 ret = -1;
5692                 break;
5693         }
5694
5695         return ret;
5696 }
5697
5698 /* Calculate the maximum number of contiguous PF queues that are configured */
5699 static int
5700 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5701 {
5702         struct rte_eth_dev_data *data = pf->dev_data;
5703         int i, num;
5704         struct i40e_rx_queue *rxq;
5705
5706         num = 0;
5707         for (i = 0; i < pf->lan_nb_qps; i++) {
5708                 rxq = data->rx_queues[i];
5709                 if (rxq && rxq->q_set)
5710                         num++;
5711                 else
5712                         break;
5713         }
5714
5715         return num;
5716 }
5717
5718 /* Configure RSS */
5719 static int
5720 i40e_pf_config_rss(struct i40e_pf *pf)
5721 {
5722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5723         struct rte_eth_rss_conf rss_conf;
5724         uint32_t i, lut = 0;
5725         uint16_t j, num;
5726
5727         /*
5728          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5729          * It's necessary to calulate the actual PF queues that are configured.
5730          */
5731         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
5732                 num = i40e_pf_calc_configured_queues_num(pf);
5733         else
5734                 num = pf->dev_data->nb_rx_queues;
5735
5736         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
5737         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5738                         num);
5739
5740         if (num == 0) {
5741                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5742                 return -ENOTSUP;
5743         }
5744
5745         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5746                 if (j == num)
5747                         j = 0;
5748                 lut = (lut << 8) | (j & ((0x1 <<
5749                         hw->func_caps.rss_table_entry_width) - 1));
5750                 if ((i & 3) == 3)
5751                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5752         }
5753
5754         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5755         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5756                 i40e_pf_disable_rss(pf);
5757                 return 0;
5758         }
5759         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5760                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5761                 /* Random default keys */
5762                 static uint32_t rss_key_default[] = {0x6b793944,
5763                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5764                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5765                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5766
5767                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5768                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5769                                                         sizeof(uint32_t);
5770         }
5771
5772         return i40e_hw_rss_hash_set(pf, &rss_conf);
5773 }
5774
5775 static int
5776 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5777                         struct rte_eth_tunnel_filter_conf *filter)
5778 {
5779         if (pf == NULL || filter == NULL) {
5780                 PMD_DRV_LOG(ERR, "Invalid parameter");
5781                 return -EINVAL;
5782         }
5783
5784         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5785                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5786                 return -EINVAL;
5787         }
5788
5789         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5790                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5791                 return -EINVAL;
5792         }
5793
5794         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5795                 (is_zero_ether_addr(filter->outer_mac))) {
5796                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5797                 return -EINVAL;
5798         }
5799
5800         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5801                 (is_zero_ether_addr(filter->inner_mac))) {
5802                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5803                 return -EINVAL;
5804         }
5805
5806         return 0;
5807 }
5808
5809 static int
5810 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5811                         void *arg)
5812 {
5813         struct rte_eth_tunnel_filter_conf *filter;
5814         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5815         int ret = I40E_SUCCESS;
5816
5817         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5818
5819         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5820                 return I40E_ERR_PARAM;
5821
5822         switch (filter_op) {
5823         case RTE_ETH_FILTER_NOP:
5824                 if (!(pf->flags & I40E_FLAG_VXLAN))
5825                         ret = I40E_NOT_SUPPORTED;
5826         case RTE_ETH_FILTER_ADD:
5827                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5828                 break;
5829         case RTE_ETH_FILTER_DELETE:
5830                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5831                 break;
5832         default:
5833                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5834                 ret = I40E_ERR_PARAM;
5835                 break;
5836         }
5837
5838         return ret;
5839 }
5840
5841 static int
5842 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5843 {
5844         int ret = 0;
5845         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5846
5847         /* RSS setup */
5848         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5849                 ret = i40e_pf_config_rss(pf);
5850         else
5851                 i40e_pf_disable_rss(pf);
5852
5853         return ret;
5854 }
5855
5856 /* Get the symmetric hash enable configurations per port */
5857 static void
5858 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5859 {
5860         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5861
5862         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5863 }
5864
5865 /* Set the symmetric hash enable configurations per port */
5866 static void
5867 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5868 {
5869         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5870
5871         if (enable > 0) {
5872                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5873                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5874                                                         "been enabled");
5875                         return;
5876                 }
5877                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5878         } else {
5879                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5880                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5881                                                         "been disabled");
5882                         return;
5883                 }
5884                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5885         }
5886         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5887         I40E_WRITE_FLUSH(hw);
5888 }
5889
5890 /*
5891  * Get global configurations of hash function type and symmetric hash enable
5892  * per flow type (pctype). Note that global configuration means it affects all
5893  * the ports on the same NIC.
5894  */
5895 static int
5896 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5897                                    struct rte_eth_hash_global_conf *g_cfg)
5898 {
5899         uint32_t reg, mask = I40E_FLOW_TYPES;
5900         uint16_t i;
5901         enum i40e_filter_pctype pctype;
5902
5903         memset(g_cfg, 0, sizeof(*g_cfg));
5904         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5905         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5906                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5907         else
5908                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5909         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5910                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5911
5912         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5913                 if (!(mask & (1UL << i)))
5914                         continue;
5915                 mask &= ~(1UL << i);
5916                 /* Bit set indicats the coresponding flow type is supported */
5917                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5918                 pctype = i40e_flowtype_to_pctype(i);
5919                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5920                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5921                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5922         }
5923
5924         return 0;
5925 }
5926
5927 static int
5928 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5929 {
5930         uint32_t i;
5931         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5932
5933         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5934                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5935                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5936                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5937                                                 g_cfg->hash_func);
5938                 return -EINVAL;
5939         }
5940
5941         /*
5942          * As i40e supports less than 32 flow types, only first 32 bits need to
5943          * be checked.
5944          */
5945         mask0 = g_cfg->valid_bit_mask[0];
5946         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5947                 if (i == 0) {
5948                         /* Check if any unsupported flow type configured */
5949                         if ((mask0 | i40e_mask) ^ i40e_mask)
5950                                 goto mask_err;
5951                 } else {
5952                         if (g_cfg->valid_bit_mask[i])
5953                                 goto mask_err;
5954                 }
5955         }
5956
5957         return 0;
5958
5959 mask_err:
5960         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5961
5962         return -EINVAL;
5963 }
5964
5965 /*
5966  * Set global configurations of hash function type and symmetric hash enable
5967  * per flow type (pctype). Note any modifying global configuration will affect
5968  * all the ports on the same NIC.
5969  */
5970 static int
5971 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5972                                    struct rte_eth_hash_global_conf *g_cfg)
5973 {
5974         int ret;
5975         uint16_t i;
5976         uint32_t reg;
5977         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5978         enum i40e_filter_pctype pctype;
5979
5980         /* Check the input parameters */
5981         ret = i40e_hash_global_config_check(g_cfg);
5982         if (ret < 0)
5983                 return ret;
5984
5985         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5986                 if (!(mask0 & (1UL << i)))
5987                         continue;
5988                 mask0 &= ~(1UL << i);
5989                 pctype = i40e_flowtype_to_pctype(i);
5990                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5991                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5992                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5993         }
5994
5995         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5996         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5997                 /* Toeplitz */
5998                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5999                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6000                                                                 "Toeplitz");
6001                         goto out;
6002                 }
6003                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6004         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6005                 /* Simple XOR */
6006                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6007                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6008                                                         "Simple XOR");
6009                         goto out;
6010                 }
6011                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6012         } else
6013                 /* Use the default, and keep it as it is */
6014                 goto out;
6015
6016         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6017
6018 out:
6019         I40E_WRITE_FLUSH(hw);
6020
6021         return 0;
6022 }
6023
6024 static int
6025 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6026 {
6027         int ret = 0;
6028
6029         if (!hw || !info) {
6030                 PMD_DRV_LOG(ERR, "Invalid pointer");
6031                 return -EFAULT;
6032         }
6033
6034         switch (info->info_type) {
6035         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6036                 i40e_get_symmetric_hash_enable_per_port(hw,
6037                                         &(info->info.enable));
6038                 break;
6039         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6040                 ret = i40e_get_hash_filter_global_config(hw,
6041                                 &(info->info.global_conf));
6042                 break;
6043         default:
6044                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6045                                                         info->info_type);
6046                 ret = -EINVAL;
6047                 break;
6048         }
6049
6050         return ret;
6051 }
6052
6053 static int
6054 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6055 {
6056         int ret = 0;
6057
6058         if (!hw || !info) {
6059                 PMD_DRV_LOG(ERR, "Invalid pointer");
6060                 return -EFAULT;
6061         }
6062
6063         switch (info->info_type) {
6064         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6065                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
6066                 break;
6067         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6068                 ret = i40e_set_hash_filter_global_config(hw,
6069                                 &(info->info.global_conf));
6070                 break;
6071         default:
6072                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6073                                                         info->info_type);
6074                 ret = -EINVAL;
6075                 break;
6076         }
6077
6078         return ret;
6079 }
6080
6081 /* Operations for hash function */
6082 static int
6083 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
6084                       enum rte_filter_op filter_op,
6085                       void *arg)
6086 {
6087         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088         int ret = 0;
6089
6090         switch (filter_op) {
6091         case RTE_ETH_FILTER_NOP:
6092                 break;
6093         case RTE_ETH_FILTER_GET:
6094                 ret = i40e_hash_filter_get(hw,
6095                         (struct rte_eth_hash_filter_info *)arg);
6096                 break;
6097         case RTE_ETH_FILTER_SET:
6098                 ret = i40e_hash_filter_set(hw,
6099                         (struct rte_eth_hash_filter_info *)arg);
6100                 break;
6101         default:
6102                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
6103                                                                 filter_op);
6104                 ret = -ENOTSUP;
6105                 break;
6106         }
6107
6108         return ret;
6109 }
6110
6111 /*
6112  * Configure ethertype filter, which can director packet by filtering
6113  * with mac address and ether_type or only ether_type
6114  */
6115 static int
6116 i40e_ethertype_filter_set(struct i40e_pf *pf,
6117                         struct rte_eth_ethertype_filter *filter,
6118                         bool add)
6119 {
6120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6121         struct i40e_control_filter_stats stats;
6122         uint16_t flags = 0;
6123         int ret;
6124
6125         if (filter->queue >= pf->dev_data->nb_rx_queues) {
6126                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6127                 return -EINVAL;
6128         }
6129         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6130                 filter->ether_type == ETHER_TYPE_IPv6) {
6131                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6132                         " control packet filter.", filter->ether_type);
6133                 return -EINVAL;
6134         }
6135         if (filter->ether_type == ETHER_TYPE_VLAN)
6136                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6137                         " not supported.");
6138
6139         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6140                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6141         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6142                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6143         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6144
6145         memset(&stats, 0, sizeof(stats));
6146         ret = i40e_aq_add_rem_control_packet_filter(hw,
6147                         filter->mac_addr.addr_bytes,
6148                         filter->ether_type, flags,
6149                         pf->main_vsi->seid,
6150                         filter->queue, add, &stats, NULL);
6151
6152         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6153                          " mac_etype_used = %u, etype_used = %u,"
6154                          " mac_etype_free = %u, etype_free = %u\n",
6155                          ret, stats.mac_etype_used, stats.etype_used,
6156                          stats.mac_etype_free, stats.etype_free);
6157         if (ret < 0)
6158                 return -ENOSYS;
6159         return 0;
6160 }
6161
6162 /*
6163  * Handle operations for ethertype filter.
6164  */
6165 static int
6166 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6167                                 enum rte_filter_op filter_op,
6168                                 void *arg)
6169 {
6170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6171         int ret = 0;
6172
6173         if (filter_op == RTE_ETH_FILTER_NOP)
6174                 return ret;
6175
6176         if (arg == NULL) {
6177                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6178                             filter_op);
6179                 return -EINVAL;
6180         }
6181
6182         switch (filter_op) {
6183         case RTE_ETH_FILTER_ADD:
6184                 ret = i40e_ethertype_filter_set(pf,
6185                         (struct rte_eth_ethertype_filter *)arg,
6186                         TRUE);
6187                 break;
6188         case RTE_ETH_FILTER_DELETE:
6189                 ret = i40e_ethertype_filter_set(pf,
6190                         (struct rte_eth_ethertype_filter *)arg,
6191                         FALSE);
6192                 break;
6193         default:
6194                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6195                 ret = -ENOSYS;
6196                 break;
6197         }
6198         return ret;
6199 }
6200
6201 static int
6202 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
6203                      enum rte_filter_type filter_type,
6204                      enum rte_filter_op filter_op,
6205                      void *arg)
6206 {
6207         int ret = 0;
6208
6209         if (dev == NULL)
6210                 return -EINVAL;
6211
6212         switch (filter_type) {
6213         case RTE_ETH_FILTER_HASH:
6214                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
6215                 break;
6216         case RTE_ETH_FILTER_MACVLAN:
6217                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
6218                 break;
6219         case RTE_ETH_FILTER_ETHERTYPE:
6220                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
6221                 break;
6222         case RTE_ETH_FILTER_TUNNEL:
6223                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
6224                 break;
6225         case RTE_ETH_FILTER_FDIR:
6226                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
6227                 break;
6228         default:
6229                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6230                                                         filter_type);
6231                 ret = -EINVAL;
6232                 break;
6233         }
6234
6235         return ret;
6236 }
6237
6238 /*
6239  * As some registers wouldn't be reset unless a global hardware reset,
6240  * hardware initialization is needed to put those registers into an
6241  * expected initial state.
6242  */
6243 static void
6244 i40e_hw_init(struct i40e_hw *hw)
6245 {
6246         /* clear the PF Queue Filter control register */
6247         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
6248
6249         /* Disable symmetric hash per port */
6250         i40e_set_symmetric_hash_enable_per_port(hw, 0);
6251 }
6252
6253 enum i40e_filter_pctype
6254 i40e_flowtype_to_pctype(uint16_t flow_type)
6255 {
6256         static const enum i40e_filter_pctype pctype_table[] = {
6257                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
6258                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
6259                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
6260                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
6261                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
6262                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
6263                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
6264                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
6265                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
6266                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
6267                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
6268                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
6269                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
6270                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
6271                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
6272                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
6273                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
6274                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
6275                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
6276         };
6277
6278         return pctype_table[flow_type];
6279 }
6280
6281 uint16_t
6282 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
6283 {
6284         static const uint16_t flowtype_table[] = {
6285                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
6286                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6287                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
6288                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6289                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
6290                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6291                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
6292                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6293                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
6294                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
6295                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6296                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
6297                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6298                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
6299                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6300                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
6301                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6302                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
6303                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
6304         };
6305
6306         return flowtype_table[pctype];
6307 }
6308
6309 /*
6310  * On X710, performance number is far from the expectation on recent firmware
6311  * versions; on XL710, performance number is also far from the expectation on
6312  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
6313  * mode is enabled and port MAC address is equal to the packet destination MAC
6314  * address. The fix for this issue may not be integrated in the following
6315  * firmware version. So the workaround in software driver is needed. It needs
6316  * to modify the initial values of 3 internal only registers for both X710 and
6317  * XL710. Note that the values for X710 or XL710 could be different, and the
6318  * workaround can be removed when it is fixed in firmware in the future.
6319  */
6320
6321 /* For both X710 and XL710 */
6322 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
6323 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
6324
6325 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
6326 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
6327
6328 /* For X710 */
6329 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
6330 /* For XL710 */
6331 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
6332 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
6333
6334 static void
6335 i40e_configure_registers(struct i40e_hw *hw)
6336 {
6337         static struct {
6338                 uint32_t addr;
6339                 uint64_t val;
6340         } reg_table[] = {
6341                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6342                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6343                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6344         };
6345         uint64_t reg;
6346         uint32_t i;
6347         int ret;
6348
6349         for (i = 0; i < RTE_DIM(reg_table); i++) {
6350                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6351                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6352                                 reg_table[i].val =
6353                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6354                         else /* For X710 */
6355                                 reg_table[i].val =
6356                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6357                 }
6358
6359                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6360                                                         &reg, NULL);
6361                 if (ret < 0) {
6362                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6363                                                         reg_table[i].addr);
6364                         break;
6365                 }
6366                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6367                                                 reg_table[i].addr, reg);
6368                 if (reg == reg_table[i].val)
6369                         continue;
6370
6371                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6372                                                 reg_table[i].val, NULL);
6373                 if (ret < 0) {
6374                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6375                                 "address of 0x%"PRIx32, reg_table[i].val,
6376                                                         reg_table[i].addr);
6377                         break;
6378                 }
6379                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6380                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6381         }
6382 }
6383
6384 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6385 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6386 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6387 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6388 static int
6389 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6390 {
6391         uint32_t reg;
6392         int ret;
6393
6394         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6395                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6396                 return -EINVAL;
6397         }
6398
6399         /* Configure for double VLAN RX stripping */
6400         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6401         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6402                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6403                 ret = i40e_aq_debug_write_register(hw,
6404                                                    I40E_VSI_TSR(vsi->vsi_id),
6405                                                    reg, NULL);
6406                 if (ret < 0) {
6407                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6408                                     vsi->vsi_id);
6409                         return I40E_ERR_CONFIG;
6410                 }
6411         }
6412
6413         /* Configure for double VLAN TX insertion */
6414         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6415         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6416                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6417                 ret = i40e_aq_debug_write_register(hw,
6418                                                    I40E_VSI_L2TAGSTXVALID(
6419                                                    vsi->vsi_id), reg, NULL);
6420                 if (ret < 0) {
6421                         PMD_DRV_LOG(ERR, "Failed to update "
6422                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6423                         return I40E_ERR_CONFIG;
6424                 }
6425         }
6426
6427         return 0;
6428 }
6429
6430 /**
6431  * i40e_aq_add_mirror_rule
6432  * @hw: pointer to the hardware structure
6433  * @seid: VEB seid to add mirror rule to
6434  * @dst_id: destination vsi seid
6435  * @entries: Buffer which contains the entities to be mirrored
6436  * @count: number of entities contained in the buffer
6437  * @rule_id:the rule_id of the rule to be added
6438  *
6439  * Add a mirror rule for a given veb.
6440  *
6441  **/
6442 static enum i40e_status_code
6443 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6444                         uint16_t seid, uint16_t dst_id,
6445                         uint16_t rule_type, uint16_t *entries,
6446                         uint16_t count, uint16_t *rule_id)
6447 {
6448         struct i40e_aq_desc desc;
6449         struct i40e_aqc_add_delete_mirror_rule cmd;
6450         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6451                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6452                 &desc.params.raw;
6453         uint16_t buff_len;
6454         enum i40e_status_code status;
6455
6456         i40e_fill_default_direct_cmd_desc(&desc,
6457                                           i40e_aqc_opc_add_mirror_rule);
6458         memset(&cmd, 0, sizeof(cmd));
6459
6460         buff_len = sizeof(uint16_t) * count;
6461         desc.datalen = rte_cpu_to_le_16(buff_len);
6462         if (buff_len > 0)
6463                 desc.flags |= rte_cpu_to_le_16(
6464                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6465         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6466                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6467         cmd.num_entries = rte_cpu_to_le_16(count);
6468         cmd.seid = rte_cpu_to_le_16(seid);
6469         cmd.destination = rte_cpu_to_le_16(dst_id);
6470
6471         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6472         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6473         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6474                          "rule_id = %u"
6475                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6476                          hw->aq.asq_last_status, resp->rule_id,
6477                          resp->mirror_rules_used, resp->mirror_rules_free);
6478         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6479
6480         return status;
6481 }
6482
6483 /**
6484  * i40e_aq_del_mirror_rule
6485  * @hw: pointer to the hardware structure
6486  * @seid: VEB seid to add mirror rule to
6487  * @entries: Buffer which contains the entities to be mirrored
6488  * @count: number of entities contained in the buffer
6489  * @rule_id:the rule_id of the rule to be delete
6490  *
6491  * Delete a mirror rule for a given veb.
6492  *
6493  **/
6494 static enum i40e_status_code
6495 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6496                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6497                 uint16_t count, uint16_t rule_id)
6498 {
6499         struct i40e_aq_desc desc;
6500         struct i40e_aqc_add_delete_mirror_rule cmd;
6501         uint16_t buff_len = 0;
6502         enum i40e_status_code status;
6503         void *buff = NULL;
6504
6505         i40e_fill_default_direct_cmd_desc(&desc,
6506                                           i40e_aqc_opc_delete_mirror_rule);
6507         memset(&cmd, 0, sizeof(cmd));
6508         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6509                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6510                                                           I40E_AQ_FLAG_RD));
6511                 cmd.num_entries = count;
6512                 buff_len = sizeof(uint16_t) * count;
6513                 desc.datalen = rte_cpu_to_le_16(buff_len);
6514                 buff = (void *)entries;
6515         } else
6516                 /* rule id is filled in destination field for deleting mirror rule */
6517                 cmd.destination = rte_cpu_to_le_16(rule_id);
6518
6519         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6520                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6521         cmd.seid = rte_cpu_to_le_16(seid);
6522
6523         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6524         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6525
6526         return status;
6527 }
6528
6529 /**
6530  * i40e_mirror_rule_set
6531  * @dev: pointer to the hardware structure
6532  * @mirror_conf: mirror rule info
6533  * @sw_id: mirror rule's sw_id
6534  * @on: enable/disable
6535  *
6536  * set a mirror rule.
6537  *
6538  **/
6539 static int
6540 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6541                         struct rte_eth_mirror_conf *mirror_conf,
6542                         uint8_t sw_id, uint8_t on)
6543 {
6544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6547         struct i40e_mirror_rule *parent = NULL;
6548         uint16_t seid, dst_seid, rule_id;
6549         uint16_t i, j = 0;
6550         int ret;
6551
6552         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6553
6554         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6555                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6556                         " without veb or vfs.");
6557                 return -ENOSYS;
6558         }
6559         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6560                 PMD_DRV_LOG(ERR, "mirror table is full.");
6561                 return -ENOSPC;
6562         }
6563         if (mirror_conf->dst_pool > pf->vf_num) {
6564                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6565                                  mirror_conf->dst_pool);
6566                 return -EINVAL;
6567         }
6568
6569         seid = pf->main_vsi->veb->seid;
6570
6571         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6572                 if (sw_id <= it->index) {
6573                         mirr_rule = it;
6574                         break;
6575                 }
6576                 parent = it;
6577         }
6578         if (mirr_rule && sw_id == mirr_rule->index) {
6579                 if (on) {
6580                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6581                         return -EEXIST;
6582                 } else {
6583                         ret = i40e_aq_del_mirror_rule(hw, seid,
6584                                         mirr_rule->rule_type,
6585                                         mirr_rule->entries,
6586                                         mirr_rule->num_entries, mirr_rule->id);
6587                         if (ret < 0) {
6588                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6589                                                    " ret = %d, aq_err = %d.",
6590                                                    ret, hw->aq.asq_last_status);
6591                                 return -ENOSYS;
6592                         }
6593                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6594                         rte_free(mirr_rule);
6595                         pf->nb_mirror_rule--;
6596                         return 0;
6597                 }
6598         } else if (!on) {
6599                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6600                 return -ENOENT;
6601         }
6602
6603         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6604                                 sizeof(struct i40e_mirror_rule) , 0);
6605         if (!mirr_rule) {
6606                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6607                 return I40E_ERR_NO_MEMORY;
6608         }
6609         switch (mirror_conf->rule_type) {
6610         case ETH_MIRROR_VLAN:
6611                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6612                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6613                                 mirr_rule->entries[j] =
6614                                         mirror_conf->vlan.vlan_id[i];
6615                                 j++;
6616                         }
6617                 }
6618                 if (j == 0) {
6619                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6620                         rte_free(mirr_rule);
6621                         return -EINVAL;
6622                 }
6623                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6624                 break;
6625         case ETH_MIRROR_VIRTUAL_POOL_UP:
6626         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6627                 /* check if the specified pool bit is out of range */
6628                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6629                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6630                         rte_free(mirr_rule);
6631                         return -EINVAL;
6632                 }
6633                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6634                         if (mirror_conf->pool_mask & (1ULL << i)) {
6635                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6636                                 j++;
6637                         }
6638                 }
6639                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6640                         /* add pf vsi to entries */
6641                         mirr_rule->entries[j] = pf->main_vsi_seid;
6642                         j++;
6643                 }
6644                 if (j == 0) {
6645                         PMD_DRV_LOG(ERR, "pool is not specified.");
6646                         rte_free(mirr_rule);
6647                         return -EINVAL;
6648                 }
6649                 /* egress and ingress in aq commands means from switch but not port */
6650                 mirr_rule->rule_type =
6651                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6652                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6653                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6654                 break;
6655         case ETH_MIRROR_UPLINK_PORT:
6656                 /* egress and ingress in aq commands means from switch but not port*/
6657                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6658                 break;
6659         case ETH_MIRROR_DOWNLINK_PORT:
6660                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6661                 break;
6662         default:
6663                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6664                         mirror_conf->rule_type);
6665                 rte_free(mirr_rule);
6666                 return -EINVAL;
6667         }
6668
6669         /* If the dst_pool is equal to vf_num, consider it as PF */
6670         if (mirror_conf->dst_pool == pf->vf_num)
6671                 dst_seid = pf->main_vsi_seid;
6672         else
6673                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6674
6675         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6676                                       mirr_rule->rule_type, mirr_rule->entries,
6677                                       j, &rule_id);
6678         if (ret < 0) {
6679                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6680                                    " ret = %d, aq_err = %d.",
6681                                    ret, hw->aq.asq_last_status);
6682                 rte_free(mirr_rule);
6683                 return -ENOSYS;
6684         }
6685
6686         mirr_rule->index = sw_id;
6687         mirr_rule->num_entries = j;
6688         mirr_rule->id = rule_id;
6689         mirr_rule->dst_vsi_seid = dst_seid;
6690
6691         if (parent)
6692                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6693         else
6694                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6695
6696         pf->nb_mirror_rule++;
6697         return 0;
6698 }
6699
6700 /**
6701  * i40e_mirror_rule_reset
6702  * @dev: pointer to the device
6703  * @sw_id: mirror rule's sw_id
6704  *
6705  * reset a mirror rule.
6706  *
6707  **/
6708 static int
6709 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6710 {
6711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6713         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6714         uint16_t seid;
6715         int ret;
6716
6717         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6718
6719         seid = pf->main_vsi->veb->seid;
6720
6721         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6722                 if (sw_id == it->index) {
6723                         mirr_rule = it;
6724                         break;
6725                 }
6726         }
6727         if (mirr_rule) {
6728                 ret = i40e_aq_del_mirror_rule(hw, seid,
6729                                 mirr_rule->rule_type,
6730                                 mirr_rule->entries,
6731                                 mirr_rule->num_entries, mirr_rule->id);
6732                 if (ret < 0) {
6733                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6734                                            " status = %d, aq_err = %d.",
6735                                            ret, hw->aq.asq_last_status);
6736                         return -ENOSYS;
6737                 }
6738                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6739                 rte_free(mirr_rule);
6740                 pf->nb_mirror_rule--;
6741         } else {
6742                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6743                 return -ENOENT;
6744         }
6745         return 0;
6746 }
6747
6748 static int
6749 i40e_timesync_enable(struct rte_eth_dev *dev)
6750 {
6751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752         struct rte_eth_link *link = &dev->data->dev_link;
6753         uint32_t tsync_ctl_l;
6754         uint32_t tsync_ctl_h;
6755         uint32_t tsync_inc_l;
6756         uint32_t tsync_inc_h;
6757
6758         switch (link->link_speed) {
6759         case ETH_LINK_SPEED_40G:
6760                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6761                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6762                 break;
6763         case ETH_LINK_SPEED_10G:
6764                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6765                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6766                 break;
6767         case ETH_LINK_SPEED_1000:
6768                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6769                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6770                 break;
6771         default:
6772                 tsync_inc_l = 0x0;
6773                 tsync_inc_h = 0x0;
6774         }
6775
6776         /* Clear timesync registers. */
6777         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6778         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6779         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6780         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6781         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6782         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6783         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6784
6785         /* Set the timesync increment value. */
6786         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6787         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6788
6789         /* Enable timestamping of PTP packets. */
6790         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6791         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6792
6793         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6794         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6795         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6796
6797         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6798         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6799
6800         return 0;
6801 }
6802
6803 static int
6804 i40e_timesync_disable(struct rte_eth_dev *dev)
6805 {
6806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6807         uint32_t tsync_ctl_l;
6808         uint32_t tsync_ctl_h;
6809
6810         /* Disable timestamping of transmitted PTP packets. */
6811         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6812         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6813
6814         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6815         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6816
6817         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6818         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6819
6820         /* Set the timesync increment value. */
6821         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6822         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6823
6824         return 0;
6825 }
6826
6827 static int
6828 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6829                                 struct timespec *timestamp, uint32_t flags)
6830 {
6831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6832         uint32_t sync_status;
6833         uint32_t rx_stmpl;
6834         uint32_t rx_stmph;
6835         uint32_t index = flags & 0x03;
6836
6837         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6838         if ((sync_status & (1 << index)) == 0)
6839                 return -EINVAL;
6840
6841         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6842         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6843
6844         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6845         timestamp->tv_nsec = 0;
6846
6847         return  0;
6848 }
6849
6850 static int
6851 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6852                                 struct timespec *timestamp)
6853 {
6854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6855         uint32_t sync_status;
6856         uint32_t tx_stmpl;
6857         uint32_t tx_stmph;
6858
6859         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6860         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6861                 return -EINVAL;
6862
6863         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6864         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6865
6866         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6867         timestamp->tv_nsec = 0;
6868
6869         return  0;
6870 }
6871
6872 /*
6873  * i40e_parse_dcb_configure - parse dcb configure from user
6874  * @dev: the device being configured
6875  * @dcb_cfg: pointer of the result of parse
6876  * @*tc_map: bit map of enabled traffic classes
6877  *
6878  * Returns 0 on success, negative value on failure
6879  */
6880 static int
6881 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6882                          struct i40e_dcbx_config *dcb_cfg,
6883                          uint8_t *tc_map)
6884 {
6885         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6886         uint8_t i, tc_bw, bw_lf;
6887
6888         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6889
6890         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6891         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6892                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6893                 return -EINVAL;
6894         }
6895
6896         /* assume each tc has the same bw */
6897         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6898         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6899                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6900         /* to ensure the sum of tcbw is equal to 100 */
6901         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6902         for (i = 0; i < bw_lf; i++)
6903                 dcb_cfg->etscfg.tcbwtable[i]++;
6904
6905         /* assume each tc has the same Transmission Selection Algorithm */
6906         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6907                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6908
6909         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6910                 dcb_cfg->etscfg.prioritytable[i] =
6911                                 dcb_rx_conf->dcb_tc[i];
6912
6913         /* FW needs one App to configure HW */
6914         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6915         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6916         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6917         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6918
6919         if (dcb_rx_conf->nb_tcs == 0)
6920                 *tc_map = 1; /* tc0 only */
6921         else
6922                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6923
6924         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6925                 dcb_cfg->pfc.willing = 0;
6926                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6927                 dcb_cfg->pfc.pfcenable = *tc_map;
6928         }
6929         return 0;
6930 }
6931
6932 /*
6933  * i40e_vsi_get_bw_info - Query VSI BW Information
6934  * @vsi: the VSI being queried
6935  *
6936  * Returns 0 on success, negative value on failure
6937  */
6938 static int
6939 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6940 {
6941         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6942         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6943         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6944         int i, ret;
6945         uint32_t tc_bw_max;
6946
6947         /* Get the VSI level BW configuration */
6948         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6949         if (ret) {
6950                 PMD_INIT_LOG(ERR,
6951                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
6952                          i40e_stat_str(hw, ret),
6953                          i40e_aq_str(hw, hw->aq.asq_last_status));
6954                 return -EINVAL;
6955         }
6956
6957         /* Get the VSI level BW configuration per TC */
6958         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6959                                                   NULL);
6960         if (ret) {
6961                 PMD_INIT_LOG(ERR,
6962                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6963                          i40e_stat_str(hw, ret),
6964                          i40e_aq_str(hw, hw->aq.asq_last_status));
6965                 return -EINVAL;
6966         }
6967
6968         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6969                 PMD_INIT_LOG(WARNING,
6970                          "Enabled TCs mismatch from querying VSI BW info"
6971                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6972                          bw_ets_config.tc_valid_bits);
6973                 /* Still continuing */
6974         }
6975
6976         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6977         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6978         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6979                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6980         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6981                 vsi->bw_info.bw_ets_share_credits[i] =
6982                                 bw_ets_config.share_credits[i];
6983                 vsi->bw_info.bw_ets_limit_credits[i] =
6984                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6985                 /* 3 bits out of 4 for each TC */
6986                 vsi->bw_info.bw_ets_max_quanta[i] =
6987                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6988                 PMD_INIT_LOG(DEBUG,
6989                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6990                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
6991         }
6992
6993         return 0;
6994 }
6995
6996 static int
6997 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6998                               struct i40e_aqc_vsi_properties_data *info,
6999                               uint8_t enabled_tcmap)
7000 {
7001         int ret, i, total_tc = 0;
7002         uint16_t qpnum_per_tc, bsf, qp_idx;
7003         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
7004
7005         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
7006         if (ret != I40E_SUCCESS)
7007                 return ret;
7008
7009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7010                 if (enabled_tcmap & (1 << i))
7011                         total_tc++;
7012         }
7013         if (total_tc == 0)
7014                 total_tc = 1;
7015         vsi->enabled_tc = enabled_tcmap;
7016
7017         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
7018         /* Number of queues per enabled TC */
7019         if (qpnum_per_tc == 0) {
7020                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
7021                 return I40E_ERR_INVALID_QP_ID;
7022         }
7023         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
7024                                 I40E_MAX_Q_PER_TC);
7025         bsf = rte_bsf32(qpnum_per_tc);
7026
7027         /**
7028          * Configure TC and queue mapping parameters, for enabled TC,
7029          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
7030          * default queue will serve it.
7031          */
7032         qp_idx = 0;
7033         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7034                 if (vsi->enabled_tc & (1 << i)) {
7035                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
7036                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7037                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
7038                         qp_idx += qpnum_per_tc;
7039                 } else
7040                         info->tc_mapping[i] = 0;
7041         }
7042
7043         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
7044         if (vsi->type == I40E_VSI_SRIOV) {
7045                 info->mapping_flags |=
7046                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
7047                 for (i = 0; i < vsi->nb_qps; i++)
7048                         info->queue_mapping[i] =
7049                                 rte_cpu_to_le_16(vsi->base_queue + i);
7050         } else {
7051                 info->mapping_flags |=
7052                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7053                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
7054         }
7055         info->valid_sections |=
7056                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
7057
7058         return I40E_SUCCESS;
7059 }
7060
7061 /*
7062  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
7063  * @vsi: VSI to be configured
7064  * @tc_map: enabled TC bitmap
7065  *
7066  * Returns 0 on success, negative value on failure
7067  */
7068 static int
7069 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
7070 {
7071         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
7072         struct i40e_vsi_context ctxt;
7073         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7074         int ret = 0;
7075         int i;
7076
7077         /* Check if enabled_tc is same as existing or new TCs */
7078         if (vsi->enabled_tc == tc_map)
7079                 return ret;
7080
7081         /* configure tc bandwidth */
7082         memset(&bw_data, 0, sizeof(bw_data));
7083         bw_data.tc_valid_bits = tc_map;
7084         /* Enable ETS TCs with equal BW Share for now across all VSIs */
7085         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7086                 if (tc_map & BIT_ULL(i))
7087                         bw_data.tc_bw_credits[i] = 1;
7088         }
7089         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
7090         if (ret) {
7091                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
7092                         " per TC failed = %d",
7093                         hw->aq.asq_last_status);
7094                 goto out;
7095         }
7096         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
7097                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
7098
7099         /* Update Queue Pairs Mapping for currently enabled UPs */
7100         ctxt.seid = vsi->seid;
7101         ctxt.pf_num = hw->pf_id;
7102         ctxt.vf_num = 0;
7103         ctxt.uplink_seid = vsi->uplink_seid;
7104         ctxt.info = vsi->info;
7105         i40e_get_cap(hw);
7106         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
7107         if (ret)
7108                 goto out;
7109
7110         /* Update the VSI after updating the VSI queue-mapping information */
7111         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7112         if (ret) {
7113                 PMD_INIT_LOG(ERR, "Failed to configure "
7114                             "TC queue mapping = %d",
7115                             hw->aq.asq_last_status);
7116                 goto out;
7117         }
7118         /* update the local VSI info with updated queue map */
7119         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7120                                         sizeof(vsi->info.tc_mapping));
7121         (void)rte_memcpy(&vsi->info.queue_mapping,
7122                         &ctxt.info.queue_mapping,
7123                 sizeof(vsi->info.queue_mapping));
7124         vsi->info.mapping_flags = ctxt.info.mapping_flags;
7125         vsi->info.valid_sections = 0;
7126
7127         /* Update current VSI BW information */
7128         ret = i40e_vsi_get_bw_info(vsi);
7129         if (ret) {
7130                 PMD_INIT_LOG(ERR,
7131                          "Failed updating vsi bw info, err %s aq_err %s",
7132                          i40e_stat_str(hw, ret),
7133                          i40e_aq_str(hw, hw->aq.asq_last_status));
7134                 goto out;
7135         }
7136
7137         vsi->enabled_tc = tc_map;
7138
7139 out:
7140         return ret;
7141 }
7142
7143 /*
7144  * i40e_dcb_hw_configure - program the dcb setting to hw
7145  * @pf: pf the configuration is taken on
7146  * @new_cfg: new configuration
7147  * @tc_map: enabled TC bitmap
7148  *
7149  * Returns 0 on success, negative value on failure
7150  */
7151 static enum i40e_status_code
7152 i40e_dcb_hw_configure(struct i40e_pf *pf,
7153                       struct i40e_dcbx_config *new_cfg,
7154                       uint8_t tc_map)
7155 {
7156         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7157         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7158         struct i40e_vsi *main_vsi = pf->main_vsi;
7159         struct i40e_vsi_list *vsi_list;
7160         int i, ret;
7161         uint32_t val;
7162
7163         /* Use the FW API if FW > v4.4*/
7164         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7165                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7166                                   " to configure DCB");
7167                 return I40E_ERR_FIRMWARE_API_VERSION;
7168         }
7169
7170         /* Check if need reconfiguration */
7171         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7172                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7173                 return I40E_SUCCESS;
7174         }
7175
7176         /* Copy the new config to the current config */
7177         *old_cfg = *new_cfg;
7178         old_cfg->etsrec = old_cfg->etscfg;
7179         ret = i40e_set_dcb_config(hw);
7180         if (ret) {
7181                 PMD_INIT_LOG(ERR,
7182                          "Set DCB Config failed, err %s aq_err %s\n",
7183                          i40e_stat_str(hw, ret),
7184                          i40e_aq_str(hw, hw->aq.asq_last_status));
7185                 return ret;
7186         }
7187         /* set receive Arbiter to RR mode and ETS scheme by default */
7188         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7189                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7190                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
7191                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7192                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7193                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7194                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7195                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
7196                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
7197                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
7198                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
7199                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
7200                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
7201         }
7202         /* get local mib to check whether it is configured correctly */
7203         /* IEEE mode */
7204         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
7205         /* Get Local DCB Config */
7206         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
7207                                      &hw->local_dcbx_config);
7208
7209         /* Update each VSI */
7210         i40e_vsi_config_tc(main_vsi, tc_map);
7211         if (main_vsi->veb) {
7212                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
7213                         /* Beside main VSI, only enable default
7214                          * TC for other VSIs
7215                          */
7216                         ret = i40e_vsi_config_tc(vsi_list->vsi,
7217                                                 I40E_DEFAULT_TCMAP);
7218                         if (ret)
7219                                 PMD_INIT_LOG(WARNING,
7220                                          "Failed configuring TC for VSI seid=%d\n",
7221                                          vsi_list->vsi->seid);
7222                         /* continue */
7223                 }
7224         }
7225         return I40E_SUCCESS;
7226 }
7227
7228 /*
7229  * i40e_dcb_init_configure - initial dcb config
7230  * @dev: device being configured
7231  * @sw_dcb: indicate whether dcb is sw configured or hw offload
7232  *
7233  * Returns 0 on success, negative value on failure
7234  */
7235 static int
7236 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
7237 {
7238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7240         int ret = 0;
7241
7242         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7243                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7244                 return -ENOTSUP;
7245         }
7246
7247         /* DCB initialization:
7248          * Update DCB configuration from the Firmware and configure
7249          * LLDP MIB change event.
7250          */
7251         if (sw_dcb == TRUE) {
7252                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
7253                 if (ret != I40E_SUCCESS)
7254                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
7255
7256                 ret = i40e_init_dcb(hw);
7257                 /* if sw_dcb, lldp agent is stopped, the return from
7258                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
7259                  * adminq status.
7260                  */
7261                 if (ret != I40E_SUCCESS &&
7262                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
7263                         memset(&hw->local_dcbx_config, 0,
7264                                 sizeof(struct i40e_dcbx_config));
7265                         /* set dcb default configuration */
7266                         hw->local_dcbx_config.etscfg.willing = 0;
7267                         hw->local_dcbx_config.etscfg.maxtcs = 0;
7268                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
7269                         hw->local_dcbx_config.etscfg.tsatable[0] =
7270                                                 I40E_IEEE_TSA_ETS;
7271                         hw->local_dcbx_config.etsrec =
7272                                 hw->local_dcbx_config.etscfg;
7273                         hw->local_dcbx_config.pfc.willing = 0;
7274                         hw->local_dcbx_config.pfc.pfccap =
7275                                                 I40E_MAX_TRAFFIC_CLASS;
7276                         /* FW needs one App to configure HW */
7277                         hw->local_dcbx_config.numapps = 1;
7278                         hw->local_dcbx_config.app[0].selector =
7279                                                 I40E_APP_SEL_ETHTYPE;
7280                         hw->local_dcbx_config.app[0].priority = 3;
7281                         hw->local_dcbx_config.app[0].protocolid =
7282                                                 I40E_APP_PROTOID_FCOE;
7283                         ret = i40e_set_dcb_config(hw);
7284                         if (ret) {
7285                                 PMD_INIT_LOG(ERR, "default dcb config fails."
7286                                         " err = %d, aq_err = %d.", ret,
7287                                           hw->aq.asq_last_status);
7288                                 return -ENOSYS;
7289                         }
7290                 } else {
7291                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7292                                           " aq_err = %d.", ret,
7293                                           hw->aq.asq_last_status);
7294                         return -ENOTSUP;
7295                 }
7296         } else {
7297                 ret = i40e_aq_start_lldp(hw, NULL);
7298                 if (ret != I40E_SUCCESS)
7299                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
7300
7301                 ret = i40e_init_dcb(hw);
7302                 if (!ret) {
7303                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
7304                                 PMD_INIT_LOG(ERR, "HW doesn't support"
7305                                                   " DCBX offload.");
7306                                 return -ENOTSUP;
7307                         }
7308                 } else {
7309                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7310                                           " aq_err = %d.", ret,
7311                                           hw->aq.asq_last_status);
7312                         return -ENOTSUP;
7313                 }
7314         }
7315         return 0;
7316 }
7317
7318 /*
7319  * i40e_dcb_setup - setup dcb related config
7320  * @dev: device being configured
7321  *
7322  * Returns 0 on success, negative value on failure
7323  */
7324 static int
7325 i40e_dcb_setup(struct rte_eth_dev *dev)
7326 {
7327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7328         struct i40e_dcbx_config dcb_cfg;
7329         uint8_t tc_map = 0;
7330         int ret = 0;
7331
7332         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7333                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7334                 return -ENOTSUP;
7335         }
7336
7337         if (pf->vf_num != 0 ||
7338             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7339                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7340
7341         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7342         if (ret) {
7343                 PMD_INIT_LOG(ERR, "invalid dcb config");
7344                 return -EINVAL;
7345         }
7346         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7347         if (ret) {
7348                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7349                 return -ENOSYS;
7350         }
7351         return 0;
7352 }
7353
7354 static int
7355 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7356                       struct rte_eth_dcb_info *dcb_info)
7357 {
7358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7360         struct i40e_vsi *vsi = pf->main_vsi;
7361         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7362         uint16_t bsf, tc_mapping;
7363         int i;
7364
7365         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7366                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7367         else
7368                 dcb_info->nb_tcs = 1;
7369         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7370                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7371         for (i = 0; i < dcb_info->nb_tcs; i++)
7372                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7373
7374         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7375                 if (vsi->enabled_tc & (1 << i)) {
7376                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7377                         /* only main vsi support multi TCs */
7378                         dcb_info->tc_queue.tc_rxq[0][i].base =
7379                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7380                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7381                         dcb_info->tc_queue.tc_txq[0][i].base =
7382                                 dcb_info->tc_queue.tc_rxq[0][i].base;
7383                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7384                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7385                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7386                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7387                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
7388                 }
7389         }
7390         return 0;
7391 }