1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 static const char *const valid_keys[] = {
402 ETH_I40E_FLOATING_VEB_ARG,
403 ETH_I40E_FLOATING_VEB_LIST_ARG,
404 ETH_I40E_SUPPORT_MULTI_DRIVER,
405 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
406 ETH_I40E_USE_LATEST_VEC,
410 static const struct rte_pci_id pci_id_i40e_map[] = {
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .fw_version_get = i40e_fw_version_get,
459 .dev_infos_get = i40e_dev_info_get,
460 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
461 .vlan_filter_set = i40e_vlan_filter_set,
462 .vlan_tpid_set = i40e_vlan_tpid_set,
463 .vlan_offload_set = i40e_vlan_offload_set,
464 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
465 .vlan_pvid_set = i40e_vlan_pvid_set,
466 .rx_queue_start = i40e_dev_rx_queue_start,
467 .rx_queue_stop = i40e_dev_rx_queue_stop,
468 .tx_queue_start = i40e_dev_tx_queue_start,
469 .tx_queue_stop = i40e_dev_tx_queue_stop,
470 .rx_queue_setup = i40e_dev_rx_queue_setup,
471 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
472 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
473 .rx_queue_release = i40e_dev_rx_queue_release,
474 .rx_queue_count = i40e_dev_rx_queue_count,
475 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
476 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
477 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
478 .tx_queue_setup = i40e_dev_tx_queue_setup,
479 .tx_queue_release = i40e_dev_tx_queue_release,
480 .dev_led_on = i40e_dev_led_on,
481 .dev_led_off = i40e_dev_led_off,
482 .flow_ctrl_get = i40e_flow_ctrl_get,
483 .flow_ctrl_set = i40e_flow_ctrl_set,
484 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
485 .mac_addr_add = i40e_macaddr_add,
486 .mac_addr_remove = i40e_macaddr_remove,
487 .reta_update = i40e_dev_rss_reta_update,
488 .reta_query = i40e_dev_rss_reta_query,
489 .rss_hash_update = i40e_dev_rss_hash_update,
490 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
491 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
492 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
493 .filter_ctrl = i40e_dev_filter_ctrl,
494 .rxq_info_get = i40e_rxq_info_get,
495 .txq_info_get = i40e_txq_info_get,
496 .rx_burst_mode_get = i40e_rx_burst_mode_get,
497 .tx_burst_mode_get = i40e_tx_burst_mode_get,
498 .mirror_rule_set = i40e_mirror_rule_set,
499 .mirror_rule_reset = i40e_mirror_rule_reset,
500 .timesync_enable = i40e_timesync_enable,
501 .timesync_disable = i40e_timesync_disable,
502 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
503 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
504 .get_dcb_info = i40e_dev_get_dcb_info,
505 .timesync_adjust_time = i40e_timesync_adjust_time,
506 .timesync_read_time = i40e_timesync_read_time,
507 .timesync_write_time = i40e_timesync_write_time,
508 .get_reg = i40e_get_regs,
509 .get_eeprom_length = i40e_get_eeprom_length,
510 .get_eeprom = i40e_get_eeprom,
511 .get_module_info = i40e_get_module_info,
512 .get_module_eeprom = i40e_get_module_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
515 .tm_ops_get = i40e_tm_ops_get,
516 .tx_done_cleanup = i40e_tx_done_cleanup,
519 /* store statistics names and its offset in stats structure */
520 struct rte_i40e_xstats_name_off {
521 char name[RTE_ETH_XSTATS_NAME_SIZE];
525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
526 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
527 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
528 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
529 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
530 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
531 rx_unknown_protocol)},
532 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
533 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
534 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
535 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
539 sizeof(rte_i40e_stats_strings[0]))
541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
542 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
543 tx_dropped_link_down)},
544 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
545 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
548 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
550 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
554 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
555 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
556 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
557 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
558 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
559 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
576 mac_short_packet_dropped)},
577 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
580 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
581 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_flow_director_atr_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
595 {"rx_flow_director_sb_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
597 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
608 sizeof(rte_i40e_hw_port_strings[0]))
610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
611 {"xon_packets", offsetof(struct i40e_hw_port_stats,
613 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
618 sizeof(rte_i40e_rxq_prio_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
626 priority_xon_2_xoff)},
629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
630 sizeof(rte_i40e_txq_prio_strings[0]))
633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 char name[RTE_ETH_NAME_MAX_LEN];
637 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
640 if (pci_dev->device.devargs) {
641 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
647 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
648 sizeof(struct i40e_adapter),
649 eth_dev_pci_specific_init, pci_dev,
650 eth_i40e_dev_init, NULL);
652 if (retval || eth_da.nb_representor_ports < 1)
655 /* probe VF representor ports */
656 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
657 pci_dev->device.name);
659 if (pf_ethdev == NULL)
662 for (i = 0; i < eth_da.nb_representor_ports; i++) {
663 struct i40e_vf_representor representor = {
664 .vf_id = eth_da.representor_ports[i],
665 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
666 pf_ethdev->data->dev_private)->switch_domain_id,
667 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
668 pf_ethdev->data->dev_private)
671 /* representor port net_bdf_port */
672 snprintf(name, sizeof(name), "net_%s_representor_%d",
673 pci_dev->device.name, eth_da.representor_ports[i]);
675 retval = rte_eth_dev_create(&pci_dev->device, name,
676 sizeof(struct i40e_vf_representor), NULL, NULL,
677 i40e_vf_representor_init, &representor);
680 PMD_DRV_LOG(ERR, "failed to create i40e vf "
681 "representor %s.", name);
687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
689 struct rte_eth_dev *ethdev;
691 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
695 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
696 return rte_eth_dev_pci_generic_remove(pci_dev,
697 i40e_vf_representor_uninit);
699 return rte_eth_dev_pci_generic_remove(pci_dev,
700 eth_i40e_dev_uninit);
703 static struct rte_pci_driver rte_i40e_pmd = {
704 .id_table = pci_id_i40e_map,
705 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
706 .probe = eth_i40e_pci_probe,
707 .remove = eth_i40e_pci_remove,
711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
714 uint32_t ori_reg_val;
715 struct rte_eth_dev *dev;
717 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
718 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
719 i40e_write_rx_ctl(hw, reg_addr, reg_val);
720 if (ori_reg_val != reg_val)
722 "i40e device %s changed global register [0x%08x]."
723 " original: 0x%08x, new: 0x%08x",
724 dev->device->name, reg_addr, ori_reg_val, reg_val);
727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
731 #ifndef I40E_GLQF_ORT
732 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
734 #ifndef I40E_GLQF_PIT
735 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
737 #ifndef I40E_GLQF_L3_MAP
738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
744 * Initialize registers for parsing packet type of QinQ
745 * This should be removed from code once proper
746 * configuration API is added to avoid configuration conflicts
747 * between ports of the same device.
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
750 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
753 static inline void i40e_config_automask(struct i40e_pf *pf)
755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
758 /* INTENA flag is not auto-cleared for interrupt */
759 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
760 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
761 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
763 /* If support multi-driver, PF will use INT0. */
764 if (!pf->support_multi_driver)
765 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
767 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
770 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
773 * Add a ethertype filter to drop all flow control frames transmitted
777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
780 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
782 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
785 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
786 I40E_FLOW_CONTROL_ETHERTYPE, flags,
787 pf->main_vsi_seid, 0,
791 "Failed to add filter to drop flow control frames from VSIs.");
795 floating_veb_list_handler(__rte_unused const char *key,
796 const char *floating_veb_value,
800 unsigned int count = 0;
803 bool *vf_floating_veb = opaque;
805 while (isblank(*floating_veb_value))
806 floating_veb_value++;
808 /* Reset floating VEB configuration for VFs */
809 for (idx = 0; idx < I40E_MAX_VF; idx++)
810 vf_floating_veb[idx] = false;
814 while (isblank(*floating_veb_value))
815 floating_veb_value++;
816 if (*floating_veb_value == '\0')
819 idx = strtoul(floating_veb_value, &end, 10);
820 if (errno || end == NULL)
822 while (isblank(*end))
826 } else if ((*end == ';') || (*end == '\0')) {
828 if (min == I40E_MAX_VF)
830 if (max >= I40E_MAX_VF)
831 max = I40E_MAX_VF - 1;
832 for (idx = min; idx <= max; idx++) {
833 vf_floating_veb[idx] = true;
840 floating_veb_value = end + 1;
841 } while (*end != '\0');
850 config_vf_floating_veb(struct rte_devargs *devargs,
851 uint16_t floating_veb,
852 bool *vf_floating_veb)
854 struct rte_kvargs *kvlist;
856 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
860 /* All the VFs attach to the floating VEB by default
861 * when the floating VEB is enabled.
863 for (i = 0; i < I40E_MAX_VF; i++)
864 vf_floating_veb[i] = true;
869 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
873 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
874 rte_kvargs_free(kvlist);
877 /* When the floating_veb_list parameter exists, all the VFs
878 * will attach to the legacy VEB firstly, then configure VFs
879 * to the floating VEB according to the floating_veb_list.
881 if (rte_kvargs_process(kvlist, floating_veb_list,
882 floating_veb_list_handler,
883 vf_floating_veb) < 0) {
884 rte_kvargs_free(kvlist);
887 rte_kvargs_free(kvlist);
891 i40e_check_floating_handler(__rte_unused const char *key,
893 __rte_unused void *opaque)
895 if (strcmp(value, "1"))
902 is_floating_veb_supported(struct rte_devargs *devargs)
904 struct rte_kvargs *kvlist;
905 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
910 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
914 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
915 rte_kvargs_free(kvlist);
918 /* Floating VEB is enabled when there's key-value:
919 * enable_floating_veb=1
921 if (rte_kvargs_process(kvlist, floating_veb_key,
922 i40e_check_floating_handler, NULL) < 0) {
923 rte_kvargs_free(kvlist);
926 rte_kvargs_free(kvlist);
932 config_floating_veb(struct rte_eth_dev *dev)
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
938 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
940 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
942 is_floating_veb_supported(pci_dev->device.devargs);
943 config_vf_floating_veb(pci_dev->device.devargs,
945 pf->floating_veb_list);
947 pf->floating_veb = false;
951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
958 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
959 char ethertype_hash_name[RTE_HASH_NAMESIZE];
962 struct rte_hash_parameters ethertype_hash_params = {
963 .name = ethertype_hash_name,
964 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
965 .key_len = sizeof(struct i40e_ethertype_filter_input),
966 .hash_func = rte_hash_crc,
967 .hash_func_init_val = 0,
968 .socket_id = rte_socket_id(),
971 /* Initialize ethertype filter rule list and hash */
972 TAILQ_INIT(ðertype_rule->ethertype_list);
973 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
974 "ethertype_%s", dev->device->name);
975 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
976 if (!ethertype_rule->hash_table) {
977 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
980 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
981 sizeof(struct i40e_ethertype_filter *) *
982 I40E_MAX_ETHERTYPE_FILTER_NUM,
984 if (!ethertype_rule->hash_map) {
986 "Failed to allocate memory for ethertype hash map!");
988 goto err_ethertype_hash_map_alloc;
993 err_ethertype_hash_map_alloc:
994 rte_hash_free(ethertype_rule->hash_table);
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1007 struct rte_hash_parameters tunnel_hash_params = {
1008 .name = tunnel_hash_name,
1009 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011 .hash_func = rte_hash_crc,
1012 .hash_func_init_val = 0,
1013 .socket_id = rte_socket_id(),
1016 /* Initialize tunnel filter rule list and hash */
1017 TAILQ_INIT(&tunnel_rule->tunnel_list);
1018 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019 "tunnel_%s", dev->device->name);
1020 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021 if (!tunnel_rule->hash_table) {
1022 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1025 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026 sizeof(struct i40e_tunnel_filter *) *
1027 I40E_MAX_TUNNEL_FILTER_NUM,
1029 if (!tunnel_rule->hash_map) {
1031 "Failed to allocate memory for tunnel hash map!");
1033 goto err_tunnel_hash_map_alloc;
1038 err_tunnel_hash_map_alloc:
1039 rte_hash_free(tunnel_rule->hash_table);
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1052 struct rte_hash_parameters fdir_hash_params = {
1053 .name = fdir_hash_name,
1054 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055 .key_len = sizeof(struct i40e_fdir_input),
1056 .hash_func = rte_hash_crc,
1057 .hash_func_init_val = 0,
1058 .socket_id = rte_socket_id(),
1061 /* Initialize flow director filter rule list and hash */
1062 TAILQ_INIT(&fdir_info->fdir_list);
1063 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064 "fdir_%s", dev->device->name);
1065 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066 if (!fdir_info->hash_table) {
1067 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1070 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071 sizeof(struct i40e_fdir_filter *) *
1072 I40E_MAX_FDIR_FILTER_NUM,
1074 if (!fdir_info->hash_map) {
1076 "Failed to allocate memory for fdir hash map!");
1078 goto err_fdir_hash_map_alloc;
1082 err_fdir_hash_map_alloc:
1083 rte_hash_free(fdir_info->hash_table);
1089 i40e_init_customized_info(struct i40e_pf *pf)
1093 /* Initialize customized pctype */
1094 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095 pf->customized_pctype[i].index = i;
1096 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097 pf->customized_pctype[i].valid = false;
1100 pf->gtp_support = false;
1101 pf->esp_support = false;
1105 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1109 struct i40e_queue_regions *info = &pf->queue_region;
1112 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1113 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1115 memset(info, 0, sizeof(struct i40e_queue_regions));
1119 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1124 unsigned long support_multi_driver;
1127 pf = (struct i40e_pf *)opaque;
1130 support_multi_driver = strtoul(value, &end, 10);
1131 if (errno != 0 || end == value || *end != 0) {
1132 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1136 if (support_multi_driver == 1 || support_multi_driver == 0)
1137 pf->support_multi_driver = (bool)support_multi_driver;
1139 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1140 "enable global configuration by default."
1141 ETH_I40E_SUPPORT_MULTI_DRIVER);
1146 i40e_support_multi_driver(struct rte_eth_dev *dev)
1148 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1149 struct rte_kvargs *kvlist;
1152 /* Enable global configuration by default */
1153 pf->support_multi_driver = false;
1155 if (!dev->device->devargs)
1158 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1162 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1163 if (!kvargs_count) {
1164 rte_kvargs_free(kvlist);
1168 if (kvargs_count > 1)
1169 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1170 "the first invalid or last valid one is used !",
1171 ETH_I40E_SUPPORT_MULTI_DRIVER);
1173 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1174 i40e_parse_multi_drv_handler, pf) < 0) {
1175 rte_kvargs_free(kvlist);
1179 rte_kvargs_free(kvlist);
1184 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1185 uint32_t reg_addr, uint64_t reg_val,
1186 struct i40e_asq_cmd_details *cmd_details)
1188 uint64_t ori_reg_val;
1189 struct rte_eth_dev *dev;
1192 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1193 if (ret != I40E_SUCCESS) {
1195 "Fail to debug read from 0x%08x",
1199 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1201 if (ori_reg_val != reg_val)
1202 PMD_DRV_LOG(WARNING,
1203 "i40e device %s changed global register [0x%08x]."
1204 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1205 dev->device->name, reg_addr, ori_reg_val, reg_val);
1207 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1211 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1215 struct i40e_adapter *ad = opaque;
1218 use_latest_vec = atoi(value);
1220 if (use_latest_vec != 0 && use_latest_vec != 1)
1221 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1223 ad->use_latest_vec = (uint8_t)use_latest_vec;
1229 i40e_use_latest_vec(struct rte_eth_dev *dev)
1231 struct i40e_adapter *ad =
1232 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1233 struct rte_kvargs *kvlist;
1236 ad->use_latest_vec = false;
1238 if (!dev->device->devargs)
1241 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1245 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1246 if (!kvargs_count) {
1247 rte_kvargs_free(kvlist);
1251 if (kvargs_count > 1)
1252 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1253 "the first invalid or last valid one is used !",
1254 ETH_I40E_USE_LATEST_VEC);
1256 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1257 i40e_parse_latest_vec_handler, ad) < 0) {
1258 rte_kvargs_free(kvlist);
1262 rte_kvargs_free(kvlist);
1267 read_vf_msg_config(__rte_unused const char *key,
1271 struct i40e_vf_msg_cfg *cfg = opaque;
1273 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1274 &cfg->ignore_second) != 3) {
1275 memset(cfg, 0, sizeof(*cfg));
1276 PMD_DRV_LOG(ERR, "format error! example: "
1277 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1282 * If the message validation function been enabled, the 'period'
1283 * and 'ignore_second' must greater than 0.
1285 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1286 memset(cfg, 0, sizeof(*cfg));
1287 PMD_DRV_LOG(ERR, "%s error! the second and third"
1288 " number must be greater than 0!",
1289 ETH_I40E_VF_MSG_CFG);
1297 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1298 struct i40e_vf_msg_cfg *msg_cfg)
1300 struct rte_kvargs *kvlist;
1304 memset(msg_cfg, 0, sizeof(*msg_cfg));
1306 if (!dev->device->devargs)
1309 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1313 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1317 if (kvargs_count > 1) {
1318 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1319 ETH_I40E_VF_MSG_CFG);
1324 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1325 read_vf_msg_config, msg_cfg) < 0)
1329 rte_kvargs_free(kvlist);
1333 #define I40E_ALARM_INTERVAL 50000 /* us */
1336 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1338 struct rte_pci_device *pci_dev;
1339 struct rte_intr_handle *intr_handle;
1340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct i40e_vsi *vsi;
1345 uint8_t aq_fail = 0;
1347 PMD_INIT_FUNC_TRACE();
1349 dev->dev_ops = &i40e_eth_dev_ops;
1350 dev->rx_pkt_burst = i40e_recv_pkts;
1351 dev->tx_pkt_burst = i40e_xmit_pkts;
1352 dev->tx_pkt_prepare = i40e_prep_pkts;
1354 /* for secondary processes, we don't initialise any further as primary
1355 * has already done this work. Only check we don't need a different
1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1358 i40e_set_rx_function(dev);
1359 i40e_set_tx_function(dev);
1362 i40e_set_default_ptype_table(dev);
1363 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1364 intr_handle = &pci_dev->intr_handle;
1366 rte_eth_copy_pci_info(dev, pci_dev);
1368 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1369 pf->adapter->eth_dev = dev;
1370 pf->dev_data = dev->data;
1372 hw->back = I40E_PF_TO_ADAPTER(pf);
1373 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1376 "Hardware is not available, as address is NULL");
1380 hw->vendor_id = pci_dev->id.vendor_id;
1381 hw->device_id = pci_dev->id.device_id;
1382 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1383 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1384 hw->bus.device = pci_dev->addr.devid;
1385 hw->bus.func = pci_dev->addr.function;
1386 hw->adapter_stopped = 0;
1387 hw->adapter_closed = 0;
1389 /* Init switch device pointer */
1390 hw->switch_dev = NULL;
1393 * Switch Tag value should not be identical to either the First Tag
1394 * or Second Tag values. So set something other than common Ethertype
1395 * for internal switching.
1397 hw->switch_tag = 0xffff;
1399 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1400 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1401 PMD_INIT_LOG(ERR, "\nERROR: "
1402 "Firmware recovery mode detected. Limiting functionality.\n"
1403 "Refer to the Intel(R) Ethernet Adapters and Devices "
1404 "User Guide for details on firmware recovery mode.");
1408 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1409 /* Check if need to support multi-driver */
1410 i40e_support_multi_driver(dev);
1411 /* Check if users want the latest supported vec path */
1412 i40e_use_latest_vec(dev);
1414 /* Make sure all is clean before doing PF reset */
1417 /* Reset here to make sure all is clean for each PF */
1418 ret = i40e_pf_reset(hw);
1420 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1424 /* Initialize the shared code (base driver) */
1425 ret = i40e_init_shared_code(hw);
1427 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1431 /* Initialize the parameters for adminq */
1432 i40e_init_adminq_parameter(hw);
1433 ret = i40e_init_adminq(hw);
1434 if (ret != I40E_SUCCESS) {
1435 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1438 /* Firmware of SFP x722 does not support adminq option */
1439 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1440 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1442 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1443 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1444 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1445 ((hw->nvm.version >> 12) & 0xf),
1446 ((hw->nvm.version >> 4) & 0xff),
1447 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1449 /* Initialize the hardware */
1452 i40e_config_automask(pf);
1454 i40e_set_default_pctype_table(dev);
1457 * To work around the NVM issue, initialize registers
1458 * for packet type of QinQ by software.
1459 * It should be removed once issues are fixed in NVM.
1461 if (!pf->support_multi_driver)
1462 i40e_GLQF_reg_init(hw);
1464 /* Initialize the input set for filters (hash and fd) to default value */
1465 i40e_filter_input_set_init(pf);
1467 /* initialise the L3_MAP register */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_aq_debug_write_global_register(hw,
1470 I40E_GLQF_L3_MAP(40),
1473 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1476 "Global register 0x%08x is changed with 0x28",
1477 I40E_GLQF_L3_MAP(40));
1480 /* Need the special FW version to support floating VEB */
1481 config_floating_veb(dev);
1482 /* Clear PXE mode */
1483 i40e_clear_pxe_mode(hw);
1484 i40e_dev_sync_phy_type(hw);
1487 * On X710, performance number is far from the expectation on recent
1488 * firmware versions. The fix for this issue may not be integrated in
1489 * the following firmware version. So the workaround in software driver
1490 * is needed. It needs to modify the initial values of 3 internal only
1491 * registers. Note that the workaround can be removed when it is fixed
1492 * in firmware in the future.
1494 i40e_configure_registers(hw);
1496 /* Get hw capabilities */
1497 ret = i40e_get_cap(hw);
1498 if (ret != I40E_SUCCESS) {
1499 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1500 goto err_get_capabilities;
1503 /* Initialize parameters for PF */
1504 ret = i40e_pf_parameter_init(dev);
1506 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1507 goto err_parameter_init;
1510 /* Initialize the queue management */
1511 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1513 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1514 goto err_qp_pool_init;
1516 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1517 hw->func_caps.num_msix_vectors - 1);
1519 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1520 goto err_msix_pool_init;
1523 /* Initialize lan hmc */
1524 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1525 hw->func_caps.num_rx_qp, 0, 0);
1526 if (ret != I40E_SUCCESS) {
1527 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1528 goto err_init_lan_hmc;
1531 /* Configure lan hmc */
1532 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1533 if (ret != I40E_SUCCESS) {
1534 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1535 goto err_configure_lan_hmc;
1538 /* Get and check the mac address */
1539 i40e_get_mac_addr(hw, hw->mac.addr);
1540 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1541 PMD_INIT_LOG(ERR, "mac address is not valid");
1543 goto err_get_mac_addr;
1545 /* Copy the permanent MAC address */
1546 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1547 (struct rte_ether_addr *)hw->mac.perm_addr);
1549 /* Disable flow control */
1550 hw->fc.requested_mode = I40E_FC_NONE;
1551 i40e_set_fc(hw, &aq_fail, TRUE);
1553 /* Set the global registers with default ether type value */
1554 if (!pf->support_multi_driver) {
1555 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1556 RTE_ETHER_TYPE_VLAN);
1557 if (ret != I40E_SUCCESS) {
1559 "Failed to set the default outer "
1561 goto err_setup_pf_switch;
1565 /* PF setup, which includes VSI setup */
1566 ret = i40e_pf_setup(pf);
1568 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1569 goto err_setup_pf_switch;
1574 /* Disable double vlan by default */
1575 i40e_vsi_config_double_vlan(vsi, FALSE);
1577 /* Disable S-TAG identification when floating_veb is disabled */
1578 if (!pf->floating_veb) {
1579 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1580 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1581 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1582 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1586 if (!vsi->max_macaddrs)
1587 len = RTE_ETHER_ADDR_LEN;
1589 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1591 /* Should be after VSI initialized */
1592 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1593 if (!dev->data->mac_addrs) {
1595 "Failed to allocated memory for storing mac address");
1598 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1599 &dev->data->mac_addrs[0]);
1601 /* Pass the information to the rte_eth_dev_close() that it should also
1602 * release the private port resources.
1604 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1606 /* Init dcb to sw mode by default */
1607 ret = i40e_dcb_init_configure(dev, TRUE);
1608 if (ret != I40E_SUCCESS) {
1609 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1610 pf->flags &= ~I40E_FLAG_DCB;
1612 /* Update HW struct after DCB configuration */
1615 /* initialize pf host driver to setup SRIOV resource if applicable */
1616 i40e_pf_host_init(dev);
1618 /* register callback func to eal lib */
1619 rte_intr_callback_register(intr_handle,
1620 i40e_dev_interrupt_handler, dev);
1622 /* configure and enable device interrupt */
1623 i40e_pf_config_irq0(hw, TRUE);
1624 i40e_pf_enable_irq0(hw);
1626 /* enable uio intr after callback register */
1627 rte_intr_enable(intr_handle);
1629 /* By default disable flexible payload in global configuration */
1630 if (!pf->support_multi_driver)
1631 i40e_flex_payload_reg_set_default(hw);
1634 * Add an ethertype filter to drop all flow control frames transmitted
1635 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1638 i40e_add_tx_flow_control_drop_filter(pf);
1640 /* Set the max frame size to 0x2600 by default,
1641 * in case other drivers changed the default value.
1643 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1645 /* initialize mirror rule list */
1646 TAILQ_INIT(&pf->mirror_list);
1648 /* initialize RSS rule list */
1649 TAILQ_INIT(&pf->rss_config_list);
1651 /* initialize Traffic Manager configuration */
1652 i40e_tm_conf_init(dev);
1654 /* Initialize customized information */
1655 i40e_init_customized_info(pf);
1657 ret = i40e_init_ethtype_filter_list(dev);
1659 goto err_init_ethtype_filter_list;
1660 ret = i40e_init_tunnel_filter_list(dev);
1662 goto err_init_tunnel_filter_list;
1663 ret = i40e_init_fdir_filter_list(dev);
1665 goto err_init_fdir_filter_list;
1667 /* initialize queue region configuration */
1668 i40e_init_queue_region_conf(dev);
1670 /* initialize RSS configuration from rte_flow */
1671 memset(&pf->rss_info, 0,
1672 sizeof(struct i40e_rte_flow_rss_conf));
1674 /* reset all stats of the device, including pf and main vsi */
1675 i40e_dev_stats_reset(dev);
1679 err_init_fdir_filter_list:
1680 rte_free(pf->tunnel.hash_table);
1681 rte_free(pf->tunnel.hash_map);
1682 err_init_tunnel_filter_list:
1683 rte_free(pf->ethertype.hash_table);
1684 rte_free(pf->ethertype.hash_map);
1685 err_init_ethtype_filter_list:
1686 rte_free(dev->data->mac_addrs);
1687 dev->data->mac_addrs = NULL;
1689 i40e_vsi_release(pf->main_vsi);
1690 err_setup_pf_switch:
1692 err_configure_lan_hmc:
1693 (void)i40e_shutdown_lan_hmc(hw);
1695 i40e_res_pool_destroy(&pf->msix_pool);
1697 i40e_res_pool_destroy(&pf->qp_pool);
1700 err_get_capabilities:
1701 (void)i40e_shutdown_adminq(hw);
1707 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1709 struct i40e_ethertype_filter *p_ethertype;
1710 struct i40e_ethertype_rule *ethertype_rule;
1712 ethertype_rule = &pf->ethertype;
1713 /* Remove all ethertype filter rules and hash */
1714 if (ethertype_rule->hash_map)
1715 rte_free(ethertype_rule->hash_map);
1716 if (ethertype_rule->hash_table)
1717 rte_hash_free(ethertype_rule->hash_table);
1719 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1720 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1721 p_ethertype, rules);
1722 rte_free(p_ethertype);
1727 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1729 struct i40e_tunnel_filter *p_tunnel;
1730 struct i40e_tunnel_rule *tunnel_rule;
1732 tunnel_rule = &pf->tunnel;
1733 /* Remove all tunnel director rules and hash */
1734 if (tunnel_rule->hash_map)
1735 rte_free(tunnel_rule->hash_map);
1736 if (tunnel_rule->hash_table)
1737 rte_hash_free(tunnel_rule->hash_table);
1739 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1740 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1746 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1748 struct i40e_fdir_filter *p_fdir;
1749 struct i40e_fdir_info *fdir_info;
1751 fdir_info = &pf->fdir;
1752 /* Remove all flow director rules and hash */
1753 if (fdir_info->hash_map)
1754 rte_free(fdir_info->hash_map);
1755 if (fdir_info->hash_table)
1756 rte_hash_free(fdir_info->hash_table);
1758 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1759 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1764 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1767 * Disable by default flexible payload
1768 * for corresponding L2/L3/L4 layers.
1770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1771 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1772 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1776 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1780 PMD_INIT_FUNC_TRACE();
1782 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1785 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787 if (hw->adapter_closed == 0)
1788 i40e_dev_close(dev);
1794 i40e_dev_configure(struct rte_eth_dev *dev)
1796 struct i40e_adapter *ad =
1797 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1803 ret = i40e_dev_sync_phy_type(hw);
1807 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1808 * bulk allocation or vector Rx preconditions we will reset it.
1810 ad->rx_bulk_alloc_allowed = true;
1811 ad->rx_vec_allowed = true;
1812 ad->tx_simple_allowed = true;
1813 ad->tx_vec_allowed = true;
1815 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1816 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1818 /* Only legacy filter API needs the following fdir config. So when the
1819 * legacy filter API is deprecated, the following codes should also be
1822 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1823 ret = i40e_fdir_setup(pf);
1824 if (ret != I40E_SUCCESS) {
1825 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1828 ret = i40e_fdir_configure(dev);
1830 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1834 i40e_fdir_teardown(pf);
1836 ret = i40e_dev_init_vlan(dev);
1841 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1842 * RSS setting have different requirements.
1843 * General PMD driver call sequence are NIC init, configure,
1844 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1845 * will try to lookup the VSI that specific queue belongs to if VMDQ
1846 * applicable. So, VMDQ setting has to be done before
1847 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1848 * For RSS setting, it will try to calculate actual configured RX queue
1849 * number, which will be available after rx_queue_setup(). dev_start()
1850 * function is good to place RSS setup.
1852 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1853 ret = i40e_vmdq_setup(dev);
1858 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1859 ret = i40e_dcb_setup(dev);
1861 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1866 TAILQ_INIT(&pf->flow_list);
1871 /* need to release vmdq resource if exists */
1872 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1873 i40e_vsi_release(pf->vmdq[i].vsi);
1874 pf->vmdq[i].vsi = NULL;
1879 /* Need to release fdir resource if exists.
1880 * Only legacy filter API needs the following fdir config. So when the
1881 * legacy filter API is deprecated, the following code should also be
1884 i40e_fdir_teardown(pf);
1889 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1891 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1892 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1893 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1894 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1895 uint16_t msix_vect = vsi->msix_intr;
1898 for (i = 0; i < vsi->nb_qps; i++) {
1899 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1900 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1904 if (vsi->type != I40E_VSI_SRIOV) {
1905 if (!rte_intr_allow_others(intr_handle)) {
1906 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1907 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1909 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1912 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1913 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1915 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1920 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1921 vsi->user_param + (msix_vect - 1);
1923 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1924 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1926 I40E_WRITE_FLUSH(hw);
1930 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1931 int base_queue, int nb_queue,
1936 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1937 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1939 /* Bind all RX queues to allocated MSIX interrupt */
1940 for (i = 0; i < nb_queue; i++) {
1941 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1942 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1943 ((base_queue + i + 1) <<
1944 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1945 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1946 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1948 if (i == nb_queue - 1)
1949 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1950 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1953 /* Write first RX queue to Link list register as the head element */
1954 if (vsi->type != I40E_VSI_SRIOV) {
1956 i40e_calc_itr_interval(1, pf->support_multi_driver);
1958 if (msix_vect == I40E_MISC_VEC_ID) {
1959 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1961 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1963 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1965 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1968 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1970 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1972 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1974 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1981 if (msix_vect == I40E_MISC_VEC_ID) {
1983 I40E_VPINT_LNKLST0(vsi->user_param),
1985 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1987 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1989 /* num_msix_vectors_vf needs to minus irq0 */
1990 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1991 vsi->user_param + (msix_vect - 1);
1993 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1995 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1997 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2001 I40E_WRITE_FLUSH(hw);
2005 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2012 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2013 uint16_t queue_idx = 0;
2017 for (i = 0; i < vsi->nb_qps; i++) {
2018 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2019 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2022 /* VF bind interrupt */
2023 if (vsi->type == I40E_VSI_SRIOV) {
2024 __vsi_queues_bind_intr(vsi, msix_vect,
2025 vsi->base_queue, vsi->nb_qps,
2030 /* PF & VMDq bind interrupt */
2031 if (rte_intr_dp_is_en(intr_handle)) {
2032 if (vsi->type == I40E_VSI_MAIN) {
2035 } else if (vsi->type == I40E_VSI_VMDQ2) {
2036 struct i40e_vsi *main_vsi =
2037 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2038 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2043 for (i = 0; i < vsi->nb_used_qps; i++) {
2045 if (!rte_intr_allow_others(intr_handle))
2046 /* allow to share MISC_VEC_ID */
2047 msix_vect = I40E_MISC_VEC_ID;
2049 /* no enough msix_vect, map all to one */
2050 __vsi_queues_bind_intr(vsi, msix_vect,
2051 vsi->base_queue + i,
2052 vsi->nb_used_qps - i,
2054 for (; !!record && i < vsi->nb_used_qps; i++)
2055 intr_handle->intr_vec[queue_idx + i] =
2059 /* 1:1 queue/msix_vect mapping */
2060 __vsi_queues_bind_intr(vsi, msix_vect,
2061 vsi->base_queue + i, 1,
2064 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2072 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2074 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2077 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2078 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2079 uint16_t msix_intr, i;
2081 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2082 for (i = 0; i < vsi->nb_msix; i++) {
2083 msix_intr = vsi->msix_intr + i;
2084 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2085 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2086 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2087 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2090 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2091 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2092 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2093 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2095 I40E_WRITE_FLUSH(hw);
2099 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2101 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2102 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2103 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2105 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2106 uint16_t msix_intr, i;
2108 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2109 for (i = 0; i < vsi->nb_msix; i++) {
2110 msix_intr = vsi->msix_intr + i;
2111 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2112 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2115 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2116 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2118 I40E_WRITE_FLUSH(hw);
2121 static inline uint8_t
2122 i40e_parse_link_speeds(uint16_t link_speeds)
2124 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2126 if (link_speeds & ETH_LINK_SPEED_40G)
2127 link_speed |= I40E_LINK_SPEED_40GB;
2128 if (link_speeds & ETH_LINK_SPEED_25G)
2129 link_speed |= I40E_LINK_SPEED_25GB;
2130 if (link_speeds & ETH_LINK_SPEED_20G)
2131 link_speed |= I40E_LINK_SPEED_20GB;
2132 if (link_speeds & ETH_LINK_SPEED_10G)
2133 link_speed |= I40E_LINK_SPEED_10GB;
2134 if (link_speeds & ETH_LINK_SPEED_1G)
2135 link_speed |= I40E_LINK_SPEED_1GB;
2136 if (link_speeds & ETH_LINK_SPEED_100M)
2137 link_speed |= I40E_LINK_SPEED_100MB;
2143 i40e_phy_conf_link(struct i40e_hw *hw,
2145 uint8_t force_speed,
2148 enum i40e_status_code status;
2149 struct i40e_aq_get_phy_abilities_resp phy_ab;
2150 struct i40e_aq_set_phy_config phy_conf;
2151 enum i40e_aq_phy_type cnt;
2152 uint8_t avail_speed;
2153 uint32_t phy_type_mask = 0;
2155 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2156 I40E_AQ_PHY_FLAG_PAUSE_RX |
2157 I40E_AQ_PHY_FLAG_PAUSE_RX |
2158 I40E_AQ_PHY_FLAG_LOW_POWER;
2161 /* To get phy capabilities of available speeds. */
2162 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2165 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2169 avail_speed = phy_ab.link_speed;
2171 /* To get the current phy config. */
2172 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2175 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2180 /* If link needs to go up and it is in autoneg mode the speed is OK,
2181 * no need to set up again.
2183 if (is_up && phy_ab.phy_type != 0 &&
2184 abilities & I40E_AQ_PHY_AN_ENABLED &&
2185 phy_ab.link_speed != 0)
2186 return I40E_SUCCESS;
2188 memset(&phy_conf, 0, sizeof(phy_conf));
2190 /* bits 0-2 use the values from get_phy_abilities_resp */
2192 abilities |= phy_ab.abilities & mask;
2194 phy_conf.abilities = abilities;
2196 /* If link needs to go up, but the force speed is not supported,
2197 * Warn users and config the default available speeds.
2199 if (is_up && !(force_speed & avail_speed)) {
2200 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2201 phy_conf.link_speed = avail_speed;
2203 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2206 /* PHY type mask needs to include each type except PHY type extension */
2207 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2208 phy_type_mask |= 1 << cnt;
2210 /* use get_phy_abilities_resp value for the rest */
2211 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2212 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2213 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2214 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2215 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2216 phy_conf.eee_capability = phy_ab.eee_capability;
2217 phy_conf.eeer = phy_ab.eeer_val;
2218 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2220 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2221 phy_ab.abilities, phy_ab.link_speed);
2222 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2223 phy_conf.abilities, phy_conf.link_speed);
2225 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2229 return I40E_SUCCESS;
2233 i40e_apply_link_speed(struct rte_eth_dev *dev)
2236 uint8_t abilities = 0;
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct rte_eth_conf *conf = &dev->data->dev_conf;
2240 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2241 I40E_AQ_PHY_LINK_ENABLED;
2243 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2244 conf->link_speeds = ETH_LINK_SPEED_40G |
2245 ETH_LINK_SPEED_25G |
2246 ETH_LINK_SPEED_20G |
2247 ETH_LINK_SPEED_10G |
2249 ETH_LINK_SPEED_100M;
2251 abilities |= I40E_AQ_PHY_AN_ENABLED;
2253 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2255 speed = i40e_parse_link_speeds(conf->link_speeds);
2257 return i40e_phy_conf_link(hw, abilities, speed, true);
2261 i40e_dev_start(struct rte_eth_dev *dev)
2263 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2264 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265 struct i40e_vsi *main_vsi = pf->main_vsi;
2267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2268 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2269 uint32_t intr_vector = 0;
2270 struct i40e_vsi *vsi;
2271 uint16_t nb_rxq, nb_txq;
2273 hw->adapter_stopped = 0;
2275 rte_intr_disable(intr_handle);
2277 if ((rte_intr_cap_multiple(intr_handle) ||
2278 !RTE_ETH_DEV_SRIOV(dev).active) &&
2279 dev->data->dev_conf.intr_conf.rxq != 0) {
2280 intr_vector = dev->data->nb_rx_queues;
2281 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2286 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2287 intr_handle->intr_vec =
2288 rte_zmalloc("intr_vec",
2289 dev->data->nb_rx_queues * sizeof(int),
2291 if (!intr_handle->intr_vec) {
2293 "Failed to allocate %d rx_queues intr_vec",
2294 dev->data->nb_rx_queues);
2299 /* Initialize VSI */
2300 ret = i40e_dev_rxtx_init(pf);
2301 if (ret != I40E_SUCCESS) {
2302 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2306 /* Map queues with MSIX interrupt */
2307 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2308 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2309 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2310 i40e_vsi_enable_queues_intr(main_vsi);
2312 /* Map VMDQ VSI queues with MSIX interrupt */
2313 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2314 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2315 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2316 I40E_ITR_INDEX_DEFAULT);
2317 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2320 /* enable FDIR MSIX interrupt */
2321 if (pf->fdir.fdir_vsi) {
2322 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2323 I40E_ITR_INDEX_NONE);
2324 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2327 /* Enable all queues which have been configured */
2328 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2329 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2334 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2335 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2340 /* Enable receiving broadcast packets */
2341 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2342 if (ret != I40E_SUCCESS)
2343 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2345 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2346 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2348 if (ret != I40E_SUCCESS)
2349 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2352 /* Enable the VLAN promiscuous mode. */
2354 for (i = 0; i < pf->vf_num; i++) {
2355 vsi = pf->vfs[i].vsi;
2356 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2361 /* Enable mac loopback mode */
2362 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2363 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2364 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2365 if (ret != I40E_SUCCESS) {
2366 PMD_DRV_LOG(ERR, "fail to set loopback link");
2371 /* Apply link configure */
2372 ret = i40e_apply_link_speed(dev);
2373 if (I40E_SUCCESS != ret) {
2374 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2378 if (!rte_intr_allow_others(intr_handle)) {
2379 rte_intr_callback_unregister(intr_handle,
2380 i40e_dev_interrupt_handler,
2382 /* configure and enable device interrupt */
2383 i40e_pf_config_irq0(hw, FALSE);
2384 i40e_pf_enable_irq0(hw);
2386 if (dev->data->dev_conf.intr_conf.lsc != 0)
2388 "lsc won't enable because of no intr multiplex");
2390 ret = i40e_aq_set_phy_int_mask(hw,
2391 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2392 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2393 I40E_AQ_EVENT_MEDIA_NA), NULL);
2394 if (ret != I40E_SUCCESS)
2395 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2397 /* Call get_link_info aq commond to enable/disable LSE */
2398 i40e_dev_link_update(dev, 0);
2401 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2402 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2403 i40e_dev_alarm_handler, dev);
2405 /* enable uio intr after callback register */
2406 rte_intr_enable(intr_handle);
2409 i40e_filter_restore(pf);
2411 if (pf->tm_conf.root && !pf->tm_conf.committed)
2412 PMD_DRV_LOG(WARNING,
2413 "please call hierarchy_commit() "
2414 "before starting the port");
2416 return I40E_SUCCESS;
2419 for (i = 0; i < nb_txq; i++)
2420 i40e_dev_tx_queue_stop(dev, i);
2422 for (i = 0; i < nb_rxq; i++)
2423 i40e_dev_rx_queue_stop(dev, i);
2429 i40e_dev_stop(struct rte_eth_dev *dev)
2431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 struct i40e_vsi *main_vsi = pf->main_vsi;
2434 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2435 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2438 if (hw->adapter_stopped == 1)
2441 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2442 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2443 rte_intr_enable(intr_handle);
2446 /* Disable all queues */
2447 for (i = 0; i < dev->data->nb_tx_queues; i++)
2448 i40e_dev_tx_queue_stop(dev, i);
2450 for (i = 0; i < dev->data->nb_rx_queues; i++)
2451 i40e_dev_rx_queue_stop(dev, i);
2453 /* un-map queues with interrupt registers */
2454 i40e_vsi_disable_queues_intr(main_vsi);
2455 i40e_vsi_queues_unbind_intr(main_vsi);
2457 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2458 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2459 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2462 if (pf->fdir.fdir_vsi) {
2463 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2464 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2466 /* Clear all queues and release memory */
2467 i40e_dev_clear_queues(dev);
2470 i40e_dev_set_link_down(dev);
2472 if (!rte_intr_allow_others(intr_handle))
2473 /* resume to the default handler */
2474 rte_intr_callback_register(intr_handle,
2475 i40e_dev_interrupt_handler,
2478 /* Clean datapath event and queue/vec mapping */
2479 rte_intr_efd_disable(intr_handle);
2480 if (intr_handle->intr_vec) {
2481 rte_free(intr_handle->intr_vec);
2482 intr_handle->intr_vec = NULL;
2485 /* reset hierarchy commit */
2486 pf->tm_conf.committed = false;
2488 hw->adapter_stopped = 1;
2490 pf->adapter->rss_reta_updated = 0;
2494 i40e_dev_close(struct rte_eth_dev *dev)
2496 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2499 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2500 struct i40e_mirror_rule *p_mirror;
2501 struct i40e_filter_control_settings settings;
2502 struct rte_flow *p_flow;
2506 uint8_t aq_fail = 0;
2509 PMD_INIT_FUNC_TRACE();
2511 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2513 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2518 /* Remove all mirror rules */
2519 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2520 ret = i40e_aq_del_mirror_rule(hw,
2521 pf->main_vsi->veb->seid,
2522 p_mirror->rule_type,
2524 p_mirror->num_entries,
2527 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2528 "status = %d, aq_err = %d.", ret,
2529 hw->aq.asq_last_status);
2531 /* remove mirror software resource anyway */
2532 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2534 pf->nb_mirror_rule--;
2537 i40e_dev_free_queues(dev);
2539 /* Disable interrupt */
2540 i40e_pf_disable_irq0(hw);
2541 rte_intr_disable(intr_handle);
2544 * Only legacy filter API needs the following fdir config. So when the
2545 * legacy filter API is deprecated, the following code should also be
2548 i40e_fdir_teardown(pf);
2550 /* shutdown and destroy the HMC */
2551 i40e_shutdown_lan_hmc(hw);
2553 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2554 i40e_vsi_release(pf->vmdq[i].vsi);
2555 pf->vmdq[i].vsi = NULL;
2560 /* release all the existing VSIs and VEBs */
2561 i40e_vsi_release(pf->main_vsi);
2563 /* shutdown the adminq */
2564 i40e_aq_queue_shutdown(hw, true);
2565 i40e_shutdown_adminq(hw);
2567 i40e_res_pool_destroy(&pf->qp_pool);
2568 i40e_res_pool_destroy(&pf->msix_pool);
2570 /* Disable flexible payload in global configuration */
2571 if (!pf->support_multi_driver)
2572 i40e_flex_payload_reg_set_default(hw);
2574 /* force a PF reset to clean anything leftover */
2575 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2576 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2577 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2578 I40E_WRITE_FLUSH(hw);
2580 dev->dev_ops = NULL;
2581 dev->rx_pkt_burst = NULL;
2582 dev->tx_pkt_burst = NULL;
2584 /* Clear PXE mode */
2585 i40e_clear_pxe_mode(hw);
2587 /* Unconfigure filter control */
2588 memset(&settings, 0, sizeof(settings));
2589 ret = i40e_set_filter_control(hw, &settings);
2591 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2594 /* Disable flow control */
2595 hw->fc.requested_mode = I40E_FC_NONE;
2596 i40e_set_fc(hw, &aq_fail, TRUE);
2598 /* uninitialize pf host driver */
2599 i40e_pf_host_uninit(dev);
2602 ret = rte_intr_callback_unregister(intr_handle,
2603 i40e_dev_interrupt_handler, dev);
2604 if (ret >= 0 || ret == -ENOENT) {
2606 } else if (ret != -EAGAIN) {
2608 "intr callback unregister failed: %d",
2611 i40e_msec_delay(500);
2612 } while (retries++ < 5);
2614 i40e_rm_ethtype_filter_list(pf);
2615 i40e_rm_tunnel_filter_list(pf);
2616 i40e_rm_fdir_filter_list(pf);
2618 /* Remove all flows */
2619 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2620 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2624 /* Remove all Traffic Manager configuration */
2625 i40e_tm_conf_uninit(dev);
2627 hw->adapter_closed = 1;
2631 * Reset PF device only to re-initialize resources in PMD layer
2634 i40e_dev_reset(struct rte_eth_dev *dev)
2638 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2639 * its VF to make them align with it. The detailed notification
2640 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2641 * To avoid unexpected behavior in VF, currently reset of PF with
2642 * SR-IOV activation is not supported. It might be supported later.
2644 if (dev->data->sriov.active)
2647 ret = eth_i40e_dev_uninit(dev);
2651 ret = eth_i40e_dev_init(dev, NULL);
2657 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2659 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 struct i40e_vsi *vsi = pf->main_vsi;
2664 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2666 if (status != I40E_SUCCESS) {
2667 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2671 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2673 if (status != I40E_SUCCESS) {
2674 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2675 /* Rollback unicast promiscuous mode */
2676 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2685 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 struct i40e_vsi *vsi = pf->main_vsi;
2692 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2694 if (status != I40E_SUCCESS) {
2695 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2699 /* must remain in all_multicast mode */
2700 if (dev->data->all_multicast == 1)
2703 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2705 if (status != I40E_SUCCESS) {
2706 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2707 /* Rollback unicast promiscuous mode */
2708 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2717 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721 struct i40e_vsi *vsi = pf->main_vsi;
2724 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2725 if (ret != I40E_SUCCESS) {
2726 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2734 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 struct i40e_vsi *vsi = pf->main_vsi;
2741 if (dev->data->promiscuous == 1)
2742 return 0; /* must remain in all_multicast mode */
2744 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2745 vsi->seid, FALSE, NULL);
2746 if (ret != I40E_SUCCESS) {
2747 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2755 * Set device link up.
2758 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2760 /* re-apply link speed setting */
2761 return i40e_apply_link_speed(dev);
2765 * Set device link down.
2768 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2770 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2771 uint8_t abilities = 0;
2772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2775 return i40e_phy_conf_link(hw, abilities, speed, false);
2778 static __rte_always_inline void
2779 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2781 /* Link status registers and values*/
2782 #define I40E_PRTMAC_LINKSTA 0x001E2420
2783 #define I40E_REG_LINK_UP 0x40000080
2784 #define I40E_PRTMAC_MACC 0x001E24E0
2785 #define I40E_REG_MACC_25GB 0x00020000
2786 #define I40E_REG_SPEED_MASK 0x38000000
2787 #define I40E_REG_SPEED_0 0x00000000
2788 #define I40E_REG_SPEED_1 0x08000000
2789 #define I40E_REG_SPEED_2 0x10000000
2790 #define I40E_REG_SPEED_3 0x18000000
2791 #define I40E_REG_SPEED_4 0x20000000
2792 uint32_t link_speed;
2795 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2796 link_speed = reg_val & I40E_REG_SPEED_MASK;
2797 reg_val &= I40E_REG_LINK_UP;
2798 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2800 if (unlikely(link->link_status == 0))
2803 /* Parse the link status */
2804 switch (link_speed) {
2805 case I40E_REG_SPEED_0:
2806 link->link_speed = ETH_SPEED_NUM_100M;
2808 case I40E_REG_SPEED_1:
2809 link->link_speed = ETH_SPEED_NUM_1G;
2811 case I40E_REG_SPEED_2:
2812 if (hw->mac.type == I40E_MAC_X722)
2813 link->link_speed = ETH_SPEED_NUM_2_5G;
2815 link->link_speed = ETH_SPEED_NUM_10G;
2817 case I40E_REG_SPEED_3:
2818 if (hw->mac.type == I40E_MAC_X722) {
2819 link->link_speed = ETH_SPEED_NUM_5G;
2821 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2823 if (reg_val & I40E_REG_MACC_25GB)
2824 link->link_speed = ETH_SPEED_NUM_25G;
2826 link->link_speed = ETH_SPEED_NUM_40G;
2829 case I40E_REG_SPEED_4:
2830 if (hw->mac.type == I40E_MAC_X722)
2831 link->link_speed = ETH_SPEED_NUM_10G;
2833 link->link_speed = ETH_SPEED_NUM_20G;
2836 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2841 static __rte_always_inline void
2842 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2843 bool enable_lse, int wait_to_complete)
2845 #define CHECK_INTERVAL 100 /* 100ms */
2846 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2847 uint32_t rep_cnt = MAX_REPEAT_TIME;
2848 struct i40e_link_status link_status;
2851 memset(&link_status, 0, sizeof(link_status));
2854 memset(&link_status, 0, sizeof(link_status));
2856 /* Get link status information from hardware */
2857 status = i40e_aq_get_link_info(hw, enable_lse,
2858 &link_status, NULL);
2859 if (unlikely(status != I40E_SUCCESS)) {
2860 link->link_speed = ETH_SPEED_NUM_NONE;
2861 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2862 PMD_DRV_LOG(ERR, "Failed to get link info");
2866 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2867 if (!wait_to_complete || link->link_status)
2870 rte_delay_ms(CHECK_INTERVAL);
2871 } while (--rep_cnt);
2873 /* Parse the link status */
2874 switch (link_status.link_speed) {
2875 case I40E_LINK_SPEED_100MB:
2876 link->link_speed = ETH_SPEED_NUM_100M;
2878 case I40E_LINK_SPEED_1GB:
2879 link->link_speed = ETH_SPEED_NUM_1G;
2881 case I40E_LINK_SPEED_10GB:
2882 link->link_speed = ETH_SPEED_NUM_10G;
2884 case I40E_LINK_SPEED_20GB:
2885 link->link_speed = ETH_SPEED_NUM_20G;
2887 case I40E_LINK_SPEED_25GB:
2888 link->link_speed = ETH_SPEED_NUM_25G;
2890 case I40E_LINK_SPEED_40GB:
2891 link->link_speed = ETH_SPEED_NUM_40G;
2894 link->link_speed = ETH_SPEED_NUM_NONE;
2900 i40e_dev_link_update(struct rte_eth_dev *dev,
2901 int wait_to_complete)
2903 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904 struct rte_eth_link link;
2905 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2908 memset(&link, 0, sizeof(link));
2910 /* i40e uses full duplex only */
2911 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2912 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2913 ETH_LINK_SPEED_FIXED);
2915 if (!wait_to_complete && !enable_lse)
2916 update_link_reg(hw, &link);
2918 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2921 rte_eth_linkstatus_get(hw->switch_dev, &link);
2923 ret = rte_eth_linkstatus_set(dev, &link);
2924 i40e_notify_all_vfs_link_status(dev);
2929 /* Get all the statistics of a VSI */
2931 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2933 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2934 struct i40e_eth_stats *nes = &vsi->eth_stats;
2935 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2936 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2938 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2939 vsi->offset_loaded, &oes->rx_bytes,
2941 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2942 vsi->offset_loaded, &oes->rx_unicast,
2944 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2945 vsi->offset_loaded, &oes->rx_multicast,
2946 &nes->rx_multicast);
2947 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2948 vsi->offset_loaded, &oes->rx_broadcast,
2949 &nes->rx_broadcast);
2950 /* exclude CRC bytes */
2951 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2952 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2954 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2955 &oes->rx_discards, &nes->rx_discards);
2956 /* GLV_REPC not supported */
2957 /* GLV_RMPC not supported */
2958 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2959 &oes->rx_unknown_protocol,
2960 &nes->rx_unknown_protocol);
2961 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2962 vsi->offset_loaded, &oes->tx_bytes,
2964 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2965 vsi->offset_loaded, &oes->tx_unicast,
2967 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2968 vsi->offset_loaded, &oes->tx_multicast,
2969 &nes->tx_multicast);
2970 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2971 vsi->offset_loaded, &oes->tx_broadcast,
2972 &nes->tx_broadcast);
2973 /* GLV_TDPC not supported */
2974 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2975 &oes->tx_errors, &nes->tx_errors);
2976 vsi->offset_loaded = true;
2978 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2980 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2981 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2982 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2983 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2984 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2985 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2986 nes->rx_unknown_protocol);
2987 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2988 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2989 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2990 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2991 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2992 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2993 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2998 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3001 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3002 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3004 /* Get rx/tx bytes of internal transfer packets */
3005 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3006 I40E_GLV_GORCL(hw->port),
3008 &pf->internal_stats_offset.rx_bytes,
3009 &pf->internal_stats.rx_bytes);
3011 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3012 I40E_GLV_GOTCL(hw->port),
3014 &pf->internal_stats_offset.tx_bytes,
3015 &pf->internal_stats.tx_bytes);
3016 /* Get total internal rx packet count */
3017 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3018 I40E_GLV_UPRCL(hw->port),
3020 &pf->internal_stats_offset.rx_unicast,
3021 &pf->internal_stats.rx_unicast);
3022 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3023 I40E_GLV_MPRCL(hw->port),
3025 &pf->internal_stats_offset.rx_multicast,
3026 &pf->internal_stats.rx_multicast);
3027 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3028 I40E_GLV_BPRCL(hw->port),
3030 &pf->internal_stats_offset.rx_broadcast,
3031 &pf->internal_stats.rx_broadcast);
3032 /* Get total internal tx packet count */
3033 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3034 I40E_GLV_UPTCL(hw->port),
3036 &pf->internal_stats_offset.tx_unicast,
3037 &pf->internal_stats.tx_unicast);
3038 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3039 I40E_GLV_MPTCL(hw->port),
3041 &pf->internal_stats_offset.tx_multicast,
3042 &pf->internal_stats.tx_multicast);
3043 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3044 I40E_GLV_BPTCL(hw->port),
3046 &pf->internal_stats_offset.tx_broadcast,
3047 &pf->internal_stats.tx_broadcast);
3049 /* exclude CRC size */
3050 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3051 pf->internal_stats.rx_multicast +
3052 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3054 /* Get statistics of struct i40e_eth_stats */
3055 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3056 I40E_GLPRT_GORCL(hw->port),
3057 pf->offset_loaded, &os->eth.rx_bytes,
3059 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3060 I40E_GLPRT_UPRCL(hw->port),
3061 pf->offset_loaded, &os->eth.rx_unicast,
3062 &ns->eth.rx_unicast);
3063 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3064 I40E_GLPRT_MPRCL(hw->port),
3065 pf->offset_loaded, &os->eth.rx_multicast,
3066 &ns->eth.rx_multicast);
3067 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3068 I40E_GLPRT_BPRCL(hw->port),
3069 pf->offset_loaded, &os->eth.rx_broadcast,
3070 &ns->eth.rx_broadcast);
3071 /* Workaround: CRC size should not be included in byte statistics,
3072 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3075 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3076 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3078 /* exclude internal rx bytes
3079 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3080 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3082 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3084 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3085 ns->eth.rx_bytes = 0;
3087 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3089 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3090 ns->eth.rx_unicast = 0;
3092 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3094 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3095 ns->eth.rx_multicast = 0;
3097 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3099 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3100 ns->eth.rx_broadcast = 0;
3102 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3104 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3105 pf->offset_loaded, &os->eth.rx_discards,
3106 &ns->eth.rx_discards);
3107 /* GLPRT_REPC not supported */
3108 /* GLPRT_RMPC not supported */
3109 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3111 &os->eth.rx_unknown_protocol,
3112 &ns->eth.rx_unknown_protocol);
3113 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3114 I40E_GLPRT_GOTCL(hw->port),
3115 pf->offset_loaded, &os->eth.tx_bytes,
3117 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3118 I40E_GLPRT_UPTCL(hw->port),
3119 pf->offset_loaded, &os->eth.tx_unicast,
3120 &ns->eth.tx_unicast);
3121 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3122 I40E_GLPRT_MPTCL(hw->port),
3123 pf->offset_loaded, &os->eth.tx_multicast,
3124 &ns->eth.tx_multicast);
3125 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3126 I40E_GLPRT_BPTCL(hw->port),
3127 pf->offset_loaded, &os->eth.tx_broadcast,
3128 &ns->eth.tx_broadcast);
3129 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3130 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3132 /* exclude internal tx bytes
3133 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3134 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3136 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3138 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3139 ns->eth.tx_bytes = 0;
3141 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3143 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3144 ns->eth.tx_unicast = 0;
3146 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3148 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3149 ns->eth.tx_multicast = 0;
3151 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3153 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3154 ns->eth.tx_broadcast = 0;
3156 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3158 /* GLPRT_TEPC not supported */
3160 /* additional port specific stats */
3161 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3162 pf->offset_loaded, &os->tx_dropped_link_down,
3163 &ns->tx_dropped_link_down);
3164 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3165 pf->offset_loaded, &os->crc_errors,
3167 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3168 pf->offset_loaded, &os->illegal_bytes,
3169 &ns->illegal_bytes);
3170 /* GLPRT_ERRBC not supported */
3171 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3172 pf->offset_loaded, &os->mac_local_faults,
3173 &ns->mac_local_faults);
3174 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3175 pf->offset_loaded, &os->mac_remote_faults,
3176 &ns->mac_remote_faults);
3177 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3178 pf->offset_loaded, &os->rx_length_errors,
3179 &ns->rx_length_errors);
3180 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3181 pf->offset_loaded, &os->link_xon_rx,
3183 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3184 pf->offset_loaded, &os->link_xoff_rx,
3186 for (i = 0; i < 8; i++) {
3187 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3189 &os->priority_xon_rx[i],
3190 &ns->priority_xon_rx[i]);
3191 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3193 &os->priority_xoff_rx[i],
3194 &ns->priority_xoff_rx[i]);
3196 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3197 pf->offset_loaded, &os->link_xon_tx,
3199 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3200 pf->offset_loaded, &os->link_xoff_tx,
3202 for (i = 0; i < 8; i++) {
3203 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3205 &os->priority_xon_tx[i],
3206 &ns->priority_xon_tx[i]);
3207 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3209 &os->priority_xoff_tx[i],
3210 &ns->priority_xoff_tx[i]);
3211 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3213 &os->priority_xon_2_xoff[i],
3214 &ns->priority_xon_2_xoff[i]);
3216 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3217 I40E_GLPRT_PRC64L(hw->port),
3218 pf->offset_loaded, &os->rx_size_64,
3220 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3221 I40E_GLPRT_PRC127L(hw->port),
3222 pf->offset_loaded, &os->rx_size_127,
3224 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3225 I40E_GLPRT_PRC255L(hw->port),
3226 pf->offset_loaded, &os->rx_size_255,
3228 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3229 I40E_GLPRT_PRC511L(hw->port),
3230 pf->offset_loaded, &os->rx_size_511,
3232 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3233 I40E_GLPRT_PRC1023L(hw->port),
3234 pf->offset_loaded, &os->rx_size_1023,
3236 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3237 I40E_GLPRT_PRC1522L(hw->port),
3238 pf->offset_loaded, &os->rx_size_1522,
3240 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3241 I40E_GLPRT_PRC9522L(hw->port),
3242 pf->offset_loaded, &os->rx_size_big,
3244 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3245 pf->offset_loaded, &os->rx_undersize,
3247 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3248 pf->offset_loaded, &os->rx_fragments,
3250 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3251 pf->offset_loaded, &os->rx_oversize,
3253 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3254 pf->offset_loaded, &os->rx_jabber,
3256 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3257 I40E_GLPRT_PTC64L(hw->port),
3258 pf->offset_loaded, &os->tx_size_64,
3260 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3261 I40E_GLPRT_PTC127L(hw->port),
3262 pf->offset_loaded, &os->tx_size_127,
3264 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3265 I40E_GLPRT_PTC255L(hw->port),
3266 pf->offset_loaded, &os->tx_size_255,
3268 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3269 I40E_GLPRT_PTC511L(hw->port),
3270 pf->offset_loaded, &os->tx_size_511,
3272 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3273 I40E_GLPRT_PTC1023L(hw->port),
3274 pf->offset_loaded, &os->tx_size_1023,
3276 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3277 I40E_GLPRT_PTC1522L(hw->port),
3278 pf->offset_loaded, &os->tx_size_1522,
3280 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3281 I40E_GLPRT_PTC9522L(hw->port),
3282 pf->offset_loaded, &os->tx_size_big,
3284 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3286 &os->fd_sb_match, &ns->fd_sb_match);
3287 /* GLPRT_MSPDC not supported */
3288 /* GLPRT_XEC not supported */
3290 pf->offset_loaded = true;
3293 i40e_update_vsi_stats(pf->main_vsi);
3296 /* Get all statistics of a port */
3298 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3303 struct i40e_vsi *vsi;
3306 /* call read registers - updates values, now write them to struct */
3307 i40e_read_stats_registers(pf, hw);
3309 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3310 pf->main_vsi->eth_stats.rx_multicast +
3311 pf->main_vsi->eth_stats.rx_broadcast -
3312 pf->main_vsi->eth_stats.rx_discards;
3313 stats->opackets = ns->eth.tx_unicast +
3314 ns->eth.tx_multicast +
3315 ns->eth.tx_broadcast;
3316 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3317 stats->obytes = ns->eth.tx_bytes;
3318 stats->oerrors = ns->eth.tx_errors +
3319 pf->main_vsi->eth_stats.tx_errors;
3322 stats->imissed = ns->eth.rx_discards +
3323 pf->main_vsi->eth_stats.rx_discards;
3324 stats->ierrors = ns->crc_errors +
3325 ns->rx_length_errors + ns->rx_undersize +
3326 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3329 for (i = 0; i < pf->vf_num; i++) {
3330 vsi = pf->vfs[i].vsi;
3331 i40e_update_vsi_stats(vsi);
3333 stats->ipackets += (vsi->eth_stats.rx_unicast +
3334 vsi->eth_stats.rx_multicast +
3335 vsi->eth_stats.rx_broadcast -
3336 vsi->eth_stats.rx_discards);
3337 stats->ibytes += vsi->eth_stats.rx_bytes;
3338 stats->oerrors += vsi->eth_stats.tx_errors;
3339 stats->imissed += vsi->eth_stats.rx_discards;
3343 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3344 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3345 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3346 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3347 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3348 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3349 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3350 ns->eth.rx_unknown_protocol);
3351 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3352 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3353 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3354 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3355 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3356 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3358 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3359 ns->tx_dropped_link_down);
3360 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3361 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3363 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3364 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3365 ns->mac_local_faults);
3366 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3367 ns->mac_remote_faults);
3368 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3369 ns->rx_length_errors);
3370 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3371 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3372 for (i = 0; i < 8; i++) {
3373 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3374 i, ns->priority_xon_rx[i]);
3375 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3376 i, ns->priority_xoff_rx[i]);
3378 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3379 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3380 for (i = 0; i < 8; i++) {
3381 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3382 i, ns->priority_xon_tx[i]);
3383 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3384 i, ns->priority_xoff_tx[i]);
3385 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3386 i, ns->priority_xon_2_xoff[i]);
3388 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3389 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3390 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3391 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3392 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3393 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3394 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3395 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3396 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3397 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3398 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3399 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3400 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3401 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3402 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3403 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3404 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3405 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3406 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3407 ns->mac_short_packet_dropped);
3408 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3409 ns->checksum_error);
3410 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3411 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3415 /* Reset the statistics */
3417 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 /* Mark PF and VSI stats to update the offset, aka "reset" */
3423 pf->offset_loaded = false;
3425 pf->main_vsi->offset_loaded = false;
3427 /* read the stats, reading current register values into offset */
3428 i40e_read_stats_registers(pf, hw);
3434 i40e_xstats_calc_num(void)
3436 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3437 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3438 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3441 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3442 struct rte_eth_xstat_name *xstats_names,
3443 __rte_unused unsigned limit)
3448 if (xstats_names == NULL)
3449 return i40e_xstats_calc_num();
3451 /* Note: limit checked in rte_eth_xstats_names() */
3453 /* Get stats from i40e_eth_stats struct */
3454 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3455 strlcpy(xstats_names[count].name,
3456 rte_i40e_stats_strings[i].name,
3457 sizeof(xstats_names[count].name));
3461 /* Get individiual stats from i40e_hw_port struct */
3462 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3463 strlcpy(xstats_names[count].name,
3464 rte_i40e_hw_port_strings[i].name,
3465 sizeof(xstats_names[count].name));
3469 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3470 for (prio = 0; prio < 8; prio++) {
3471 snprintf(xstats_names[count].name,
3472 sizeof(xstats_names[count].name),
3473 "rx_priority%u_%s", prio,
3474 rte_i40e_rxq_prio_strings[i].name);
3479 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3480 for (prio = 0; prio < 8; prio++) {
3481 snprintf(xstats_names[count].name,
3482 sizeof(xstats_names[count].name),
3483 "tx_priority%u_%s", prio,
3484 rte_i40e_txq_prio_strings[i].name);
3492 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497 unsigned i, count, prio;
3498 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3500 count = i40e_xstats_calc_num();
3504 i40e_read_stats_registers(pf, hw);
3511 /* Get stats from i40e_eth_stats struct */
3512 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3513 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3514 rte_i40e_stats_strings[i].offset);
3515 xstats[count].id = count;
3519 /* Get individiual stats from i40e_hw_port struct */
3520 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3521 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3522 rte_i40e_hw_port_strings[i].offset);
3523 xstats[count].id = count;
3527 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3528 for (prio = 0; prio < 8; prio++) {
3529 xstats[count].value =
3530 *(uint64_t *)(((char *)hw_stats) +
3531 rte_i40e_rxq_prio_strings[i].offset +
3532 (sizeof(uint64_t) * prio));
3533 xstats[count].id = count;
3538 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3539 for (prio = 0; prio < 8; prio++) {
3540 xstats[count].value =
3541 *(uint64_t *)(((char *)hw_stats) +
3542 rte_i40e_txq_prio_strings[i].offset +
3543 (sizeof(uint64_t) * prio));
3544 xstats[count].id = count;
3553 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561 full_ver = hw->nvm.oem_ver;
3562 ver = (u8)(full_ver >> 24);
3563 build = (u16)((full_ver >> 8) & 0xffff);
3564 patch = (u8)(full_ver & 0xff);
3566 ret = snprintf(fw_version, fw_size,
3567 "%d.%d%d 0x%08x %d.%d.%d",
3568 ((hw->nvm.version >> 12) & 0xf),
3569 ((hw->nvm.version >> 4) & 0xff),
3570 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3573 ret += 1; /* add the size of '\0' */
3574 if (fw_size < (u32)ret)
3581 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3582 * the Rx data path does not hang if the FW LLDP is stopped.
3583 * return true if lldp need to stop
3584 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3587 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3590 char ver_str[64] = {0};
3591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593 i40e_fw_version_get(dev, ver_str, 64);
3594 nvm_ver = atof(ver_str);
3595 if ((hw->mac.type == I40E_MAC_X722 ||
3596 hw->mac.type == I40E_MAC_X722_VF) &&
3597 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3599 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3606 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3608 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3609 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610 struct i40e_vsi *vsi = pf->main_vsi;
3611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3613 dev_info->max_rx_queues = vsi->nb_qps;
3614 dev_info->max_tx_queues = vsi->nb_qps;
3615 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3616 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3617 dev_info->max_mac_addrs = vsi->max_macaddrs;
3618 dev_info->max_vfs = pci_dev->max_vfs;
3619 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3620 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3621 dev_info->rx_queue_offload_capa = 0;
3622 dev_info->rx_offload_capa =
3623 DEV_RX_OFFLOAD_VLAN_STRIP |
3624 DEV_RX_OFFLOAD_QINQ_STRIP |
3625 DEV_RX_OFFLOAD_IPV4_CKSUM |
3626 DEV_RX_OFFLOAD_UDP_CKSUM |
3627 DEV_RX_OFFLOAD_TCP_CKSUM |
3628 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3629 DEV_RX_OFFLOAD_KEEP_CRC |
3630 DEV_RX_OFFLOAD_SCATTER |
3631 DEV_RX_OFFLOAD_VLAN_EXTEND |
3632 DEV_RX_OFFLOAD_VLAN_FILTER |
3633 DEV_RX_OFFLOAD_JUMBO_FRAME |
3634 DEV_RX_OFFLOAD_RSS_HASH;
3636 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3637 dev_info->tx_offload_capa =
3638 DEV_TX_OFFLOAD_VLAN_INSERT |
3639 DEV_TX_OFFLOAD_QINQ_INSERT |
3640 DEV_TX_OFFLOAD_IPV4_CKSUM |
3641 DEV_TX_OFFLOAD_UDP_CKSUM |
3642 DEV_TX_OFFLOAD_TCP_CKSUM |
3643 DEV_TX_OFFLOAD_SCTP_CKSUM |
3644 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3645 DEV_TX_OFFLOAD_TCP_TSO |
3646 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3647 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3648 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3649 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3650 DEV_TX_OFFLOAD_MULTI_SEGS |
3651 dev_info->tx_queue_offload_capa;
3652 dev_info->dev_capa =
3653 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3654 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3656 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3658 dev_info->reta_size = pf->hash_lut_size;
3659 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3661 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3663 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3664 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3665 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3667 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3672 dev_info->default_txconf = (struct rte_eth_txconf) {
3674 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3675 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3676 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3678 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3679 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3683 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3684 .nb_max = I40E_MAX_RING_DESC,
3685 .nb_min = I40E_MIN_RING_DESC,
3686 .nb_align = I40E_ALIGN_RING_DESC,
3689 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3690 .nb_max = I40E_MAX_RING_DESC,
3691 .nb_min = I40E_MIN_RING_DESC,
3692 .nb_align = I40E_ALIGN_RING_DESC,
3693 .nb_seg_max = I40E_TX_MAX_SEG,
3694 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3697 if (pf->flags & I40E_FLAG_VMDQ) {
3698 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3699 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3700 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3701 pf->max_nb_vmdq_vsi;
3702 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3703 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3704 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3707 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3709 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3710 dev_info->default_rxportconf.nb_queues = 2;
3711 dev_info->default_txportconf.nb_queues = 2;
3712 if (dev->data->nb_rx_queues == 1)
3713 dev_info->default_rxportconf.ring_size = 2048;
3715 dev_info->default_rxportconf.ring_size = 1024;
3716 if (dev->data->nb_tx_queues == 1)
3717 dev_info->default_txportconf.ring_size = 1024;
3719 dev_info->default_txportconf.ring_size = 512;
3721 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3723 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3724 dev_info->default_rxportconf.nb_queues = 1;
3725 dev_info->default_txportconf.nb_queues = 1;
3726 dev_info->default_rxportconf.ring_size = 256;
3727 dev_info->default_txportconf.ring_size = 256;
3730 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3731 dev_info->default_rxportconf.nb_queues = 1;
3732 dev_info->default_txportconf.nb_queues = 1;
3733 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3734 dev_info->default_rxportconf.ring_size = 512;
3735 dev_info->default_txportconf.ring_size = 256;
3737 dev_info->default_rxportconf.ring_size = 256;
3738 dev_info->default_txportconf.ring_size = 256;
3741 dev_info->default_rxportconf.burst_size = 32;
3742 dev_info->default_txportconf.burst_size = 32;
3748 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3751 struct i40e_vsi *vsi = pf->main_vsi;
3752 PMD_INIT_FUNC_TRACE();
3755 return i40e_vsi_add_vlan(vsi, vlan_id);
3757 return i40e_vsi_delete_vlan(vsi, vlan_id);
3761 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3762 enum rte_vlan_type vlan_type,
3763 uint16_t tpid, int qinq)
3765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768 uint16_t reg_id = 3;
3772 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3776 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3778 if (ret != I40E_SUCCESS) {
3780 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3785 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3788 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3789 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3790 if (reg_r == reg_w) {
3791 PMD_DRV_LOG(DEBUG, "No need to write");
3795 ret = i40e_aq_debug_write_global_register(hw,
3796 I40E_GL_SWT_L2TAGCTRL(reg_id),
3798 if (ret != I40E_SUCCESS) {
3800 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3805 "Global register 0x%08x is changed with value 0x%08x",
3806 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3812 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3813 enum rte_vlan_type vlan_type,
3816 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3818 int qinq = dev->data->dev_conf.rxmode.offloads &
3819 DEV_RX_OFFLOAD_VLAN_EXTEND;
3822 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3823 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3824 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3826 "Unsupported vlan type.");
3830 if (pf->support_multi_driver) {
3831 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3835 /* 802.1ad frames ability is added in NVM API 1.7*/
3836 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3838 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3839 hw->first_tag = rte_cpu_to_le_16(tpid);
3840 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3841 hw->second_tag = rte_cpu_to_le_16(tpid);
3843 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3844 hw->second_tag = rte_cpu_to_le_16(tpid);
3846 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3847 if (ret != I40E_SUCCESS) {
3849 "Set switch config failed aq_err: %d",
3850 hw->aq.asq_last_status);
3854 /* If NVM API < 1.7, keep the register setting */
3855 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3862 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3865 struct i40e_vsi *vsi = pf->main_vsi;
3866 struct rte_eth_rxmode *rxmode;
3868 rxmode = &dev->data->dev_conf.rxmode;
3869 if (mask & ETH_VLAN_FILTER_MASK) {
3870 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3871 i40e_vsi_config_vlan_filter(vsi, TRUE);
3873 i40e_vsi_config_vlan_filter(vsi, FALSE);
3876 if (mask & ETH_VLAN_STRIP_MASK) {
3877 /* Enable or disable VLAN stripping */
3878 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3879 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3881 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3884 if (mask & ETH_VLAN_EXTEND_MASK) {
3885 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3886 i40e_vsi_config_double_vlan(vsi, TRUE);
3887 /* Set global registers with default ethertype. */
3888 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3889 RTE_ETHER_TYPE_VLAN);
3890 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3891 RTE_ETHER_TYPE_VLAN);
3894 i40e_vsi_config_double_vlan(vsi, FALSE);
3901 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3902 __rte_unused uint16_t queue,
3903 __rte_unused int on)
3905 PMD_INIT_FUNC_TRACE();
3909 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3912 struct i40e_vsi *vsi = pf->main_vsi;
3913 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3914 struct i40e_vsi_vlan_pvid_info info;
3916 memset(&info, 0, sizeof(info));
3919 info.config.pvid = pvid;
3921 info.config.reject.tagged =
3922 data->dev_conf.txmode.hw_vlan_reject_tagged;
3923 info.config.reject.untagged =
3924 data->dev_conf.txmode.hw_vlan_reject_untagged;
3927 return i40e_vsi_vlan_pvid_set(vsi, &info);
3931 i40e_dev_led_on(struct rte_eth_dev *dev)
3933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934 uint32_t mode = i40e_led_get(hw);
3937 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3943 i40e_dev_led_off(struct rte_eth_dev *dev)
3945 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946 uint32_t mode = i40e_led_get(hw);
3949 i40e_led_set(hw, 0, false);
3955 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960 fc_conf->pause_time = pf->fc_conf.pause_time;
3962 /* read out from register, in case they are modified by other port */
3963 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3964 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3965 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3966 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3968 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3969 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3971 /* Return current mode according to actual setting*/
3972 switch (hw->fc.current_mode) {
3974 fc_conf->mode = RTE_FC_FULL;
3976 case I40E_FC_TX_PAUSE:
3977 fc_conf->mode = RTE_FC_TX_PAUSE;
3979 case I40E_FC_RX_PAUSE:
3980 fc_conf->mode = RTE_FC_RX_PAUSE;
3984 fc_conf->mode = RTE_FC_NONE;
3991 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3993 uint32_t mflcn_reg, fctrl_reg, reg;
3994 uint32_t max_high_water;
3995 uint8_t i, aq_failure;
3999 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4000 [RTE_FC_NONE] = I40E_FC_NONE,
4001 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4002 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4003 [RTE_FC_FULL] = I40E_FC_FULL
4006 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4008 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4009 if ((fc_conf->high_water > max_high_water) ||
4010 (fc_conf->high_water < fc_conf->low_water)) {
4012 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4017 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4019 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4021 pf->fc_conf.pause_time = fc_conf->pause_time;
4022 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4023 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4025 PMD_INIT_FUNC_TRACE();
4027 /* All the link flow control related enable/disable register
4028 * configuration is handle by the F/W
4030 err = i40e_set_fc(hw, &aq_failure, true);
4034 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4035 /* Configure flow control refresh threshold,
4036 * the value for stat_tx_pause_refresh_timer[8]
4037 * is used for global pause operation.
4041 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4042 pf->fc_conf.pause_time);
4044 /* configure the timer value included in transmitted pause
4046 * the value for stat_tx_pause_quanta[8] is used for global
4049 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4050 pf->fc_conf.pause_time);
4052 fctrl_reg = I40E_READ_REG(hw,
4053 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4055 if (fc_conf->mac_ctrl_frame_fwd != 0)
4056 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4058 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4060 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4063 /* Configure pause time (2 TCs per register) */
4064 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4065 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4066 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4068 /* Configure flow control refresh threshold value */
4069 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4070 pf->fc_conf.pause_time / 2);
4072 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4074 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4075 *depending on configuration
4077 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4078 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4079 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4081 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4082 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4085 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4088 if (!pf->support_multi_driver) {
4089 /* config water marker both based on the packets and bytes */
4090 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4091 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4092 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4093 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4094 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4095 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4096 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4097 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4099 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4100 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4104 "Water marker configuration is not supported.");
4107 I40E_WRITE_FLUSH(hw);
4113 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4114 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4116 PMD_INIT_FUNC_TRACE();
4121 /* Add a MAC address, and update filters */
4123 i40e_macaddr_add(struct rte_eth_dev *dev,
4124 struct rte_ether_addr *mac_addr,
4125 __rte_unused uint32_t index,
4128 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4129 struct i40e_mac_filter_info mac_filter;
4130 struct i40e_vsi *vsi;
4131 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4134 /* If VMDQ not enabled or configured, return */
4135 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4136 !pf->nb_cfg_vmdq_vsi)) {
4137 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4138 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4143 if (pool > pf->nb_cfg_vmdq_vsi) {
4144 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4145 pool, pf->nb_cfg_vmdq_vsi);
4149 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4150 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4151 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4153 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4158 vsi = pf->vmdq[pool - 1].vsi;
4160 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4161 if (ret != I40E_SUCCESS) {
4162 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4168 /* Remove a MAC address, and update filters */
4170 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4172 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4173 struct i40e_vsi *vsi;
4174 struct rte_eth_dev_data *data = dev->data;
4175 struct rte_ether_addr *macaddr;
4180 macaddr = &(data->mac_addrs[index]);
4182 pool_sel = dev->data->mac_pool_sel[index];
4184 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4185 if (pool_sel & (1ULL << i)) {
4189 /* No VMDQ pool enabled or configured */
4190 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4191 (i > pf->nb_cfg_vmdq_vsi)) {
4193 "No VMDQ pool enabled/configured");
4196 vsi = pf->vmdq[i - 1].vsi;
4198 ret = i40e_vsi_delete_mac(vsi, macaddr);
4201 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4208 /* Set perfect match or hash match of MAC and VLAN for a VF */
4210 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4211 struct rte_eth_mac_filter *filter,
4215 struct i40e_mac_filter_info mac_filter;
4216 struct rte_ether_addr old_mac;
4217 struct rte_ether_addr *new_mac;
4218 struct i40e_pf_vf *vf = NULL;
4223 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4226 hw = I40E_PF_TO_HW(pf);
4228 if (filter == NULL) {
4229 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4233 new_mac = &filter->mac_addr;
4235 if (rte_is_zero_ether_addr(new_mac)) {
4236 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4240 vf_id = filter->dst_id;
4242 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4243 PMD_DRV_LOG(ERR, "Invalid argument.");
4246 vf = &pf->vfs[vf_id];
4248 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4249 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4254 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4255 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4256 RTE_ETHER_ADDR_LEN);
4257 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4258 RTE_ETHER_ADDR_LEN);
4260 mac_filter.filter_type = filter->filter_type;
4261 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4262 if (ret != I40E_SUCCESS) {
4263 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4266 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4268 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4269 RTE_ETHER_ADDR_LEN);
4270 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4271 if (ret != I40E_SUCCESS) {
4272 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4276 /* Clear device address as it has been removed */
4277 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4278 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4284 /* MAC filter handle */
4286 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4290 struct rte_eth_mac_filter *filter;
4291 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4292 int ret = I40E_NOT_SUPPORTED;
4294 filter = (struct rte_eth_mac_filter *)(arg);
4296 switch (filter_op) {
4297 case RTE_ETH_FILTER_NOP:
4300 case RTE_ETH_FILTER_ADD:
4301 i40e_pf_disable_irq0(hw);
4303 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4304 i40e_pf_enable_irq0(hw);
4306 case RTE_ETH_FILTER_DELETE:
4307 i40e_pf_disable_irq0(hw);
4309 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4310 i40e_pf_enable_irq0(hw);
4313 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4314 ret = I40E_ERR_PARAM;
4322 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4324 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4325 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4332 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4333 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4334 vsi->type != I40E_VSI_SRIOV,
4337 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4341 uint32_t *lut_dw = (uint32_t *)lut;
4342 uint16_t i, lut_size_dw = lut_size / 4;
4344 if (vsi->type == I40E_VSI_SRIOV) {
4345 for (i = 0; i <= lut_size_dw; i++) {
4346 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4347 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4350 for (i = 0; i < lut_size_dw; i++)
4351 lut_dw[i] = I40E_READ_REG(hw,
4360 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4369 pf = I40E_VSI_TO_PF(vsi);
4370 hw = I40E_VSI_TO_HW(vsi);
4372 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4373 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4374 vsi->type != I40E_VSI_SRIOV,
4377 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4381 uint32_t *lut_dw = (uint32_t *)lut;
4382 uint16_t i, lut_size_dw = lut_size / 4;
4384 if (vsi->type == I40E_VSI_SRIOV) {
4385 for (i = 0; i < lut_size_dw; i++)
4388 I40E_VFQF_HLUT1(i, vsi->user_param),
4391 for (i = 0; i < lut_size_dw; i++)
4392 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4395 I40E_WRITE_FLUSH(hw);
4402 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4403 struct rte_eth_rss_reta_entry64 *reta_conf,
4406 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4407 uint16_t i, lut_size = pf->hash_lut_size;
4408 uint16_t idx, shift;
4412 if (reta_size != lut_size ||
4413 reta_size > ETH_RSS_RETA_SIZE_512) {
4415 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4416 reta_size, lut_size);
4420 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4422 PMD_DRV_LOG(ERR, "No memory can be allocated");
4425 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4428 for (i = 0; i < reta_size; i++) {
4429 idx = i / RTE_RETA_GROUP_SIZE;
4430 shift = i % RTE_RETA_GROUP_SIZE;
4431 if (reta_conf[idx].mask & (1ULL << shift))
4432 lut[i] = reta_conf[idx].reta[shift];
4434 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4436 pf->adapter->rss_reta_updated = 1;
4445 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4446 struct rte_eth_rss_reta_entry64 *reta_conf,
4449 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4450 uint16_t i, lut_size = pf->hash_lut_size;
4451 uint16_t idx, shift;
4455 if (reta_size != lut_size ||
4456 reta_size > ETH_RSS_RETA_SIZE_512) {
4458 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4459 reta_size, lut_size);
4463 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4465 PMD_DRV_LOG(ERR, "No memory can be allocated");
4469 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4472 for (i = 0; i < reta_size; i++) {
4473 idx = i / RTE_RETA_GROUP_SIZE;
4474 shift = i % RTE_RETA_GROUP_SIZE;
4475 if (reta_conf[idx].mask & (1ULL << shift))
4476 reta_conf[idx].reta[shift] = lut[i];
4486 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4487 * @hw: pointer to the HW structure
4488 * @mem: pointer to mem struct to fill out
4489 * @size: size of memory requested
4490 * @alignment: what to align the allocation to
4492 enum i40e_status_code
4493 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4494 struct i40e_dma_mem *mem,
4498 const struct rte_memzone *mz = NULL;
4499 char z_name[RTE_MEMZONE_NAMESIZE];
4502 return I40E_ERR_PARAM;
4504 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4505 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4506 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4508 return I40E_ERR_NO_MEMORY;
4513 mem->zone = (const void *)mz;
4515 "memzone %s allocated with physical address: %"PRIu64,
4518 return I40E_SUCCESS;
4522 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4523 * @hw: pointer to the HW structure
4524 * @mem: ptr to mem struct to free
4526 enum i40e_status_code
4527 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4528 struct i40e_dma_mem *mem)
4531 return I40E_ERR_PARAM;
4534 "memzone %s to be freed with physical address: %"PRIu64,
4535 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4536 rte_memzone_free((const struct rte_memzone *)mem->zone);
4541 return I40E_SUCCESS;
4545 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4546 * @hw: pointer to the HW structure
4547 * @mem: pointer to mem struct to fill out
4548 * @size: size of memory requested
4550 enum i40e_status_code
4551 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4552 struct i40e_virt_mem *mem,
4556 return I40E_ERR_PARAM;
4559 mem->va = rte_zmalloc("i40e", size, 0);
4562 return I40E_SUCCESS;
4564 return I40E_ERR_NO_MEMORY;
4568 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4569 * @hw: pointer to the HW structure
4570 * @mem: pointer to mem struct to free
4572 enum i40e_status_code
4573 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4574 struct i40e_virt_mem *mem)
4577 return I40E_ERR_PARAM;
4582 return I40E_SUCCESS;
4586 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4588 rte_spinlock_init(&sp->spinlock);
4592 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4594 rte_spinlock_lock(&sp->spinlock);
4598 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4600 rte_spinlock_unlock(&sp->spinlock);
4604 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4610 * Get the hardware capabilities, which will be parsed
4611 * and saved into struct i40e_hw.
4614 i40e_get_cap(struct i40e_hw *hw)
4616 struct i40e_aqc_list_capabilities_element_resp *buf;
4617 uint16_t len, size = 0;
4620 /* Calculate a huge enough buff for saving response data temporarily */
4621 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4622 I40E_MAX_CAP_ELE_NUM;
4623 buf = rte_zmalloc("i40e", len, 0);
4625 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4626 return I40E_ERR_NO_MEMORY;
4629 /* Get, parse the capabilities and save it to hw */
4630 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4631 i40e_aqc_opc_list_func_capabilities, NULL);
4632 if (ret != I40E_SUCCESS)
4633 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4635 /* Free the temporary buffer after being used */
4641 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4643 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4651 pf = (struct i40e_pf *)opaque;
4655 num = strtoul(value, &end, 0);
4656 if (errno != 0 || end == value || *end != 0) {
4657 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4658 "kept the value = %hu", value, pf->vf_nb_qp_max);
4662 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4663 pf->vf_nb_qp_max = (uint16_t)num;
4665 /* here return 0 to make next valid same argument work */
4666 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4667 "power of 2 and equal or less than 16 !, Now it is "
4668 "kept the value = %hu", num, pf->vf_nb_qp_max);
4673 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4675 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4676 struct rte_kvargs *kvlist;
4679 /* set default queue number per VF as 4 */
4680 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4682 if (dev->device->devargs == NULL)
4685 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4689 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4690 if (!kvargs_count) {
4691 rte_kvargs_free(kvlist);
4695 if (kvargs_count > 1)
4696 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4697 "the first invalid or last valid one is used !",
4698 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4700 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4701 i40e_pf_parse_vf_queue_number_handler, pf);
4703 rte_kvargs_free(kvlist);
4709 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4714 uint16_t qp_count = 0, vsi_count = 0;
4716 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4717 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4721 i40e_pf_config_vf_rxq_number(dev);
4723 /* Add the parameter init for LFC */
4724 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4725 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4726 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4728 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4729 pf->max_num_vsi = hw->func_caps.num_vsis;
4730 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4731 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4733 /* FDir queue/VSI allocation */
4734 pf->fdir_qp_offset = 0;
4735 if (hw->func_caps.fd) {
4736 pf->flags |= I40E_FLAG_FDIR;
4737 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4739 pf->fdir_nb_qps = 0;
4741 qp_count += pf->fdir_nb_qps;
4744 /* LAN queue/VSI allocation */
4745 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4746 if (!hw->func_caps.rss) {
4749 pf->flags |= I40E_FLAG_RSS;
4750 if (hw->mac.type == I40E_MAC_X722)
4751 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4752 pf->lan_nb_qps = pf->lan_nb_qp_max;
4754 qp_count += pf->lan_nb_qps;
4757 /* VF queue/VSI allocation */
4758 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4759 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4760 pf->flags |= I40E_FLAG_SRIOV;
4761 pf->vf_nb_qps = pf->vf_nb_qp_max;
4762 pf->vf_num = pci_dev->max_vfs;
4764 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4765 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4770 qp_count += pf->vf_nb_qps * pf->vf_num;
4771 vsi_count += pf->vf_num;
4773 /* VMDq queue/VSI allocation */
4774 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4775 pf->vmdq_nb_qps = 0;
4776 pf->max_nb_vmdq_vsi = 0;
4777 if (hw->func_caps.vmdq) {
4778 if (qp_count < hw->func_caps.num_tx_qp &&
4779 vsi_count < hw->func_caps.num_vsis) {
4780 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4781 qp_count) / pf->vmdq_nb_qp_max;
4783 /* Limit the maximum number of VMDq vsi to the maximum
4784 * ethdev can support
4786 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4787 hw->func_caps.num_vsis - vsi_count);
4788 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4790 if (pf->max_nb_vmdq_vsi) {
4791 pf->flags |= I40E_FLAG_VMDQ;
4792 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4794 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4795 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4796 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4799 "No enough queues left for VMDq");
4802 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4805 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4806 vsi_count += pf->max_nb_vmdq_vsi;
4808 if (hw->func_caps.dcb)
4809 pf->flags |= I40E_FLAG_DCB;
4811 if (qp_count > hw->func_caps.num_tx_qp) {
4813 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4814 qp_count, hw->func_caps.num_tx_qp);
4817 if (vsi_count > hw->func_caps.num_vsis) {
4819 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4820 vsi_count, hw->func_caps.num_vsis);
4828 i40e_pf_get_switch_config(struct i40e_pf *pf)
4830 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4831 struct i40e_aqc_get_switch_config_resp *switch_config;
4832 struct i40e_aqc_switch_config_element_resp *element;
4833 uint16_t start_seid = 0, num_reported;
4836 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4837 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4838 if (!switch_config) {
4839 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4843 /* Get the switch configurations */
4844 ret = i40e_aq_get_switch_config(hw, switch_config,
4845 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4846 if (ret != I40E_SUCCESS) {
4847 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4850 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4851 if (num_reported != 1) { /* The number should be 1 */
4852 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4856 /* Parse the switch configuration elements */
4857 element = &(switch_config->element[0]);
4858 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4859 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4860 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4862 PMD_DRV_LOG(INFO, "Unknown element type");
4865 rte_free(switch_config);
4871 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4874 struct pool_entry *entry;
4876 if (pool == NULL || num == 0)
4879 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4880 if (entry == NULL) {
4881 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4885 /* queue heap initialize */
4886 pool->num_free = num;
4887 pool->num_alloc = 0;
4889 LIST_INIT(&pool->alloc_list);
4890 LIST_INIT(&pool->free_list);
4892 /* Initialize element */
4896 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4901 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4903 struct pool_entry *entry, *next_entry;
4908 for (entry = LIST_FIRST(&pool->alloc_list);
4909 entry && (next_entry = LIST_NEXT(entry, next), 1);
4910 entry = next_entry) {
4911 LIST_REMOVE(entry, next);
4915 for (entry = LIST_FIRST(&pool->free_list);
4916 entry && (next_entry = LIST_NEXT(entry, next), 1);
4917 entry = next_entry) {
4918 LIST_REMOVE(entry, next);
4923 pool->num_alloc = 0;
4925 LIST_INIT(&pool->alloc_list);
4926 LIST_INIT(&pool->free_list);
4930 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4933 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4934 uint32_t pool_offset;
4939 PMD_DRV_LOG(ERR, "Invalid parameter");
4943 pool_offset = base - pool->base;
4944 /* Lookup in alloc list */
4945 LIST_FOREACH(entry, &pool->alloc_list, next) {
4946 if (entry->base == pool_offset) {
4947 valid_entry = entry;
4948 LIST_REMOVE(entry, next);
4953 /* Not find, return */
4954 if (valid_entry == NULL) {
4955 PMD_DRV_LOG(ERR, "Failed to find entry");
4960 * Found it, move it to free list and try to merge.
4961 * In order to make merge easier, always sort it by qbase.
4962 * Find adjacent prev and last entries.
4965 LIST_FOREACH(entry, &pool->free_list, next) {
4966 if (entry->base > valid_entry->base) {
4974 len = valid_entry->len;
4975 /* Try to merge with next one*/
4977 /* Merge with next one */
4978 if (valid_entry->base + len == next->base) {
4979 next->base = valid_entry->base;
4981 rte_free(valid_entry);
4988 /* Merge with previous one */
4989 if (prev->base + prev->len == valid_entry->base) {
4991 /* If it merge with next one, remove next node */
4993 LIST_REMOVE(valid_entry, next);
4994 rte_free(valid_entry);
4997 rte_free(valid_entry);
5004 /* Not find any entry to merge, insert */
5007 LIST_INSERT_AFTER(prev, valid_entry, next);
5008 else if (next != NULL)
5009 LIST_INSERT_BEFORE(next, valid_entry, next);
5010 else /* It's empty list, insert to head */
5011 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5014 pool->num_free += len;
5015 pool->num_alloc -= len;
5021 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5024 struct pool_entry *entry, *valid_entry;
5026 if (pool == NULL || num == 0) {
5027 PMD_DRV_LOG(ERR, "Invalid parameter");
5031 if (pool->num_free < num) {
5032 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5033 num, pool->num_free);
5038 /* Lookup in free list and find most fit one */
5039 LIST_FOREACH(entry, &pool->free_list, next) {
5040 if (entry->len >= num) {
5042 if (entry->len == num) {
5043 valid_entry = entry;
5046 if (valid_entry == NULL || valid_entry->len > entry->len)
5047 valid_entry = entry;
5051 /* Not find one to satisfy the request, return */
5052 if (valid_entry == NULL) {
5053 PMD_DRV_LOG(ERR, "No valid entry found");
5057 * The entry have equal queue number as requested,
5058 * remove it from alloc_list.
5060 if (valid_entry->len == num) {
5061 LIST_REMOVE(valid_entry, next);
5064 * The entry have more numbers than requested,
5065 * create a new entry for alloc_list and minus its
5066 * queue base and number in free_list.
5068 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5069 if (entry == NULL) {
5071 "Failed to allocate memory for resource pool");
5074 entry->base = valid_entry->base;
5076 valid_entry->base += num;
5077 valid_entry->len -= num;
5078 valid_entry = entry;
5081 /* Insert it into alloc list, not sorted */
5082 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5084 pool->num_free -= valid_entry->len;
5085 pool->num_alloc += valid_entry->len;
5087 return valid_entry->base + pool->base;
5091 * bitmap_is_subset - Check whether src2 is subset of src1
5094 bitmap_is_subset(uint8_t src1, uint8_t src2)
5096 return !((src1 ^ src2) & src2);
5099 static enum i40e_status_code
5100 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5102 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5104 /* If DCB is not supported, only default TC is supported */
5105 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5106 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5107 return I40E_NOT_SUPPORTED;
5110 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5112 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5113 hw->func_caps.enabled_tcmap, enabled_tcmap);
5114 return I40E_NOT_SUPPORTED;
5116 return I40E_SUCCESS;
5120 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5121 struct i40e_vsi_vlan_pvid_info *info)
5124 struct i40e_vsi_context ctxt;
5125 uint8_t vlan_flags = 0;
5128 if (vsi == NULL || info == NULL) {
5129 PMD_DRV_LOG(ERR, "invalid parameters");
5130 return I40E_ERR_PARAM;
5134 vsi->info.pvid = info->config.pvid;
5136 * If insert pvid is enabled, only tagged pkts are
5137 * allowed to be sent out.
5139 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5140 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5143 if (info->config.reject.tagged == 0)
5144 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5146 if (info->config.reject.untagged == 0)
5147 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5149 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5150 I40E_AQ_VSI_PVLAN_MODE_MASK);
5151 vsi->info.port_vlan_flags |= vlan_flags;
5152 vsi->info.valid_sections =
5153 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5154 memset(&ctxt, 0, sizeof(ctxt));
5155 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5156 ctxt.seid = vsi->seid;
5158 hw = I40E_VSI_TO_HW(vsi);
5159 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5160 if (ret != I40E_SUCCESS)
5161 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5167 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5169 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5171 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5173 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5174 if (ret != I40E_SUCCESS)
5178 PMD_DRV_LOG(ERR, "seid not valid");
5182 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5183 tc_bw_data.tc_valid_bits = enabled_tcmap;
5184 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5185 tc_bw_data.tc_bw_credits[i] =
5186 (enabled_tcmap & (1 << i)) ? 1 : 0;
5188 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5189 if (ret != I40E_SUCCESS) {
5190 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5194 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5195 sizeof(vsi->info.qs_handle));
5196 return I40E_SUCCESS;
5199 static enum i40e_status_code
5200 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5201 struct i40e_aqc_vsi_properties_data *info,
5202 uint8_t enabled_tcmap)
5204 enum i40e_status_code ret;
5205 int i, total_tc = 0;
5206 uint16_t qpnum_per_tc, bsf, qp_idx;
5208 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5209 if (ret != I40E_SUCCESS)
5212 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5213 if (enabled_tcmap & (1 << i))
5217 vsi->enabled_tc = enabled_tcmap;
5219 /* Number of queues per enabled TC */
5220 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5221 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5222 bsf = rte_bsf32(qpnum_per_tc);
5224 /* Adjust the queue number to actual queues that can be applied */
5225 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5226 vsi->nb_qps = qpnum_per_tc * total_tc;
5229 * Configure TC and queue mapping parameters, for enabled TC,
5230 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5231 * default queue will serve it.
5234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5235 if (vsi->enabled_tc & (1 << i)) {
5236 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5237 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5238 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5239 qp_idx += qpnum_per_tc;
5241 info->tc_mapping[i] = 0;
5244 /* Associate queue number with VSI */
5245 if (vsi->type == I40E_VSI_SRIOV) {
5246 info->mapping_flags |=
5247 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5248 for (i = 0; i < vsi->nb_qps; i++)
5249 info->queue_mapping[i] =
5250 rte_cpu_to_le_16(vsi->base_queue + i);
5252 info->mapping_flags |=
5253 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5254 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5256 info->valid_sections |=
5257 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5259 return I40E_SUCCESS;
5263 i40e_veb_release(struct i40e_veb *veb)
5265 struct i40e_vsi *vsi;
5271 if (!TAILQ_EMPTY(&veb->head)) {
5272 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5275 /* associate_vsi field is NULL for floating VEB */
5276 if (veb->associate_vsi != NULL) {
5277 vsi = veb->associate_vsi;
5278 hw = I40E_VSI_TO_HW(vsi);
5280 vsi->uplink_seid = veb->uplink_seid;
5283 veb->associate_pf->main_vsi->floating_veb = NULL;
5284 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5287 i40e_aq_delete_element(hw, veb->seid, NULL);
5289 return I40E_SUCCESS;
5293 static struct i40e_veb *
5294 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5296 struct i40e_veb *veb;
5302 "veb setup failed, associated PF shouldn't null");
5305 hw = I40E_PF_TO_HW(pf);
5307 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5309 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5313 veb->associate_vsi = vsi;
5314 veb->associate_pf = pf;
5315 TAILQ_INIT(&veb->head);
5316 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5318 /* create floating veb if vsi is NULL */
5320 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5321 I40E_DEFAULT_TCMAP, false,
5322 &veb->seid, false, NULL);
5324 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5325 true, &veb->seid, false, NULL);
5328 if (ret != I40E_SUCCESS) {
5329 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5330 hw->aq.asq_last_status);
5333 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5335 /* get statistics index */
5336 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5337 &veb->stats_idx, NULL, NULL, NULL);
5338 if (ret != I40E_SUCCESS) {
5339 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5340 hw->aq.asq_last_status);
5343 /* Get VEB bandwidth, to be implemented */
5344 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5346 vsi->uplink_seid = veb->seid;
5355 i40e_vsi_release(struct i40e_vsi *vsi)
5359 struct i40e_vsi_list *vsi_list;
5362 struct i40e_mac_filter *f;
5363 uint16_t user_param;
5366 return I40E_SUCCESS;
5371 user_param = vsi->user_param;
5373 pf = I40E_VSI_TO_PF(vsi);
5374 hw = I40E_VSI_TO_HW(vsi);
5376 /* VSI has child to attach, release child first */
5378 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5379 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5382 i40e_veb_release(vsi->veb);
5385 if (vsi->floating_veb) {
5386 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5387 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5392 /* Remove all macvlan filters of the VSI */
5393 i40e_vsi_remove_all_macvlan_filter(vsi);
5394 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5397 if (vsi->type != I40E_VSI_MAIN &&
5398 ((vsi->type != I40E_VSI_SRIOV) ||
5399 !pf->floating_veb_list[user_param])) {
5400 /* Remove vsi from parent's sibling list */
5401 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5402 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5403 return I40E_ERR_PARAM;
5405 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5406 &vsi->sib_vsi_list, list);
5408 /* Remove all switch element of the VSI */
5409 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5410 if (ret != I40E_SUCCESS)
5411 PMD_DRV_LOG(ERR, "Failed to delete element");
5414 if ((vsi->type == I40E_VSI_SRIOV) &&
5415 pf->floating_veb_list[user_param]) {
5416 /* Remove vsi from parent's sibling list */
5417 if (vsi->parent_vsi == NULL ||
5418 vsi->parent_vsi->floating_veb == NULL) {
5419 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5420 return I40E_ERR_PARAM;
5422 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5423 &vsi->sib_vsi_list, list);
5425 /* Remove all switch element of the VSI */
5426 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5427 if (ret != I40E_SUCCESS)
5428 PMD_DRV_LOG(ERR, "Failed to delete element");
5431 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5433 if (vsi->type != I40E_VSI_SRIOV)
5434 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5437 return I40E_SUCCESS;
5441 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5443 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5444 struct i40e_aqc_remove_macvlan_element_data def_filter;
5445 struct i40e_mac_filter_info filter;
5448 if (vsi->type != I40E_VSI_MAIN)
5449 return I40E_ERR_CONFIG;
5450 memset(&def_filter, 0, sizeof(def_filter));
5451 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5453 def_filter.vlan_tag = 0;
5454 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5455 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5456 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5457 if (ret != I40E_SUCCESS) {
5458 struct i40e_mac_filter *f;
5459 struct rte_ether_addr *mac;
5462 "Cannot remove the default macvlan filter");
5463 /* It needs to add the permanent mac into mac list */
5464 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5466 PMD_DRV_LOG(ERR, "failed to allocate memory");
5467 return I40E_ERR_NO_MEMORY;
5469 mac = &f->mac_info.mac_addr;
5470 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5472 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5473 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5478 rte_memcpy(&filter.mac_addr,
5479 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5480 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5481 return i40e_vsi_add_mac(vsi, &filter);
5485 * i40e_vsi_get_bw_config - Query VSI BW Information
5486 * @vsi: the VSI to be queried
5488 * Returns 0 on success, negative value on failure
5490 static enum i40e_status_code
5491 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5493 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5494 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5495 struct i40e_hw *hw = &vsi->adapter->hw;
5500 memset(&bw_config, 0, sizeof(bw_config));
5501 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5502 if (ret != I40E_SUCCESS) {
5503 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5504 hw->aq.asq_last_status);
5508 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5509 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5510 &ets_sla_config, NULL);
5511 if (ret != I40E_SUCCESS) {
5513 "VSI failed to get TC bandwdith configuration %u",
5514 hw->aq.asq_last_status);
5518 /* store and print out BW info */
5519 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5520 vsi->bw_info.bw_max = bw_config.max_bw;
5521 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5522 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5523 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5524 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5526 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5527 vsi->bw_info.bw_ets_share_credits[i] =
5528 ets_sla_config.share_credits[i];
5529 vsi->bw_info.bw_ets_credits[i] =
5530 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5531 /* 4 bits per TC, 4th bit is reserved */
5532 vsi->bw_info.bw_ets_max[i] =
5533 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5534 RTE_LEN2MASK(3, uint8_t));
5535 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5536 vsi->bw_info.bw_ets_share_credits[i]);
5537 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5538 vsi->bw_info.bw_ets_credits[i]);
5539 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5540 vsi->bw_info.bw_ets_max[i]);
5543 return I40E_SUCCESS;
5546 /* i40e_enable_pf_lb
5547 * @pf: pointer to the pf structure
5549 * allow loopback on pf
5552 i40e_enable_pf_lb(struct i40e_pf *pf)
5554 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5555 struct i40e_vsi_context ctxt;
5558 /* Use the FW API if FW >= v5.0 */
5559 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5560 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5564 memset(&ctxt, 0, sizeof(ctxt));
5565 ctxt.seid = pf->main_vsi_seid;
5566 ctxt.pf_num = hw->pf_id;
5567 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5569 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5570 ret, hw->aq.asq_last_status);
5573 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5574 ctxt.info.valid_sections =
5575 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5576 ctxt.info.switch_id |=
5577 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5579 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5581 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5582 hw->aq.asq_last_status);
5587 i40e_vsi_setup(struct i40e_pf *pf,
5588 enum i40e_vsi_type type,
5589 struct i40e_vsi *uplink_vsi,
5590 uint16_t user_param)
5592 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5593 struct i40e_vsi *vsi;
5594 struct i40e_mac_filter_info filter;
5596 struct i40e_vsi_context ctxt;
5597 struct rte_ether_addr broadcast =
5598 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5600 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5601 uplink_vsi == NULL) {
5603 "VSI setup failed, VSI link shouldn't be NULL");
5607 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5609 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5614 * 1.type is not MAIN and uplink vsi is not NULL
5615 * If uplink vsi didn't setup VEB, create one first under veb field
5616 * 2.type is SRIOV and the uplink is NULL
5617 * If floating VEB is NULL, create one veb under floating veb field
5620 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5621 uplink_vsi->veb == NULL) {
5622 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5624 if (uplink_vsi->veb == NULL) {
5625 PMD_DRV_LOG(ERR, "VEB setup failed");
5628 /* set ALLOWLOOPBACk on pf, when veb is created */
5629 i40e_enable_pf_lb(pf);
5632 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5633 pf->main_vsi->floating_veb == NULL) {
5634 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5636 if (pf->main_vsi->floating_veb == NULL) {
5637 PMD_DRV_LOG(ERR, "VEB setup failed");
5642 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5644 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5647 TAILQ_INIT(&vsi->mac_list);
5649 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5650 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5651 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5652 vsi->user_param = user_param;
5653 vsi->vlan_anti_spoof_on = 0;
5654 vsi->vlan_filter_on = 0;
5655 /* Allocate queues */
5656 switch (vsi->type) {
5657 case I40E_VSI_MAIN :
5658 vsi->nb_qps = pf->lan_nb_qps;
5660 case I40E_VSI_SRIOV :
5661 vsi->nb_qps = pf->vf_nb_qps;
5663 case I40E_VSI_VMDQ2:
5664 vsi->nb_qps = pf->vmdq_nb_qps;
5667 vsi->nb_qps = pf->fdir_nb_qps;
5673 * The filter status descriptor is reported in rx queue 0,
5674 * while the tx queue for fdir filter programming has no
5675 * such constraints, can be non-zero queues.
5676 * To simplify it, choose FDIR vsi use queue 0 pair.
5677 * To make sure it will use queue 0 pair, queue allocation
5678 * need be done before this function is called
5680 if (type != I40E_VSI_FDIR) {
5681 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5683 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5687 vsi->base_queue = ret;
5689 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5691 /* VF has MSIX interrupt in VF range, don't allocate here */
5692 if (type == I40E_VSI_MAIN) {
5693 if (pf->support_multi_driver) {
5694 /* If support multi-driver, need to use INT0 instead of
5695 * allocating from msix pool. The Msix pool is init from
5696 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5697 * to 1 without calling i40e_res_pool_alloc.
5702 ret = i40e_res_pool_alloc(&pf->msix_pool,
5703 RTE_MIN(vsi->nb_qps,
5704 RTE_MAX_RXTX_INTR_VEC_ID));
5707 "VSI MAIN %d get heap failed %d",
5709 goto fail_queue_alloc;
5711 vsi->msix_intr = ret;
5712 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5713 RTE_MAX_RXTX_INTR_VEC_ID);
5715 } else if (type != I40E_VSI_SRIOV) {
5716 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5718 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5719 goto fail_queue_alloc;
5721 vsi->msix_intr = ret;
5729 if (type == I40E_VSI_MAIN) {
5730 /* For main VSI, no need to add since it's default one */
5731 vsi->uplink_seid = pf->mac_seid;
5732 vsi->seid = pf->main_vsi_seid;
5733 /* Bind queues with specific MSIX interrupt */
5735 * Needs 2 interrupt at least, one for misc cause which will
5736 * enabled from OS side, Another for queues binding the
5737 * interrupt from device side only.
5740 /* Get default VSI parameters from hardware */
5741 memset(&ctxt, 0, sizeof(ctxt));
5742 ctxt.seid = vsi->seid;
5743 ctxt.pf_num = hw->pf_id;
5744 ctxt.uplink_seid = vsi->uplink_seid;
5746 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5747 if (ret != I40E_SUCCESS) {
5748 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5749 goto fail_msix_alloc;
5751 rte_memcpy(&vsi->info, &ctxt.info,
5752 sizeof(struct i40e_aqc_vsi_properties_data));
5753 vsi->vsi_id = ctxt.vsi_number;
5754 vsi->info.valid_sections = 0;
5756 /* Configure tc, enabled TC0 only */
5757 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5759 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5760 goto fail_msix_alloc;
5763 /* TC, queue mapping */
5764 memset(&ctxt, 0, sizeof(ctxt));
5765 vsi->info.valid_sections |=
5766 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5767 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5768 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5769 rte_memcpy(&ctxt.info, &vsi->info,
5770 sizeof(struct i40e_aqc_vsi_properties_data));
5771 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5772 I40E_DEFAULT_TCMAP);
5773 if (ret != I40E_SUCCESS) {
5775 "Failed to configure TC queue mapping");
5776 goto fail_msix_alloc;
5778 ctxt.seid = vsi->seid;
5779 ctxt.pf_num = hw->pf_id;
5780 ctxt.uplink_seid = vsi->uplink_seid;
5783 /* Update VSI parameters */
5784 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5785 if (ret != I40E_SUCCESS) {
5786 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5787 goto fail_msix_alloc;
5790 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5791 sizeof(vsi->info.tc_mapping));
5792 rte_memcpy(&vsi->info.queue_mapping,
5793 &ctxt.info.queue_mapping,
5794 sizeof(vsi->info.queue_mapping));
5795 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5796 vsi->info.valid_sections = 0;
5798 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5802 * Updating default filter settings are necessary to prevent
5803 * reception of tagged packets.
5804 * Some old firmware configurations load a default macvlan
5805 * filter which accepts both tagged and untagged packets.
5806 * The updating is to use a normal filter instead if needed.
5807 * For NVM 4.2.2 or after, the updating is not needed anymore.
5808 * The firmware with correct configurations load the default
5809 * macvlan filter which is expected and cannot be removed.
5811 i40e_update_default_filter_setting(vsi);
5812 i40e_config_qinq(hw, vsi);
5813 } else if (type == I40E_VSI_SRIOV) {
5814 memset(&ctxt, 0, sizeof(ctxt));
5816 * For other VSI, the uplink_seid equals to uplink VSI's
5817 * uplink_seid since they share same VEB
5819 if (uplink_vsi == NULL)
5820 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5822 vsi->uplink_seid = uplink_vsi->uplink_seid;
5823 ctxt.pf_num = hw->pf_id;
5824 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5825 ctxt.uplink_seid = vsi->uplink_seid;
5826 ctxt.connection_type = 0x1;
5827 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5829 /* Use the VEB configuration if FW >= v5.0 */
5830 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5831 /* Configure switch ID */
5832 ctxt.info.valid_sections |=
5833 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5834 ctxt.info.switch_id =
5835 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5838 /* Configure port/vlan */
5839 ctxt.info.valid_sections |=
5840 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5841 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5842 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5843 hw->func_caps.enabled_tcmap);
5844 if (ret != I40E_SUCCESS) {
5846 "Failed to configure TC queue mapping");
5847 goto fail_msix_alloc;
5850 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5851 ctxt.info.valid_sections |=
5852 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5854 * Since VSI is not created yet, only configure parameter,
5855 * will add vsi below.
5858 i40e_config_qinq(hw, vsi);
5859 } else if (type == I40E_VSI_VMDQ2) {
5860 memset(&ctxt, 0, sizeof(ctxt));
5862 * For other VSI, the uplink_seid equals to uplink VSI's
5863 * uplink_seid since they share same VEB
5865 vsi->uplink_seid = uplink_vsi->uplink_seid;
5866 ctxt.pf_num = hw->pf_id;
5868 ctxt.uplink_seid = vsi->uplink_seid;
5869 ctxt.connection_type = 0x1;
5870 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5872 ctxt.info.valid_sections |=
5873 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5874 /* user_param carries flag to enable loop back */
5876 ctxt.info.switch_id =
5877 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5878 ctxt.info.switch_id |=
5879 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5882 /* Configure port/vlan */
5883 ctxt.info.valid_sections |=
5884 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5885 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5886 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5887 I40E_DEFAULT_TCMAP);
5888 if (ret != I40E_SUCCESS) {
5890 "Failed to configure TC queue mapping");
5891 goto fail_msix_alloc;
5893 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5894 ctxt.info.valid_sections |=
5895 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5896 } else if (type == I40E_VSI_FDIR) {
5897 memset(&ctxt, 0, sizeof(ctxt));
5898 vsi->uplink_seid = uplink_vsi->uplink_seid;
5899 ctxt.pf_num = hw->pf_id;
5901 ctxt.uplink_seid = vsi->uplink_seid;
5902 ctxt.connection_type = 0x1; /* regular data port */
5903 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5904 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5905 I40E_DEFAULT_TCMAP);
5906 if (ret != I40E_SUCCESS) {
5908 "Failed to configure TC queue mapping.");
5909 goto fail_msix_alloc;
5911 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5912 ctxt.info.valid_sections |=
5913 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5915 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5916 goto fail_msix_alloc;
5919 if (vsi->type != I40E_VSI_MAIN) {
5920 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5921 if (ret != I40E_SUCCESS) {
5922 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5923 hw->aq.asq_last_status);
5924 goto fail_msix_alloc;
5926 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5927 vsi->info.valid_sections = 0;
5928 vsi->seid = ctxt.seid;
5929 vsi->vsi_id = ctxt.vsi_number;
5930 vsi->sib_vsi_list.vsi = vsi;
5931 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5932 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5933 &vsi->sib_vsi_list, list);
5935 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5936 &vsi->sib_vsi_list, list);
5940 /* MAC/VLAN configuration */
5941 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5942 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5944 ret = i40e_vsi_add_mac(vsi, &filter);
5945 if (ret != I40E_SUCCESS) {
5946 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5947 goto fail_msix_alloc;
5950 /* Get VSI BW information */
5951 i40e_vsi_get_bw_config(vsi);
5954 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5956 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5962 /* Configure vlan filter on or off */
5964 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5967 struct i40e_mac_filter *f;
5969 struct i40e_mac_filter_info *mac_filter;
5970 enum rte_mac_filter_type desired_filter;
5971 int ret = I40E_SUCCESS;
5974 /* Filter to match MAC and VLAN */
5975 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5977 /* Filter to match only MAC */
5978 desired_filter = RTE_MAC_PERFECT_MATCH;
5983 mac_filter = rte_zmalloc("mac_filter_info_data",
5984 num * sizeof(*mac_filter), 0);
5985 if (mac_filter == NULL) {
5986 PMD_DRV_LOG(ERR, "failed to allocate memory");
5987 return I40E_ERR_NO_MEMORY;
5992 /* Remove all existing mac */
5993 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5994 mac_filter[i] = f->mac_info;
5995 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5997 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5998 on ? "enable" : "disable");
6004 /* Override with new filter */
6005 for (i = 0; i < num; i++) {
6006 mac_filter[i].filter_type = desired_filter;
6007 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6009 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6010 on ? "enable" : "disable");
6016 rte_free(mac_filter);
6020 /* Configure vlan stripping on or off */
6022 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6024 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6025 struct i40e_vsi_context ctxt;
6027 int ret = I40E_SUCCESS;
6029 /* Check if it has been already on or off */
6030 if (vsi->info.valid_sections &
6031 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6033 if ((vsi->info.port_vlan_flags &
6034 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6035 return 0; /* already on */
6037 if ((vsi->info.port_vlan_flags &
6038 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6039 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6040 return 0; /* already off */
6045 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6047 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6048 vsi->info.valid_sections =
6049 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6050 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6051 vsi->info.port_vlan_flags |= vlan_flags;
6052 ctxt.seid = vsi->seid;
6053 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6054 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6056 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6057 on ? "enable" : "disable");
6063 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6065 struct rte_eth_dev_data *data = dev->data;
6069 /* Apply vlan offload setting */
6070 mask = ETH_VLAN_STRIP_MASK |
6071 ETH_VLAN_FILTER_MASK |
6072 ETH_VLAN_EXTEND_MASK;
6073 ret = i40e_vlan_offload_set(dev, mask);
6075 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6079 /* Apply pvid setting */
6080 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6081 data->dev_conf.txmode.hw_vlan_insert_pvid);
6083 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6089 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6091 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6093 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6097 i40e_update_flow_control(struct i40e_hw *hw)
6099 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6100 struct i40e_link_status link_status;
6101 uint32_t rxfc = 0, txfc = 0, reg;
6105 memset(&link_status, 0, sizeof(link_status));
6106 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6107 if (ret != I40E_SUCCESS) {
6108 PMD_DRV_LOG(ERR, "Failed to get link status information");
6109 goto write_reg; /* Disable flow control */
6112 an_info = hw->phy.link_info.an_info;
6113 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6114 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6115 ret = I40E_ERR_NOT_READY;
6116 goto write_reg; /* Disable flow control */
6119 * If link auto negotiation is enabled, flow control needs to
6120 * be configured according to it
6122 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6123 case I40E_LINK_PAUSE_RXTX:
6126 hw->fc.current_mode = I40E_FC_FULL;
6128 case I40E_AQ_LINK_PAUSE_RX:
6130 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6132 case I40E_AQ_LINK_PAUSE_TX:
6134 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6137 hw->fc.current_mode = I40E_FC_NONE;
6142 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6143 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6144 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6145 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6146 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6147 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6154 i40e_pf_setup(struct i40e_pf *pf)
6156 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6157 struct i40e_filter_control_settings settings;
6158 struct i40e_vsi *vsi;
6161 /* Clear all stats counters */
6162 pf->offset_loaded = FALSE;
6163 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6164 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6165 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6166 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6168 ret = i40e_pf_get_switch_config(pf);
6169 if (ret != I40E_SUCCESS) {
6170 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6174 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6176 PMD_INIT_LOG(WARNING,
6177 "failed to allocate switch domain for device %d", ret);
6179 if (pf->flags & I40E_FLAG_FDIR) {
6180 /* make queue allocated first, let FDIR use queue pair 0*/
6181 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6182 if (ret != I40E_FDIR_QUEUE_ID) {
6184 "queue allocation fails for FDIR: ret =%d",
6186 pf->flags &= ~I40E_FLAG_FDIR;
6189 /* main VSI setup */
6190 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6192 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6193 return I40E_ERR_NOT_READY;
6197 /* Configure filter control */
6198 memset(&settings, 0, sizeof(settings));
6199 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6200 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6201 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6202 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6204 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6205 hw->func_caps.rss_table_size);
6206 return I40E_ERR_PARAM;
6208 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6209 hw->func_caps.rss_table_size);
6210 pf->hash_lut_size = hw->func_caps.rss_table_size;
6212 /* Enable ethtype and macvlan filters */
6213 settings.enable_ethtype = TRUE;
6214 settings.enable_macvlan = TRUE;
6215 ret = i40e_set_filter_control(hw, &settings);
6217 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6220 /* Update flow control according to the auto negotiation */
6221 i40e_update_flow_control(hw);
6223 return I40E_SUCCESS;
6227 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6233 * Set or clear TX Queue Disable flags,
6234 * which is required by hardware.
6236 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6237 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6239 /* Wait until the request is finished */
6240 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6241 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6242 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6243 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6244 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6250 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6251 return I40E_SUCCESS; /* already on, skip next steps */
6253 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6254 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6256 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6257 return I40E_SUCCESS; /* already off, skip next steps */
6258 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6260 /* Write the register */
6261 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6262 /* Check the result */
6263 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6264 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6265 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6267 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6268 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6271 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6272 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6276 /* Check if it is timeout */
6277 if (j >= I40E_CHK_Q_ENA_COUNT) {
6278 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6279 (on ? "enable" : "disable"), q_idx);
6280 return I40E_ERR_TIMEOUT;
6283 return I40E_SUCCESS;
6287 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6292 /* Wait until the request is finished */
6293 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6294 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6295 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6296 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6297 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6302 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6303 return I40E_SUCCESS; /* Already on, skip next steps */
6304 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6306 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6307 return I40E_SUCCESS; /* Already off, skip next steps */
6308 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6311 /* Write the register */
6312 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6313 /* Check the result */
6314 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6315 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6316 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6318 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6319 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6322 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6323 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6328 /* Check if it is timeout */
6329 if (j >= I40E_CHK_Q_ENA_COUNT) {
6330 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6331 (on ? "enable" : "disable"), q_idx);
6332 return I40E_ERR_TIMEOUT;
6335 return I40E_SUCCESS;
6338 /* Initialize VSI for TX */
6340 i40e_dev_tx_init(struct i40e_pf *pf)
6342 struct rte_eth_dev_data *data = pf->dev_data;
6344 uint32_t ret = I40E_SUCCESS;
6345 struct i40e_tx_queue *txq;
6347 for (i = 0; i < data->nb_tx_queues; i++) {
6348 txq = data->tx_queues[i];
6349 if (!txq || !txq->q_set)
6351 ret = i40e_tx_queue_init(txq);
6352 if (ret != I40E_SUCCESS)
6355 if (ret == I40E_SUCCESS)
6356 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6362 /* Initialize VSI for RX */
6364 i40e_dev_rx_init(struct i40e_pf *pf)
6366 struct rte_eth_dev_data *data = pf->dev_data;
6367 int ret = I40E_SUCCESS;
6369 struct i40e_rx_queue *rxq;
6371 i40e_pf_config_mq_rx(pf);
6372 for (i = 0; i < data->nb_rx_queues; i++) {
6373 rxq = data->rx_queues[i];
6374 if (!rxq || !rxq->q_set)
6377 ret = i40e_rx_queue_init(rxq);
6378 if (ret != I40E_SUCCESS) {
6380 "Failed to do RX queue initialization");
6384 if (ret == I40E_SUCCESS)
6385 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6392 i40e_dev_rxtx_init(struct i40e_pf *pf)
6396 err = i40e_dev_tx_init(pf);
6398 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6401 err = i40e_dev_rx_init(pf);
6403 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6411 i40e_vmdq_setup(struct rte_eth_dev *dev)
6413 struct rte_eth_conf *conf = &dev->data->dev_conf;
6414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6415 int i, err, conf_vsis, j, loop;
6416 struct i40e_vsi *vsi;
6417 struct i40e_vmdq_info *vmdq_info;
6418 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6419 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6422 * Disable interrupt to avoid message from VF. Furthermore, it will
6423 * avoid race condition in VSI creation/destroy.
6425 i40e_pf_disable_irq0(hw);
6427 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6428 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6432 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6433 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6434 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6435 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6436 pf->max_nb_vmdq_vsi);
6440 if (pf->vmdq != NULL) {
6441 PMD_INIT_LOG(INFO, "VMDQ already configured");
6445 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6446 sizeof(*vmdq_info) * conf_vsis, 0);
6448 if (pf->vmdq == NULL) {
6449 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6453 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6455 /* Create VMDQ VSI */
6456 for (i = 0; i < conf_vsis; i++) {
6457 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6458 vmdq_conf->enable_loop_back);
6460 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6464 vmdq_info = &pf->vmdq[i];
6466 vmdq_info->vsi = vsi;
6468 pf->nb_cfg_vmdq_vsi = conf_vsis;
6470 /* Configure Vlan */
6471 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6472 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6473 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6474 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6475 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6476 vmdq_conf->pool_map[i].vlan_id, j);
6478 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6479 vmdq_conf->pool_map[i].vlan_id);
6481 PMD_INIT_LOG(ERR, "Failed to add vlan");
6489 i40e_pf_enable_irq0(hw);
6494 for (i = 0; i < conf_vsis; i++)
6495 if (pf->vmdq[i].vsi == NULL)
6498 i40e_vsi_release(pf->vmdq[i].vsi);
6502 i40e_pf_enable_irq0(hw);
6507 i40e_stat_update_32(struct i40e_hw *hw,
6515 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6519 if (new_data >= *offset)
6520 *stat = (uint64_t)(new_data - *offset);
6522 *stat = (uint64_t)((new_data +
6523 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6527 i40e_stat_update_48(struct i40e_hw *hw,
6536 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6537 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6538 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6543 if (new_data >= *offset)
6544 *stat = new_data - *offset;
6546 *stat = (uint64_t)((new_data +
6547 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6549 *stat &= I40E_48_BIT_MASK;
6554 i40e_pf_disable_irq0(struct i40e_hw *hw)
6556 /* Disable all interrupt types */
6557 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6558 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6559 I40E_WRITE_FLUSH(hw);
6564 i40e_pf_enable_irq0(struct i40e_hw *hw)
6566 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6567 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6568 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6569 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6570 I40E_WRITE_FLUSH(hw);
6574 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6576 /* read pending request and disable first */
6577 i40e_pf_disable_irq0(hw);
6578 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6579 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6580 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6583 /* Link no queues with irq0 */
6584 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6585 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6589 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6595 uint32_t index, offset, val;
6600 * Try to find which VF trigger a reset, use absolute VF id to access
6601 * since the reg is global register.
6603 for (i = 0; i < pf->vf_num; i++) {
6604 abs_vf_id = hw->func_caps.vf_base_id + i;
6605 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6606 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6607 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6608 /* VFR event occurred */
6609 if (val & (0x1 << offset)) {
6612 /* Clear the event first */
6613 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6615 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6617 * Only notify a VF reset event occurred,
6618 * don't trigger another SW reset
6620 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6621 if (ret != I40E_SUCCESS)
6622 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6628 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6633 for (i = 0; i < pf->vf_num; i++)
6634 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6638 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6641 struct i40e_arq_event_info info;
6642 uint16_t pending, opcode;
6645 info.buf_len = I40E_AQ_BUF_SZ;
6646 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6647 if (!info.msg_buf) {
6648 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6654 ret = i40e_clean_arq_element(hw, &info, &pending);
6656 if (ret != I40E_SUCCESS) {
6658 "Failed to read msg from AdminQ, aq_err: %u",
6659 hw->aq.asq_last_status);
6662 opcode = rte_le_to_cpu_16(info.desc.opcode);
6665 case i40e_aqc_opc_send_msg_to_pf:
6666 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6667 i40e_pf_host_handle_vf_msg(dev,
6668 rte_le_to_cpu_16(info.desc.retval),
6669 rte_le_to_cpu_32(info.desc.cookie_high),
6670 rte_le_to_cpu_32(info.desc.cookie_low),
6674 case i40e_aqc_opc_get_link_status:
6675 ret = i40e_dev_link_update(dev, 0);
6677 _rte_eth_dev_callback_process(dev,
6678 RTE_ETH_EVENT_INTR_LSC, NULL);
6681 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6686 rte_free(info.msg_buf);
6690 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6692 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6693 #define I40E_MDD_CLEAR16 0xFFFF
6694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6696 bool mdd_detected = false;
6697 struct i40e_pf_vf *vf;
6701 /* find what triggered the MDD event */
6702 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6703 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6704 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6705 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6706 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6707 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6708 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6709 I40E_GL_MDET_TX_EVENT_SHIFT;
6710 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6711 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6712 hw->func_caps.base_queue;
6713 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6714 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6715 event, queue, pf_num, vf_num, dev->data->name);
6716 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6717 mdd_detected = true;
6719 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6720 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6721 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6722 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6723 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6724 I40E_GL_MDET_RX_EVENT_SHIFT;
6725 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6726 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6727 hw->func_caps.base_queue;
6729 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6730 "queue %d of function 0x%02x device %s\n",
6731 event, queue, func, dev->data->name);
6732 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6733 mdd_detected = true;
6737 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6738 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6739 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6740 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6742 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6743 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6744 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6746 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6750 /* see if one of the VFs needs its hand slapped */
6751 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6753 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6754 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6755 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6757 vf->num_mdd_events++;
6758 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6760 i, vf->num_mdd_events);
6763 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6764 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6765 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6767 vf->num_mdd_events++;
6768 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6770 i, vf->num_mdd_events);
6776 * Interrupt handler triggered by NIC for handling
6777 * specific interrupt.
6780 * Pointer to interrupt handle.
6782 * The address of parameter (struct rte_eth_dev *) regsitered before.
6788 i40e_dev_interrupt_handler(void *param)
6790 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794 /* Disable interrupt */
6795 i40e_pf_disable_irq0(hw);
6797 /* read out interrupt causes */
6798 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6800 /* No interrupt event indicated */
6801 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6802 PMD_DRV_LOG(INFO, "No interrupt event");
6805 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6806 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6807 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6808 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6809 i40e_handle_mdd_event(dev);
6811 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6812 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6813 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6814 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6815 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6816 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6817 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6818 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6819 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6820 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6822 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6823 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6824 i40e_dev_handle_vfr_event(dev);
6826 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6827 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6828 i40e_dev_handle_aq_msg(dev);
6832 /* Enable interrupt */
6833 i40e_pf_enable_irq0(hw);
6837 i40e_dev_alarm_handler(void *param)
6839 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843 /* Disable interrupt */
6844 i40e_pf_disable_irq0(hw);
6846 /* read out interrupt causes */
6847 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6849 /* No interrupt event indicated */
6850 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6852 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6853 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6854 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6855 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6856 i40e_handle_mdd_event(dev);
6858 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6859 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6860 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6861 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6862 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6863 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6864 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6865 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6866 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6867 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6869 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6870 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6871 i40e_dev_handle_vfr_event(dev);
6873 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6874 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6875 i40e_dev_handle_aq_msg(dev);
6879 /* Enable interrupt */
6880 i40e_pf_enable_irq0(hw);
6881 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6882 i40e_dev_alarm_handler, dev);
6886 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6887 struct i40e_macvlan_filter *filter,
6890 int ele_num, ele_buff_size;
6891 int num, actual_num, i;
6893 int ret = I40E_SUCCESS;
6894 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6895 struct i40e_aqc_add_macvlan_element_data *req_list;
6897 if (filter == NULL || total == 0)
6898 return I40E_ERR_PARAM;
6899 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6900 ele_buff_size = hw->aq.asq_buf_size;
6902 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6903 if (req_list == NULL) {
6904 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6905 return I40E_ERR_NO_MEMORY;
6910 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6911 memset(req_list, 0, ele_buff_size);
6913 for (i = 0; i < actual_num; i++) {
6914 rte_memcpy(req_list[i].mac_addr,
6915 &filter[num + i].macaddr, ETH_ADDR_LEN);
6916 req_list[i].vlan_tag =
6917 rte_cpu_to_le_16(filter[num + i].vlan_id);
6919 switch (filter[num + i].filter_type) {
6920 case RTE_MAC_PERFECT_MATCH:
6921 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6922 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6924 case RTE_MACVLAN_PERFECT_MATCH:
6925 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6927 case RTE_MAC_HASH_MATCH:
6928 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6929 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6931 case RTE_MACVLAN_HASH_MATCH:
6932 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6935 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6936 ret = I40E_ERR_PARAM;
6940 req_list[i].queue_number = 0;
6942 req_list[i].flags = rte_cpu_to_le_16(flags);
6945 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6947 if (ret != I40E_SUCCESS) {
6948 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6952 } while (num < total);
6960 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6961 struct i40e_macvlan_filter *filter,
6964 int ele_num, ele_buff_size;
6965 int num, actual_num, i;
6967 int ret = I40E_SUCCESS;
6968 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6969 struct i40e_aqc_remove_macvlan_element_data *req_list;
6971 if (filter == NULL || total == 0)
6972 return I40E_ERR_PARAM;
6974 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6975 ele_buff_size = hw->aq.asq_buf_size;
6977 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6978 if (req_list == NULL) {
6979 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6980 return I40E_ERR_NO_MEMORY;
6985 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6986 memset(req_list, 0, ele_buff_size);
6988 for (i = 0; i < actual_num; i++) {
6989 rte_memcpy(req_list[i].mac_addr,
6990 &filter[num + i].macaddr, ETH_ADDR_LEN);
6991 req_list[i].vlan_tag =
6992 rte_cpu_to_le_16(filter[num + i].vlan_id);
6994 switch (filter[num + i].filter_type) {
6995 case RTE_MAC_PERFECT_MATCH:
6996 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6997 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6999 case RTE_MACVLAN_PERFECT_MATCH:
7000 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7002 case RTE_MAC_HASH_MATCH:
7003 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7004 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7006 case RTE_MACVLAN_HASH_MATCH:
7007 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7010 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7011 ret = I40E_ERR_PARAM;
7014 req_list[i].flags = rte_cpu_to_le_16(flags);
7017 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7019 if (ret != I40E_SUCCESS) {
7020 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7024 } while (num < total);
7031 /* Find out specific MAC filter */
7032 static struct i40e_mac_filter *
7033 i40e_find_mac_filter(struct i40e_vsi *vsi,
7034 struct rte_ether_addr *macaddr)
7036 struct i40e_mac_filter *f;
7038 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7039 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7047 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7050 uint32_t vid_idx, vid_bit;
7052 if (vlan_id > ETH_VLAN_ID_MAX)
7055 vid_idx = I40E_VFTA_IDX(vlan_id);
7056 vid_bit = I40E_VFTA_BIT(vlan_id);
7058 if (vsi->vfta[vid_idx] & vid_bit)
7065 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7066 uint16_t vlan_id, bool on)
7068 uint32_t vid_idx, vid_bit;
7070 vid_idx = I40E_VFTA_IDX(vlan_id);
7071 vid_bit = I40E_VFTA_BIT(vlan_id);
7074 vsi->vfta[vid_idx] |= vid_bit;
7076 vsi->vfta[vid_idx] &= ~vid_bit;
7080 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7081 uint16_t vlan_id, bool on)
7083 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7084 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7087 if (vlan_id > ETH_VLAN_ID_MAX)
7090 i40e_store_vlan_filter(vsi, vlan_id, on);
7092 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7095 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7098 ret = i40e_aq_add_vlan(hw, vsi->seid,
7099 &vlan_data, 1, NULL);
7100 if (ret != I40E_SUCCESS)
7101 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7103 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7104 &vlan_data, 1, NULL);
7105 if (ret != I40E_SUCCESS)
7107 "Failed to remove vlan filter");
7112 * Find all vlan options for specific mac addr,
7113 * return with actual vlan found.
7116 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7117 struct i40e_macvlan_filter *mv_f,
7118 int num, struct rte_ether_addr *addr)
7124 * Not to use i40e_find_vlan_filter to decrease the loop time,
7125 * although the code looks complex.
7127 if (num < vsi->vlan_num)
7128 return I40E_ERR_PARAM;
7131 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7133 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7134 if (vsi->vfta[j] & (1 << k)) {
7137 "vlan number doesn't match");
7138 return I40E_ERR_PARAM;
7140 rte_memcpy(&mv_f[i].macaddr,
7141 addr, ETH_ADDR_LEN);
7143 j * I40E_UINT32_BIT_SIZE + k;
7149 return I40E_SUCCESS;
7153 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7154 struct i40e_macvlan_filter *mv_f,
7159 struct i40e_mac_filter *f;
7161 if (num < vsi->mac_num)
7162 return I40E_ERR_PARAM;
7164 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7166 PMD_DRV_LOG(ERR, "buffer number not match");
7167 return I40E_ERR_PARAM;
7169 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7171 mv_f[i].vlan_id = vlan;
7172 mv_f[i].filter_type = f->mac_info.filter_type;
7176 return I40E_SUCCESS;
7180 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7183 struct i40e_mac_filter *f;
7184 struct i40e_macvlan_filter *mv_f;
7185 int ret = I40E_SUCCESS;
7187 if (vsi == NULL || vsi->mac_num == 0)
7188 return I40E_ERR_PARAM;
7190 /* Case that no vlan is set */
7191 if (vsi->vlan_num == 0)
7194 num = vsi->mac_num * vsi->vlan_num;
7196 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7198 PMD_DRV_LOG(ERR, "failed to allocate memory");
7199 return I40E_ERR_NO_MEMORY;
7203 if (vsi->vlan_num == 0) {
7204 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7205 rte_memcpy(&mv_f[i].macaddr,
7206 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7207 mv_f[i].filter_type = f->mac_info.filter_type;
7208 mv_f[i].vlan_id = 0;
7212 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7213 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7214 vsi->vlan_num, &f->mac_info.mac_addr);
7215 if (ret != I40E_SUCCESS)
7217 for (j = i; j < i + vsi->vlan_num; j++)
7218 mv_f[j].filter_type = f->mac_info.filter_type;
7223 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7231 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7233 struct i40e_macvlan_filter *mv_f;
7235 int ret = I40E_SUCCESS;
7237 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7238 return I40E_ERR_PARAM;
7240 /* If it's already set, just return */
7241 if (i40e_find_vlan_filter(vsi,vlan))
7242 return I40E_SUCCESS;
7244 mac_num = vsi->mac_num;
7247 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7248 return I40E_ERR_PARAM;
7251 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7254 PMD_DRV_LOG(ERR, "failed to allocate memory");
7255 return I40E_ERR_NO_MEMORY;
7258 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7260 if (ret != I40E_SUCCESS)
7263 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7265 if (ret != I40E_SUCCESS)
7268 i40e_set_vlan_filter(vsi, vlan, 1);
7278 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7280 struct i40e_macvlan_filter *mv_f;
7282 int ret = I40E_SUCCESS;
7285 * Vlan 0 is the generic filter for untagged packets
7286 * and can't be removed.
7288 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7289 return I40E_ERR_PARAM;
7291 /* If can't find it, just return */
7292 if (!i40e_find_vlan_filter(vsi, vlan))
7293 return I40E_ERR_PARAM;
7295 mac_num = vsi->mac_num;
7298 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7299 return I40E_ERR_PARAM;
7302 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7305 PMD_DRV_LOG(ERR, "failed to allocate memory");
7306 return I40E_ERR_NO_MEMORY;
7309 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7311 if (ret != I40E_SUCCESS)
7314 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7316 if (ret != I40E_SUCCESS)
7319 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7320 if (vsi->vlan_num == 1) {
7321 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7322 if (ret != I40E_SUCCESS)
7325 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7326 if (ret != I40E_SUCCESS)
7330 i40e_set_vlan_filter(vsi, vlan, 0);
7340 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7342 struct i40e_mac_filter *f;
7343 struct i40e_macvlan_filter *mv_f;
7344 int i, vlan_num = 0;
7345 int ret = I40E_SUCCESS;
7347 /* If it's add and we've config it, return */
7348 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7350 return I40E_SUCCESS;
7351 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7352 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7355 * If vlan_num is 0, that's the first time to add mac,
7356 * set mask for vlan_id 0.
7358 if (vsi->vlan_num == 0) {
7359 i40e_set_vlan_filter(vsi, 0, 1);
7362 vlan_num = vsi->vlan_num;
7363 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7364 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7367 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7369 PMD_DRV_LOG(ERR, "failed to allocate memory");
7370 return I40E_ERR_NO_MEMORY;
7373 for (i = 0; i < vlan_num; i++) {
7374 mv_f[i].filter_type = mac_filter->filter_type;
7375 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7379 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7380 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7381 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7382 &mac_filter->mac_addr);
7383 if (ret != I40E_SUCCESS)
7387 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7388 if (ret != I40E_SUCCESS)
7391 /* Add the mac addr into mac list */
7392 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7394 PMD_DRV_LOG(ERR, "failed to allocate memory");
7395 ret = I40E_ERR_NO_MEMORY;
7398 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7400 f->mac_info.filter_type = mac_filter->filter_type;
7401 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7412 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7414 struct i40e_mac_filter *f;
7415 struct i40e_macvlan_filter *mv_f;
7417 enum rte_mac_filter_type filter_type;
7418 int ret = I40E_SUCCESS;
7420 /* Can't find it, return an error */
7421 f = i40e_find_mac_filter(vsi, addr);
7423 return I40E_ERR_PARAM;
7425 vlan_num = vsi->vlan_num;
7426 filter_type = f->mac_info.filter_type;
7427 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7428 filter_type == RTE_MACVLAN_HASH_MATCH) {
7429 if (vlan_num == 0) {
7430 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7431 return I40E_ERR_PARAM;
7433 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7434 filter_type == RTE_MAC_HASH_MATCH)
7437 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7439 PMD_DRV_LOG(ERR, "failed to allocate memory");
7440 return I40E_ERR_NO_MEMORY;
7443 for (i = 0; i < vlan_num; i++) {
7444 mv_f[i].filter_type = filter_type;
7445 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7448 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7449 filter_type == RTE_MACVLAN_HASH_MATCH) {
7450 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7451 if (ret != I40E_SUCCESS)
7455 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7456 if (ret != I40E_SUCCESS)
7459 /* Remove the mac addr into mac list */
7460 TAILQ_REMOVE(&vsi->mac_list, f, next);
7470 /* Configure hash enable flags for RSS */
7472 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7480 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7481 if (flags & (1ULL << i))
7482 hena |= adapter->pctypes_tbl[i];
7488 /* Parse the hash enable flags */
7490 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7492 uint64_t rss_hf = 0;
7498 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7499 if (flags & adapter->pctypes_tbl[i])
7500 rss_hf |= (1ULL << i);
7507 i40e_pf_disable_rss(struct i40e_pf *pf)
7509 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7511 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7512 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7513 I40E_WRITE_FLUSH(hw);
7517 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7519 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7520 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7521 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7522 I40E_VFQF_HKEY_MAX_INDEX :
7523 I40E_PFQF_HKEY_MAX_INDEX;
7526 if (!key || key_len == 0) {
7527 PMD_DRV_LOG(DEBUG, "No key to be configured");
7529 } else if (key_len != (key_idx + 1) *
7531 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7535 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7536 struct i40e_aqc_get_set_rss_key_data *key_dw =
7537 (struct i40e_aqc_get_set_rss_key_data *)key;
7539 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7541 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7543 uint32_t *hash_key = (uint32_t *)key;
7546 if (vsi->type == I40E_VSI_SRIOV) {
7547 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7550 I40E_VFQF_HKEY1(i, vsi->user_param),
7554 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7555 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7558 I40E_WRITE_FLUSH(hw);
7565 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7567 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7568 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7572 if (!key || !key_len)
7575 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7576 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7577 (struct i40e_aqc_get_set_rss_key_data *)key);
7579 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7583 uint32_t *key_dw = (uint32_t *)key;
7586 if (vsi->type == I40E_VSI_SRIOV) {
7587 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7588 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7589 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7591 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7594 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7595 reg = I40E_PFQF_HKEY(i);
7596 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7598 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7606 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7612 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7613 rss_conf->rss_key_len);
7617 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7618 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7619 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7620 I40E_WRITE_FLUSH(hw);
7626 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7627 struct rte_eth_rss_conf *rss_conf)
7629 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7631 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7634 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7635 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7637 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7638 if (rss_hf != 0) /* Enable RSS */
7640 return 0; /* Nothing to do */
7643 if (rss_hf == 0) /* Disable RSS */
7646 return i40e_hw_rss_hash_set(pf, rss_conf);
7650 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7651 struct rte_eth_rss_conf *rss_conf)
7653 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7654 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7661 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7662 &rss_conf->rss_key_len);
7666 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7667 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7668 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7674 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7676 switch (filter_type) {
7677 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7678 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7680 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7681 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7683 case RTE_TUNNEL_FILTER_IMAC_TENID:
7684 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7686 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7687 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7689 case ETH_TUNNEL_FILTER_IMAC:
7690 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7692 case ETH_TUNNEL_FILTER_OIP:
7693 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7695 case ETH_TUNNEL_FILTER_IIP:
7696 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7699 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7706 /* Convert tunnel filter structure */
7708 i40e_tunnel_filter_convert(
7709 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7710 struct i40e_tunnel_filter *tunnel_filter)
7712 rte_ether_addr_copy((struct rte_ether_addr *)
7713 &cld_filter->element.outer_mac,
7714 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7715 rte_ether_addr_copy((struct rte_ether_addr *)
7716 &cld_filter->element.inner_mac,
7717 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7718 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7719 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7720 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7721 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7722 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7724 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7725 tunnel_filter->input.flags = cld_filter->element.flags;
7726 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7727 tunnel_filter->queue = cld_filter->element.queue_number;
7728 rte_memcpy(tunnel_filter->input.general_fields,
7729 cld_filter->general_fields,
7730 sizeof(cld_filter->general_fields));
7735 /* Check if there exists the tunnel filter */
7736 struct i40e_tunnel_filter *
7737 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7738 const struct i40e_tunnel_filter_input *input)
7742 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7746 return tunnel_rule->hash_map[ret];
7749 /* Add a tunnel filter into the SW list */
7751 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7752 struct i40e_tunnel_filter *tunnel_filter)
7754 struct i40e_tunnel_rule *rule = &pf->tunnel;
7757 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7760 "Failed to insert tunnel filter to hash table %d!",
7764 rule->hash_map[ret] = tunnel_filter;
7766 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7771 /* Delete a tunnel filter from the SW list */
7773 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7774 struct i40e_tunnel_filter_input *input)
7776 struct i40e_tunnel_rule *rule = &pf->tunnel;
7777 struct i40e_tunnel_filter *tunnel_filter;
7780 ret = rte_hash_del_key(rule->hash_table, input);
7783 "Failed to delete tunnel filter to hash table %d!",
7787 tunnel_filter = rule->hash_map[ret];
7788 rule->hash_map[ret] = NULL;
7790 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7791 rte_free(tunnel_filter);
7797 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7798 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7802 uint32_t ipv4_addr, ipv4_addr_le;
7803 uint8_t i, tun_type = 0;
7804 /* internal varialbe to convert ipv6 byte order */
7805 uint32_t convert_ipv6[4];
7807 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7808 struct i40e_vsi *vsi = pf->main_vsi;
7809 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7810 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7811 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7812 struct i40e_tunnel_filter *tunnel, *node;
7813 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7815 cld_filter = rte_zmalloc("tunnel_filter",
7816 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7819 if (NULL == cld_filter) {
7820 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7823 pfilter = cld_filter;
7825 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7826 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7827 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7828 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7830 pfilter->element.inner_vlan =
7831 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7832 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7833 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7834 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7835 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7836 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7838 sizeof(pfilter->element.ipaddr.v4.data));
7840 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7841 for (i = 0; i < 4; i++) {
7843 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7845 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7847 sizeof(pfilter->element.ipaddr.v6.data));
7850 /* check tunneled type */
7851 switch (tunnel_filter->tunnel_type) {
7852 case RTE_TUNNEL_TYPE_VXLAN:
7853 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7855 case RTE_TUNNEL_TYPE_NVGRE:
7856 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7858 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7859 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7861 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7862 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7865 /* Other tunnel types is not supported. */
7866 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7867 rte_free(cld_filter);
7871 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7872 &pfilter->element.flags);
7874 rte_free(cld_filter);
7878 pfilter->element.flags |= rte_cpu_to_le_16(
7879 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7880 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7881 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7882 pfilter->element.queue_number =
7883 rte_cpu_to_le_16(tunnel_filter->queue_id);
7885 /* Check if there is the filter in SW list */
7886 memset(&check_filter, 0, sizeof(check_filter));
7887 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7888 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7890 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7891 rte_free(cld_filter);
7895 if (!add && !node) {
7896 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7897 rte_free(cld_filter);
7902 ret = i40e_aq_add_cloud_filters(hw,
7903 vsi->seid, &cld_filter->element, 1);
7905 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7906 rte_free(cld_filter);
7909 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7910 if (tunnel == NULL) {
7911 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7912 rte_free(cld_filter);
7916 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7917 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7921 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7922 &cld_filter->element, 1);
7924 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7925 rte_free(cld_filter);
7928 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7931 rte_free(cld_filter);
7935 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7936 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7937 #define I40E_TR_GENEVE_KEY_MASK 0x8
7938 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7939 #define I40E_TR_GRE_KEY_MASK 0x400
7940 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7941 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7942 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7943 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7944 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7945 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7946 #define I40E_TR_L4_TYPE_TCP 0x2
7947 #define I40E_TR_L4_TYPE_UDP 0x4
7948 #define I40E_TR_L4_TYPE_SCTP 0x8
7951 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7953 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7954 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7956 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7957 enum i40e_status_code status = I40E_SUCCESS;
7959 if (pf->support_multi_driver) {
7960 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7961 return I40E_NOT_SUPPORTED;
7964 memset(&filter_replace, 0,
7965 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7966 memset(&filter_replace_buf, 0,
7967 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7969 /* create L1 filter */
7970 filter_replace.old_filter_type =
7971 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7972 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7973 filter_replace.tr_bit = 0;
7975 /* Prepare the buffer, 3 entries */
7976 filter_replace_buf.data[0] =
7977 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7978 filter_replace_buf.data[0] |=
7979 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7980 filter_replace_buf.data[2] = 0xFF;
7981 filter_replace_buf.data[3] = 0xFF;
7982 filter_replace_buf.data[4] =
7983 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7984 filter_replace_buf.data[4] |=
7985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7986 filter_replace_buf.data[7] = 0xF0;
7987 filter_replace_buf.data[8]
7988 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7989 filter_replace_buf.data[8] |=
7990 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7991 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7992 I40E_TR_GENEVE_KEY_MASK |
7993 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7994 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7995 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7996 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7998 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7999 &filter_replace_buf);
8000 if (!status && (filter_replace.old_filter_type !=
8001 filter_replace.new_filter_type))
8002 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8003 " original: 0x%x, new: 0x%x",
8005 filter_replace.old_filter_type,
8006 filter_replace.new_filter_type);
8012 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8014 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8015 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8016 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8017 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8018 enum i40e_status_code status = I40E_SUCCESS;
8020 if (pf->support_multi_driver) {
8021 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8022 return I40E_NOT_SUPPORTED;
8026 memset(&filter_replace, 0,
8027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8028 memset(&filter_replace_buf, 0,
8029 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8030 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8031 I40E_AQC_MIRROR_CLOUD_FILTER;
8032 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8033 filter_replace.new_filter_type =
8034 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8035 /* Prepare the buffer, 2 entries */
8036 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8037 filter_replace_buf.data[0] |=
8038 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8039 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8040 filter_replace_buf.data[4] |=
8041 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8042 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8043 &filter_replace_buf);
8046 if (filter_replace.old_filter_type !=
8047 filter_replace.new_filter_type)
8048 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8049 " original: 0x%x, new: 0x%x",
8051 filter_replace.old_filter_type,
8052 filter_replace.new_filter_type);
8055 memset(&filter_replace, 0,
8056 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8057 memset(&filter_replace_buf, 0,
8058 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8060 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8061 I40E_AQC_MIRROR_CLOUD_FILTER;
8062 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8063 filter_replace.new_filter_type =
8064 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8065 /* Prepare the buffer, 2 entries */
8066 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8067 filter_replace_buf.data[0] |=
8068 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8069 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8070 filter_replace_buf.data[4] |=
8071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8073 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8074 &filter_replace_buf);
8075 if (!status && (filter_replace.old_filter_type !=
8076 filter_replace.new_filter_type))
8077 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8078 " original: 0x%x, new: 0x%x",
8080 filter_replace.old_filter_type,
8081 filter_replace.new_filter_type);
8086 static enum i40e_status_code
8087 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8089 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8090 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8091 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8092 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8093 enum i40e_status_code status = I40E_SUCCESS;
8095 if (pf->support_multi_driver) {
8096 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8097 return I40E_NOT_SUPPORTED;
8101 memset(&filter_replace, 0,
8102 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8103 memset(&filter_replace_buf, 0,
8104 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8105 /* create L1 filter */
8106 filter_replace.old_filter_type =
8107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8108 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8109 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8110 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111 /* Prepare the buffer, 2 entries */
8112 filter_replace_buf.data[0] =
8113 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8114 filter_replace_buf.data[0] |=
8115 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8116 filter_replace_buf.data[2] = 0xFF;
8117 filter_replace_buf.data[3] = 0xFF;
8118 filter_replace_buf.data[4] =
8119 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8120 filter_replace_buf.data[4] |=
8121 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8122 filter_replace_buf.data[6] = 0xFF;
8123 filter_replace_buf.data[7] = 0xFF;
8124 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8125 &filter_replace_buf);
8128 if (filter_replace.old_filter_type !=
8129 filter_replace.new_filter_type)
8130 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8131 " original: 0x%x, new: 0x%x",
8133 filter_replace.old_filter_type,
8134 filter_replace.new_filter_type);
8137 memset(&filter_replace, 0,
8138 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8139 memset(&filter_replace_buf, 0,
8140 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8141 /* create L1 filter */
8142 filter_replace.old_filter_type =
8143 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8144 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8145 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8146 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8147 /* Prepare the buffer, 2 entries */
8148 filter_replace_buf.data[0] =
8149 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8150 filter_replace_buf.data[0] |=
8151 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8152 filter_replace_buf.data[2] = 0xFF;
8153 filter_replace_buf.data[3] = 0xFF;
8154 filter_replace_buf.data[4] =
8155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8156 filter_replace_buf.data[4] |=
8157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8158 filter_replace_buf.data[6] = 0xFF;
8159 filter_replace_buf.data[7] = 0xFF;
8161 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8162 &filter_replace_buf);
8163 if (!status && (filter_replace.old_filter_type !=
8164 filter_replace.new_filter_type))
8165 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8166 " original: 0x%x, new: 0x%x",
8168 filter_replace.old_filter_type,
8169 filter_replace.new_filter_type);
8175 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8177 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8178 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8180 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8181 enum i40e_status_code status = I40E_SUCCESS;
8183 if (pf->support_multi_driver) {
8184 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8185 return I40E_NOT_SUPPORTED;
8189 memset(&filter_replace, 0,
8190 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8191 memset(&filter_replace_buf, 0,
8192 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8193 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8194 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8195 filter_replace.new_filter_type =
8196 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8197 /* Prepare the buffer, 2 entries */
8198 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8199 filter_replace_buf.data[0] |=
8200 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8201 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8202 filter_replace_buf.data[4] |=
8203 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8204 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8205 &filter_replace_buf);
8208 if (filter_replace.old_filter_type !=
8209 filter_replace.new_filter_type)
8210 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8211 " original: 0x%x, new: 0x%x",
8213 filter_replace.old_filter_type,
8214 filter_replace.new_filter_type);
8217 memset(&filter_replace, 0,
8218 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8219 memset(&filter_replace_buf, 0,
8220 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8221 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8222 filter_replace.old_filter_type =
8223 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8224 filter_replace.new_filter_type =
8225 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8226 /* Prepare the buffer, 2 entries */
8227 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8228 filter_replace_buf.data[0] |=
8229 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8230 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8231 filter_replace_buf.data[4] |=
8232 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8234 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8235 &filter_replace_buf);
8236 if (!status && (filter_replace.old_filter_type !=
8237 filter_replace.new_filter_type))
8238 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8239 " original: 0x%x, new: 0x%x",
8241 filter_replace.old_filter_type,
8242 filter_replace.new_filter_type);
8247 static enum i40e_status_code
8248 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8249 enum i40e_l4_port_type l4_port_type)
8251 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8252 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8253 enum i40e_status_code status = I40E_SUCCESS;
8254 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8255 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8257 if (pf->support_multi_driver) {
8258 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8259 return I40E_NOT_SUPPORTED;
8262 memset(&filter_replace, 0,
8263 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8264 memset(&filter_replace_buf, 0,
8265 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8267 /* create L1 filter */
8268 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8269 filter_replace.old_filter_type =
8270 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8271 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8272 filter_replace_buf.data[8] =
8273 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8275 filter_replace.old_filter_type =
8276 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8277 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8278 filter_replace_buf.data[8] =
8279 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8282 filter_replace.tr_bit = 0;
8283 /* Prepare the buffer, 3 entries */
8284 filter_replace_buf.data[0] =
8285 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8286 filter_replace_buf.data[0] |=
8287 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8288 filter_replace_buf.data[2] = 0x00;
8289 filter_replace_buf.data[3] =
8290 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8291 filter_replace_buf.data[4] =
8292 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8293 filter_replace_buf.data[4] |=
8294 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8295 filter_replace_buf.data[5] = 0x00;
8296 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8297 I40E_TR_L4_TYPE_TCP |
8298 I40E_TR_L4_TYPE_SCTP;
8299 filter_replace_buf.data[7] = 0x00;
8300 filter_replace_buf.data[8] |=
8301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8302 filter_replace_buf.data[9] = 0x00;
8303 filter_replace_buf.data[10] = 0xFF;
8304 filter_replace_buf.data[11] = 0xFF;
8306 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8307 &filter_replace_buf);
8308 if (!status && filter_replace.old_filter_type !=
8309 filter_replace.new_filter_type)
8310 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8311 " original: 0x%x, new: 0x%x",
8313 filter_replace.old_filter_type,
8314 filter_replace.new_filter_type);
8319 static enum i40e_status_code
8320 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8321 enum i40e_l4_port_type l4_port_type)
8323 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8324 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8325 enum i40e_status_code status = I40E_SUCCESS;
8326 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8327 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8329 if (pf->support_multi_driver) {
8330 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8331 return I40E_NOT_SUPPORTED;
8334 memset(&filter_replace, 0,
8335 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8336 memset(&filter_replace_buf, 0,
8337 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8339 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8340 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8341 filter_replace.new_filter_type =
8342 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8343 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8345 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8346 filter_replace.new_filter_type =
8347 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8348 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8351 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8352 filter_replace.tr_bit = 0;
8353 /* Prepare the buffer, 2 entries */
8354 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8355 filter_replace_buf.data[0] |=
8356 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8357 filter_replace_buf.data[4] |=
8358 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8359 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8360 &filter_replace_buf);
8362 if (!status && filter_replace.old_filter_type !=
8363 filter_replace.new_filter_type)
8364 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8365 " original: 0x%x, new: 0x%x",
8367 filter_replace.old_filter_type,
8368 filter_replace.new_filter_type);
8374 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8375 struct i40e_tunnel_filter_conf *tunnel_filter,
8379 uint32_t ipv4_addr, ipv4_addr_le;
8380 uint8_t i, tun_type = 0;
8381 /* internal variable to convert ipv6 byte order */
8382 uint32_t convert_ipv6[4];
8384 struct i40e_pf_vf *vf = NULL;
8385 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8386 struct i40e_vsi *vsi;
8387 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8388 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8389 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8390 struct i40e_tunnel_filter *tunnel, *node;
8391 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8393 bool big_buffer = 0;
8395 cld_filter = rte_zmalloc("tunnel_filter",
8396 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8399 if (cld_filter == NULL) {
8400 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8403 pfilter = cld_filter;
8405 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8406 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8407 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8408 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8410 pfilter->element.inner_vlan =
8411 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8412 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8413 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8414 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8415 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8416 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8418 sizeof(pfilter->element.ipaddr.v4.data));
8420 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8421 for (i = 0; i < 4; i++) {
8423 rte_cpu_to_le_32(rte_be_to_cpu_32(
8424 tunnel_filter->ip_addr.ipv6_addr[i]));
8426 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8428 sizeof(pfilter->element.ipaddr.v6.data));
8431 /* check tunneled type */
8432 switch (tunnel_filter->tunnel_type) {
8433 case I40E_TUNNEL_TYPE_VXLAN:
8434 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8436 case I40E_TUNNEL_TYPE_NVGRE:
8437 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8439 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8440 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8442 case I40E_TUNNEL_TYPE_MPLSoUDP:
8443 if (!pf->mpls_replace_flag) {
8444 i40e_replace_mpls_l1_filter(pf);
8445 i40e_replace_mpls_cloud_filter(pf);
8446 pf->mpls_replace_flag = 1;
8448 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8449 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8451 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8452 (teid_le & 0xF) << 12;
8453 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8456 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8458 case I40E_TUNNEL_TYPE_MPLSoGRE:
8459 if (!pf->mpls_replace_flag) {
8460 i40e_replace_mpls_l1_filter(pf);
8461 i40e_replace_mpls_cloud_filter(pf);
8462 pf->mpls_replace_flag = 1;
8464 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8465 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8467 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8468 (teid_le & 0xF) << 12;
8469 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8472 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8474 case I40E_TUNNEL_TYPE_GTPC:
8475 if (!pf->gtp_replace_flag) {
8476 i40e_replace_gtp_l1_filter(pf);
8477 i40e_replace_gtp_cloud_filter(pf);
8478 pf->gtp_replace_flag = 1;
8480 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8481 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8482 (teid_le >> 16) & 0xFFFF;
8483 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8485 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8489 case I40E_TUNNEL_TYPE_GTPU:
8490 if (!pf->gtp_replace_flag) {
8491 i40e_replace_gtp_l1_filter(pf);
8492 i40e_replace_gtp_cloud_filter(pf);
8493 pf->gtp_replace_flag = 1;
8495 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8496 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8497 (teid_le >> 16) & 0xFFFF;
8498 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8500 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8504 case I40E_TUNNEL_TYPE_QINQ:
8505 if (!pf->qinq_replace_flag) {
8506 ret = i40e_cloud_filter_qinq_create(pf);
8509 "QinQ tunnel filter already created.");
8510 pf->qinq_replace_flag = 1;
8512 /* Add in the General fields the values of
8513 * the Outer and Inner VLAN
8514 * Big Buffer should be set, see changes in
8515 * i40e_aq_add_cloud_filters
8517 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8518 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8521 case I40E_CLOUD_TYPE_UDP:
8522 case I40E_CLOUD_TYPE_TCP:
8523 case I40E_CLOUD_TYPE_SCTP:
8524 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8525 if (!pf->sport_replace_flag) {
8526 i40e_replace_port_l1_filter(pf,
8527 tunnel_filter->l4_port_type);
8528 i40e_replace_port_cloud_filter(pf,
8529 tunnel_filter->l4_port_type);
8530 pf->sport_replace_flag = 1;
8532 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8533 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8534 I40E_DIRECTION_INGRESS_KEY;
8536 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8537 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8538 I40E_TR_L4_TYPE_UDP;
8539 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8540 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8541 I40E_TR_L4_TYPE_TCP;
8543 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8544 I40E_TR_L4_TYPE_SCTP;
8546 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8547 (teid_le >> 16) & 0xFFFF;
8550 if (!pf->dport_replace_flag) {
8551 i40e_replace_port_l1_filter(pf,
8552 tunnel_filter->l4_port_type);
8553 i40e_replace_port_cloud_filter(pf,
8554 tunnel_filter->l4_port_type);
8555 pf->dport_replace_flag = 1;
8557 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8558 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8559 I40E_DIRECTION_INGRESS_KEY;
8561 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8562 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8563 I40E_TR_L4_TYPE_UDP;
8564 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8565 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8566 I40E_TR_L4_TYPE_TCP;
8568 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8569 I40E_TR_L4_TYPE_SCTP;
8571 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8572 (teid_le >> 16) & 0xFFFF;
8578 /* Other tunnel types is not supported. */
8579 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8580 rte_free(cld_filter);
8584 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8585 pfilter->element.flags =
8586 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8587 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8588 pfilter->element.flags =
8589 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8590 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8591 pfilter->element.flags =
8592 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8593 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8594 pfilter->element.flags =
8595 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8596 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8597 pfilter->element.flags |=
8598 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8599 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8600 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8601 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8602 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8603 pfilter->element.flags |=
8604 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8606 pfilter->element.flags |=
8607 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8609 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8610 &pfilter->element.flags);
8612 rte_free(cld_filter);
8617 pfilter->element.flags |= rte_cpu_to_le_16(
8618 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8619 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8620 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8621 pfilter->element.queue_number =
8622 rte_cpu_to_le_16(tunnel_filter->queue_id);
8624 if (!tunnel_filter->is_to_vf)
8627 if (tunnel_filter->vf_id >= pf->vf_num) {
8628 PMD_DRV_LOG(ERR, "Invalid argument.");
8629 rte_free(cld_filter);
8632 vf = &pf->vfs[tunnel_filter->vf_id];
8636 /* Check if there is the filter in SW list */
8637 memset(&check_filter, 0, sizeof(check_filter));
8638 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8639 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8640 check_filter.vf_id = tunnel_filter->vf_id;
8641 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8643 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8644 rte_free(cld_filter);
8648 if (!add && !node) {
8649 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8650 rte_free(cld_filter);
8656 ret = i40e_aq_add_cloud_filters_bb(hw,
8657 vsi->seid, cld_filter, 1);
8659 ret = i40e_aq_add_cloud_filters(hw,
8660 vsi->seid, &cld_filter->element, 1);
8662 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8663 rte_free(cld_filter);
8666 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8667 if (tunnel == NULL) {
8668 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8669 rte_free(cld_filter);
8673 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8674 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8679 ret = i40e_aq_rem_cloud_filters_bb(
8680 hw, vsi->seid, cld_filter, 1);
8682 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8683 &cld_filter->element, 1);
8685 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8686 rte_free(cld_filter);
8689 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8692 rte_free(cld_filter);
8697 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8701 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8702 if (pf->vxlan_ports[i] == port)
8710 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8713 uint8_t filter_idx = 0;
8714 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8716 idx = i40e_get_vxlan_port_idx(pf, port);
8718 /* Check if port already exists */
8720 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8724 /* Now check if there is space to add the new port */
8725 idx = i40e_get_vxlan_port_idx(pf, 0);
8728 "Maximum number of UDP ports reached, not adding port %d",
8733 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8736 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8740 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8743 /* New port: add it and mark its index in the bitmap */
8744 pf->vxlan_ports[idx] = port;
8745 pf->vxlan_bitmap |= (1 << idx);
8747 if (!(pf->flags & I40E_FLAG_VXLAN))
8748 pf->flags |= I40E_FLAG_VXLAN;
8754 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8757 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8759 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8760 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8764 idx = i40e_get_vxlan_port_idx(pf, port);
8767 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8771 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8772 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8776 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8779 pf->vxlan_ports[idx] = 0;
8780 pf->vxlan_bitmap &= ~(1 << idx);
8782 if (!pf->vxlan_bitmap)
8783 pf->flags &= ~I40E_FLAG_VXLAN;
8788 /* Add UDP tunneling port */
8790 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8791 struct rte_eth_udp_tunnel *udp_tunnel)
8794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8796 if (udp_tunnel == NULL)
8799 switch (udp_tunnel->prot_type) {
8800 case RTE_TUNNEL_TYPE_VXLAN:
8801 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8802 I40E_AQC_TUNNEL_TYPE_VXLAN);
8804 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8805 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8806 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8808 case RTE_TUNNEL_TYPE_GENEVE:
8809 case RTE_TUNNEL_TYPE_TEREDO:
8810 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8815 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8823 /* Remove UDP tunneling port */
8825 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8826 struct rte_eth_udp_tunnel *udp_tunnel)
8829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8831 if (udp_tunnel == NULL)
8834 switch (udp_tunnel->prot_type) {
8835 case RTE_TUNNEL_TYPE_VXLAN:
8836 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8837 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8839 case RTE_TUNNEL_TYPE_GENEVE:
8840 case RTE_TUNNEL_TYPE_TEREDO:
8841 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8845 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8853 /* Calculate the maximum number of contiguous PF queues that are configured */
8855 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8857 struct rte_eth_dev_data *data = pf->dev_data;
8859 struct i40e_rx_queue *rxq;
8862 for (i = 0; i < pf->lan_nb_qps; i++) {
8863 rxq = data->rx_queues[i];
8864 if (rxq && rxq->q_set)
8875 i40e_pf_config_rss(struct i40e_pf *pf)
8877 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8878 struct rte_eth_rss_conf rss_conf;
8879 uint32_t i, lut = 0;
8883 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8884 * It's necessary to calculate the actual PF queues that are configured.
8886 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8887 num = i40e_pf_calc_configured_queues_num(pf);
8889 num = pf->dev_data->nb_rx_queues;
8891 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8892 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8897 "No PF queues are configured to enable RSS for port %u",
8898 pf->dev_data->port_id);
8902 if (pf->adapter->rss_reta_updated == 0) {
8903 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8906 lut = (lut << 8) | (j & ((0x1 <<
8907 hw->func_caps.rss_table_entry_width) - 1));
8909 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8914 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8915 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8916 i40e_pf_disable_rss(pf);
8919 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8920 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8921 /* Random default keys */
8922 static uint32_t rss_key_default[] = {0x6b793944,
8923 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8924 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8925 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8927 rss_conf.rss_key = (uint8_t *)rss_key_default;
8928 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8932 return i40e_hw_rss_hash_set(pf, &rss_conf);
8936 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8937 struct rte_eth_tunnel_filter_conf *filter)
8939 if (pf == NULL || filter == NULL) {
8940 PMD_DRV_LOG(ERR, "Invalid parameter");
8944 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8945 PMD_DRV_LOG(ERR, "Invalid queue ID");
8949 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8950 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8954 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8955 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8956 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8960 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8961 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8962 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8969 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8970 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8972 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8974 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8978 if (pf->support_multi_driver) {
8979 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8983 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8984 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8987 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8988 } else if (len == 4) {
8989 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8991 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8996 ret = i40e_aq_debug_write_global_register(hw,
8997 I40E_GL_PRS_FVBM(2),
9001 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9002 "with value 0x%08x",
9003 I40E_GL_PRS_FVBM(2), reg);
9007 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9008 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9014 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9021 switch (cfg->cfg_type) {
9022 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9023 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9026 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9034 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9035 enum rte_filter_op filter_op,
9038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9039 int ret = I40E_ERR_PARAM;
9041 switch (filter_op) {
9042 case RTE_ETH_FILTER_SET:
9043 ret = i40e_dev_global_config_set(hw,
9044 (struct rte_eth_global_cfg *)arg);
9047 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9055 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9056 enum rte_filter_op filter_op,
9059 struct rte_eth_tunnel_filter_conf *filter;
9060 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9061 int ret = I40E_SUCCESS;
9063 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9065 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9066 return I40E_ERR_PARAM;
9068 switch (filter_op) {
9069 case RTE_ETH_FILTER_NOP:
9070 if (!(pf->flags & I40E_FLAG_VXLAN))
9071 ret = I40E_NOT_SUPPORTED;
9073 case RTE_ETH_FILTER_ADD:
9074 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9076 case RTE_ETH_FILTER_DELETE:
9077 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9080 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9081 ret = I40E_ERR_PARAM;
9089 i40e_pf_config_mq_rx(struct i40e_pf *pf)
9092 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9095 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
9096 ret = i40e_pf_config_rss(pf);
9098 i40e_pf_disable_rss(pf);
9103 /* Get the symmetric hash enable configurations per port */
9105 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9107 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9109 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9112 /* Set the symmetric hash enable configurations per port */
9114 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9116 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9119 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9121 "Symmetric hash has already been enabled");
9124 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9126 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9128 "Symmetric hash has already been disabled");
9131 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9133 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9134 I40E_WRITE_FLUSH(hw);
9138 * Get global configurations of hash function type and symmetric hash enable
9139 * per flow type (pctype). Note that global configuration means it affects all
9140 * the ports on the same NIC.
9143 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9144 struct rte_eth_hash_global_conf *g_cfg)
9146 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9150 memset(g_cfg, 0, sizeof(*g_cfg));
9151 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9152 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9153 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9155 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9156 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9157 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9160 * As i40e supports less than 64 flow types, only first 64 bits need to
9163 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9164 g_cfg->valid_bit_mask[i] = 0ULL;
9165 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9168 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9170 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9171 if (!adapter->pctypes_tbl[i])
9173 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9174 j < I40E_FILTER_PCTYPE_MAX; j++) {
9175 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9176 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9177 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9178 g_cfg->sym_hash_enable_mask[0] |=
9189 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9190 const struct rte_eth_hash_global_conf *g_cfg)
9193 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9195 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9196 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9197 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9198 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9204 * As i40e supports less than 64 flow types, only first 64 bits need to
9207 mask0 = g_cfg->valid_bit_mask[0];
9208 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9210 /* Check if any unsupported flow type configured */
9211 if ((mask0 | i40e_mask) ^ i40e_mask)
9214 if (g_cfg->valid_bit_mask[i])
9222 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9228 * Set global configurations of hash function type and symmetric hash enable
9229 * per flow type (pctype). Note any modifying global configuration will affect
9230 * all the ports on the same NIC.
9233 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9234 struct rte_eth_hash_global_conf *g_cfg)
9236 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9237 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9241 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9243 if (pf->support_multi_driver) {
9244 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9248 /* Check the input parameters */
9249 ret = i40e_hash_global_config_check(adapter, g_cfg);
9254 * As i40e supports less than 64 flow types, only first 64 bits need to
9257 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9258 if (mask0 & (1UL << i)) {
9259 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9260 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9262 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9263 j < I40E_FILTER_PCTYPE_MAX; j++) {
9264 if (adapter->pctypes_tbl[i] & (1ULL << j))
9265 i40e_write_global_rx_ctl(hw,
9272 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9273 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9275 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9277 "Hash function already set to Toeplitz");
9280 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9281 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9283 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9285 "Hash function already set to Simple XOR");
9288 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9290 /* Use the default, and keep it as it is */
9293 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9296 I40E_WRITE_FLUSH(hw);
9302 * Valid input sets for hash and flow director filters per PCTYPE
9305 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9306 enum rte_filter_type filter)
9310 static const uint64_t valid_hash_inset_table[] = {
9311 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9312 I40E_INSET_DMAC | I40E_INSET_SMAC |
9313 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9314 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9315 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9316 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9317 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9318 I40E_INSET_FLEX_PAYLOAD,
9319 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9320 I40E_INSET_DMAC | I40E_INSET_SMAC |
9321 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9322 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9323 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9324 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9325 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9326 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9327 I40E_INSET_FLEX_PAYLOAD,
9328 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9329 I40E_INSET_DMAC | I40E_INSET_SMAC |
9330 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9331 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9332 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9333 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9334 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9335 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9336 I40E_INSET_FLEX_PAYLOAD,
9337 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9338 I40E_INSET_DMAC | I40E_INSET_SMAC |
9339 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9340 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9341 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9342 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9343 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9344 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9345 I40E_INSET_FLEX_PAYLOAD,
9346 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9347 I40E_INSET_DMAC | I40E_INSET_SMAC |
9348 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9349 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9350 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9351 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9352 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9353 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9354 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9355 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9356 I40E_INSET_DMAC | I40E_INSET_SMAC |
9357 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9358 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9359 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9360 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9361 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9362 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9363 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9364 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9365 I40E_INSET_DMAC | I40E_INSET_SMAC |
9366 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9367 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9368 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9369 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9370 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9371 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9372 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9373 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9374 I40E_INSET_DMAC | I40E_INSET_SMAC |
9375 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9376 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9377 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9378 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9379 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9380 I40E_INSET_FLEX_PAYLOAD,
9381 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9382 I40E_INSET_DMAC | I40E_INSET_SMAC |
9383 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9384 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9385 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9386 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9387 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9388 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9389 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9390 I40E_INSET_DMAC | I40E_INSET_SMAC |
9391 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9392 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9393 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9394 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9395 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9396 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9397 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9398 I40E_INSET_DMAC | I40E_INSET_SMAC |
9399 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9400 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9401 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9402 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9403 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9404 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9405 I40E_INSET_FLEX_PAYLOAD,
9406 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9407 I40E_INSET_DMAC | I40E_INSET_SMAC |
9408 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9409 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9410 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9411 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9412 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9413 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9414 I40E_INSET_FLEX_PAYLOAD,
9415 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9416 I40E_INSET_DMAC | I40E_INSET_SMAC |
9417 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9418 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9419 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9420 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9421 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9422 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9423 I40E_INSET_FLEX_PAYLOAD,
9424 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9425 I40E_INSET_DMAC | I40E_INSET_SMAC |
9426 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9427 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9428 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9429 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9430 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9431 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9432 I40E_INSET_FLEX_PAYLOAD,
9433 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9434 I40E_INSET_DMAC | I40E_INSET_SMAC |
9435 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9436 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9437 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9438 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9439 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9440 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9441 I40E_INSET_FLEX_PAYLOAD,
9442 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9443 I40E_INSET_DMAC | I40E_INSET_SMAC |
9444 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9445 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9446 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9447 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9448 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9449 I40E_INSET_FLEX_PAYLOAD,
9450 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9451 I40E_INSET_DMAC | I40E_INSET_SMAC |
9452 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9453 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9454 I40E_INSET_FLEX_PAYLOAD,
9458 * Flow director supports only fields defined in
9459 * union rte_eth_fdir_flow.
9461 static const uint64_t valid_fdir_inset_table[] = {
9462 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9463 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9464 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9465 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9466 I40E_INSET_IPV4_TTL,
9467 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9468 I40E_INSET_DMAC | I40E_INSET_SMAC |
9469 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9471 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9472 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9473 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9474 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9475 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9476 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9477 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9478 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9479 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9480 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9481 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9482 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9483 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9484 I40E_INSET_DMAC | I40E_INSET_SMAC |
9485 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9486 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9487 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9488 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9489 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9490 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9491 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9492 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9493 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9494 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9496 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9497 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9498 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9500 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9501 I40E_INSET_DMAC | I40E_INSET_SMAC |
9502 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9503 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9504 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9505 I40E_INSET_IPV4_TTL,
9506 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9507 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9508 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9509 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9510 I40E_INSET_IPV6_HOP_LIMIT,
9511 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9512 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9513 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9514 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9515 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9516 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9517 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9518 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9519 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9520 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9521 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9522 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9523 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9524 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9525 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9526 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9527 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9528 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9529 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9530 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9531 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9532 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9533 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9534 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9535 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9536 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9537 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9538 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9539 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9540 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9542 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9543 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9544 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9545 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9546 I40E_INSET_IPV6_HOP_LIMIT,
9547 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9548 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9549 I40E_INSET_LAST_ETHER_TYPE,
9552 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9554 if (filter == RTE_ETH_FILTER_HASH)
9555 valid = valid_hash_inset_table[pctype];
9557 valid = valid_fdir_inset_table[pctype];
9563 * Validate if the input set is allowed for a specific PCTYPE
9566 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9567 enum rte_filter_type filter, uint64_t inset)
9571 valid = i40e_get_valid_input_set(pctype, filter);
9572 if (inset & (~valid))
9578 /* default input set fields combination per pctype */
9580 i40e_get_default_input_set(uint16_t pctype)
9582 static const uint64_t default_inset_table[] = {
9583 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9584 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9585 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9586 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9587 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9588 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9589 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9590 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9591 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9592 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9593 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9594 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9595 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9596 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9597 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9598 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9599 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9600 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9601 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9602 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9604 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9605 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9606 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9607 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9608 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9609 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9610 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9611 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9612 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9613 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9614 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9615 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9616 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9617 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9618 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9619 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9620 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9621 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9622 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9623 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9624 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9625 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9627 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9628 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9629 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9630 I40E_INSET_LAST_ETHER_TYPE,
9633 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9636 return default_inset_table[pctype];
9640 * Parse the input set from index to logical bit masks
9643 i40e_parse_input_set(uint64_t *inset,
9644 enum i40e_filter_pctype pctype,
9645 enum rte_eth_input_set_field *field,
9651 static const struct {
9652 enum rte_eth_input_set_field field;
9654 } inset_convert_table[] = {
9655 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9656 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9657 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9658 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9659 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9660 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9661 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9662 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9663 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9664 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9665 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9666 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9667 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9668 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9669 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9670 I40E_INSET_IPV6_NEXT_HDR},
9671 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9672 I40E_INSET_IPV6_HOP_LIMIT},
9673 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9674 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9675 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9676 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9677 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9678 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9679 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9680 I40E_INSET_SCTP_VT},
9681 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9682 I40E_INSET_TUNNEL_DMAC},
9683 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9684 I40E_INSET_VLAN_TUNNEL},
9685 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9686 I40E_INSET_TUNNEL_ID},
9687 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9688 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9689 I40E_INSET_FLEX_PAYLOAD_W1},
9690 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9691 I40E_INSET_FLEX_PAYLOAD_W2},
9692 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9693 I40E_INSET_FLEX_PAYLOAD_W3},
9694 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9695 I40E_INSET_FLEX_PAYLOAD_W4},
9696 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9697 I40E_INSET_FLEX_PAYLOAD_W5},
9698 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9699 I40E_INSET_FLEX_PAYLOAD_W6},
9700 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9701 I40E_INSET_FLEX_PAYLOAD_W7},
9702 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9703 I40E_INSET_FLEX_PAYLOAD_W8},
9706 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9709 /* Only one item allowed for default or all */
9711 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9712 *inset = i40e_get_default_input_set(pctype);
9714 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9715 *inset = I40E_INSET_NONE;
9720 for (i = 0, *inset = 0; i < size; i++) {
9721 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9722 if (field[i] == inset_convert_table[j].field) {
9723 *inset |= inset_convert_table[j].inset;
9728 /* It contains unsupported input set, return immediately */
9729 if (j == RTE_DIM(inset_convert_table))
9737 * Translate the input set from bit masks to register aware bit masks
9741 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9751 static const struct inset_map inset_map_common[] = {
9752 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9753 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9754 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9755 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9756 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9757 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9758 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9759 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9760 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9761 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9762 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9763 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9764 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9765 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9766 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9767 {I40E_INSET_TUNNEL_DMAC,
9768 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9769 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9770 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9771 {I40E_INSET_TUNNEL_SRC_PORT,
9772 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9773 {I40E_INSET_TUNNEL_DST_PORT,
9774 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9775 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9776 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9777 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9778 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9779 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9780 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9781 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9782 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9783 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9786 /* some different registers map in x722*/
9787 static const struct inset_map inset_map_diff_x722[] = {
9788 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9789 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9790 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9791 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9794 static const struct inset_map inset_map_diff_not_x722[] = {
9795 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9796 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9797 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9798 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9804 /* Translate input set to register aware inset */
9805 if (type == I40E_MAC_X722) {
9806 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9807 if (input & inset_map_diff_x722[i].inset)
9808 val |= inset_map_diff_x722[i].inset_reg;
9811 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9812 if (input & inset_map_diff_not_x722[i].inset)
9813 val |= inset_map_diff_not_x722[i].inset_reg;
9817 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9818 if (input & inset_map_common[i].inset)
9819 val |= inset_map_common[i].inset_reg;
9826 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9829 uint64_t inset_need_mask = inset;
9831 static const struct {
9834 } inset_mask_map[] = {
9835 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9836 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9837 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9838 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9839 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9840 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9841 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9842 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9845 if (!inset || !mask || !nb_elem)
9848 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9849 /* Clear the inset bit, if no MASK is required,
9850 * for example proto + ttl
9852 if ((inset & inset_mask_map[i].inset) ==
9853 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9854 inset_need_mask &= ~inset_mask_map[i].inset;
9855 if (!inset_need_mask)
9858 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9859 if ((inset_need_mask & inset_mask_map[i].inset) ==
9860 inset_mask_map[i].inset) {
9861 if (idx >= nb_elem) {
9862 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9865 mask[idx] = inset_mask_map[i].mask;
9874 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9876 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9878 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9880 i40e_write_rx_ctl(hw, addr, val);
9881 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9882 (uint32_t)i40e_read_rx_ctl(hw, addr));
9886 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9888 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9889 struct rte_eth_dev *dev;
9891 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9893 i40e_write_rx_ctl(hw, addr, val);
9894 PMD_DRV_LOG(WARNING,
9895 "i40e device %s changed global register [0x%08x]."
9896 " original: 0x%08x, new: 0x%08x",
9897 dev->device->name, addr, reg,
9898 (uint32_t)i40e_read_rx_ctl(hw, addr));
9903 i40e_filter_input_set_init(struct i40e_pf *pf)
9905 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9906 enum i40e_filter_pctype pctype;
9907 uint64_t input_set, inset_reg;
9908 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9912 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9913 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9914 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9916 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9919 input_set = i40e_get_default_input_set(pctype);
9921 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9922 I40E_INSET_MASK_NUM_REG);
9925 if (pf->support_multi_driver && num > 0) {
9926 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9929 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9932 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9933 (uint32_t)(inset_reg & UINT32_MAX));
9934 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9935 (uint32_t)((inset_reg >>
9936 I40E_32_BIT_WIDTH) & UINT32_MAX));
9937 if (!pf->support_multi_driver) {
9938 i40e_check_write_global_reg(hw,
9939 I40E_GLQF_HASH_INSET(0, pctype),
9940 (uint32_t)(inset_reg & UINT32_MAX));
9941 i40e_check_write_global_reg(hw,
9942 I40E_GLQF_HASH_INSET(1, pctype),
9943 (uint32_t)((inset_reg >>
9944 I40E_32_BIT_WIDTH) & UINT32_MAX));
9946 for (i = 0; i < num; i++) {
9947 i40e_check_write_global_reg(hw,
9948 I40E_GLQF_FD_MSK(i, pctype),
9950 i40e_check_write_global_reg(hw,
9951 I40E_GLQF_HASH_MSK(i, pctype),
9954 /*clear unused mask registers of the pctype */
9955 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9956 i40e_check_write_global_reg(hw,
9957 I40E_GLQF_FD_MSK(i, pctype),
9959 i40e_check_write_global_reg(hw,
9960 I40E_GLQF_HASH_MSK(i, pctype),
9964 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9966 I40E_WRITE_FLUSH(hw);
9968 /* store the default input set */
9969 if (!pf->support_multi_driver)
9970 pf->hash_input_set[pctype] = input_set;
9971 pf->fdir.input_set[pctype] = input_set;
9976 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9977 struct rte_eth_input_set_conf *conf)
9979 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9980 enum i40e_filter_pctype pctype;
9981 uint64_t input_set, inset_reg = 0;
9982 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9986 PMD_DRV_LOG(ERR, "Invalid pointer");
9989 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9990 conf->op != RTE_ETH_INPUT_SET_ADD) {
9991 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9995 if (pf->support_multi_driver) {
9996 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10000 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10001 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10002 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10006 if (hw->mac.type == I40E_MAC_X722) {
10007 /* get translated pctype value in fd pctype register */
10008 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10009 I40E_GLQF_FD_PCTYPES((int)pctype));
10012 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10015 PMD_DRV_LOG(ERR, "Failed to parse input set");
10019 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10020 /* get inset value in register */
10021 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10022 inset_reg <<= I40E_32_BIT_WIDTH;
10023 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10024 input_set |= pf->hash_input_set[pctype];
10026 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10027 I40E_INSET_MASK_NUM_REG);
10031 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10033 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10034 (uint32_t)(inset_reg & UINT32_MAX));
10035 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10036 (uint32_t)((inset_reg >>
10037 I40E_32_BIT_WIDTH) & UINT32_MAX));
10039 for (i = 0; i < num; i++)
10040 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10042 /*clear unused mask registers of the pctype */
10043 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10044 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10046 I40E_WRITE_FLUSH(hw);
10048 pf->hash_input_set[pctype] = input_set;
10053 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10054 struct rte_eth_input_set_conf *conf)
10056 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10057 enum i40e_filter_pctype pctype;
10058 uint64_t input_set, inset_reg = 0;
10059 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10062 if (!hw || !conf) {
10063 PMD_DRV_LOG(ERR, "Invalid pointer");
10066 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10067 conf->op != RTE_ETH_INPUT_SET_ADD) {
10068 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10072 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10074 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10075 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10079 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10082 PMD_DRV_LOG(ERR, "Failed to parse input set");
10086 /* get inset value in register */
10087 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10088 inset_reg <<= I40E_32_BIT_WIDTH;
10089 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10091 /* Can not change the inset reg for flex payload for fdir,
10092 * it is done by writing I40E_PRTQF_FD_FLXINSET
10093 * in i40e_set_flex_mask_on_pctype.
10095 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10096 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10098 input_set |= pf->fdir.input_set[pctype];
10099 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10100 I40E_INSET_MASK_NUM_REG);
10103 if (pf->support_multi_driver && num > 0) {
10104 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10108 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10110 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10111 (uint32_t)(inset_reg & UINT32_MAX));
10112 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10113 (uint32_t)((inset_reg >>
10114 I40E_32_BIT_WIDTH) & UINT32_MAX));
10116 if (!pf->support_multi_driver) {
10117 for (i = 0; i < num; i++)
10118 i40e_check_write_global_reg(hw,
10119 I40E_GLQF_FD_MSK(i, pctype),
10121 /*clear unused mask registers of the pctype */
10122 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10123 i40e_check_write_global_reg(hw,
10124 I40E_GLQF_FD_MSK(i, pctype),
10127 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10129 I40E_WRITE_FLUSH(hw);
10131 pf->fdir.input_set[pctype] = input_set;
10136 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10140 if (!hw || !info) {
10141 PMD_DRV_LOG(ERR, "Invalid pointer");
10145 switch (info->info_type) {
10146 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10147 i40e_get_symmetric_hash_enable_per_port(hw,
10148 &(info->info.enable));
10150 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10151 ret = i40e_get_hash_filter_global_config(hw,
10152 &(info->info.global_conf));
10155 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10165 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10169 if (!hw || !info) {
10170 PMD_DRV_LOG(ERR, "Invalid pointer");
10174 switch (info->info_type) {
10175 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10176 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10178 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10179 ret = i40e_set_hash_filter_global_config(hw,
10180 &(info->info.global_conf));
10182 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10183 ret = i40e_hash_filter_inset_select(hw,
10184 &(info->info.input_set_conf));
10188 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10197 /* Operations for hash function */
10199 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10200 enum rte_filter_op filter_op,
10203 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10206 switch (filter_op) {
10207 case RTE_ETH_FILTER_NOP:
10209 case RTE_ETH_FILTER_GET:
10210 ret = i40e_hash_filter_get(hw,
10211 (struct rte_eth_hash_filter_info *)arg);
10213 case RTE_ETH_FILTER_SET:
10214 ret = i40e_hash_filter_set(hw,
10215 (struct rte_eth_hash_filter_info *)arg);
10218 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10227 /* Convert ethertype filter structure */
10229 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10230 struct i40e_ethertype_filter *filter)
10232 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10233 RTE_ETHER_ADDR_LEN);
10234 filter->input.ether_type = input->ether_type;
10235 filter->flags = input->flags;
10236 filter->queue = input->queue;
10241 /* Check if there exists the ehtertype filter */
10242 struct i40e_ethertype_filter *
10243 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10244 const struct i40e_ethertype_filter_input *input)
10248 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10252 return ethertype_rule->hash_map[ret];
10255 /* Add ethertype filter in SW list */
10257 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10258 struct i40e_ethertype_filter *filter)
10260 struct i40e_ethertype_rule *rule = &pf->ethertype;
10263 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10266 "Failed to insert ethertype filter"
10267 " to hash table %d!",
10271 rule->hash_map[ret] = filter;
10273 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10278 /* Delete ethertype filter in SW list */
10280 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10281 struct i40e_ethertype_filter_input *input)
10283 struct i40e_ethertype_rule *rule = &pf->ethertype;
10284 struct i40e_ethertype_filter *filter;
10287 ret = rte_hash_del_key(rule->hash_table, input);
10290 "Failed to delete ethertype filter"
10291 " to hash table %d!",
10295 filter = rule->hash_map[ret];
10296 rule->hash_map[ret] = NULL;
10298 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10305 * Configure ethertype filter, which can director packet by filtering
10306 * with mac address and ether_type or only ether_type
10309 i40e_ethertype_filter_set(struct i40e_pf *pf,
10310 struct rte_eth_ethertype_filter *filter,
10313 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10314 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10315 struct i40e_ethertype_filter *ethertype_filter, *node;
10316 struct i40e_ethertype_filter check_filter;
10317 struct i40e_control_filter_stats stats;
10318 uint16_t flags = 0;
10321 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10322 PMD_DRV_LOG(ERR, "Invalid queue ID");
10325 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10326 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10328 "unsupported ether_type(0x%04x) in control packet filter.",
10329 filter->ether_type);
10332 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10333 PMD_DRV_LOG(WARNING,
10334 "filter vlan ether_type in first tag is not supported.");
10336 /* Check if there is the filter in SW list */
10337 memset(&check_filter, 0, sizeof(check_filter));
10338 i40e_ethertype_filter_convert(filter, &check_filter);
10339 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10340 &check_filter.input);
10342 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10346 if (!add && !node) {
10347 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10351 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10352 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10353 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10354 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10355 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10357 memset(&stats, 0, sizeof(stats));
10358 ret = i40e_aq_add_rem_control_packet_filter(hw,
10359 filter->mac_addr.addr_bytes,
10360 filter->ether_type, flags,
10361 pf->main_vsi->seid,
10362 filter->queue, add, &stats, NULL);
10365 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10366 ret, stats.mac_etype_used, stats.etype_used,
10367 stats.mac_etype_free, stats.etype_free);
10371 /* Add or delete a filter in SW list */
10373 ethertype_filter = rte_zmalloc("ethertype_filter",
10374 sizeof(*ethertype_filter), 0);
10375 if (ethertype_filter == NULL) {
10376 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10380 rte_memcpy(ethertype_filter, &check_filter,
10381 sizeof(check_filter));
10382 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10384 rte_free(ethertype_filter);
10386 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10393 * Handle operations for ethertype filter.
10396 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10397 enum rte_filter_op filter_op,
10400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10403 if (filter_op == RTE_ETH_FILTER_NOP)
10407 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10412 switch (filter_op) {
10413 case RTE_ETH_FILTER_ADD:
10414 ret = i40e_ethertype_filter_set(pf,
10415 (struct rte_eth_ethertype_filter *)arg,
10418 case RTE_ETH_FILTER_DELETE:
10419 ret = i40e_ethertype_filter_set(pf,
10420 (struct rte_eth_ethertype_filter *)arg,
10424 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10432 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10433 enum rte_filter_type filter_type,
10434 enum rte_filter_op filter_op,
10442 switch (filter_type) {
10443 case RTE_ETH_FILTER_NONE:
10444 /* For global configuration */
10445 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10447 case RTE_ETH_FILTER_HASH:
10448 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10450 case RTE_ETH_FILTER_MACVLAN:
10451 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10453 case RTE_ETH_FILTER_ETHERTYPE:
10454 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10456 case RTE_ETH_FILTER_TUNNEL:
10457 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10459 case RTE_ETH_FILTER_FDIR:
10460 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10462 case RTE_ETH_FILTER_GENERIC:
10463 if (filter_op != RTE_ETH_FILTER_GET)
10465 *(const void **)arg = &i40e_flow_ops;
10468 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10478 * Check and enable Extended Tag.
10479 * Enabling Extended Tag is important for 40G performance.
10482 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10484 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10488 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10491 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10495 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10496 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10501 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10504 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10508 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10509 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10512 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10513 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10516 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10523 * As some registers wouldn't be reset unless a global hardware reset,
10524 * hardware initialization is needed to put those registers into an
10525 * expected initial state.
10528 i40e_hw_init(struct rte_eth_dev *dev)
10530 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10532 i40e_enable_extended_tag(dev);
10534 /* clear the PF Queue Filter control register */
10535 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10537 /* Disable symmetric hash per port */
10538 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10542 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10543 * however this function will return only one highest pctype index,
10544 * which is not quite correct. This is known problem of i40e driver
10545 * and needs to be fixed later.
10547 enum i40e_filter_pctype
10548 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10551 uint64_t pctype_mask;
10553 if (flow_type < I40E_FLOW_TYPE_MAX) {
10554 pctype_mask = adapter->pctypes_tbl[flow_type];
10555 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10556 if (pctype_mask & (1ULL << i))
10557 return (enum i40e_filter_pctype)i;
10560 return I40E_FILTER_PCTYPE_INVALID;
10564 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10565 enum i40e_filter_pctype pctype)
10568 uint64_t pctype_mask = 1ULL << pctype;
10570 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10572 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10576 return RTE_ETH_FLOW_UNKNOWN;
10580 * On X710, performance number is far from the expectation on recent firmware
10581 * versions; on XL710, performance number is also far from the expectation on
10582 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10583 * mode is enabled and port MAC address is equal to the packet destination MAC
10584 * address. The fix for this issue may not be integrated in the following
10585 * firmware version. So the workaround in software driver is needed. It needs
10586 * to modify the initial values of 3 internal only registers for both X710 and
10587 * XL710. Note that the values for X710 or XL710 could be different, and the
10588 * workaround can be removed when it is fixed in firmware in the future.
10591 /* For both X710 and XL710 */
10592 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10593 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10594 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10596 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10597 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10600 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10601 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10604 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10606 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10607 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10610 * GL_SWR_PM_UP_THR:
10611 * The value is not impacted from the link speed, its value is set according
10612 * to the total number of ports for a better pipe-monitor configuration.
10615 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10617 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10618 .device_id = (dev), \
10619 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10621 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10622 .device_id = (dev), \
10623 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10625 static const struct {
10626 uint16_t device_id;
10628 } swr_pm_table[] = {
10629 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10630 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10631 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10632 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10633 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10635 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10636 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10637 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10638 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10639 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10640 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10641 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10645 if (value == NULL) {
10646 PMD_DRV_LOG(ERR, "value is NULL");
10650 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10651 if (hw->device_id == swr_pm_table[i].device_id) {
10652 *value = swr_pm_table[i].val;
10654 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10656 hw->device_id, *value);
10665 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10667 enum i40e_status_code status;
10668 struct i40e_aq_get_phy_abilities_resp phy_ab;
10669 int ret = -ENOTSUP;
10672 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10676 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10679 rte_delay_us(100000);
10681 status = i40e_aq_get_phy_capabilities(hw, false,
10682 true, &phy_ab, NULL);
10690 i40e_configure_registers(struct i40e_hw *hw)
10696 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10697 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10698 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10704 for (i = 0; i < RTE_DIM(reg_table); i++) {
10705 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10706 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10708 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10709 else /* For X710/XL710/XXV710 */
10710 if (hw->aq.fw_maj_ver < 6)
10712 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10715 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10718 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10719 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10721 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10722 else /* For X710/XL710/XXV710 */
10724 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10727 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10730 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10731 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10732 "GL_SWR_PM_UP_THR value fixup",
10737 reg_table[i].val = cfg_val;
10740 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10743 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10744 reg_table[i].addr);
10747 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10748 reg_table[i].addr, reg);
10749 if (reg == reg_table[i].val)
10752 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10753 reg_table[i].val, NULL);
10756 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10757 reg_table[i].val, reg_table[i].addr);
10760 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10761 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10765 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10766 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10767 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10768 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10770 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10775 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10776 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10780 /* Configure for double VLAN RX stripping */
10781 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10782 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10783 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10784 ret = i40e_aq_debug_write_register(hw,
10785 I40E_VSI_TSR(vsi->vsi_id),
10788 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10790 return I40E_ERR_CONFIG;
10794 /* Configure for double VLAN TX insertion */
10795 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10796 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10797 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10798 ret = i40e_aq_debug_write_register(hw,
10799 I40E_VSI_L2TAGSTXVALID(
10800 vsi->vsi_id), reg, NULL);
10803 "Failed to update VSI_L2TAGSTXVALID[%d]",
10805 return I40E_ERR_CONFIG;
10813 * i40e_aq_add_mirror_rule
10814 * @hw: pointer to the hardware structure
10815 * @seid: VEB seid to add mirror rule to
10816 * @dst_id: destination vsi seid
10817 * @entries: Buffer which contains the entities to be mirrored
10818 * @count: number of entities contained in the buffer
10819 * @rule_id:the rule_id of the rule to be added
10821 * Add a mirror rule for a given veb.
10824 static enum i40e_status_code
10825 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10826 uint16_t seid, uint16_t dst_id,
10827 uint16_t rule_type, uint16_t *entries,
10828 uint16_t count, uint16_t *rule_id)
10830 struct i40e_aq_desc desc;
10831 struct i40e_aqc_add_delete_mirror_rule cmd;
10832 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10833 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10836 enum i40e_status_code status;
10838 i40e_fill_default_direct_cmd_desc(&desc,
10839 i40e_aqc_opc_add_mirror_rule);
10840 memset(&cmd, 0, sizeof(cmd));
10842 buff_len = sizeof(uint16_t) * count;
10843 desc.datalen = rte_cpu_to_le_16(buff_len);
10845 desc.flags |= rte_cpu_to_le_16(
10846 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10847 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10848 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10849 cmd.num_entries = rte_cpu_to_le_16(count);
10850 cmd.seid = rte_cpu_to_le_16(seid);
10851 cmd.destination = rte_cpu_to_le_16(dst_id);
10853 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10854 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10856 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10857 hw->aq.asq_last_status, resp->rule_id,
10858 resp->mirror_rules_used, resp->mirror_rules_free);
10859 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10865 * i40e_aq_del_mirror_rule
10866 * @hw: pointer to the hardware structure
10867 * @seid: VEB seid to add mirror rule to
10868 * @entries: Buffer which contains the entities to be mirrored
10869 * @count: number of entities contained in the buffer
10870 * @rule_id:the rule_id of the rule to be delete
10872 * Delete a mirror rule for a given veb.
10875 static enum i40e_status_code
10876 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10877 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10878 uint16_t count, uint16_t rule_id)
10880 struct i40e_aq_desc desc;
10881 struct i40e_aqc_add_delete_mirror_rule cmd;
10882 uint16_t buff_len = 0;
10883 enum i40e_status_code status;
10886 i40e_fill_default_direct_cmd_desc(&desc,
10887 i40e_aqc_opc_delete_mirror_rule);
10888 memset(&cmd, 0, sizeof(cmd));
10889 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10890 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10892 cmd.num_entries = count;
10893 buff_len = sizeof(uint16_t) * count;
10894 desc.datalen = rte_cpu_to_le_16(buff_len);
10895 buff = (void *)entries;
10897 /* rule id is filled in destination field for deleting mirror rule */
10898 cmd.destination = rte_cpu_to_le_16(rule_id);
10900 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10901 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10902 cmd.seid = rte_cpu_to_le_16(seid);
10904 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10905 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10911 * i40e_mirror_rule_set
10912 * @dev: pointer to the hardware structure
10913 * @mirror_conf: mirror rule info
10914 * @sw_id: mirror rule's sw_id
10915 * @on: enable/disable
10917 * set a mirror rule.
10921 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10922 struct rte_eth_mirror_conf *mirror_conf,
10923 uint8_t sw_id, uint8_t on)
10925 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10927 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10928 struct i40e_mirror_rule *parent = NULL;
10929 uint16_t seid, dst_seid, rule_id;
10933 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10935 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10937 "mirror rule can not be configured without veb or vfs.");
10940 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10941 PMD_DRV_LOG(ERR, "mirror table is full.");
10944 if (mirror_conf->dst_pool > pf->vf_num) {
10945 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10946 mirror_conf->dst_pool);
10950 seid = pf->main_vsi->veb->seid;
10952 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10953 if (sw_id <= it->index) {
10959 if (mirr_rule && sw_id == mirr_rule->index) {
10961 PMD_DRV_LOG(ERR, "mirror rule exists.");
10964 ret = i40e_aq_del_mirror_rule(hw, seid,
10965 mirr_rule->rule_type,
10966 mirr_rule->entries,
10967 mirr_rule->num_entries, mirr_rule->id);
10970 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10971 ret, hw->aq.asq_last_status);
10974 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10975 rte_free(mirr_rule);
10976 pf->nb_mirror_rule--;
10980 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10984 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10985 sizeof(struct i40e_mirror_rule) , 0);
10987 PMD_DRV_LOG(ERR, "failed to allocate memory");
10988 return I40E_ERR_NO_MEMORY;
10990 switch (mirror_conf->rule_type) {
10991 case ETH_MIRROR_VLAN:
10992 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10993 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10994 mirr_rule->entries[j] =
10995 mirror_conf->vlan.vlan_id[i];
11000 PMD_DRV_LOG(ERR, "vlan is not specified.");
11001 rte_free(mirr_rule);
11004 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11006 case ETH_MIRROR_VIRTUAL_POOL_UP:
11007 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11008 /* check if the specified pool bit is out of range */
11009 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11010 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11011 rte_free(mirr_rule);
11014 for (i = 0, j = 0; i < pf->vf_num; i++) {
11015 if (mirror_conf->pool_mask & (1ULL << i)) {
11016 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11020 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11021 /* add pf vsi to entries */
11022 mirr_rule->entries[j] = pf->main_vsi_seid;
11026 PMD_DRV_LOG(ERR, "pool is not specified.");
11027 rte_free(mirr_rule);
11030 /* egress and ingress in aq commands means from switch but not port */
11031 mirr_rule->rule_type =
11032 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11033 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11034 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11036 case ETH_MIRROR_UPLINK_PORT:
11037 /* egress and ingress in aq commands means from switch but not port*/
11038 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11040 case ETH_MIRROR_DOWNLINK_PORT:
11041 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11044 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11045 mirror_conf->rule_type);
11046 rte_free(mirr_rule);
11050 /* If the dst_pool is equal to vf_num, consider it as PF */
11051 if (mirror_conf->dst_pool == pf->vf_num)
11052 dst_seid = pf->main_vsi_seid;
11054 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11056 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11057 mirr_rule->rule_type, mirr_rule->entries,
11061 "failed to add mirror rule: ret = %d, aq_err = %d.",
11062 ret, hw->aq.asq_last_status);
11063 rte_free(mirr_rule);
11067 mirr_rule->index = sw_id;
11068 mirr_rule->num_entries = j;
11069 mirr_rule->id = rule_id;
11070 mirr_rule->dst_vsi_seid = dst_seid;
11073 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11075 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11077 pf->nb_mirror_rule++;
11082 * i40e_mirror_rule_reset
11083 * @dev: pointer to the device
11084 * @sw_id: mirror rule's sw_id
11086 * reset a mirror rule.
11090 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11092 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11094 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11098 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11100 seid = pf->main_vsi->veb->seid;
11102 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11103 if (sw_id == it->index) {
11109 ret = i40e_aq_del_mirror_rule(hw, seid,
11110 mirr_rule->rule_type,
11111 mirr_rule->entries,
11112 mirr_rule->num_entries, mirr_rule->id);
11115 "failed to remove mirror rule: status = %d, aq_err = %d.",
11116 ret, hw->aq.asq_last_status);
11119 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11120 rte_free(mirr_rule);
11121 pf->nb_mirror_rule--;
11123 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11130 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11133 uint64_t systim_cycles;
11135 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11136 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11139 return systim_cycles;
11143 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11145 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11146 uint64_t rx_tstamp;
11148 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11149 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11156 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11159 uint64_t tx_tstamp;
11161 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11162 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11169 i40e_start_timecounters(struct rte_eth_dev *dev)
11171 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11172 struct i40e_adapter *adapter = dev->data->dev_private;
11173 struct rte_eth_link link;
11174 uint32_t tsync_inc_l;
11175 uint32_t tsync_inc_h;
11177 /* Get current link speed. */
11178 i40e_dev_link_update(dev, 1);
11179 rte_eth_linkstatus_get(dev, &link);
11181 switch (link.link_speed) {
11182 case ETH_SPEED_NUM_40G:
11183 case ETH_SPEED_NUM_25G:
11184 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11185 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11187 case ETH_SPEED_NUM_10G:
11188 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11189 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11191 case ETH_SPEED_NUM_1G:
11192 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11193 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11200 /* Set the timesync increment value. */
11201 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11202 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11204 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11205 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11206 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11208 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11209 adapter->systime_tc.cc_shift = 0;
11210 adapter->systime_tc.nsec_mask = 0;
11212 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11213 adapter->rx_tstamp_tc.cc_shift = 0;
11214 adapter->rx_tstamp_tc.nsec_mask = 0;
11216 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11217 adapter->tx_tstamp_tc.cc_shift = 0;
11218 adapter->tx_tstamp_tc.nsec_mask = 0;
11222 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11224 struct i40e_adapter *adapter = dev->data->dev_private;
11226 adapter->systime_tc.nsec += delta;
11227 adapter->rx_tstamp_tc.nsec += delta;
11228 adapter->tx_tstamp_tc.nsec += delta;
11234 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11237 struct i40e_adapter *adapter = dev->data->dev_private;
11239 ns = rte_timespec_to_ns(ts);
11241 /* Set the timecounters to a new value. */
11242 adapter->systime_tc.nsec = ns;
11243 adapter->rx_tstamp_tc.nsec = ns;
11244 adapter->tx_tstamp_tc.nsec = ns;
11250 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11252 uint64_t ns, systime_cycles;
11253 struct i40e_adapter *adapter = dev->data->dev_private;
11255 systime_cycles = i40e_read_systime_cyclecounter(dev);
11256 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11257 *ts = rte_ns_to_timespec(ns);
11263 i40e_timesync_enable(struct rte_eth_dev *dev)
11265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11266 uint32_t tsync_ctl_l;
11267 uint32_t tsync_ctl_h;
11269 /* Stop the timesync system time. */
11270 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11271 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11272 /* Reset the timesync system time value. */
11273 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11274 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11276 i40e_start_timecounters(dev);
11278 /* Clear timesync registers. */
11279 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11280 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11281 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11282 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11283 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11284 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11286 /* Enable timestamping of PTP packets. */
11287 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11288 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11290 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11291 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11292 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11294 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11295 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11301 i40e_timesync_disable(struct rte_eth_dev *dev)
11303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11304 uint32_t tsync_ctl_l;
11305 uint32_t tsync_ctl_h;
11307 /* Disable timestamping of transmitted PTP packets. */
11308 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11309 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11311 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11312 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11314 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11315 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11317 /* Reset the timesync increment value. */
11318 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11319 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11325 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11326 struct timespec *timestamp, uint32_t flags)
11328 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11329 struct i40e_adapter *adapter = dev->data->dev_private;
11330 uint32_t sync_status;
11331 uint32_t index = flags & 0x03;
11332 uint64_t rx_tstamp_cycles;
11335 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11336 if ((sync_status & (1 << index)) == 0)
11339 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11340 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11341 *timestamp = rte_ns_to_timespec(ns);
11347 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11348 struct timespec *timestamp)
11350 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11351 struct i40e_adapter *adapter = dev->data->dev_private;
11352 uint32_t sync_status;
11353 uint64_t tx_tstamp_cycles;
11356 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11357 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11360 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11361 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11362 *timestamp = rte_ns_to_timespec(ns);
11368 * i40e_parse_dcb_configure - parse dcb configure from user
11369 * @dev: the device being configured
11370 * @dcb_cfg: pointer of the result of parse
11371 * @*tc_map: bit map of enabled traffic classes
11373 * Returns 0 on success, negative value on failure
11376 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11377 struct i40e_dcbx_config *dcb_cfg,
11380 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11381 uint8_t i, tc_bw, bw_lf;
11383 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11385 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11386 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11387 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11391 /* assume each tc has the same bw */
11392 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11393 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11394 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11395 /* to ensure the sum of tcbw is equal to 100 */
11396 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11397 for (i = 0; i < bw_lf; i++)
11398 dcb_cfg->etscfg.tcbwtable[i]++;
11400 /* assume each tc has the same Transmission Selection Algorithm */
11401 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11402 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11404 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11405 dcb_cfg->etscfg.prioritytable[i] =
11406 dcb_rx_conf->dcb_tc[i];
11408 /* FW needs one App to configure HW */
11409 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11410 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11411 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11412 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11414 if (dcb_rx_conf->nb_tcs == 0)
11415 *tc_map = 1; /* tc0 only */
11417 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11419 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11420 dcb_cfg->pfc.willing = 0;
11421 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11422 dcb_cfg->pfc.pfcenable = *tc_map;
11428 static enum i40e_status_code
11429 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11430 struct i40e_aqc_vsi_properties_data *info,
11431 uint8_t enabled_tcmap)
11433 enum i40e_status_code ret;
11434 int i, total_tc = 0;
11435 uint16_t qpnum_per_tc, bsf, qp_idx;
11436 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11437 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11438 uint16_t used_queues;
11440 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11441 if (ret != I40E_SUCCESS)
11444 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11445 if (enabled_tcmap & (1 << i))
11450 vsi->enabled_tc = enabled_tcmap;
11452 /* different VSI has different queues assigned */
11453 if (vsi->type == I40E_VSI_MAIN)
11454 used_queues = dev_data->nb_rx_queues -
11455 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11456 else if (vsi->type == I40E_VSI_VMDQ2)
11457 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11459 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11460 return I40E_ERR_NO_AVAILABLE_VSI;
11463 qpnum_per_tc = used_queues / total_tc;
11464 /* Number of queues per enabled TC */
11465 if (qpnum_per_tc == 0) {
11466 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11467 return I40E_ERR_INVALID_QP_ID;
11469 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11470 I40E_MAX_Q_PER_TC);
11471 bsf = rte_bsf32(qpnum_per_tc);
11474 * Configure TC and queue mapping parameters, for enabled TC,
11475 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11476 * default queue will serve it.
11479 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11480 if (vsi->enabled_tc & (1 << i)) {
11481 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11482 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11483 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11484 qp_idx += qpnum_per_tc;
11486 info->tc_mapping[i] = 0;
11489 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11490 if (vsi->type == I40E_VSI_SRIOV) {
11491 info->mapping_flags |=
11492 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11493 for (i = 0; i < vsi->nb_qps; i++)
11494 info->queue_mapping[i] =
11495 rte_cpu_to_le_16(vsi->base_queue + i);
11497 info->mapping_flags |=
11498 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11499 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11501 info->valid_sections |=
11502 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11504 return I40E_SUCCESS;
11508 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11509 * @veb: VEB to be configured
11510 * @tc_map: enabled TC bitmap
11512 * Returns 0 on success, negative value on failure
11514 static enum i40e_status_code
11515 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11517 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11518 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11519 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11520 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11521 enum i40e_status_code ret = I40E_SUCCESS;
11525 /* Check if enabled_tc is same as existing or new TCs */
11526 if (veb->enabled_tc == tc_map)
11529 /* configure tc bandwidth */
11530 memset(&veb_bw, 0, sizeof(veb_bw));
11531 veb_bw.tc_valid_bits = tc_map;
11532 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11533 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11534 if (tc_map & BIT_ULL(i))
11535 veb_bw.tc_bw_share_credits[i] = 1;
11537 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11541 "AQ command Config switch_comp BW allocation per TC failed = %d",
11542 hw->aq.asq_last_status);
11546 memset(&ets_query, 0, sizeof(ets_query));
11547 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11549 if (ret != I40E_SUCCESS) {
11551 "Failed to get switch_comp ETS configuration %u",
11552 hw->aq.asq_last_status);
11555 memset(&bw_query, 0, sizeof(bw_query));
11556 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11558 if (ret != I40E_SUCCESS) {
11560 "Failed to get switch_comp bandwidth configuration %u",
11561 hw->aq.asq_last_status);
11565 /* store and print out BW info */
11566 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11567 veb->bw_info.bw_max = ets_query.tc_bw_max;
11568 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11569 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11570 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11571 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11572 I40E_16_BIT_WIDTH);
11573 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11574 veb->bw_info.bw_ets_share_credits[i] =
11575 bw_query.tc_bw_share_credits[i];
11576 veb->bw_info.bw_ets_credits[i] =
11577 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11578 /* 4 bits per TC, 4th bit is reserved */
11579 veb->bw_info.bw_ets_max[i] =
11580 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11581 RTE_LEN2MASK(3, uint8_t));
11582 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11583 veb->bw_info.bw_ets_share_credits[i]);
11584 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11585 veb->bw_info.bw_ets_credits[i]);
11586 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11587 veb->bw_info.bw_ets_max[i]);
11590 veb->enabled_tc = tc_map;
11597 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11598 * @vsi: VSI to be configured
11599 * @tc_map: enabled TC bitmap
11601 * Returns 0 on success, negative value on failure
11603 static enum i40e_status_code
11604 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11606 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11607 struct i40e_vsi_context ctxt;
11608 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11609 enum i40e_status_code ret = I40E_SUCCESS;
11612 /* Check if enabled_tc is same as existing or new TCs */
11613 if (vsi->enabled_tc == tc_map)
11616 /* configure tc bandwidth */
11617 memset(&bw_data, 0, sizeof(bw_data));
11618 bw_data.tc_valid_bits = tc_map;
11619 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11620 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11621 if (tc_map & BIT_ULL(i))
11622 bw_data.tc_bw_credits[i] = 1;
11624 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11627 "AQ command Config VSI BW allocation per TC failed = %d",
11628 hw->aq.asq_last_status);
11631 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11632 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11634 /* Update Queue Pairs Mapping for currently enabled UPs */
11635 ctxt.seid = vsi->seid;
11636 ctxt.pf_num = hw->pf_id;
11638 ctxt.uplink_seid = vsi->uplink_seid;
11639 ctxt.info = vsi->info;
11641 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11645 /* Update the VSI after updating the VSI queue-mapping information */
11646 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11648 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11649 hw->aq.asq_last_status);
11652 /* update the local VSI info with updated queue map */
11653 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11654 sizeof(vsi->info.tc_mapping));
11655 rte_memcpy(&vsi->info.queue_mapping,
11656 &ctxt.info.queue_mapping,
11657 sizeof(vsi->info.queue_mapping));
11658 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11659 vsi->info.valid_sections = 0;
11661 /* query and update current VSI BW information */
11662 ret = i40e_vsi_get_bw_config(vsi);
11665 "Failed updating vsi bw info, err %s aq_err %s",
11666 i40e_stat_str(hw, ret),
11667 i40e_aq_str(hw, hw->aq.asq_last_status));
11671 vsi->enabled_tc = tc_map;
11678 * i40e_dcb_hw_configure - program the dcb setting to hw
11679 * @pf: pf the configuration is taken on
11680 * @new_cfg: new configuration
11681 * @tc_map: enabled TC bitmap
11683 * Returns 0 on success, negative value on failure
11685 static enum i40e_status_code
11686 i40e_dcb_hw_configure(struct i40e_pf *pf,
11687 struct i40e_dcbx_config *new_cfg,
11690 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11691 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11692 struct i40e_vsi *main_vsi = pf->main_vsi;
11693 struct i40e_vsi_list *vsi_list;
11694 enum i40e_status_code ret;
11698 /* Use the FW API if FW > v4.4*/
11699 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11700 (hw->aq.fw_maj_ver >= 5))) {
11702 "FW < v4.4, can not use FW LLDP API to configure DCB");
11703 return I40E_ERR_FIRMWARE_API_VERSION;
11706 /* Check if need reconfiguration */
11707 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11708 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11709 return I40E_SUCCESS;
11712 /* Copy the new config to the current config */
11713 *old_cfg = *new_cfg;
11714 old_cfg->etsrec = old_cfg->etscfg;
11715 ret = i40e_set_dcb_config(hw);
11717 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11718 i40e_stat_str(hw, ret),
11719 i40e_aq_str(hw, hw->aq.asq_last_status));
11722 /* set receive Arbiter to RR mode and ETS scheme by default */
11723 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11724 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11725 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11726 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11727 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11728 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11729 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11730 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11731 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11732 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11733 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11734 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11735 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11737 /* get local mib to check whether it is configured correctly */
11739 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11740 /* Get Local DCB Config */
11741 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11742 &hw->local_dcbx_config);
11744 /* if Veb is created, need to update TC of it at first */
11745 if (main_vsi->veb) {
11746 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11748 PMD_INIT_LOG(WARNING,
11749 "Failed configuring TC for VEB seid=%d",
11750 main_vsi->veb->seid);
11752 /* Update each VSI */
11753 i40e_vsi_config_tc(main_vsi, tc_map);
11754 if (main_vsi->veb) {
11755 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11756 /* Beside main VSI and VMDQ VSIs, only enable default
11757 * TC for other VSIs
11759 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11760 ret = i40e_vsi_config_tc(vsi_list->vsi,
11763 ret = i40e_vsi_config_tc(vsi_list->vsi,
11764 I40E_DEFAULT_TCMAP);
11766 PMD_INIT_LOG(WARNING,
11767 "Failed configuring TC for VSI seid=%d",
11768 vsi_list->vsi->seid);
11772 return I40E_SUCCESS;
11776 * i40e_dcb_init_configure - initial dcb config
11777 * @dev: device being configured
11778 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11780 * Returns 0 on success, negative value on failure
11783 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11785 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11789 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11790 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11794 /* DCB initialization:
11795 * Update DCB configuration from the Firmware and configure
11796 * LLDP MIB change event.
11798 if (sw_dcb == TRUE) {
11799 /* Stopping lldp is necessary for DPDK, but it will cause
11800 * DCB init failed. For i40e_init_dcb(), the prerequisite
11801 * for successful initialization of DCB is that LLDP is
11802 * enabled. So it is needed to start lldp before DCB init
11803 * and stop it after initialization.
11805 ret = i40e_aq_start_lldp(hw, true, NULL);
11806 if (ret != I40E_SUCCESS)
11807 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11809 ret = i40e_init_dcb(hw, true);
11810 /* If lldp agent is stopped, the return value from
11811 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11812 * adminq status. Otherwise, it should return success.
11814 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11815 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11816 memset(&hw->local_dcbx_config, 0,
11817 sizeof(struct i40e_dcbx_config));
11818 /* set dcb default configuration */
11819 hw->local_dcbx_config.etscfg.willing = 0;
11820 hw->local_dcbx_config.etscfg.maxtcs = 0;
11821 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11822 hw->local_dcbx_config.etscfg.tsatable[0] =
11824 /* all UPs mapping to TC0 */
11825 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11826 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11827 hw->local_dcbx_config.etsrec =
11828 hw->local_dcbx_config.etscfg;
11829 hw->local_dcbx_config.pfc.willing = 0;
11830 hw->local_dcbx_config.pfc.pfccap =
11831 I40E_MAX_TRAFFIC_CLASS;
11832 /* FW needs one App to configure HW */
11833 hw->local_dcbx_config.numapps = 1;
11834 hw->local_dcbx_config.app[0].selector =
11835 I40E_APP_SEL_ETHTYPE;
11836 hw->local_dcbx_config.app[0].priority = 3;
11837 hw->local_dcbx_config.app[0].protocolid =
11838 I40E_APP_PROTOID_FCOE;
11839 ret = i40e_set_dcb_config(hw);
11842 "default dcb config fails. err = %d, aq_err = %d.",
11843 ret, hw->aq.asq_last_status);
11848 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11849 ret, hw->aq.asq_last_status);
11853 if (i40e_need_stop_lldp(dev)) {
11854 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11855 if (ret != I40E_SUCCESS)
11856 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11859 ret = i40e_aq_start_lldp(hw, true, NULL);
11860 if (ret != I40E_SUCCESS)
11861 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11863 ret = i40e_init_dcb(hw, true);
11865 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11867 "HW doesn't support DCBX offload.");
11872 "DCBX configuration failed, err = %d, aq_err = %d.",
11873 ret, hw->aq.asq_last_status);
11881 * i40e_dcb_setup - setup dcb related config
11882 * @dev: device being configured
11884 * Returns 0 on success, negative value on failure
11887 i40e_dcb_setup(struct rte_eth_dev *dev)
11889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11890 struct i40e_dcbx_config dcb_cfg;
11891 uint8_t tc_map = 0;
11894 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11895 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11899 if (pf->vf_num != 0)
11900 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11902 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11904 PMD_INIT_LOG(ERR, "invalid dcb config");
11907 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11909 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11917 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11918 struct rte_eth_dcb_info *dcb_info)
11920 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11921 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11922 struct i40e_vsi *vsi = pf->main_vsi;
11923 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11924 uint16_t bsf, tc_mapping;
11927 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11928 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11930 dcb_info->nb_tcs = 1;
11931 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11932 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11933 for (i = 0; i < dcb_info->nb_tcs; i++)
11934 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11936 /* get queue mapping if vmdq is disabled */
11937 if (!pf->nb_cfg_vmdq_vsi) {
11938 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11939 if (!(vsi->enabled_tc & (1 << i)))
11941 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11942 dcb_info->tc_queue.tc_rxq[j][i].base =
11943 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11944 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11945 dcb_info->tc_queue.tc_txq[j][i].base =
11946 dcb_info->tc_queue.tc_rxq[j][i].base;
11947 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11948 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11949 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11950 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11951 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11956 /* get queue mapping if vmdq is enabled */
11958 vsi = pf->vmdq[j].vsi;
11959 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11960 if (!(vsi->enabled_tc & (1 << i)))
11962 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11963 dcb_info->tc_queue.tc_rxq[j][i].base =
11964 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11965 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11966 dcb_info->tc_queue.tc_txq[j][i].base =
11967 dcb_info->tc_queue.tc_rxq[j][i].base;
11968 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11969 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11970 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11971 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11972 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11975 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11980 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11982 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11983 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11984 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11985 uint16_t msix_intr;
11987 msix_intr = intr_handle->intr_vec[queue_id];
11988 if (msix_intr == I40E_MISC_VEC_ID)
11989 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11990 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11991 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11992 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11995 I40E_PFINT_DYN_CTLN(msix_intr -
11996 I40E_RX_VEC_START),
11997 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11998 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11999 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12001 I40E_WRITE_FLUSH(hw);
12002 rte_intr_ack(&pci_dev->intr_handle);
12008 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12010 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12011 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12012 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12013 uint16_t msix_intr;
12015 msix_intr = intr_handle->intr_vec[queue_id];
12016 if (msix_intr == I40E_MISC_VEC_ID)
12017 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12018 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12021 I40E_PFINT_DYN_CTLN(msix_intr -
12022 I40E_RX_VEC_START),
12023 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12024 I40E_WRITE_FLUSH(hw);
12030 * This function is used to check if the register is valid.
12031 * Below is the valid registers list for X722 only:
12035 * 0x208e00--0x209000
12036 * 0x20be00--0x20c000
12037 * 0x263c00--0x264000
12038 * 0x265c00--0x266000
12040 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12042 if ((type != I40E_MAC_X722) &&
12043 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12044 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12045 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12046 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12047 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12048 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12049 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12055 static int i40e_get_regs(struct rte_eth_dev *dev,
12056 struct rte_dev_reg_info *regs)
12058 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12059 uint32_t *ptr_data = regs->data;
12060 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12061 const struct i40e_reg_info *reg_info;
12063 if (ptr_data == NULL) {
12064 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12065 regs->width = sizeof(uint32_t);
12069 /* The first few registers have to be read using AQ operations */
12071 while (i40e_regs_adminq[reg_idx].name) {
12072 reg_info = &i40e_regs_adminq[reg_idx++];
12073 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12075 arr_idx2 <= reg_info->count2;
12077 reg_offset = arr_idx * reg_info->stride1 +
12078 arr_idx2 * reg_info->stride2;
12079 reg_offset += reg_info->base_addr;
12080 ptr_data[reg_offset >> 2] =
12081 i40e_read_rx_ctl(hw, reg_offset);
12085 /* The remaining registers can be read using primitives */
12087 while (i40e_regs_others[reg_idx].name) {
12088 reg_info = &i40e_regs_others[reg_idx++];
12089 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12091 arr_idx2 <= reg_info->count2;
12093 reg_offset = arr_idx * reg_info->stride1 +
12094 arr_idx2 * reg_info->stride2;
12095 reg_offset += reg_info->base_addr;
12096 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12097 ptr_data[reg_offset >> 2] = 0;
12099 ptr_data[reg_offset >> 2] =
12100 I40E_READ_REG(hw, reg_offset);
12107 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12111 /* Convert word count to byte count */
12112 return hw->nvm.sr_size << 1;
12115 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12116 struct rte_dev_eeprom_info *eeprom)
12118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12119 uint16_t *data = eeprom->data;
12120 uint16_t offset, length, cnt_words;
12123 offset = eeprom->offset >> 1;
12124 length = eeprom->length >> 1;
12125 cnt_words = length;
12127 if (offset > hw->nvm.sr_size ||
12128 offset + length > hw->nvm.sr_size) {
12129 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12133 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12135 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12136 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12137 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12144 static int i40e_get_module_info(struct rte_eth_dev *dev,
12145 struct rte_eth_dev_module_info *modinfo)
12147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12148 uint32_t sff8472_comp = 0;
12149 uint32_t sff8472_swap = 0;
12150 uint32_t sff8636_rev = 0;
12151 i40e_status status;
12154 /* Check if firmware supports reading module EEPROM. */
12155 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12157 "Module EEPROM memory read not supported. "
12158 "Please update the NVM image.\n");
12162 status = i40e_update_link_info(hw);
12166 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12168 "Cannot read module EEPROM memory. "
12169 "No module connected.\n");
12173 type = hw->phy.link_info.module_type[0];
12176 case I40E_MODULE_TYPE_SFP:
12177 status = i40e_aq_get_phy_register(hw,
12178 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12179 I40E_I2C_EEPROM_DEV_ADDR, 1,
12180 I40E_MODULE_SFF_8472_COMP,
12181 &sff8472_comp, NULL);
12185 status = i40e_aq_get_phy_register(hw,
12186 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12187 I40E_I2C_EEPROM_DEV_ADDR, 1,
12188 I40E_MODULE_SFF_8472_SWAP,
12189 &sff8472_swap, NULL);
12193 /* Check if the module requires address swap to access
12194 * the other EEPROM memory page.
12196 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12197 PMD_DRV_LOG(WARNING,
12198 "Module address swap to access "
12199 "page 0xA2 is not supported.\n");
12200 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12201 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12202 } else if (sff8472_comp == 0x00) {
12203 /* Module is not SFF-8472 compliant */
12204 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12205 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12207 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12208 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12211 case I40E_MODULE_TYPE_QSFP_PLUS:
12212 /* Read from memory page 0. */
12213 status = i40e_aq_get_phy_register(hw,
12214 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12216 I40E_MODULE_REVISION_ADDR,
12217 &sff8636_rev, NULL);
12220 /* Determine revision compliance byte */
12221 if (sff8636_rev > 0x02) {
12222 /* Module is SFF-8636 compliant */
12223 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12224 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12226 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12227 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12230 case I40E_MODULE_TYPE_QSFP28:
12231 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12232 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12235 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12241 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12242 struct rte_dev_eeprom_info *info)
12244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12245 bool is_sfp = false;
12246 i40e_status status;
12248 uint32_t value = 0;
12251 if (!info || !info->length || !info->data)
12254 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12258 for (i = 0; i < info->length; i++) {
12259 u32 offset = i + info->offset;
12260 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12262 /* Check if we need to access the other memory page */
12264 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12265 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12266 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12269 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12270 /* Compute memory page number and offset. */
12271 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12275 status = i40e_aq_get_phy_register(hw,
12276 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12277 addr, 1, offset, &value, NULL);
12280 data[i] = (uint8_t)value;
12285 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12286 struct rte_ether_addr *mac_addr)
12288 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12290 struct i40e_vsi *vsi = pf->main_vsi;
12291 struct i40e_mac_filter_info mac_filter;
12292 struct i40e_mac_filter *f;
12295 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12296 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12300 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12301 if (rte_is_same_ether_addr(&pf->dev_addr,
12302 &f->mac_info.mac_addr))
12307 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12311 mac_filter = f->mac_info;
12312 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12313 if (ret != I40E_SUCCESS) {
12314 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12317 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12318 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12319 if (ret != I40E_SUCCESS) {
12320 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12323 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12325 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12326 mac_addr->addr_bytes, NULL);
12327 if (ret != I40E_SUCCESS) {
12328 PMD_DRV_LOG(ERR, "Failed to change mac");
12336 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12338 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12339 struct rte_eth_dev_data *dev_data = pf->dev_data;
12340 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12343 /* check if mtu is within the allowed range */
12344 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12347 /* mtu setting is forbidden if port is start */
12348 if (dev_data->dev_started) {
12349 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12350 dev_data->port_id);
12354 if (frame_size > RTE_ETHER_MAX_LEN)
12355 dev_data->dev_conf.rxmode.offloads |=
12356 DEV_RX_OFFLOAD_JUMBO_FRAME;
12358 dev_data->dev_conf.rxmode.offloads &=
12359 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12361 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12366 /* Restore ethertype filter */
12368 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12370 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12371 struct i40e_ethertype_filter_list
12372 *ethertype_list = &pf->ethertype.ethertype_list;
12373 struct i40e_ethertype_filter *f;
12374 struct i40e_control_filter_stats stats;
12377 TAILQ_FOREACH(f, ethertype_list, rules) {
12379 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12380 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12381 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12382 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12383 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12385 memset(&stats, 0, sizeof(stats));
12386 i40e_aq_add_rem_control_packet_filter(hw,
12387 f->input.mac_addr.addr_bytes,
12388 f->input.ether_type,
12389 flags, pf->main_vsi->seid,
12390 f->queue, 1, &stats, NULL);
12392 PMD_DRV_LOG(INFO, "Ethertype filter:"
12393 " mac_etype_used = %u, etype_used = %u,"
12394 " mac_etype_free = %u, etype_free = %u",
12395 stats.mac_etype_used, stats.etype_used,
12396 stats.mac_etype_free, stats.etype_free);
12399 /* Restore tunnel filter */
12401 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12403 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12404 struct i40e_vsi *vsi;
12405 struct i40e_pf_vf *vf;
12406 struct i40e_tunnel_filter_list
12407 *tunnel_list = &pf->tunnel.tunnel_list;
12408 struct i40e_tunnel_filter *f;
12409 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12410 bool big_buffer = 0;
12412 TAILQ_FOREACH(f, tunnel_list, rules) {
12414 vsi = pf->main_vsi;
12416 vf = &pf->vfs[f->vf_id];
12419 memset(&cld_filter, 0, sizeof(cld_filter));
12420 rte_ether_addr_copy((struct rte_ether_addr *)
12421 &f->input.outer_mac,
12422 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12423 rte_ether_addr_copy((struct rte_ether_addr *)
12424 &f->input.inner_mac,
12425 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12426 cld_filter.element.inner_vlan = f->input.inner_vlan;
12427 cld_filter.element.flags = f->input.flags;
12428 cld_filter.element.tenant_id = f->input.tenant_id;
12429 cld_filter.element.queue_number = f->queue;
12430 rte_memcpy(cld_filter.general_fields,
12431 f->input.general_fields,
12432 sizeof(f->input.general_fields));
12434 if (((f->input.flags &
12435 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12436 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12438 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12439 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12441 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12442 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12446 i40e_aq_add_cloud_filters_bb(hw,
12447 vsi->seid, &cld_filter, 1);
12449 i40e_aq_add_cloud_filters(hw, vsi->seid,
12450 &cld_filter.element, 1);
12454 /* Restore RSS filter */
12456 i40e_rss_filter_restore(struct i40e_pf *pf)
12458 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12459 struct i40e_rss_filter *filter;
12461 TAILQ_FOREACH(filter, list, next) {
12462 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12467 i40e_filter_restore(struct i40e_pf *pf)
12469 i40e_ethertype_filter_restore(pf);
12470 i40e_tunnel_filter_restore(pf);
12471 i40e_fdir_filter_restore(pf);
12472 i40e_rss_filter_restore(pf);
12476 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12478 if (strcmp(dev->device->driver->name, drv->driver.name))
12485 is_i40e_supported(struct rte_eth_dev *dev)
12487 return is_device_supported(dev, &rte_i40e_pmd);
12490 struct i40e_customized_pctype*
12491 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12495 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12496 if (pf->customized_pctype[i].index == index)
12497 return &pf->customized_pctype[i];
12503 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12504 uint32_t pkg_size, uint32_t proto_num,
12505 struct rte_pmd_i40e_proto_info *proto,
12506 enum rte_pmd_i40e_package_op op)
12508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12509 uint32_t pctype_num;
12510 struct rte_pmd_i40e_ptype_info *pctype;
12511 uint32_t buff_size;
12512 struct i40e_customized_pctype *new_pctype = NULL;
12514 uint8_t pctype_value;
12519 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12520 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12521 PMD_DRV_LOG(ERR, "Unsupported operation.");
12525 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12526 (uint8_t *)&pctype_num, sizeof(pctype_num),
12527 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12529 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12533 PMD_DRV_LOG(INFO, "No new pctype added");
12537 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12538 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12540 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12543 /* get information about new pctype list */
12544 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12545 (uint8_t *)pctype, buff_size,
12546 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12548 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12553 /* Update customized pctype. */
12554 for (i = 0; i < pctype_num; i++) {
12555 pctype_value = pctype[i].ptype_id;
12556 memset(name, 0, sizeof(name));
12557 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12558 proto_id = pctype[i].protocols[j];
12559 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12561 for (n = 0; n < proto_num; n++) {
12562 if (proto[n].proto_id != proto_id)
12564 strlcat(name, proto[n].name, sizeof(name));
12565 strlcat(name, "_", sizeof(name));
12569 name[strlen(name) - 1] = '\0';
12570 PMD_DRV_LOG(INFO, "name = %s\n", name);
12571 if (!strcmp(name, "GTPC"))
12573 i40e_find_customized_pctype(pf,
12574 I40E_CUSTOMIZED_GTPC);
12575 else if (!strcmp(name, "GTPU_IPV4"))
12577 i40e_find_customized_pctype(pf,
12578 I40E_CUSTOMIZED_GTPU_IPV4);
12579 else if (!strcmp(name, "GTPU_IPV6"))
12581 i40e_find_customized_pctype(pf,
12582 I40E_CUSTOMIZED_GTPU_IPV6);
12583 else if (!strcmp(name, "GTPU"))
12585 i40e_find_customized_pctype(pf,
12586 I40E_CUSTOMIZED_GTPU);
12587 else if (!strcmp(name, "IPV4_L2TPV3"))
12589 i40e_find_customized_pctype(pf,
12590 I40E_CUSTOMIZED_IPV4_L2TPV3);
12591 else if (!strcmp(name, "IPV6_L2TPV3"))
12593 i40e_find_customized_pctype(pf,
12594 I40E_CUSTOMIZED_IPV6_L2TPV3);
12595 else if (!strcmp(name, "IPV4_ESP"))
12597 i40e_find_customized_pctype(pf,
12598 I40E_CUSTOMIZED_ESP_IPV4);
12599 else if (!strcmp(name, "IPV6_ESP"))
12601 i40e_find_customized_pctype(pf,
12602 I40E_CUSTOMIZED_ESP_IPV6);
12603 else if (!strcmp(name, "IPV4_UDP_ESP"))
12605 i40e_find_customized_pctype(pf,
12606 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12607 else if (!strcmp(name, "IPV6_UDP_ESP"))
12609 i40e_find_customized_pctype(pf,
12610 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12611 else if (!strcmp(name, "IPV4_AH"))
12613 i40e_find_customized_pctype(pf,
12614 I40E_CUSTOMIZED_AH_IPV4);
12615 else if (!strcmp(name, "IPV6_AH"))
12617 i40e_find_customized_pctype(pf,
12618 I40E_CUSTOMIZED_AH_IPV6);
12620 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12621 new_pctype->pctype = pctype_value;
12622 new_pctype->valid = true;
12624 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12625 new_pctype->valid = false;
12635 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12636 uint32_t pkg_size, uint32_t proto_num,
12637 struct rte_pmd_i40e_proto_info *proto,
12638 enum rte_pmd_i40e_package_op op)
12640 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12641 uint16_t port_id = dev->data->port_id;
12642 uint32_t ptype_num;
12643 struct rte_pmd_i40e_ptype_info *ptype;
12644 uint32_t buff_size;
12646 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12651 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12652 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12653 PMD_DRV_LOG(ERR, "Unsupported operation.");
12657 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12658 rte_pmd_i40e_ptype_mapping_reset(port_id);
12662 /* get information about new ptype num */
12663 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12664 (uint8_t *)&ptype_num, sizeof(ptype_num),
12665 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12667 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12671 PMD_DRV_LOG(INFO, "No new ptype added");
12675 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12676 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12678 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12682 /* get information about new ptype list */
12683 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12684 (uint8_t *)ptype, buff_size,
12685 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12687 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12692 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12693 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12694 if (!ptype_mapping) {
12695 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12700 /* Update ptype mapping table. */
12701 for (i = 0; i < ptype_num; i++) {
12702 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12703 ptype_mapping[i].sw_ptype = 0;
12705 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12706 proto_id = ptype[i].protocols[j];
12707 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12709 for (n = 0; n < proto_num; n++) {
12710 if (proto[n].proto_id != proto_id)
12712 memset(name, 0, sizeof(name));
12713 strcpy(name, proto[n].name);
12714 PMD_DRV_LOG(INFO, "name = %s\n", name);
12715 if (!strncasecmp(name, "PPPOE", 5))
12716 ptype_mapping[i].sw_ptype |=
12717 RTE_PTYPE_L2_ETHER_PPPOE;
12718 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12720 ptype_mapping[i].sw_ptype |=
12721 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12722 ptype_mapping[i].sw_ptype |=
12724 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12726 ptype_mapping[i].sw_ptype |=
12727 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12728 ptype_mapping[i].sw_ptype |=
12729 RTE_PTYPE_INNER_L4_FRAG;
12730 } else if (!strncasecmp(name, "OIPV4", 5)) {
12731 ptype_mapping[i].sw_ptype |=
12732 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12734 } else if (!strncasecmp(name, "IPV4", 4) &&
12736 ptype_mapping[i].sw_ptype |=
12737 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12738 else if (!strncasecmp(name, "IPV4", 4) &&
12740 ptype_mapping[i].sw_ptype |=
12741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12742 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12744 ptype_mapping[i].sw_ptype |=
12745 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12746 ptype_mapping[i].sw_ptype |=
12748 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12750 ptype_mapping[i].sw_ptype |=
12751 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12752 ptype_mapping[i].sw_ptype |=
12753 RTE_PTYPE_INNER_L4_FRAG;
12754 } else if (!strncasecmp(name, "OIPV6", 5)) {
12755 ptype_mapping[i].sw_ptype |=
12756 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12758 } else if (!strncasecmp(name, "IPV6", 4) &&
12760 ptype_mapping[i].sw_ptype |=
12761 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12762 else if (!strncasecmp(name, "IPV6", 4) &&
12764 ptype_mapping[i].sw_ptype |=
12765 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12766 else if (!strncasecmp(name, "UDP", 3) &&
12768 ptype_mapping[i].sw_ptype |=
12770 else if (!strncasecmp(name, "UDP", 3) &&
12772 ptype_mapping[i].sw_ptype |=
12773 RTE_PTYPE_INNER_L4_UDP;
12774 else if (!strncasecmp(name, "TCP", 3) &&
12776 ptype_mapping[i].sw_ptype |=
12778 else if (!strncasecmp(name, "TCP", 3) &&
12780 ptype_mapping[i].sw_ptype |=
12781 RTE_PTYPE_INNER_L4_TCP;
12782 else if (!strncasecmp(name, "SCTP", 4) &&
12784 ptype_mapping[i].sw_ptype |=
12786 else if (!strncasecmp(name, "SCTP", 4) &&
12788 ptype_mapping[i].sw_ptype |=
12789 RTE_PTYPE_INNER_L4_SCTP;
12790 else if ((!strncasecmp(name, "ICMP", 4) ||
12791 !strncasecmp(name, "ICMPV6", 6)) &&
12793 ptype_mapping[i].sw_ptype |=
12795 else if ((!strncasecmp(name, "ICMP", 4) ||
12796 !strncasecmp(name, "ICMPV6", 6)) &&
12798 ptype_mapping[i].sw_ptype |=
12799 RTE_PTYPE_INNER_L4_ICMP;
12800 else if (!strncasecmp(name, "GTPC", 4)) {
12801 ptype_mapping[i].sw_ptype |=
12802 RTE_PTYPE_TUNNEL_GTPC;
12804 } else if (!strncasecmp(name, "GTPU", 4)) {
12805 ptype_mapping[i].sw_ptype |=
12806 RTE_PTYPE_TUNNEL_GTPU;
12808 } else if (!strncasecmp(name, "ESP", 3)) {
12809 ptype_mapping[i].sw_ptype |=
12810 RTE_PTYPE_TUNNEL_ESP;
12812 } else if (!strncasecmp(name, "GRENAT", 6)) {
12813 ptype_mapping[i].sw_ptype |=
12814 RTE_PTYPE_TUNNEL_GRENAT;
12816 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12817 !strncasecmp(name, "L2TPV2", 6) ||
12818 !strncasecmp(name, "L2TPV3", 6)) {
12819 ptype_mapping[i].sw_ptype |=
12820 RTE_PTYPE_TUNNEL_L2TP;
12829 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12832 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12834 rte_free(ptype_mapping);
12840 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12841 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12844 uint32_t proto_num;
12845 struct rte_pmd_i40e_proto_info *proto;
12846 uint32_t buff_size;
12850 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12851 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12852 PMD_DRV_LOG(ERR, "Unsupported operation.");
12856 /* get information about protocol number */
12857 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12858 (uint8_t *)&proto_num, sizeof(proto_num),
12859 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12861 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12865 PMD_DRV_LOG(INFO, "No new protocol added");
12869 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12870 proto = rte_zmalloc("new_proto", buff_size, 0);
12872 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12876 /* get information about protocol list */
12877 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12878 (uint8_t *)proto, buff_size,
12879 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12881 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12886 /* Check if GTP is supported. */
12887 for (i = 0; i < proto_num; i++) {
12888 if (!strncmp(proto[i].name, "GTP", 3)) {
12889 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12890 pf->gtp_support = true;
12892 pf->gtp_support = false;
12897 /* Check if ESP is supported. */
12898 for (i = 0; i < proto_num; i++) {
12899 if (!strncmp(proto[i].name, "ESP", 3)) {
12900 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12901 pf->esp_support = true;
12903 pf->esp_support = false;
12908 /* Update customized pctype info */
12909 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12910 proto_num, proto, op);
12912 PMD_DRV_LOG(INFO, "No pctype is updated.");
12914 /* Update customized ptype info */
12915 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12916 proto_num, proto, op);
12918 PMD_DRV_LOG(INFO, "No ptype is updated.");
12923 /* Create a QinQ cloud filter
12925 * The Fortville NIC has limited resources for tunnel filters,
12926 * so we can only reuse existing filters.
12928 * In step 1 we define which Field Vector fields can be used for
12930 * As we do not have the inner tag defined as a field,
12931 * we have to define it first, by reusing one of L1 entries.
12933 * In step 2 we are replacing one of existing filter types with
12934 * a new one for QinQ.
12935 * As we reusing L1 and replacing L2, some of the default filter
12936 * types will disappear,which depends on L1 and L2 entries we reuse.
12938 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12940 * 1. Create L1 filter of outer vlan (12b) which will be in use
12941 * later when we define the cloud filter.
12942 * a. Valid_flags.replace_cloud = 0
12943 * b. Old_filter = 10 (Stag_Inner_Vlan)
12944 * c. New_filter = 0x10
12945 * d. TR bit = 0xff (optional, not used here)
12946 * e. Buffer – 2 entries:
12947 * i. Byte 0 = 8 (outer vlan FV index).
12949 * Byte 2-3 = 0x0fff
12950 * ii. Byte 0 = 37 (inner vlan FV index).
12952 * Byte 2-3 = 0x0fff
12955 * 2. Create cloud filter using two L1 filters entries: stag and
12956 * new filter(outer vlan+ inner vlan)
12957 * a. Valid_flags.replace_cloud = 1
12958 * b. Old_filter = 1 (instead of outer IP)
12959 * c. New_filter = 0x10
12960 * d. Buffer – 2 entries:
12961 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12962 * Byte 1-3 = 0 (rsv)
12963 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12964 * Byte 9-11 = 0 (rsv)
12967 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12969 int ret = -ENOTSUP;
12970 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12971 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12972 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12973 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12975 if (pf->support_multi_driver) {
12976 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12981 memset(&filter_replace, 0,
12982 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12983 memset(&filter_replace_buf, 0,
12984 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12986 /* create L1 filter */
12987 filter_replace.old_filter_type =
12988 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12989 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12990 filter_replace.tr_bit = 0;
12992 /* Prepare the buffer, 2 entries */
12993 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12994 filter_replace_buf.data[0] |=
12995 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12996 /* Field Vector 12b mask */
12997 filter_replace_buf.data[2] = 0xff;
12998 filter_replace_buf.data[3] = 0x0f;
12999 filter_replace_buf.data[4] =
13000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13001 filter_replace_buf.data[4] |=
13002 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13003 /* Field Vector 12b mask */
13004 filter_replace_buf.data[6] = 0xff;
13005 filter_replace_buf.data[7] = 0x0f;
13006 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13007 &filter_replace_buf);
13008 if (ret != I40E_SUCCESS)
13011 if (filter_replace.old_filter_type !=
13012 filter_replace.new_filter_type)
13013 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13014 " original: 0x%x, new: 0x%x",
13016 filter_replace.old_filter_type,
13017 filter_replace.new_filter_type);
13019 /* Apply the second L2 cloud filter */
13020 memset(&filter_replace, 0,
13021 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13022 memset(&filter_replace_buf, 0,
13023 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13025 /* create L2 filter, input for L2 filter will be L1 filter */
13026 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13027 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13028 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13030 /* Prepare the buffer, 2 entries */
13031 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13032 filter_replace_buf.data[0] |=
13033 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13034 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13035 filter_replace_buf.data[4] |=
13036 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13037 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13038 &filter_replace_buf);
13039 if (!ret && (filter_replace.old_filter_type !=
13040 filter_replace.new_filter_type))
13041 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13042 " original: 0x%x, new: 0x%x",
13044 filter_replace.old_filter_type,
13045 filter_replace.new_filter_type);
13051 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13052 const struct rte_flow_action_rss *in)
13054 if (in->key_len > RTE_DIM(out->key) ||
13055 in->queue_num > RTE_DIM(out->queue))
13057 if (!in->key && in->key_len)
13059 out->conf = (struct rte_flow_action_rss){
13061 .level = in->level,
13062 .types = in->types,
13063 .key_len = in->key_len,
13064 .queue_num = in->queue_num,
13065 .queue = memcpy(out->queue, in->queue,
13066 sizeof(*in->queue) * in->queue_num),
13069 out->conf.key = memcpy(out->key, in->key, in->key_len);
13073 /* Write HENA register to enable hash */
13075 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13077 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13078 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13082 ret = i40e_set_rss_key(pf->main_vsi, key,
13083 rss_conf->conf.key_len);
13087 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13088 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13089 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13090 I40E_WRITE_FLUSH(hw);
13095 /* Configure hash input set */
13097 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13099 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13100 struct rte_eth_input_set_conf conf;
13105 static const struct {
13107 enum rte_eth_input_set_field field;
13108 } inset_match_table[] = {
13109 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13110 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13111 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13112 RTE_ETH_INPUT_SET_L3_DST_IP4},
13113 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13114 RTE_ETH_INPUT_SET_UNKNOWN},
13115 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13116 RTE_ETH_INPUT_SET_UNKNOWN},
13118 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13119 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13120 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13121 RTE_ETH_INPUT_SET_L3_DST_IP4},
13122 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13123 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13124 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13125 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13127 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13128 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13129 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13130 RTE_ETH_INPUT_SET_L3_DST_IP4},
13131 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13132 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13133 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13134 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13136 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13137 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13138 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13139 RTE_ETH_INPUT_SET_L3_DST_IP4},
13140 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13141 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13142 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13143 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13145 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13146 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13147 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13148 RTE_ETH_INPUT_SET_L3_DST_IP4},
13149 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13150 RTE_ETH_INPUT_SET_UNKNOWN},
13151 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13152 RTE_ETH_INPUT_SET_UNKNOWN},
13154 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13155 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13156 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13157 RTE_ETH_INPUT_SET_L3_DST_IP6},
13158 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13159 RTE_ETH_INPUT_SET_UNKNOWN},
13160 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13161 RTE_ETH_INPUT_SET_UNKNOWN},
13163 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13164 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13165 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13166 RTE_ETH_INPUT_SET_L3_DST_IP6},
13167 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13168 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13169 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13170 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13172 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13173 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13174 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13175 RTE_ETH_INPUT_SET_L3_DST_IP6},
13176 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13177 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13178 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13179 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13181 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13182 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13183 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13184 RTE_ETH_INPUT_SET_L3_DST_IP6},
13185 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13186 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13187 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13188 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13190 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13191 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13192 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13193 RTE_ETH_INPUT_SET_L3_DST_IP6},
13194 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13195 RTE_ETH_INPUT_SET_UNKNOWN},
13196 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13197 RTE_ETH_INPUT_SET_UNKNOWN},
13200 mask0 = types & pf->adapter->flow_types_mask;
13201 conf.op = RTE_ETH_INPUT_SET_SELECT;
13202 conf.inset_size = 0;
13203 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13204 if (mask0 & (1ULL << i)) {
13205 conf.flow_type = i;
13210 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13211 if ((types & inset_match_table[j].type) ==
13212 inset_match_table[j].type) {
13213 if (inset_match_table[j].field ==
13214 RTE_ETH_INPUT_SET_UNKNOWN)
13217 conf.field[conf.inset_size] =
13218 inset_match_table[j].field;
13223 if (conf.inset_size) {
13224 ret = i40e_hash_filter_inset_select(hw, &conf);
13232 /* Look up the conflicted rule then mark it as invalid */
13234 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13235 struct i40e_rte_flow_rss_conf *conf)
13237 struct i40e_rss_filter *rss_item;
13238 uint64_t rss_inset;
13240 /* Clear input set bits before comparing the pctype */
13241 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13242 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13244 /* Look up the conflicted rule then mark it as invalid */
13245 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13246 if (!rss_item->rss_filter_info.valid)
13249 if (conf->conf.queue_num &&
13250 rss_item->rss_filter_info.conf.queue_num)
13251 rss_item->rss_filter_info.valid = false;
13253 if (conf->conf.types &&
13254 (rss_item->rss_filter_info.conf.types &
13256 (conf->conf.types & rss_inset))
13257 rss_item->rss_filter_info.valid = false;
13259 if (conf->conf.func ==
13260 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13261 rss_item->rss_filter_info.conf.func ==
13262 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13263 rss_item->rss_filter_info.valid = false;
13267 /* Configure RSS hash function */
13269 i40e_rss_config_hash_function(struct i40e_pf *pf,
13270 struct i40e_rte_flow_rss_conf *conf)
13272 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13277 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13278 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13279 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13280 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13281 I40E_WRITE_FLUSH(hw);
13282 i40e_rss_mark_invalid_rule(pf, conf);
13286 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13288 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13289 I40E_WRITE_FLUSH(hw);
13290 i40e_rss_mark_invalid_rule(pf, conf);
13291 } else if (conf->conf.func ==
13292 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13293 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13295 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13296 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13297 if (mask0 & (1UL << i))
13301 if (i == UINT64_BIT)
13304 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13305 j < I40E_FILTER_PCTYPE_MAX; j++) {
13306 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13307 i40e_write_global_rx_ctl(hw,
13309 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13316 /* Enable RSS according to the configuration */
13318 i40e_rss_enable_hash(struct i40e_pf *pf,
13319 struct i40e_rte_flow_rss_conf *conf)
13321 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13322 struct i40e_rte_flow_rss_conf rss_conf;
13324 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13327 memset(&rss_conf, 0, sizeof(rss_conf));
13328 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13330 /* Configure hash input set */
13331 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13334 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13335 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13336 /* Random default keys */
13337 static uint32_t rss_key_default[] = {0x6b793944,
13338 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13339 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13340 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13342 rss_conf.conf.key = (uint8_t *)rss_key_default;
13343 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13346 "No valid RSS key config for i40e, using default\n");
13349 rss_conf.conf.types |= rss_info->conf.types;
13350 i40e_rss_hash_set(pf, &rss_conf);
13352 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13353 i40e_rss_config_hash_function(pf, conf);
13355 i40e_rss_mark_invalid_rule(pf, conf);
13360 /* Configure RSS queue region */
13362 i40e_rss_config_queue_region(struct i40e_pf *pf,
13363 struct i40e_rte_flow_rss_conf *conf)
13365 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13370 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13371 * It's necessary to calculate the actual PF queues that are configured.
13373 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13374 num = i40e_pf_calc_configured_queues_num(pf);
13376 num = pf->dev_data->nb_rx_queues;
13378 num = RTE_MIN(num, conf->conf.queue_num);
13379 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13384 "No PF queues are configured to enable RSS for port %u",
13385 pf->dev_data->port_id);
13389 /* Fill in redirection table */
13390 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13393 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13394 hw->func_caps.rss_table_entry_width) - 1));
13396 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13399 i40e_rss_mark_invalid_rule(pf, conf);
13404 /* Configure RSS hash function to default */
13406 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13407 struct i40e_rte_flow_rss_conf *conf)
13409 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13414 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13415 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13416 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13418 "Hash function already set to Toeplitz");
13419 I40E_WRITE_FLUSH(hw);
13423 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13425 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13426 I40E_WRITE_FLUSH(hw);
13427 } else if (conf->conf.func ==
13428 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13429 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13431 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13432 if (mask0 & (1UL << i))
13436 if (i == UINT64_BIT)
13439 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13440 j < I40E_FILTER_PCTYPE_MAX; j++) {
13441 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13442 i40e_write_global_rx_ctl(hw,
13451 /* Disable RSS hash and configure default input set */
13453 i40e_rss_disable_hash(struct i40e_pf *pf,
13454 struct i40e_rte_flow_rss_conf *conf)
13456 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13458 struct i40e_rte_flow_rss_conf rss_conf;
13461 memset(&rss_conf, 0, sizeof(rss_conf));
13462 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13464 /* Disable RSS hash */
13465 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13466 i40e_rss_hash_set(pf, &rss_conf);
13468 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13469 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13470 !(conf->conf.types & (1ULL << i)))
13473 /* Configure default input set */
13474 struct rte_eth_input_set_conf input_conf = {
13475 .op = RTE_ETH_INPUT_SET_SELECT,
13479 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13480 i40e_hash_filter_inset_select(hw, &input_conf);
13483 rss_info->conf.types = rss_conf.conf.types;
13485 i40e_rss_clear_hash_function(pf, conf);
13490 /* Configure RSS queue region to default */
13492 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13494 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13495 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13496 uint16_t queue[I40E_MAX_Q_PER_TC];
13497 uint32_t num_rxq, i;
13501 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13503 for (j = 0; j < num_rxq; j++)
13506 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13507 * It's necessary to calculate the actual PF queues that are configured.
13509 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13510 num = i40e_pf_calc_configured_queues_num(pf);
13512 num = pf->dev_data->nb_rx_queues;
13514 num = RTE_MIN(num, num_rxq);
13515 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13520 "No PF queues are configured to enable RSS for port %u",
13521 pf->dev_data->port_id);
13525 /* Fill in redirection table */
13526 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13529 lut = (lut << 8) | (queue[j] & ((0x1 <<
13530 hw->func_caps.rss_table_entry_width) - 1));
13532 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13535 rss_info->conf.queue_num = 0;
13536 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13542 i40e_config_rss_filter(struct i40e_pf *pf,
13543 struct i40e_rte_flow_rss_conf *conf, bool add)
13545 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13546 struct rte_flow_action_rss update_conf = rss_info->conf;
13550 if (conf->conf.queue_num) {
13551 /* Configure RSS queue region */
13552 ret = i40e_rss_config_queue_region(pf, conf);
13556 update_conf.queue_num = conf->conf.queue_num;
13557 update_conf.queue = conf->conf.queue;
13558 } else if (conf->conf.func ==
13559 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13560 /* Configure hash function */
13561 ret = i40e_rss_config_hash_function(pf, conf);
13565 update_conf.func = conf->conf.func;
13567 /* Configure hash enable and input set */
13568 ret = i40e_rss_enable_hash(pf, conf);
13572 update_conf.types |= conf->conf.types;
13573 update_conf.key = conf->conf.key;
13574 update_conf.key_len = conf->conf.key_len;
13577 /* Update RSS info in pf */
13578 if (i40e_rss_conf_init(rss_info, &update_conf))
13584 if (conf->conf.queue_num)
13585 i40e_rss_clear_queue_region(pf);
13586 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13587 i40e_rss_clear_hash_function(pf, conf);
13589 i40e_rss_disable_hash(pf, conf);
13595 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13596 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13597 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13598 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13600 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13601 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13603 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13604 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13607 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13608 ETH_I40E_FLOATING_VEB_ARG "=1"
13609 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13610 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13611 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13612 ETH_I40E_USE_LATEST_VEC "=0|1");