drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 377                                        void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 715
 716 #ifndef I40E_GLQF_ORT
 717 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_PIT
 720 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for flexible payload, which should be set by NVM.
 727          * This should be removed from code once it is fixed in NVM.
 728          */
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 740         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 741
 742         /* Initialize registers for parsing packet type of QinQ */
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 748
 749 /*
 750  * Add a ethertype filter to drop all flow control frames transmitted
 751  * from VSIs.
 752 */
 753 static void
 754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 759                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 760         int ret;
 761
 762         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 763                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 764                                 pf->main_vsi_seid, 0,
 765                                 TRUE, NULL, NULL);
 766         if (ret)
 767                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 768                                   " frames from VSIs.");
 769 }
 770
 771 static int
 772 floating_veb_list_handler(__rte_unused const char *key,
 773                           const char *floating_veb_value,
 774                           void *opaque)
 775 {
 776         int idx = 0;
 777         unsigned int count = 0;
 778         char *end = NULL;
 779         int min, max;
 780         bool *vf_floating_veb = opaque;
 781
 782         while (isblank(*floating_veb_value))
 783                 floating_veb_value++;
 784
 785         /* Reset floating VEB configuration for VFs */
 786         for (idx = 0; idx < I40E_MAX_VF; idx++)
 787                 vf_floating_veb[idx] = false;
 788
 789         min = I40E_MAX_VF;
 790         do {
 791                 while (isblank(*floating_veb_value))
 792                         floating_veb_value++;
 793                 if (*floating_veb_value == '\0')
 794                         return -1;
 795                 errno = 0;
 796                 idx = strtoul(floating_veb_value, &end, 10);
 797                 if (errno || end == NULL)
 798                         return -1;
 799                 while (isblank(*end))
 800                         end++;
 801                 if (*end == '-') {
 802                         min = idx;
 803                 } else if ((*end == ';') || (*end == '\0')) {
 804                         max = idx;
 805                         if (min == I40E_MAX_VF)
 806                                 min = idx;
 807                         if (max >= I40E_MAX_VF)
 808                                 max = I40E_MAX_VF - 1;
 809                         for (idx = min; idx <= max; idx++) {
 810                                 vf_floating_veb[idx] = true;
 811                                 count++;
 812                         }
 813                         min = I40E_MAX_VF;
 814                 } else {
 815                         return -1;
 816                 }
 817                 floating_veb_value = end + 1;
 818         } while (*end != '\0');
 819
 820         if (count == 0)
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 config_vf_floating_veb(struct rte_devargs *devargs,
 828                        uint16_t floating_veb,
 829                        bool *vf_floating_veb)
 830 {
 831         struct rte_kvargs *kvlist;
 832         int i;
 833         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 834
 835         if (!floating_veb)
 836                 return;
 837         /* All the VFs attach to the floating VEB by default
 838          * when the floating VEB is enabled.
 839          */
 840         for (i = 0; i < I40E_MAX_VF; i++)
 841                 vf_floating_veb[i] = true;
 842
 843         if (devargs == NULL)
 844                 return;
 845
 846         kvlist = rte_kvargs_parse(devargs->args, NULL);
 847         if (kvlist == NULL)
 848                 return;
 849
 850         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         /* When the floating_veb_list parameter exists, all the VFs
 855          * will attach to the legacy VEB firstly, then configure VFs
 856          * to the floating VEB according to the floating_veb_list.
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_list,
 859                                floating_veb_list_handler,
 860                                vf_floating_veb) < 0) {
 861                 rte_kvargs_free(kvlist);
 862                 return;
 863         }
 864         rte_kvargs_free(kvlist);
 865 }
 866
 867 static int
 868 i40e_check_floating_handler(__rte_unused const char *key,
 869                             const char *value,
 870                             __rte_unused void *opaque)
 871 {
 872         if (strcmp(value, "1"))
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int
 879 is_floating_veb_supported(struct rte_devargs *devargs)
 880 {
 881         struct rte_kvargs *kvlist;
 882         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 883
 884         if (devargs == NULL)
 885                 return 0;
 886
 887         kvlist = rte_kvargs_parse(devargs->args, NULL);
 888         if (kvlist == NULL)
 889                 return 0;
 890
 891         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         /* Floating VEB is enabled when there's key-value:
 896          * enable_floating_veb=1
 897          */
 898         if (rte_kvargs_process(kvlist, floating_veb_key,
 899                                i40e_check_floating_handler, NULL) < 0) {
 900                 rte_kvargs_free(kvlist);
 901                 return 0;
 902         }
 903         rte_kvargs_free(kvlist);
 904
 905         return 1;
 906 }
 907
 908 static void
 909 config_floating_veb(struct rte_eth_dev *dev)
 910 {
 911         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 916
 917         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 918                 pf->floating_veb =
 919                         is_floating_veb_supported(pci_dev->device.devargs);
 920                 config_vf_floating_veb(pci_dev->device.devargs,
 921                                        pf->floating_veb,
 922                                        pf->floating_veb_list);
 923         } else {
 924                 pf->floating_veb = false;
 925         }
 926 }
 927
 928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 930
 931 static int
 932 eth_i40e_dev_init(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev;
 935         struct rte_intr_handle *intr_handle;
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         struct i40e_vsi *vsi;
 939         int ret;
 940         uint32_t len;
 941         uint8_t aq_fail = 0;
 942
 943         PMD_INIT_FUNC_TRACE();
 944
 945         dev->dev_ops = &i40e_eth_dev_ops;
 946         dev->rx_pkt_burst = i40e_recv_pkts;
 947         dev->tx_pkt_burst = i40e_xmit_pkts;
 948
 949         /* for secondary processes, we don't initialise any further as primary
 950          * has already done this work. Only check we don't need a different
 951          * RX function */
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 953                 i40e_set_rx_function(dev);
 954                 i40e_set_tx_function(dev);
 955                 return 0;
 956         }
 957         pci_dev = I40E_DEV_TO_PCI(dev);
 958         intr_handle = &pci_dev->intr_handle;
 959
 960         rte_eth_copy_pci_info(dev, pci_dev);
 961
 962         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 963         pf->adapter->eth_dev = dev;
 964         pf->dev_data = dev->data;
 965
 966         hw->back = I40E_PF_TO_ADAPTER(pf);
 967         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 968         if (!hw->hw_addr) {
 969                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 970                              "as address is NULL");
 971                 return -ENODEV;
 972         }
 973
 974         hw->vendor_id = pci_dev->id.vendor_id;
 975         hw->device_id = pci_dev->id.device_id;
 976         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 977         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 978         hw->bus.device = pci_dev->addr.devid;
 979         hw->bus.func = pci_dev->addr.function;
 980         hw->adapter_stopped = 0;
 981
 982         /* Make sure all is clean before doing PF reset */
 983         i40e_clear_hw(hw);
 984
 985         /* Initialize the hardware */
 986         i40e_hw_init(dev);
 987
 988         /* Reset here to make sure all is clean for each PF */
 989         ret = i40e_pf_reset(hw);
 990         if (ret) {
 991                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 992                 return ret;
 993         }
 994
 995         /* Initialize the shared code (base driver) */
 996         ret = i40e_init_shared_code(hw);
 997         if (ret) {
 998                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 999                 return ret;
1000         }
1001
1002         /*
1003          * To work around the NVM issue, initialize registers
1004          * for flexible payload and packet type of QinQ by
1005          * software. It should be removed once issues are fixed
1006          * in NVM.
1007          */
1008         i40e_GLQF_reg_init(hw);
1009
1010         /* Initialize the input set for filters (hash and fd) to default value */
1011         i40e_filter_input_set_init(pf);
1012
1013         /* Initialize the parameters for adminq */
1014         i40e_init_adminq_parameter(hw);
1015         ret = i40e_init_adminq(hw);
1016         if (ret != I40E_SUCCESS) {
1017                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1018                 return -EIO;
1019         }
1020         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1021                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1022                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1023                      ((hw->nvm.version >> 12) & 0xf),
1024                      ((hw->nvm.version >> 4) & 0xff),
1025                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1026
1027         /* Need the special FW version to support floating VEB */
1028         config_floating_veb(dev);
1029         /* Clear PXE mode */
1030         i40e_clear_pxe_mode(hw);
1031         ret = i40e_dev_sync_phy_type(hw);
1032         if (ret) {
1033                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1034                 goto err_sync_phy_type;
1035         }
1036         /*
1037          * On X710, performance number is far from the expectation on recent
1038          * firmware versions. The fix for this issue may not be integrated in
1039          * the following firmware version. So the workaround in software driver
1040          * is needed. It needs to modify the initial values of 3 internal only
1041          * registers. Note that the workaround can be removed when it is fixed
1042          * in firmware in the future.
1043          */
1044         i40e_configure_registers(hw);
1045
1046         /* Get hw capabilities */
1047         ret = i40e_get_cap(hw);
1048         if (ret != I40E_SUCCESS) {
1049                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1050                 goto err_get_capabilities;
1051         }
1052
1053         /* Initialize parameters for PF */
1054         ret = i40e_pf_parameter_init(dev);
1055         if (ret != 0) {
1056                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1057                 goto err_parameter_init;
1058         }
1059
1060         /* Initialize the queue management */
1061         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1062         if (ret < 0) {
1063                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1064                 goto err_qp_pool_init;
1065         }
1066         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1067                                 hw->func_caps.num_msix_vectors - 1);
1068         if (ret < 0) {
1069                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1070                 goto err_msix_pool_init;
1071         }
1072
1073         /* Initialize lan hmc */
1074         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1075                                 hw->func_caps.num_rx_qp, 0, 0);
1076         if (ret != I40E_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1078                 goto err_init_lan_hmc;
1079         }
1080
1081         /* Configure lan hmc */
1082         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1085                 goto err_configure_lan_hmc;
1086         }
1087
1088         /* Get and check the mac address */
1089         i40e_get_mac_addr(hw, hw->mac.addr);
1090         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1091                 PMD_INIT_LOG(ERR, "mac address is not valid");
1092                 ret = -EIO;
1093                 goto err_get_mac_addr;
1094         }
1095         /* Copy the permanent MAC address */
1096         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1097                         (struct ether_addr *) hw->mac.perm_addr);
1098
1099         /* Disable flow control */
1100         hw->fc.requested_mode = I40E_FC_NONE;
1101         i40e_set_fc(hw, &aq_fail, TRUE);
1102
1103         /* Set the global registers with default ether type value */
1104         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1105         if (ret != I40E_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1107                              "VLAN ether type");
1108                 goto err_setup_pf_switch;
1109         }
1110
1111         /* PF setup, which includes VSI setup */
1112         ret = i40e_pf_setup(pf);
1113         if (ret) {
1114                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1115                 goto err_setup_pf_switch;
1116         }
1117
1118         /* reset all stats of the device, including pf and main vsi */
1119         i40e_dev_stats_reset(dev);
1120
1121         vsi = pf->main_vsi;
1122
1123         /* Disable double vlan by default */
1124         i40e_vsi_config_double_vlan(vsi, FALSE);
1125
1126         /* Disable S-TAG identification when floating_veb is disabled */
1127         if (!pf->floating_veb) {
1128                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1129                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1130                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1131                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1132                 }
1133         }
1134
1135         if (!vsi->max_macaddrs)
1136                 len = ETHER_ADDR_LEN;
1137         else
1138                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1139
1140         /* Should be after VSI initialized */
1141         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1142         if (!dev->data->mac_addrs) {
1143                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1144                                         "for storing mac address");
1145                 goto err_mac_alloc;
1146         }
1147         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1148                                         &dev->data->mac_addrs[0]);
1149
1150         /* initialize pf host driver to setup SRIOV resource if applicable */
1151         i40e_pf_host_init(dev);
1152
1153         /* register callback func to eal lib */
1154         rte_intr_callback_register(intr_handle,
1155                                    i40e_dev_interrupt_handler, dev);
1156
1157         /* configure and enable device interrupt */
1158         i40e_pf_config_irq0(hw, TRUE);
1159         i40e_pf_enable_irq0(hw);
1160
1161         /* enable uio intr after callback register */
1162         rte_intr_enable(intr_handle);
1163         /*
1164          * Add an ethertype filter to drop all flow control frames transmitted
1165          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1166          * frames to wire.
1167          */
1168         i40e_add_tx_flow_control_drop_filter(pf);
1169
1170         /* Set the max frame size to 0x2600 by default,
1171          * in case other drivers changed the default value.
1172          */
1173         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1174
1175         /* initialize mirror rule list */
1176         TAILQ_INIT(&pf->mirror_list);
1177
1178         /* Init dcb to sw mode by default */
1179         ret = i40e_dcb_init_configure(dev, TRUE);
1180         if (ret != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1182                 pf->flags &= ~I40E_FLAG_DCB;
1183         }
1184
1185         return 0;
1186
1187 err_mac_alloc:
1188         i40e_vsi_release(pf->main_vsi);
1189 err_setup_pf_switch:
1190 err_get_mac_addr:
1191 err_configure_lan_hmc:
1192         (void)i40e_shutdown_lan_hmc(hw);
1193 err_init_lan_hmc:
1194         i40e_res_pool_destroy(&pf->msix_pool);
1195 err_msix_pool_init:
1196         i40e_res_pool_destroy(&pf->qp_pool);
1197 err_qp_pool_init:
1198 err_parameter_init:
1199 err_get_capabilities:
1200 err_sync_phy_type:
1201         (void)i40e_shutdown_adminq(hw);
1202
1203         return ret;
1204 }
1205
1206 static int
1207 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1208 {
1209         struct rte_pci_device *pci_dev;
1210         struct rte_intr_handle *intr_handle;
1211         struct i40e_hw *hw;
1212         struct i40e_filter_control_settings settings;
1213         int ret;
1214         uint8_t aq_fail = 0;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1219                 return 0;
1220
1221         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         pci_dev = I40E_DEV_TO_PCI(dev);
1223         intr_handle = &pci_dev->intr_handle;
1224
1225         if (hw->adapter_stopped == 0)
1226                 i40e_dev_close(dev);
1227
1228         dev->dev_ops = NULL;
1229         dev->rx_pkt_burst = NULL;
1230         dev->tx_pkt_burst = NULL;
1231
1232         /* Clear PXE mode */
1233         i40e_clear_pxe_mode(hw);
1234
1235         /* Unconfigure filter control */
1236         memset(&settings, 0, sizeof(settings));
1237         ret = i40e_set_filter_control(hw, &settings);
1238         if (ret)
1239                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1240                                         ret);
1241
1242         /* Disable flow control */
1243         hw->fc.requested_mode = I40E_FC_NONE;
1244         i40e_set_fc(hw, &aq_fail, TRUE);
1245
1246         /* uninitialize pf host driver */
1247         i40e_pf_host_uninit(dev);
1248
1249         rte_free(dev->data->mac_addrs);
1250         dev->data->mac_addrs = NULL;
1251
1252         /* disable uio intr before callback unregister */
1253         rte_intr_disable(intr_handle);
1254
1255         /* register callback func to eal lib */
1256         rte_intr_callback_unregister(intr_handle,
1257                                      i40e_dev_interrupt_handler, dev);
1258
1259         return 0;
1260 }
1261
1262 static int
1263 i40e_dev_configure(struct rte_eth_dev *dev)
1264 {
1265         struct i40e_adapter *ad =
1266                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1268         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1269         int i, ret;
1270
1271         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1272          * bulk allocation or vector Rx preconditions we will reset it.
1273          */
1274         ad->rx_bulk_alloc_allowed = true;
1275         ad->rx_vec_allowed = true;
1276         ad->tx_simple_allowed = true;
1277         ad->tx_vec_allowed = true;
1278
1279         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1280                 ret = i40e_fdir_setup(pf);
1281                 if (ret != I40E_SUCCESS) {
1282                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1283                         return -ENOTSUP;
1284                 }
1285                 ret = i40e_fdir_configure(dev);
1286                 if (ret < 0) {
1287                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1288                         goto err;
1289                 }
1290         } else
1291                 i40e_fdir_teardown(pf);
1292
1293         ret = i40e_dev_init_vlan(dev);
1294         if (ret < 0)
1295                 goto err;
1296
1297         /* VMDQ setup.
1298          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1299          *  RSS setting have different requirements.
1300          *  General PMD driver call sequence are NIC init, configure,
1301          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1302          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1303          *  applicable. So, VMDQ setting has to be done before
1304          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1305          *  For RSS setting, it will try to calculate actual configured RX queue
1306          *  number, which will be available after rx_queue_setup(). dev_start()
1307          *  function is good to place RSS setup.
1308          */
1309         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1310                 ret = i40e_vmdq_setup(dev);
1311                 if (ret)
1312                         goto err;
1313         }
1314
1315         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1316                 ret = i40e_dcb_setup(dev);
1317                 if (ret) {
1318                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1319                         goto err_dcb;
1320                 }
1321         }
1322
1323         return 0;
1324
1325 err_dcb:
1326         /* need to release vmdq resource if exists */
1327         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1328                 i40e_vsi_release(pf->vmdq[i].vsi);
1329                 pf->vmdq[i].vsi = NULL;
1330         }
1331         rte_free(pf->vmdq);
1332         pf->vmdq = NULL;
1333 err:
1334         /* need to release fdir resource if exists */
1335         i40e_fdir_teardown(pf);
1336         return ret;
1337 }
1338
1339 void
1340 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1341 {
1342         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1343         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1346         uint16_t msix_vect = vsi->msix_intr;
1347         uint16_t i;
1348
1349         for (i = 0; i < vsi->nb_qps; i++) {
1350                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1351                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1352                 rte_wmb();
1353         }
1354
1355         if (vsi->type != I40E_VSI_SRIOV) {
1356                 if (!rte_intr_allow_others(intr_handle)) {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1358                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1361                                        0);
1362                 } else {
1363                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1364                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365                         I40E_WRITE_REG(hw,
1366                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1367                                                        msix_vect - 1), 0);
1368                 }
1369         } else {
1370                 uint32_t reg;
1371                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1372                         vsi->user_param + (msix_vect - 1);
1373
1374                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1375                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1376         }
1377         I40E_WRITE_FLUSH(hw);
1378 }
1379
1380 static void
1381 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1382                        int base_queue, int nb_queue)
1383 {
1384         int i;
1385         uint32_t val;
1386         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1387
1388         /* Bind all RX queues to allocated MSIX interrupt */
1389         for (i = 0; i < nb_queue; i++) {
1390                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1391                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1392                         ((base_queue + i + 1) <<
1393                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1394                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1395                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1396
1397                 if (i == nb_queue - 1)
1398                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1399                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1400         }
1401
1402         /* Write first RX queue to Link list register as the head element */
1403         if (vsi->type != I40E_VSI_SRIOV) {
1404                 uint16_t interval =
1405                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1406
1407                 if (msix_vect == I40E_MISC_VEC_ID) {
1408                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1409                                        (base_queue <<
1410                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1411                                        (0x0 <<
1412                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1413                         I40E_WRITE_REG(hw,
1414                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1415                                        interval);
1416                 } else {
1417                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1418                                        (base_queue <<
1419                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1420                                        (0x0 <<
1421                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1422                         I40E_WRITE_REG(hw,
1423                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1424                                                        msix_vect - 1),
1425                                        interval);
1426                 }
1427         } else {
1428                 uint32_t reg;
1429
1430                 if (msix_vect == I40E_MISC_VEC_ID) {
1431                         I40E_WRITE_REG(hw,
1432                                        I40E_VPINT_LNKLST0(vsi->user_param),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1437                 } else {
1438                         /* num_msix_vectors_vf needs to minus irq0 */
1439                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1440                                 vsi->user_param + (msix_vect - 1);
1441
1442                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1443                                        (base_queue <<
1444                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1445                                        (0x0 <<
1446                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1447                 }
1448         }
1449
1450         I40E_WRITE_FLUSH(hw);
1451 }
1452
1453 void
1454 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1455 {
1456         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1457         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1458         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1459         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1460         uint16_t msix_vect = vsi->msix_intr;
1461         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1462         uint16_t queue_idx = 0;
1463         int record = 0;
1464         uint32_t val;
1465         int i;
1466
1467         for (i = 0; i < vsi->nb_qps; i++) {
1468                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1469                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1470         }
1471
1472         /* INTENA flag is not auto-cleared for interrupt */
1473         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1474         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1475                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1476                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1477         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1478
1479         /* VF bind interrupt */
1480         if (vsi->type == I40E_VSI_SRIOV) {
1481                 __vsi_queues_bind_intr(vsi, msix_vect,
1482                                        vsi->base_queue, vsi->nb_qps);
1483                 return;
1484         }
1485
1486         /* PF & VMDq bind interrupt */
1487         if (rte_intr_dp_is_en(intr_handle)) {
1488                 if (vsi->type == I40E_VSI_MAIN) {
1489                         queue_idx = 0;
1490                         record = 1;
1491                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1492                         struct i40e_vsi *main_vsi =
1493                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1494                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1495                         record = 1;
1496                 }
1497         }
1498
1499         for (i = 0; i < vsi->nb_used_qps; i++) {
1500                 if (nb_msix <= 1) {
1501                         if (!rte_intr_allow_others(intr_handle))
1502                                 /* allow to share MISC_VEC_ID */
1503                                 msix_vect = I40E_MISC_VEC_ID;
1504
1505                         /* no enough msix_vect, map all to one */
1506                         __vsi_queues_bind_intr(vsi, msix_vect,
1507                                                vsi->base_queue + i,
1508                                                vsi->nb_used_qps - i);
1509                         for (; !!record && i < vsi->nb_used_qps; i++)
1510                                 intr_handle->intr_vec[queue_idx + i] =
1511                                         msix_vect;
1512                         break;
1513                 }
1514                 /* 1:1 queue/msix_vect mapping */
1515                 __vsi_queues_bind_intr(vsi, msix_vect,
1516                                        vsi->base_queue + i, 1);
1517                 if (!!record)
1518                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1519
1520                 msix_vect++;
1521                 nb_msix--;
1522         }
1523 }
1524
1525 static void
1526 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1531         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1532         uint16_t interval = i40e_calc_itr_interval(\
1533                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1534         uint16_t msix_intr, i;
1535
1536         if (rte_intr_allow_others(intr_handle))
1537                 for (i = 0; i < vsi->nb_msix; i++) {
1538                         msix_intr = vsi->msix_intr + i;
1539                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1540                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1541                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1542                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1543                                 (interval <<
1544                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1545                 }
1546         else
1547                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1548                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1549                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1550                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1551                                (interval <<
1552                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1553
1554         I40E_WRITE_FLUSH(hw);
1555 }
1556
1557 static void
1558 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1559 {
1560         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1561         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1564         uint16_t msix_intr, i;
1565
1566         if (rte_intr_allow_others(intr_handle))
1567                 for (i = 0; i < vsi->nb_msix; i++) {
1568                         msix_intr = vsi->msix_intr + i;
1569                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1570                                        0);
1571                 }
1572         else
1573                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1574
1575         I40E_WRITE_FLUSH(hw);
1576 }
1577
1578 static inline uint8_t
1579 i40e_parse_link_speeds(uint16_t link_speeds)
1580 {
1581         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1582
1583         if (link_speeds & ETH_LINK_SPEED_40G)
1584                 link_speed |= I40E_LINK_SPEED_40GB;
1585         if (link_speeds & ETH_LINK_SPEED_25G)
1586                 link_speed |= I40E_LINK_SPEED_25GB;
1587         if (link_speeds & ETH_LINK_SPEED_20G)
1588                 link_speed |= I40E_LINK_SPEED_20GB;
1589         if (link_speeds & ETH_LINK_SPEED_10G)
1590                 link_speed |= I40E_LINK_SPEED_10GB;
1591         if (link_speeds & ETH_LINK_SPEED_1G)
1592                 link_speed |= I40E_LINK_SPEED_1GB;
1593         if (link_speeds & ETH_LINK_SPEED_100M)
1594                 link_speed |= I40E_LINK_SPEED_100MB;
1595
1596         return link_speed;
1597 }
1598
1599 static int
1600 i40e_phy_conf_link(struct i40e_hw *hw,
1601                    uint8_t abilities,
1602                    uint8_t force_speed)
1603 {
1604         enum i40e_status_code status;
1605         struct i40e_aq_get_phy_abilities_resp phy_ab;
1606         struct i40e_aq_set_phy_config phy_conf;
1607         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1608                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_LOW_POWER;
1611         const uint8_t advt = I40E_LINK_SPEED_40GB |
1612                         I40E_LINK_SPEED_25GB |
1613                         I40E_LINK_SPEED_10GB |
1614                         I40E_LINK_SPEED_1GB |
1615                         I40E_LINK_SPEED_100MB;
1616         int ret = -ENOTSUP;
1617
1618
1619         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1620                                               NULL);
1621         if (status)
1622                 return ret;
1623
1624         memset(&phy_conf, 0, sizeof(phy_conf));
1625
1626         /* bits 0-2 use the values from get_phy_abilities_resp */
1627         abilities &= ~mask;
1628         abilities |= phy_ab.abilities & mask;
1629
1630         /* update ablities and speed */
1631         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1632                 phy_conf.link_speed = advt;
1633         else
1634                 phy_conf.link_speed = force_speed;
1635
1636         phy_conf.abilities = abilities;
1637
1638         /* use get_phy_abilities_resp value for the rest */
1639         phy_conf.phy_type = phy_ab.phy_type;
1640         phy_conf.eee_capability = phy_ab.eee_capability;
1641         phy_conf.eeer = phy_ab.eeer_val;
1642         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1643
1644         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1645                     phy_ab.abilities, phy_ab.link_speed);
1646         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1647                     phy_conf.abilities, phy_conf.link_speed);
1648
1649         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1650         if (status)
1651                 return ret;
1652
1653         return I40E_SUCCESS;
1654 }
1655
1656 static int
1657 i40e_apply_link_speed(struct rte_eth_dev *dev)
1658 {
1659         uint8_t speed;
1660         uint8_t abilities = 0;
1661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct rte_eth_conf *conf = &dev->data->dev_conf;
1663
1664         speed = i40e_parse_link_speeds(conf->link_speeds);
1665         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1666                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1667         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1668                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1669         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1670
1671         /* Skip changing speed on 40G interfaces, FW does not support */
1672         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1673                 speed =  I40E_LINK_SPEED_UNKNOWN;
1674                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1675         }
1676
1677         return i40e_phy_conf_link(hw, abilities, speed);
1678 }
1679
1680 static int
1681 i40e_dev_start(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *main_vsi = pf->main_vsi;
1686         int ret, i;
1687         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         uint32_t intr_vector = 0;
1690
1691         hw->adapter_stopped = 0;
1692
1693         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1694                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1695                              dev->data->port_id);
1696                 return -EINVAL;
1697         }
1698
1699         rte_intr_disable(intr_handle);
1700
1701         if ((rte_intr_cap_multiple(intr_handle) ||
1702              !RTE_ETH_DEV_SRIOV(dev).active) &&
1703             dev->data->dev_conf.intr_conf.rxq != 0) {
1704                 intr_vector = dev->data->nb_rx_queues;
1705                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1706                         return -1;
1707         }
1708
1709         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1710                 intr_handle->intr_vec =
1711                         rte_zmalloc("intr_vec",
1712                                     dev->data->nb_rx_queues * sizeof(int),
1713                                     0);
1714                 if (!intr_handle->intr_vec) {
1715                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1716                                      " intr_vec\n", dev->data->nb_rx_queues);
1717                         return -ENOMEM;
1718                 }
1719         }
1720
1721         /* Initialize VSI */
1722         ret = i40e_dev_rxtx_init(pf);
1723         if (ret != I40E_SUCCESS) {
1724                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1725                 goto err_up;
1726         }
1727
1728         /* Map queues with MSIX interrupt */
1729         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1730                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1731         i40e_vsi_queues_bind_intr(main_vsi);
1732         i40e_vsi_enable_queues_intr(main_vsi);
1733
1734         /* Map VMDQ VSI queues with MSIX interrupt */
1735         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1736                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1737                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1738                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1739         }
1740
1741         /* enable FDIR MSIX interrupt */
1742         if (pf->fdir.fdir_vsi) {
1743                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1744                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1745         }
1746
1747         /* Enable all queues which have been configured */
1748         ret = i40e_dev_switch_queues(pf, TRUE);
1749         if (ret != I40E_SUCCESS) {
1750                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1751                 goto err_up;
1752         }
1753
1754         /* Enable receiving broadcast packets */
1755         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1756         if (ret != I40E_SUCCESS)
1757                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1758
1759         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1760                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1761                                                 true, NULL);
1762                 if (ret != I40E_SUCCESS)
1763                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1764         }
1765
1766         /* Apply link configure */
1767         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1768                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1769                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1770                                 ETH_LINK_SPEED_40G)) {
1771                 PMD_DRV_LOG(ERR, "Invalid link setting");
1772                 goto err_up;
1773         }
1774         ret = i40e_apply_link_speed(dev);
1775         if (I40E_SUCCESS != ret) {
1776                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1777                 goto err_up;
1778         }
1779
1780         if (!rte_intr_allow_others(intr_handle)) {
1781                 rte_intr_callback_unregister(intr_handle,
1782                                              i40e_dev_interrupt_handler,
1783                                              (void *)dev);
1784                 /* configure and enable device interrupt */
1785                 i40e_pf_config_irq0(hw, FALSE);
1786                 i40e_pf_enable_irq0(hw);
1787
1788                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1789                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1790                                      " no intr multiplex\n");
1791         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1792                 ret = i40e_aq_set_phy_int_mask(hw,
1793                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1794                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1795                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1796                 if (ret != I40E_SUCCESS)
1797                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1798
1799                 /* Call get_link_info aq commond to enable LSE */
1800                 i40e_dev_link_update(dev, 0);
1801         }
1802
1803         /* enable uio intr after callback register */
1804         rte_intr_enable(intr_handle);
1805
1806         return I40E_SUCCESS;
1807
1808 err_up:
1809         i40e_dev_switch_queues(pf, FALSE);
1810         i40e_dev_clear_queues(dev);
1811
1812         return ret;
1813 }
1814
1815 static void
1816 i40e_dev_stop(struct rte_eth_dev *dev)
1817 {
1818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819         struct i40e_vsi *main_vsi = pf->main_vsi;
1820         struct i40e_mirror_rule *p_mirror;
1821         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1822         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1823         int i;
1824
1825         /* Disable all queues */
1826         i40e_dev_switch_queues(pf, FALSE);
1827
1828         /* un-map queues with interrupt registers */
1829         i40e_vsi_disable_queues_intr(main_vsi);
1830         i40e_vsi_queues_unbind_intr(main_vsi);
1831
1832         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1833                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1834                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1835         }
1836
1837         if (pf->fdir.fdir_vsi) {
1838                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1839                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1840         }
1841         /* Clear all queues and release memory */
1842         i40e_dev_clear_queues(dev);
1843
1844         /* Set link down */
1845         i40e_dev_set_link_down(dev);
1846
1847         /* Remove all mirror rules */
1848         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1849                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1850                 rte_free(p_mirror);
1851         }
1852         pf->nb_mirror_rule = 0;
1853
1854         if (!rte_intr_allow_others(intr_handle))
1855                 /* resume to the default handler */
1856                 rte_intr_callback_register(intr_handle,
1857                                            i40e_dev_interrupt_handler,
1858                                            (void *)dev);
1859
1860         /* Clean datapath event and queue/vec mapping */
1861         rte_intr_efd_disable(intr_handle);
1862         if (intr_handle->intr_vec) {
1863                 rte_free(intr_handle->intr_vec);
1864                 intr_handle->intr_vec = NULL;
1865         }
1866 }
1867
1868 static void
1869 i40e_dev_close(struct rte_eth_dev *dev)
1870 {
1871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875         uint32_t reg;
1876         int i;
1877
1878         PMD_INIT_FUNC_TRACE();
1879
1880         i40e_dev_stop(dev);
1881         hw->adapter_stopped = 1;
1882         i40e_dev_free_queues(dev);
1883
1884         /* Disable interrupt */
1885         i40e_pf_disable_irq0(hw);
1886         rte_intr_disable(intr_handle);
1887
1888         /* shutdown and destroy the HMC */
1889         i40e_shutdown_lan_hmc(hw);
1890
1891         /* release all the existing VSIs and VEBs */
1892         i40e_fdir_teardown(pf);
1893         i40e_vsi_release(pf->main_vsi);
1894
1895         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1896                 i40e_vsi_release(pf->vmdq[i].vsi);
1897                 pf->vmdq[i].vsi = NULL;
1898         }
1899
1900         rte_free(pf->vmdq);
1901         pf->vmdq = NULL;
1902
1903         /* shutdown the adminq */
1904         i40e_aq_queue_shutdown(hw, true);
1905         i40e_shutdown_adminq(hw);
1906
1907         i40e_res_pool_destroy(&pf->qp_pool);
1908         i40e_res_pool_destroy(&pf->msix_pool);
1909
1910         /* force a PF reset to clean anything leftover */
1911         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1912         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1913                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1914         I40E_WRITE_FLUSH(hw);
1915 }
1916
1917 static void
1918 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int status;
1924
1925         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1926                                                      true, NULL, true);
1927         if (status != I40E_SUCCESS)
1928                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1929
1930         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1931                                                         TRUE, NULL);
1932         if (status != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1934
1935 }
1936
1937 static void
1938 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1939 {
1940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct i40e_vsi *vsi = pf->main_vsi;
1943         int status;
1944
1945         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1946                                                      false, NULL, true);
1947         if (status != I40E_SUCCESS)
1948                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1949
1950         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1951                                                         false, NULL);
1952         if (status != I40E_SUCCESS)
1953                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1954 }
1955
1956 static void
1957 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1958 {
1959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct i40e_vsi *vsi = pf->main_vsi;
1962         int ret;
1963
1964         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1965         if (ret != I40E_SUCCESS)
1966                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1967 }
1968
1969 static void
1970 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1971 {
1972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         struct i40e_vsi *vsi = pf->main_vsi;
1975         int ret;
1976
1977         if (dev->data->promiscuous == 1)
1978                 return; /* must remain in all_multicast mode */
1979
1980         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1981                                 vsi->seid, FALSE, NULL);
1982         if (ret != I40E_SUCCESS)
1983                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1984 }
1985
1986 /*
1987  * Set device link up.
1988  */
1989 static int
1990 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1991 {
1992         /* re-apply link speed setting */
1993         return i40e_apply_link_speed(dev);
1994 }
1995
1996 /*
1997  * Set device link down.
1998  */
1999 static int
2000 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2001 {
2002         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2003         uint8_t abilities = 0;
2004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005
2006         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2007                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2008         return i40e_phy_conf_link(hw, abilities, speed);
2009 }
2010
2011 int
2012 i40e_dev_link_update(struct rte_eth_dev *dev,
2013                      int wait_to_complete)
2014 {
2015 #define CHECK_INTERVAL 100  /* 100ms */
2016 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct i40e_link_status link_status;
2019         struct rte_eth_link link, old;
2020         int status;
2021         unsigned rep_cnt = MAX_REPEAT_TIME;
2022         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2023
2024         memset(&link, 0, sizeof(link));
2025         memset(&old, 0, sizeof(old));
2026         memset(&link_status, 0, sizeof(link_status));
2027         rte_i40e_dev_atomic_read_link_status(dev, &old);
2028
2029         do {
2030                 /* Get link status information from hardware */
2031                 status = i40e_aq_get_link_info(hw, enable_lse,
2032                                                 &link_status, NULL);
2033                 if (status != I40E_SUCCESS) {
2034                         link.link_speed = ETH_SPEED_NUM_100M;
2035                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2036                         PMD_DRV_LOG(ERR, "Failed to get link info");
2037                         goto out;
2038                 }
2039
2040                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2041                 if (!wait_to_complete)
2042                         break;
2043
2044                 rte_delay_ms(CHECK_INTERVAL);
2045         } while (!link.link_status && rep_cnt--);
2046
2047         if (!link.link_status)
2048                 goto out;
2049
2050         /* i40e uses full duplex only */
2051         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2052
2053         /* Parse the link status */
2054         switch (link_status.link_speed) {
2055         case I40E_LINK_SPEED_100MB:
2056                 link.link_speed = ETH_SPEED_NUM_100M;
2057                 break;
2058         case I40E_LINK_SPEED_1GB:
2059                 link.link_speed = ETH_SPEED_NUM_1G;
2060                 break;
2061         case I40E_LINK_SPEED_10GB:
2062                 link.link_speed = ETH_SPEED_NUM_10G;
2063                 break;
2064         case I40E_LINK_SPEED_20GB:
2065                 link.link_speed = ETH_SPEED_NUM_20G;
2066                 break;
2067         case I40E_LINK_SPEED_25GB:
2068                 link.link_speed = ETH_SPEED_NUM_25G;
2069                 break;
2070         case I40E_LINK_SPEED_40GB:
2071                 link.link_speed = ETH_SPEED_NUM_40G;
2072                 break;
2073         default:
2074                 link.link_speed = ETH_SPEED_NUM_100M;
2075                 break;
2076         }
2077
2078         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2079                         ETH_LINK_SPEED_FIXED);
2080
2081 out:
2082         rte_i40e_dev_atomic_write_link_status(dev, &link);
2083         if (link.link_status == old.link_status)
2084                 return -1;
2085
2086         return 0;
2087 }
2088
2089 /* Get all the statistics of a VSI */
2090 void
2091 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2092 {
2093         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2094         struct i40e_eth_stats *nes = &vsi->eth_stats;
2095         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2096         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2097
2098         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2099                             vsi->offset_loaded, &oes->rx_bytes,
2100                             &nes->rx_bytes);
2101         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2102                             vsi->offset_loaded, &oes->rx_unicast,
2103                             &nes->rx_unicast);
2104         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2105                             vsi->offset_loaded, &oes->rx_multicast,
2106                             &nes->rx_multicast);
2107         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2108                             vsi->offset_loaded, &oes->rx_broadcast,
2109                             &nes->rx_broadcast);
2110         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2111                             &oes->rx_discards, &nes->rx_discards);
2112         /* GLV_REPC not supported */
2113         /* GLV_RMPC not supported */
2114         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2115                             &oes->rx_unknown_protocol,
2116                             &nes->rx_unknown_protocol);
2117         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2118                             vsi->offset_loaded, &oes->tx_bytes,
2119                             &nes->tx_bytes);
2120         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2121                             vsi->offset_loaded, &oes->tx_unicast,
2122                             &nes->tx_unicast);
2123         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2124                             vsi->offset_loaded, &oes->tx_multicast,
2125                             &nes->tx_multicast);
2126         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2127                             vsi->offset_loaded,  &oes->tx_broadcast,
2128                             &nes->tx_broadcast);
2129         /* GLV_TDPC not supported */
2130         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2131                             &oes->tx_errors, &nes->tx_errors);
2132         vsi->offset_loaded = true;
2133
2134         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2135                     vsi->vsi_id);
2136         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2137         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2138         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2139         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2140         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2141         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2142                     nes->rx_unknown_protocol);
2143         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2144         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2145         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2146         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2147         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2148         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2149         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2150                     vsi->vsi_id);
2151 }
2152
2153 static void
2154 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2155 {
2156         unsigned int i;
2157         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2158         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2159
2160         /* Get statistics of struct i40e_eth_stats */
2161         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2162                             I40E_GLPRT_GORCL(hw->port),
2163                             pf->offset_loaded, &os->eth.rx_bytes,
2164                             &ns->eth.rx_bytes);
2165         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2166                             I40E_GLPRT_UPRCL(hw->port),
2167                             pf->offset_loaded, &os->eth.rx_unicast,
2168                             &ns->eth.rx_unicast);
2169         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2170                             I40E_GLPRT_MPRCL(hw->port),
2171                             pf->offset_loaded, &os->eth.rx_multicast,
2172                             &ns->eth.rx_multicast);
2173         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2174                             I40E_GLPRT_BPRCL(hw->port),
2175                             pf->offset_loaded, &os->eth.rx_broadcast,
2176                             &ns->eth.rx_broadcast);
2177         /* Workaround: CRC size should not be included in byte statistics,
2178          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2179          */
2180         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2181                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2182
2183         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2184                             pf->offset_loaded, &os->eth.rx_discards,
2185                             &ns->eth.rx_discards);
2186         /* GLPRT_REPC not supported */
2187         /* GLPRT_RMPC not supported */
2188         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2189                             pf->offset_loaded,
2190                             &os->eth.rx_unknown_protocol,
2191                             &ns->eth.rx_unknown_protocol);
2192         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2193                             I40E_GLPRT_GOTCL(hw->port),
2194                             pf->offset_loaded, &os->eth.tx_bytes,
2195                             &ns->eth.tx_bytes);
2196         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2197                             I40E_GLPRT_UPTCL(hw->port),
2198                             pf->offset_loaded, &os->eth.tx_unicast,
2199                             &ns->eth.tx_unicast);
2200         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2201                             I40E_GLPRT_MPTCL(hw->port),
2202                             pf->offset_loaded, &os->eth.tx_multicast,
2203                             &ns->eth.tx_multicast);
2204         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2205                             I40E_GLPRT_BPTCL(hw->port),
2206                             pf->offset_loaded, &os->eth.tx_broadcast,
2207                             &ns->eth.tx_broadcast);
2208         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2209                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2210         /* GLPRT_TEPC not supported */
2211
2212         /* additional port specific stats */
2213         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2214                             pf->offset_loaded, &os->tx_dropped_link_down,
2215                             &ns->tx_dropped_link_down);
2216         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2217                             pf->offset_loaded, &os->crc_errors,
2218                             &ns->crc_errors);
2219         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2220                             pf->offset_loaded, &os->illegal_bytes,
2221                             &ns->illegal_bytes);
2222         /* GLPRT_ERRBC not supported */
2223         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2224                             pf->offset_loaded, &os->mac_local_faults,
2225                             &ns->mac_local_faults);
2226         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2227                             pf->offset_loaded, &os->mac_remote_faults,
2228                             &ns->mac_remote_faults);
2229         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2230                             pf->offset_loaded, &os->rx_length_errors,
2231                             &ns->rx_length_errors);
2232         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2233                             pf->offset_loaded, &os->link_xon_rx,
2234                             &ns->link_xon_rx);
2235         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2236                             pf->offset_loaded, &os->link_xoff_rx,
2237                             &ns->link_xoff_rx);
2238         for (i = 0; i < 8; i++) {
2239                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2240                                     pf->offset_loaded,
2241                                     &os->priority_xon_rx[i],
2242                                     &ns->priority_xon_rx[i]);
2243                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2244                                     pf->offset_loaded,
2245                                     &os->priority_xoff_rx[i],
2246                                     &ns->priority_xoff_rx[i]);
2247         }
2248         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2249                             pf->offset_loaded, &os->link_xon_tx,
2250                             &ns->link_xon_tx);
2251         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2252                             pf->offset_loaded, &os->link_xoff_tx,
2253                             &ns->link_xoff_tx);
2254         for (i = 0; i < 8; i++) {
2255                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2256                                     pf->offset_loaded,
2257                                     &os->priority_xon_tx[i],
2258                                     &ns->priority_xon_tx[i]);
2259                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2260                                     pf->offset_loaded,
2261                                     &os->priority_xoff_tx[i],
2262                                     &ns->priority_xoff_tx[i]);
2263                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2264                                     pf->offset_loaded,
2265                                     &os->priority_xon_2_xoff[i],
2266                                     &ns->priority_xon_2_xoff[i]);
2267         }
2268         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2269                             I40E_GLPRT_PRC64L(hw->port),
2270                             pf->offset_loaded, &os->rx_size_64,
2271                             &ns->rx_size_64);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2273                             I40E_GLPRT_PRC127L(hw->port),
2274                             pf->offset_loaded, &os->rx_size_127,
2275                             &ns->rx_size_127);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2277                             I40E_GLPRT_PRC255L(hw->port),
2278                             pf->offset_loaded, &os->rx_size_255,
2279                             &ns->rx_size_255);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2281                             I40E_GLPRT_PRC511L(hw->port),
2282                             pf->offset_loaded, &os->rx_size_511,
2283                             &ns->rx_size_511);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2285                             I40E_GLPRT_PRC1023L(hw->port),
2286                             pf->offset_loaded, &os->rx_size_1023,
2287                             &ns->rx_size_1023);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2289                             I40E_GLPRT_PRC1522L(hw->port),
2290                             pf->offset_loaded, &os->rx_size_1522,
2291                             &ns->rx_size_1522);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2293                             I40E_GLPRT_PRC9522L(hw->port),
2294                             pf->offset_loaded, &os->rx_size_big,
2295                             &ns->rx_size_big);
2296         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2297                             pf->offset_loaded, &os->rx_undersize,
2298                             &ns->rx_undersize);
2299         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2300                             pf->offset_loaded, &os->rx_fragments,
2301                             &ns->rx_fragments);
2302         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2303                             pf->offset_loaded, &os->rx_oversize,
2304                             &ns->rx_oversize);
2305         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2306                             pf->offset_loaded, &os->rx_jabber,
2307                             &ns->rx_jabber);
2308         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2309                             I40E_GLPRT_PTC64L(hw->port),
2310                             pf->offset_loaded, &os->tx_size_64,
2311                             &ns->tx_size_64);
2312         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2313                             I40E_GLPRT_PTC127L(hw->port),
2314                             pf->offset_loaded, &os->tx_size_127,
2315                             &ns->tx_size_127);
2316         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2317                             I40E_GLPRT_PTC255L(hw->port),
2318                             pf->offset_loaded, &os->tx_size_255,
2319                             &ns->tx_size_255);
2320         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2321                             I40E_GLPRT_PTC511L(hw->port),
2322                             pf->offset_loaded, &os->tx_size_511,
2323                             &ns->tx_size_511);
2324         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2325                             I40E_GLPRT_PTC1023L(hw->port),
2326                             pf->offset_loaded, &os->tx_size_1023,
2327                             &ns->tx_size_1023);
2328         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2329                             I40E_GLPRT_PTC1522L(hw->port),
2330                             pf->offset_loaded, &os->tx_size_1522,
2331                             &ns->tx_size_1522);
2332         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2333                             I40E_GLPRT_PTC9522L(hw->port),
2334                             pf->offset_loaded, &os->tx_size_big,
2335                             &ns->tx_size_big);
2336         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2337                            pf->offset_loaded,
2338                            &os->fd_sb_match, &ns->fd_sb_match);
2339         /* GLPRT_MSPDC not supported */
2340         /* GLPRT_XEC not supported */
2341
2342         pf->offset_loaded = true;
2343
2344         if (pf->main_vsi)
2345                 i40e_update_vsi_stats(pf->main_vsi);
2346 }
2347
2348 /* Get all statistics of a port */
2349 static void
2350 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2351 {
2352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2355         unsigned i;
2356
2357         /* call read registers - updates values, now write them to struct */
2358         i40e_read_stats_registers(pf, hw);
2359
2360         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2361                         pf->main_vsi->eth_stats.rx_multicast +
2362                         pf->main_vsi->eth_stats.rx_broadcast -
2363                         pf->main_vsi->eth_stats.rx_discards;
2364         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2365                         pf->main_vsi->eth_stats.tx_multicast +
2366                         pf->main_vsi->eth_stats.tx_broadcast;
2367         stats->ibytes   = ns->eth.rx_bytes;
2368         stats->obytes   = ns->eth.tx_bytes;
2369         stats->oerrors  = ns->eth.tx_errors +
2370                         pf->main_vsi->eth_stats.tx_errors;
2371
2372         /* Rx Errors */
2373         stats->imissed  = ns->eth.rx_discards +
2374                         pf->main_vsi->eth_stats.rx_discards;
2375         stats->ierrors  = ns->crc_errors +
2376                         ns->rx_length_errors + ns->rx_undersize +
2377                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2378
2379         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2380         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2381         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2382         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2383         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2384         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2385         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2386                     ns->eth.rx_unknown_protocol);
2387         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2388         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2389         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2390         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2391         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2392         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2393
2394         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2395                     ns->tx_dropped_link_down);
2396         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2397         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2398                     ns->illegal_bytes);
2399         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2400         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2401                     ns->mac_local_faults);
2402         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2403                     ns->mac_remote_faults);
2404         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2405                     ns->rx_length_errors);
2406         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2407         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2408         for (i = 0; i < 8; i++) {
2409                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2410                                 i, ns->priority_xon_rx[i]);
2411                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2412                                 i, ns->priority_xoff_rx[i]);
2413         }
2414         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2415         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2416         for (i = 0; i < 8; i++) {
2417                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2418                                 i, ns->priority_xon_tx[i]);
2419                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2420                                 i, ns->priority_xoff_tx[i]);
2421                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2422                                 i, ns->priority_xon_2_xoff[i]);
2423         }
2424         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2425         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2426         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2427         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2428         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2429         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2430         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2431         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2432         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2433         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2434         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2435         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2436         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2437         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2438         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2439         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2440         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2441         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2442         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2443                         ns->mac_short_packet_dropped);
2444         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2445                     ns->checksum_error);
2446         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2447         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2448 }
2449
2450 /* Reset the statistics */
2451 static void
2452 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2453 {
2454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         /* Mark PF and VSI stats to update the offset, aka "reset" */
2458         pf->offset_loaded = false;
2459         if (pf->main_vsi)
2460                 pf->main_vsi->offset_loaded = false;
2461
2462         /* read the stats, reading current register values into offset */
2463         i40e_read_stats_registers(pf, hw);
2464 }
2465
2466 static uint32_t
2467 i40e_xstats_calc_num(void)
2468 {
2469         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2470                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2471                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2472 }
2473
2474 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2475                                      struct rte_eth_xstat_name *xstats_names,
2476                                      __rte_unused unsigned limit)
2477 {
2478         unsigned count = 0;
2479         unsigned i, prio;
2480
2481         if (xstats_names == NULL)
2482                 return i40e_xstats_calc_num();
2483
2484         /* Note: limit checked in rte_eth_xstats_names() */
2485
2486         /* Get stats from i40e_eth_stats struct */
2487         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2488                 snprintf(xstats_names[count].name,
2489                          sizeof(xstats_names[count].name),
2490                          "%s", rte_i40e_stats_strings[i].name);
2491                 count++;
2492         }
2493
2494         /* Get individiual stats from i40e_hw_port struct */
2495         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2496                 snprintf(xstats_names[count].name,
2497                         sizeof(xstats_names[count].name),
2498                          "%s", rte_i40e_hw_port_strings[i].name);
2499                 count++;
2500         }
2501
2502         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2503                 for (prio = 0; prio < 8; prio++) {
2504                         snprintf(xstats_names[count].name,
2505                                  sizeof(xstats_names[count].name),
2506                                  "rx_priority%u_%s", prio,
2507                                  rte_i40e_rxq_prio_strings[i].name);
2508                         count++;
2509                 }
2510         }
2511
2512         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2513                 for (prio = 0; prio < 8; prio++) {
2514                         snprintf(xstats_names[count].name,
2515                                  sizeof(xstats_names[count].name),
2516                                  "tx_priority%u_%s", prio,
2517                                  rte_i40e_txq_prio_strings[i].name);
2518                         count++;
2519                 }
2520         }
2521         return count;
2522 }
2523
2524 static int
2525 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2526                     unsigned n)
2527 {
2528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2529         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         unsigned i, count, prio;
2531         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2532
2533         count = i40e_xstats_calc_num();
2534         if (n < count)
2535                 return count;
2536
2537         i40e_read_stats_registers(pf, hw);
2538
2539         if (xstats == NULL)
2540                 return 0;
2541
2542         count = 0;
2543
2544         /* Get stats from i40e_eth_stats struct */
2545         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2546                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2547                         rte_i40e_stats_strings[i].offset);
2548                 xstats[count].id = count;
2549                 count++;
2550         }
2551
2552         /* Get individiual stats from i40e_hw_port struct */
2553         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2554                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2555                         rte_i40e_hw_port_strings[i].offset);
2556                 xstats[count].id = count;
2557                 count++;
2558         }
2559
2560         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2561                 for (prio = 0; prio < 8; prio++) {
2562                         xstats[count].value =
2563                                 *(uint64_t *)(((char *)hw_stats) +
2564                                 rte_i40e_rxq_prio_strings[i].offset +
2565                                 (sizeof(uint64_t) * prio));
2566                         xstats[count].id = count;
2567                         count++;
2568                 }
2569         }
2570
2571         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2572                 for (prio = 0; prio < 8; prio++) {
2573                         xstats[count].value =
2574                                 *(uint64_t *)(((char *)hw_stats) +
2575                                 rte_i40e_txq_prio_strings[i].offset +
2576                                 (sizeof(uint64_t) * prio));
2577                         xstats[count].id = count;
2578                         count++;
2579                 }
2580         }
2581
2582         return count;
2583 }
2584
2585 static int
2586 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2587                                  __rte_unused uint16_t queue_id,
2588                                  __rte_unused uint8_t stat_idx,
2589                                  __rte_unused uint8_t is_rx)
2590 {
2591         PMD_INIT_FUNC_TRACE();
2592
2593         return -ENOSYS;
2594 }
2595
2596 static void
2597 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2598 {
2599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601         struct i40e_vsi *vsi = pf->main_vsi;
2602         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2603
2604         dev_info->pci_dev = pci_dev;
2605         dev_info->max_rx_queues = vsi->nb_qps;
2606         dev_info->max_tx_queues = vsi->nb_qps;
2607         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2608         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2609         dev_info->max_mac_addrs = vsi->max_macaddrs;
2610         dev_info->max_vfs = pci_dev->max_vfs;
2611         dev_info->rx_offload_capa =
2612                 DEV_RX_OFFLOAD_VLAN_STRIP |
2613                 DEV_RX_OFFLOAD_QINQ_STRIP |
2614                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2615                 DEV_RX_OFFLOAD_UDP_CKSUM |
2616                 DEV_RX_OFFLOAD_TCP_CKSUM;
2617         dev_info->tx_offload_capa =
2618                 DEV_TX_OFFLOAD_VLAN_INSERT |
2619                 DEV_TX_OFFLOAD_QINQ_INSERT |
2620                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2621                 DEV_TX_OFFLOAD_UDP_CKSUM |
2622                 DEV_TX_OFFLOAD_TCP_CKSUM |
2623                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2624                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2625                 DEV_TX_OFFLOAD_TCP_TSO |
2626                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2627                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2628                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2629                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2630         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2631                                                 sizeof(uint32_t);
2632         dev_info->reta_size = pf->hash_lut_size;
2633         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2634
2635         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2636                 .rx_thresh = {
2637                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2638                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2639                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2640                 },
2641                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2642                 .rx_drop_en = 0,
2643         };
2644
2645         dev_info->default_txconf = (struct rte_eth_txconf) {
2646                 .tx_thresh = {
2647                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2648                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2649                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2650                 },
2651                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2652                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2653                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2654                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2655         };
2656
2657         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2658                 .nb_max = I40E_MAX_RING_DESC,
2659                 .nb_min = I40E_MIN_RING_DESC,
2660                 .nb_align = I40E_ALIGN_RING_DESC,
2661         };
2662
2663         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2664                 .nb_max = I40E_MAX_RING_DESC,
2665                 .nb_min = I40E_MIN_RING_DESC,
2666                 .nb_align = I40E_ALIGN_RING_DESC,
2667         };
2668
2669         if (pf->flags & I40E_FLAG_VMDQ) {
2670                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2671                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2672                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2673                                                 pf->max_nb_vmdq_vsi;
2674                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2675                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2676                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2677         }
2678
2679         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2680                 /* For XL710 */
2681                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2682         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2683                 /* For XXV710 */
2684                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2685         else
2686                 /* For X710 */
2687                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2688 }
2689
2690 static int
2691 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2692 {
2693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2694         struct i40e_vsi *vsi = pf->main_vsi;
2695         PMD_INIT_FUNC_TRACE();
2696
2697         if (on)
2698                 return i40e_vsi_add_vlan(vsi, vlan_id);
2699         else
2700                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2701 }
2702
2703 static int
2704 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2705                    enum rte_vlan_type vlan_type,
2706                    uint16_t tpid)
2707 {
2708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709         uint64_t reg_r = 0, reg_w = 0;
2710         uint16_t reg_id = 0;
2711         int ret = 0;
2712         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2713
2714         switch (vlan_type) {
2715         case ETH_VLAN_TYPE_OUTER:
2716                 if (qinq)
2717                         reg_id = 2;
2718                 else
2719                         reg_id = 3;
2720                 break;
2721         case ETH_VLAN_TYPE_INNER:
2722                 if (qinq)
2723                         reg_id = 3;
2724                 else {
2725                         ret = -EINVAL;
2726                         PMD_DRV_LOG(ERR,
2727                                 "Unsupported vlan type in single vlan.\n");
2728                         return ret;
2729                 }
2730                 break;
2731         default:
2732                 ret = -EINVAL;
2733                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2734                 return ret;
2735         }
2736         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2737                                           &reg_r, NULL);
2738         if (ret != I40E_SUCCESS) {
2739                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2740                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2741                 ret = -EIO;
2742                 return ret;
2743         }
2744         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2745                     "0x%08"PRIx64"", reg_id, reg_r);
2746
2747         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2748         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2749         if (reg_r == reg_w) {
2750                 ret = 0;
2751                 PMD_DRV_LOG(DEBUG, "No need to write");
2752                 return ret;
2753         }
2754
2755         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2756                                            reg_w, NULL);
2757         if (ret != I40E_SUCCESS) {
2758                 ret = -EIO;
2759                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2760                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2761                 return ret;
2762         }
2763         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2764                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2765
2766         return ret;
2767 }
2768
2769 static void
2770 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2771 {
2772         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2773         struct i40e_vsi *vsi = pf->main_vsi;
2774
2775         if (mask & ETH_VLAN_FILTER_MASK) {
2776                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2777                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2778                 else
2779                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2780         }
2781
2782         if (mask & ETH_VLAN_STRIP_MASK) {
2783                 /* Enable or disable VLAN stripping */
2784                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2785                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2786                 else
2787                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2788         }
2789
2790         if (mask & ETH_VLAN_EXTEND_MASK) {
2791                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2792                         i40e_vsi_config_double_vlan(vsi, TRUE);
2793                         /* Set global registers with default ether type value */
2794                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2795                                            ETHER_TYPE_VLAN);
2796                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2797                                            ETHER_TYPE_VLAN);
2798                 }
2799                 else
2800                         i40e_vsi_config_double_vlan(vsi, FALSE);
2801         }
2802 }
2803
2804 static void
2805 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2806                           __rte_unused uint16_t queue,
2807                           __rte_unused int on)
2808 {
2809         PMD_INIT_FUNC_TRACE();
2810 }
2811
2812 static int
2813 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2814 {
2815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2816         struct i40e_vsi *vsi = pf->main_vsi;
2817         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2818         struct i40e_vsi_vlan_pvid_info info;
2819
2820         memset(&info, 0, sizeof(info));
2821         info.on = on;
2822         if (info.on)
2823                 info.config.pvid = pvid;
2824         else {
2825                 info.config.reject.tagged =
2826                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2827                 info.config.reject.untagged =
2828                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2829         }
2830
2831         return i40e_vsi_vlan_pvid_set(vsi, &info);
2832 }
2833
2834 static int
2835 i40e_dev_led_on(struct rte_eth_dev *dev)
2836 {
2837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         uint32_t mode = i40e_led_get(hw);
2839
2840         if (mode == 0)
2841                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2842
2843         return 0;
2844 }
2845
2846 static int
2847 i40e_dev_led_off(struct rte_eth_dev *dev)
2848 {
2849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850         uint32_t mode = i40e_led_get(hw);
2851
2852         if (mode != 0)
2853                 i40e_led_set(hw, 0, false);
2854
2855         return 0;
2856 }
2857
2858 static int
2859 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2860 {
2861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863
2864         fc_conf->pause_time = pf->fc_conf.pause_time;
2865         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2866         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2867
2868          /* Return current mode according to actual setting*/
2869         switch (hw->fc.current_mode) {
2870         case I40E_FC_FULL:
2871                 fc_conf->mode = RTE_FC_FULL;
2872                 break;
2873         case I40E_FC_TX_PAUSE:
2874                 fc_conf->mode = RTE_FC_TX_PAUSE;
2875                 break;
2876         case I40E_FC_RX_PAUSE:
2877                 fc_conf->mode = RTE_FC_RX_PAUSE;
2878                 break;
2879         case I40E_FC_NONE:
2880         default:
2881                 fc_conf->mode = RTE_FC_NONE;
2882         };
2883
2884         return 0;
2885 }
2886
2887 static int
2888 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2889 {
2890         uint32_t mflcn_reg, fctrl_reg, reg;
2891         uint32_t max_high_water;
2892         uint8_t i, aq_failure;
2893         int err;
2894         struct i40e_hw *hw;
2895         struct i40e_pf *pf;
2896         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2897                 [RTE_FC_NONE] = I40E_FC_NONE,
2898                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2899                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2900                 [RTE_FC_FULL] = I40E_FC_FULL
2901         };
2902
2903         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2904
2905         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2906         if ((fc_conf->high_water > max_high_water) ||
2907                         (fc_conf->high_water < fc_conf->low_water)) {
2908                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2909                         "High_water must <= %d.", max_high_water);
2910                 return -EINVAL;
2911         }
2912
2913         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2916
2917         pf->fc_conf.pause_time = fc_conf->pause_time;
2918         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2919         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2920
2921         PMD_INIT_FUNC_TRACE();
2922
2923         /* All the link flow control related enable/disable register
2924          * configuration is handle by the F/W
2925          */
2926         err = i40e_set_fc(hw, &aq_failure, true);
2927         if (err < 0)
2928                 return -ENOSYS;
2929
2930         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2931                 /* Configure flow control refresh threshold,
2932                  * the value for stat_tx_pause_refresh_timer[8]
2933                  * is used for global pause operation.
2934                  */
2935
2936                 I40E_WRITE_REG(hw,
2937                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2938                                pf->fc_conf.pause_time);
2939
2940                 /* configure the timer value included in transmitted pause
2941                  * frame,
2942                  * the value for stat_tx_pause_quanta[8] is used for global
2943                  * pause operation
2944                  */
2945                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2946                                pf->fc_conf.pause_time);
2947
2948                 fctrl_reg = I40E_READ_REG(hw,
2949                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2950
2951                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2952                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2953                 else
2954                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2955
2956                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2957                                fctrl_reg);
2958         } else {
2959                 /* Configure pause time (2 TCs per register) */
2960                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2961                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2962                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2963
2964                 /* Configure flow control refresh threshold value */
2965                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2966                                pf->fc_conf.pause_time / 2);
2967
2968                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2969
2970                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2971                  *depending on configuration
2972                  */
2973                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2974                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2975                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2976                 } else {
2977                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2978                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2979                 }
2980
2981                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2982         }
2983
2984         /* config the water marker both based on the packets and bytes */
2985         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2986                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2987                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2988         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2989                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2990                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2991         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2992                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2993                        << I40E_KILOSHIFT);
2994         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2995                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2996                        << I40E_KILOSHIFT);
2997
2998         I40E_WRITE_FLUSH(hw);
2999
3000         return 0;
3001 }
3002
3003 static int
3004 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3005                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3006 {
3007         PMD_INIT_FUNC_TRACE();
3008
3009         return -ENOSYS;
3010 }
3011
3012 /* Add a MAC address, and update filters */
3013 static void
3014 i40e_macaddr_add(struct rte_eth_dev *dev,
3015                  struct ether_addr *mac_addr,
3016                  __rte_unused uint32_t index,
3017                  uint32_t pool)
3018 {
3019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3020         struct i40e_mac_filter_info mac_filter;
3021         struct i40e_vsi *vsi;
3022         int ret;
3023
3024         /* If VMDQ not enabled or configured, return */
3025         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3026                           !pf->nb_cfg_vmdq_vsi)) {
3027                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3028                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3029                         pool);
3030                 return;
3031         }
3032
3033         if (pool > pf->nb_cfg_vmdq_vsi) {
3034                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3035                                 pool, pf->nb_cfg_vmdq_vsi);
3036                 return;
3037         }
3038
3039         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3040         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3041                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3042         else
3043                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3044
3045         if (pool == 0)
3046                 vsi = pf->main_vsi;
3047         else
3048                 vsi = pf->vmdq[pool - 1].vsi;
3049
3050         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3051         if (ret != I40E_SUCCESS) {
3052                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3053                 return;
3054         }
3055 }
3056
3057 /* Remove a MAC address, and update filters */
3058 static void
3059 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3060 {
3061         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3062         struct i40e_vsi *vsi;
3063         struct rte_eth_dev_data *data = dev->data;
3064         struct ether_addr *macaddr;
3065         int ret;
3066         uint32_t i;
3067         uint64_t pool_sel;
3068
3069         macaddr = &(data->mac_addrs[index]);
3070
3071         pool_sel = dev->data->mac_pool_sel[index];
3072
3073         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3074                 if (pool_sel & (1ULL << i)) {
3075                         if (i == 0)
3076                                 vsi = pf->main_vsi;
3077                         else {
3078                                 /* No VMDQ pool enabled or configured */
3079                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3080                                         (i > pf->nb_cfg_vmdq_vsi)) {
3081                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3082                                                         "/configured");
3083                                         return;
3084                                 }
3085                                 vsi = pf->vmdq[i - 1].vsi;
3086                         }
3087                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3088
3089                         if (ret) {
3090                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3091                                 return;
3092                         }
3093                 }
3094         }
3095 }
3096
3097 /* Set perfect match or hash match of MAC and VLAN for a VF */
3098 static int
3099 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3100                  struct rte_eth_mac_filter *filter,
3101                  bool add)
3102 {
3103         struct i40e_hw *hw;
3104         struct i40e_mac_filter_info mac_filter;
3105         struct ether_addr old_mac;
3106         struct ether_addr *new_mac;
3107         struct i40e_pf_vf *vf = NULL;
3108         uint16_t vf_id;
3109         int ret;
3110
3111         if (pf == NULL) {
3112                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3113                 return -EINVAL;
3114         }
3115         hw = I40E_PF_TO_HW(pf);
3116
3117         if (filter == NULL) {
3118                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3119                 return -EINVAL;
3120         }
3121
3122         new_mac = &filter->mac_addr;
3123
3124         if (is_zero_ether_addr(new_mac)) {
3125                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3126                 return -EINVAL;
3127         }
3128
3129         vf_id = filter->dst_id;
3130
3131         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3132                 PMD_DRV_LOG(ERR, "Invalid argument.");
3133                 return -EINVAL;
3134         }
3135         vf = &pf->vfs[vf_id];
3136
3137         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3138                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3139                 return -EINVAL;
3140         }
3141
3142         if (add) {
3143                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3144                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3145                                 ETHER_ADDR_LEN);
3146                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3147                                  ETHER_ADDR_LEN);
3148
3149                 mac_filter.filter_type = filter->filter_type;
3150                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3151                 if (ret != I40E_SUCCESS) {
3152                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3153                         return -1;
3154                 }
3155                 ether_addr_copy(new_mac, &pf->dev_addr);
3156         } else {
3157                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3158                                 ETHER_ADDR_LEN);
3159                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3160                 if (ret != I40E_SUCCESS) {
3161                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3162                         return -1;
3163                 }
3164
3165                 /* Clear device address as it has been removed */
3166                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3167                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3168         }
3169
3170         return 0;
3171 }
3172
3173 /* MAC filter handle */
3174 static int
3175 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3176                 void *arg)
3177 {
3178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3179         struct rte_eth_mac_filter *filter;
3180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3181         int ret = I40E_NOT_SUPPORTED;
3182
3183         filter = (struct rte_eth_mac_filter *)(arg);
3184
3185         switch (filter_op) {
3186         case RTE_ETH_FILTER_NOP:
3187                 ret = I40E_SUCCESS;
3188                 break;
3189         case RTE_ETH_FILTER_ADD:
3190                 i40e_pf_disable_irq0(hw);
3191                 if (filter->is_vf)
3192                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3193                 i40e_pf_enable_irq0(hw);
3194                 break;
3195         case RTE_ETH_FILTER_DELETE:
3196                 i40e_pf_disable_irq0(hw);
3197                 if (filter->is_vf)
3198                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3199                 i40e_pf_enable_irq0(hw);
3200                 break;
3201         default:
3202                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3203                 ret = I40E_ERR_PARAM;
3204                 break;
3205         }
3206
3207         return ret;
3208 }
3209
3210 static int
3211 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3212 {
3213         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3214         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3215         int ret;
3216
3217         if (!lut)
3218                 return -EINVAL;
3219
3220         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3221                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3222                                           lut, lut_size);
3223                 if (ret) {
3224                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3225                         return ret;
3226                 }
3227         } else {
3228                 uint32_t *lut_dw = (uint32_t *)lut;
3229                 uint16_t i, lut_size_dw = lut_size / 4;
3230
3231                 for (i = 0; i < lut_size_dw; i++)
3232                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3233         }
3234
3235         return 0;
3236 }
3237
3238 static int
3239 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3240 {
3241         struct i40e_pf *pf;
3242         struct i40e_hw *hw;
3243         int ret;
3244
3245         if (!vsi || !lut)
3246                 return -EINVAL;
3247
3248         pf = I40E_VSI_TO_PF(vsi);
3249         hw = I40E_VSI_TO_HW(vsi);
3250
3251         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3252                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3253                                           lut, lut_size);
3254                 if (ret) {
3255                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3256                         return ret;
3257                 }
3258         } else {
3259                 uint32_t *lut_dw = (uint32_t *)lut;
3260                 uint16_t i, lut_size_dw = lut_size / 4;
3261
3262                 for (i = 0; i < lut_size_dw; i++)
3263                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3264                 I40E_WRITE_FLUSH(hw);
3265         }
3266
3267         return 0;
3268 }
3269
3270 static int
3271 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3272                          struct rte_eth_rss_reta_entry64 *reta_conf,
3273                          uint16_t reta_size)
3274 {
3275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3276         uint16_t i, lut_size = pf->hash_lut_size;
3277         uint16_t idx, shift;
3278         uint8_t *lut;
3279         int ret;
3280
3281         if (reta_size != lut_size ||
3282                 reta_size > ETH_RSS_RETA_SIZE_512) {
3283                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3284                         "(%d) doesn't match the number hardware can supported "
3285                                         "(%d)\n", reta_size, lut_size);
3286                 return -EINVAL;
3287         }
3288
3289         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3290         if (!lut) {
3291                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3292                 return -ENOMEM;
3293         }
3294         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3295         if (ret)
3296                 goto out;
3297         for (i = 0; i < reta_size; i++) {
3298                 idx = i / RTE_RETA_GROUP_SIZE;
3299                 shift = i % RTE_RETA_GROUP_SIZE;
3300                 if (reta_conf[idx].mask & (1ULL << shift))
3301                         lut[i] = reta_conf[idx].reta[shift];
3302         }
3303         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3304
3305 out:
3306         rte_free(lut);
3307
3308         return ret;
3309 }
3310
3311 static int
3312 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3313                         struct rte_eth_rss_reta_entry64 *reta_conf,
3314                         uint16_t reta_size)
3315 {
3316         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3317         uint16_t i, lut_size = pf->hash_lut_size;
3318         uint16_t idx, shift;
3319         uint8_t *lut;
3320         int ret;
3321
3322         if (reta_size != lut_size ||
3323                 reta_size > ETH_RSS_RETA_SIZE_512) {
3324                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3325                         "(%d) doesn't match the number hardware can supported "
3326                                         "(%d)\n", reta_size, lut_size);
3327                 return -EINVAL;
3328         }
3329
3330         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3331         if (!lut) {
3332                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3333                 return -ENOMEM;
3334         }
3335
3336         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3337         if (ret)
3338                 goto out;
3339         for (i = 0; i < reta_size; i++) {
3340                 idx = i / RTE_RETA_GROUP_SIZE;
3341                 shift = i % RTE_RETA_GROUP_SIZE;
3342                 if (reta_conf[idx].mask & (1ULL << shift))
3343                         reta_conf[idx].reta[shift] = lut[i];
3344         }
3345
3346 out:
3347         rte_free(lut);
3348
3349         return ret;
3350 }
3351
3352 /**
3353  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3354  * @hw:   pointer to the HW structure
3355  * @mem:  pointer to mem struct to fill out
3356  * @size: size of memory requested
3357  * @alignment: what to align the allocation to
3358  **/
3359 enum i40e_status_code
3360 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3361                         struct i40e_dma_mem *mem,
3362                         u64 size,
3363                         u32 alignment)
3364 {
3365         const struct rte_memzone *mz = NULL;
3366         char z_name[RTE_MEMZONE_NAMESIZE];
3367
3368         if (!mem)
3369                 return I40E_ERR_PARAM;
3370
3371         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3372         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3373                                          alignment, RTE_PGSIZE_2M);
3374         if (!mz)
3375                 return I40E_ERR_NO_MEMORY;
3376
3377         mem->size = size;
3378         mem->va = mz->addr;
3379         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3380         mem->zone = (const void *)mz;
3381         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3382                     "%"PRIu64, mz->name, mem->pa);
3383
3384         return I40E_SUCCESS;
3385 }
3386
3387 /**
3388  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3389  * @hw:   pointer to the HW structure
3390  * @mem:  ptr to mem struct to free
3391  **/
3392 enum i40e_status_code
3393 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3394                     struct i40e_dma_mem *mem)
3395 {
3396         if (!mem)
3397                 return I40E_ERR_PARAM;
3398
3399         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3400                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3401                     mem->pa);
3402         rte_memzone_free((const struct rte_memzone *)mem->zone);
3403         mem->zone = NULL;
3404         mem->va = NULL;
3405         mem->pa = (u64)0;
3406
3407         return I40E_SUCCESS;
3408 }
3409
3410 /**
3411  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3412  * @hw:   pointer to the HW structure
3413  * @mem:  pointer to mem struct to fill out
3414  * @size: size of memory requested
3415  **/
3416 enum i40e_status_code
3417 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3418                          struct i40e_virt_mem *mem,
3419                          u32 size)
3420 {
3421         if (!mem)
3422                 return I40E_ERR_PARAM;
3423
3424         mem->size = size;
3425         mem->va = rte_zmalloc("i40e", size, 0);
3426
3427         if (mem->va)
3428                 return I40E_SUCCESS;
3429         else
3430                 return I40E_ERR_NO_MEMORY;
3431 }
3432
3433 /**
3434  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3435  * @hw:   pointer to the HW structure
3436  * @mem:  pointer to mem struct to free
3437  **/
3438 enum i40e_status_code
3439 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3440                      struct i40e_virt_mem *mem)
3441 {
3442         if (!mem)
3443                 return I40E_ERR_PARAM;
3444
3445         rte_free(mem->va);
3446         mem->va = NULL;
3447
3448         return I40E_SUCCESS;
3449 }
3450
3451 void
3452 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3453 {
3454         rte_spinlock_init(&sp->spinlock);
3455 }
3456
3457 void
3458 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3459 {
3460         rte_spinlock_lock(&sp->spinlock);
3461 }
3462
3463 void
3464 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3465 {
3466         rte_spinlock_unlock(&sp->spinlock);
3467 }
3468
3469 void
3470 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3471 {
3472         return;
3473 }
3474
3475 /**
3476  * Get the hardware capabilities, which will be parsed
3477  * and saved into struct i40e_hw.
3478  */
3479 static int
3480 i40e_get_cap(struct i40e_hw *hw)
3481 {
3482         struct i40e_aqc_list_capabilities_element_resp *buf;
3483         uint16_t len, size = 0;
3484         int ret;
3485
3486         /* Calculate a huge enough buff for saving response data temporarily */
3487         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3488                                                 I40E_MAX_CAP_ELE_NUM;
3489         buf = rte_zmalloc("i40e", len, 0);
3490         if (!buf) {
3491                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3492                 return I40E_ERR_NO_MEMORY;
3493         }
3494
3495         /* Get, parse the capabilities and save it to hw */
3496         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3497                         i40e_aqc_opc_list_func_capabilities, NULL);
3498         if (ret != I40E_SUCCESS)
3499                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3500
3501         /* Free the temporary buffer after being used */
3502         rte_free(buf);
3503
3504         return ret;
3505 }
3506
3507 static int
3508 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3509 {
3510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3511         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3512         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3513         uint16_t qp_count = 0, vsi_count = 0;
3514
3515         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3516                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3517                 return -EINVAL;
3518         }
3519         /* Add the parameter init for LFC */
3520         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3521         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3522         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3523
3524         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3525         pf->max_num_vsi = hw->func_caps.num_vsis;
3526         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3527         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3528         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3529
3530         /* FDir queue/VSI allocation */
3531         pf->fdir_qp_offset = 0;
3532         if (hw->func_caps.fd) {
3533                 pf->flags |= I40E_FLAG_FDIR;
3534                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3535         } else {
3536                 pf->fdir_nb_qps = 0;
3537         }
3538         qp_count += pf->fdir_nb_qps;
3539         vsi_count += 1;
3540
3541         /* LAN queue/VSI allocation */
3542         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3543         if (!hw->func_caps.rss) {
3544                 pf->lan_nb_qps = 1;
3545         } else {
3546                 pf->flags |= I40E_FLAG_RSS;
3547                 if (hw->mac.type == I40E_MAC_X722)
3548                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3549                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3550         }
3551         qp_count += pf->lan_nb_qps;
3552         vsi_count += 1;
3553
3554         /* VF queue/VSI allocation */
3555         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3556         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3557                 pf->flags |= I40E_FLAG_SRIOV;
3558                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3559                 pf->vf_num = pci_dev->max_vfs;
3560                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3561                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3562                             pf->vf_nb_qps * pf->vf_num);
3563         } else {
3564                 pf->vf_nb_qps = 0;
3565                 pf->vf_num = 0;
3566         }
3567         qp_count += pf->vf_nb_qps * pf->vf_num;
3568         vsi_count += pf->vf_num;
3569
3570         /* VMDq queue/VSI allocation */
3571         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3572         pf->vmdq_nb_qps = 0;
3573         pf->max_nb_vmdq_vsi = 0;
3574         if (hw->func_caps.vmdq) {
3575                 if (qp_count < hw->func_caps.num_tx_qp &&
3576                         vsi_count < hw->func_caps.num_vsis) {
3577                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3578                                 qp_count) / pf->vmdq_nb_qp_max;
3579
3580                         /* Limit the maximum number of VMDq vsi to the maximum
3581                          * ethdev can support
3582                          */
3583                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3584                                 hw->func_caps.num_vsis - vsi_count);
3585                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3586                                 ETH_64_POOLS);
3587                         if (pf->max_nb_vmdq_vsi) {
3588                                 pf->flags |= I40E_FLAG_VMDQ;
3589                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3590                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3591                                             "per VMDQ VSI, in total %u queues",
3592                                             pf->max_nb_vmdq_vsi,
3593                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3594                                             pf->max_nb_vmdq_vsi);
3595                         } else {
3596                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3597                                             "VMDq");
3598                         }
3599                 } else {
3600                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3601                 }
3602         }
3603         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3604         vsi_count += pf->max_nb_vmdq_vsi;
3605
3606         if (hw->func_caps.dcb)
3607                 pf->flags |= I40E_FLAG_DCB;
3608
3609         if (qp_count > hw->func_caps.num_tx_qp) {
3610                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3611                             "the hardware maximum %u", qp_count,
3612                             hw->func_caps.num_tx_qp);
3613                 return -EINVAL;
3614         }
3615         if (vsi_count > hw->func_caps.num_vsis) {
3616                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3617                             "the hardware maximum %u", vsi_count,
3618                             hw->func_caps.num_vsis);
3619                 return -EINVAL;
3620         }
3621
3622         return 0;
3623 }
3624
3625 static int
3626 i40e_pf_get_switch_config(struct i40e_pf *pf)
3627 {
3628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3629         struct i40e_aqc_get_switch_config_resp *switch_config;
3630         struct i40e_aqc_switch_config_element_resp *element;
3631         uint16_t start_seid = 0, num_reported;
3632         int ret;
3633
3634         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3635                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3636         if (!switch_config) {
3637                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3638                 return -ENOMEM;
3639         }
3640
3641         /* Get the switch configurations */
3642         ret = i40e_aq_get_switch_config(hw, switch_config,
3643                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3644         if (ret != I40E_SUCCESS) {
3645                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3646                 goto fail;
3647         }
3648         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3649         if (num_reported != 1) { /* The number should be 1 */
3650                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3651                 goto fail;
3652         }
3653
3654         /* Parse the switch configuration elements */
3655         element = &(switch_config->element[0]);
3656         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3657                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3658                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3659         } else
3660                 PMD_DRV_LOG(INFO, "Unknown element type");
3661
3662 fail:
3663         rte_free(switch_config);
3664
3665         return ret;
3666 }
3667
3668 static int
3669 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3670                         uint32_t num)
3671 {
3672         struct pool_entry *entry;
3673
3674         if (pool == NULL || num == 0)
3675                 return -EINVAL;
3676
3677         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3678         if (entry == NULL) {
3679                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3680                 return -ENOMEM;
3681         }
3682
3683         /* queue heap initialize */
3684         pool->num_free = num;
3685         pool->num_alloc = 0;
3686         pool->base = base;
3687         LIST_INIT(&pool->alloc_list);
3688         LIST_INIT(&pool->free_list);
3689
3690         /* Initialize element  */
3691         entry->base = 0;
3692         entry->len = num;
3693
3694         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3695         return 0;
3696 }
3697
3698 static void
3699 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3700 {
3701         struct pool_entry *entry, *next_entry;
3702
3703         if (pool == NULL)
3704                 return;
3705
3706         for (entry = LIST_FIRST(&pool->alloc_list);
3707                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3708                         entry = next_entry) {
3709                 LIST_REMOVE(entry, next);
3710                 rte_free(entry);
3711         }
3712
3713         for (entry = LIST_FIRST(&pool->free_list);
3714                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3715                         entry = next_entry) {
3716                 LIST_REMOVE(entry, next);
3717                 rte_free(entry);
3718         }
3719
3720         pool->num_free = 0;
3721         pool->num_alloc = 0;
3722         pool->base = 0;
3723         LIST_INIT(&pool->alloc_list);
3724         LIST_INIT(&pool->free_list);
3725 }
3726
3727 static int
3728 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3729                        uint32_t base)
3730 {
3731         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3732         uint32_t pool_offset;
3733         int insert;
3734
3735         if (pool == NULL) {
3736                 PMD_DRV_LOG(ERR, "Invalid parameter");
3737                 return -EINVAL;
3738         }
3739
3740         pool_offset = base - pool->base;
3741         /* Lookup in alloc list */
3742         LIST_FOREACH(entry, &pool->alloc_list, next) {
3743                 if (entry->base == pool_offset) {
3744                         valid_entry = entry;
3745                         LIST_REMOVE(entry, next);
3746                         break;
3747                 }
3748         }
3749
3750         /* Not find, return */
3751         if (valid_entry == NULL) {
3752                 PMD_DRV_LOG(ERR, "Failed to find entry");
3753                 return -EINVAL;
3754         }
3755
3756         /**
3757          * Found it, move it to free list  and try to merge.
3758          * In order to make merge easier, always sort it by qbase.
3759          * Find adjacent prev and last entries.
3760          */
3761         prev = next = NULL;
3762         LIST_FOREACH(entry, &pool->free_list, next) {
3763                 if (entry->base > valid_entry->base) {
3764                         next = entry;
3765                         break;
3766                 }
3767                 prev = entry;
3768         }
3769
3770         insert = 0;
3771         /* Try to merge with next one*/
3772         if (next != NULL) {
3773                 /* Merge with next one */
3774                 if (valid_entry->base + valid_entry->len == next->base) {
3775                         next->base = valid_entry->base;
3776                         next->len += valid_entry->len;
3777                         rte_free(valid_entry);
3778                         valid_entry = next;
3779                         insert = 1;
3780                 }
3781         }
3782
3783         if (prev != NULL) {
3784                 /* Merge with previous one */
3785                 if (prev->base + prev->len == valid_entry->base) {
3786                         prev->len += valid_entry->len;
3787                         /* If it merge with next one, remove next node */
3788                         if (insert == 1) {
3789                                 LIST_REMOVE(valid_entry, next);
3790                                 rte_free(valid_entry);
3791                         } else {
3792                                 rte_free(valid_entry);
3793                                 insert = 1;
3794                         }
3795                 }
3796         }
3797
3798         /* Not find any entry to merge, insert */
3799         if (insert == 0) {
3800                 if (prev != NULL)
3801                         LIST_INSERT_AFTER(prev, valid_entry, next);
3802                 else if (next != NULL)
3803                         LIST_INSERT_BEFORE(next, valid_entry, next);
3804                 else /* It's empty list, insert to head */
3805                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3806         }
3807
3808         pool->num_free += valid_entry->len;
3809         pool->num_alloc -= valid_entry->len;
3810
3811         return 0;
3812 }
3813
3814 static int
3815 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3816                        uint16_t num)
3817 {
3818         struct pool_entry *entry, *valid_entry;
3819
3820         if (pool == NULL || num == 0) {
3821                 PMD_DRV_LOG(ERR, "Invalid parameter");
3822                 return -EINVAL;
3823         }
3824
3825         if (pool->num_free < num) {
3826                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3827                             num, pool->num_free);
3828                 return -ENOMEM;
3829         }
3830
3831         valid_entry = NULL;
3832         /* Lookup  in free list and find most fit one */
3833         LIST_FOREACH(entry, &pool->free_list, next) {
3834                 if (entry->len >= num) {
3835                         /* Find best one */
3836                         if (entry->len == num) {
3837                                 valid_entry = entry;
3838                                 break;
3839                         }
3840                         if (valid_entry == NULL || valid_entry->len > entry->len)
3841                                 valid_entry = entry;
3842                 }
3843         }
3844
3845         /* Not find one to satisfy the request, return */
3846         if (valid_entry == NULL) {
3847                 PMD_DRV_LOG(ERR, "No valid entry found");
3848                 return -ENOMEM;
3849         }
3850         /**
3851          * The entry have equal queue number as requested,
3852          * remove it from alloc_list.
3853          */
3854         if (valid_entry->len == num) {
3855                 LIST_REMOVE(valid_entry, next);
3856         } else {
3857                 /**
3858                  * The entry have more numbers than requested,
3859                  * create a new entry for alloc_list and minus its
3860                  * queue base and number in free_list.
3861                  */
3862                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3863                 if (entry == NULL) {
3864                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3865                                     "resource pool");
3866                         return -ENOMEM;
3867                 }
3868                 entry->base = valid_entry->base;
3869                 entry->len = num;
3870                 valid_entry->base += num;
3871                 valid_entry->len -= num;
3872                 valid_entry = entry;
3873         }
3874
3875         /* Insert it into alloc list, not sorted */
3876         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3877
3878         pool->num_free -= valid_entry->len;
3879         pool->num_alloc += valid_entry->len;
3880
3881         return valid_entry->base + pool->base;
3882 }
3883
3884 /**
3885  * bitmap_is_subset - Check whether src2 is subset of src1
3886  **/
3887 static inline int
3888 bitmap_is_subset(uint8_t src1, uint8_t src2)
3889 {
3890         return !((src1 ^ src2) & src2);
3891 }
3892
3893 static enum i40e_status_code
3894 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3895 {
3896         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3897
3898         /* If DCB is not supported, only default TC is supported */
3899         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3900                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3901                 return I40E_NOT_SUPPORTED;
3902         }
3903
3904         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3905                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3906                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3907                             enabled_tcmap);
3908                 return I40E_NOT_SUPPORTED;
3909         }
3910         return I40E_SUCCESS;
3911 }
3912
3913 int
3914 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3915                                 struct i40e_vsi_vlan_pvid_info *info)
3916 {
3917         struct i40e_hw *hw;
3918         struct i40e_vsi_context ctxt;
3919         uint8_t vlan_flags = 0;
3920         int ret;
3921
3922         if (vsi == NULL || info == NULL) {
3923                 PMD_DRV_LOG(ERR, "invalid parameters");
3924                 return I40E_ERR_PARAM;
3925         }
3926
3927         if (info->on) {
3928                 vsi->info.pvid = info->config.pvid;
3929                 /**
3930                  * If insert pvid is enabled, only tagged pkts are
3931                  * allowed to be sent out.
3932                  */
3933                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3934                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3935         } else {
3936                 vsi->info.pvid = 0;
3937                 if (info->config.reject.tagged == 0)
3938                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3939
3940                 if (info->config.reject.untagged == 0)
3941                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3942         }
3943         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3944                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3945         vsi->info.port_vlan_flags |= vlan_flags;
3946         vsi->info.valid_sections =
3947                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3948         memset(&ctxt, 0, sizeof(ctxt));
3949         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3950         ctxt.seid = vsi->seid;
3951
3952         hw = I40E_VSI_TO_HW(vsi);
3953         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3954         if (ret != I40E_SUCCESS)
3955                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3956
3957         return ret;
3958 }
3959
3960 static int
3961 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3962 {
3963         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3964         int i, ret;
3965         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3966
3967         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3968         if (ret != I40E_SUCCESS)
3969                 return ret;
3970
3971         if (!vsi->seid) {
3972                 PMD_DRV_LOG(ERR, "seid not valid");
3973                 return -EINVAL;
3974         }
3975
3976         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3977         tc_bw_data.tc_valid_bits = enabled_tcmap;
3978         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3979                 tc_bw_data.tc_bw_credits[i] =
3980                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3981
3982         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3983         if (ret != I40E_SUCCESS) {
3984                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3985                 return ret;
3986         }
3987
3988         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3989                                         sizeof(vsi->info.qs_handle));
3990         return I40E_SUCCESS;
3991 }
3992
3993 static enum i40e_status_code
3994 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3995                                  struct i40e_aqc_vsi_properties_data *info,
3996                                  uint8_t enabled_tcmap)
3997 {
3998         enum i40e_status_code ret;
3999         int i, total_tc = 0;
4000         uint16_t qpnum_per_tc, bsf, qp_idx;
4001
4002         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4003         if (ret != I40E_SUCCESS)
4004                 return ret;
4005
4006         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4007                 if (enabled_tcmap & (1 << i))
4008                         total_tc++;
4009         vsi->enabled_tc = enabled_tcmap;
4010
4011         /* Number of queues per enabled TC */
4012         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4013         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4014         bsf = rte_bsf32(qpnum_per_tc);
4015
4016         /* Adjust the queue number to actual queues that can be applied */
4017         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4018                 vsi->nb_qps = qpnum_per_tc * total_tc;
4019
4020         /**
4021          * Configure TC and queue mapping parameters, for enabled TC,
4022          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4023          * default queue will serve it.
4024          */
4025         qp_idx = 0;
4026         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4027                 if (vsi->enabled_tc & (1 << i)) {
4028                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4029                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4030                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4031                         qp_idx += qpnum_per_tc;
4032                 } else
4033                         info->tc_mapping[i] = 0;
4034         }
4035
4036         /* Associate queue number with VSI */
4037         if (vsi->type == I40E_VSI_SRIOV) {
4038                 info->mapping_flags |=
4039                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4040                 for (i = 0; i < vsi->nb_qps; i++)
4041                         info->queue_mapping[i] =
4042                                 rte_cpu_to_le_16(vsi->base_queue + i);
4043         } else {
4044                 info->mapping_flags |=
4045                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4046                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4047         }
4048         info->valid_sections |=
4049                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4050
4051         return I40E_SUCCESS;
4052 }
4053
4054 static int
4055 i40e_veb_release(struct i40e_veb *veb)
4056 {
4057         struct i40e_vsi *vsi;
4058         struct i40e_hw *hw;
4059
4060         if (veb == NULL)
4061                 return -EINVAL;
4062
4063         if (!TAILQ_EMPTY(&veb->head)) {
4064                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4065                 return -EACCES;
4066         }
4067         /* associate_vsi field is NULL for floating VEB */
4068         if (veb->associate_vsi != NULL) {
4069                 vsi = veb->associate_vsi;
4070                 hw = I40E_VSI_TO_HW(vsi);
4071
4072                 vsi->uplink_seid = veb->uplink_seid;
4073                 vsi->veb = NULL;
4074         } else {
4075                 veb->associate_pf->main_vsi->floating_veb = NULL;
4076                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4077         }
4078
4079         i40e_aq_delete_element(hw, veb->seid, NULL);
4080         rte_free(veb);
4081         return I40E_SUCCESS;
4082 }
4083
4084 /* Setup a veb */
4085 static struct i40e_veb *
4086 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4087 {
4088         struct i40e_veb *veb;
4089         int ret;
4090         struct i40e_hw *hw;
4091
4092         if (pf == NULL) {
4093                 PMD_DRV_LOG(ERR,
4094                             "veb setup failed, associated PF shouldn't null");
4095                 return NULL;
4096         }
4097         hw = I40E_PF_TO_HW(pf);
4098
4099         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4100         if (!veb) {
4101                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4102                 goto fail;
4103         }
4104
4105         veb->associate_vsi = vsi;
4106         veb->associate_pf = pf;
4107         TAILQ_INIT(&veb->head);
4108         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4109
4110         /* create floating veb if vsi is NULL */
4111         if (vsi != NULL) {
4112                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4113                                       I40E_DEFAULT_TCMAP, false,
4114                                       &veb->seid, false, NULL);
4115         } else {
4116                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4117                                       true, &veb->seid, false, NULL);
4118         }
4119
4120         if (ret != I40E_SUCCESS) {
4121                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4122                             hw->aq.asq_last_status);
4123                 goto fail;
4124         }
4125
4126         /* get statistics index */
4127         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4128                                 &veb->stats_idx, NULL, NULL, NULL);
4129         if (ret != I40E_SUCCESS) {
4130                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4131                             hw->aq.asq_last_status);
4132                 goto fail;
4133         }
4134         /* Get VEB bandwidth, to be implemented */
4135         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4136         if (vsi)
4137                 vsi->uplink_seid = veb->seid;
4138
4139         return veb;
4140 fail:
4141         rte_free(veb);
4142         return NULL;
4143 }
4144
4145 int
4146 i40e_vsi_release(struct i40e_vsi *vsi)
4147 {
4148         struct i40e_pf *pf;
4149         struct i40e_hw *hw;
4150         struct i40e_vsi_list *vsi_list;
4151         void *temp;
4152         int ret;
4153         struct i40e_mac_filter *f;
4154         uint16_t user_param;
4155
4156         if (!vsi)
4157                 return I40E_SUCCESS;
4158
4159         user_param = vsi->user_param;
4160
4161         pf = I40E_VSI_TO_PF(vsi);
4162         hw = I40E_VSI_TO_HW(vsi);
4163
4164         /* VSI has child to attach, release child first */
4165         if (vsi->veb) {
4166                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4167                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4168                                 return -1;
4169                 }
4170                 i40e_veb_release(vsi->veb);
4171         }
4172
4173         if (vsi->floating_veb) {
4174                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4175                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4176                                 return -1;
4177                 }
4178         }
4179
4180         /* Remove all macvlan filters of the VSI */
4181         i40e_vsi_remove_all_macvlan_filter(vsi);
4182         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4183                 rte_free(f);
4184
4185         if (vsi->type != I40E_VSI_MAIN &&
4186             ((vsi->type != I40E_VSI_SRIOV) ||
4187             !pf->floating_veb_list[user_param])) {
4188                 /* Remove vsi from parent's sibling list */
4189                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4190                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4191                         return I40E_ERR_PARAM;
4192                 }
4193                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4194                                 &vsi->sib_vsi_list, list);
4195
4196                 /* Remove all switch element of the VSI */
4197                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4198                 if (ret != I40E_SUCCESS)
4199                         PMD_DRV_LOG(ERR, "Failed to delete element");
4200         }
4201
4202         if ((vsi->type == I40E_VSI_SRIOV) &&
4203             pf->floating_veb_list[user_param]) {
4204                 /* Remove vsi from parent's sibling list */
4205                 if (vsi->parent_vsi == NULL ||
4206                     vsi->parent_vsi->floating_veb == NULL) {
4207                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4208                         return I40E_ERR_PARAM;
4209                 }
4210                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4211                              &vsi->sib_vsi_list, list);
4212
4213                 /* Remove all switch element of the VSI */
4214                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4215                 if (ret != I40E_SUCCESS)
4216                         PMD_DRV_LOG(ERR, "Failed to delete element");
4217         }
4218
4219         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4220
4221         if (vsi->type != I40E_VSI_SRIOV)
4222                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4223         rte_free(vsi);
4224
4225         return I40E_SUCCESS;
4226 }
4227
4228 static int
4229 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4230 {
4231         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4232         struct i40e_aqc_remove_macvlan_element_data def_filter;
4233         struct i40e_mac_filter_info filter;
4234         int ret;
4235
4236         if (vsi->type != I40E_VSI_MAIN)
4237                 return I40E_ERR_CONFIG;
4238         memset(&def_filter, 0, sizeof(def_filter));
4239         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4240                                         ETH_ADDR_LEN);
4241         def_filter.vlan_tag = 0;
4242         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4243                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4244         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4245         if (ret != I40E_SUCCESS) {
4246                 struct i40e_mac_filter *f;
4247                 struct ether_addr *mac;
4248
4249                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4250                             "macvlan filter");
4251                 /* It needs to add the permanent mac into mac list */
4252                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4253                 if (f == NULL) {
4254                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4255                         return I40E_ERR_NO_MEMORY;
4256                 }
4257                 mac = &f->mac_info.mac_addr;
4258                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4259                                 ETH_ADDR_LEN);
4260                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4261                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4262                 vsi->mac_num++;
4263
4264                 return ret;
4265         }
4266         (void)rte_memcpy(&filter.mac_addr,
4267                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4268         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4269         return i40e_vsi_add_mac(vsi, &filter);
4270 }
4271
4272 /*
4273  * i40e_vsi_get_bw_config - Query VSI BW Information
4274  * @vsi: the VSI to be queried
4275  *
4276  * Returns 0 on success, negative value on failure
4277  */
4278 static enum i40e_status_code
4279 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4280 {
4281         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4282         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4283         struct i40e_hw *hw = &vsi->adapter->hw;
4284         i40e_status ret;
4285         int i;
4286         uint32_t bw_max;
4287
4288         memset(&bw_config, 0, sizeof(bw_config));
4289         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4290         if (ret != I40E_SUCCESS) {
4291                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4292                             hw->aq.asq_last_status);
4293                 return ret;
4294         }
4295
4296         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4297         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4298                                         &ets_sla_config, NULL);
4299         if (ret != I40E_SUCCESS) {
4300                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4301                             "configuration %u", hw->aq.asq_last_status);
4302                 return ret;
4303         }
4304
4305         /* store and print out BW info */
4306         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4307         vsi->bw_info.bw_max = bw_config.max_bw;
4308         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4309         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4310         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4311                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4312                      I40E_16_BIT_WIDTH);
4313         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4314                 vsi->bw_info.bw_ets_share_credits[i] =
4315                                 ets_sla_config.share_credits[i];
4316                 vsi->bw_info.bw_ets_credits[i] =
4317                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4318                 /* 4 bits per TC, 4th bit is reserved */
4319                 vsi->bw_info.bw_ets_max[i] =
4320                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4321                                   RTE_LEN2MASK(3, uint8_t));
4322                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4323                             vsi->bw_info.bw_ets_share_credits[i]);
4324                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4325                             vsi->bw_info.bw_ets_credits[i]);
4326                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4327                             vsi->bw_info.bw_ets_max[i]);
4328         }
4329
4330         return I40E_SUCCESS;
4331 }
4332
4333 /* i40e_enable_pf_lb
4334  * @pf: pointer to the pf structure
4335  *
4336  * allow loopback on pf
4337  */
4338 static inline void
4339 i40e_enable_pf_lb(struct i40e_pf *pf)
4340 {
4341         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4342         struct i40e_vsi_context ctxt;
4343         int ret;
4344
4345         /* Use the FW API if FW >= v5.0 */
4346         if (hw->aq.fw_maj_ver < 5) {
4347                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4348                 return;
4349         }
4350
4351         memset(&ctxt, 0, sizeof(ctxt));
4352         ctxt.seid = pf->main_vsi_seid;
4353         ctxt.pf_num = hw->pf_id;
4354         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4355         if (ret) {
4356                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4357                             ret, hw->aq.asq_last_status);
4358                 return;
4359         }
4360         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4361         ctxt.info.valid_sections =
4362                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4363         ctxt.info.switch_id |=
4364                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4365
4366         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4367         if (ret)
4368                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4369                             hw->aq.asq_last_status);
4370 }
4371
4372 /* Setup a VSI */
4373 struct i40e_vsi *
4374 i40e_vsi_setup(struct i40e_pf *pf,
4375                enum i40e_vsi_type type,
4376                struct i40e_vsi *uplink_vsi,
4377                uint16_t user_param)
4378 {
4379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4380         struct i40e_vsi *vsi;
4381         struct i40e_mac_filter_info filter;
4382         int ret;
4383         struct i40e_vsi_context ctxt;
4384         struct ether_addr broadcast =
4385                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4386
4387         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4388             uplink_vsi == NULL) {
4389                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4390                             "VSI link shouldn't be NULL");
4391                 return NULL;
4392         }
4393
4394         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4395                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4396                             "uplink VSI should be NULL");
4397                 return NULL;
4398         }
4399
4400         /* two situations
4401          * 1.type is not MAIN and uplink vsi is not NULL
4402          * If uplink vsi didn't setup VEB, create one first under veb field
4403          * 2.type is SRIOV and the uplink is NULL
4404          * If floating VEB is NULL, create one veb under floating veb field
4405          */
4406
4407         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4408             uplink_vsi->veb == NULL) {
4409                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4410
4411                 if (uplink_vsi->veb == NULL) {
4412                         PMD_DRV_LOG(ERR, "VEB setup failed");
4413                         return NULL;
4414                 }
4415                 /* set ALLOWLOOPBACk on pf, when veb is created */
4416                 i40e_enable_pf_lb(pf);
4417         }
4418
4419         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4420             pf->main_vsi->floating_veb == NULL) {
4421                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4422
4423                 if (pf->main_vsi->floating_veb == NULL) {
4424                         PMD_DRV_LOG(ERR, "VEB setup failed");
4425                         return NULL;
4426                 }
4427         }
4428
4429         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4430         if (!vsi) {
4431                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4432                 return NULL;
4433         }
4434         TAILQ_INIT(&vsi->mac_list);
4435         vsi->type = type;
4436         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4437         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4438         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4439         vsi->user_param = user_param;
4440         /* Allocate queues */
4441         switch (vsi->type) {
4442         case I40E_VSI_MAIN  :
4443                 vsi->nb_qps = pf->lan_nb_qps;
4444                 break;
4445         case I40E_VSI_SRIOV :
4446                 vsi->nb_qps = pf->vf_nb_qps;
4447                 break;
4448         case I40E_VSI_VMDQ2:
4449                 vsi->nb_qps = pf->vmdq_nb_qps;
4450                 break;
4451         case I40E_VSI_FDIR:
4452                 vsi->nb_qps = pf->fdir_nb_qps;
4453                 break;
4454         default:
4455                 goto fail_mem;
4456         }
4457         /*
4458          * The filter status descriptor is reported in rx queue 0,
4459          * while the tx queue for fdir filter programming has no
4460          * such constraints, can be non-zero queues.
4461          * To simplify it, choose FDIR vsi use queue 0 pair.
4462          * To make sure it will use queue 0 pair, queue allocation
4463          * need be done before this function is called
4464          */
4465         if (type != I40E_VSI_FDIR) {
4466                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4467                         if (ret < 0) {
4468                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4469                                                 vsi->seid, ret);
4470                                 goto fail_mem;
4471                         }
4472                         vsi->base_queue = ret;
4473         } else
4474                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4475
4476         /* VF has MSIX interrupt in VF range, don't allocate here */
4477         if (type == I40E_VSI_MAIN) {
4478                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4479                                           RTE_MIN(vsi->nb_qps,
4480                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4481                 if (ret < 0) {
4482                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4483                                     vsi->seid, ret);
4484                         goto fail_queue_alloc;
4485                 }
4486                 vsi->msix_intr = ret;
4487                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4488         } else if (type != I40E_VSI_SRIOV) {
4489                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4490                 if (ret < 0) {
4491                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4492                         goto fail_queue_alloc;
4493                 }
4494                 vsi->msix_intr = ret;
4495                 vsi->nb_msix = 1;
4496         } else {
4497                 vsi->msix_intr = 0;
4498                 vsi->nb_msix = 0;
4499         }
4500
4501         /* Add VSI */
4502         if (type == I40E_VSI_MAIN) {
4503                 /* For main VSI, no need to add since it's default one */
4504                 vsi->uplink_seid = pf->mac_seid;
4505                 vsi->seid = pf->main_vsi_seid;
4506                 /* Bind queues with specific MSIX interrupt */
4507                 /**
4508                  * Needs 2 interrupt at least, one for misc cause which will
4509                  * enabled from OS side, Another for queues binding the
4510                  * interrupt from device side only.
4511                  */
4512
4513                 /* Get default VSI parameters from hardware */
4514                 memset(&ctxt, 0, sizeof(ctxt));
4515                 ctxt.seid = vsi->seid;
4516                 ctxt.pf_num = hw->pf_id;
4517                 ctxt.uplink_seid = vsi->uplink_seid;
4518                 ctxt.vf_num = 0;
4519                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4520                 if (ret != I40E_SUCCESS) {
4521                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4522                         goto fail_msix_alloc;
4523                 }
4524                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4525                         sizeof(struct i40e_aqc_vsi_properties_data));
4526                 vsi->vsi_id = ctxt.vsi_number;
4527                 vsi->info.valid_sections = 0;
4528
4529                 /* Configure tc, enabled TC0 only */
4530                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4531                         I40E_SUCCESS) {
4532                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4533                         goto fail_msix_alloc;
4534                 }
4535
4536                 /* TC, queue mapping */
4537                 memset(&ctxt, 0, sizeof(ctxt));
4538                 vsi->info.valid_sections |=
4539                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4540                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4541                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4542                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4543                         sizeof(struct i40e_aqc_vsi_properties_data));
4544                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4545                                                 I40E_DEFAULT_TCMAP);
4546                 if (ret != I40E_SUCCESS) {
4547                         PMD_DRV_LOG(ERR, "Failed to configure "
4548                                     "TC queue mapping");
4549                         goto fail_msix_alloc;
4550                 }
4551                 ctxt.seid = vsi->seid;
4552                 ctxt.pf_num = hw->pf_id;
4553                 ctxt.uplink_seid = vsi->uplink_seid;
4554                 ctxt.vf_num = 0;
4555
4556                 /* Update VSI parameters */
4557                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4558                 if (ret != I40E_SUCCESS) {
4559                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4560                         goto fail_msix_alloc;
4561                 }
4562
4563                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4564                                                 sizeof(vsi->info.tc_mapping));
4565                 (void)rte_memcpy(&vsi->info.queue_mapping,
4566                                 &ctxt.info.queue_mapping,
4567                         sizeof(vsi->info.queue_mapping));
4568                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4569                 vsi->info.valid_sections = 0;
4570
4571                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4572                                 ETH_ADDR_LEN);
4573
4574                 /**
4575                  * Updating default filter settings are necessary to prevent
4576                  * reception of tagged packets.
4577                  * Some old firmware configurations load a default macvlan
4578                  * filter which accepts both tagged and untagged packets.
4579                  * The updating is to use a normal filter instead if needed.
4580                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4581                  * The firmware with correct configurations load the default
4582                  * macvlan filter which is expected and cannot be removed.
4583                  */
4584                 i40e_update_default_filter_setting(vsi);
4585                 i40e_config_qinq(hw, vsi);
4586         } else if (type == I40E_VSI_SRIOV) {
4587                 memset(&ctxt, 0, sizeof(ctxt));
4588                 /**
4589                  * For other VSI, the uplink_seid equals to uplink VSI's
4590                  * uplink_seid since they share same VEB
4591                  */
4592                 if (uplink_vsi == NULL)
4593                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4594                 else
4595                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4596                 ctxt.pf_num = hw->pf_id;
4597                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4598                 ctxt.uplink_seid = vsi->uplink_seid;
4599                 ctxt.connection_type = 0x1;
4600                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4601
4602                 /* Use the VEB configuration if FW >= v5.0 */
4603                 if (hw->aq.fw_maj_ver >= 5) {
4604                         /* Configure switch ID */
4605                         ctxt.info.valid_sections |=
4606                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4607                         ctxt.info.switch_id =
4608                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4609                 }
4610
4611                 /* Configure port/vlan */
4612                 ctxt.info.valid_sections |=
4613                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4614                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4615                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4616                                                 I40E_DEFAULT_TCMAP);
4617                 if (ret != I40E_SUCCESS) {
4618                         PMD_DRV_LOG(ERR, "Failed to configure "
4619                                     "TC queue mapping");
4620                         goto fail_msix_alloc;
4621                 }
4622                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4623                 ctxt.info.valid_sections |=
4624                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4625                 /**
4626                  * Since VSI is not created yet, only configure parameter,
4627                  * will add vsi below.
4628                  */
4629
4630                 i40e_config_qinq(hw, vsi);
4631         } else if (type == I40E_VSI_VMDQ2) {
4632                 memset(&ctxt, 0, sizeof(ctxt));
4633                 /*
4634                  * For other VSI, the uplink_seid equals to uplink VSI's
4635                  * uplink_seid since they share same VEB
4636                  */
4637                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4638                 ctxt.pf_num = hw->pf_id;
4639                 ctxt.vf_num = 0;
4640                 ctxt.uplink_seid = vsi->uplink_seid;
4641                 ctxt.connection_type = 0x1;
4642                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4643
4644                 ctxt.info.valid_sections |=
4645                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4646                 /* user_param carries flag to enable loop back */
4647                 if (user_param) {
4648                         ctxt.info.switch_id =
4649                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4650                         ctxt.info.switch_id |=
4651                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4652                 }
4653
4654                 /* Configure port/vlan */
4655                 ctxt.info.valid_sections |=
4656                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4657                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4658                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4659                                                 I40E_DEFAULT_TCMAP);
4660                 if (ret != I40E_SUCCESS) {
4661                         PMD_DRV_LOG(ERR, "Failed to configure "
4662                                         "TC queue mapping");
4663                         goto fail_msix_alloc;
4664                 }
4665                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4666                 ctxt.info.valid_sections |=
4667                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4668         } else if (type == I40E_VSI_FDIR) {
4669                 memset(&ctxt, 0, sizeof(ctxt));
4670                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4671                 ctxt.pf_num = hw->pf_id;
4672                 ctxt.vf_num = 0;
4673                 ctxt.uplink_seid = vsi->uplink_seid;
4674                 ctxt.connection_type = 0x1;     /* regular data port */
4675                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4676                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4677                                                 I40E_DEFAULT_TCMAP);
4678                 if (ret != I40E_SUCCESS) {
4679                         PMD_DRV_LOG(ERR, "Failed to configure "
4680                                         "TC queue mapping.");
4681                         goto fail_msix_alloc;
4682                 }
4683                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4684                 ctxt.info.valid_sections |=
4685                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4686         } else {
4687                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4688                 goto fail_msix_alloc;
4689         }
4690
4691         if (vsi->type != I40E_VSI_MAIN) {
4692                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4693                 if (ret != I40E_SUCCESS) {
4694                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4695                                     hw->aq.asq_last_status);
4696                         goto fail_msix_alloc;
4697                 }
4698                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4699                 vsi->info.valid_sections = 0;
4700                 vsi->seid = ctxt.seid;
4701                 vsi->vsi_id = ctxt.vsi_number;
4702                 vsi->sib_vsi_list.vsi = vsi;
4703                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4704                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4705                                           &vsi->sib_vsi_list, list);
4706                 } else {
4707                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4708                                           &vsi->sib_vsi_list, list);
4709                 }
4710         }
4711
4712         /* MAC/VLAN configuration */
4713         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4714         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4715
4716         ret = i40e_vsi_add_mac(vsi, &filter);
4717         if (ret != I40E_SUCCESS) {
4718                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4719                 goto fail_msix_alloc;
4720         }
4721
4722         /* Get VSI BW information */
4723         i40e_vsi_get_bw_config(vsi);
4724         return vsi;
4725 fail_msix_alloc:
4726         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4727 fail_queue_alloc:
4728         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4729 fail_mem:
4730         rte_free(vsi);
4731         return NULL;
4732 }
4733
4734 /* Configure vlan filter on or off */
4735 int
4736 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4737 {
4738         int i, num;
4739         struct i40e_mac_filter *f;
4740         void *temp;
4741         struct i40e_mac_filter_info *mac_filter;
4742         enum rte_mac_filter_type desired_filter;
4743         int ret = I40E_SUCCESS;
4744
4745         if (on) {
4746                 /* Filter to match MAC and VLAN */
4747                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4748         } else {
4749                 /* Filter to match only MAC */
4750                 desired_filter = RTE_MAC_PERFECT_MATCH;
4751         }
4752
4753         num = vsi->mac_num;
4754
4755         mac_filter = rte_zmalloc("mac_filter_info_data",
4756                                  num * sizeof(*mac_filter), 0);
4757         if (mac_filter == NULL) {
4758                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4759                 return I40E_ERR_NO_MEMORY;
4760         }
4761
4762         i = 0;
4763
4764         /* Remove all existing mac */
4765         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4766                 mac_filter[i] = f->mac_info;
4767                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4768                 if (ret) {
4769                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4770                                     on ? "enable" : "disable");
4771                         goto DONE;
4772                 }
4773                 i++;
4774         }
4775
4776         /* Override with new filter */
4777         for (i = 0; i < num; i++) {
4778                 mac_filter[i].filter_type = desired_filter;
4779                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4780                 if (ret) {
4781                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4782                                     on ? "enable" : "disable");
4783                         goto DONE;
4784                 }
4785         }
4786
4787 DONE:
4788         rte_free(mac_filter);
4789         return ret;
4790 }
4791
4792 /* Configure vlan stripping on or off */
4793 int
4794 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4795 {
4796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4797         struct i40e_vsi_context ctxt;
4798         uint8_t vlan_flags;
4799         int ret = I40E_SUCCESS;
4800
4801         /* Check if it has been already on or off */
4802         if (vsi->info.valid_sections &
4803                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4804                 if (on) {
4805                         if ((vsi->info.port_vlan_flags &
4806                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4807                                 return 0; /* already on */
4808                 } else {
4809                         if ((vsi->info.port_vlan_flags &
4810                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4811                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4812                                 return 0; /* already off */
4813                 }
4814         }
4815
4816         if (on)
4817                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4818         else
4819                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4820         vsi->info.valid_sections =
4821                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4822         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4823         vsi->info.port_vlan_flags |= vlan_flags;
4824         ctxt.seid = vsi->seid;
4825         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4826         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4827         if (ret)
4828                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4829                             on ? "enable" : "disable");
4830
4831         return ret;
4832 }
4833
4834 static int
4835 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4836 {
4837         struct rte_eth_dev_data *data = dev->data;
4838         int ret;
4839         int mask = 0;
4840
4841         /* Apply vlan offload setting */
4842         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4843         i40e_vlan_offload_set(dev, mask);
4844
4845         /* Apply double-vlan setting, not implemented yet */
4846
4847         /* Apply pvid setting */
4848         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4849                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4850         if (ret)
4851                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4852
4853         return ret;
4854 }
4855
4856 static int
4857 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4858 {
4859         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4860
4861         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4862 }
4863
4864 static int
4865 i40e_update_flow_control(struct i40e_hw *hw)
4866 {
4867 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4868         struct i40e_link_status link_status;
4869         uint32_t rxfc = 0, txfc = 0, reg;
4870         uint8_t an_info;
4871         int ret;
4872
4873         memset(&link_status, 0, sizeof(link_status));
4874         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4875         if (ret != I40E_SUCCESS) {
4876                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4877                 goto write_reg; /* Disable flow control */
4878         }
4879
4880         an_info = hw->phy.link_info.an_info;
4881         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4882                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4883                 ret = I40E_ERR_NOT_READY;
4884                 goto write_reg; /* Disable flow control */
4885         }
4886         /**
4887          * If link auto negotiation is enabled, flow control needs to
4888          * be configured according to it
4889          */
4890         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4891         case I40E_LINK_PAUSE_RXTX:
4892                 rxfc = 1;
4893                 txfc = 1;
4894                 hw->fc.current_mode = I40E_FC_FULL;
4895                 break;
4896         case I40E_AQ_LINK_PAUSE_RX:
4897                 rxfc = 1;
4898                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4899                 break;
4900         case I40E_AQ_LINK_PAUSE_TX:
4901                 txfc = 1;
4902                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4903                 break;
4904         default:
4905                 hw->fc.current_mode = I40E_FC_NONE;
4906                 break;
4907         }
4908
4909 write_reg:
4910         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4911                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4912         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4913         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4914         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4915         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4916
4917         return ret;
4918 }
4919
4920 /* PF setup */
4921 static int
4922 i40e_pf_setup(struct i40e_pf *pf)
4923 {
4924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4925         struct i40e_filter_control_settings settings;
4926         struct i40e_vsi *vsi;
4927         int ret;
4928
4929         /* Clear all stats counters */
4930         pf->offset_loaded = FALSE;
4931         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4932         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4933
4934         ret = i40e_pf_get_switch_config(pf);
4935         if (ret != I40E_SUCCESS) {
4936                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4937                 return ret;
4938         }
4939         if (pf->flags & I40E_FLAG_FDIR) {
4940                 /* make queue allocated first, let FDIR use queue pair 0*/
4941                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4942                 if (ret != I40E_FDIR_QUEUE_ID) {
4943                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4944                                     " ret =%d", ret);
4945                         pf->flags &= ~I40E_FLAG_FDIR;
4946                 }
4947         }
4948         /*  main VSI setup */
4949         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4950         if (!vsi) {
4951                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4952                 return I40E_ERR_NOT_READY;
4953         }
4954         pf->main_vsi = vsi;
4955
4956         /* Configure filter control */
4957         memset(&settings, 0, sizeof(settings));
4958         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4959                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4960         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4961                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4962         else {
4963                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4964                                                 hw->func_caps.rss_table_size);
4965                 return I40E_ERR_PARAM;
4966         }
4967         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4968                         "size: %u\n", hw->func_caps.rss_table_size);
4969         pf->hash_lut_size = hw->func_caps.rss_table_size;
4970
4971         /* Enable ethtype and macvlan filters */
4972         settings.enable_ethtype = TRUE;
4973         settings.enable_macvlan = TRUE;
4974         ret = i40e_set_filter_control(hw, &settings);
4975         if (ret)
4976                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4977                                                                 ret);
4978
4979         /* Update flow control according to the auto negotiation */
4980         i40e_update_flow_control(hw);
4981
4982         return I40E_SUCCESS;
4983 }
4984
4985 int
4986 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4987 {
4988         uint32_t reg;
4989         uint16_t j;
4990
4991         /**
4992          * Set or clear TX Queue Disable flags,
4993          * which is required by hardware.
4994          */
4995         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4996         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4997
4998         /* Wait until the request is finished */
4999         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5000                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5001                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5002                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5003                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5004                                                         & 0x1))) {
5005                         break;
5006                 }
5007         }
5008         if (on) {
5009                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5010                         return I40E_SUCCESS; /* already on, skip next steps */
5011
5012                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5013                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5014         } else {
5015                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5016                         return I40E_SUCCESS; /* already off, skip next steps */
5017                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5018         }
5019         /* Write the register */
5020         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5021         /* Check the result */
5022         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5023                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5024                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5025                 if (on) {
5026                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5027                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5028                                 break;
5029                 } else {
5030                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5031                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5032                                 break;
5033                 }
5034         }
5035         /* Check if it is timeout */
5036         if (j >= I40E_CHK_Q_ENA_COUNT) {
5037                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5038                             (on ? "enable" : "disable"), q_idx);
5039                 return I40E_ERR_TIMEOUT;
5040         }
5041
5042         return I40E_SUCCESS;
5043 }
5044
5045 /* Swith on or off the tx queues */
5046 static int
5047 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5048 {
5049         struct rte_eth_dev_data *dev_data = pf->dev_data;
5050         struct i40e_tx_queue *txq;
5051         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5052         uint16_t i;
5053         int ret;
5054
5055         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5056                 txq = dev_data->tx_queues[i];
5057                 /* Don't operate the queue if not configured or
5058                  * if starting only per queue */
5059                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5060                         continue;
5061                 if (on)
5062                         ret = i40e_dev_tx_queue_start(dev, i);
5063                 else
5064                         ret = i40e_dev_tx_queue_stop(dev, i);
5065                 if ( ret != I40E_SUCCESS)
5066                         return ret;
5067         }
5068
5069         return I40E_SUCCESS;
5070 }
5071
5072 int
5073 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5074 {
5075         uint32_t reg;
5076         uint16_t j;
5077
5078         /* Wait until the request is finished */
5079         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5080                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5081                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5082                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5083                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5084                         break;
5085         }
5086
5087         if (on) {
5088                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5089                         return I40E_SUCCESS; /* Already on, skip next steps */
5090                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5091         } else {
5092                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5093                         return I40E_SUCCESS; /* Already off, skip next steps */
5094                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5095         }
5096
5097         /* Write the register */
5098         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5099         /* Check the result */
5100         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5101                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5102                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5103                 if (on) {
5104                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5105                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5106                                 break;
5107                 } else {
5108                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5109                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5110                                 break;
5111                 }
5112         }
5113
5114         /* Check if it is timeout */
5115         if (j >= I40E_CHK_Q_ENA_COUNT) {
5116                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5117                             (on ? "enable" : "disable"), q_idx);
5118                 return I40E_ERR_TIMEOUT;
5119         }
5120
5121         return I40E_SUCCESS;
5122 }
5123 /* Switch on or off the rx queues */
5124 static int
5125 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5126 {
5127         struct rte_eth_dev_data *dev_data = pf->dev_data;
5128         struct i40e_rx_queue *rxq;
5129         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5130         uint16_t i;
5131         int ret;
5132
5133         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5134                 rxq = dev_data->rx_queues[i];
5135                 /* Don't operate the queue if not configured or
5136                  * if starting only per queue */
5137                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5138                         continue;
5139                 if (on)
5140                         ret = i40e_dev_rx_queue_start(dev, i);
5141                 else
5142                         ret = i40e_dev_rx_queue_stop(dev, i);
5143                 if (ret != I40E_SUCCESS)
5144                         return ret;
5145         }
5146
5147         return I40E_SUCCESS;
5148 }
5149
5150 /* Switch on or off all the rx/tx queues */
5151 int
5152 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5153 {
5154         int ret;
5155
5156         if (on) {
5157                 /* enable rx queues before enabling tx queues */
5158                 ret = i40e_dev_switch_rx_queues(pf, on);
5159                 if (ret) {
5160                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5161                         return ret;
5162                 }
5163                 ret = i40e_dev_switch_tx_queues(pf, on);
5164         } else {
5165                 /* Stop tx queues before stopping rx queues */
5166                 ret = i40e_dev_switch_tx_queues(pf, on);
5167                 if (ret) {
5168                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5169                         return ret;
5170                 }
5171                 ret = i40e_dev_switch_rx_queues(pf, on);
5172         }
5173
5174         return ret;
5175 }
5176
5177 /* Initialize VSI for TX */
5178 static int
5179 i40e_dev_tx_init(struct i40e_pf *pf)
5180 {
5181         struct rte_eth_dev_data *data = pf->dev_data;
5182         uint16_t i;
5183         uint32_t ret = I40E_SUCCESS;
5184         struct i40e_tx_queue *txq;
5185
5186         for (i = 0; i < data->nb_tx_queues; i++) {
5187                 txq = data->tx_queues[i];
5188                 if (!txq || !txq->q_set)
5189                         continue;
5190                 ret = i40e_tx_queue_init(txq);
5191                 if (ret != I40E_SUCCESS)
5192                         break;
5193         }
5194         if (ret == I40E_SUCCESS)
5195                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5196                                      ->eth_dev);
5197
5198         return ret;
5199 }
5200
5201 /* Initialize VSI for RX */
5202 static int
5203 i40e_dev_rx_init(struct i40e_pf *pf)
5204 {
5205         struct rte_eth_dev_data *data = pf->dev_data;
5206         int ret = I40E_SUCCESS;
5207         uint16_t i;
5208         struct i40e_rx_queue *rxq;
5209
5210         i40e_pf_config_mq_rx(pf);
5211         for (i = 0; i < data->nb_rx_queues; i++) {
5212                 rxq = data->rx_queues[i];
5213                 if (!rxq || !rxq->q_set)
5214                         continue;
5215
5216                 ret = i40e_rx_queue_init(rxq);
5217                 if (ret != I40E_SUCCESS) {
5218                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5219                                     "initialization");
5220                         break;
5221                 }
5222         }
5223         if (ret == I40E_SUCCESS)
5224                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5225                                      ->eth_dev);
5226
5227         return ret;
5228 }
5229
5230 static int
5231 i40e_dev_rxtx_init(struct i40e_pf *pf)
5232 {
5233         int err;
5234
5235         err = i40e_dev_tx_init(pf);
5236         if (err) {
5237                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5238                 return err;
5239         }
5240         err = i40e_dev_rx_init(pf);
5241         if (err) {
5242                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5243                 return err;
5244         }
5245
5246         return err;
5247 }
5248
5249 static int
5250 i40e_vmdq_setup(struct rte_eth_dev *dev)
5251 {
5252         struct rte_eth_conf *conf = &dev->data->dev_conf;
5253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5254         int i, err, conf_vsis, j, loop;
5255         struct i40e_vsi *vsi;
5256         struct i40e_vmdq_info *vmdq_info;
5257         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5259
5260         /*
5261          * Disable interrupt to avoid message from VF. Furthermore, it will
5262          * avoid race condition in VSI creation/destroy.
5263          */
5264         i40e_pf_disable_irq0(hw);
5265
5266         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5267                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5268                 return -ENOTSUP;
5269         }
5270
5271         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5272         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5273                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5274                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5275                         pf->max_nb_vmdq_vsi);
5276                 return -ENOTSUP;
5277         }
5278
5279         if (pf->vmdq != NULL) {
5280                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5281                 return 0;
5282         }
5283
5284         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5285                                 sizeof(*vmdq_info) * conf_vsis, 0);
5286
5287         if (pf->vmdq == NULL) {
5288                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5289                 return -ENOMEM;
5290         }
5291
5292         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5293
5294         /* Create VMDQ VSI */
5295         for (i = 0; i < conf_vsis; i++) {
5296                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5297                                 vmdq_conf->enable_loop_back);
5298                 if (vsi == NULL) {
5299                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5300                         err = -1;
5301                         goto err_vsi_setup;
5302                 }
5303                 vmdq_info = &pf->vmdq[i];
5304                 vmdq_info->pf = pf;
5305                 vmdq_info->vsi = vsi;
5306         }
5307         pf->nb_cfg_vmdq_vsi = conf_vsis;
5308
5309         /* Configure Vlan */
5310         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5311         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5312                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5313                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5314                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5315                                         vmdq_conf->pool_map[i].vlan_id, j);
5316
5317                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5318                                                 vmdq_conf->pool_map[i].vlan_id);
5319                                 if (err) {
5320                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5321                                         err = -1;
5322                                         goto err_vsi_setup;
5323                                 }
5324                         }
5325                 }
5326         }
5327
5328         i40e_pf_enable_irq0(hw);
5329
5330         return 0;
5331
5332 err_vsi_setup:
5333         for (i = 0; i < conf_vsis; i++)
5334                 if (pf->vmdq[i].vsi == NULL)
5335                         break;
5336                 else
5337                         i40e_vsi_release(pf->vmdq[i].vsi);
5338
5339         rte_free(pf->vmdq);
5340         pf->vmdq = NULL;
5341         i40e_pf_enable_irq0(hw);
5342         return err;
5343 }
5344
5345 static void
5346 i40e_stat_update_32(struct i40e_hw *hw,
5347                    uint32_t reg,
5348                    bool offset_loaded,
5349                    uint64_t *offset,
5350                    uint64_t *stat)
5351 {
5352         uint64_t new_data;
5353
5354         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5355         if (!offset_loaded)
5356                 *offset = new_data;
5357
5358         if (new_data >= *offset)
5359                 *stat = (uint64_t)(new_data - *offset);
5360         else
5361                 *stat = (uint64_t)((new_data +
5362                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5363 }
5364
5365 static void
5366 i40e_stat_update_48(struct i40e_hw *hw,
5367                    uint32_t hireg,
5368                    uint32_t loreg,
5369                    bool offset_loaded,
5370                    uint64_t *offset,
5371                    uint64_t *stat)
5372 {
5373         uint64_t new_data;
5374
5375         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5376         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5377                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5378
5379         if (!offset_loaded)
5380                 *offset = new_data;
5381
5382         if (new_data >= *offset)
5383                 *stat = new_data - *offset;
5384         else
5385                 *stat = (uint64_t)((new_data +
5386                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5387
5388         *stat &= I40E_48_BIT_MASK;
5389 }
5390
5391 /* Disable IRQ0 */
5392 void
5393 i40e_pf_disable_irq0(struct i40e_hw *hw)
5394 {
5395         /* Disable all interrupt types */
5396         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5397         I40E_WRITE_FLUSH(hw);
5398 }
5399
5400 /* Enable IRQ0 */
5401 void
5402 i40e_pf_enable_irq0(struct i40e_hw *hw)
5403 {
5404         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5405                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5406                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5407                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5408         I40E_WRITE_FLUSH(hw);
5409 }
5410
5411 static void
5412 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5413 {
5414         /* read pending request and disable first */
5415         i40e_pf_disable_irq0(hw);
5416         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5417         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5418                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5419
5420         if (no_queue)
5421                 /* Link no queues with irq0 */
5422                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5423                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5424 }
5425
5426 static void
5427 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5428 {
5429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5431         int i;
5432         uint16_t abs_vf_id;
5433         uint32_t index, offset, val;
5434
5435         if (!pf->vfs)
5436                 return;
5437         /**
5438          * Try to find which VF trigger a reset, use absolute VF id to access
5439          * since the reg is global register.
5440          */
5441         for (i = 0; i < pf->vf_num; i++) {
5442                 abs_vf_id = hw->func_caps.vf_base_id + i;
5443                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5444                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5445                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5446                 /* VFR event occured */
5447                 if (val & (0x1 << offset)) {
5448                         int ret;
5449
5450                         /* Clear the event first */
5451                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5452                                                         (0x1 << offset));
5453                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5454                         /**
5455                          * Only notify a VF reset event occured,
5456                          * don't trigger another SW reset
5457                          */
5458                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5459                         if (ret != I40E_SUCCESS)
5460                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5461                 }
5462         }
5463 }
5464
5465 static void
5466 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5467 {
5468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5469         struct i40e_virtchnl_pf_event event;
5470         int i;
5471
5472         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5473         event.event_data.link_event.link_status =
5474                 dev->data->dev_link.link_status;
5475         event.event_data.link_event.link_speed =
5476                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5477
5478         for (i = 0; i < pf->vf_num; i++)
5479                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5480                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5481 }
5482
5483 static void
5484 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5485 {
5486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5487         struct i40e_arq_event_info info;
5488         uint16_t pending, opcode;
5489         int ret;
5490
5491         info.buf_len = I40E_AQ_BUF_SZ;
5492         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5493         if (!info.msg_buf) {
5494                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5495                 return;
5496         }
5497
5498         pending = 1;
5499         while (pending) {
5500                 ret = i40e_clean_arq_element(hw, &info, &pending);
5501
5502                 if (ret != I40E_SUCCESS) {
5503                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5504                                     "aq_err: %u", hw->aq.asq_last_status);
5505                         break;
5506                 }
5507                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5508
5509                 switch (opcode) {
5510                 case i40e_aqc_opc_send_msg_to_pf:
5511                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5512                         i40e_pf_host_handle_vf_msg(dev,
5513                                         rte_le_to_cpu_16(info.desc.retval),
5514                                         rte_le_to_cpu_32(info.desc.cookie_high),
5515                                         rte_le_to_cpu_32(info.desc.cookie_low),
5516                                         info.msg_buf,
5517                                         info.msg_len);
5518                         break;
5519                 case i40e_aqc_opc_get_link_status:
5520                         ret = i40e_dev_link_update(dev, 0);
5521                         if (!ret) {
5522                                 i40e_notify_all_vfs_link_status(dev);
5523                                 _rte_eth_dev_callback_process(dev,
5524                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5525                         }
5526                         break;
5527                 default:
5528                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5529                                     opcode);
5530                         break;
5531                 }
5532         }
5533         rte_free(info.msg_buf);
5534 }
5535
5536 /**
5537  * Interrupt handler triggered by NIC  for handling
5538  * specific interrupt.
5539  *
5540  * @param handle
5541  *  Pointer to interrupt handle.
5542  * @param param
5543  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5544  *
5545  * @return
5546  *  void
5547  */
5548 static void
5549 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5550                            void *param)
5551 {
5552         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5554         uint32_t icr0;
5555
5556         /* Disable interrupt */
5557         i40e_pf_disable_irq0(hw);
5558
5559         /* read out interrupt causes */
5560         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5561
5562         /* No interrupt event indicated */
5563         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5564                 PMD_DRV_LOG(INFO, "No interrupt event");
5565                 goto done;
5566         }
5567 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5568         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5569                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5570         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5571                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5572         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5573                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5574         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5575                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5576         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5577                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5578         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5579                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5580         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5581                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5582 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5583
5584         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5585                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5586                 i40e_dev_handle_vfr_event(dev);
5587         }
5588         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5589                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5590                 i40e_dev_handle_aq_msg(dev);
5591         }
5592
5593 done:
5594         /* Enable interrupt */
5595         i40e_pf_enable_irq0(hw);
5596         rte_intr_enable(intr_handle);
5597 }
5598
5599 static int
5600 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5601                          struct i40e_macvlan_filter *filter,
5602                          int total)
5603 {
5604         int ele_num, ele_buff_size;
5605         int num, actual_num, i;
5606         uint16_t flags;
5607         int ret = I40E_SUCCESS;
5608         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5609         struct i40e_aqc_add_macvlan_element_data *req_list;
5610
5611         if (filter == NULL  || total == 0)
5612                 return I40E_ERR_PARAM;
5613         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5614         ele_buff_size = hw->aq.asq_buf_size;
5615
5616         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5617         if (req_list == NULL) {
5618                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5619                 return I40E_ERR_NO_MEMORY;
5620         }
5621
5622         num = 0;
5623         do {
5624                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5625                 memset(req_list, 0, ele_buff_size);
5626
5627                 for (i = 0; i < actual_num; i++) {
5628                         (void)rte_memcpy(req_list[i].mac_addr,
5629                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5630                         req_list[i].vlan_tag =
5631                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5632
5633                         switch (filter[num + i].filter_type) {
5634                         case RTE_MAC_PERFECT_MATCH:
5635                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5636                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5637                                 break;
5638                         case RTE_MACVLAN_PERFECT_MATCH:
5639                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5640                                 break;
5641                         case RTE_MAC_HASH_MATCH:
5642                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5643                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5644                                 break;
5645                         case RTE_MACVLAN_HASH_MATCH:
5646                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5647                                 break;
5648                         default:
5649                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5650                                 ret = I40E_ERR_PARAM;
5651                                 goto DONE;
5652                         }
5653
5654                         req_list[i].queue_number = 0;
5655
5656                         req_list[i].flags = rte_cpu_to_le_16(flags);
5657                 }
5658
5659                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5660                                                 actual_num, NULL);
5661                 if (ret != I40E_SUCCESS) {
5662                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5663                         goto DONE;
5664                 }
5665                 num += actual_num;
5666         } while (num < total);
5667
5668 DONE:
5669         rte_free(req_list);
5670         return ret;
5671 }
5672
5673 static int
5674 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5675                             struct i40e_macvlan_filter *filter,
5676                             int total)
5677 {
5678         int ele_num, ele_buff_size;
5679         int num, actual_num, i;
5680         uint16_t flags;
5681         int ret = I40E_SUCCESS;
5682         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5683         struct i40e_aqc_remove_macvlan_element_data *req_list;
5684
5685         if (filter == NULL  || total == 0)
5686                 return I40E_ERR_PARAM;
5687
5688         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5689         ele_buff_size = hw->aq.asq_buf_size;
5690
5691         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5692         if (req_list == NULL) {
5693                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5694                 return I40E_ERR_NO_MEMORY;
5695         }
5696
5697         num = 0;
5698         do {
5699                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5700                 memset(req_list, 0, ele_buff_size);
5701
5702                 for (i = 0; i < actual_num; i++) {
5703                         (void)rte_memcpy(req_list[i].mac_addr,
5704                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5705                         req_list[i].vlan_tag =
5706                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5707
5708                         switch (filter[num + i].filter_type) {
5709                         case RTE_MAC_PERFECT_MATCH:
5710                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5711                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5712                                 break;
5713                         case RTE_MACVLAN_PERFECT_MATCH:
5714                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5715                                 break;
5716                         case RTE_MAC_HASH_MATCH:
5717                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5718                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5719                                 break;
5720                         case RTE_MACVLAN_HASH_MATCH:
5721                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5722                                 break;
5723                         default:
5724                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5725                                 ret = I40E_ERR_PARAM;
5726                                 goto DONE;
5727                         }
5728                         req_list[i].flags = rte_cpu_to_le_16(flags);
5729                 }
5730
5731                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5732                                                 actual_num, NULL);
5733                 if (ret != I40E_SUCCESS) {
5734                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5735                         goto DONE;
5736                 }
5737                 num += actual_num;
5738         } while (num < total);
5739
5740 DONE:
5741         rte_free(req_list);
5742         return ret;
5743 }
5744
5745 /* Find out specific MAC filter */
5746 static struct i40e_mac_filter *
5747 i40e_find_mac_filter(struct i40e_vsi *vsi,
5748                          struct ether_addr *macaddr)
5749 {
5750         struct i40e_mac_filter *f;
5751
5752         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5753                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5754                         return f;
5755         }
5756
5757         return NULL;
5758 }
5759
5760 static bool
5761 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5762                          uint16_t vlan_id)
5763 {
5764         uint32_t vid_idx, vid_bit;
5765
5766         if (vlan_id > ETH_VLAN_ID_MAX)
5767                 return 0;
5768
5769         vid_idx = I40E_VFTA_IDX(vlan_id);
5770         vid_bit = I40E_VFTA_BIT(vlan_id);
5771
5772         if (vsi->vfta[vid_idx] & vid_bit)
5773                 return 1;
5774         else
5775                 return 0;
5776 }
5777
5778 static void
5779 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5780                          uint16_t vlan_id, bool on)
5781 {
5782         uint32_t vid_idx, vid_bit;
5783
5784         if (vlan_id > ETH_VLAN_ID_MAX)
5785                 return;
5786
5787         vid_idx = I40E_VFTA_IDX(vlan_id);
5788         vid_bit = I40E_VFTA_BIT(vlan_id);
5789
5790         if (on)
5791                 vsi->vfta[vid_idx] |= vid_bit;
5792         else
5793                 vsi->vfta[vid_idx] &= ~vid_bit;
5794 }
5795
5796 /**
5797  * Find all vlan options for specific mac addr,
5798  * return with actual vlan found.
5799  */
5800 static inline int
5801 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5802                            struct i40e_macvlan_filter *mv_f,
5803                            int num, struct ether_addr *addr)
5804 {
5805         int i;
5806         uint32_t j, k;
5807
5808         /**
5809          * Not to use i40e_find_vlan_filter to decrease the loop time,
5810          * although the code looks complex.
5811           */
5812         if (num < vsi->vlan_num)
5813                 return I40E_ERR_PARAM;
5814
5815         i = 0;
5816         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5817                 if (vsi->vfta[j]) {
5818                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5819                                 if (vsi->vfta[j] & (1 << k)) {
5820                                         if (i > num - 1) {
5821                                                 PMD_DRV_LOG(ERR, "vlan number "
5822                                                             "not match");
5823                                                 return I40E_ERR_PARAM;
5824                                         }
5825                                         (void)rte_memcpy(&mv_f[i].macaddr,
5826                                                         addr, ETH_ADDR_LEN);
5827                                         mv_f[i].vlan_id =
5828                                                 j * I40E_UINT32_BIT_SIZE + k;
5829                                         i++;
5830                                 }
5831                         }
5832                 }
5833         }
5834         return I40E_SUCCESS;
5835 }
5836
5837 static inline int
5838 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5839                            struct i40e_macvlan_filter *mv_f,
5840                            int num,
5841                            uint16_t vlan)
5842 {
5843         int i = 0;
5844         struct i40e_mac_filter *f;
5845
5846         if (num < vsi->mac_num)
5847                 return I40E_ERR_PARAM;
5848
5849         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5850                 if (i > num - 1) {
5851                         PMD_DRV_LOG(ERR, "buffer number not match");
5852                         return I40E_ERR_PARAM;
5853                 }
5854                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5855                                 ETH_ADDR_LEN);
5856                 mv_f[i].vlan_id = vlan;
5857                 mv_f[i].filter_type = f->mac_info.filter_type;
5858                 i++;
5859         }
5860
5861         return I40E_SUCCESS;
5862 }
5863
5864 static int
5865 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5866 {
5867         int i, num;
5868         struct i40e_mac_filter *f;
5869         struct i40e_macvlan_filter *mv_f;
5870         int ret = I40E_SUCCESS;
5871
5872         if (vsi == NULL || vsi->mac_num == 0)
5873                 return I40E_ERR_PARAM;
5874
5875         /* Case that no vlan is set */
5876         if (vsi->vlan_num == 0)
5877                 num = vsi->mac_num;
5878         else
5879                 num = vsi->mac_num * vsi->vlan_num;
5880
5881         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5882         if (mv_f == NULL) {
5883                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5884                 return I40E_ERR_NO_MEMORY;
5885         }
5886
5887         i = 0;
5888         if (vsi->vlan_num == 0) {
5889                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5890                         (void)rte_memcpy(&mv_f[i].macaddr,
5891                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5892                         mv_f[i].vlan_id = 0;
5893                         i++;
5894                 }
5895         } else {
5896                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5897                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5898                                         vsi->vlan_num, &f->mac_info.mac_addr);
5899                         if (ret != I40E_SUCCESS)
5900                                 goto DONE;
5901                         i += vsi->vlan_num;
5902                 }
5903         }
5904
5905         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5906 DONE:
5907         rte_free(mv_f);
5908
5909         return ret;
5910 }
5911
5912 int
5913 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5914 {
5915         struct i40e_macvlan_filter *mv_f;
5916         int mac_num;
5917         int ret = I40E_SUCCESS;
5918
5919         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5920                 return I40E_ERR_PARAM;
5921
5922         /* If it's already set, just return */
5923         if (i40e_find_vlan_filter(vsi,vlan))
5924                 return I40E_SUCCESS;
5925
5926         mac_num = vsi->mac_num;
5927
5928         if (mac_num == 0) {
5929                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5930                 return I40E_ERR_PARAM;
5931         }
5932
5933         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5934
5935         if (mv_f == NULL) {
5936                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5937                 return I40E_ERR_NO_MEMORY;
5938         }
5939
5940         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5941
5942         if (ret != I40E_SUCCESS)
5943                 goto DONE;
5944
5945         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5946
5947         if (ret != I40E_SUCCESS)
5948                 goto DONE;
5949
5950         i40e_set_vlan_filter(vsi, vlan, 1);
5951
5952         vsi->vlan_num++;
5953         ret = I40E_SUCCESS;
5954 DONE:
5955         rte_free(mv_f);
5956         return ret;
5957 }
5958
5959 int
5960 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5961 {
5962         struct i40e_macvlan_filter *mv_f;
5963         int mac_num;
5964         int ret = I40E_SUCCESS;
5965
5966         /**
5967          * Vlan 0 is the generic filter for untagged packets
5968          * and can't be removed.
5969          */
5970         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5971                 return I40E_ERR_PARAM;
5972
5973         /* If can't find it, just return */
5974         if (!i40e_find_vlan_filter(vsi, vlan))
5975                 return I40E_ERR_PARAM;
5976
5977         mac_num = vsi->mac_num;
5978
5979         if (mac_num == 0) {
5980                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5981                 return I40E_ERR_PARAM;
5982         }
5983
5984         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5985
5986         if (mv_f == NULL) {
5987                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5988                 return I40E_ERR_NO_MEMORY;
5989         }
5990
5991         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5992
5993         if (ret != I40E_SUCCESS)
5994                 goto DONE;
5995
5996         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5997
5998         if (ret != I40E_SUCCESS)
5999                 goto DONE;
6000
6001         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6002         if (vsi->vlan_num == 1) {
6003                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6004                 if (ret != I40E_SUCCESS)
6005                         goto DONE;
6006
6007                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6008                 if (ret != I40E_SUCCESS)
6009                         goto DONE;
6010         }
6011
6012         i40e_set_vlan_filter(vsi, vlan, 0);
6013
6014         vsi->vlan_num--;
6015         ret = I40E_SUCCESS;
6016 DONE:
6017         rte_free(mv_f);
6018         return ret;
6019 }
6020
6021 int
6022 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6023 {
6024         struct i40e_mac_filter *f;
6025         struct i40e_macvlan_filter *mv_f;
6026         int i, vlan_num = 0;
6027         int ret = I40E_SUCCESS;
6028
6029         /* If it's add and we've config it, return */
6030         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6031         if (f != NULL)
6032                 return I40E_SUCCESS;
6033         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6034                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6035
6036                 /**
6037                  * If vlan_num is 0, that's the first time to add mac,
6038                  * set mask for vlan_id 0.
6039                  */
6040                 if (vsi->vlan_num == 0) {
6041                         i40e_set_vlan_filter(vsi, 0, 1);
6042                         vsi->vlan_num = 1;
6043                 }
6044                 vlan_num = vsi->vlan_num;
6045         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6046                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6047                 vlan_num = 1;
6048
6049         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6050         if (mv_f == NULL) {
6051                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6052                 return I40E_ERR_NO_MEMORY;
6053         }
6054
6055         for (i = 0; i < vlan_num; i++) {
6056                 mv_f[i].filter_type = mac_filter->filter_type;
6057                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6058                                 ETH_ADDR_LEN);
6059         }
6060
6061         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6062                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6063                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6064                                         &mac_filter->mac_addr);
6065                 if (ret != I40E_SUCCESS)
6066                         goto DONE;
6067         }
6068
6069         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6070         if (ret != I40E_SUCCESS)
6071                 goto DONE;
6072
6073         /* Add the mac addr into mac list */
6074         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6075         if (f == NULL) {
6076                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6077                 ret = I40E_ERR_NO_MEMORY;
6078                 goto DONE;
6079         }
6080         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6081                         ETH_ADDR_LEN);
6082         f->mac_info.filter_type = mac_filter->filter_type;
6083         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6084         vsi->mac_num++;
6085
6086         ret = I40E_SUCCESS;
6087 DONE:
6088         rte_free(mv_f);
6089
6090         return ret;
6091 }
6092
6093 int
6094 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6095 {
6096         struct i40e_mac_filter *f;
6097         struct i40e_macvlan_filter *mv_f;
6098         int i, vlan_num;
6099         enum rte_mac_filter_type filter_type;
6100         int ret = I40E_SUCCESS;
6101
6102         /* Can't find it, return an error */
6103         f = i40e_find_mac_filter(vsi, addr);
6104         if (f == NULL)
6105                 return I40E_ERR_PARAM;
6106
6107         vlan_num = vsi->vlan_num;
6108         filter_type = f->mac_info.filter_type;
6109         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6110                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6111                 if (vlan_num == 0) {
6112                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6113                         return I40E_ERR_PARAM;
6114                 }
6115         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6116                         filter_type == RTE_MAC_HASH_MATCH)
6117                 vlan_num = 1;
6118
6119         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6120         if (mv_f == NULL) {
6121                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6122                 return I40E_ERR_NO_MEMORY;
6123         }
6124
6125         for (i = 0; i < vlan_num; i++) {
6126                 mv_f[i].filter_type = filter_type;
6127                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6128                                 ETH_ADDR_LEN);
6129         }
6130         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6131                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6132                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6133                 if (ret != I40E_SUCCESS)
6134                         goto DONE;
6135         }
6136
6137         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6138         if (ret != I40E_SUCCESS)
6139                 goto DONE;
6140
6141         /* Remove the mac addr into mac list */
6142         TAILQ_REMOVE(&vsi->mac_list, f, next);
6143         rte_free(f);
6144         vsi->mac_num--;
6145
6146         ret = I40E_SUCCESS;
6147 DONE:
6148         rte_free(mv_f);
6149         return ret;
6150 }
6151
6152 /* Configure hash enable flags for RSS */
6153 uint64_t
6154 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6155 {
6156         uint64_t hena = 0;
6157
6158         if (!flags)
6159                 return hena;
6160
6161         if (flags & ETH_RSS_FRAG_IPV4)
6162                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6163         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6164                 if (type == I40E_MAC_X722) {
6165                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6166                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6167                 } else
6168                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6169         }
6170         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6171                 if (type == I40E_MAC_X722) {
6172                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6173                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6174                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6175                 } else
6176                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6177         }
6178         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6179                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6180         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6181                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6182         if (flags & ETH_RSS_FRAG_IPV6)
6183                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6184         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6185                 if (type == I40E_MAC_X722) {
6186                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6187                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6188                 } else
6189                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6190         }
6191         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6192                 if (type == I40E_MAC_X722) {
6193                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6194                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6195                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6196                 } else
6197                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6198         }
6199         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6200                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6201         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6202                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6203         if (flags & ETH_RSS_L2_PAYLOAD)
6204                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6205
6206         return hena;
6207 }
6208
6209 /* Parse the hash enable flags */
6210 uint64_t
6211 i40e_parse_hena(uint64_t flags)
6212 {
6213         uint64_t rss_hf = 0;
6214
6215         if (!flags)
6216                 return rss_hf;
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6218                 rss_hf |= ETH_RSS_FRAG_IPV4;
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6221 #ifdef X722_SUPPORT
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6224 #endif
6225         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6226                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6227 #ifdef X722_SUPPORT
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6230         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6231                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6232 #endif
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6234                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6235         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6236                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6238                 rss_hf |= ETH_RSS_FRAG_IPV6;
6239         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6240                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6241 #ifdef X722_SUPPORT
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6244 #endif
6245         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6246                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6247 #ifdef X722_SUPPORT
6248         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6249                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6250         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6251                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6252 #endif
6253         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6254                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6255         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6256                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6257         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6258                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6259
6260         return rss_hf;
6261 }
6262
6263 /* Disable RSS */
6264 static void
6265 i40e_pf_disable_rss(struct i40e_pf *pf)
6266 {
6267         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6268         uint64_t hena;
6269
6270         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6271         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6272         if (hw->mac.type == I40E_MAC_X722)
6273                 hena &= ~I40E_RSS_HENA_ALL_X722;
6274         else
6275                 hena &= ~I40E_RSS_HENA_ALL;
6276         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6277         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6278         I40E_WRITE_FLUSH(hw);
6279 }
6280
6281 static int
6282 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6283 {
6284         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6285         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6286         int ret = 0;
6287
6288         if (!key || key_len == 0) {
6289                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6290                 return 0;
6291         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6292                 sizeof(uint32_t)) {
6293                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6294                 return -EINVAL;
6295         }
6296
6297         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6298                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6299                         (struct i40e_aqc_get_set_rss_key_data *)key;
6300
6301                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6302                 if (ret)
6303                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6304                                      "via AQ");
6305         } else {
6306                 uint32_t *hash_key = (uint32_t *)key;
6307                 uint16_t i;
6308
6309                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6310                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6311                 I40E_WRITE_FLUSH(hw);
6312         }
6313
6314         return ret;
6315 }
6316
6317 static int
6318 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6319 {
6320         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6321         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6322         int ret;
6323
6324         if (!key || !key_len)
6325                 return -EINVAL;
6326
6327         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6328                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6329                         (struct i40e_aqc_get_set_rss_key_data *)key);
6330                 if (ret) {
6331                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6332                         return ret;
6333                 }
6334         } else {
6335                 uint32_t *key_dw = (uint32_t *)key;
6336                 uint16_t i;
6337
6338                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6339                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6340         }
6341         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6342
6343         return 0;
6344 }
6345
6346 static int
6347 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6348 {
6349         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6350         uint64_t rss_hf;
6351         uint64_t hena;
6352         int ret;
6353
6354         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6355                                rss_conf->rss_key_len);
6356         if (ret)
6357                 return ret;
6358
6359         rss_hf = rss_conf->rss_hf;
6360         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6361         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6362         if (hw->mac.type == I40E_MAC_X722)
6363                 hena &= ~I40E_RSS_HENA_ALL_X722;
6364         else
6365                 hena &= ~I40E_RSS_HENA_ALL;
6366         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6367         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6368         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6369         I40E_WRITE_FLUSH(hw);
6370
6371         return 0;
6372 }
6373
6374 static int
6375 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6376                          struct rte_eth_rss_conf *rss_conf)
6377 {
6378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6380         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6381         uint64_t hena;
6382
6383         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6384         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6385         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6386                  ? I40E_RSS_HENA_ALL_X722
6387                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6388                 if (rss_hf != 0) /* Enable RSS */
6389                         return -EINVAL;
6390                 return 0; /* Nothing to do */
6391         }
6392         /* RSS enabled */
6393         if (rss_hf == 0) /* Disable RSS */
6394                 return -EINVAL;
6395
6396         return i40e_hw_rss_hash_set(pf, rss_conf);
6397 }
6398
6399 static int
6400 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6401                            struct rte_eth_rss_conf *rss_conf)
6402 {
6403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6405         uint64_t hena;
6406
6407         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6408                          &rss_conf->rss_key_len);
6409
6410         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6411         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6412         rss_conf->rss_hf = i40e_parse_hena(hena);
6413
6414         return 0;
6415 }
6416
6417 static int
6418 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6419 {
6420         switch (filter_type) {
6421         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6422                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6423                 break;
6424         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6425                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6426                 break;
6427         case RTE_TUNNEL_FILTER_IMAC_TENID:
6428                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6429                 break;
6430         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6431                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6432                 break;
6433         case ETH_TUNNEL_FILTER_IMAC:
6434                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6435                 break;
6436         case ETH_TUNNEL_FILTER_OIP:
6437                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6438                 break;
6439         case ETH_TUNNEL_FILTER_IIP:
6440                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6441                 break;
6442         default:
6443                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6444                 return -EINVAL;
6445         }
6446
6447         return 0;
6448 }
6449
6450 static int
6451 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6452                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6453                         uint8_t add)
6454 {
6455         uint16_t ip_type;
6456         uint32_t ipv4_addr;
6457         uint8_t i, tun_type = 0;
6458         /* internal varialbe to convert ipv6 byte order */
6459         uint32_t convert_ipv6[4];
6460         int val, ret = 0;
6461         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6462         struct i40e_vsi *vsi = pf->main_vsi;
6463         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6464         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6465
6466         cld_filter = rte_zmalloc("tunnel_filter",
6467                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6468                 0);
6469
6470         if (NULL == cld_filter) {
6471                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6472                 return -EINVAL;
6473         }
6474         pfilter = cld_filter;
6475
6476         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6477         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6478
6479         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6480         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6481                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6482                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6483                 rte_memcpy(&pfilter->ipaddr.v4.data,
6484                                 &rte_cpu_to_le_32(ipv4_addr),
6485                                 sizeof(pfilter->ipaddr.v4.data));
6486         } else {
6487                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6488                 for (i = 0; i < 4; i++) {
6489                         convert_ipv6[i] =
6490                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6491                 }
6492                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6493                                 sizeof(pfilter->ipaddr.v6.data));
6494         }
6495
6496         /* check tunneled type */
6497         switch (tunnel_filter->tunnel_type) {
6498         case RTE_TUNNEL_TYPE_VXLAN:
6499                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6500                 break;
6501         case RTE_TUNNEL_TYPE_NVGRE:
6502                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6503                 break;
6504         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6505                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6506                 break;
6507         default:
6508                 /* Other tunnel types is not supported. */
6509                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6510                 rte_free(cld_filter);
6511                 return -EINVAL;
6512         }
6513
6514         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6515                                                 &pfilter->flags);
6516         if (val < 0) {
6517                 rte_free(cld_filter);
6518                 return -EINVAL;
6519         }
6520
6521         pfilter->flags |= rte_cpu_to_le_16(
6522                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6523                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6524         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6525         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6526
6527         if (add)
6528                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6529         else
6530                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6531                                                 cld_filter, 1);
6532
6533         rte_free(cld_filter);
6534         return ret;
6535 }
6536
6537 static int
6538 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6539 {
6540         uint8_t i;
6541
6542         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6543                 if (pf->vxlan_ports[i] == port)
6544                         return i;
6545         }
6546
6547         return -1;
6548 }
6549
6550 static int
6551 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6552 {
6553         int  idx, ret;
6554         uint8_t filter_idx;
6555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6556
6557         idx = i40e_get_vxlan_port_idx(pf, port);
6558
6559         /* Check if port already exists */
6560         if (idx >= 0) {
6561                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6562                 return -EINVAL;
6563         }
6564
6565         /* Now check if there is space to add the new port */
6566         idx = i40e_get_vxlan_port_idx(pf, 0);
6567         if (idx < 0) {
6568                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6569                         "not adding port %d", port);
6570                 return -ENOSPC;
6571         }
6572
6573         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6574                                         &filter_idx, NULL);
6575         if (ret < 0) {
6576                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6577                 return -1;
6578         }
6579
6580         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6581                          port,  filter_idx);
6582
6583         /* New port: add it and mark its index in the bitmap */
6584         pf->vxlan_ports[idx] = port;
6585         pf->vxlan_bitmap |= (1 << idx);
6586
6587         if (!(pf->flags & I40E_FLAG_VXLAN))
6588                 pf->flags |= I40E_FLAG_VXLAN;
6589
6590         return 0;
6591 }
6592
6593 static int
6594 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6595 {
6596         int idx;
6597         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6598
6599         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6600                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6601                 return -EINVAL;
6602         }
6603
6604         idx = i40e_get_vxlan_port_idx(pf, port);
6605
6606         if (idx < 0) {
6607                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6608                 return -EINVAL;
6609         }
6610
6611         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6612                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6613                 return -1;
6614         }
6615
6616         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6617                         port, idx);
6618
6619         pf->vxlan_ports[idx] = 0;
6620         pf->vxlan_bitmap &= ~(1 << idx);
6621
6622         if (!pf->vxlan_bitmap)
6623                 pf->flags &= ~I40E_FLAG_VXLAN;
6624
6625         return 0;
6626 }
6627
6628 /* Add UDP tunneling port */
6629 static int
6630 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6631                              struct rte_eth_udp_tunnel *udp_tunnel)
6632 {
6633         int ret = 0;
6634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6635
6636         if (udp_tunnel == NULL)
6637                 return -EINVAL;
6638
6639         switch (udp_tunnel->prot_type) {
6640         case RTE_TUNNEL_TYPE_VXLAN:
6641                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6642                 break;
6643
6644         case RTE_TUNNEL_TYPE_GENEVE:
6645         case RTE_TUNNEL_TYPE_TEREDO:
6646                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6647                 ret = -1;
6648                 break;
6649
6650         default:
6651                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6652                 ret = -1;
6653                 break;
6654         }
6655
6656         return ret;
6657 }
6658
6659 /* Remove UDP tunneling port */
6660 static int
6661 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6662                              struct rte_eth_udp_tunnel *udp_tunnel)
6663 {
6664         int ret = 0;
6665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6666
6667         if (udp_tunnel == NULL)
6668                 return -EINVAL;
6669
6670         switch (udp_tunnel->prot_type) {
6671         case RTE_TUNNEL_TYPE_VXLAN:
6672                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6673                 break;
6674         case RTE_TUNNEL_TYPE_GENEVE:
6675         case RTE_TUNNEL_TYPE_TEREDO:
6676                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6677                 ret = -1;
6678                 break;
6679         default:
6680                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6681                 ret = -1;
6682                 break;
6683         }
6684
6685         return ret;
6686 }
6687
6688 /* Calculate the maximum number of contiguous PF queues that are configured */
6689 static int
6690 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6691 {
6692         struct rte_eth_dev_data *data = pf->dev_data;
6693         int i, num;
6694         struct i40e_rx_queue *rxq;
6695
6696         num = 0;
6697         for (i = 0; i < pf->lan_nb_qps; i++) {
6698                 rxq = data->rx_queues[i];
6699                 if (rxq && rxq->q_set)
6700                         num++;
6701                 else
6702                         break;
6703         }
6704
6705         return num;
6706 }
6707
6708 /* Configure RSS */
6709 static int
6710 i40e_pf_config_rss(struct i40e_pf *pf)
6711 {
6712         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6713         struct rte_eth_rss_conf rss_conf;
6714         uint32_t i, lut = 0;
6715         uint16_t j, num;
6716
6717         /*
6718          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6719          * It's necessary to calulate the actual PF queues that are configured.
6720          */
6721         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6722                 num = i40e_pf_calc_configured_queues_num(pf);
6723         else
6724                 num = pf->dev_data->nb_rx_queues;
6725
6726         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6727         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6728                         num);
6729
6730         if (num == 0) {
6731                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6732                 return -ENOTSUP;
6733         }
6734
6735         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6736                 if (j == num)
6737                         j = 0;
6738                 lut = (lut << 8) | (j & ((0x1 <<
6739                         hw->func_caps.rss_table_entry_width) - 1));
6740                 if ((i & 3) == 3)
6741                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6742         }
6743
6744         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6745         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6746                 i40e_pf_disable_rss(pf);
6747                 return 0;
6748         }
6749         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6750                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6751                 /* Random default keys */
6752                 static uint32_t rss_key_default[] = {0x6b793944,
6753                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6754                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6755                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6756
6757                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6758                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6759                                                         sizeof(uint32_t);
6760         }
6761
6762         return i40e_hw_rss_hash_set(pf, &rss_conf);
6763 }
6764
6765 static int
6766 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6767                                struct rte_eth_tunnel_filter_conf *filter)
6768 {
6769         if (pf == NULL || filter == NULL) {
6770                 PMD_DRV_LOG(ERR, "Invalid parameter");
6771                 return -EINVAL;
6772         }
6773
6774         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6775                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6776                 return -EINVAL;
6777         }
6778
6779         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6780                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6781                 return -EINVAL;
6782         }
6783
6784         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6785                 (is_zero_ether_addr(&filter->outer_mac))) {
6786                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6787                 return -EINVAL;
6788         }
6789
6790         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6791                 (is_zero_ether_addr(&filter->inner_mac))) {
6792                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6793                 return -EINVAL;
6794         }
6795
6796         return 0;
6797 }
6798
6799 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6800 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6801 static int
6802 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6803 {
6804         uint32_t val, reg;
6805         int ret = -EINVAL;
6806
6807         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6808         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6809
6810         if (len == 3) {
6811                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6812         } else if (len == 4) {
6813                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6814         } else {
6815                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6816                 return ret;
6817         }
6818
6819         if (reg != val) {
6820                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6821                                                    reg, NULL);
6822                 if (ret != 0)
6823                         return ret;
6824         } else {
6825                 ret = 0;
6826         }
6827         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6828                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6829
6830         return ret;
6831 }
6832
6833 static int
6834 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6835 {
6836         int ret = -EINVAL;
6837
6838         if (!hw || !cfg)
6839                 return -EINVAL;
6840
6841         switch (cfg->cfg_type) {
6842         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6843                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6844                 break;
6845         default:
6846                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6847                 break;
6848         }
6849
6850         return ret;
6851 }
6852
6853 static int
6854 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6855                                enum rte_filter_op filter_op,
6856                                void *arg)
6857 {
6858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         int ret = I40E_ERR_PARAM;
6860
6861         switch (filter_op) {
6862         case RTE_ETH_FILTER_SET:
6863                 ret = i40e_dev_global_config_set(hw,
6864                         (struct rte_eth_global_cfg *)arg);
6865                 break;
6866         default:
6867                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6868                 break;
6869         }
6870
6871         return ret;
6872 }
6873
6874 static int
6875 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6876                           enum rte_filter_op filter_op,
6877                           void *arg)
6878 {
6879         struct rte_eth_tunnel_filter_conf *filter;
6880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6881         int ret = I40E_SUCCESS;
6882
6883         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6884
6885         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6886                 return I40E_ERR_PARAM;
6887
6888         switch (filter_op) {
6889         case RTE_ETH_FILTER_NOP:
6890                 if (!(pf->flags & I40E_FLAG_VXLAN))
6891                         ret = I40E_NOT_SUPPORTED;
6892                 break;
6893         case RTE_ETH_FILTER_ADD:
6894                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6895                 break;
6896         case RTE_ETH_FILTER_DELETE:
6897                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6898                 break;
6899         default:
6900                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6901                 ret = I40E_ERR_PARAM;
6902                 break;
6903         }
6904
6905         return ret;
6906 }
6907
6908 static int
6909 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6910 {
6911         int ret = 0;
6912         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6913
6914         /* RSS setup */
6915         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6916                 ret = i40e_pf_config_rss(pf);
6917         else
6918                 i40e_pf_disable_rss(pf);
6919
6920         return ret;
6921 }
6922
6923 /* Get the symmetric hash enable configurations per port */
6924 static void
6925 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6926 {
6927         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6928
6929         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6930 }
6931
6932 /* Set the symmetric hash enable configurations per port */
6933 static void
6934 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6935 {
6936         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6937
6938         if (enable > 0) {
6939                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6940                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6941                                                         "been enabled");
6942                         return;
6943                 }
6944                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6945         } else {
6946                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6947                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6948                                                         "been disabled");
6949                         return;
6950                 }
6951                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6952         }
6953         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6954         I40E_WRITE_FLUSH(hw);
6955 }
6956
6957 /*
6958  * Get global configurations of hash function type and symmetric hash enable
6959  * per flow type (pctype). Note that global configuration means it affects all
6960  * the ports on the same NIC.
6961  */
6962 static int
6963 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6964                                    struct rte_eth_hash_global_conf *g_cfg)
6965 {
6966         uint32_t reg, mask = I40E_FLOW_TYPES;
6967         uint16_t i;
6968         enum i40e_filter_pctype pctype;
6969
6970         memset(g_cfg, 0, sizeof(*g_cfg));
6971         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6972         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6973                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6974         else
6975                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6976         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6977                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6978
6979         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6980                 if (!(mask & (1UL << i)))
6981                         continue;
6982                 mask &= ~(1UL << i);
6983                 /* Bit set indicats the coresponding flow type is supported */
6984                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6985                 /* if flowtype is invalid, continue */
6986                 if (!I40E_VALID_FLOW(i))
6987                         continue;
6988                 pctype = i40e_flowtype_to_pctype(i);
6989                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6990                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6991                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6992         }
6993
6994         return 0;
6995 }
6996
6997 static int
6998 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6999 {
7000         uint32_t i;
7001         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7002
7003         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7004                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7005                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7006                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7007                                                 g_cfg->hash_func);
7008                 return -EINVAL;
7009         }
7010
7011         /*
7012          * As i40e supports less than 32 flow types, only first 32 bits need to
7013          * be checked.
7014          */
7015         mask0 = g_cfg->valid_bit_mask[0];
7016         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7017                 if (i == 0) {
7018                         /* Check if any unsupported flow type configured */
7019                         if ((mask0 | i40e_mask) ^ i40e_mask)
7020                                 goto mask_err;
7021                 } else {
7022                         if (g_cfg->valid_bit_mask[i])
7023                                 goto mask_err;
7024                 }
7025         }
7026
7027         return 0;
7028
7029 mask_err:
7030         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7031
7032         return -EINVAL;
7033 }
7034
7035 /*
7036  * Set global configurations of hash function type and symmetric hash enable
7037  * per flow type (pctype). Note any modifying global configuration will affect
7038  * all the ports on the same NIC.
7039  */
7040 static int
7041 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7042                                    struct rte_eth_hash_global_conf *g_cfg)
7043 {
7044         int ret;
7045         uint16_t i;
7046         uint32_t reg;
7047         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7048         enum i40e_filter_pctype pctype;
7049
7050         /* Check the input parameters */
7051         ret = i40e_hash_global_config_check(g_cfg);
7052         if (ret < 0)
7053                 return ret;
7054
7055         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7056                 if (!(mask0 & (1UL << i)))
7057                         continue;
7058                 mask0 &= ~(1UL << i);
7059                 /* if flowtype is invalid, continue */
7060                 if (!I40E_VALID_FLOW(i))
7061                         continue;
7062                 pctype = i40e_flowtype_to_pctype(i);
7063                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7064                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7065                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7066         }
7067
7068         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7069         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7070                 /* Toeplitz */
7071                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7072                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7073                                                                 "Toeplitz");
7074                         goto out;
7075                 }
7076                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7077         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7078                 /* Simple XOR */
7079                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7080                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7081                                                         "Simple XOR");
7082                         goto out;
7083                 }
7084                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7085         } else
7086                 /* Use the default, and keep it as it is */
7087                 goto out;
7088
7089         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7090
7091 out:
7092         I40E_WRITE_FLUSH(hw);
7093
7094         return 0;
7095 }
7096
7097 /**
7098  * Valid input sets for hash and flow director filters per PCTYPE
7099  */
7100 static uint64_t
7101 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7102                 enum rte_filter_type filter)
7103 {
7104         uint64_t valid;
7105
7106         static const uint64_t valid_hash_inset_table[] = {
7107                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7108                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7109                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7110                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7111                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7112                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7113                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7114                         I40E_INSET_FLEX_PAYLOAD,
7115                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7119                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7120                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7121                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7122                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7123                         I40E_INSET_FLEX_PAYLOAD,
7124 #ifdef X722_SUPPORT
7125                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7129                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7130                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7131                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7132                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7133                         I40E_INSET_FLEX_PAYLOAD,
7134                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7135                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7136                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7137                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7138                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7139                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7140                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7141                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7142                         I40E_INSET_FLEX_PAYLOAD,
7143 #endif
7144                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7145                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7146                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7147                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7148                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7149                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7150                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7151                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7152                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7153 #ifdef X722_SUPPORT
7154                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7158                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7159                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7160                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7161                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7162                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7163 #endif
7164                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7165                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7166                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7167                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7168                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7169                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7170                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7171                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7172                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7173                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7174                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7175                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7176                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7177                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7178                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7179                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7180                         I40E_INSET_FLEX_PAYLOAD,
7181                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7182                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7183                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7184                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7185                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7186                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7187                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7188                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7189                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7190                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7191                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7192                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7193                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7194                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7195                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7196                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7197 #ifdef X722_SUPPORT
7198                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7199                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7200                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7202                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7203                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7204                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7205                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7206                         I40E_INSET_FLEX_PAYLOAD,
7207                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7208                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7209                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7210                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7211                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7212                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7213                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7214                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7215                         I40E_INSET_FLEX_PAYLOAD,
7216 #endif
7217                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7218                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7219                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7220                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7221                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7222                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7223                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7224                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7225                         I40E_INSET_FLEX_PAYLOAD,
7226 #ifdef X722_SUPPORT
7227                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7228                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7229                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7230                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7231                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7232                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7233                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7234                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7235                         I40E_INSET_FLEX_PAYLOAD,
7236 #endif
7237                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7238                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7239                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7240                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7241                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7242                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7243                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7244                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7245                         I40E_INSET_FLEX_PAYLOAD,
7246                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7247                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7248                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7249                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7250                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7251                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7252                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7253                         I40E_INSET_FLEX_PAYLOAD,
7254                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7255                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7256                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7257                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7258                         I40E_INSET_FLEX_PAYLOAD,
7259         };
7260
7261         /**
7262          * Flow director supports only fields defined in
7263          * union rte_eth_fdir_flow.
7264          */
7265         static const uint64_t valid_fdir_inset_table[] = {
7266                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7270                 I40E_INSET_IPV4_TTL,
7271                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7276 #ifdef X722_SUPPORT
7277                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7278                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7279                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7280                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7281                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7282                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7283                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7284                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7285                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7286                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7287 #endif
7288                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7289                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7290                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7291                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7292                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7293 #ifdef X722_SUPPORT
7294                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7295                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7296                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7297                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7298                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7299 #endif
7300                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7303                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7304                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7305                 I40E_INSET_SCTP_VT,
7306                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7308                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7309                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7310                 I40E_INSET_IPV4_TTL,
7311                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7315                 I40E_INSET_IPV6_HOP_LIMIT,
7316                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7317                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7318                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7319                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7320                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7321 #ifdef X722_SUPPORT
7322                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7327                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7328                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7329                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7330                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7331                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7332 #endif
7333                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7334                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7335                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7336                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7337                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7338 #ifdef X722_SUPPORT
7339                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7340                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7341                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7342                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7343                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7344 #endif
7345                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7346                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7347                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7348                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7349                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7350                 I40E_INSET_SCTP_VT,
7351                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7352                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7353                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7354                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7355                 I40E_INSET_IPV6_HOP_LIMIT,
7356                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7357                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7358                 I40E_INSET_LAST_ETHER_TYPE,
7359         };
7360
7361         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7362                 return 0;
7363         if (filter == RTE_ETH_FILTER_HASH)
7364                 valid = valid_hash_inset_table[pctype];
7365         else
7366                 valid = valid_fdir_inset_table[pctype];
7367
7368         return valid;
7369 }
7370
7371 /**
7372  * Validate if the input set is allowed for a specific PCTYPE
7373  */
7374 static int
7375 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7376                 enum rte_filter_type filter, uint64_t inset)
7377 {
7378         uint64_t valid;
7379
7380         valid = i40e_get_valid_input_set(pctype, filter);
7381         if (inset & (~valid))
7382                 return -EINVAL;
7383
7384         return 0;
7385 }
7386
7387 /* default input set fields combination per pctype */
7388 static uint64_t
7389 i40e_get_default_input_set(uint16_t pctype)
7390 {
7391         static const uint64_t default_inset_table[] = {
7392                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7393                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7394                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7397 #ifdef X722_SUPPORT
7398                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7399                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7400                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7401                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7404 #endif
7405                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7408 #ifdef X722_SUPPORT
7409                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7410                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7412 #endif
7413                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7414                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7415                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7416                         I40E_INSET_SCTP_VT,
7417                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7418                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7419                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7420                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7421                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7424 #ifdef X722_SUPPORT
7425                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7427                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7428                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7431 #endif
7432                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7433                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7435 #ifdef X722_SUPPORT
7436                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7437                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7438                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7439 #endif
7440                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7441                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7442                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7443                         I40E_INSET_SCTP_VT,
7444                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7445                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7446                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7447                         I40E_INSET_LAST_ETHER_TYPE,
7448         };
7449
7450         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7451                 return 0;
7452
7453         return default_inset_table[pctype];
7454 }
7455
7456 /**
7457  * Parse the input set from index to logical bit masks
7458  */
7459 static int
7460 i40e_parse_input_set(uint64_t *inset,
7461                      enum i40e_filter_pctype pctype,
7462                      enum rte_eth_input_set_field *field,
7463                      uint16_t size)
7464 {
7465         uint16_t i, j;
7466         int ret = -EINVAL;
7467
7468         static const struct {
7469                 enum rte_eth_input_set_field field;
7470                 uint64_t inset;
7471         } inset_convert_table[] = {
7472                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7473                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7474                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7475                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7476                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7477                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7478                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7479                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7480                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7481                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7482                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7483                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7484                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7485                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7486                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7487                         I40E_INSET_IPV6_NEXT_HDR},
7488                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7489                         I40E_INSET_IPV6_HOP_LIMIT},
7490                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7491                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7492                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7493                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7494                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7495                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7496                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7497                         I40E_INSET_SCTP_VT},
7498                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7499                         I40E_INSET_TUNNEL_DMAC},
7500                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7501                         I40E_INSET_VLAN_TUNNEL},
7502                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7503                         I40E_INSET_TUNNEL_ID},
7504                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7505                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7506                         I40E_INSET_FLEX_PAYLOAD_W1},
7507                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7508                         I40E_INSET_FLEX_PAYLOAD_W2},
7509                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7510                         I40E_INSET_FLEX_PAYLOAD_W3},
7511                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7512                         I40E_INSET_FLEX_PAYLOAD_W4},
7513                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7514                         I40E_INSET_FLEX_PAYLOAD_W5},
7515                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7516                         I40E_INSET_FLEX_PAYLOAD_W6},
7517                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7518                         I40E_INSET_FLEX_PAYLOAD_W7},
7519                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7520                         I40E_INSET_FLEX_PAYLOAD_W8},
7521         };
7522
7523         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7524                 return ret;
7525
7526         /* Only one item allowed for default or all */
7527         if (size == 1) {
7528                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7529                         *inset = i40e_get_default_input_set(pctype);
7530                         return 0;
7531                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7532                         *inset = I40E_INSET_NONE;
7533                         return 0;
7534                 }
7535         }
7536
7537         for (i = 0, *inset = 0; i < size; i++) {
7538                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7539                         if (field[i] == inset_convert_table[j].field) {
7540                                 *inset |= inset_convert_table[j].inset;
7541                                 break;
7542                         }
7543                 }
7544
7545                 /* It contains unsupported input set, return immediately */
7546                 if (j == RTE_DIM(inset_convert_table))
7547                         return ret;
7548         }
7549
7550         return 0;
7551 }
7552
7553 /**
7554  * Translate the input set from bit masks to register aware bit masks
7555  * and vice versa
7556  */
7557 static uint64_t
7558 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7559 {
7560         uint64_t val = 0;
7561         uint16_t i;
7562
7563         struct inset_map {
7564                 uint64_t inset;
7565                 uint64_t inset_reg;
7566         };
7567
7568         static const struct inset_map inset_map_common[] = {
7569                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7570                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7571                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7572                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7573                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7574                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7575                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7576                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7577                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7578                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7579                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7580                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7581                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7582                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7583                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7584                 {I40E_INSET_TUNNEL_DMAC,
7585                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7586                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7587                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7588                 {I40E_INSET_TUNNEL_SRC_PORT,
7589                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7590                 {I40E_INSET_TUNNEL_DST_PORT,
7591                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7592                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7593                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7594                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7595                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7596                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7597                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7598                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7599                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7600                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7601         };
7602
7603     /* some different registers map in x722*/
7604         static const struct inset_map inset_map_diff_x722[] = {
7605                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7606                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7607                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7608                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7609         };
7610
7611         static const struct inset_map inset_map_diff_not_x722[] = {
7612                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7613                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7614                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7615                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7616         };
7617
7618         if (input == 0)
7619                 return val;
7620
7621         /* Translate input set to register aware inset */
7622         if (type == I40E_MAC_X722) {
7623                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7624                         if (input & inset_map_diff_x722[i].inset)
7625                                 val |= inset_map_diff_x722[i].inset_reg;
7626                 }
7627         } else {
7628                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7629                         if (input & inset_map_diff_not_x722[i].inset)
7630                                 val |= inset_map_diff_not_x722[i].inset_reg;
7631                 }
7632         }
7633
7634         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7635                 if (input & inset_map_common[i].inset)
7636                         val |= inset_map_common[i].inset_reg;
7637         }
7638
7639         return val;
7640 }
7641
7642 static int
7643 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7644 {
7645         uint8_t i, idx = 0;
7646         uint64_t inset_need_mask = inset;
7647
7648         static const struct {
7649                 uint64_t inset;
7650                 uint32_t mask;
7651         } inset_mask_map[] = {
7652                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7653                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7654                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7655                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7656                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7657                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7658                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7659                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7660         };
7661
7662         if (!inset || !mask || !nb_elem)
7663                 return 0;
7664
7665         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7666                 /* Clear the inset bit, if no MASK is required,
7667                  * for example proto + ttl
7668                  */
7669                 if ((inset & inset_mask_map[i].inset) ==
7670                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7671                         inset_need_mask &= ~inset_mask_map[i].inset;
7672                 if (!inset_need_mask)
7673                         return 0;
7674         }
7675         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7676                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7677                     inset_mask_map[i].inset) {
7678                         if (idx >= nb_elem) {
7679                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7680                                 return -EINVAL;
7681                         }
7682                         mask[idx] = inset_mask_map[i].mask;
7683                         idx++;
7684                 }
7685         }
7686
7687         return idx;
7688 }
7689
7690 static void
7691 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7692 {
7693         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7694
7695         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7696         if (reg != val)
7697                 i40e_write_rx_ctl(hw, addr, val);
7698         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7699                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7700 }
7701
7702 static void
7703 i40e_filter_input_set_init(struct i40e_pf *pf)
7704 {
7705         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7706         enum i40e_filter_pctype pctype;
7707         uint64_t input_set, inset_reg;
7708         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7709         int num, i;
7710
7711         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7712              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7713                 if (hw->mac.type == I40E_MAC_X722) {
7714                         if (!I40E_VALID_PCTYPE_X722(pctype))
7715                                 continue;
7716                 } else {
7717                         if (!I40E_VALID_PCTYPE(pctype))
7718                                 continue;
7719                 }
7720
7721                 input_set = i40e_get_default_input_set(pctype);
7722
7723                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7724                                                    I40E_INSET_MASK_NUM_REG);
7725                 if (num < 0)
7726                         return;
7727                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7728                                         input_set);
7729
7730                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7731                                       (uint32_t)(inset_reg & UINT32_MAX));
7732                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7733                                      (uint32_t)((inset_reg >>
7734                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7735                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7736                                       (uint32_t)(inset_reg & UINT32_MAX));
7737                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7738                                      (uint32_t)((inset_reg >>
7739                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7740
7741                 for (i = 0; i < num; i++) {
7742                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7743                                              mask_reg[i]);
7744                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7745                                              mask_reg[i]);
7746                 }
7747                 /*clear unused mask registers of the pctype */
7748                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7749                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7750                                              0);
7751                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7752                                              0);
7753                 }
7754                 I40E_WRITE_FLUSH(hw);
7755
7756                 /* store the default input set */
7757                 pf->hash_input_set[pctype] = input_set;
7758                 pf->fdir.input_set[pctype] = input_set;
7759         }
7760 }
7761
7762 int
7763 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7764                          struct rte_eth_input_set_conf *conf)
7765 {
7766         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7767         enum i40e_filter_pctype pctype;
7768         uint64_t input_set, inset_reg = 0;
7769         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7770         int ret, i, num;
7771
7772         if (!conf) {
7773                 PMD_DRV_LOG(ERR, "Invalid pointer");
7774                 return -EFAULT;
7775         }
7776         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7777             conf->op != RTE_ETH_INPUT_SET_ADD) {
7778                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7779                 return -EINVAL;
7780         }
7781
7782         if (!I40E_VALID_FLOW(conf->flow_type)) {
7783                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7784                 return -EINVAL;
7785         }
7786
7787         if (hw->mac.type == I40E_MAC_X722) {
7788                 /* get translated pctype value in fd pctype register */
7789                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7790                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7791                         conf->flow_type)));
7792         } else
7793                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7794
7795         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7796                                    conf->inset_size);
7797         if (ret) {
7798                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7799                 return -EINVAL;
7800         }
7801         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7802                                     input_set) != 0) {
7803                 PMD_DRV_LOG(ERR, "Invalid input set");
7804                 return -EINVAL;
7805         }
7806         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7807                 /* get inset value in register */
7808                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7809                 inset_reg <<= I40E_32_BIT_WIDTH;
7810                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7811                 input_set |= pf->hash_input_set[pctype];
7812         }
7813         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7814                                            I40E_INSET_MASK_NUM_REG);
7815         if (num < 0)
7816                 return -EINVAL;
7817
7818         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7819
7820         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7821                               (uint32_t)(inset_reg & UINT32_MAX));
7822         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7823                              (uint32_t)((inset_reg >>
7824                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7825
7826         for (i = 0; i < num; i++)
7827                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7828                                      mask_reg[i]);
7829         /*clear unused mask registers of the pctype */
7830         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7831                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7832                                      0);
7833         I40E_WRITE_FLUSH(hw);
7834
7835         pf->hash_input_set[pctype] = input_set;
7836         return 0;
7837 }
7838
7839 int
7840 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7841                          struct rte_eth_input_set_conf *conf)
7842 {
7843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7844         enum i40e_filter_pctype pctype;
7845         uint64_t input_set, inset_reg = 0;
7846         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7847         int ret, i, num;
7848
7849         if (!hw || !conf) {
7850                 PMD_DRV_LOG(ERR, "Invalid pointer");
7851                 return -EFAULT;
7852         }
7853         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7854             conf->op != RTE_ETH_INPUT_SET_ADD) {
7855                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7856                 return -EINVAL;
7857         }
7858
7859         if (!I40E_VALID_FLOW(conf->flow_type)) {
7860                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7861                 return -EINVAL;
7862         }
7863
7864         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7865
7866         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7867                                    conf->inset_size);
7868         if (ret) {
7869                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7870                 return -EINVAL;
7871         }
7872         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7873                                     input_set) != 0) {
7874                 PMD_DRV_LOG(ERR, "Invalid input set");
7875                 return -EINVAL;
7876         }
7877
7878         /* get inset value in register */
7879         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7880         inset_reg <<= I40E_32_BIT_WIDTH;
7881         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7882
7883         /* Can not change the inset reg for flex payload for fdir,
7884          * it is done by writing I40E_PRTQF_FD_FLXINSET
7885          * in i40e_set_flex_mask_on_pctype.
7886          */
7887         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7888                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7889         else
7890                 input_set |= pf->fdir.input_set[pctype];
7891         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7892                                            I40E_INSET_MASK_NUM_REG);
7893         if (num < 0)
7894                 return -EINVAL;
7895
7896         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7897
7898         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7899                               (uint32_t)(inset_reg & UINT32_MAX));
7900         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7901                              (uint32_t)((inset_reg >>
7902                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7903
7904         for (i = 0; i < num; i++)
7905                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7906                                      mask_reg[i]);
7907         /*clear unused mask registers of the pctype */
7908         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7909                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7910                                      0);
7911         I40E_WRITE_FLUSH(hw);
7912
7913         pf->fdir.input_set[pctype] = input_set;
7914         return 0;
7915 }
7916
7917 static int
7918 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7919 {
7920         int ret = 0;
7921
7922         if (!hw || !info) {
7923                 PMD_DRV_LOG(ERR, "Invalid pointer");
7924                 return -EFAULT;
7925         }
7926
7927         switch (info->info_type) {
7928         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7929                 i40e_get_symmetric_hash_enable_per_port(hw,
7930                                         &(info->info.enable));
7931                 break;
7932         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7933                 ret = i40e_get_hash_filter_global_config(hw,
7934                                 &(info->info.global_conf));
7935                 break;
7936         default:
7937                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7938                                                         info->info_type);
7939                 ret = -EINVAL;
7940                 break;
7941         }
7942
7943         return ret;
7944 }
7945
7946 static int
7947 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7948 {
7949         int ret = 0;
7950
7951         if (!hw || !info) {
7952                 PMD_DRV_LOG(ERR, "Invalid pointer");
7953                 return -EFAULT;
7954         }
7955
7956         switch (info->info_type) {
7957         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7958                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7959                 break;
7960         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7961                 ret = i40e_set_hash_filter_global_config(hw,
7962                                 &(info->info.global_conf));
7963                 break;
7964         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7965                 ret = i40e_hash_filter_inset_select(hw,
7966                                                &(info->info.input_set_conf));
7967                 break;
7968
7969         default:
7970                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7971                                                         info->info_type);
7972                 ret = -EINVAL;
7973                 break;
7974         }
7975
7976         return ret;
7977 }
7978
7979 /* Operations for hash function */
7980 static int
7981 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7982                       enum rte_filter_op filter_op,
7983                       void *arg)
7984 {
7985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7986         int ret = 0;
7987
7988         switch (filter_op) {
7989         case RTE_ETH_FILTER_NOP:
7990                 break;
7991         case RTE_ETH_FILTER_GET:
7992                 ret = i40e_hash_filter_get(hw,
7993                         (struct rte_eth_hash_filter_info *)arg);
7994                 break;
7995         case RTE_ETH_FILTER_SET:
7996                 ret = i40e_hash_filter_set(hw,
7997                         (struct rte_eth_hash_filter_info *)arg);
7998                 break;
7999         default:
8000                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8001                                                                 filter_op);
8002                 ret = -ENOTSUP;
8003                 break;
8004         }
8005
8006         return ret;
8007 }
8008
8009 /*
8010  * Configure ethertype filter, which can director packet by filtering
8011  * with mac address and ether_type or only ether_type
8012  */
8013 static int
8014 i40e_ethertype_filter_set(struct i40e_pf *pf,
8015                         struct rte_eth_ethertype_filter *filter,
8016                         bool add)
8017 {
8018         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8019         struct i40e_control_filter_stats stats;
8020         uint16_t flags = 0;
8021         int ret;
8022
8023         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8024                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8025                 return -EINVAL;
8026         }
8027         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8028                 filter->ether_type == ETHER_TYPE_IPv6) {
8029                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8030                         " control packet filter.", filter->ether_type);
8031                 return -EINVAL;
8032         }
8033         if (filter->ether_type == ETHER_TYPE_VLAN)
8034                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8035                         " not supported.");
8036
8037         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8038                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8039         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8040                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8041         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8042
8043         memset(&stats, 0, sizeof(stats));
8044         ret = i40e_aq_add_rem_control_packet_filter(hw,
8045                         filter->mac_addr.addr_bytes,
8046                         filter->ether_type, flags,
8047                         pf->main_vsi->seid,
8048                         filter->queue, add, &stats, NULL);
8049
8050         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8051                          " mac_etype_used = %u, etype_used = %u,"
8052                          " mac_etype_free = %u, etype_free = %u\n",
8053                          ret, stats.mac_etype_used, stats.etype_used,
8054                          stats.mac_etype_free, stats.etype_free);
8055         if (ret < 0)
8056                 return -ENOSYS;
8057         return 0;
8058 }
8059
8060 /*
8061  * Handle operations for ethertype filter.
8062  */
8063 static int
8064 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8065                                 enum rte_filter_op filter_op,
8066                                 void *arg)
8067 {
8068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8069         int ret = 0;
8070
8071         if (filter_op == RTE_ETH_FILTER_NOP)
8072                 return ret;
8073
8074         if (arg == NULL) {
8075                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8076                             filter_op);
8077                 return -EINVAL;
8078         }
8079
8080         switch (filter_op) {
8081         case RTE_ETH_FILTER_ADD:
8082                 ret = i40e_ethertype_filter_set(pf,
8083                         (struct rte_eth_ethertype_filter *)arg,
8084                         TRUE);
8085                 break;
8086         case RTE_ETH_FILTER_DELETE:
8087                 ret = i40e_ethertype_filter_set(pf,
8088                         (struct rte_eth_ethertype_filter *)arg,
8089                         FALSE);
8090                 break;
8091         default:
8092                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8093                 ret = -ENOSYS;
8094                 break;
8095         }
8096         return ret;
8097 }
8098
8099 static int
8100 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8101                      enum rte_filter_type filter_type,
8102                      enum rte_filter_op filter_op,
8103                      void *arg)
8104 {
8105         int ret = 0;
8106
8107         if (dev == NULL)
8108                 return -EINVAL;
8109
8110         switch (filter_type) {
8111         case RTE_ETH_FILTER_NONE:
8112                 /* For global configuration */
8113                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8114                 break;
8115         case RTE_ETH_FILTER_HASH:
8116                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8117                 break;
8118         case RTE_ETH_FILTER_MACVLAN:
8119                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8120                 break;
8121         case RTE_ETH_FILTER_ETHERTYPE:
8122                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8123                 break;
8124         case RTE_ETH_FILTER_TUNNEL:
8125                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8126                 break;
8127         case RTE_ETH_FILTER_FDIR:
8128                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8129                 break;
8130         default:
8131                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8132                                                         filter_type);
8133                 ret = -EINVAL;
8134                 break;
8135         }
8136
8137         return ret;
8138 }
8139
8140 /*
8141  * Check and enable Extended Tag.
8142  * Enabling Extended Tag is important for 40G performance.
8143  */
8144 static void
8145 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8146 {
8147         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8148         uint32_t buf = 0;
8149         int ret;
8150
8151         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8152                                       PCI_DEV_CAP_REG);
8153         if (ret < 0) {
8154                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8155                             PCI_DEV_CAP_REG);
8156                 return;
8157         }
8158         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8159                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8160                 return;
8161         }
8162
8163         buf = 0;
8164         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8165                                       PCI_DEV_CTRL_REG);
8166         if (ret < 0) {
8167                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8168                             PCI_DEV_CTRL_REG);
8169                 return;
8170         }
8171         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8172                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8173                 return;
8174         }
8175         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8176         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8177                                        PCI_DEV_CTRL_REG);
8178         if (ret < 0) {
8179                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8180                             PCI_DEV_CTRL_REG);
8181                 return;
8182         }
8183 }
8184
8185 /*
8186  * As some registers wouldn't be reset unless a global hardware reset,
8187  * hardware initialization is needed to put those registers into an
8188  * expected initial state.
8189  */
8190 static void
8191 i40e_hw_init(struct rte_eth_dev *dev)
8192 {
8193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8194
8195         i40e_enable_extended_tag(dev);
8196
8197         /* clear the PF Queue Filter control register */
8198         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8199
8200         /* Disable symmetric hash per port */
8201         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8202 }
8203
8204 enum i40e_filter_pctype
8205 i40e_flowtype_to_pctype(uint16_t flow_type)
8206 {
8207         static const enum i40e_filter_pctype pctype_table[] = {
8208                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8209                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8210                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8211                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8212                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8213                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8214                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8215                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8216                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8217                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8218                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8219                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8220                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8221                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8222                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8223                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8224                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8225                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8226                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8227         };
8228
8229         return pctype_table[flow_type];
8230 }
8231
8232 uint16_t
8233 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8234 {
8235         static const uint16_t flowtype_table[] = {
8236                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8237                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8238                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8239 #ifdef X722_SUPPORT
8240                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8241                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8242                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8243                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8244 #endif
8245                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8246                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8247 #ifdef X722_SUPPORT
8248                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8249                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8250 #endif
8251                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8252                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8253                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8254                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8255                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8256                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8257                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8258 #ifdef X722_SUPPORT
8259                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8260                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8261                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8262                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8263 #endif
8264                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8265                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8266 #ifdef X722_SUPPORT
8267                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8268                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8269 #endif
8270                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8271                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8272                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8273                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8274                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8275         };
8276
8277         return flowtype_table[pctype];
8278 }
8279
8280 /*
8281  * On X710, performance number is far from the expectation on recent firmware
8282  * versions; on XL710, performance number is also far from the expectation on
8283  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8284  * mode is enabled and port MAC address is equal to the packet destination MAC
8285  * address. The fix for this issue may not be integrated in the following
8286  * firmware version. So the workaround in software driver is needed. It needs
8287  * to modify the initial values of 3 internal only registers for both X710 and
8288  * XL710. Note that the values for X710 or XL710 could be different, and the
8289  * workaround can be removed when it is fixed in firmware in the future.
8290  */
8291
8292 /* For both X710 and XL710 */
8293 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8294 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8295
8296 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8297 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8298
8299 /* For X710 */
8300 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8301 /* For XL710 */
8302 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8303 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8304
8305 static int
8306 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8307 {
8308         enum i40e_status_code status;
8309         struct i40e_aq_get_phy_abilities_resp phy_ab;
8310         int ret = -ENOTSUP;
8311
8312         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8313                                               NULL);
8314
8315         if (status)
8316                 return ret;
8317
8318         return 0;
8319 }
8320
8321
8322 static void
8323 i40e_configure_registers(struct i40e_hw *hw)
8324 {
8325         static struct {
8326                 uint32_t addr;
8327                 uint64_t val;
8328         } reg_table[] = {
8329                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8330                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8331                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8332         };
8333         uint64_t reg;
8334         uint32_t i;
8335         int ret;
8336
8337         for (i = 0; i < RTE_DIM(reg_table); i++) {
8338                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8339                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8340                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8341                                 reg_table[i].val =
8342                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8343                         else /* For X710 */
8344                                 reg_table[i].val =
8345                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8346                 }
8347
8348                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8349                                                         &reg, NULL);
8350                 if (ret < 0) {
8351                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8352                                                         reg_table[i].addr);
8353                         break;
8354                 }
8355                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8356                                                 reg_table[i].addr, reg);
8357                 if (reg == reg_table[i].val)
8358                         continue;
8359
8360                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8361                                                 reg_table[i].val, NULL);
8362                 if (ret < 0) {
8363                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8364                                 "address of 0x%"PRIx32, reg_table[i].val,
8365                                                         reg_table[i].addr);
8366                         break;
8367                 }
8368                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8369                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8370         }
8371 }
8372
8373 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8374 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8375 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8376 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8377 static int
8378 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8379 {
8380         uint32_t reg;
8381         int ret;
8382
8383         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8384                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8385                 return -EINVAL;
8386         }
8387
8388         /* Configure for double VLAN RX stripping */
8389         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8390         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8391                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8392                 ret = i40e_aq_debug_write_register(hw,
8393                                                    I40E_VSI_TSR(vsi->vsi_id),
8394                                                    reg, NULL);
8395                 if (ret < 0) {
8396                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8397                                     vsi->vsi_id);
8398                         return I40E_ERR_CONFIG;
8399                 }
8400         }
8401
8402         /* Configure for double VLAN TX insertion */
8403         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8404         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8405                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8406                 ret = i40e_aq_debug_write_register(hw,
8407                                                    I40E_VSI_L2TAGSTXVALID(
8408                                                    vsi->vsi_id), reg, NULL);
8409                 if (ret < 0) {
8410                         PMD_DRV_LOG(ERR, "Failed to update "
8411                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8412                         return I40E_ERR_CONFIG;
8413                 }
8414         }
8415
8416         return 0;
8417 }
8418
8419 /**
8420  * i40e_aq_add_mirror_rule
8421  * @hw: pointer to the hardware structure
8422  * @seid: VEB seid to add mirror rule to
8423  * @dst_id: destination vsi seid
8424  * @entries: Buffer which contains the entities to be mirrored
8425  * @count: number of entities contained in the buffer
8426  * @rule_id:the rule_id of the rule to be added
8427  *
8428  * Add a mirror rule for a given veb.
8429  *
8430  **/
8431 static enum i40e_status_code
8432 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8433                         uint16_t seid, uint16_t dst_id,
8434                         uint16_t rule_type, uint16_t *entries,
8435                         uint16_t count, uint16_t *rule_id)
8436 {
8437         struct i40e_aq_desc desc;
8438         struct i40e_aqc_add_delete_mirror_rule cmd;
8439         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8440                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8441                 &desc.params.raw;
8442         uint16_t buff_len;
8443         enum i40e_status_code status;
8444
8445         i40e_fill_default_direct_cmd_desc(&desc,
8446                                           i40e_aqc_opc_add_mirror_rule);
8447         memset(&cmd, 0, sizeof(cmd));
8448
8449         buff_len = sizeof(uint16_t) * count;
8450         desc.datalen = rte_cpu_to_le_16(buff_len);
8451         if (buff_len > 0)
8452                 desc.flags |= rte_cpu_to_le_16(
8453                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8454         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8455                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8456         cmd.num_entries = rte_cpu_to_le_16(count);
8457         cmd.seid = rte_cpu_to_le_16(seid);
8458         cmd.destination = rte_cpu_to_le_16(dst_id);
8459
8460         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8461         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8462         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8463                          "rule_id = %u"
8464                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8465                          hw->aq.asq_last_status, resp->rule_id,
8466                          resp->mirror_rules_used, resp->mirror_rules_free);
8467         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8468
8469         return status;
8470 }
8471
8472 /**
8473  * i40e_aq_del_mirror_rule
8474  * @hw: pointer to the hardware structure
8475  * @seid: VEB seid to add mirror rule to
8476  * @entries: Buffer which contains the entities to be mirrored
8477  * @count: number of entities contained in the buffer
8478  * @rule_id:the rule_id of the rule to be delete
8479  *
8480  * Delete a mirror rule for a given veb.
8481  *
8482  **/
8483 static enum i40e_status_code
8484 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8485                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8486                 uint16_t count, uint16_t rule_id)
8487 {
8488         struct i40e_aq_desc desc;
8489         struct i40e_aqc_add_delete_mirror_rule cmd;
8490         uint16_t buff_len = 0;
8491         enum i40e_status_code status;
8492         void *buff = NULL;
8493
8494         i40e_fill_default_direct_cmd_desc(&desc,
8495                                           i40e_aqc_opc_delete_mirror_rule);
8496         memset(&cmd, 0, sizeof(cmd));
8497         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8498                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8499                                                           I40E_AQ_FLAG_RD));
8500                 cmd.num_entries = count;
8501                 buff_len = sizeof(uint16_t) * count;
8502                 desc.datalen = rte_cpu_to_le_16(buff_len);
8503                 buff = (void *)entries;
8504         } else
8505                 /* rule id is filled in destination field for deleting mirror rule */
8506                 cmd.destination = rte_cpu_to_le_16(rule_id);
8507
8508         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8509                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8510         cmd.seid = rte_cpu_to_le_16(seid);
8511
8512         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8513         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8514
8515         return status;
8516 }
8517
8518 /**
8519  * i40e_mirror_rule_set
8520  * @dev: pointer to the hardware structure
8521  * @mirror_conf: mirror rule info
8522  * @sw_id: mirror rule's sw_id
8523  * @on: enable/disable
8524  *
8525  * set a mirror rule.
8526  *
8527  **/
8528 static int
8529 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8530                         struct rte_eth_mirror_conf *mirror_conf,
8531                         uint8_t sw_id, uint8_t on)
8532 {
8533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8535         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8536         struct i40e_mirror_rule *parent = NULL;
8537         uint16_t seid, dst_seid, rule_id;
8538         uint16_t i, j = 0;
8539         int ret;
8540
8541         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8542
8543         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8544                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8545                         " without veb or vfs.");
8546                 return -ENOSYS;
8547         }
8548         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8549                 PMD_DRV_LOG(ERR, "mirror table is full.");
8550                 return -ENOSPC;
8551         }
8552         if (mirror_conf->dst_pool > pf->vf_num) {
8553                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8554                                  mirror_conf->dst_pool);
8555                 return -EINVAL;
8556         }
8557
8558         seid = pf->main_vsi->veb->seid;
8559
8560         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8561                 if (sw_id <= it->index) {
8562                         mirr_rule = it;
8563                         break;
8564                 }
8565                 parent = it;
8566         }
8567         if (mirr_rule && sw_id == mirr_rule->index) {
8568                 if (on) {
8569                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8570                         return -EEXIST;
8571                 } else {
8572                         ret = i40e_aq_del_mirror_rule(hw, seid,
8573                                         mirr_rule->rule_type,
8574                                         mirr_rule->entries,
8575                                         mirr_rule->num_entries, mirr_rule->id);
8576                         if (ret < 0) {
8577                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8578                                                    " ret = %d, aq_err = %d.",
8579                                                    ret, hw->aq.asq_last_status);
8580                                 return -ENOSYS;
8581                         }
8582                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8583                         rte_free(mirr_rule);
8584                         pf->nb_mirror_rule--;
8585                         return 0;
8586                 }
8587         } else if (!on) {
8588                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8589                 return -ENOENT;
8590         }
8591
8592         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8593                                 sizeof(struct i40e_mirror_rule) , 0);
8594         if (!mirr_rule) {
8595                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8596                 return I40E_ERR_NO_MEMORY;
8597         }
8598         switch (mirror_conf->rule_type) {
8599         case ETH_MIRROR_VLAN:
8600                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8601                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8602                                 mirr_rule->entries[j] =
8603                                         mirror_conf->vlan.vlan_id[i];
8604                                 j++;
8605                         }
8606                 }
8607                 if (j == 0) {
8608                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8609                         rte_free(mirr_rule);
8610                         return -EINVAL;
8611                 }
8612                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8613                 break;
8614         case ETH_MIRROR_VIRTUAL_POOL_UP:
8615         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8616                 /* check if the specified pool bit is out of range */
8617                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8618                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8619                         rte_free(mirr_rule);
8620                         return -EINVAL;
8621                 }
8622                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8623                         if (mirror_conf->pool_mask & (1ULL << i)) {
8624                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8625                                 j++;
8626                         }
8627                 }
8628                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8629                         /* add pf vsi to entries */
8630                         mirr_rule->entries[j] = pf->main_vsi_seid;
8631                         j++;
8632                 }
8633                 if (j == 0) {
8634                         PMD_DRV_LOG(ERR, "pool is not specified.");
8635                         rte_free(mirr_rule);
8636                         return -EINVAL;
8637                 }
8638                 /* egress and ingress in aq commands means from switch but not port */
8639                 mirr_rule->rule_type =
8640                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8641                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8642                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8643                 break;
8644         case ETH_MIRROR_UPLINK_PORT:
8645                 /* egress and ingress in aq commands means from switch but not port*/
8646                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8647                 break;
8648         case ETH_MIRROR_DOWNLINK_PORT:
8649                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8650                 break;
8651         default:
8652                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8653                         mirror_conf->rule_type);
8654                 rte_free(mirr_rule);
8655                 return -EINVAL;
8656         }
8657
8658         /* If the dst_pool is equal to vf_num, consider it as PF */
8659         if (mirror_conf->dst_pool == pf->vf_num)
8660                 dst_seid = pf->main_vsi_seid;
8661         else
8662                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8663
8664         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8665                                       mirr_rule->rule_type, mirr_rule->entries,
8666                                       j, &rule_id);
8667         if (ret < 0) {
8668                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8669                                    " ret = %d, aq_err = %d.",
8670                                    ret, hw->aq.asq_last_status);
8671                 rte_free(mirr_rule);
8672                 return -ENOSYS;
8673         }
8674
8675         mirr_rule->index = sw_id;
8676         mirr_rule->num_entries = j;
8677         mirr_rule->id = rule_id;
8678         mirr_rule->dst_vsi_seid = dst_seid;
8679
8680         if (parent)
8681                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8682         else
8683                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8684
8685         pf->nb_mirror_rule++;
8686         return 0;
8687 }
8688
8689 /**
8690  * i40e_mirror_rule_reset
8691  * @dev: pointer to the device
8692  * @sw_id: mirror rule's sw_id
8693  *
8694  * reset a mirror rule.
8695  *
8696  **/
8697 static int
8698 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8699 {
8700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8702         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8703         uint16_t seid;
8704         int ret;
8705
8706         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8707
8708         seid = pf->main_vsi->veb->seid;
8709
8710         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8711                 if (sw_id == it->index) {
8712                         mirr_rule = it;
8713                         break;
8714                 }
8715         }
8716         if (mirr_rule) {
8717                 ret = i40e_aq_del_mirror_rule(hw, seid,
8718                                 mirr_rule->rule_type,
8719                                 mirr_rule->entries,
8720                                 mirr_rule->num_entries, mirr_rule->id);
8721                 if (ret < 0) {
8722                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8723                                            " status = %d, aq_err = %d.",
8724                                            ret, hw->aq.asq_last_status);
8725                         return -ENOSYS;
8726                 }
8727                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8728                 rte_free(mirr_rule);
8729                 pf->nb_mirror_rule--;
8730         } else {
8731                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8732                 return -ENOENT;
8733         }
8734         return 0;
8735 }
8736
8737 static uint64_t
8738 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8739 {
8740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8741         uint64_t systim_cycles;
8742
8743         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8744         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8745                         << 32;
8746
8747         return systim_cycles;
8748 }
8749
8750 static uint64_t
8751 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8752 {
8753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8754         uint64_t rx_tstamp;
8755
8756         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8757         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8758                         << 32;
8759
8760         return rx_tstamp;
8761 }
8762
8763 static uint64_t
8764 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8765 {
8766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8767         uint64_t tx_tstamp;
8768
8769         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8770         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8771                         << 32;
8772
8773         return tx_tstamp;
8774 }
8775
8776 static void
8777 i40e_start_timecounters(struct rte_eth_dev *dev)
8778 {
8779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8780         struct i40e_adapter *adapter =
8781                         (struct i40e_adapter *)dev->data->dev_private;
8782         struct rte_eth_link link;
8783         uint32_t tsync_inc_l;
8784         uint32_t tsync_inc_h;
8785
8786         /* Get current link speed. */
8787         memset(&link, 0, sizeof(link));
8788         i40e_dev_link_update(dev, 1);
8789         rte_i40e_dev_atomic_read_link_status(dev, &link);
8790
8791         switch (link.link_speed) {
8792         case ETH_SPEED_NUM_40G:
8793                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8794                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8795                 break;
8796         case ETH_SPEED_NUM_10G:
8797                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8798                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8799                 break;
8800         case ETH_SPEED_NUM_1G:
8801                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8802                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8803                 break;
8804         default:
8805                 tsync_inc_l = 0x0;
8806                 tsync_inc_h = 0x0;
8807         }
8808
8809         /* Set the timesync increment value. */
8810         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8811         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8812
8813         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8814         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8815         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8816
8817         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8818         adapter->systime_tc.cc_shift = 0;
8819         adapter->systime_tc.nsec_mask = 0;
8820
8821         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8822         adapter->rx_tstamp_tc.cc_shift = 0;
8823         adapter->rx_tstamp_tc.nsec_mask = 0;
8824
8825         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8826         adapter->tx_tstamp_tc.cc_shift = 0;
8827         adapter->tx_tstamp_tc.nsec_mask = 0;
8828 }
8829
8830 static int
8831 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8832 {
8833         struct i40e_adapter *adapter =
8834                         (struct i40e_adapter *)dev->data->dev_private;
8835
8836         adapter->systime_tc.nsec += delta;
8837         adapter->rx_tstamp_tc.nsec += delta;
8838         adapter->tx_tstamp_tc.nsec += delta;
8839
8840         return 0;
8841 }
8842
8843 static int
8844 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8845 {
8846         uint64_t ns;
8847         struct i40e_adapter *adapter =
8848                         (struct i40e_adapter *)dev->data->dev_private;
8849
8850         ns = rte_timespec_to_ns(ts);
8851
8852         /* Set the timecounters to a new value. */
8853         adapter->systime_tc.nsec = ns;
8854         adapter->rx_tstamp_tc.nsec = ns;
8855         adapter->tx_tstamp_tc.nsec = ns;
8856
8857         return 0;
8858 }
8859
8860 static int
8861 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8862 {
8863         uint64_t ns, systime_cycles;
8864         struct i40e_adapter *adapter =
8865                         (struct i40e_adapter *)dev->data->dev_private;
8866
8867         systime_cycles = i40e_read_systime_cyclecounter(dev);
8868         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8869         *ts = rte_ns_to_timespec(ns);
8870
8871         return 0;
8872 }
8873
8874 static int
8875 i40e_timesync_enable(struct rte_eth_dev *dev)
8876 {
8877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8878         uint32_t tsync_ctl_l;
8879         uint32_t tsync_ctl_h;
8880
8881         /* Stop the timesync system time. */
8882         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8883         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8884         /* Reset the timesync system time value. */
8885         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8886         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8887
8888         i40e_start_timecounters(dev);
8889
8890         /* Clear timesync registers. */
8891         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8892         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8893         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8894         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8895         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8896         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8897
8898         /* Enable timestamping of PTP packets. */
8899         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8900         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8901
8902         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8903         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8904         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8905
8906         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8907         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8908
8909         return 0;
8910 }
8911
8912 static int
8913 i40e_timesync_disable(struct rte_eth_dev *dev)
8914 {
8915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8916         uint32_t tsync_ctl_l;
8917         uint32_t tsync_ctl_h;
8918
8919         /* Disable timestamping of transmitted PTP packets. */
8920         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8921         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8922
8923         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8924         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8925
8926         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8927         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8928
8929         /* Reset the timesync increment value. */
8930         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8931         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8932
8933         return 0;
8934 }
8935
8936 static int
8937 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8938                                 struct timespec *timestamp, uint32_t flags)
8939 {
8940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8941         struct i40e_adapter *adapter =
8942                 (struct i40e_adapter *)dev->data->dev_private;
8943
8944         uint32_t sync_status;
8945         uint32_t index = flags & 0x03;
8946         uint64_t rx_tstamp_cycles;
8947         uint64_t ns;
8948
8949         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8950         if ((sync_status & (1 << index)) == 0)
8951                 return -EINVAL;
8952
8953         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8954         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8955         *timestamp = rte_ns_to_timespec(ns);
8956
8957         return 0;
8958 }
8959
8960 static int
8961 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8962                                 struct timespec *timestamp)
8963 {
8964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8965         struct i40e_adapter *adapter =
8966                 (struct i40e_adapter *)dev->data->dev_private;
8967
8968         uint32_t sync_status;
8969         uint64_t tx_tstamp_cycles;
8970         uint64_t ns;
8971
8972         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8973         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8974                 return -EINVAL;
8975
8976         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8977         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8978         *timestamp = rte_ns_to_timespec(ns);
8979
8980         return 0;
8981 }
8982
8983 /*
8984  * i40e_parse_dcb_configure - parse dcb configure from user
8985  * @dev: the device being configured
8986  * @dcb_cfg: pointer of the result of parse
8987  * @*tc_map: bit map of enabled traffic classes
8988  *
8989  * Returns 0 on success, negative value on failure
8990  */
8991 static int
8992 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8993                          struct i40e_dcbx_config *dcb_cfg,
8994                          uint8_t *tc_map)
8995 {
8996         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8997         uint8_t i, tc_bw, bw_lf;
8998
8999         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9000
9001         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9002         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9003                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9004                 return -EINVAL;
9005         }
9006
9007         /* assume each tc has the same bw */
9008         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9009         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9010                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9011         /* to ensure the sum of tcbw is equal to 100 */
9012         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9013         for (i = 0; i < bw_lf; i++)
9014                 dcb_cfg->etscfg.tcbwtable[i]++;
9015
9016         /* assume each tc has the same Transmission Selection Algorithm */
9017         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9018                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9019
9020         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9021                 dcb_cfg->etscfg.prioritytable[i] =
9022                                 dcb_rx_conf->dcb_tc[i];
9023
9024         /* FW needs one App to configure HW */
9025         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9026         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9027         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9028         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9029
9030         if (dcb_rx_conf->nb_tcs == 0)
9031                 *tc_map = 1; /* tc0 only */
9032         else
9033                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9034
9035         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9036                 dcb_cfg->pfc.willing = 0;
9037                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9038                 dcb_cfg->pfc.pfcenable = *tc_map;
9039         }
9040         return 0;
9041 }
9042
9043
9044 static enum i40e_status_code
9045 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9046                               struct i40e_aqc_vsi_properties_data *info,
9047                               uint8_t enabled_tcmap)
9048 {
9049         enum i40e_status_code ret;
9050         int i, total_tc = 0;
9051         uint16_t qpnum_per_tc, bsf, qp_idx;
9052         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9054         uint16_t used_queues;
9055
9056         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9057         if (ret != I40E_SUCCESS)
9058                 return ret;
9059
9060         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9061                 if (enabled_tcmap & (1 << i))
9062                         total_tc++;
9063         }
9064         if (total_tc == 0)
9065                 total_tc = 1;
9066         vsi->enabled_tc = enabled_tcmap;
9067
9068         /* different VSI has different queues assigned */
9069         if (vsi->type == I40E_VSI_MAIN)
9070                 used_queues = dev_data->nb_rx_queues -
9071                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9072         else if (vsi->type == I40E_VSI_VMDQ2)
9073                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9074         else {
9075                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9076                 return I40E_ERR_NO_AVAILABLE_VSI;
9077         }
9078
9079         qpnum_per_tc = used_queues / total_tc;
9080         /* Number of queues per enabled TC */
9081         if (qpnum_per_tc == 0) {
9082                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9083                 return I40E_ERR_INVALID_QP_ID;
9084         }
9085         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9086                                 I40E_MAX_Q_PER_TC);
9087         bsf = rte_bsf32(qpnum_per_tc);
9088
9089         /**
9090          * Configure TC and queue mapping parameters, for enabled TC,
9091          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9092          * default queue will serve it.
9093          */
9094         qp_idx = 0;
9095         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9096                 if (vsi->enabled_tc & (1 << i)) {
9097                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9098                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9099                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9100                         qp_idx += qpnum_per_tc;
9101                 } else
9102                         info->tc_mapping[i] = 0;
9103         }
9104
9105         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9106         if (vsi->type == I40E_VSI_SRIOV) {
9107                 info->mapping_flags |=
9108                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9109                 for (i = 0; i < vsi->nb_qps; i++)
9110                         info->queue_mapping[i] =
9111                                 rte_cpu_to_le_16(vsi->base_queue + i);
9112         } else {
9113                 info->mapping_flags |=
9114                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9115                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9116         }
9117         info->valid_sections |=
9118                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9119
9120         return I40E_SUCCESS;
9121 }
9122
9123 /*
9124  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9125  * @veb: VEB to be configured
9126  * @tc_map: enabled TC bitmap
9127  *
9128  * Returns 0 on success, negative value on failure
9129  */
9130 static enum i40e_status_code
9131 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9132 {
9133         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9134         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9135         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9136         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9137         enum i40e_status_code ret = I40E_SUCCESS;
9138         int i;
9139         uint32_t bw_max;
9140
9141         /* Check if enabled_tc is same as existing or new TCs */
9142         if (veb->enabled_tc == tc_map)
9143                 return ret;
9144
9145         /* configure tc bandwidth */
9146         memset(&veb_bw, 0, sizeof(veb_bw));
9147         veb_bw.tc_valid_bits = tc_map;
9148         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9149         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9150                 if (tc_map & BIT_ULL(i))
9151                         veb_bw.tc_bw_share_credits[i] = 1;
9152         }
9153         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9154                                                    &veb_bw, NULL);
9155         if (ret) {
9156                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9157                                   " per TC failed = %d",
9158                                   hw->aq.asq_last_status);
9159                 return ret;
9160         }
9161
9162         memset(&ets_query, 0, sizeof(ets_query));
9163         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9164                                                    &ets_query, NULL);
9165         if (ret != I40E_SUCCESS) {
9166                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9167                                  " configuration %u", hw->aq.asq_last_status);
9168                 return ret;
9169         }
9170         memset(&bw_query, 0, sizeof(bw_query));
9171         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9172                                                   &bw_query, NULL);
9173         if (ret != I40E_SUCCESS) {
9174                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9175                                  " configuration %u", hw->aq.asq_last_status);
9176                 return ret;
9177         }
9178
9179         /* store and print out BW info */
9180         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9181         veb->bw_info.bw_max = ets_query.tc_bw_max;
9182         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9183         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9184         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9185                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9186                      I40E_16_BIT_WIDTH);
9187         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9188                 veb->bw_info.bw_ets_share_credits[i] =
9189                                 bw_query.tc_bw_share_credits[i];
9190                 veb->bw_info.bw_ets_credits[i] =
9191                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9192                 /* 4 bits per TC, 4th bit is reserved */
9193                 veb->bw_info.bw_ets_max[i] =
9194                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9195                                   RTE_LEN2MASK(3, uint8_t));
9196                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9197                             veb->bw_info.bw_ets_share_credits[i]);
9198                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9199                             veb->bw_info.bw_ets_credits[i]);
9200                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9201                             veb->bw_info.bw_ets_max[i]);
9202         }
9203
9204         veb->enabled_tc = tc_map;
9205
9206         return ret;
9207 }
9208
9209
9210 /*
9211  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9212  * @vsi: VSI to be configured
9213  * @tc_map: enabled TC bitmap
9214  *
9215  * Returns 0 on success, negative value on failure
9216  */
9217 static enum i40e_status_code
9218 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9219 {
9220         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9221         struct i40e_vsi_context ctxt;
9222         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9223         enum i40e_status_code ret = I40E_SUCCESS;
9224         int i;
9225
9226         /* Check if enabled_tc is same as existing or new TCs */
9227         if (vsi->enabled_tc == tc_map)
9228                 return ret;
9229
9230         /* configure tc bandwidth */
9231         memset(&bw_data, 0, sizeof(bw_data));
9232         bw_data.tc_valid_bits = tc_map;
9233         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9234         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9235                 if (tc_map & BIT_ULL(i))
9236                         bw_data.tc_bw_credits[i] = 1;
9237         }
9238         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9239         if (ret) {
9240                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9241                         " per TC failed = %d",
9242                         hw->aq.asq_last_status);
9243                 goto out;
9244         }
9245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9246                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9247
9248         /* Update Queue Pairs Mapping for currently enabled UPs */
9249         ctxt.seid = vsi->seid;
9250         ctxt.pf_num = hw->pf_id;
9251         ctxt.vf_num = 0;
9252         ctxt.uplink_seid = vsi->uplink_seid;
9253         ctxt.info = vsi->info;
9254         i40e_get_cap(hw);
9255         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9256         if (ret)
9257                 goto out;
9258
9259         /* Update the VSI after updating the VSI queue-mapping information */
9260         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9261         if (ret) {
9262                 PMD_INIT_LOG(ERR, "Failed to configure "
9263                             "TC queue mapping = %d",
9264                             hw->aq.asq_last_status);
9265                 goto out;
9266         }
9267         /* update the local VSI info with updated queue map */
9268         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9269                                         sizeof(vsi->info.tc_mapping));
9270         (void)rte_memcpy(&vsi->info.queue_mapping,
9271                         &ctxt.info.queue_mapping,
9272                 sizeof(vsi->info.queue_mapping));
9273         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9274         vsi->info.valid_sections = 0;
9275
9276         /* query and update current VSI BW information */
9277         ret = i40e_vsi_get_bw_config(vsi);
9278         if (ret) {
9279                 PMD_INIT_LOG(ERR,
9280                          "Failed updating vsi bw info, err %s aq_err %s",
9281                          i40e_stat_str(hw, ret),
9282                          i40e_aq_str(hw, hw->aq.asq_last_status));
9283                 goto out;
9284         }
9285
9286         vsi->enabled_tc = tc_map;
9287
9288 out:
9289         return ret;
9290 }
9291
9292 /*
9293  * i40e_dcb_hw_configure - program the dcb setting to hw
9294  * @pf: pf the configuration is taken on
9295  * @new_cfg: new configuration
9296  * @tc_map: enabled TC bitmap
9297  *
9298  * Returns 0 on success, negative value on failure
9299  */
9300 static enum i40e_status_code
9301 i40e_dcb_hw_configure(struct i40e_pf *pf,
9302                       struct i40e_dcbx_config *new_cfg,
9303                       uint8_t tc_map)
9304 {
9305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9306         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9307         struct i40e_vsi *main_vsi = pf->main_vsi;
9308         struct i40e_vsi_list *vsi_list;
9309         enum i40e_status_code ret;
9310         int i;
9311         uint32_t val;
9312
9313         /* Use the FW API if FW > v4.4*/
9314         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9315               (hw->aq.fw_maj_ver >= 5))) {
9316                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9317                                   " to configure DCB");
9318                 return I40E_ERR_FIRMWARE_API_VERSION;
9319         }
9320
9321         /* Check if need reconfiguration */
9322         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9323                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9324                 return I40E_SUCCESS;
9325         }
9326
9327         /* Copy the new config to the current config */
9328         *old_cfg = *new_cfg;
9329         old_cfg->etsrec = old_cfg->etscfg;
9330         ret = i40e_set_dcb_config(hw);
9331         if (ret) {
9332                 PMD_INIT_LOG(ERR,
9333                          "Set DCB Config failed, err %s aq_err %s\n",
9334                          i40e_stat_str(hw, ret),
9335                          i40e_aq_str(hw, hw->aq.asq_last_status));
9336                 return ret;
9337         }
9338         /* set receive Arbiter to RR mode and ETS scheme by default */
9339         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9340                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9341                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9342                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9343                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9344                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9345                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9346                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9347                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9348                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9349                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9350                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9351                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9352         }
9353         /* get local mib to check whether it is configured correctly */
9354         /* IEEE mode */
9355         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9356         /* Get Local DCB Config */
9357         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9358                                      &hw->local_dcbx_config);
9359
9360         /* if Veb is created, need to update TC of it at first */
9361         if (main_vsi->veb) {
9362                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9363                 if (ret)
9364                         PMD_INIT_LOG(WARNING,
9365                                  "Failed configuring TC for VEB seid=%d\n",
9366                                  main_vsi->veb->seid);
9367         }
9368         /* Update each VSI */
9369         i40e_vsi_config_tc(main_vsi, tc_map);
9370         if (main_vsi->veb) {
9371                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9372                         /* Beside main VSI and VMDQ VSIs, only enable default
9373                          * TC for other VSIs
9374                          */
9375                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9376                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9377                                                          tc_map);
9378                         else
9379                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9380                                                          I40E_DEFAULT_TCMAP);
9381                         if (ret)
9382                                 PMD_INIT_LOG(WARNING,
9383                                          "Failed configuring TC for VSI seid=%d\n",
9384                                          vsi_list->vsi->seid);
9385                         /* continue */
9386                 }
9387         }
9388         return I40E_SUCCESS;
9389 }
9390
9391 /*
9392  * i40e_dcb_init_configure - initial dcb config
9393  * @dev: device being configured
9394  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9395  *
9396  * Returns 0 on success, negative value on failure
9397  */
9398 static int
9399 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9400 {
9401         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9402         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9403         int ret = 0;
9404
9405         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9406                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9407                 return -ENOTSUP;
9408         }
9409
9410         /* DCB initialization:
9411          * Update DCB configuration from the Firmware and configure
9412          * LLDP MIB change event.
9413          */
9414         if (sw_dcb == TRUE) {
9415                 ret = i40e_init_dcb(hw);
9416                 /* If lldp agent is stopped, the return value from
9417                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9418                  * adminq status. Otherwise, it should return success.
9419                  */
9420                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9421                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9422                         memset(&hw->local_dcbx_config, 0,
9423                                 sizeof(struct i40e_dcbx_config));
9424                         /* set dcb default configuration */
9425                         hw->local_dcbx_config.etscfg.willing = 0;
9426                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9427                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9428                         hw->local_dcbx_config.etscfg.tsatable[0] =
9429                                                 I40E_IEEE_TSA_ETS;
9430                         hw->local_dcbx_config.etsrec =
9431                                 hw->local_dcbx_config.etscfg;
9432                         hw->local_dcbx_config.pfc.willing = 0;
9433                         hw->local_dcbx_config.pfc.pfccap =
9434                                                 I40E_MAX_TRAFFIC_CLASS;
9435                         /* FW needs one App to configure HW */
9436                         hw->local_dcbx_config.numapps = 1;
9437                         hw->local_dcbx_config.app[0].selector =
9438                                                 I40E_APP_SEL_ETHTYPE;
9439                         hw->local_dcbx_config.app[0].priority = 3;
9440                         hw->local_dcbx_config.app[0].protocolid =
9441                                                 I40E_APP_PROTOID_FCOE;
9442                         ret = i40e_set_dcb_config(hw);
9443                         if (ret) {
9444                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9445                                         " err = %d, aq_err = %d.", ret,
9446                                           hw->aq.asq_last_status);
9447                                 return -ENOSYS;
9448                         }
9449                 } else {
9450                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9451                                           " err = %d, aq_err = %d.", ret,
9452                                           hw->aq.asq_last_status);
9453                         return -ENOTSUP;
9454                 }
9455         } else {
9456                 ret = i40e_aq_start_lldp(hw, NULL);
9457                 if (ret != I40E_SUCCESS)
9458                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9459
9460                 ret = i40e_init_dcb(hw);
9461                 if (!ret) {
9462                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9463                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9464                                                   " DCBX offload.");
9465                                 return -ENOTSUP;
9466                         }
9467                 } else {
9468                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9469                                           " aq_err = %d.", ret,
9470                                           hw->aq.asq_last_status);
9471                         return -ENOTSUP;
9472                 }
9473         }
9474         return 0;
9475 }
9476
9477 /*
9478  * i40e_dcb_setup - setup dcb related config
9479  * @dev: device being configured
9480  *
9481  * Returns 0 on success, negative value on failure
9482  */
9483 static int
9484 i40e_dcb_setup(struct rte_eth_dev *dev)
9485 {
9486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9487         struct i40e_dcbx_config dcb_cfg;
9488         uint8_t tc_map = 0;
9489         int ret = 0;
9490
9491         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9492                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9493                 return -ENOTSUP;
9494         }
9495
9496         if (pf->vf_num != 0)
9497                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9498
9499         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9500         if (ret) {
9501                 PMD_INIT_LOG(ERR, "invalid dcb config");
9502                 return -EINVAL;
9503         }
9504         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9505         if (ret) {
9506                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9507                 return -ENOSYS;
9508         }
9509
9510         return 0;
9511 }
9512
9513 static int
9514 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9515                       struct rte_eth_dcb_info *dcb_info)
9516 {
9517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9519         struct i40e_vsi *vsi = pf->main_vsi;
9520         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9521         uint16_t bsf, tc_mapping;
9522         int i, j = 0;
9523
9524         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9525                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9526         else
9527                 dcb_info->nb_tcs = 1;
9528         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9529                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9530         for (i = 0; i < dcb_info->nb_tcs; i++)
9531                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9532
9533         /* get queue mapping if vmdq is disabled */
9534         if (!pf->nb_cfg_vmdq_vsi) {
9535                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9536                         if (!(vsi->enabled_tc & (1 << i)))
9537                                 continue;
9538                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9539                         dcb_info->tc_queue.tc_rxq[j][i].base =
9540                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9541                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9542                         dcb_info->tc_queue.tc_txq[j][i].base =
9543                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9544                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9545                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9546                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9547                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9548                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9549                 }
9550                 return 0;
9551         }
9552
9553         /* get queue mapping if vmdq is enabled */
9554         do {
9555                 vsi = pf->vmdq[j].vsi;
9556                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9557                         if (!(vsi->enabled_tc & (1 << i)))
9558                                 continue;
9559                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9560                         dcb_info->tc_queue.tc_rxq[j][i].base =
9561                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9562                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9563                         dcb_info->tc_queue.tc_txq[j][i].base =
9564                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9565                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9566                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9567                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9568                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9569                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9570                 }
9571                 j++;
9572         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9573         return 0;
9574 }
9575
9576 static int
9577 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9578 {
9579         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9580         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9581         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9582         uint16_t interval =
9583                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9584         uint16_t msix_intr;
9585
9586         msix_intr = intr_handle->intr_vec[queue_id];
9587         if (msix_intr == I40E_MISC_VEC_ID)
9588                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9589                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9590                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9591                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9592                                (interval <<
9593                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9594         else
9595                 I40E_WRITE_REG(hw,
9596                                I40E_PFINT_DYN_CTLN(msix_intr -
9597                                                    I40E_RX_VEC_START),
9598                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9599                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9600                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9601                                (interval <<
9602                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9603
9604         I40E_WRITE_FLUSH(hw);
9605         rte_intr_enable(&pci_dev->intr_handle);
9606
9607         return 0;
9608 }
9609
9610 static int
9611 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9612 {
9613         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9616         uint16_t msix_intr;
9617
9618         msix_intr = intr_handle->intr_vec[queue_id];
9619         if (msix_intr == I40E_MISC_VEC_ID)
9620                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9621         else
9622                 I40E_WRITE_REG(hw,
9623                                I40E_PFINT_DYN_CTLN(msix_intr -
9624                                                    I40E_RX_VEC_START),
9625                                0);
9626         I40E_WRITE_FLUSH(hw);
9627
9628         return 0;
9629 }
9630
9631 static int i40e_get_regs(struct rte_eth_dev *dev,
9632                          struct rte_dev_reg_info *regs)
9633 {
9634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9635         uint32_t *ptr_data = regs->data;
9636         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9637         const struct i40e_reg_info *reg_info;
9638
9639         if (ptr_data == NULL) {
9640                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9641                 regs->width = sizeof(uint32_t);
9642                 return 0;
9643         }
9644
9645         /* The first few registers have to be read using AQ operations */
9646         reg_idx = 0;
9647         while (i40e_regs_adminq[reg_idx].name) {
9648                 reg_info = &i40e_regs_adminq[reg_idx++];
9649                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9650                         for (arr_idx2 = 0;
9651                                         arr_idx2 <= reg_info->count2;
9652                                         arr_idx2++) {
9653                                 reg_offset = arr_idx * reg_info->stride1 +
9654                                         arr_idx2 * reg_info->stride2;
9655                                 reg_offset += reg_info->base_addr;
9656                                 ptr_data[reg_offset >> 2] =
9657                                         i40e_read_rx_ctl(hw, reg_offset);
9658                         }
9659         }
9660
9661         /* The remaining registers can be read using primitives */
9662         reg_idx = 0;
9663         while (i40e_regs_others[reg_idx].name) {
9664                 reg_info = &i40e_regs_others[reg_idx++];
9665                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9666                         for (arr_idx2 = 0;
9667                                         arr_idx2 <= reg_info->count2;
9668                                         arr_idx2++) {
9669                                 reg_offset = arr_idx * reg_info->stride1 +
9670                                         arr_idx2 * reg_info->stride2;
9671                                 reg_offset += reg_info->base_addr;
9672                                 ptr_data[reg_offset >> 2] =
9673                                         I40E_READ_REG(hw, reg_offset);
9674                         }
9675         }
9676
9677         return 0;
9678 }
9679
9680 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9681 {
9682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9683
9684         /* Convert word count to byte count */
9685         return hw->nvm.sr_size << 1;
9686 }
9687
9688 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9689                            struct rte_dev_eeprom_info *eeprom)
9690 {
9691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9692         uint16_t *data = eeprom->data;
9693         uint16_t offset, length, cnt_words;
9694         int ret_code;
9695
9696         offset = eeprom->offset >> 1;
9697         length = eeprom->length >> 1;
9698         cnt_words = length;
9699
9700         if (offset > hw->nvm.sr_size ||
9701                 offset + length > hw->nvm.sr_size) {
9702                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9703                 return -EINVAL;
9704         }
9705
9706         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9707
9708         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9709         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9710                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9711                 return -EIO;
9712         }
9713
9714         return 0;
9715 }
9716
9717 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9718                                       struct ether_addr *mac_addr)
9719 {
9720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9721
9722         if (!is_valid_assigned_ether_addr(mac_addr)) {
9723                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9724                 return;
9725         }
9726
9727         /* Flags: 0x3 updates port address */
9728         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9729 }
9730
9731 static int
9732 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9733 {
9734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9735         struct rte_eth_dev_data *dev_data = pf->dev_data;
9736         uint32_t frame_size = mtu + ETHER_HDR_LEN
9737                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9738         int ret = 0;
9739
9740         /* check if mtu is within the allowed range */
9741         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9742                 return -EINVAL;
9743
9744         /* mtu setting is forbidden if port is start */
9745         if (dev_data->dev_started) {
9746                 PMD_DRV_LOG(ERR,
9747                             "port %d must be stopped before configuration\n",
9748                             dev_data->port_id);
9749                 return -EBUSY;
9750         }
9751
9752         if (frame_size > ETHER_MAX_LEN)
9753                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9754         else
9755                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9756
9757         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9758
9759         return ret;
9760 }