drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 295                           struct ether_addr *mac_addr,
 296                           uint32_t index,
 297                           uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418
 419 int i40e_logtype_init;
 420 int i40e_logtype_driver;
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 633         struct rte_pci_device *pci_dev)
 634 {
 635         return rte_eth_dev_pci_generic_probe(pci_dev,
 636                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 637 }
 638
 639 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 640 {
 641         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 642 }
 643
 644 static struct rte_pci_driver rte_i40e_pmd = {
 645         .id_table = pci_id_i40e_map,
 646         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 647         .probe = eth_i40e_pci_probe,
 648         .remove = eth_i40e_pci_remove,
 649 };
 650
 651 static inline int
 652 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 653                                      struct rte_eth_link *link)
 654 {
 655         struct rte_eth_link *dst = link;
 656         struct rte_eth_link *src = &(dev->data->dev_link);
 657
 658         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 659                                         *(uint64_t *)src) == 0)
 660                 return -1;
 661
 662         return 0;
 663 }
 664
 665 static inline int
 666 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 667                                       struct rte_eth_link *link)
 668 {
 669         struct rte_eth_link *dst = &(dev->data->dev_link);
 670         struct rte_eth_link *src = link;
 671
 672         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 673                                         *(uint64_t *)src) == 0)
 674                 return -1;
 675
 676         return 0;
 677 }
 678
 679 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 680 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 681 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 682
 683 #ifndef I40E_GLQF_ORT
 684 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 685 #endif
 686 #ifndef I40E_GLQF_PIT
 687 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 688 #endif
 689 #ifndef I40E_GLQF_L3_MAP
 690 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 691 #endif
 692
 693 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 694 {
 695         /*
 696          * Initialize registers for flexible payload, which should be set by NVM.
 697          * This should be removed from code once it is fixed in NVM.
 698          */
 699         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 709         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 710         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 711
 712         /* Initialize registers for parsing packet type of QinQ */
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 714         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 715 }
 716
 717 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 718
 719 /*
 720  * Add a ethertype filter to drop all flow control frames transmitted
 721  * from VSIs.
 722 */
 723 static void
 724 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 725 {
 726         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 727         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 728                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 729                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 730         int ret;
 731
 732         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 733                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 734                                 pf->main_vsi_seid, 0,
 735                                 TRUE, NULL, NULL);
 736         if (ret)
 737                 PMD_INIT_LOG(ERR,
 738                         "Failed to add filter to drop flow control frames from VSIs.");
 739 }
 740
 741 static int
 742 floating_veb_list_handler(__rte_unused const char *key,
 743                           const char *floating_veb_value,
 744                           void *opaque)
 745 {
 746         int idx = 0;
 747         unsigned int count = 0;
 748         char *end = NULL;
 749         int min, max;
 750         bool *vf_floating_veb = opaque;
 751
 752         while (isblank(*floating_veb_value))
 753                 floating_veb_value++;
 754
 755         /* Reset floating VEB configuration for VFs */
 756         for (idx = 0; idx < I40E_MAX_VF; idx++)
 757                 vf_floating_veb[idx] = false;
 758
 759         min = I40E_MAX_VF;
 760         do {
 761                 while (isblank(*floating_veb_value))
 762                         floating_veb_value++;
 763                 if (*floating_veb_value == '\0')
 764                         return -1;
 765                 errno = 0;
 766                 idx = strtoul(floating_veb_value, &end, 10);
 767                 if (errno || end == NULL)
 768                         return -1;
 769                 while (isblank(*end))
 770                         end++;
 771                 if (*end == '-') {
 772                         min = idx;
 773                 } else if ((*end == ';') || (*end == '\0')) {
 774                         max = idx;
 775                         if (min == I40E_MAX_VF)
 776                                 min = idx;
 777                         if (max >= I40E_MAX_VF)
 778                                 max = I40E_MAX_VF - 1;
 779                         for (idx = min; idx <= max; idx++) {
 780                                 vf_floating_veb[idx] = true;
 781                                 count++;
 782                         }
 783                         min = I40E_MAX_VF;
 784                 } else {
 785                         return -1;
 786                 }
 787                 floating_veb_value = end + 1;
 788         } while (*end != '\0');
 789
 790         if (count == 0)
 791                 return -1;
 792
 793         return 0;
 794 }
 795
 796 static void
 797 config_vf_floating_veb(struct rte_devargs *devargs,
 798                        uint16_t floating_veb,
 799                        bool *vf_floating_veb)
 800 {
 801         struct rte_kvargs *kvlist;
 802         int i;
 803         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 804
 805         if (!floating_veb)
 806                 return;
 807         /* All the VFs attach to the floating VEB by default
 808          * when the floating VEB is enabled.
 809          */
 810         for (i = 0; i < I40E_MAX_VF; i++)
 811                 vf_floating_veb[i] = true;
 812
 813         if (devargs == NULL)
 814                 return;
 815
 816         kvlist = rte_kvargs_parse(devargs->args, NULL);
 817         if (kvlist == NULL)
 818                 return;
 819
 820         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         /* When the floating_veb_list parameter exists, all the VFs
 825          * will attach to the legacy VEB firstly, then configure VFs
 826          * to the floating VEB according to the floating_veb_list.
 827          */
 828         if (rte_kvargs_process(kvlist, floating_veb_list,
 829                                floating_veb_list_handler,
 830                                vf_floating_veb) < 0) {
 831                 rte_kvargs_free(kvlist);
 832                 return;
 833         }
 834         rte_kvargs_free(kvlist);
 835 }
 836
 837 static int
 838 i40e_check_floating_handler(__rte_unused const char *key,
 839                             const char *value,
 840                             __rte_unused void *opaque)
 841 {
 842         if (strcmp(value, "1"))
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 static int
 849 is_floating_veb_supported(struct rte_devargs *devargs)
 850 {
 851         struct rte_kvargs *kvlist;
 852         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 853
 854         if (devargs == NULL)
 855                 return 0;
 856
 857         kvlist = rte_kvargs_parse(devargs->args, NULL);
 858         if (kvlist == NULL)
 859                 return 0;
 860
 861         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 862                 rte_kvargs_free(kvlist);
 863                 return 0;
 864         }
 865         /* Floating VEB is enabled when there's key-value:
 866          * enable_floating_veb=1
 867          */
 868         if (rte_kvargs_process(kvlist, floating_veb_key,
 869                                i40e_check_floating_handler, NULL) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return 0;
 872         }
 873         rte_kvargs_free(kvlist);
 874
 875         return 1;
 876 }
 877
 878 static void
 879 config_floating_veb(struct rte_eth_dev *dev)
 880 {
 881         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884
 885         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 886
 887         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 888                 pf->floating_veb =
 889                         is_floating_veb_supported(pci_dev->device.devargs);
 890                 config_vf_floating_veb(pci_dev->device.devargs,
 891                                        pf->floating_veb,
 892                                        pf->floating_veb_list);
 893         } else {
 894                 pf->floating_veb = false;
 895         }
 896 }
 897
 898 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 899 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 900
 901 static int
 902 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 903 {
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 906         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 907         int ret;
 908
 909         struct rte_hash_parameters ethertype_hash_params = {
 910                 .name = ethertype_hash_name,
 911                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 912                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 913                 .hash_func = rte_hash_crc,
 914                 .hash_func_init_val = 0,
 915                 .socket_id = rte_socket_id(),
 916         };
 917
 918         /* Initialize ethertype filter rule list and hash */
 919         TAILQ_INIT(&ethertype_rule->ethertype_list);
 920         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 921                  "ethertype_%s", dev->data->name);
 922         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 923         if (!ethertype_rule->hash_table) {
 924                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 925                 return -EINVAL;
 926         }
 927         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 928                                        sizeof(struct i40e_ethertype_filter *) *
 929                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 930                                        0);
 931         if (!ethertype_rule->hash_map) {
 932                 PMD_INIT_LOG(ERR,
 933                              "Failed to allocate memory for ethertype hash map!");
 934                 ret = -ENOMEM;
 935                 goto err_ethertype_hash_map_alloc;
 936         }
 937
 938         return 0;
 939
 940 err_ethertype_hash_map_alloc:
 941         rte_hash_free(ethertype_rule->hash_table);
 942
 943         return ret;
 944 }
 945
 946 static int
 947 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 948 {
 949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 950         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 951         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 952         int ret;
 953
 954         struct rte_hash_parameters tunnel_hash_params = {
 955                 .name = tunnel_hash_name,
 956                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 957                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 958                 .hash_func = rte_hash_crc,
 959                 .hash_func_init_val = 0,
 960                 .socket_id = rte_socket_id(),
 961         };
 962
 963         /* Initialize tunnel filter rule list and hash */
 964         TAILQ_INIT(&tunnel_rule->tunnel_list);
 965         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 966                  "tunnel_%s", dev->data->name);
 967         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 968         if (!tunnel_rule->hash_table) {
 969                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 970                 return -EINVAL;
 971         }
 972         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 973                                     sizeof(struct i40e_tunnel_filter *) *
 974                                     I40E_MAX_TUNNEL_FILTER_NUM,
 975                                     0);
 976         if (!tunnel_rule->hash_map) {
 977                 PMD_INIT_LOG(ERR,
 978                              "Failed to allocate memory for tunnel hash map!");
 979                 ret = -ENOMEM;
 980                 goto err_tunnel_hash_map_alloc;
 981         }
 982
 983         return 0;
 984
 985 err_tunnel_hash_map_alloc:
 986         rte_hash_free(tunnel_rule->hash_table);
 987
 988         return ret;
 989 }
 990
 991 static int
 992 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 993 {
 994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 995         struct i40e_fdir_info *fdir_info = &pf->fdir;
 996         char fdir_hash_name[RTE_HASH_NAMESIZE];
 997         int ret;
 998
 999         struct rte_hash_parameters fdir_hash_params = {
1000                 .name = fdir_hash_name,
1001                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1002                 .key_len = sizeof(struct rte_eth_fdir_input),
1003                 .hash_func = rte_hash_crc,
1004                 .hash_func_init_val = 0,
1005                 .socket_id = rte_socket_id(),
1006         };
1007
1008         /* Initialize flow director filter rule list and hash */
1009         TAILQ_INIT(&fdir_info->fdir_list);
1010         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1011                  "fdir_%s", dev->data->name);
1012         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1013         if (!fdir_info->hash_table) {
1014                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1015                 return -EINVAL;
1016         }
1017         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1018                                           sizeof(struct i40e_fdir_filter *) *
1019                                           I40E_MAX_FDIR_FILTER_NUM,
1020                                           0);
1021         if (!fdir_info->hash_map) {
1022                 PMD_INIT_LOG(ERR,
1023                              "Failed to allocate memory for fdir hash map!");
1024                 ret = -ENOMEM;
1025                 goto err_fdir_hash_map_alloc;
1026         }
1027         return 0;
1028
1029 err_fdir_hash_map_alloc:
1030         rte_hash_free(fdir_info->hash_table);
1031
1032         return ret;
1033 }
1034
1035 static int
1036 eth_i40e_dev_init(struct rte_eth_dev *dev)
1037 {
1038         struct rte_pci_device *pci_dev;
1039         struct rte_intr_handle *intr_handle;
1040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042         struct i40e_vsi *vsi;
1043         int ret;
1044         uint32_t len;
1045         uint8_t aq_fail = 0;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         dev->dev_ops = &i40e_eth_dev_ops;
1050         dev->rx_pkt_burst = i40e_recv_pkts;
1051         dev->tx_pkt_burst = i40e_xmit_pkts;
1052         dev->tx_pkt_prepare = i40e_prep_pkts;
1053
1054         /* for secondary processes, we don't initialise any further as primary
1055          * has already done this work. Only check we don't need a different
1056          * RX function */
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1058                 i40e_set_rx_function(dev);
1059                 i40e_set_tx_function(dev);
1060                 return 0;
1061         }
1062         i40e_set_default_ptype_table(dev);
1063         pci_dev = I40E_DEV_TO_PCI(dev);
1064         intr_handle = &pci_dev->intr_handle;
1065
1066         rte_eth_copy_pci_info(dev, pci_dev);
1067         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1068
1069         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1070         pf->adapter->eth_dev = dev;
1071         pf->dev_data = dev->data;
1072
1073         hw->back = I40E_PF_TO_ADAPTER(pf);
1074         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1075         if (!hw->hw_addr) {
1076                 PMD_INIT_LOG(ERR,
1077                         "Hardware is not available, as address is NULL");
1078                 return -ENODEV;
1079         }
1080
1081         hw->vendor_id = pci_dev->id.vendor_id;
1082         hw->device_id = pci_dev->id.device_id;
1083         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1084         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1085         hw->bus.device = pci_dev->addr.devid;
1086         hw->bus.func = pci_dev->addr.function;
1087         hw->adapter_stopped = 0;
1088
1089         /* Make sure all is clean before doing PF reset */
1090         i40e_clear_hw(hw);
1091
1092         /* Initialize the hardware */
1093         i40e_hw_init(dev);
1094
1095         /* Reset here to make sure all is clean for each PF */
1096         ret = i40e_pf_reset(hw);
1097         if (ret) {
1098                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1099                 return ret;
1100         }
1101
1102         /* Initialize the shared code (base driver) */
1103         ret = i40e_init_shared_code(hw);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1106                 return ret;
1107         }
1108
1109         /*
1110          * To work around the NVM issue, initialize registers
1111          * for flexible payload and packet type of QinQ by
1112          * software. It should be removed once issues are fixed
1113          * in NVM.
1114          */
1115         i40e_GLQF_reg_init(hw);
1116
1117         /* Initialize the input set for filters (hash and fd) to default value */
1118         i40e_filter_input_set_init(pf);
1119
1120         /* Initialize the parameters for adminq */
1121         i40e_init_adminq_parameter(hw);
1122         ret = i40e_init_adminq(hw);
1123         if (ret != I40E_SUCCESS) {
1124                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1125                 return -EIO;
1126         }
1127         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1128                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1129                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1130                      ((hw->nvm.version >> 12) & 0xf),
1131                      ((hw->nvm.version >> 4) & 0xff),
1132                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1133
1134         /* initialise the L3_MAP register */
1135         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1136                                    0x00000028,  NULL);
1137         if (ret)
1138                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1139
1140         /* Need the special FW version to support floating VEB */
1141         config_floating_veb(dev);
1142         /* Clear PXE mode */
1143         i40e_clear_pxe_mode(hw);
1144         ret = i40e_dev_sync_phy_type(hw);
1145         if (ret) {
1146                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1147                 goto err_sync_phy_type;
1148         }
1149         /*
1150          * On X710, performance number is far from the expectation on recent
1151          * firmware versions. The fix for this issue may not be integrated in
1152          * the following firmware version. So the workaround in software driver
1153          * is needed. It needs to modify the initial values of 3 internal only
1154          * registers. Note that the workaround can be removed when it is fixed
1155          * in firmware in the future.
1156          */
1157         i40e_configure_registers(hw);
1158
1159         /* Get hw capabilities */
1160         ret = i40e_get_cap(hw);
1161         if (ret != I40E_SUCCESS) {
1162                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1163                 goto err_get_capabilities;
1164         }
1165
1166         /* Initialize parameters for PF */
1167         ret = i40e_pf_parameter_init(dev);
1168         if (ret != 0) {
1169                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1170                 goto err_parameter_init;
1171         }
1172
1173         /* Initialize the queue management */
1174         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1175         if (ret < 0) {
1176                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1177                 goto err_qp_pool_init;
1178         }
1179         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1180                                 hw->func_caps.num_msix_vectors - 1);
1181         if (ret < 0) {
1182                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1183                 goto err_msix_pool_init;
1184         }
1185
1186         /* Initialize lan hmc */
1187         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1188                                 hw->func_caps.num_rx_qp, 0, 0);
1189         if (ret != I40E_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1191                 goto err_init_lan_hmc;
1192         }
1193
1194         /* Configure lan hmc */
1195         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1196         if (ret != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1198                 goto err_configure_lan_hmc;
1199         }
1200
1201         /* Get and check the mac address */
1202         i40e_get_mac_addr(hw, hw->mac.addr);
1203         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1204                 PMD_INIT_LOG(ERR, "mac address is not valid");
1205                 ret = -EIO;
1206                 goto err_get_mac_addr;
1207         }
1208         /* Copy the permanent MAC address */
1209         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1210                         (struct ether_addr *) hw->mac.perm_addr);
1211
1212         /* Disable flow control */
1213         hw->fc.requested_mode = I40E_FC_NONE;
1214         i40e_set_fc(hw, &aq_fail, TRUE);
1215
1216         /* Set the global registers with default ether type value */
1217         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1218         if (ret != I40E_SUCCESS) {
1219                 PMD_INIT_LOG(ERR,
1220                         "Failed to set the default outer VLAN ether type");
1221                 goto err_setup_pf_switch;
1222         }
1223
1224         /* PF setup, which includes VSI setup */
1225         ret = i40e_pf_setup(pf);
1226         if (ret) {
1227                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1228                 goto err_setup_pf_switch;
1229         }
1230
1231         /* reset all stats of the device, including pf and main vsi */
1232         i40e_dev_stats_reset(dev);
1233
1234         vsi = pf->main_vsi;
1235
1236         /* Disable double vlan by default */
1237         i40e_vsi_config_double_vlan(vsi, FALSE);
1238
1239         /* Disable S-TAG identification when floating_veb is disabled */
1240         if (!pf->floating_veb) {
1241                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1242                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1243                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1244                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1245                 }
1246         }
1247
1248         if (!vsi->max_macaddrs)
1249                 len = ETHER_ADDR_LEN;
1250         else
1251                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1252
1253         /* Should be after VSI initialized */
1254         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1255         if (!dev->data->mac_addrs) {
1256                 PMD_INIT_LOG(ERR,
1257                         "Failed to allocated memory for storing mac address");
1258                 goto err_mac_alloc;
1259         }
1260         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1261                                         &dev->data->mac_addrs[0]);
1262
1263         /* Init dcb to sw mode by default */
1264         ret = i40e_dcb_init_configure(dev, TRUE);
1265         if (ret != I40E_SUCCESS) {
1266                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1267                 pf->flags &= ~I40E_FLAG_DCB;
1268         }
1269         /* Update HW struct after DCB configuration */
1270         i40e_get_cap(hw);
1271
1272         /* initialize pf host driver to setup SRIOV resource if applicable */
1273         i40e_pf_host_init(dev);
1274
1275         /* register callback func to eal lib */
1276         rte_intr_callback_register(intr_handle,
1277                                    i40e_dev_interrupt_handler, dev);
1278
1279         /* configure and enable device interrupt */
1280         i40e_pf_config_irq0(hw, TRUE);
1281         i40e_pf_enable_irq0(hw);
1282
1283         /* enable uio intr after callback register */
1284         rte_intr_enable(intr_handle);
1285         /*
1286          * Add an ethertype filter to drop all flow control frames transmitted
1287          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1288          * frames to wire.
1289          */
1290         i40e_add_tx_flow_control_drop_filter(pf);
1291
1292         /* Set the max frame size to 0x2600 by default,
1293          * in case other drivers changed the default value.
1294          */
1295         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1296
1297         /* initialize mirror rule list */
1298         TAILQ_INIT(&pf->mirror_list);
1299
1300         ret = i40e_init_ethtype_filter_list(dev);
1301         if (ret < 0)
1302                 goto err_init_ethtype_filter_list;
1303         ret = i40e_init_tunnel_filter_list(dev);
1304         if (ret < 0)
1305                 goto err_init_tunnel_filter_list;
1306         ret = i40e_init_fdir_filter_list(dev);
1307         if (ret < 0)
1308                 goto err_init_fdir_filter_list;
1309
1310         return 0;
1311
1312 err_init_fdir_filter_list:
1313         rte_free(pf->tunnel.hash_table);
1314         rte_free(pf->tunnel.hash_map);
1315 err_init_tunnel_filter_list:
1316         rte_free(pf->ethertype.hash_table);
1317         rte_free(pf->ethertype.hash_map);
1318 err_init_ethtype_filter_list:
1319         rte_free(dev->data->mac_addrs);
1320 err_mac_alloc:
1321         i40e_vsi_release(pf->main_vsi);
1322 err_setup_pf_switch:
1323 err_get_mac_addr:
1324 err_configure_lan_hmc:
1325         (void)i40e_shutdown_lan_hmc(hw);
1326 err_init_lan_hmc:
1327         i40e_res_pool_destroy(&pf->msix_pool);
1328 err_msix_pool_init:
1329         i40e_res_pool_destroy(&pf->qp_pool);
1330 err_qp_pool_init:
1331 err_parameter_init:
1332 err_get_capabilities:
1333 err_sync_phy_type:
1334         (void)i40e_shutdown_adminq(hw);
1335
1336         return ret;
1337 }
1338
1339 static void
1340 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1341 {
1342         struct i40e_ethertype_filter *p_ethertype;
1343         struct i40e_ethertype_rule *ethertype_rule;
1344
1345         ethertype_rule = &pf->ethertype;
1346         /* Remove all ethertype filter rules and hash */
1347         if (ethertype_rule->hash_map)
1348                 rte_free(ethertype_rule->hash_map);
1349         if (ethertype_rule->hash_table)
1350                 rte_hash_free(ethertype_rule->hash_table);
1351
1352         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1353                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1354                              p_ethertype, rules);
1355                 rte_free(p_ethertype);
1356         }
1357 }
1358
1359 static void
1360 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1361 {
1362         struct i40e_tunnel_filter *p_tunnel;
1363         struct i40e_tunnel_rule *tunnel_rule;
1364
1365         tunnel_rule = &pf->tunnel;
1366         /* Remove all tunnel director rules and hash */
1367         if (tunnel_rule->hash_map)
1368                 rte_free(tunnel_rule->hash_map);
1369         if (tunnel_rule->hash_table)
1370                 rte_hash_free(tunnel_rule->hash_table);
1371
1372         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1373                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1374                 rte_free(p_tunnel);
1375         }
1376 }
1377
1378 static void
1379 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1380 {
1381         struct i40e_fdir_filter *p_fdir;
1382         struct i40e_fdir_info *fdir_info;
1383
1384         fdir_info = &pf->fdir;
1385         /* Remove all flow director rules and hash */
1386         if (fdir_info->hash_map)
1387                 rte_free(fdir_info->hash_map);
1388         if (fdir_info->hash_table)
1389                 rte_hash_free(fdir_info->hash_table);
1390
1391         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1393                 rte_free(p_fdir);
1394         }
1395 }
1396
1397 static int
1398 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1399 {
1400         struct i40e_pf *pf;
1401         struct rte_pci_device *pci_dev;
1402         struct rte_intr_handle *intr_handle;
1403         struct i40e_hw *hw;
1404         struct i40e_filter_control_settings settings;
1405         struct rte_flow *p_flow;
1406         int ret;
1407         uint8_t aq_fail = 0;
1408
1409         PMD_INIT_FUNC_TRACE();
1410
1411         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1412                 return 0;
1413
1414         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1415         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1416         pci_dev = I40E_DEV_TO_PCI(dev);
1417         intr_handle = &pci_dev->intr_handle;
1418
1419         if (hw->adapter_stopped == 0)
1420                 i40e_dev_close(dev);
1421
1422         dev->dev_ops = NULL;
1423         dev->rx_pkt_burst = NULL;
1424         dev->tx_pkt_burst = NULL;
1425
1426         /* Clear PXE mode */
1427         i40e_clear_pxe_mode(hw);
1428
1429         /* Unconfigure filter control */
1430         memset(&settings, 0, sizeof(settings));
1431         ret = i40e_set_filter_control(hw, &settings);
1432         if (ret)
1433                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1434                                         ret);
1435
1436         /* Disable flow control */
1437         hw->fc.requested_mode = I40E_FC_NONE;
1438         i40e_set_fc(hw, &aq_fail, TRUE);
1439
1440         /* uninitialize pf host driver */
1441         i40e_pf_host_uninit(dev);
1442
1443         rte_free(dev->data->mac_addrs);
1444         dev->data->mac_addrs = NULL;
1445
1446         /* disable uio intr before callback unregister */
1447         rte_intr_disable(intr_handle);
1448
1449         /* register callback func to eal lib */
1450         rte_intr_callback_unregister(intr_handle,
1451                                      i40e_dev_interrupt_handler, dev);
1452
1453         i40e_rm_ethtype_filter_list(pf);
1454         i40e_rm_tunnel_filter_list(pf);
1455         i40e_rm_fdir_filter_list(pf);
1456
1457         /* Remove all flows */
1458         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1459                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1460                 rte_free(p_flow);
1461         }
1462
1463         return 0;
1464 }
1465
1466 static int
1467 i40e_dev_configure(struct rte_eth_dev *dev)
1468 {
1469         struct i40e_adapter *ad =
1470                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1472         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1473         int i, ret;
1474
1475         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1476          * bulk allocation or vector Rx preconditions we will reset it.
1477          */
1478         ad->rx_bulk_alloc_allowed = true;
1479         ad->rx_vec_allowed = true;
1480         ad->tx_simple_allowed = true;
1481         ad->tx_vec_allowed = true;
1482
1483         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1484                 ret = i40e_fdir_setup(pf);
1485                 if (ret != I40E_SUCCESS) {
1486                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1487                         return -ENOTSUP;
1488                 }
1489                 ret = i40e_fdir_configure(dev);
1490                 if (ret < 0) {
1491                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1492                         goto err;
1493                 }
1494         } else
1495                 i40e_fdir_teardown(pf);
1496
1497         ret = i40e_dev_init_vlan(dev);
1498         if (ret < 0)
1499                 goto err;
1500
1501         /* VMDQ setup.
1502          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1503          *  RSS setting have different requirements.
1504          *  General PMD driver call sequence are NIC init, configure,
1505          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1506          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1507          *  applicable. So, VMDQ setting has to be done before
1508          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1509          *  For RSS setting, it will try to calculate actual configured RX queue
1510          *  number, which will be available after rx_queue_setup(). dev_start()
1511          *  function is good to place RSS setup.
1512          */
1513         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1514                 ret = i40e_vmdq_setup(dev);
1515                 if (ret)
1516                         goto err;
1517         }
1518
1519         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1520                 ret = i40e_dcb_setup(dev);
1521                 if (ret) {
1522                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1523                         goto err_dcb;
1524                 }
1525         }
1526
1527         TAILQ_INIT(&pf->flow_list);
1528
1529         return 0;
1530
1531 err_dcb:
1532         /* need to release vmdq resource if exists */
1533         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1534                 i40e_vsi_release(pf->vmdq[i].vsi);
1535                 pf->vmdq[i].vsi = NULL;
1536         }
1537         rte_free(pf->vmdq);
1538         pf->vmdq = NULL;
1539 err:
1540         /* need to release fdir resource if exists */
1541         i40e_fdir_teardown(pf);
1542         return ret;
1543 }
1544
1545 void
1546 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1547 {
1548         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1549         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1551         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1552         uint16_t msix_vect = vsi->msix_intr;
1553         uint16_t i;
1554
1555         for (i = 0; i < vsi->nb_qps; i++) {
1556                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1557                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1558                 rte_wmb();
1559         }
1560
1561         if (vsi->type != I40E_VSI_SRIOV) {
1562                 if (!rte_intr_allow_others(intr_handle)) {
1563                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1564                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1565                         I40E_WRITE_REG(hw,
1566                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1567                                        0);
1568                 } else {
1569                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1570                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1571                         I40E_WRITE_REG(hw,
1572                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1573                                                        msix_vect - 1), 0);
1574                 }
1575         } else {
1576                 uint32_t reg;
1577                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1578                         vsi->user_param + (msix_vect - 1);
1579
1580                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1581                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1582         }
1583         I40E_WRITE_FLUSH(hw);
1584 }
1585
1586 static void
1587 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1588                        int base_queue, int nb_queue)
1589 {
1590         int i;
1591         uint32_t val;
1592         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1593
1594         /* Bind all RX queues to allocated MSIX interrupt */
1595         for (i = 0; i < nb_queue; i++) {
1596                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1597                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1598                         ((base_queue + i + 1) <<
1599                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1600                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1601                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1602
1603                 if (i == nb_queue - 1)
1604                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1605                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1606         }
1607
1608         /* Write first RX queue to Link list register as the head element */
1609         if (vsi->type != I40E_VSI_SRIOV) {
1610                 uint16_t interval =
1611                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1612
1613                 if (msix_vect == I40E_MISC_VEC_ID) {
1614                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1615                                        (base_queue <<
1616                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1617                                        (0x0 <<
1618                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1619                         I40E_WRITE_REG(hw,
1620                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1621                                        interval);
1622                 } else {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1630                                                        msix_vect - 1),
1631                                        interval);
1632                 }
1633         } else {
1634                 uint32_t reg;
1635
1636                 if (msix_vect == I40E_MISC_VEC_ID) {
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_VPINT_LNKLST0(vsi->user_param),
1639                                        (base_queue <<
1640                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1641                                        (0x0 <<
1642                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1643                 } else {
1644                         /* num_msix_vectors_vf needs to minus irq0 */
1645                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1646                                 vsi->user_param + (msix_vect - 1);
1647
1648                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1649                                        (base_queue <<
1650                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1651                                        (0x0 <<
1652                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1653                 }
1654         }
1655
1656         I40E_WRITE_FLUSH(hw);
1657 }
1658
1659 void
1660 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1661 {
1662         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1663         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1664         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1665         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1666         uint16_t msix_vect = vsi->msix_intr;
1667         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1668         uint16_t queue_idx = 0;
1669         int record = 0;
1670         uint32_t val;
1671         int i;
1672
1673         for (i = 0; i < vsi->nb_qps; i++) {
1674                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1675                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1676         }
1677
1678         /* INTENA flag is not auto-cleared for interrupt */
1679         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1680         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1681                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1682                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1683         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1684
1685         /* VF bind interrupt */
1686         if (vsi->type == I40E_VSI_SRIOV) {
1687                 __vsi_queues_bind_intr(vsi, msix_vect,
1688                                        vsi->base_queue, vsi->nb_qps);
1689                 return;
1690         }
1691
1692         /* PF & VMDq bind interrupt */
1693         if (rte_intr_dp_is_en(intr_handle)) {
1694                 if (vsi->type == I40E_VSI_MAIN) {
1695                         queue_idx = 0;
1696                         record = 1;
1697                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1698                         struct i40e_vsi *main_vsi =
1699                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1700                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1701                         record = 1;
1702                 }
1703         }
1704
1705         for (i = 0; i < vsi->nb_used_qps; i++) {
1706                 if (nb_msix <= 1) {
1707                         if (!rte_intr_allow_others(intr_handle))
1708                                 /* allow to share MISC_VEC_ID */
1709                                 msix_vect = I40E_MISC_VEC_ID;
1710
1711                         /* no enough msix_vect, map all to one */
1712                         __vsi_queues_bind_intr(vsi, msix_vect,
1713                                                vsi->base_queue + i,
1714                                                vsi->nb_used_qps - i);
1715                         for (; !!record && i < vsi->nb_used_qps; i++)
1716                                 intr_handle->intr_vec[queue_idx + i] =
1717                                         msix_vect;
1718                         break;
1719                 }
1720                 /* 1:1 queue/msix_vect mapping */
1721                 __vsi_queues_bind_intr(vsi, msix_vect,
1722                                        vsi->base_queue + i, 1);
1723                 if (!!record)
1724                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1725
1726                 msix_vect++;
1727                 nb_msix--;
1728         }
1729 }
1730
1731 static void
1732 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1733 {
1734         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1735         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1736         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1738         uint16_t interval = i40e_calc_itr_interval(\
1739                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1740         uint16_t msix_intr, i;
1741
1742         if (rte_intr_allow_others(intr_handle))
1743                 for (i = 0; i < vsi->nb_msix; i++) {
1744                         msix_intr = vsi->msix_intr + i;
1745                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1746                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1747                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1748                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1749                                 (interval <<
1750                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1751                 }
1752         else
1753                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1754                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1755                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1756                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1757                                (interval <<
1758                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1759
1760         I40E_WRITE_FLUSH(hw);
1761 }
1762
1763 static void
1764 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1765 {
1766         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1767         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1768         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1769         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1770         uint16_t msix_intr, i;
1771
1772         if (rte_intr_allow_others(intr_handle))
1773                 for (i = 0; i < vsi->nb_msix; i++) {
1774                         msix_intr = vsi->msix_intr + i;
1775                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1776                                        0);
1777                 }
1778         else
1779                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1780
1781         I40E_WRITE_FLUSH(hw);
1782 }
1783
1784 static inline uint8_t
1785 i40e_parse_link_speeds(uint16_t link_speeds)
1786 {
1787         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1788
1789         if (link_speeds & ETH_LINK_SPEED_40G)
1790                 link_speed |= I40E_LINK_SPEED_40GB;
1791         if (link_speeds & ETH_LINK_SPEED_25G)
1792                 link_speed |= I40E_LINK_SPEED_25GB;
1793         if (link_speeds & ETH_LINK_SPEED_20G)
1794                 link_speed |= I40E_LINK_SPEED_20GB;
1795         if (link_speeds & ETH_LINK_SPEED_10G)
1796                 link_speed |= I40E_LINK_SPEED_10GB;
1797         if (link_speeds & ETH_LINK_SPEED_1G)
1798                 link_speed |= I40E_LINK_SPEED_1GB;
1799         if (link_speeds & ETH_LINK_SPEED_100M)
1800                 link_speed |= I40E_LINK_SPEED_100MB;
1801
1802         return link_speed;
1803 }
1804
1805 static int
1806 i40e_phy_conf_link(struct i40e_hw *hw,
1807                    uint8_t abilities,
1808                    uint8_t force_speed)
1809 {
1810         enum i40e_status_code status;
1811         struct i40e_aq_get_phy_abilities_resp phy_ab;
1812         struct i40e_aq_set_phy_config phy_conf;
1813         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1814                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1815                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1816                         I40E_AQ_PHY_FLAG_LOW_POWER;
1817         const uint8_t advt = I40E_LINK_SPEED_40GB |
1818                         I40E_LINK_SPEED_25GB |
1819                         I40E_LINK_SPEED_10GB |
1820                         I40E_LINK_SPEED_1GB |
1821                         I40E_LINK_SPEED_100MB;
1822         int ret = -ENOTSUP;
1823
1824
1825         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1826                                               NULL);
1827         if (status)
1828                 return ret;
1829
1830         memset(&phy_conf, 0, sizeof(phy_conf));
1831
1832         /* bits 0-2 use the values from get_phy_abilities_resp */
1833         abilities &= ~mask;
1834         abilities |= phy_ab.abilities & mask;
1835
1836         /* update ablities and speed */
1837         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1838                 phy_conf.link_speed = advt;
1839         else
1840                 phy_conf.link_speed = force_speed;
1841
1842         phy_conf.abilities = abilities;
1843
1844         /* use get_phy_abilities_resp value for the rest */
1845         phy_conf.phy_type = phy_ab.phy_type;
1846         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1847         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1848         phy_conf.eee_capability = phy_ab.eee_capability;
1849         phy_conf.eeer = phy_ab.eeer_val;
1850         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1851
1852         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1853                     phy_ab.abilities, phy_ab.link_speed);
1854         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1855                     phy_conf.abilities, phy_conf.link_speed);
1856
1857         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1858         if (status)
1859                 return ret;
1860
1861         return I40E_SUCCESS;
1862 }
1863
1864 static int
1865 i40e_apply_link_speed(struct rte_eth_dev *dev)
1866 {
1867         uint8_t speed;
1868         uint8_t abilities = 0;
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct rte_eth_conf *conf = &dev->data->dev_conf;
1871
1872         speed = i40e_parse_link_speeds(conf->link_speeds);
1873         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1874         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1875                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1876         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1877
1878         /* Skip changing speed on 40G interfaces, FW does not support */
1879         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1880                 speed =  I40E_LINK_SPEED_UNKNOWN;
1881                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1882         }
1883
1884         return i40e_phy_conf_link(hw, abilities, speed);
1885 }
1886
1887 static int
1888 i40e_dev_start(struct rte_eth_dev *dev)
1889 {
1890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892         struct i40e_vsi *main_vsi = pf->main_vsi;
1893         int ret, i;
1894         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1895         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1896         uint32_t intr_vector = 0;
1897         struct i40e_vsi *vsi;
1898
1899         hw->adapter_stopped = 0;
1900
1901         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1902                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1903                              dev->data->port_id);
1904                 return -EINVAL;
1905         }
1906
1907         rte_intr_disable(intr_handle);
1908
1909         if ((rte_intr_cap_multiple(intr_handle) ||
1910              !RTE_ETH_DEV_SRIOV(dev).active) &&
1911             dev->data->dev_conf.intr_conf.rxq != 0) {
1912                 intr_vector = dev->data->nb_rx_queues;
1913                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1914                 if (ret)
1915                         return ret;
1916         }
1917
1918         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1919                 intr_handle->intr_vec =
1920                         rte_zmalloc("intr_vec",
1921                                     dev->data->nb_rx_queues * sizeof(int),
1922                                     0);
1923                 if (!intr_handle->intr_vec) {
1924                         PMD_INIT_LOG(ERR,
1925                                 "Failed to allocate %d rx_queues intr_vec",
1926                                 dev->data->nb_rx_queues);
1927                         return -ENOMEM;
1928                 }
1929         }
1930
1931         /* Initialize VSI */
1932         ret = i40e_dev_rxtx_init(pf);
1933         if (ret != I40E_SUCCESS) {
1934                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1935                 goto err_up;
1936         }
1937
1938         /* Map queues with MSIX interrupt */
1939         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1940                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1941         i40e_vsi_queues_bind_intr(main_vsi);
1942         i40e_vsi_enable_queues_intr(main_vsi);
1943
1944         /* Map VMDQ VSI queues with MSIX interrupt */
1945         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1946                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1947                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1948                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1949         }
1950
1951         /* enable FDIR MSIX interrupt */
1952         if (pf->fdir.fdir_vsi) {
1953                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1954                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1955         }
1956
1957         /* Enable all queues which have been configured */
1958         ret = i40e_dev_switch_queues(pf, TRUE);
1959         if (ret != I40E_SUCCESS) {
1960                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1961                 goto err_up;
1962         }
1963
1964         /* Enable receiving broadcast packets */
1965         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1966         if (ret != I40E_SUCCESS)
1967                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1968
1969         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1970                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1971                                                 true, NULL);
1972                 if (ret != I40E_SUCCESS)
1973                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1974         }
1975
1976         /* Enable the VLAN promiscuous mode. */
1977         if (pf->vfs) {
1978                 for (i = 0; i < pf->vf_num; i++) {
1979                         vsi = pf->vfs[i].vsi;
1980                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1981                                                      true, NULL);
1982                 }
1983         }
1984
1985         /* Apply link configure */
1986         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1987                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1988                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1989                                 ETH_LINK_SPEED_40G)) {
1990                 PMD_DRV_LOG(ERR, "Invalid link setting");
1991                 goto err_up;
1992         }
1993         ret = i40e_apply_link_speed(dev);
1994         if (I40E_SUCCESS != ret) {
1995                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1996                 goto err_up;
1997         }
1998
1999         if (!rte_intr_allow_others(intr_handle)) {
2000                 rte_intr_callback_unregister(intr_handle,
2001                                              i40e_dev_interrupt_handler,
2002                                              (void *)dev);
2003                 /* configure and enable device interrupt */
2004                 i40e_pf_config_irq0(hw, FALSE);
2005                 i40e_pf_enable_irq0(hw);
2006
2007                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2008                         PMD_INIT_LOG(INFO,
2009                                 "lsc won't enable because of no intr multiplex");
2010         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2011                 ret = i40e_aq_set_phy_int_mask(hw,
2012                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2013                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2014                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2015                 if (ret != I40E_SUCCESS)
2016                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2017
2018                 /* Call get_link_info aq commond to enable LSE */
2019                 i40e_dev_link_update(dev, 0);
2020         }
2021
2022         /* enable uio intr after callback register */
2023         rte_intr_enable(intr_handle);
2024
2025         i40e_filter_restore(pf);
2026
2027         return I40E_SUCCESS;
2028
2029 err_up:
2030         i40e_dev_switch_queues(pf, FALSE);
2031         i40e_dev_clear_queues(dev);
2032
2033         return ret;
2034 }
2035
2036 static void
2037 i40e_dev_stop(struct rte_eth_dev *dev)
2038 {
2039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2040         struct i40e_vsi *main_vsi = pf->main_vsi;
2041         struct i40e_mirror_rule *p_mirror;
2042         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2043         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2044         int i;
2045
2046         /* Disable all queues */
2047         i40e_dev_switch_queues(pf, FALSE);
2048
2049         /* un-map queues with interrupt registers */
2050         i40e_vsi_disable_queues_intr(main_vsi);
2051         i40e_vsi_queues_unbind_intr(main_vsi);
2052
2053         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2054                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2055                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2056         }
2057
2058         if (pf->fdir.fdir_vsi) {
2059                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2060                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2061         }
2062         /* Clear all queues and release memory */
2063         i40e_dev_clear_queues(dev);
2064
2065         /* Set link down */
2066         i40e_dev_set_link_down(dev);
2067
2068         /* Remove all mirror rules */
2069         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2070                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2071                 rte_free(p_mirror);
2072         }
2073         pf->nb_mirror_rule = 0;
2074
2075         if (!rte_intr_allow_others(intr_handle))
2076                 /* resume to the default handler */
2077                 rte_intr_callback_register(intr_handle,
2078                                            i40e_dev_interrupt_handler,
2079                                            (void *)dev);
2080
2081         /* Clean datapath event and queue/vec mapping */
2082         rte_intr_efd_disable(intr_handle);
2083         if (intr_handle->intr_vec) {
2084                 rte_free(intr_handle->intr_vec);
2085                 intr_handle->intr_vec = NULL;
2086         }
2087 }
2088
2089 static void
2090 i40e_dev_close(struct rte_eth_dev *dev)
2091 {
2092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2093         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2096         uint32_t reg;
2097         int i;
2098
2099         PMD_INIT_FUNC_TRACE();
2100
2101         i40e_dev_stop(dev);
2102         hw->adapter_stopped = 1;
2103         i40e_dev_free_queues(dev);
2104
2105         /* Disable interrupt */
2106         i40e_pf_disable_irq0(hw);
2107         rte_intr_disable(intr_handle);
2108
2109         /* shutdown and destroy the HMC */
2110         i40e_shutdown_lan_hmc(hw);
2111
2112         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2113                 i40e_vsi_release(pf->vmdq[i].vsi);
2114                 pf->vmdq[i].vsi = NULL;
2115         }
2116         rte_free(pf->vmdq);
2117         pf->vmdq = NULL;
2118
2119         /* release all the existing VSIs and VEBs */
2120         i40e_fdir_teardown(pf);
2121         i40e_vsi_release(pf->main_vsi);
2122
2123         /* shutdown the adminq */
2124         i40e_aq_queue_shutdown(hw, true);
2125         i40e_shutdown_adminq(hw);
2126
2127         i40e_res_pool_destroy(&pf->qp_pool);
2128         i40e_res_pool_destroy(&pf->msix_pool);
2129
2130         /* force a PF reset to clean anything leftover */
2131         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2132         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2133                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2134         I40E_WRITE_FLUSH(hw);
2135 }
2136
2137 static void
2138 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2139 {
2140         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct i40e_vsi *vsi = pf->main_vsi;
2143         int status;
2144
2145         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2146                                                      true, NULL, true);
2147         if (status != I40E_SUCCESS)
2148                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2149
2150         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2151                                                         TRUE, NULL);
2152         if (status != I40E_SUCCESS)
2153                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2154
2155 }
2156
2157 static void
2158 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2159 {
2160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2161         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162         struct i40e_vsi *vsi = pf->main_vsi;
2163         int status;
2164
2165         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2166                                                      false, NULL, true);
2167         if (status != I40E_SUCCESS)
2168                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2169
2170         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2171                                                         false, NULL);
2172         if (status != I40E_SUCCESS)
2173                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2174 }
2175
2176 static void
2177 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2178 {
2179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2180         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181         struct i40e_vsi *vsi = pf->main_vsi;
2182         int ret;
2183
2184         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2185         if (ret != I40E_SUCCESS)
2186                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2187 }
2188
2189 static void
2190 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         struct i40e_vsi *vsi = pf->main_vsi;
2195         int ret;
2196
2197         if (dev->data->promiscuous == 1)
2198                 return; /* must remain in all_multicast mode */
2199
2200         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2201                                 vsi->seid, FALSE, NULL);
2202         if (ret != I40E_SUCCESS)
2203                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2204 }
2205
2206 /*
2207  * Set device link up.
2208  */
2209 static int
2210 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2211 {
2212         /* re-apply link speed setting */
2213         return i40e_apply_link_speed(dev);
2214 }
2215
2216 /*
2217  * Set device link down.
2218  */
2219 static int
2220 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2221 {
2222         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2223         uint8_t abilities = 0;
2224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225
2226         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2227         return i40e_phy_conf_link(hw, abilities, speed);
2228 }
2229
2230 int
2231 i40e_dev_link_update(struct rte_eth_dev *dev,
2232                      int wait_to_complete)
2233 {
2234 #define CHECK_INTERVAL 100  /* 100ms */
2235 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         struct i40e_link_status link_status;
2238         struct rte_eth_link link, old;
2239         int status;
2240         unsigned rep_cnt = MAX_REPEAT_TIME;
2241         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2242
2243         memset(&link, 0, sizeof(link));
2244         memset(&old, 0, sizeof(old));
2245         memset(&link_status, 0, sizeof(link_status));
2246         rte_i40e_dev_atomic_read_link_status(dev, &old);
2247
2248         do {
2249                 /* Get link status information from hardware */
2250                 status = i40e_aq_get_link_info(hw, enable_lse,
2251                                                 &link_status, NULL);
2252                 if (status != I40E_SUCCESS) {
2253                         link.link_speed = ETH_SPEED_NUM_100M;
2254                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2255                         PMD_DRV_LOG(ERR, "Failed to get link info");
2256                         goto out;
2257                 }
2258
2259                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2260                 if (!wait_to_complete || link.link_status)
2261                         break;
2262
2263                 rte_delay_ms(CHECK_INTERVAL);
2264         } while (--rep_cnt);
2265
2266         if (!link.link_status)
2267                 goto out;
2268
2269         /* i40e uses full duplex only */
2270         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2271
2272         /* Parse the link status */
2273         switch (link_status.link_speed) {
2274         case I40E_LINK_SPEED_100MB:
2275                 link.link_speed = ETH_SPEED_NUM_100M;
2276                 break;
2277         case I40E_LINK_SPEED_1GB:
2278                 link.link_speed = ETH_SPEED_NUM_1G;
2279                 break;
2280         case I40E_LINK_SPEED_10GB:
2281                 link.link_speed = ETH_SPEED_NUM_10G;
2282                 break;
2283         case I40E_LINK_SPEED_20GB:
2284                 link.link_speed = ETH_SPEED_NUM_20G;
2285                 break;
2286         case I40E_LINK_SPEED_25GB:
2287                 link.link_speed = ETH_SPEED_NUM_25G;
2288                 break;
2289         case I40E_LINK_SPEED_40GB:
2290                 link.link_speed = ETH_SPEED_NUM_40G;
2291                 break;
2292         default:
2293                 link.link_speed = ETH_SPEED_NUM_100M;
2294                 break;
2295         }
2296
2297         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2298                         ETH_LINK_SPEED_FIXED);
2299
2300 out:
2301         rte_i40e_dev_atomic_write_link_status(dev, &link);
2302         if (link.link_status == old.link_status)
2303                 return -1;
2304
2305         return 0;
2306 }
2307
2308 /* Get all the statistics of a VSI */
2309 void
2310 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2311 {
2312         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2313         struct i40e_eth_stats *nes = &vsi->eth_stats;
2314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2315         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2316
2317         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2318                             vsi->offset_loaded, &oes->rx_bytes,
2319                             &nes->rx_bytes);
2320         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2321                             vsi->offset_loaded, &oes->rx_unicast,
2322                             &nes->rx_unicast);
2323         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2324                             vsi->offset_loaded, &oes->rx_multicast,
2325                             &nes->rx_multicast);
2326         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2327                             vsi->offset_loaded, &oes->rx_broadcast,
2328                             &nes->rx_broadcast);
2329         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2330                             &oes->rx_discards, &nes->rx_discards);
2331         /* GLV_REPC not supported */
2332         /* GLV_RMPC not supported */
2333         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2334                             &oes->rx_unknown_protocol,
2335                             &nes->rx_unknown_protocol);
2336         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2337                             vsi->offset_loaded, &oes->tx_bytes,
2338                             &nes->tx_bytes);
2339         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2340                             vsi->offset_loaded, &oes->tx_unicast,
2341                             &nes->tx_unicast);
2342         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2343                             vsi->offset_loaded, &oes->tx_multicast,
2344                             &nes->tx_multicast);
2345         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2346                             vsi->offset_loaded,  &oes->tx_broadcast,
2347                             &nes->tx_broadcast);
2348         /* GLV_TDPC not supported */
2349         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2350                             &oes->tx_errors, &nes->tx_errors);
2351         vsi->offset_loaded = true;
2352
2353         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2354                     vsi->vsi_id);
2355         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2356         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2357         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2358         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2359         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2360         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2361                     nes->rx_unknown_protocol);
2362         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2363         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2364         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2365         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2366         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2367         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2368         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2369                     vsi->vsi_id);
2370 }
2371
2372 static void
2373 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2374 {
2375         unsigned int i;
2376         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2377         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2378
2379         /* Get statistics of struct i40e_eth_stats */
2380         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2381                             I40E_GLPRT_GORCL(hw->port),
2382                             pf->offset_loaded, &os->eth.rx_bytes,
2383                             &ns->eth.rx_bytes);
2384         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2385                             I40E_GLPRT_UPRCL(hw->port),
2386                             pf->offset_loaded, &os->eth.rx_unicast,
2387                             &ns->eth.rx_unicast);
2388         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2389                             I40E_GLPRT_MPRCL(hw->port),
2390                             pf->offset_loaded, &os->eth.rx_multicast,
2391                             &ns->eth.rx_multicast);
2392         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2393                             I40E_GLPRT_BPRCL(hw->port),
2394                             pf->offset_loaded, &os->eth.rx_broadcast,
2395                             &ns->eth.rx_broadcast);
2396         /* Workaround: CRC size should not be included in byte statistics,
2397          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2398          */
2399         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2400                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2401
2402         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2403                             pf->offset_loaded, &os->eth.rx_discards,
2404                             &ns->eth.rx_discards);
2405         /* GLPRT_REPC not supported */
2406         /* GLPRT_RMPC not supported */
2407         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2408                             pf->offset_loaded,
2409                             &os->eth.rx_unknown_protocol,
2410                             &ns->eth.rx_unknown_protocol);
2411         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2412                             I40E_GLPRT_GOTCL(hw->port),
2413                             pf->offset_loaded, &os->eth.tx_bytes,
2414                             &ns->eth.tx_bytes);
2415         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2416                             I40E_GLPRT_UPTCL(hw->port),
2417                             pf->offset_loaded, &os->eth.tx_unicast,
2418                             &ns->eth.tx_unicast);
2419         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2420                             I40E_GLPRT_MPTCL(hw->port),
2421                             pf->offset_loaded, &os->eth.tx_multicast,
2422                             &ns->eth.tx_multicast);
2423         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2424                             I40E_GLPRT_BPTCL(hw->port),
2425                             pf->offset_loaded, &os->eth.tx_broadcast,
2426                             &ns->eth.tx_broadcast);
2427         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2428                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2429         /* GLPRT_TEPC not supported */
2430
2431         /* additional port specific stats */
2432         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2433                             pf->offset_loaded, &os->tx_dropped_link_down,
2434                             &ns->tx_dropped_link_down);
2435         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2436                             pf->offset_loaded, &os->crc_errors,
2437                             &ns->crc_errors);
2438         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2439                             pf->offset_loaded, &os->illegal_bytes,
2440                             &ns->illegal_bytes);
2441         /* GLPRT_ERRBC not supported */
2442         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2443                             pf->offset_loaded, &os->mac_local_faults,
2444                             &ns->mac_local_faults);
2445         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2446                             pf->offset_loaded, &os->mac_remote_faults,
2447                             &ns->mac_remote_faults);
2448         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2449                             pf->offset_loaded, &os->rx_length_errors,
2450                             &ns->rx_length_errors);
2451         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2452                             pf->offset_loaded, &os->link_xon_rx,
2453                             &ns->link_xon_rx);
2454         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2455                             pf->offset_loaded, &os->link_xoff_rx,
2456                             &ns->link_xoff_rx);
2457         for (i = 0; i < 8; i++) {
2458                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2459                                     pf->offset_loaded,
2460                                     &os->priority_xon_rx[i],
2461                                     &ns->priority_xon_rx[i]);
2462                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2463                                     pf->offset_loaded,
2464                                     &os->priority_xoff_rx[i],
2465                                     &ns->priority_xoff_rx[i]);
2466         }
2467         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2468                             pf->offset_loaded, &os->link_xon_tx,
2469                             &ns->link_xon_tx);
2470         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2471                             pf->offset_loaded, &os->link_xoff_tx,
2472                             &ns->link_xoff_tx);
2473         for (i = 0; i < 8; i++) {
2474                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2475                                     pf->offset_loaded,
2476                                     &os->priority_xon_tx[i],
2477                                     &ns->priority_xon_tx[i]);
2478                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2479                                     pf->offset_loaded,
2480                                     &os->priority_xoff_tx[i],
2481                                     &ns->priority_xoff_tx[i]);
2482                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2483                                     pf->offset_loaded,
2484                                     &os->priority_xon_2_xoff[i],
2485                                     &ns->priority_xon_2_xoff[i]);
2486         }
2487         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2488                             I40E_GLPRT_PRC64L(hw->port),
2489                             pf->offset_loaded, &os->rx_size_64,
2490                             &ns->rx_size_64);
2491         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2492                             I40E_GLPRT_PRC127L(hw->port),
2493                             pf->offset_loaded, &os->rx_size_127,
2494                             &ns->rx_size_127);
2495         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2496                             I40E_GLPRT_PRC255L(hw->port),
2497                             pf->offset_loaded, &os->rx_size_255,
2498                             &ns->rx_size_255);
2499         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2500                             I40E_GLPRT_PRC511L(hw->port),
2501                             pf->offset_loaded, &os->rx_size_511,
2502                             &ns->rx_size_511);
2503         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2504                             I40E_GLPRT_PRC1023L(hw->port),
2505                             pf->offset_loaded, &os->rx_size_1023,
2506                             &ns->rx_size_1023);
2507         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2508                             I40E_GLPRT_PRC1522L(hw->port),
2509                             pf->offset_loaded, &os->rx_size_1522,
2510                             &ns->rx_size_1522);
2511         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2512                             I40E_GLPRT_PRC9522L(hw->port),
2513                             pf->offset_loaded, &os->rx_size_big,
2514                             &ns->rx_size_big);
2515         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2516                             pf->offset_loaded, &os->rx_undersize,
2517                             &ns->rx_undersize);
2518         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2519                             pf->offset_loaded, &os->rx_fragments,
2520                             &ns->rx_fragments);
2521         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2522                             pf->offset_loaded, &os->rx_oversize,
2523                             &ns->rx_oversize);
2524         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2525                             pf->offset_loaded, &os->rx_jabber,
2526                             &ns->rx_jabber);
2527         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2528                             I40E_GLPRT_PTC64L(hw->port),
2529                             pf->offset_loaded, &os->tx_size_64,
2530                             &ns->tx_size_64);
2531         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2532                             I40E_GLPRT_PTC127L(hw->port),
2533                             pf->offset_loaded, &os->tx_size_127,
2534                             &ns->tx_size_127);
2535         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2536                             I40E_GLPRT_PTC255L(hw->port),
2537                             pf->offset_loaded, &os->tx_size_255,
2538                             &ns->tx_size_255);
2539         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2540                             I40E_GLPRT_PTC511L(hw->port),
2541                             pf->offset_loaded, &os->tx_size_511,
2542                             &ns->tx_size_511);
2543         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2544                             I40E_GLPRT_PTC1023L(hw->port),
2545                             pf->offset_loaded, &os->tx_size_1023,
2546                             &ns->tx_size_1023);
2547         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2548                             I40E_GLPRT_PTC1522L(hw->port),
2549                             pf->offset_loaded, &os->tx_size_1522,
2550                             &ns->tx_size_1522);
2551         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2552                             I40E_GLPRT_PTC9522L(hw->port),
2553                             pf->offset_loaded, &os->tx_size_big,
2554                             &ns->tx_size_big);
2555         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2556                            pf->offset_loaded,
2557                            &os->fd_sb_match, &ns->fd_sb_match);
2558         /* GLPRT_MSPDC not supported */
2559         /* GLPRT_XEC not supported */
2560
2561         pf->offset_loaded = true;
2562
2563         if (pf->main_vsi)
2564                 i40e_update_vsi_stats(pf->main_vsi);
2565 }
2566
2567 /* Get all statistics of a port */
2568 static void
2569 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2574         unsigned i;
2575
2576         /* call read registers - updates values, now write them to struct */
2577         i40e_read_stats_registers(pf, hw);
2578
2579         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2580                         pf->main_vsi->eth_stats.rx_multicast +
2581                         pf->main_vsi->eth_stats.rx_broadcast -
2582                         pf->main_vsi->eth_stats.rx_discards;
2583         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2584                         pf->main_vsi->eth_stats.tx_multicast +
2585                         pf->main_vsi->eth_stats.tx_broadcast;
2586         stats->ibytes   = ns->eth.rx_bytes;
2587         stats->obytes   = ns->eth.tx_bytes;
2588         stats->oerrors  = ns->eth.tx_errors +
2589                         pf->main_vsi->eth_stats.tx_errors;
2590
2591         /* Rx Errors */
2592         stats->imissed  = ns->eth.rx_discards +
2593                         pf->main_vsi->eth_stats.rx_discards;
2594         stats->ierrors  = ns->crc_errors +
2595                         ns->rx_length_errors + ns->rx_undersize +
2596                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2597
2598         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2599         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2600         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2601         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2602         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2603         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2604         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2605                     ns->eth.rx_unknown_protocol);
2606         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2607         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2608         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2609         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2610         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2611         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2612
2613         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2614                     ns->tx_dropped_link_down);
2615         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2616         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2617                     ns->illegal_bytes);
2618         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2619         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2620                     ns->mac_local_faults);
2621         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2622                     ns->mac_remote_faults);
2623         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2624                     ns->rx_length_errors);
2625         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2626         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2627         for (i = 0; i < 8; i++) {
2628                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2629                                 i, ns->priority_xon_rx[i]);
2630                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2631                                 i, ns->priority_xoff_rx[i]);
2632         }
2633         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2634         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2635         for (i = 0; i < 8; i++) {
2636                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2637                                 i, ns->priority_xon_tx[i]);
2638                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2639                                 i, ns->priority_xoff_tx[i]);
2640                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2641                                 i, ns->priority_xon_2_xoff[i]);
2642         }
2643         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2644         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2645         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2646         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2647         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2648         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2649         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2650         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2651         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2652         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2653         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2654         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2655         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2656         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2657         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2658         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2659         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2660         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2661         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2662                         ns->mac_short_packet_dropped);
2663         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2664                     ns->checksum_error);
2665         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2666         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2667 }
2668
2669 /* Reset the statistics */
2670 static void
2671 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2672 {
2673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675
2676         /* Mark PF and VSI stats to update the offset, aka "reset" */
2677         pf->offset_loaded = false;
2678         if (pf->main_vsi)
2679                 pf->main_vsi->offset_loaded = false;
2680
2681         /* read the stats, reading current register values into offset */
2682         i40e_read_stats_registers(pf, hw);
2683 }
2684
2685 static uint32_t
2686 i40e_xstats_calc_num(void)
2687 {
2688         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2689                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2690                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2691 }
2692
2693 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2694                                      struct rte_eth_xstat_name *xstats_names,
2695                                      __rte_unused unsigned limit)
2696 {
2697         unsigned count = 0;
2698         unsigned i, prio;
2699
2700         if (xstats_names == NULL)
2701                 return i40e_xstats_calc_num();
2702
2703         /* Note: limit checked in rte_eth_xstats_names() */
2704
2705         /* Get stats from i40e_eth_stats struct */
2706         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2707                 snprintf(xstats_names[count].name,
2708                          sizeof(xstats_names[count].name),
2709                          "%s", rte_i40e_stats_strings[i].name);
2710                 count++;
2711         }
2712
2713         /* Get individiual stats from i40e_hw_port struct */
2714         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2715                 snprintf(xstats_names[count].name,
2716                         sizeof(xstats_names[count].name),
2717                          "%s", rte_i40e_hw_port_strings[i].name);
2718                 count++;
2719         }
2720
2721         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2722                 for (prio = 0; prio < 8; prio++) {
2723                         snprintf(xstats_names[count].name,
2724                                  sizeof(xstats_names[count].name),
2725                                  "rx_priority%u_%s", prio,
2726                                  rte_i40e_rxq_prio_strings[i].name);
2727                         count++;
2728                 }
2729         }
2730
2731         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2732                 for (prio = 0; prio < 8; prio++) {
2733                         snprintf(xstats_names[count].name,
2734                                  sizeof(xstats_names[count].name),
2735                                  "tx_priority%u_%s", prio,
2736                                  rte_i40e_txq_prio_strings[i].name);
2737                         count++;
2738                 }
2739         }
2740         return count;
2741 }
2742
2743 static int
2744 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2745                     unsigned n)
2746 {
2747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749         unsigned i, count, prio;
2750         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2751
2752         count = i40e_xstats_calc_num();
2753         if (n < count)
2754                 return count;
2755
2756         i40e_read_stats_registers(pf, hw);
2757
2758         if (xstats == NULL)
2759                 return 0;
2760
2761         count = 0;
2762
2763         /* Get stats from i40e_eth_stats struct */
2764         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2765                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2766                         rte_i40e_stats_strings[i].offset);
2767                 xstats[count].id = count;
2768                 count++;
2769         }
2770
2771         /* Get individiual stats from i40e_hw_port struct */
2772         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2773                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2774                         rte_i40e_hw_port_strings[i].offset);
2775                 xstats[count].id = count;
2776                 count++;
2777         }
2778
2779         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2780                 for (prio = 0; prio < 8; prio++) {
2781                         xstats[count].value =
2782                                 *(uint64_t *)(((char *)hw_stats) +
2783                                 rte_i40e_rxq_prio_strings[i].offset +
2784                                 (sizeof(uint64_t) * prio));
2785                         xstats[count].id = count;
2786                         count++;
2787                 }
2788         }
2789
2790         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2791                 for (prio = 0; prio < 8; prio++) {
2792                         xstats[count].value =
2793                                 *(uint64_t *)(((char *)hw_stats) +
2794                                 rte_i40e_txq_prio_strings[i].offset +
2795                                 (sizeof(uint64_t) * prio));
2796                         xstats[count].id = count;
2797                         count++;
2798                 }
2799         }
2800
2801         return count;
2802 }
2803
2804 static int
2805 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2806                                  __rte_unused uint16_t queue_id,
2807                                  __rte_unused uint8_t stat_idx,
2808                                  __rte_unused uint8_t is_rx)
2809 {
2810         PMD_INIT_FUNC_TRACE();
2811
2812         return -ENOSYS;
2813 }
2814
2815 static int
2816 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2817 {
2818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         u32 full_ver;
2820         u8 ver, patch;
2821         u16 build;
2822         int ret;
2823
2824         full_ver = hw->nvm.oem_ver;
2825         ver = (u8)(full_ver >> 24);
2826         build = (u16)((full_ver >> 8) & 0xffff);
2827         patch = (u8)(full_ver & 0xff);
2828
2829         ret = snprintf(fw_version, fw_size,
2830                  "%d.%d%d 0x%08x %d.%d.%d",
2831                  ((hw->nvm.version >> 12) & 0xf),
2832                  ((hw->nvm.version >> 4) & 0xff),
2833                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2834                  ver, build, patch);
2835
2836         ret += 1; /* add the size of '\0' */
2837         if (fw_size < (u32)ret)
2838                 return ret;
2839         else
2840                 return 0;
2841 }
2842
2843 static void
2844 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2845 {
2846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848         struct i40e_vsi *vsi = pf->main_vsi;
2849         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2850
2851         dev_info->pci_dev = pci_dev;
2852         dev_info->max_rx_queues = vsi->nb_qps;
2853         dev_info->max_tx_queues = vsi->nb_qps;
2854         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2855         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2856         dev_info->max_mac_addrs = vsi->max_macaddrs;
2857         dev_info->max_vfs = pci_dev->max_vfs;
2858         dev_info->rx_offload_capa =
2859                 DEV_RX_OFFLOAD_VLAN_STRIP |
2860                 DEV_RX_OFFLOAD_QINQ_STRIP |
2861                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2862                 DEV_RX_OFFLOAD_UDP_CKSUM |
2863                 DEV_RX_OFFLOAD_TCP_CKSUM;
2864         dev_info->tx_offload_capa =
2865                 DEV_TX_OFFLOAD_VLAN_INSERT |
2866                 DEV_TX_OFFLOAD_QINQ_INSERT |
2867                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2868                 DEV_TX_OFFLOAD_UDP_CKSUM |
2869                 DEV_TX_OFFLOAD_TCP_CKSUM |
2870                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2871                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2872                 DEV_TX_OFFLOAD_TCP_TSO |
2873                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2874                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2875                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2876                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2877         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2878                                                 sizeof(uint32_t);
2879         dev_info->reta_size = pf->hash_lut_size;
2880         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2881
2882         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2883                 .rx_thresh = {
2884                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2885                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2886                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2887                 },
2888                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2889                 .rx_drop_en = 0,
2890         };
2891
2892         dev_info->default_txconf = (struct rte_eth_txconf) {
2893                 .tx_thresh = {
2894                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2895                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2896                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2897                 },
2898                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2899                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2900                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2901                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2902         };
2903
2904         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2905                 .nb_max = I40E_MAX_RING_DESC,
2906                 .nb_min = I40E_MIN_RING_DESC,
2907                 .nb_align = I40E_ALIGN_RING_DESC,
2908         };
2909
2910         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2911                 .nb_max = I40E_MAX_RING_DESC,
2912                 .nb_min = I40E_MIN_RING_DESC,
2913                 .nb_align = I40E_ALIGN_RING_DESC,
2914                 .nb_seg_max = I40E_TX_MAX_SEG,
2915                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2916         };
2917
2918         if (pf->flags & I40E_FLAG_VMDQ) {
2919                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2920                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2921                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2922                                                 pf->max_nb_vmdq_vsi;
2923                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2924                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2925                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2926         }
2927
2928         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2929                 /* For XL710 */
2930                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2931         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2932                 /* For XXV710 */
2933                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2934         else
2935                 /* For X710 */
2936                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2937 }
2938
2939 static int
2940 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2941 {
2942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2943         struct i40e_vsi *vsi = pf->main_vsi;
2944         PMD_INIT_FUNC_TRACE();
2945
2946         if (on)
2947                 return i40e_vsi_add_vlan(vsi, vlan_id);
2948         else
2949                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2950 }
2951
2952 static int
2953 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2954                    enum rte_vlan_type vlan_type,
2955                    uint16_t tpid)
2956 {
2957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         uint64_t reg_r = 0, reg_w = 0;
2959         uint16_t reg_id = 0;
2960         int ret = 0;
2961         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2962
2963         switch (vlan_type) {
2964         case ETH_VLAN_TYPE_OUTER:
2965                 if (qinq)
2966                         reg_id = 2;
2967                 else
2968                         reg_id = 3;
2969                 break;
2970         case ETH_VLAN_TYPE_INNER:
2971                 if (qinq)
2972                         reg_id = 3;
2973                 else {
2974                         ret = -EINVAL;
2975                         PMD_DRV_LOG(ERR,
2976                                 "Unsupported vlan type in single vlan.");
2977                         return ret;
2978                 }
2979                 break;
2980         default:
2981                 ret = -EINVAL;
2982                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2983                 return ret;
2984         }
2985         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2986                                           &reg_r, NULL);
2987         if (ret != I40E_SUCCESS) {
2988                 PMD_DRV_LOG(ERR,
2989                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2990                            reg_id);
2991                 ret = -EIO;
2992                 return ret;
2993         }
2994         PMD_DRV_LOG(DEBUG,
2995                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2996                 reg_id, reg_r);
2997
2998         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2999         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3000         if (reg_r == reg_w) {
3001                 ret = 0;
3002                 PMD_DRV_LOG(DEBUG, "No need to write");
3003                 return ret;
3004         }
3005
3006         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3007                                            reg_w, NULL);
3008         if (ret != I40E_SUCCESS) {
3009                 ret = -EIO;
3010                 PMD_DRV_LOG(ERR,
3011                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3012                         reg_id);
3013                 return ret;
3014         }
3015         PMD_DRV_LOG(DEBUG,
3016                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3017                 reg_w, reg_id);
3018
3019         return ret;
3020 }
3021
3022 static void
3023 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3024 {
3025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3026         struct i40e_vsi *vsi = pf->main_vsi;
3027
3028         if (mask & ETH_VLAN_FILTER_MASK) {
3029                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3030                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3031                 else
3032                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3033         }
3034
3035         if (mask & ETH_VLAN_STRIP_MASK) {
3036                 /* Enable or disable VLAN stripping */
3037                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3038                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3039                 else
3040                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3041         }
3042
3043         if (mask & ETH_VLAN_EXTEND_MASK) {
3044                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3045                         i40e_vsi_config_double_vlan(vsi, TRUE);
3046                         /* Set global registers with default ether type value */
3047                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3048                                            ETHER_TYPE_VLAN);
3049                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3050                                            ETHER_TYPE_VLAN);
3051                 }
3052                 else
3053                         i40e_vsi_config_double_vlan(vsi, FALSE);
3054         }
3055 }
3056
3057 static void
3058 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3059                           __rte_unused uint16_t queue,
3060                           __rte_unused int on)
3061 {
3062         PMD_INIT_FUNC_TRACE();
3063 }
3064
3065 static int
3066 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3067 {
3068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3069         struct i40e_vsi *vsi = pf->main_vsi;
3070         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3071         struct i40e_vsi_vlan_pvid_info info;
3072
3073         memset(&info, 0, sizeof(info));
3074         info.on = on;
3075         if (info.on)
3076                 info.config.pvid = pvid;
3077         else {
3078                 info.config.reject.tagged =
3079                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3080                 info.config.reject.untagged =
3081                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3082         }
3083
3084         return i40e_vsi_vlan_pvid_set(vsi, &info);
3085 }
3086
3087 static int
3088 i40e_dev_led_on(struct rte_eth_dev *dev)
3089 {
3090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         uint32_t mode = i40e_led_get(hw);
3092
3093         if (mode == 0)
3094                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3095
3096         return 0;
3097 }
3098
3099 static int
3100 i40e_dev_led_off(struct rte_eth_dev *dev)
3101 {
3102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3103         uint32_t mode = i40e_led_get(hw);
3104
3105         if (mode != 0)
3106                 i40e_led_set(hw, 0, false);
3107
3108         return 0;
3109 }
3110
3111 static int
3112 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3113 {
3114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3116
3117         fc_conf->pause_time = pf->fc_conf.pause_time;
3118         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3119         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3120
3121          /* Return current mode according to actual setting*/
3122         switch (hw->fc.current_mode) {
3123         case I40E_FC_FULL:
3124                 fc_conf->mode = RTE_FC_FULL;
3125                 break;
3126         case I40E_FC_TX_PAUSE:
3127                 fc_conf->mode = RTE_FC_TX_PAUSE;
3128                 break;
3129         case I40E_FC_RX_PAUSE:
3130                 fc_conf->mode = RTE_FC_RX_PAUSE;
3131                 break;
3132         case I40E_FC_NONE:
3133         default:
3134                 fc_conf->mode = RTE_FC_NONE;
3135         };
3136
3137         return 0;
3138 }
3139
3140 static int
3141 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3142 {
3143         uint32_t mflcn_reg, fctrl_reg, reg;
3144         uint32_t max_high_water;
3145         uint8_t i, aq_failure;
3146         int err;
3147         struct i40e_hw *hw;
3148         struct i40e_pf *pf;
3149         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3150                 [RTE_FC_NONE] = I40E_FC_NONE,
3151                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3152                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3153                 [RTE_FC_FULL] = I40E_FC_FULL
3154         };
3155
3156         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3157
3158         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3159         if ((fc_conf->high_water > max_high_water) ||
3160                         (fc_conf->high_water < fc_conf->low_water)) {
3161                 PMD_INIT_LOG(ERR,
3162                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3163                         max_high_water);
3164                 return -EINVAL;
3165         }
3166
3167         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3168         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3170
3171         pf->fc_conf.pause_time = fc_conf->pause_time;
3172         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3173         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3174
3175         PMD_INIT_FUNC_TRACE();
3176
3177         /* All the link flow control related enable/disable register
3178          * configuration is handle by the F/W
3179          */
3180         err = i40e_set_fc(hw, &aq_failure, true);
3181         if (err < 0)
3182                 return -ENOSYS;
3183
3184         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3185                 /* Configure flow control refresh threshold,
3186                  * the value for stat_tx_pause_refresh_timer[8]
3187                  * is used for global pause operation.
3188                  */
3189
3190                 I40E_WRITE_REG(hw,
3191                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3192                                pf->fc_conf.pause_time);
3193
3194                 /* configure the timer value included in transmitted pause
3195                  * frame,
3196                  * the value for stat_tx_pause_quanta[8] is used for global
3197                  * pause operation
3198                  */
3199                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3200                                pf->fc_conf.pause_time);
3201
3202                 fctrl_reg = I40E_READ_REG(hw,
3203                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3204
3205                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3206                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3207                 else
3208                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3209
3210                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3211                                fctrl_reg);
3212         } else {
3213                 /* Configure pause time (2 TCs per register) */
3214                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3215                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3216                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3217
3218                 /* Configure flow control refresh threshold value */
3219                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3220                                pf->fc_conf.pause_time / 2);
3221
3222                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3223
3224                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3225                  *depending on configuration
3226                  */
3227                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3228                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3229                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3230                 } else {
3231                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3232                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3233                 }
3234
3235                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3236         }
3237
3238         /* config the water marker both based on the packets and bytes */
3239         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3240                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3241                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3242         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3243                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3244                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3245         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3246                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3247                        << I40E_KILOSHIFT);
3248         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3249                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3250                        << I40E_KILOSHIFT);
3251
3252         I40E_WRITE_FLUSH(hw);
3253
3254         return 0;
3255 }
3256
3257 static int
3258 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3259                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3260 {
3261         PMD_INIT_FUNC_TRACE();
3262
3263         return -ENOSYS;
3264 }
3265
3266 /* Add a MAC address, and update filters */
3267 static void
3268 i40e_macaddr_add(struct rte_eth_dev *dev,
3269                  struct ether_addr *mac_addr,
3270                  __rte_unused uint32_t index,
3271                  uint32_t pool)
3272 {
3273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3274         struct i40e_mac_filter_info mac_filter;
3275         struct i40e_vsi *vsi;
3276         int ret;
3277
3278         /* If VMDQ not enabled or configured, return */
3279         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3280                           !pf->nb_cfg_vmdq_vsi)) {
3281                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3282                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3283                         pool);
3284                 return;
3285         }
3286
3287         if (pool > pf->nb_cfg_vmdq_vsi) {
3288                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3289                                 pool, pf->nb_cfg_vmdq_vsi);
3290                 return;
3291         }
3292
3293         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3294         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3295                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3296         else
3297                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3298
3299         if (pool == 0)
3300                 vsi = pf->main_vsi;
3301         else
3302                 vsi = pf->vmdq[pool - 1].vsi;
3303
3304         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3305         if (ret != I40E_SUCCESS) {
3306                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3307                 return;
3308         }
3309 }
3310
3311 /* Remove a MAC address, and update filters */
3312 static void
3313 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3314 {
3315         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3316         struct i40e_vsi *vsi;
3317         struct rte_eth_dev_data *data = dev->data;
3318         struct ether_addr *macaddr;
3319         int ret;
3320         uint32_t i;
3321         uint64_t pool_sel;
3322
3323         macaddr = &(data->mac_addrs[index]);
3324
3325         pool_sel = dev->data->mac_pool_sel[index];
3326
3327         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3328                 if (pool_sel & (1ULL << i)) {
3329                         if (i == 0)
3330                                 vsi = pf->main_vsi;
3331                         else {
3332                                 /* No VMDQ pool enabled or configured */
3333                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3334                                         (i > pf->nb_cfg_vmdq_vsi)) {
3335                                         PMD_DRV_LOG(ERR,
3336                                                 "No VMDQ pool enabled/configured");
3337                                         return;
3338                                 }
3339                                 vsi = pf->vmdq[i - 1].vsi;
3340                         }
3341                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3342
3343                         if (ret) {
3344                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3345                                 return;
3346                         }
3347                 }
3348         }
3349 }
3350
3351 /* Set perfect match or hash match of MAC and VLAN for a VF */
3352 static int
3353 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3354                  struct rte_eth_mac_filter *filter,
3355                  bool add)
3356 {
3357         struct i40e_hw *hw;
3358         struct i40e_mac_filter_info mac_filter;
3359         struct ether_addr old_mac;
3360         struct ether_addr *new_mac;
3361         struct i40e_pf_vf *vf = NULL;
3362         uint16_t vf_id;
3363         int ret;
3364
3365         if (pf == NULL) {
3366                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3367                 return -EINVAL;
3368         }
3369         hw = I40E_PF_TO_HW(pf);
3370
3371         if (filter == NULL) {
3372                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3373                 return -EINVAL;
3374         }
3375
3376         new_mac = &filter->mac_addr;
3377
3378         if (is_zero_ether_addr(new_mac)) {
3379                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3380                 return -EINVAL;
3381         }
3382
3383         vf_id = filter->dst_id;
3384
3385         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3386                 PMD_DRV_LOG(ERR, "Invalid argument.");
3387                 return -EINVAL;
3388         }
3389         vf = &pf->vfs[vf_id];
3390
3391         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3392                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3393                 return -EINVAL;
3394         }
3395
3396         if (add) {
3397                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3398                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3399                                 ETHER_ADDR_LEN);
3400                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3401                                  ETHER_ADDR_LEN);
3402
3403                 mac_filter.filter_type = filter->filter_type;
3404                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3405                 if (ret != I40E_SUCCESS) {
3406                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3407                         return -1;
3408                 }
3409                 ether_addr_copy(new_mac, &pf->dev_addr);
3410         } else {
3411                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3412                                 ETHER_ADDR_LEN);
3413                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3414                 if (ret != I40E_SUCCESS) {
3415                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3416                         return -1;
3417                 }
3418
3419                 /* Clear device address as it has been removed */
3420                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3421                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3422         }
3423
3424         return 0;
3425 }
3426
3427 /* MAC filter handle */
3428 static int
3429 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3430                 void *arg)
3431 {
3432         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3433         struct rte_eth_mac_filter *filter;
3434         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3435         int ret = I40E_NOT_SUPPORTED;
3436
3437         filter = (struct rte_eth_mac_filter *)(arg);
3438
3439         switch (filter_op) {
3440         case RTE_ETH_FILTER_NOP:
3441                 ret = I40E_SUCCESS;
3442                 break;
3443         case RTE_ETH_FILTER_ADD:
3444                 i40e_pf_disable_irq0(hw);
3445                 if (filter->is_vf)
3446                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3447                 i40e_pf_enable_irq0(hw);
3448                 break;
3449         case RTE_ETH_FILTER_DELETE:
3450                 i40e_pf_disable_irq0(hw);
3451                 if (filter->is_vf)
3452                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3453                 i40e_pf_enable_irq0(hw);
3454                 break;
3455         default:
3456                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3457                 ret = I40E_ERR_PARAM;
3458                 break;
3459         }
3460
3461         return ret;
3462 }
3463
3464 static int
3465 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3466 {
3467         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3468         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3469         int ret;
3470
3471         if (!lut)
3472                 return -EINVAL;
3473
3474         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3475                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3476                                           lut, lut_size);
3477                 if (ret) {
3478                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3479                         return ret;
3480                 }
3481         } else {
3482                 uint32_t *lut_dw = (uint32_t *)lut;
3483                 uint16_t i, lut_size_dw = lut_size / 4;
3484
3485                 for (i = 0; i < lut_size_dw; i++)
3486                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3487         }
3488
3489         return 0;
3490 }
3491
3492 static int
3493 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3494 {
3495         struct i40e_pf *pf;
3496         struct i40e_hw *hw;
3497         int ret;
3498
3499         if (!vsi || !lut)
3500                 return -EINVAL;
3501
3502         pf = I40E_VSI_TO_PF(vsi);
3503         hw = I40E_VSI_TO_HW(vsi);
3504
3505         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3506                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3507                                           lut, lut_size);
3508                 if (ret) {
3509                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3510                         return ret;
3511                 }
3512         } else {
3513                 uint32_t *lut_dw = (uint32_t *)lut;
3514                 uint16_t i, lut_size_dw = lut_size / 4;
3515
3516                 for (i = 0; i < lut_size_dw; i++)
3517                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3518                 I40E_WRITE_FLUSH(hw);
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int
3525 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3526                          struct rte_eth_rss_reta_entry64 *reta_conf,
3527                          uint16_t reta_size)
3528 {
3529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530         uint16_t i, lut_size = pf->hash_lut_size;
3531         uint16_t idx, shift;
3532         uint8_t *lut;
3533         int ret;
3534
3535         if (reta_size != lut_size ||
3536                 reta_size > ETH_RSS_RETA_SIZE_512) {
3537                 PMD_DRV_LOG(ERR,
3538                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3539                         reta_size, lut_size);
3540                 return -EINVAL;
3541         }
3542
3543         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3544         if (!lut) {
3545                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3546                 return -ENOMEM;
3547         }
3548         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3549         if (ret)
3550                 goto out;
3551         for (i = 0; i < reta_size; i++) {
3552                 idx = i / RTE_RETA_GROUP_SIZE;
3553                 shift = i % RTE_RETA_GROUP_SIZE;
3554                 if (reta_conf[idx].mask & (1ULL << shift))
3555                         lut[i] = reta_conf[idx].reta[shift];
3556         }
3557         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3558
3559 out:
3560         rte_free(lut);
3561
3562         return ret;
3563 }
3564
3565 static int
3566 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3567                         struct rte_eth_rss_reta_entry64 *reta_conf,
3568                         uint16_t reta_size)
3569 {
3570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3571         uint16_t i, lut_size = pf->hash_lut_size;
3572         uint16_t idx, shift;
3573         uint8_t *lut;
3574         int ret;
3575
3576         if (reta_size != lut_size ||
3577                 reta_size > ETH_RSS_RETA_SIZE_512) {
3578                 PMD_DRV_LOG(ERR,
3579                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3580                         reta_size, lut_size);
3581                 return -EINVAL;
3582         }
3583
3584         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3585         if (!lut) {
3586                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3587                 return -ENOMEM;
3588         }
3589
3590         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3591         if (ret)
3592                 goto out;
3593         for (i = 0; i < reta_size; i++) {
3594                 idx = i / RTE_RETA_GROUP_SIZE;
3595                 shift = i % RTE_RETA_GROUP_SIZE;
3596                 if (reta_conf[idx].mask & (1ULL << shift))
3597                         reta_conf[idx].reta[shift] = lut[i];
3598         }
3599
3600 out:
3601         rte_free(lut);
3602
3603         return ret;
3604 }
3605
3606 /**
3607  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3608  * @hw:   pointer to the HW structure
3609  * @mem:  pointer to mem struct to fill out
3610  * @size: size of memory requested
3611  * @alignment: what to align the allocation to
3612  **/
3613 enum i40e_status_code
3614 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3615                         struct i40e_dma_mem *mem,
3616                         u64 size,
3617                         u32 alignment)
3618 {
3619         const struct rte_memzone *mz = NULL;
3620         char z_name[RTE_MEMZONE_NAMESIZE];
3621
3622         if (!mem)
3623                 return I40E_ERR_PARAM;
3624
3625         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3626         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3627                                          alignment, RTE_PGSIZE_2M);
3628         if (!mz)
3629                 return I40E_ERR_NO_MEMORY;
3630
3631         mem->size = size;
3632         mem->va = mz->addr;
3633         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3634         mem->zone = (const void *)mz;
3635         PMD_DRV_LOG(DEBUG,
3636                 "memzone %s allocated with physical address: %"PRIu64,
3637                 mz->name, mem->pa);
3638
3639         return I40E_SUCCESS;
3640 }
3641
3642 /**
3643  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3644  * @hw:   pointer to the HW structure
3645  * @mem:  ptr to mem struct to free
3646  **/
3647 enum i40e_status_code
3648 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3649                     struct i40e_dma_mem *mem)
3650 {
3651         if (!mem)
3652                 return I40E_ERR_PARAM;
3653
3654         PMD_DRV_LOG(DEBUG,
3655                 "memzone %s to be freed with physical address: %"PRIu64,
3656                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3657         rte_memzone_free((const struct rte_memzone *)mem->zone);
3658         mem->zone = NULL;
3659         mem->va = NULL;
3660         mem->pa = (u64)0;
3661
3662         return I40E_SUCCESS;
3663 }
3664
3665 /**
3666  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3667  * @hw:   pointer to the HW structure
3668  * @mem:  pointer to mem struct to fill out
3669  * @size: size of memory requested
3670  **/
3671 enum i40e_status_code
3672 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3673                          struct i40e_virt_mem *mem,
3674                          u32 size)
3675 {
3676         if (!mem)
3677                 return I40E_ERR_PARAM;
3678
3679         mem->size = size;
3680         mem->va = rte_zmalloc("i40e", size, 0);
3681
3682         if (mem->va)
3683                 return I40E_SUCCESS;
3684         else
3685                 return I40E_ERR_NO_MEMORY;
3686 }
3687
3688 /**
3689  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3690  * @hw:   pointer to the HW structure
3691  * @mem:  pointer to mem struct to free
3692  **/
3693 enum i40e_status_code
3694 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3695                      struct i40e_virt_mem *mem)
3696 {
3697         if (!mem)
3698                 return I40E_ERR_PARAM;
3699
3700         rte_free(mem->va);
3701         mem->va = NULL;
3702
3703         return I40E_SUCCESS;
3704 }
3705
3706 void
3707 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3708 {
3709         rte_spinlock_init(&sp->spinlock);
3710 }
3711
3712 void
3713 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3714 {
3715         rte_spinlock_lock(&sp->spinlock);
3716 }
3717
3718 void
3719 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3720 {
3721         rte_spinlock_unlock(&sp->spinlock);
3722 }
3723
3724 void
3725 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3726 {
3727         return;
3728 }
3729
3730 /**
3731  * Get the hardware capabilities, which will be parsed
3732  * and saved into struct i40e_hw.
3733  */
3734 static int
3735 i40e_get_cap(struct i40e_hw *hw)
3736 {
3737         struct i40e_aqc_list_capabilities_element_resp *buf;
3738         uint16_t len, size = 0;
3739         int ret;
3740
3741         /* Calculate a huge enough buff for saving response data temporarily */
3742         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3743                                                 I40E_MAX_CAP_ELE_NUM;
3744         buf = rte_zmalloc("i40e", len, 0);
3745         if (!buf) {
3746                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3747                 return I40E_ERR_NO_MEMORY;
3748         }
3749
3750         /* Get, parse the capabilities and save it to hw */
3751         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3752                         i40e_aqc_opc_list_func_capabilities, NULL);
3753         if (ret != I40E_SUCCESS)
3754                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3755
3756         /* Free the temporary buffer after being used */
3757         rte_free(buf);
3758
3759         return ret;
3760 }
3761
3762 static int
3763 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3764 {
3765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3767         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3768         uint16_t qp_count = 0, vsi_count = 0;
3769
3770         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3771                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3772                 return -EINVAL;
3773         }
3774         /* Add the parameter init for LFC */
3775         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3776         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3777         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3778
3779         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3780         pf->max_num_vsi = hw->func_caps.num_vsis;
3781         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3782         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3783         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3784
3785         /* FDir queue/VSI allocation */
3786         pf->fdir_qp_offset = 0;
3787         if (hw->func_caps.fd) {
3788                 pf->flags |= I40E_FLAG_FDIR;
3789                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3790         } else {
3791                 pf->fdir_nb_qps = 0;
3792         }
3793         qp_count += pf->fdir_nb_qps;
3794         vsi_count += 1;
3795
3796         /* LAN queue/VSI allocation */
3797         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3798         if (!hw->func_caps.rss) {
3799                 pf->lan_nb_qps = 1;
3800         } else {
3801                 pf->flags |= I40E_FLAG_RSS;
3802                 if (hw->mac.type == I40E_MAC_X722)
3803                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3804                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3805         }
3806         qp_count += pf->lan_nb_qps;
3807         vsi_count += 1;
3808
3809         /* VF queue/VSI allocation */
3810         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3811         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3812                 pf->flags |= I40E_FLAG_SRIOV;
3813                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3814                 pf->vf_num = pci_dev->max_vfs;
3815                 PMD_DRV_LOG(DEBUG,
3816                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3817                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3818         } else {
3819                 pf->vf_nb_qps = 0;
3820                 pf->vf_num = 0;
3821         }
3822         qp_count += pf->vf_nb_qps * pf->vf_num;
3823         vsi_count += pf->vf_num;
3824
3825         /* VMDq queue/VSI allocation */
3826         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3827         pf->vmdq_nb_qps = 0;
3828         pf->max_nb_vmdq_vsi = 0;
3829         if (hw->func_caps.vmdq) {
3830                 if (qp_count < hw->func_caps.num_tx_qp &&
3831                         vsi_count < hw->func_caps.num_vsis) {
3832                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3833                                 qp_count) / pf->vmdq_nb_qp_max;
3834
3835                         /* Limit the maximum number of VMDq vsi to the maximum
3836                          * ethdev can support
3837                          */
3838                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3839                                 hw->func_caps.num_vsis - vsi_count);
3840                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3841                                 ETH_64_POOLS);
3842                         if (pf->max_nb_vmdq_vsi) {
3843                                 pf->flags |= I40E_FLAG_VMDQ;
3844                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3845                                 PMD_DRV_LOG(DEBUG,
3846                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3847                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3848                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3849                         } else {
3850                                 PMD_DRV_LOG(INFO,
3851                                         "No enough queues left for VMDq");
3852                         }
3853                 } else {
3854                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3855                 }
3856         }
3857         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3858         vsi_count += pf->max_nb_vmdq_vsi;
3859
3860         if (hw->func_caps.dcb)
3861                 pf->flags |= I40E_FLAG_DCB;
3862
3863         if (qp_count > hw->func_caps.num_tx_qp) {
3864                 PMD_DRV_LOG(ERR,
3865                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3866                         qp_count, hw->func_caps.num_tx_qp);
3867                 return -EINVAL;
3868         }
3869         if (vsi_count > hw->func_caps.num_vsis) {
3870                 PMD_DRV_LOG(ERR,
3871                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3872                         vsi_count, hw->func_caps.num_vsis);
3873                 return -EINVAL;
3874         }
3875
3876         return 0;
3877 }
3878
3879 static int
3880 i40e_pf_get_switch_config(struct i40e_pf *pf)
3881 {
3882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3883         struct i40e_aqc_get_switch_config_resp *switch_config;
3884         struct i40e_aqc_switch_config_element_resp *element;
3885         uint16_t start_seid = 0, num_reported;
3886         int ret;
3887
3888         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3889                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3890         if (!switch_config) {
3891                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3892                 return -ENOMEM;
3893         }
3894
3895         /* Get the switch configurations */
3896         ret = i40e_aq_get_switch_config(hw, switch_config,
3897                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3898         if (ret != I40E_SUCCESS) {
3899                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3900                 goto fail;
3901         }
3902         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3903         if (num_reported != 1) { /* The number should be 1 */
3904                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3905                 goto fail;
3906         }
3907
3908         /* Parse the switch configuration elements */
3909         element = &(switch_config->element[0]);
3910         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3911                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3912                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3913         } else
3914                 PMD_DRV_LOG(INFO, "Unknown element type");
3915
3916 fail:
3917         rte_free(switch_config);
3918
3919         return ret;
3920 }
3921
3922 static int
3923 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3924                         uint32_t num)
3925 {
3926         struct pool_entry *entry;
3927
3928         if (pool == NULL || num == 0)
3929                 return -EINVAL;
3930
3931         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3932         if (entry == NULL) {
3933                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3934                 return -ENOMEM;
3935         }
3936
3937         /* queue heap initialize */
3938         pool->num_free = num;
3939         pool->num_alloc = 0;
3940         pool->base = base;
3941         LIST_INIT(&pool->alloc_list);
3942         LIST_INIT(&pool->free_list);
3943
3944         /* Initialize element  */
3945         entry->base = 0;
3946         entry->len = num;
3947
3948         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3949         return 0;
3950 }
3951
3952 static void
3953 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3954 {
3955         struct pool_entry *entry, *next_entry;
3956
3957         if (pool == NULL)
3958                 return;
3959
3960         for (entry = LIST_FIRST(&pool->alloc_list);
3961                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3962                         entry = next_entry) {
3963                 LIST_REMOVE(entry, next);
3964                 rte_free(entry);
3965         }
3966
3967         for (entry = LIST_FIRST(&pool->free_list);
3968                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3969                         entry = next_entry) {
3970                 LIST_REMOVE(entry, next);
3971                 rte_free(entry);
3972         }
3973
3974         pool->num_free = 0;
3975         pool->num_alloc = 0;
3976         pool->base = 0;
3977         LIST_INIT(&pool->alloc_list);
3978         LIST_INIT(&pool->free_list);
3979 }
3980
3981 static int
3982 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3983                        uint32_t base)
3984 {
3985         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3986         uint32_t pool_offset;
3987         int insert;
3988
3989         if (pool == NULL) {
3990                 PMD_DRV_LOG(ERR, "Invalid parameter");
3991                 return -EINVAL;
3992         }
3993
3994         pool_offset = base - pool->base;
3995         /* Lookup in alloc list */
3996         LIST_FOREACH(entry, &pool->alloc_list, next) {
3997                 if (entry->base == pool_offset) {
3998                         valid_entry = entry;
3999                         LIST_REMOVE(entry, next);
4000                         break;
4001                 }
4002         }
4003
4004         /* Not find, return */
4005         if (valid_entry == NULL) {
4006                 PMD_DRV_LOG(ERR, "Failed to find entry");
4007                 return -EINVAL;
4008         }
4009
4010         /**
4011          * Found it, move it to free list  and try to merge.
4012          * In order to make merge easier, always sort it by qbase.
4013          * Find adjacent prev and last entries.
4014          */
4015         prev = next = NULL;
4016         LIST_FOREACH(entry, &pool->free_list, next) {
4017                 if (entry->base > valid_entry->base) {
4018                         next = entry;
4019                         break;
4020                 }
4021                 prev = entry;
4022         }
4023
4024         insert = 0;
4025         /* Try to merge with next one*/
4026         if (next != NULL) {
4027                 /* Merge with next one */
4028                 if (valid_entry->base + valid_entry->len == next->base) {
4029                         next->base = valid_entry->base;
4030                         next->len += valid_entry->len;
4031                         rte_free(valid_entry);
4032                         valid_entry = next;
4033                         insert = 1;
4034                 }
4035         }
4036
4037         if (prev != NULL) {
4038                 /* Merge with previous one */
4039                 if (prev->base + prev->len == valid_entry->base) {
4040                         prev->len += valid_entry->len;
4041                         /* If it merge with next one, remove next node */
4042                         if (insert == 1) {
4043                                 LIST_REMOVE(valid_entry, next);
4044                                 rte_free(valid_entry);
4045                         } else {
4046                                 rte_free(valid_entry);
4047                                 insert = 1;
4048                         }
4049                 }
4050         }
4051
4052         /* Not find any entry to merge, insert */
4053         if (insert == 0) {
4054                 if (prev != NULL)
4055                         LIST_INSERT_AFTER(prev, valid_entry, next);
4056                 else if (next != NULL)
4057                         LIST_INSERT_BEFORE(next, valid_entry, next);
4058                 else /* It's empty list, insert to head */
4059                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4060         }
4061
4062         pool->num_free += valid_entry->len;
4063         pool->num_alloc -= valid_entry->len;
4064
4065         return 0;
4066 }
4067
4068 static int
4069 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4070                        uint16_t num)
4071 {
4072         struct pool_entry *entry, *valid_entry;
4073
4074         if (pool == NULL || num == 0) {
4075                 PMD_DRV_LOG(ERR, "Invalid parameter");
4076                 return -EINVAL;
4077         }
4078
4079         if (pool->num_free < num) {
4080                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4081                             num, pool->num_free);
4082                 return -ENOMEM;
4083         }
4084
4085         valid_entry = NULL;
4086         /* Lookup  in free list and find most fit one */
4087         LIST_FOREACH(entry, &pool->free_list, next) {
4088                 if (entry->len >= num) {
4089                         /* Find best one */
4090                         if (entry->len == num) {
4091                                 valid_entry = entry;
4092                                 break;
4093                         }
4094                         if (valid_entry == NULL || valid_entry->len > entry->len)
4095                                 valid_entry = entry;
4096                 }
4097         }
4098
4099         /* Not find one to satisfy the request, return */
4100         if (valid_entry == NULL) {
4101                 PMD_DRV_LOG(ERR, "No valid entry found");
4102                 return -ENOMEM;
4103         }
4104         /**
4105          * The entry have equal queue number as requested,
4106          * remove it from alloc_list.
4107          */
4108         if (valid_entry->len == num) {
4109                 LIST_REMOVE(valid_entry, next);
4110         } else {
4111                 /**
4112                  * The entry have more numbers than requested,
4113                  * create a new entry for alloc_list and minus its
4114                  * queue base and number in free_list.
4115                  */
4116                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4117                 if (entry == NULL) {
4118                         PMD_DRV_LOG(ERR,
4119                                 "Failed to allocate memory for resource pool");
4120                         return -ENOMEM;
4121                 }
4122                 entry->base = valid_entry->base;
4123                 entry->len = num;
4124                 valid_entry->base += num;
4125                 valid_entry->len -= num;
4126                 valid_entry = entry;
4127         }
4128
4129         /* Insert it into alloc list, not sorted */
4130         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4131
4132         pool->num_free -= valid_entry->len;
4133         pool->num_alloc += valid_entry->len;
4134
4135         return valid_entry->base + pool->base;
4136 }
4137
4138 /**
4139  * bitmap_is_subset - Check whether src2 is subset of src1
4140  **/
4141 static inline int
4142 bitmap_is_subset(uint8_t src1, uint8_t src2)
4143 {
4144         return !((src1 ^ src2) & src2);
4145 }
4146
4147 static enum i40e_status_code
4148 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4149 {
4150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4151
4152         /* If DCB is not supported, only default TC is supported */
4153         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4154                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4155                 return I40E_NOT_SUPPORTED;
4156         }
4157
4158         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4159                 PMD_DRV_LOG(ERR,
4160                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4161                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4162                 return I40E_NOT_SUPPORTED;
4163         }
4164         return I40E_SUCCESS;
4165 }
4166
4167 int
4168 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4169                                 struct i40e_vsi_vlan_pvid_info *info)
4170 {
4171         struct i40e_hw *hw;
4172         struct i40e_vsi_context ctxt;
4173         uint8_t vlan_flags = 0;
4174         int ret;
4175
4176         if (vsi == NULL || info == NULL) {
4177                 PMD_DRV_LOG(ERR, "invalid parameters");
4178                 return I40E_ERR_PARAM;
4179         }
4180
4181         if (info->on) {
4182                 vsi->info.pvid = info->config.pvid;
4183                 /**
4184                  * If insert pvid is enabled, only tagged pkts are
4185                  * allowed to be sent out.
4186                  */
4187                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4188                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4189         } else {
4190                 vsi->info.pvid = 0;
4191                 if (info->config.reject.tagged == 0)
4192                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4193
4194                 if (info->config.reject.untagged == 0)
4195                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4196         }
4197         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4198                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4199         vsi->info.port_vlan_flags |= vlan_flags;
4200         vsi->info.valid_sections =
4201                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4202         memset(&ctxt, 0, sizeof(ctxt));
4203         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4204         ctxt.seid = vsi->seid;
4205
4206         hw = I40E_VSI_TO_HW(vsi);
4207         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4208         if (ret != I40E_SUCCESS)
4209                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4210
4211         return ret;
4212 }
4213
4214 static int
4215 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4216 {
4217         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4218         int i, ret;
4219         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4220
4221         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4222         if (ret != I40E_SUCCESS)
4223                 return ret;
4224
4225         if (!vsi->seid) {
4226                 PMD_DRV_LOG(ERR, "seid not valid");
4227                 return -EINVAL;
4228         }
4229
4230         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4231         tc_bw_data.tc_valid_bits = enabled_tcmap;
4232         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4233                 tc_bw_data.tc_bw_credits[i] =
4234                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4235
4236         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4237         if (ret != I40E_SUCCESS) {
4238                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4239                 return ret;
4240         }
4241
4242         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4243                                         sizeof(vsi->info.qs_handle));
4244         return I40E_SUCCESS;
4245 }
4246
4247 static enum i40e_status_code
4248 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4249                                  struct i40e_aqc_vsi_properties_data *info,
4250                                  uint8_t enabled_tcmap)
4251 {
4252         enum i40e_status_code ret;
4253         int i, total_tc = 0;
4254         uint16_t qpnum_per_tc, bsf, qp_idx;
4255
4256         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4257         if (ret != I40E_SUCCESS)
4258                 return ret;
4259
4260         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4261                 if (enabled_tcmap & (1 << i))
4262                         total_tc++;
4263         vsi->enabled_tc = enabled_tcmap;
4264
4265         /* Number of queues per enabled TC */
4266         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4267         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4268         bsf = rte_bsf32(qpnum_per_tc);
4269
4270         /* Adjust the queue number to actual queues that can be applied */
4271         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4272                 vsi->nb_qps = qpnum_per_tc * total_tc;
4273
4274         /**
4275          * Configure TC and queue mapping parameters, for enabled TC,
4276          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4277          * default queue will serve it.
4278          */
4279         qp_idx = 0;
4280         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4281                 if (vsi->enabled_tc & (1 << i)) {
4282                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4283                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4284                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4285                         qp_idx += qpnum_per_tc;
4286                 } else
4287                         info->tc_mapping[i] = 0;
4288         }
4289
4290         /* Associate queue number with VSI */
4291         if (vsi->type == I40E_VSI_SRIOV) {
4292                 info->mapping_flags |=
4293                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4294                 for (i = 0; i < vsi->nb_qps; i++)
4295                         info->queue_mapping[i] =
4296                                 rte_cpu_to_le_16(vsi->base_queue + i);
4297         } else {
4298                 info->mapping_flags |=
4299                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4300                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4301         }
4302         info->valid_sections |=
4303                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4304
4305         return I40E_SUCCESS;
4306 }
4307
4308 static int
4309 i40e_veb_release(struct i40e_veb *veb)
4310 {
4311         struct i40e_vsi *vsi;
4312         struct i40e_hw *hw;
4313
4314         if (veb == NULL)
4315                 return -EINVAL;
4316
4317         if (!TAILQ_EMPTY(&veb->head)) {
4318                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4319                 return -EACCES;
4320         }
4321         /* associate_vsi field is NULL for floating VEB */
4322         if (veb->associate_vsi != NULL) {
4323                 vsi = veb->associate_vsi;
4324                 hw = I40E_VSI_TO_HW(vsi);
4325
4326                 vsi->uplink_seid = veb->uplink_seid;
4327                 vsi->veb = NULL;
4328         } else {
4329                 veb->associate_pf->main_vsi->floating_veb = NULL;
4330                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4331         }
4332
4333         i40e_aq_delete_element(hw, veb->seid, NULL);
4334         rte_free(veb);
4335         return I40E_SUCCESS;
4336 }
4337
4338 /* Setup a veb */
4339 static struct i40e_veb *
4340 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4341 {
4342         struct i40e_veb *veb;
4343         int ret;
4344         struct i40e_hw *hw;
4345
4346         if (pf == NULL) {
4347                 PMD_DRV_LOG(ERR,
4348                             "veb setup failed, associated PF shouldn't null");
4349                 return NULL;
4350         }
4351         hw = I40E_PF_TO_HW(pf);
4352
4353         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4354         if (!veb) {
4355                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4356                 goto fail;
4357         }
4358
4359         veb->associate_vsi = vsi;
4360         veb->associate_pf = pf;
4361         TAILQ_INIT(&veb->head);
4362         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4363
4364         /* create floating veb if vsi is NULL */
4365         if (vsi != NULL) {
4366                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4367                                       I40E_DEFAULT_TCMAP, false,
4368                                       &veb->seid, false, NULL);
4369         } else {
4370                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4371                                       true, &veb->seid, false, NULL);
4372         }
4373
4374         if (ret != I40E_SUCCESS) {
4375                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4376                             hw->aq.asq_last_status);
4377                 goto fail;
4378         }
4379         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4380
4381         /* get statistics index */
4382         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4383                                 &veb->stats_idx, NULL, NULL, NULL);
4384         if (ret != I40E_SUCCESS) {
4385                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4386                             hw->aq.asq_last_status);
4387                 goto fail;
4388         }
4389         /* Get VEB bandwidth, to be implemented */
4390         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4391         if (vsi)
4392                 vsi->uplink_seid = veb->seid;
4393
4394         return veb;
4395 fail:
4396         rte_free(veb);
4397         return NULL;
4398 }
4399
4400 int
4401 i40e_vsi_release(struct i40e_vsi *vsi)
4402 {
4403         struct i40e_pf *pf;
4404         struct i40e_hw *hw;
4405         struct i40e_vsi_list *vsi_list;
4406         void *temp;
4407         int ret;
4408         struct i40e_mac_filter *f;
4409         uint16_t user_param;
4410
4411         if (!vsi)
4412                 return I40E_SUCCESS;
4413
4414         if (!vsi->adapter)
4415                 return -EFAULT;
4416
4417         user_param = vsi->user_param;
4418
4419         pf = I40E_VSI_TO_PF(vsi);
4420         hw = I40E_VSI_TO_HW(vsi);
4421
4422         /* VSI has child to attach, release child first */
4423         if (vsi->veb) {
4424                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4425                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4426                                 return -1;
4427                 }
4428                 i40e_veb_release(vsi->veb);
4429         }
4430
4431         if (vsi->floating_veb) {
4432                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4433                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4434                                 return -1;
4435                 }
4436         }
4437
4438         /* Remove all macvlan filters of the VSI */
4439         i40e_vsi_remove_all_macvlan_filter(vsi);
4440         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4441                 rte_free(f);
4442
4443         if (vsi->type != I40E_VSI_MAIN &&
4444             ((vsi->type != I40E_VSI_SRIOV) ||
4445             !pf->floating_veb_list[user_param])) {
4446                 /* Remove vsi from parent's sibling list */
4447                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4448                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4449                         return I40E_ERR_PARAM;
4450                 }
4451                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4452                                 &vsi->sib_vsi_list, list);
4453
4454                 /* Remove all switch element of the VSI */
4455                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4456                 if (ret != I40E_SUCCESS)
4457                         PMD_DRV_LOG(ERR, "Failed to delete element");
4458         }
4459
4460         if ((vsi->type == I40E_VSI_SRIOV) &&
4461             pf->floating_veb_list[user_param]) {
4462                 /* Remove vsi from parent's sibling list */
4463                 if (vsi->parent_vsi == NULL ||
4464                     vsi->parent_vsi->floating_veb == NULL) {
4465                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4466                         return I40E_ERR_PARAM;
4467                 }
4468                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4469                              &vsi->sib_vsi_list, list);
4470
4471                 /* Remove all switch element of the VSI */
4472                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4473                 if (ret != I40E_SUCCESS)
4474                         PMD_DRV_LOG(ERR, "Failed to delete element");
4475         }
4476
4477         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4478
4479         if (vsi->type != I40E_VSI_SRIOV)
4480                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4481         rte_free(vsi);
4482
4483         return I40E_SUCCESS;
4484 }
4485
4486 static int
4487 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4488 {
4489         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4490         struct i40e_aqc_remove_macvlan_element_data def_filter;
4491         struct i40e_mac_filter_info filter;
4492         int ret;
4493
4494         if (vsi->type != I40E_VSI_MAIN)
4495                 return I40E_ERR_CONFIG;
4496         memset(&def_filter, 0, sizeof(def_filter));
4497         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4498                                         ETH_ADDR_LEN);
4499         def_filter.vlan_tag = 0;
4500         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4501                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4502         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4503         if (ret != I40E_SUCCESS) {
4504                 struct i40e_mac_filter *f;
4505                 struct ether_addr *mac;
4506
4507                 PMD_DRV_LOG(WARNING,
4508                         "Cannot remove the default macvlan filter");
4509                 /* It needs to add the permanent mac into mac list */
4510                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4511                 if (f == NULL) {
4512                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4513                         return I40E_ERR_NO_MEMORY;
4514                 }
4515                 mac = &f->mac_info.mac_addr;
4516                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4517                                 ETH_ADDR_LEN);
4518                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4519                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4520                 vsi->mac_num++;
4521
4522                 return ret;
4523         }
4524         (void)rte_memcpy(&filter.mac_addr,
4525                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4526         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4527         return i40e_vsi_add_mac(vsi, &filter);
4528 }
4529
4530 /*
4531  * i40e_vsi_get_bw_config - Query VSI BW Information
4532  * @vsi: the VSI to be queried
4533  *
4534  * Returns 0 on success, negative value on failure
4535  */
4536 static enum i40e_status_code
4537 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4538 {
4539         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4540         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4541         struct i40e_hw *hw = &vsi->adapter->hw;
4542         i40e_status ret;
4543         int i;
4544         uint32_t bw_max;
4545
4546         memset(&bw_config, 0, sizeof(bw_config));
4547         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4548         if (ret != I40E_SUCCESS) {
4549                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4550                             hw->aq.asq_last_status);
4551                 return ret;
4552         }
4553
4554         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4555         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4556                                         &ets_sla_config, NULL);
4557         if (ret != I40E_SUCCESS) {
4558                 PMD_DRV_LOG(ERR,
4559                         "VSI failed to get TC bandwdith configuration %u",
4560                         hw->aq.asq_last_status);
4561                 return ret;
4562         }
4563
4564         /* store and print out BW info */
4565         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4566         vsi->bw_info.bw_max = bw_config.max_bw;
4567         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4568         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4569         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4570                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4571                      I40E_16_BIT_WIDTH);
4572         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4573                 vsi->bw_info.bw_ets_share_credits[i] =
4574                                 ets_sla_config.share_credits[i];
4575                 vsi->bw_info.bw_ets_credits[i] =
4576                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4577                 /* 4 bits per TC, 4th bit is reserved */
4578                 vsi->bw_info.bw_ets_max[i] =
4579                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4580                                   RTE_LEN2MASK(3, uint8_t));
4581                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4582                             vsi->bw_info.bw_ets_share_credits[i]);
4583                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4584                             vsi->bw_info.bw_ets_credits[i]);
4585                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4586                             vsi->bw_info.bw_ets_max[i]);
4587         }
4588
4589         return I40E_SUCCESS;
4590 }
4591
4592 /* i40e_enable_pf_lb
4593  * @pf: pointer to the pf structure
4594  *
4595  * allow loopback on pf
4596  */
4597 static inline void
4598 i40e_enable_pf_lb(struct i40e_pf *pf)
4599 {
4600         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4601         struct i40e_vsi_context ctxt;
4602         int ret;
4603
4604         /* Use the FW API if FW >= v5.0 */
4605         if (hw->aq.fw_maj_ver < 5) {
4606                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4607                 return;
4608         }
4609
4610         memset(&ctxt, 0, sizeof(ctxt));
4611         ctxt.seid = pf->main_vsi_seid;
4612         ctxt.pf_num = hw->pf_id;
4613         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4614         if (ret) {
4615                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4616                             ret, hw->aq.asq_last_status);
4617                 return;
4618         }
4619         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4620         ctxt.info.valid_sections =
4621                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4622         ctxt.info.switch_id |=
4623                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4624
4625         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4626         if (ret)
4627                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4628                             hw->aq.asq_last_status);
4629 }
4630
4631 /* Setup a VSI */
4632 struct i40e_vsi *
4633 i40e_vsi_setup(struct i40e_pf *pf,
4634                enum i40e_vsi_type type,
4635                struct i40e_vsi *uplink_vsi,
4636                uint16_t user_param)
4637 {
4638         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4639         struct i40e_vsi *vsi;
4640         struct i40e_mac_filter_info filter;
4641         int ret;
4642         struct i40e_vsi_context ctxt;
4643         struct ether_addr broadcast =
4644                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4645
4646         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4647             uplink_vsi == NULL) {
4648                 PMD_DRV_LOG(ERR,
4649                         "VSI setup failed, VSI link shouldn't be NULL");
4650                 return NULL;
4651         }
4652
4653         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4654                 PMD_DRV_LOG(ERR,
4655                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4656                 return NULL;
4657         }
4658
4659         /* two situations
4660          * 1.type is not MAIN and uplink vsi is not NULL
4661          * If uplink vsi didn't setup VEB, create one first under veb field
4662          * 2.type is SRIOV and the uplink is NULL
4663          * If floating VEB is NULL, create one veb under floating veb field
4664          */
4665
4666         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4667             uplink_vsi->veb == NULL) {
4668                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4669
4670                 if (uplink_vsi->veb == NULL) {
4671                         PMD_DRV_LOG(ERR, "VEB setup failed");
4672                         return NULL;
4673                 }
4674                 /* set ALLOWLOOPBACk on pf, when veb is created */
4675                 i40e_enable_pf_lb(pf);
4676         }
4677
4678         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4679             pf->main_vsi->floating_veb == NULL) {
4680                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4681
4682                 if (pf->main_vsi->floating_veb == NULL) {
4683                         PMD_DRV_LOG(ERR, "VEB setup failed");
4684                         return NULL;
4685                 }
4686         }
4687
4688         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4689         if (!vsi) {
4690                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4691                 return NULL;
4692         }
4693         TAILQ_INIT(&vsi->mac_list);
4694         vsi->type = type;
4695         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4696         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4697         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4698         vsi->user_param = user_param;
4699         vsi->vlan_anti_spoof_on = 0;
4700         vsi->vlan_filter_on = 0;
4701         /* Allocate queues */
4702         switch (vsi->type) {
4703         case I40E_VSI_MAIN  :
4704                 vsi->nb_qps = pf->lan_nb_qps;
4705                 break;
4706         case I40E_VSI_SRIOV :
4707                 vsi->nb_qps = pf->vf_nb_qps;
4708                 break;
4709         case I40E_VSI_VMDQ2:
4710                 vsi->nb_qps = pf->vmdq_nb_qps;
4711                 break;
4712         case I40E_VSI_FDIR:
4713                 vsi->nb_qps = pf->fdir_nb_qps;
4714                 break;
4715         default:
4716                 goto fail_mem;
4717         }
4718         /*
4719          * The filter status descriptor is reported in rx queue 0,
4720          * while the tx queue for fdir filter programming has no
4721          * such constraints, can be non-zero queues.
4722          * To simplify it, choose FDIR vsi use queue 0 pair.
4723          * To make sure it will use queue 0 pair, queue allocation
4724          * need be done before this function is called
4725          */
4726         if (type != I40E_VSI_FDIR) {
4727                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4728                         if (ret < 0) {
4729                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4730                                                 vsi->seid, ret);
4731                                 goto fail_mem;
4732                         }
4733                         vsi->base_queue = ret;
4734         } else
4735                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4736
4737         /* VF has MSIX interrupt in VF range, don't allocate here */
4738         if (type == I40E_VSI_MAIN) {
4739                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4740                                           RTE_MIN(vsi->nb_qps,
4741                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4742                 if (ret < 0) {
4743                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4744                                     vsi->seid, ret);
4745                         goto fail_queue_alloc;
4746                 }
4747                 vsi->msix_intr = ret;
4748                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4749         } else if (type != I40E_VSI_SRIOV) {
4750                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4751                 if (ret < 0) {
4752                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4753                         goto fail_queue_alloc;
4754                 }
4755                 vsi->msix_intr = ret;
4756                 vsi->nb_msix = 1;
4757         } else {
4758                 vsi->msix_intr = 0;
4759                 vsi->nb_msix = 0;
4760         }
4761
4762         /* Add VSI */
4763         if (type == I40E_VSI_MAIN) {
4764                 /* For main VSI, no need to add since it's default one */
4765                 vsi->uplink_seid = pf->mac_seid;
4766                 vsi->seid = pf->main_vsi_seid;
4767                 /* Bind queues with specific MSIX interrupt */
4768                 /**
4769                  * Needs 2 interrupt at least, one for misc cause which will
4770                  * enabled from OS side, Another for queues binding the
4771                  * interrupt from device side only.
4772                  */
4773
4774                 /* Get default VSI parameters from hardware */
4775                 memset(&ctxt, 0, sizeof(ctxt));
4776                 ctxt.seid = vsi->seid;
4777                 ctxt.pf_num = hw->pf_id;
4778                 ctxt.uplink_seid = vsi->uplink_seid;
4779                 ctxt.vf_num = 0;
4780                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4781                 if (ret != I40E_SUCCESS) {
4782                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4783                         goto fail_msix_alloc;
4784                 }
4785                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4786                         sizeof(struct i40e_aqc_vsi_properties_data));
4787                 vsi->vsi_id = ctxt.vsi_number;
4788                 vsi->info.valid_sections = 0;
4789
4790                 /* Configure tc, enabled TC0 only */
4791                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4792                         I40E_SUCCESS) {
4793                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4794                         goto fail_msix_alloc;
4795                 }
4796
4797                 /* TC, queue mapping */
4798                 memset(&ctxt, 0, sizeof(ctxt));
4799                 vsi->info.valid_sections |=
4800                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4801                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4802                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4803                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4804                         sizeof(struct i40e_aqc_vsi_properties_data));
4805                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4806                                                 I40E_DEFAULT_TCMAP);
4807                 if (ret != I40E_SUCCESS) {
4808                         PMD_DRV_LOG(ERR,
4809                                 "Failed to configure TC queue mapping");
4810                         goto fail_msix_alloc;
4811                 }
4812                 ctxt.seid = vsi->seid;
4813                 ctxt.pf_num = hw->pf_id;
4814                 ctxt.uplink_seid = vsi->uplink_seid;
4815                 ctxt.vf_num = 0;
4816
4817                 /* Update VSI parameters */
4818                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4819                 if (ret != I40E_SUCCESS) {
4820                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4821                         goto fail_msix_alloc;
4822                 }
4823
4824                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4825                                                 sizeof(vsi->info.tc_mapping));
4826                 (void)rte_memcpy(&vsi->info.queue_mapping,
4827                                 &ctxt.info.queue_mapping,
4828                         sizeof(vsi->info.queue_mapping));
4829                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4830                 vsi->info.valid_sections = 0;
4831
4832                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4833                                 ETH_ADDR_LEN);
4834
4835                 /**
4836                  * Updating default filter settings are necessary to prevent
4837                  * reception of tagged packets.
4838                  * Some old firmware configurations load a default macvlan
4839                  * filter which accepts both tagged and untagged packets.
4840                  * The updating is to use a normal filter instead if needed.
4841                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4842                  * The firmware with correct configurations load the default
4843                  * macvlan filter which is expected and cannot be removed.
4844                  */
4845                 i40e_update_default_filter_setting(vsi);
4846                 i40e_config_qinq(hw, vsi);
4847         } else if (type == I40E_VSI_SRIOV) {
4848                 memset(&ctxt, 0, sizeof(ctxt));
4849                 /**
4850                  * For other VSI, the uplink_seid equals to uplink VSI's
4851                  * uplink_seid since they share same VEB
4852                  */
4853                 if (uplink_vsi == NULL)
4854                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4855                 else
4856                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4857                 ctxt.pf_num = hw->pf_id;
4858                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4859                 ctxt.uplink_seid = vsi->uplink_seid;
4860                 ctxt.connection_type = 0x1;
4861                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4862
4863                 /* Use the VEB configuration if FW >= v5.0 */
4864                 if (hw->aq.fw_maj_ver >= 5) {
4865                         /* Configure switch ID */
4866                         ctxt.info.valid_sections |=
4867                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4868                         ctxt.info.switch_id =
4869                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4870                 }
4871
4872                 /* Configure port/vlan */
4873                 ctxt.info.valid_sections |=
4874                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4875                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4876                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4877                                                 hw->func_caps.enabled_tcmap);
4878                 if (ret != I40E_SUCCESS) {
4879                         PMD_DRV_LOG(ERR,
4880                                 "Failed to configure TC queue mapping");
4881                         goto fail_msix_alloc;
4882                 }
4883
4884                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4885                 ctxt.info.valid_sections |=
4886                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4887                 /**
4888                  * Since VSI is not created yet, only configure parameter,
4889                  * will add vsi below.
4890                  */
4891
4892                 i40e_config_qinq(hw, vsi);
4893         } else if (type == I40E_VSI_VMDQ2) {
4894                 memset(&ctxt, 0, sizeof(ctxt));
4895                 /*
4896                  * For other VSI, the uplink_seid equals to uplink VSI's
4897                  * uplink_seid since they share same VEB
4898                  */
4899                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4900                 ctxt.pf_num = hw->pf_id;
4901                 ctxt.vf_num = 0;
4902                 ctxt.uplink_seid = vsi->uplink_seid;
4903                 ctxt.connection_type = 0x1;
4904                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4905
4906                 ctxt.info.valid_sections |=
4907                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4908                 /* user_param carries flag to enable loop back */
4909                 if (user_param) {
4910                         ctxt.info.switch_id =
4911                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4912                         ctxt.info.switch_id |=
4913                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4914                 }
4915
4916                 /* Configure port/vlan */
4917                 ctxt.info.valid_sections |=
4918                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4919                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4920                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4921                                                 I40E_DEFAULT_TCMAP);
4922                 if (ret != I40E_SUCCESS) {
4923                         PMD_DRV_LOG(ERR,
4924                                 "Failed to configure TC queue mapping");
4925                         goto fail_msix_alloc;
4926                 }
4927                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4928                 ctxt.info.valid_sections |=
4929                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4930         } else if (type == I40E_VSI_FDIR) {
4931                 memset(&ctxt, 0, sizeof(ctxt));
4932                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4933                 ctxt.pf_num = hw->pf_id;
4934                 ctxt.vf_num = 0;
4935                 ctxt.uplink_seid = vsi->uplink_seid;
4936                 ctxt.connection_type = 0x1;     /* regular data port */
4937                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4938                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4939                                                 I40E_DEFAULT_TCMAP);
4940                 if (ret != I40E_SUCCESS) {
4941                         PMD_DRV_LOG(ERR,
4942                                 "Failed to configure TC queue mapping.");
4943                         goto fail_msix_alloc;
4944                 }
4945                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4946                 ctxt.info.valid_sections |=
4947                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4948         } else {
4949                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4950                 goto fail_msix_alloc;
4951         }
4952
4953         if (vsi->type != I40E_VSI_MAIN) {
4954                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4955                 if (ret != I40E_SUCCESS) {
4956                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4957                                     hw->aq.asq_last_status);
4958                         goto fail_msix_alloc;
4959                 }
4960                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4961                 vsi->info.valid_sections = 0;
4962                 vsi->seid = ctxt.seid;
4963                 vsi->vsi_id = ctxt.vsi_number;
4964                 vsi->sib_vsi_list.vsi = vsi;
4965                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4966                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4967                                           &vsi->sib_vsi_list, list);
4968                 } else {
4969                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4970                                           &vsi->sib_vsi_list, list);
4971                 }
4972         }
4973
4974         /* MAC/VLAN configuration */
4975         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4976         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4977
4978         ret = i40e_vsi_add_mac(vsi, &filter);
4979         if (ret != I40E_SUCCESS) {
4980                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4981                 goto fail_msix_alloc;
4982         }
4983
4984         /* Get VSI BW information */
4985         i40e_vsi_get_bw_config(vsi);
4986         return vsi;
4987 fail_msix_alloc:
4988         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4989 fail_queue_alloc:
4990         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4991 fail_mem:
4992         rte_free(vsi);
4993         return NULL;
4994 }
4995
4996 /* Configure vlan filter on or off */
4997 int
4998 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4999 {
5000         int i, num;
5001         struct i40e_mac_filter *f;
5002         void *temp;
5003         struct i40e_mac_filter_info *mac_filter;
5004         enum rte_mac_filter_type desired_filter;
5005         int ret = I40E_SUCCESS;
5006
5007         if (on) {
5008                 /* Filter to match MAC and VLAN */
5009                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5010         } else {
5011                 /* Filter to match only MAC */
5012                 desired_filter = RTE_MAC_PERFECT_MATCH;
5013         }
5014
5015         num = vsi->mac_num;
5016
5017         mac_filter = rte_zmalloc("mac_filter_info_data",
5018                                  num * sizeof(*mac_filter), 0);
5019         if (mac_filter == NULL) {
5020                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5021                 return I40E_ERR_NO_MEMORY;
5022         }
5023
5024         i = 0;
5025
5026         /* Remove all existing mac */
5027         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5028                 mac_filter[i] = f->mac_info;
5029                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5030                 if (ret) {
5031                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5032                                     on ? "enable" : "disable");
5033                         goto DONE;
5034                 }
5035                 i++;
5036         }
5037
5038         /* Override with new filter */
5039         for (i = 0; i < num; i++) {
5040                 mac_filter[i].filter_type = desired_filter;
5041                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5042                 if (ret) {
5043                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5044                                     on ? "enable" : "disable");
5045                         goto DONE;
5046                 }
5047         }
5048
5049 DONE:
5050         rte_free(mac_filter);
5051         return ret;
5052 }
5053
5054 /* Configure vlan stripping on or off */
5055 int
5056 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5057 {
5058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5059         struct i40e_vsi_context ctxt;
5060         uint8_t vlan_flags;
5061         int ret = I40E_SUCCESS;
5062
5063         /* Check if it has been already on or off */
5064         if (vsi->info.valid_sections &
5065                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5066                 if (on) {
5067                         if ((vsi->info.port_vlan_flags &
5068                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5069                                 return 0; /* already on */
5070                 } else {
5071                         if ((vsi->info.port_vlan_flags &
5072                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5073                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5074                                 return 0; /* already off */
5075                 }
5076         }
5077
5078         if (on)
5079                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5080         else
5081                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5082         vsi->info.valid_sections =
5083                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5084         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5085         vsi->info.port_vlan_flags |= vlan_flags;
5086         ctxt.seid = vsi->seid;
5087         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5088         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5089         if (ret)
5090                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5091                             on ? "enable" : "disable");
5092
5093         return ret;
5094 }
5095
5096 static int
5097 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5098 {
5099         struct rte_eth_dev_data *data = dev->data;
5100         int ret;
5101         int mask = 0;
5102
5103         /* Apply vlan offload setting */
5104         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5105         i40e_vlan_offload_set(dev, mask);
5106
5107         /* Apply double-vlan setting, not implemented yet */
5108
5109         /* Apply pvid setting */
5110         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5111                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5112         if (ret)
5113                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5114
5115         return ret;
5116 }
5117
5118 static int
5119 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5120 {
5121         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5122
5123         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5124 }
5125
5126 static int
5127 i40e_update_flow_control(struct i40e_hw *hw)
5128 {
5129 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5130         struct i40e_link_status link_status;
5131         uint32_t rxfc = 0, txfc = 0, reg;
5132         uint8_t an_info;
5133         int ret;
5134
5135         memset(&link_status, 0, sizeof(link_status));
5136         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5137         if (ret != I40E_SUCCESS) {
5138                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5139                 goto write_reg; /* Disable flow control */
5140         }
5141
5142         an_info = hw->phy.link_info.an_info;
5143         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5144                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5145                 ret = I40E_ERR_NOT_READY;
5146                 goto write_reg; /* Disable flow control */
5147         }
5148         /**
5149          * If link auto negotiation is enabled, flow control needs to
5150          * be configured according to it
5151          */
5152         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5153         case I40E_LINK_PAUSE_RXTX:
5154                 rxfc = 1;
5155                 txfc = 1;
5156                 hw->fc.current_mode = I40E_FC_FULL;
5157                 break;
5158         case I40E_AQ_LINK_PAUSE_RX:
5159                 rxfc = 1;
5160                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5161                 break;
5162         case I40E_AQ_LINK_PAUSE_TX:
5163                 txfc = 1;
5164                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5165                 break;
5166         default:
5167                 hw->fc.current_mode = I40E_FC_NONE;
5168                 break;
5169         }
5170
5171 write_reg:
5172         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5173                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5174         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5175         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5176         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5177         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5178
5179         return ret;
5180 }
5181
5182 /* PF setup */
5183 static int
5184 i40e_pf_setup(struct i40e_pf *pf)
5185 {
5186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5187         struct i40e_filter_control_settings settings;
5188         struct i40e_vsi *vsi;
5189         int ret;
5190
5191         /* Clear all stats counters */
5192         pf->offset_loaded = FALSE;
5193         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5194         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5195
5196         ret = i40e_pf_get_switch_config(pf);
5197         if (ret != I40E_SUCCESS) {
5198                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5199                 return ret;
5200         }
5201         if (pf->flags & I40E_FLAG_FDIR) {
5202                 /* make queue allocated first, let FDIR use queue pair 0*/
5203                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5204                 if (ret != I40E_FDIR_QUEUE_ID) {
5205                         PMD_DRV_LOG(ERR,
5206                                 "queue allocation fails for FDIR: ret =%d",
5207                                 ret);
5208                         pf->flags &= ~I40E_FLAG_FDIR;
5209                 }
5210         }
5211         /*  main VSI setup */
5212         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5213         if (!vsi) {
5214                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5215                 return I40E_ERR_NOT_READY;
5216         }
5217         pf->main_vsi = vsi;
5218
5219         /* Configure filter control */
5220         memset(&settings, 0, sizeof(settings));
5221         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5222                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5223         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5224                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5225         else {
5226                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5227                         hw->func_caps.rss_table_size);
5228                 return I40E_ERR_PARAM;
5229         }
5230         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5231                 hw->func_caps.rss_table_size);
5232         pf->hash_lut_size = hw->func_caps.rss_table_size;
5233
5234         /* Enable ethtype and macvlan filters */
5235         settings.enable_ethtype = TRUE;
5236         settings.enable_macvlan = TRUE;
5237         ret = i40e_set_filter_control(hw, &settings);
5238         if (ret)
5239                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5240                                                                 ret);
5241
5242         /* Update flow control according to the auto negotiation */
5243         i40e_update_flow_control(hw);
5244
5245         return I40E_SUCCESS;
5246 }
5247
5248 int
5249 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5250 {
5251         uint32_t reg;
5252         uint16_t j;
5253
5254         /**
5255          * Set or clear TX Queue Disable flags,
5256          * which is required by hardware.
5257          */
5258         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5259         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5260
5261         /* Wait until the request is finished */
5262         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5263                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5264                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5265                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5266                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5267                                                         & 0x1))) {
5268                         break;
5269                 }
5270         }
5271         if (on) {
5272                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5273                         return I40E_SUCCESS; /* already on, skip next steps */
5274
5275                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5276                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5277         } else {
5278                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5279                         return I40E_SUCCESS; /* already off, skip next steps */
5280                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5281         }
5282         /* Write the register */
5283         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5284         /* Check the result */
5285         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5286                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5287                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5288                 if (on) {
5289                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5290                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5291                                 break;
5292                 } else {
5293                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5294                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5295                                 break;
5296                 }
5297         }
5298         /* Check if it is timeout */
5299         if (j >= I40E_CHK_Q_ENA_COUNT) {
5300                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5301                             (on ? "enable" : "disable"), q_idx);
5302                 return I40E_ERR_TIMEOUT;
5303         }
5304
5305         return I40E_SUCCESS;
5306 }
5307
5308 /* Swith on or off the tx queues */
5309 static int
5310 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5311 {
5312         struct rte_eth_dev_data *dev_data = pf->dev_data;
5313         struct i40e_tx_queue *txq;
5314         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5315         uint16_t i;
5316         int ret;
5317
5318         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5319                 txq = dev_data->tx_queues[i];
5320                 /* Don't operate the queue if not configured or
5321                  * if starting only per queue */
5322                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5323                         continue;
5324                 if (on)
5325                         ret = i40e_dev_tx_queue_start(dev, i);
5326                 else
5327                         ret = i40e_dev_tx_queue_stop(dev, i);
5328                 if ( ret != I40E_SUCCESS)
5329                         return ret;
5330         }
5331
5332         return I40E_SUCCESS;
5333 }
5334
5335 int
5336 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5337 {
5338         uint32_t reg;
5339         uint16_t j;
5340
5341         /* Wait until the request is finished */
5342         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5343                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5344                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5345                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5346                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5347                         break;
5348         }
5349
5350         if (on) {
5351                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5352                         return I40E_SUCCESS; /* Already on, skip next steps */
5353                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5354         } else {
5355                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5356                         return I40E_SUCCESS; /* Already off, skip next steps */
5357                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5358         }
5359
5360         /* Write the register */
5361         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5362         /* Check the result */
5363         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5364                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5365                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5366                 if (on) {
5367                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5368                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5369                                 break;
5370                 } else {
5371                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5372                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5373                                 break;
5374                 }
5375         }
5376
5377         /* Check if it is timeout */
5378         if (j >= I40E_CHK_Q_ENA_COUNT) {
5379                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5380                             (on ? "enable" : "disable"), q_idx);
5381                 return I40E_ERR_TIMEOUT;
5382         }
5383
5384         return I40E_SUCCESS;
5385 }
5386 /* Switch on or off the rx queues */
5387 static int
5388 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5389 {
5390         struct rte_eth_dev_data *dev_data = pf->dev_data;
5391         struct i40e_rx_queue *rxq;
5392         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5393         uint16_t i;
5394         int ret;
5395
5396         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5397                 rxq = dev_data->rx_queues[i];
5398                 /* Don't operate the queue if not configured or
5399                  * if starting only per queue */
5400                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5401                         continue;
5402                 if (on)
5403                         ret = i40e_dev_rx_queue_start(dev, i);
5404                 else
5405                         ret = i40e_dev_rx_queue_stop(dev, i);
5406                 if (ret != I40E_SUCCESS)
5407                         return ret;
5408         }
5409
5410         return I40E_SUCCESS;
5411 }
5412
5413 /* Switch on or off all the rx/tx queues */
5414 int
5415 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5416 {
5417         int ret;
5418
5419         if (on) {
5420                 /* enable rx queues before enabling tx queues */
5421                 ret = i40e_dev_switch_rx_queues(pf, on);
5422                 if (ret) {
5423                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5424                         return ret;
5425                 }
5426                 ret = i40e_dev_switch_tx_queues(pf, on);
5427         } else {
5428                 /* Stop tx queues before stopping rx queues */
5429                 ret = i40e_dev_switch_tx_queues(pf, on);
5430                 if (ret) {
5431                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5432                         return ret;
5433                 }
5434                 ret = i40e_dev_switch_rx_queues(pf, on);
5435         }
5436
5437         return ret;
5438 }
5439
5440 /* Initialize VSI for TX */
5441 static int
5442 i40e_dev_tx_init(struct i40e_pf *pf)
5443 {
5444         struct rte_eth_dev_data *data = pf->dev_data;
5445         uint16_t i;
5446         uint32_t ret = I40E_SUCCESS;
5447         struct i40e_tx_queue *txq;
5448
5449         for (i = 0; i < data->nb_tx_queues; i++) {
5450                 txq = data->tx_queues[i];
5451                 if (!txq || !txq->q_set)
5452                         continue;
5453                 ret = i40e_tx_queue_init(txq);
5454                 if (ret != I40E_SUCCESS)
5455                         break;
5456         }
5457         if (ret == I40E_SUCCESS)
5458                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5459                                      ->eth_dev);
5460
5461         return ret;
5462 }
5463
5464 /* Initialize VSI for RX */
5465 static int
5466 i40e_dev_rx_init(struct i40e_pf *pf)
5467 {
5468         struct rte_eth_dev_data *data = pf->dev_data;
5469         int ret = I40E_SUCCESS;
5470         uint16_t i;
5471         struct i40e_rx_queue *rxq;
5472
5473         i40e_pf_config_mq_rx(pf);
5474         for (i = 0; i < data->nb_rx_queues; i++) {
5475                 rxq = data->rx_queues[i];
5476                 if (!rxq || !rxq->q_set)
5477                         continue;
5478
5479                 ret = i40e_rx_queue_init(rxq);
5480                 if (ret != I40E_SUCCESS) {
5481                         PMD_DRV_LOG(ERR,
5482                                 "Failed to do RX queue initialization");
5483                         break;
5484                 }
5485         }
5486         if (ret == I40E_SUCCESS)
5487                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5488                                      ->eth_dev);
5489
5490         return ret;
5491 }
5492
5493 static int
5494 i40e_dev_rxtx_init(struct i40e_pf *pf)
5495 {
5496         int err;
5497
5498         err = i40e_dev_tx_init(pf);
5499         if (err) {
5500                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5501                 return err;
5502         }
5503         err = i40e_dev_rx_init(pf);
5504         if (err) {
5505                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5506                 return err;
5507         }
5508
5509         return err;
5510 }
5511
5512 static int
5513 i40e_vmdq_setup(struct rte_eth_dev *dev)
5514 {
5515         struct rte_eth_conf *conf = &dev->data->dev_conf;
5516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5517         int i, err, conf_vsis, j, loop;
5518         struct i40e_vsi *vsi;
5519         struct i40e_vmdq_info *vmdq_info;
5520         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5522
5523         /*
5524          * Disable interrupt to avoid message from VF. Furthermore, it will
5525          * avoid race condition in VSI creation/destroy.
5526          */
5527         i40e_pf_disable_irq0(hw);
5528
5529         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5530                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5531                 return -ENOTSUP;
5532         }
5533
5534         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5535         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5536                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5537                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5538                         pf->max_nb_vmdq_vsi);
5539                 return -ENOTSUP;
5540         }
5541
5542         if (pf->vmdq != NULL) {
5543                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5544                 return 0;
5545         }
5546
5547         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5548                                 sizeof(*vmdq_info) * conf_vsis, 0);
5549
5550         if (pf->vmdq == NULL) {
5551                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5552                 return -ENOMEM;
5553         }
5554
5555         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5556
5557         /* Create VMDQ VSI */
5558         for (i = 0; i < conf_vsis; i++) {
5559                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5560                                 vmdq_conf->enable_loop_back);
5561                 if (vsi == NULL) {
5562                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5563                         err = -1;
5564                         goto err_vsi_setup;
5565                 }
5566                 vmdq_info = &pf->vmdq[i];
5567                 vmdq_info->pf = pf;
5568                 vmdq_info->vsi = vsi;
5569         }
5570         pf->nb_cfg_vmdq_vsi = conf_vsis;
5571
5572         /* Configure Vlan */
5573         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5574         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5575                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5576                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5577                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5578                                         vmdq_conf->pool_map[i].vlan_id, j);
5579
5580                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5581                                                 vmdq_conf->pool_map[i].vlan_id);
5582                                 if (err) {
5583                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5584                                         err = -1;
5585                                         goto err_vsi_setup;
5586                                 }
5587                         }
5588                 }
5589         }
5590
5591         i40e_pf_enable_irq0(hw);
5592
5593         return 0;
5594
5595 err_vsi_setup:
5596         for (i = 0; i < conf_vsis; i++)
5597                 if (pf->vmdq[i].vsi == NULL)
5598                         break;
5599                 else
5600                         i40e_vsi_release(pf->vmdq[i].vsi);
5601
5602         rte_free(pf->vmdq);
5603         pf->vmdq = NULL;
5604         i40e_pf_enable_irq0(hw);
5605         return err;
5606 }
5607
5608 static void
5609 i40e_stat_update_32(struct i40e_hw *hw,
5610                    uint32_t reg,
5611                    bool offset_loaded,
5612                    uint64_t *offset,
5613                    uint64_t *stat)
5614 {
5615         uint64_t new_data;
5616
5617         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5618         if (!offset_loaded)
5619                 *offset = new_data;
5620
5621         if (new_data >= *offset)
5622                 *stat = (uint64_t)(new_data - *offset);
5623         else
5624                 *stat = (uint64_t)((new_data +
5625                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5626 }
5627
5628 static void
5629 i40e_stat_update_48(struct i40e_hw *hw,
5630                    uint32_t hireg,
5631                    uint32_t loreg,
5632                    bool offset_loaded,
5633                    uint64_t *offset,
5634                    uint64_t *stat)
5635 {
5636         uint64_t new_data;
5637
5638         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5639         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5640                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5641
5642         if (!offset_loaded)
5643                 *offset = new_data;
5644
5645         if (new_data >= *offset)
5646                 *stat = new_data - *offset;
5647         else
5648                 *stat = (uint64_t)((new_data +
5649                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5650
5651         *stat &= I40E_48_BIT_MASK;
5652 }
5653
5654 /* Disable IRQ0 */
5655 void
5656 i40e_pf_disable_irq0(struct i40e_hw *hw)
5657 {
5658         /* Disable all interrupt types */
5659         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5660         I40E_WRITE_FLUSH(hw);
5661 }
5662
5663 /* Enable IRQ0 */
5664 void
5665 i40e_pf_enable_irq0(struct i40e_hw *hw)
5666 {
5667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5668                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5669                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5670                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5671         I40E_WRITE_FLUSH(hw);
5672 }
5673
5674 static void
5675 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5676 {
5677         /* read pending request and disable first */
5678         i40e_pf_disable_irq0(hw);
5679         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5680         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5681                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5682
5683         if (no_queue)
5684                 /* Link no queues with irq0 */
5685                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5686                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5687 }
5688
5689 static void
5690 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5691 {
5692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694         int i;
5695         uint16_t abs_vf_id;
5696         uint32_t index, offset, val;
5697
5698         if (!pf->vfs)
5699                 return;
5700         /**
5701          * Try to find which VF trigger a reset, use absolute VF id to access
5702          * since the reg is global register.
5703          */
5704         for (i = 0; i < pf->vf_num; i++) {
5705                 abs_vf_id = hw->func_caps.vf_base_id + i;
5706                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5707                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5708                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5709                 /* VFR event occured */
5710                 if (val & (0x1 << offset)) {
5711                         int ret;
5712
5713                         /* Clear the event first */
5714                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5715                                                         (0x1 << offset));
5716                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5717                         /**
5718                          * Only notify a VF reset event occured,
5719                          * don't trigger another SW reset
5720                          */
5721                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5722                         if (ret != I40E_SUCCESS)
5723                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5724                 }
5725         }
5726 }
5727
5728 static void
5729 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5730 {
5731         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5732         int i;
5733
5734         for (i = 0; i < pf->vf_num; i++)
5735                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5736 }
5737
5738 static void
5739 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5740 {
5741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742         struct i40e_arq_event_info info;
5743         uint16_t pending, opcode;
5744         int ret;
5745
5746         info.buf_len = I40E_AQ_BUF_SZ;
5747         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5748         if (!info.msg_buf) {
5749                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5750                 return;
5751         }
5752
5753         pending = 1;
5754         while (pending) {
5755                 ret = i40e_clean_arq_element(hw, &info, &pending);
5756
5757                 if (ret != I40E_SUCCESS) {
5758                         PMD_DRV_LOG(INFO,
5759                                 "Failed to read msg from AdminQ, aq_err: %u",
5760                                 hw->aq.asq_last_status);
5761                         break;
5762                 }
5763                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5764
5765                 switch (opcode) {
5766                 case i40e_aqc_opc_send_msg_to_pf:
5767                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5768                         i40e_pf_host_handle_vf_msg(dev,
5769                                         rte_le_to_cpu_16(info.desc.retval),
5770                                         rte_le_to_cpu_32(info.desc.cookie_high),
5771                                         rte_le_to_cpu_32(info.desc.cookie_low),
5772                                         info.msg_buf,
5773                                         info.msg_len);
5774                         break;
5775                 case i40e_aqc_opc_get_link_status:
5776                         ret = i40e_dev_link_update(dev, 0);
5777                         if (!ret) {
5778                                 i40e_notify_all_vfs_link_status(dev);
5779                                 _rte_eth_dev_callback_process(dev,
5780                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5781                         }
5782                         break;
5783                 default:
5784                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5785                                     opcode);
5786                         break;
5787                 }
5788         }
5789         rte_free(info.msg_buf);
5790 }
5791
5792 /**
5793  * Interrupt handler triggered by NIC  for handling
5794  * specific interrupt.
5795  *
5796  * @param handle
5797  *  Pointer to interrupt handle.
5798  * @param param
5799  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5800  *
5801  * @return
5802  *  void
5803  */
5804 static void
5805 i40e_dev_interrupt_handler(void *param)
5806 {
5807         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5809         uint32_t icr0;
5810
5811         /* Disable interrupt */
5812         i40e_pf_disable_irq0(hw);
5813
5814         /* read out interrupt causes */
5815         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5816
5817         /* No interrupt event indicated */
5818         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5819                 PMD_DRV_LOG(INFO, "No interrupt event");
5820                 goto done;
5821         }
5822         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5823                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5824         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5825                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5826         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5827                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5828         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5829                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5830         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5831                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5832         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5833                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5834         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5835                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5836
5837         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5838                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5839                 i40e_dev_handle_vfr_event(dev);
5840         }
5841         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5842                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5843                 i40e_dev_handle_aq_msg(dev);
5844         }
5845
5846 done:
5847         /* Enable interrupt */
5848         i40e_pf_enable_irq0(hw);
5849         rte_intr_enable(dev->intr_handle);
5850 }
5851
5852 int
5853 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5854                          struct i40e_macvlan_filter *filter,
5855                          int total)
5856 {
5857         int ele_num, ele_buff_size;
5858         int num, actual_num, i;
5859         uint16_t flags;
5860         int ret = I40E_SUCCESS;
5861         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5862         struct i40e_aqc_add_macvlan_element_data *req_list;
5863
5864         if (filter == NULL  || total == 0)
5865                 return I40E_ERR_PARAM;
5866         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5867         ele_buff_size = hw->aq.asq_buf_size;
5868
5869         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5870         if (req_list == NULL) {
5871                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5872                 return I40E_ERR_NO_MEMORY;
5873         }
5874
5875         num = 0;
5876         do {
5877                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5878                 memset(req_list, 0, ele_buff_size);
5879
5880                 for (i = 0; i < actual_num; i++) {
5881                         (void)rte_memcpy(req_list[i].mac_addr,
5882                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5883                         req_list[i].vlan_tag =
5884                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5885
5886                         switch (filter[num + i].filter_type) {
5887                         case RTE_MAC_PERFECT_MATCH:
5888                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5889                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5890                                 break;
5891                         case RTE_MACVLAN_PERFECT_MATCH:
5892                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5893                                 break;
5894                         case RTE_MAC_HASH_MATCH:
5895                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5896                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5897                                 break;
5898                         case RTE_MACVLAN_HASH_MATCH:
5899                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5900                                 break;
5901                         default:
5902                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5903                                 ret = I40E_ERR_PARAM;
5904                                 goto DONE;
5905                         }
5906
5907                         req_list[i].queue_number = 0;
5908
5909                         req_list[i].flags = rte_cpu_to_le_16(flags);
5910                 }
5911
5912                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5913                                                 actual_num, NULL);
5914                 if (ret != I40E_SUCCESS) {
5915                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5916                         goto DONE;
5917                 }
5918                 num += actual_num;
5919         } while (num < total);
5920
5921 DONE:
5922         rte_free(req_list);
5923         return ret;
5924 }
5925
5926 int
5927 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5928                             struct i40e_macvlan_filter *filter,
5929                             int total)
5930 {
5931         int ele_num, ele_buff_size;
5932         int num, actual_num, i;
5933         uint16_t flags;
5934         int ret = I40E_SUCCESS;
5935         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5936         struct i40e_aqc_remove_macvlan_element_data *req_list;
5937
5938         if (filter == NULL  || total == 0)
5939                 return I40E_ERR_PARAM;
5940
5941         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5942         ele_buff_size = hw->aq.asq_buf_size;
5943
5944         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5945         if (req_list == NULL) {
5946                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5947                 return I40E_ERR_NO_MEMORY;
5948         }
5949
5950         num = 0;
5951         do {
5952                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5953                 memset(req_list, 0, ele_buff_size);
5954
5955                 for (i = 0; i < actual_num; i++) {
5956                         (void)rte_memcpy(req_list[i].mac_addr,
5957                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5958                         req_list[i].vlan_tag =
5959                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5960
5961                         switch (filter[num + i].filter_type) {
5962                         case RTE_MAC_PERFECT_MATCH:
5963                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5964                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5965                                 break;
5966                         case RTE_MACVLAN_PERFECT_MATCH:
5967                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5968                                 break;
5969                         case RTE_MAC_HASH_MATCH:
5970                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5971                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5972                                 break;
5973                         case RTE_MACVLAN_HASH_MATCH:
5974                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5975                                 break;
5976                         default:
5977                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5978                                 ret = I40E_ERR_PARAM;
5979                                 goto DONE;
5980                         }
5981                         req_list[i].flags = rte_cpu_to_le_16(flags);
5982                 }
5983
5984                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5985                                                 actual_num, NULL);
5986                 if (ret != I40E_SUCCESS) {
5987                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5988                         goto DONE;
5989                 }
5990                 num += actual_num;
5991         } while (num < total);
5992
5993 DONE:
5994         rte_free(req_list);
5995         return ret;
5996 }
5997
5998 /* Find out specific MAC filter */
5999 static struct i40e_mac_filter *
6000 i40e_find_mac_filter(struct i40e_vsi *vsi,
6001                          struct ether_addr *macaddr)
6002 {
6003         struct i40e_mac_filter *f;
6004
6005         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6006                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6007                         return f;
6008         }
6009
6010         return NULL;
6011 }
6012
6013 static bool
6014 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6015                          uint16_t vlan_id)
6016 {
6017         uint32_t vid_idx, vid_bit;
6018
6019         if (vlan_id > ETH_VLAN_ID_MAX)
6020                 return 0;
6021
6022         vid_idx = I40E_VFTA_IDX(vlan_id);
6023         vid_bit = I40E_VFTA_BIT(vlan_id);
6024
6025         if (vsi->vfta[vid_idx] & vid_bit)
6026                 return 1;
6027         else
6028                 return 0;
6029 }
6030
6031 static void
6032 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6033                        uint16_t vlan_id, bool on)
6034 {
6035         uint32_t vid_idx, vid_bit;
6036
6037         vid_idx = I40E_VFTA_IDX(vlan_id);
6038         vid_bit = I40E_VFTA_BIT(vlan_id);
6039
6040         if (on)
6041                 vsi->vfta[vid_idx] |= vid_bit;
6042         else
6043                 vsi->vfta[vid_idx] &= ~vid_bit;
6044 }
6045
6046 void
6047 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6048                      uint16_t vlan_id, bool on)
6049 {
6050         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6051         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6052         int ret;
6053
6054         if (vlan_id > ETH_VLAN_ID_MAX)
6055                 return;
6056
6057         i40e_store_vlan_filter(vsi, vlan_id, on);
6058
6059         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6060                 return;
6061
6062         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6063
6064         if (on) {
6065                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6066                                        &vlan_data, 1, NULL);
6067                 if (ret != I40E_SUCCESS)
6068                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6069         } else {
6070                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6071                                           &vlan_data, 1, NULL);
6072                 if (ret != I40E_SUCCESS)
6073                         PMD_DRV_LOG(ERR,
6074                                     "Failed to remove vlan filter");
6075         }
6076 }
6077
6078 /**
6079  * Find all vlan options for specific mac addr,
6080  * return with actual vlan found.
6081  */
6082 int
6083 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6084                            struct i40e_macvlan_filter *mv_f,
6085                            int num, struct ether_addr *addr)
6086 {
6087         int i;
6088         uint32_t j, k;
6089
6090         /**
6091          * Not to use i40e_find_vlan_filter to decrease the loop time,
6092          * although the code looks complex.
6093           */
6094         if (num < vsi->vlan_num)
6095                 return I40E_ERR_PARAM;
6096
6097         i = 0;
6098         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6099                 if (vsi->vfta[j]) {
6100                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6101                                 if (vsi->vfta[j] & (1 << k)) {
6102                                         if (i > num - 1) {
6103                                                 PMD_DRV_LOG(ERR,
6104                                                         "vlan number doesn't match");
6105                                                 return I40E_ERR_PARAM;
6106                                         }
6107                                         (void)rte_memcpy(&mv_f[i].macaddr,
6108                                                         addr, ETH_ADDR_LEN);
6109                                         mv_f[i].vlan_id =
6110                                                 j * I40E_UINT32_BIT_SIZE + k;
6111                                         i++;
6112                                 }
6113                         }
6114                 }
6115         }
6116         return I40E_SUCCESS;
6117 }
6118
6119 static inline int
6120 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6121                            struct i40e_macvlan_filter *mv_f,
6122                            int num,
6123                            uint16_t vlan)
6124 {
6125         int i = 0;
6126         struct i40e_mac_filter *f;
6127
6128         if (num < vsi->mac_num)
6129                 return I40E_ERR_PARAM;
6130
6131         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6132                 if (i > num - 1) {
6133                         PMD_DRV_LOG(ERR, "buffer number not match");
6134                         return I40E_ERR_PARAM;
6135                 }
6136                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6137                                 ETH_ADDR_LEN);
6138                 mv_f[i].vlan_id = vlan;
6139                 mv_f[i].filter_type = f->mac_info.filter_type;
6140                 i++;
6141         }
6142
6143         return I40E_SUCCESS;
6144 }
6145
6146 static int
6147 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6148 {
6149         int i, j, num;
6150         struct i40e_mac_filter *f;
6151         struct i40e_macvlan_filter *mv_f;
6152         int ret = I40E_SUCCESS;
6153
6154         if (vsi == NULL || vsi->mac_num == 0)
6155                 return I40E_ERR_PARAM;
6156
6157         /* Case that no vlan is set */
6158         if (vsi->vlan_num == 0)
6159                 num = vsi->mac_num;
6160         else
6161                 num = vsi->mac_num * vsi->vlan_num;
6162
6163         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6164         if (mv_f == NULL) {
6165                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6166                 return I40E_ERR_NO_MEMORY;
6167         }
6168
6169         i = 0;
6170         if (vsi->vlan_num == 0) {
6171                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6172                         (void)rte_memcpy(&mv_f[i].macaddr,
6173                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6174                         mv_f[i].filter_type = f->mac_info.filter_type;
6175                         mv_f[i].vlan_id = 0;
6176                         i++;
6177                 }
6178         } else {
6179                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6180                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6181                                         vsi->vlan_num, &f->mac_info.mac_addr);
6182                         if (ret != I40E_SUCCESS)
6183                                 goto DONE;
6184                         for (j = i; j < i + vsi->vlan_num; j++)
6185                                 mv_f[j].filter_type = f->mac_info.filter_type;
6186                         i += vsi->vlan_num;
6187                 }
6188         }
6189
6190         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6191 DONE:
6192         rte_free(mv_f);
6193
6194         return ret;
6195 }
6196
6197 int
6198 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6199 {
6200         struct i40e_macvlan_filter *mv_f;
6201         int mac_num;
6202         int ret = I40E_SUCCESS;
6203
6204         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6205                 return I40E_ERR_PARAM;
6206
6207         /* If it's already set, just return */
6208         if (i40e_find_vlan_filter(vsi,vlan))
6209                 return I40E_SUCCESS;
6210
6211         mac_num = vsi->mac_num;
6212
6213         if (mac_num == 0) {
6214                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6215                 return I40E_ERR_PARAM;
6216         }
6217
6218         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6219
6220         if (mv_f == NULL) {
6221                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6222                 return I40E_ERR_NO_MEMORY;
6223         }
6224
6225         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6226
6227         if (ret != I40E_SUCCESS)
6228                 goto DONE;
6229
6230         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6231
6232         if (ret != I40E_SUCCESS)
6233                 goto DONE;
6234
6235         i40e_set_vlan_filter(vsi, vlan, 1);
6236
6237         vsi->vlan_num++;
6238         ret = I40E_SUCCESS;
6239 DONE:
6240         rte_free(mv_f);
6241         return ret;
6242 }
6243
6244 int
6245 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6246 {
6247         struct i40e_macvlan_filter *mv_f;
6248         int mac_num;
6249         int ret = I40E_SUCCESS;
6250
6251         /**
6252          * Vlan 0 is the generic filter for untagged packets
6253          * and can't be removed.
6254          */
6255         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6256                 return I40E_ERR_PARAM;
6257
6258         /* If can't find it, just return */
6259         if (!i40e_find_vlan_filter(vsi, vlan))
6260                 return I40E_ERR_PARAM;
6261
6262         mac_num = vsi->mac_num;
6263
6264         if (mac_num == 0) {
6265                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6266                 return I40E_ERR_PARAM;
6267         }
6268
6269         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6270
6271         if (mv_f == NULL) {
6272                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6273                 return I40E_ERR_NO_MEMORY;
6274         }
6275
6276         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6277
6278         if (ret != I40E_SUCCESS)
6279                 goto DONE;
6280
6281         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6282
6283         if (ret != I40E_SUCCESS)
6284                 goto DONE;
6285
6286         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6287         if (vsi->vlan_num == 1) {
6288                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6289                 if (ret != I40E_SUCCESS)
6290                         goto DONE;
6291
6292                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6293                 if (ret != I40E_SUCCESS)
6294                         goto DONE;
6295         }
6296
6297         i40e_set_vlan_filter(vsi, vlan, 0);
6298
6299         vsi->vlan_num--;
6300         ret = I40E_SUCCESS;
6301 DONE:
6302         rte_free(mv_f);
6303         return ret;
6304 }
6305
6306 int
6307 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6308 {
6309         struct i40e_mac_filter *f;
6310         struct i40e_macvlan_filter *mv_f;
6311         int i, vlan_num = 0;
6312         int ret = I40E_SUCCESS;
6313
6314         /* If it's add and we've config it, return */
6315         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6316         if (f != NULL)
6317                 return I40E_SUCCESS;
6318         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6319                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6320
6321                 /**
6322                  * If vlan_num is 0, that's the first time to add mac,
6323                  * set mask for vlan_id 0.
6324                  */
6325                 if (vsi->vlan_num == 0) {
6326                         i40e_set_vlan_filter(vsi, 0, 1);
6327                         vsi->vlan_num = 1;
6328                 }
6329                 vlan_num = vsi->vlan_num;
6330         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6331                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6332                 vlan_num = 1;
6333
6334         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6335         if (mv_f == NULL) {
6336                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6337                 return I40E_ERR_NO_MEMORY;
6338         }
6339
6340         for (i = 0; i < vlan_num; i++) {
6341                 mv_f[i].filter_type = mac_filter->filter_type;
6342                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6343                                 ETH_ADDR_LEN);
6344         }
6345
6346         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6347                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6348                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6349                                         &mac_filter->mac_addr);
6350                 if (ret != I40E_SUCCESS)
6351                         goto DONE;
6352         }
6353
6354         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6355         if (ret != I40E_SUCCESS)
6356                 goto DONE;
6357
6358         /* Add the mac addr into mac list */
6359         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6360         if (f == NULL) {
6361                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6362                 ret = I40E_ERR_NO_MEMORY;
6363                 goto DONE;
6364         }
6365         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6366                         ETH_ADDR_LEN);
6367         f->mac_info.filter_type = mac_filter->filter_type;
6368         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6369         vsi->mac_num++;
6370
6371         ret = I40E_SUCCESS;
6372 DONE:
6373         rte_free(mv_f);
6374
6375         return ret;
6376 }
6377
6378 int
6379 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6380 {
6381         struct i40e_mac_filter *f;
6382         struct i40e_macvlan_filter *mv_f;
6383         int i, vlan_num;
6384         enum rte_mac_filter_type filter_type;
6385         int ret = I40E_SUCCESS;
6386
6387         /* Can't find it, return an error */
6388         f = i40e_find_mac_filter(vsi, addr);
6389         if (f == NULL)
6390                 return I40E_ERR_PARAM;
6391
6392         vlan_num = vsi->vlan_num;
6393         filter_type = f->mac_info.filter_type;
6394         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6395                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6396                 if (vlan_num == 0) {
6397                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6398                         return I40E_ERR_PARAM;
6399                 }
6400         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6401                         filter_type == RTE_MAC_HASH_MATCH)
6402                 vlan_num = 1;
6403
6404         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6405         if (mv_f == NULL) {
6406                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6407                 return I40E_ERR_NO_MEMORY;
6408         }
6409
6410         for (i = 0; i < vlan_num; i++) {
6411                 mv_f[i].filter_type = filter_type;
6412                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6413                                 ETH_ADDR_LEN);
6414         }
6415         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6416                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6417                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6418                 if (ret != I40E_SUCCESS)
6419                         goto DONE;
6420         }
6421
6422         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6423         if (ret != I40E_SUCCESS)
6424                 goto DONE;
6425
6426         /* Remove the mac addr into mac list */
6427         TAILQ_REMOVE(&vsi->mac_list, f, next);
6428         rte_free(f);
6429         vsi->mac_num--;
6430
6431         ret = I40E_SUCCESS;
6432 DONE:
6433         rte_free(mv_f);
6434         return ret;
6435 }
6436
6437 /* Configure hash enable flags for RSS */
6438 uint64_t
6439 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6440 {
6441         uint64_t hena = 0;
6442
6443         if (!flags)
6444                 return hena;
6445
6446         if (flags & ETH_RSS_FRAG_IPV4)
6447                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6448         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6449                 if (type == I40E_MAC_X722) {
6450                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6451                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6452                 } else
6453                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6454         }
6455         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6456                 if (type == I40E_MAC_X722) {
6457                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6458                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6459                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6460                 } else
6461                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6462         }
6463         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6464                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6465         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6466                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6467         if (flags & ETH_RSS_FRAG_IPV6)
6468                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6469         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6470                 if (type == I40E_MAC_X722) {
6471                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6472                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6473                 } else
6474                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6475         }
6476         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6477                 if (type == I40E_MAC_X722) {
6478                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6479                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6480                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6481                 } else
6482                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6483         }
6484         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6485                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6486         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6487                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6488         if (flags & ETH_RSS_L2_PAYLOAD)
6489                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6490
6491         return hena;
6492 }
6493
6494 /* Parse the hash enable flags */
6495 uint64_t
6496 i40e_parse_hena(uint64_t flags)
6497 {
6498         uint64_t rss_hf = 0;
6499
6500         if (!flags)
6501                 return rss_hf;
6502         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6503                 rss_hf |= ETH_RSS_FRAG_IPV4;
6504         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6505                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6508         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6509                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6510         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6511                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6512         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6513                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6514         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6515                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6516         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6517                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6518         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6519                 rss_hf |= ETH_RSS_FRAG_IPV6;
6520         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6521                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6522         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6523                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6524         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6525                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6526         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6527                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6528         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6529                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6530         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6531                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6532         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6533                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6534         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6535                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6536
6537         return rss_hf;
6538 }
6539
6540 /* Disable RSS */
6541 static void
6542 i40e_pf_disable_rss(struct i40e_pf *pf)
6543 {
6544         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6545         uint64_t hena;
6546
6547         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6548         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6549         if (hw->mac.type == I40E_MAC_X722)
6550                 hena &= ~I40E_RSS_HENA_ALL_X722;
6551         else
6552                 hena &= ~I40E_RSS_HENA_ALL;
6553         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6554         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6555         I40E_WRITE_FLUSH(hw);
6556 }
6557
6558 static int
6559 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6560 {
6561         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6562         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6563         int ret = 0;
6564
6565         if (!key || key_len == 0) {
6566                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6567                 return 0;
6568         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6569                 sizeof(uint32_t)) {
6570                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6571                 return -EINVAL;
6572         }
6573
6574         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6575                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6576                         (struct i40e_aqc_get_set_rss_key_data *)key;
6577
6578                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6579                 if (ret)
6580                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6581         } else {
6582                 uint32_t *hash_key = (uint32_t *)key;
6583                 uint16_t i;
6584
6585                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6586                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6587                 I40E_WRITE_FLUSH(hw);
6588         }
6589
6590         return ret;
6591 }
6592
6593 static int
6594 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6595 {
6596         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6597         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6598         int ret;
6599
6600         if (!key || !key_len)
6601                 return -EINVAL;
6602
6603         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6604                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6605                         (struct i40e_aqc_get_set_rss_key_data *)key);
6606                 if (ret) {
6607                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6608                         return ret;
6609                 }
6610         } else {
6611                 uint32_t *key_dw = (uint32_t *)key;
6612                 uint16_t i;
6613
6614                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6615                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6616         }
6617         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6618
6619         return 0;
6620 }
6621
6622 static int
6623 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6624 {
6625         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6626         uint64_t rss_hf;
6627         uint64_t hena;
6628         int ret;
6629
6630         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6631                                rss_conf->rss_key_len);
6632         if (ret)
6633                 return ret;
6634
6635         rss_hf = rss_conf->rss_hf;
6636         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6637         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6638         if (hw->mac.type == I40E_MAC_X722)
6639                 hena &= ~I40E_RSS_HENA_ALL_X722;
6640         else
6641                 hena &= ~I40E_RSS_HENA_ALL;
6642         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6643         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6644         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6645         I40E_WRITE_FLUSH(hw);
6646
6647         return 0;
6648 }
6649
6650 static int
6651 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6652                          struct rte_eth_rss_conf *rss_conf)
6653 {
6654         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6656         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6657         uint64_t hena;
6658
6659         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6660         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6661         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6662                  ? I40E_RSS_HENA_ALL_X722
6663                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6664                 if (rss_hf != 0) /* Enable RSS */
6665                         return -EINVAL;
6666                 return 0; /* Nothing to do */
6667         }
6668         /* RSS enabled */
6669         if (rss_hf == 0) /* Disable RSS */
6670                 return -EINVAL;
6671
6672         return i40e_hw_rss_hash_set(pf, rss_conf);
6673 }
6674
6675 static int
6676 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6677                            struct rte_eth_rss_conf *rss_conf)
6678 {
6679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6681         uint64_t hena;
6682
6683         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6684                          &rss_conf->rss_key_len);
6685
6686         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6687         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6688         rss_conf->rss_hf = i40e_parse_hena(hena);
6689
6690         return 0;
6691 }
6692
6693 static int
6694 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6695 {
6696         switch (filter_type) {
6697         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6698                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6699                 break;
6700         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6701                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6702                 break;
6703         case RTE_TUNNEL_FILTER_IMAC_TENID:
6704                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6705                 break;
6706         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6707                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6708                 break;
6709         case ETH_TUNNEL_FILTER_IMAC:
6710                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6711                 break;
6712         case ETH_TUNNEL_FILTER_OIP:
6713                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6714                 break;
6715         case ETH_TUNNEL_FILTER_IIP:
6716                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6717                 break;
6718         default:
6719                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6720                 return -EINVAL;
6721         }
6722
6723         return 0;
6724 }
6725
6726 /* Convert tunnel filter structure */
6727 static int
6728 i40e_tunnel_filter_convert(
6729         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6730         struct i40e_tunnel_filter *tunnel_filter)
6731 {
6732         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6733                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6734         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6735                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6736         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6737         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6738              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6739             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6740                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6741         else
6742                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6743         tunnel_filter->input.flags = cld_filter->element.flags;
6744         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6745         tunnel_filter->queue = cld_filter->element.queue_number;
6746         rte_memcpy(tunnel_filter->input.general_fields,
6747                    cld_filter->general_fields,
6748                    sizeof(cld_filter->general_fields));
6749
6750         return 0;
6751 }
6752
6753 /* Check if there exists the tunnel filter */
6754 struct i40e_tunnel_filter *
6755 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6756                              const struct i40e_tunnel_filter_input *input)
6757 {
6758         int ret;
6759
6760         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6761         if (ret < 0)
6762                 return NULL;
6763
6764         return tunnel_rule->hash_map[ret];
6765 }
6766
6767 /* Add a tunnel filter into the SW list */
6768 static int
6769 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6770                              struct i40e_tunnel_filter *tunnel_filter)
6771 {
6772         struct i40e_tunnel_rule *rule = &pf->tunnel;
6773         int ret;
6774
6775         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6776         if (ret < 0) {
6777                 PMD_DRV_LOG(ERR,
6778                             "Failed to insert tunnel filter to hash table %d!",
6779                             ret);
6780                 return ret;
6781         }
6782         rule->hash_map[ret] = tunnel_filter;
6783
6784         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6785
6786         return 0;
6787 }
6788
6789 /* Delete a tunnel filter from the SW list */
6790 int
6791 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6792                           struct i40e_tunnel_filter_input *input)
6793 {
6794         struct i40e_tunnel_rule *rule = &pf->tunnel;
6795         struct i40e_tunnel_filter *tunnel_filter;
6796         int ret;
6797
6798         ret = rte_hash_del_key(rule->hash_table, input);
6799         if (ret < 0) {
6800                 PMD_DRV_LOG(ERR,
6801                             "Failed to delete tunnel filter to hash table %d!",
6802                             ret);
6803                 return ret;
6804         }
6805         tunnel_filter = rule->hash_map[ret];
6806         rule->hash_map[ret] = NULL;
6807
6808         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6809         rte_free(tunnel_filter);
6810
6811         return 0;
6812 }
6813
6814 int
6815 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6816                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6817                         uint8_t add)
6818 {
6819         uint16_t ip_type;
6820         uint32_t ipv4_addr;
6821         uint8_t i, tun_type = 0;
6822         /* internal varialbe to convert ipv6 byte order */
6823         uint32_t convert_ipv6[4];
6824         int val, ret = 0;
6825         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6826         struct i40e_vsi *vsi = pf->main_vsi;
6827         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6828         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6829         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6830         struct i40e_tunnel_filter *tunnel, *node;
6831         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6832
6833         cld_filter = rte_zmalloc("tunnel_filter",
6834                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6835         0);
6836
6837         if (NULL == cld_filter) {
6838                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6839                 return -ENOMEM;
6840         }
6841         pfilter = cld_filter;
6842
6843         ether_addr_copy(&tunnel_filter->outer_mac,
6844                         (struct ether_addr *)&pfilter->element.outer_mac);
6845         ether_addr_copy(&tunnel_filter->inner_mac,
6846                         (struct ether_addr *)&pfilter->element.inner_mac);
6847
6848         pfilter->element.inner_vlan =
6849                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6850         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6851                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6852                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6853                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6854                                 &rte_cpu_to_le_32(ipv4_addr),
6855                                 sizeof(pfilter->element.ipaddr.v4.data));
6856         } else {
6857                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6858                 for (i = 0; i < 4; i++) {
6859                         convert_ipv6[i] =
6860                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6861                 }
6862                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6863                            &convert_ipv6,
6864                            sizeof(pfilter->element.ipaddr.v6.data));
6865         }
6866
6867         /* check tunneled type */
6868         switch (tunnel_filter->tunnel_type) {
6869         case RTE_TUNNEL_TYPE_VXLAN:
6870                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6871                 break;
6872         case RTE_TUNNEL_TYPE_NVGRE:
6873                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6874                 break;
6875         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6876                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6877                 break;
6878         default:
6879                 /* Other tunnel types is not supported. */
6880                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6881                 rte_free(cld_filter);
6882                 return -EINVAL;
6883         }
6884
6885         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6886                                        &pfilter->element.flags);
6887         if (val < 0) {
6888                 rte_free(cld_filter);
6889                 return -EINVAL;
6890         }
6891
6892         pfilter->element.flags |= rte_cpu_to_le_16(
6893                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6894                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6895         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6896         pfilter->element.queue_number =
6897                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6898
6899         /* Check if there is the filter in SW list */
6900         memset(&check_filter, 0, sizeof(check_filter));
6901         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6902         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6903         if (add && node) {
6904                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6905                 return -EINVAL;
6906         }
6907
6908         if (!add && !node) {
6909                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6910                 return -EINVAL;
6911         }
6912
6913         if (add) {
6914                 ret = i40e_aq_add_cloud_filters(hw,
6915                                         vsi->seid, &cld_filter->element, 1);
6916                 if (ret < 0) {
6917                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6918                         return -ENOTSUP;
6919                 }
6920                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6921                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6922                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6923         } else {
6924                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6925                                                    &cld_filter->element, 1);
6926                 if (ret < 0) {
6927                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6928                         return -ENOTSUP;
6929                 }
6930                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6931         }
6932
6933         rte_free(cld_filter);
6934         return ret;
6935 }
6936
6937 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6938 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6939 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6940 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6941 #define I40E_TR_GRE_KEY_MASK                    0x400
6942 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6943 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6944
6945 static enum
6946 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6947 {
6948         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6949         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6950         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6951         enum i40e_status_code status = I40E_SUCCESS;
6952
6953         memset(&filter_replace, 0,
6954                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6955         memset(&filter_replace_buf, 0,
6956                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6957
6958         /* create L1 filter */
6959         filter_replace.old_filter_type =
6960                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6961         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6962         filter_replace.tr_bit = 0;
6963
6964         /* Prepare the buffer, 3 entries */
6965         filter_replace_buf.data[0] =
6966                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6967         filter_replace_buf.data[0] |=
6968                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6969         filter_replace_buf.data[2] = 0xFF;
6970         filter_replace_buf.data[3] = 0xFF;
6971         filter_replace_buf.data[4] =
6972                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6973         filter_replace_buf.data[4] |=
6974                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6975         filter_replace_buf.data[7] = 0xF0;
6976         filter_replace_buf.data[8]
6977                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6978         filter_replace_buf.data[8] |=
6979                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6980         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6981                 I40E_TR_GENEVE_KEY_MASK |
6982                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6983         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6984                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6985                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6986
6987         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6988                                                &filter_replace_buf);
6989         return status;
6990 }
6991
6992 static enum
6993 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6994 {
6995         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6996         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6997         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6998         enum i40e_status_code status = I40E_SUCCESS;
6999
7000         /* For MPLSoUDP */
7001         memset(&filter_replace, 0,
7002                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7003         memset(&filter_replace_buf, 0,
7004                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7005         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7006                 I40E_AQC_MIRROR_CLOUD_FILTER;
7007         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7008         filter_replace.new_filter_type =
7009                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7010         /* Prepare the buffer, 2 entries */
7011         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7012         filter_replace_buf.data[0] |=
7013                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7014         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7015         filter_replace_buf.data[4] |=
7016                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7017         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7018                                                &filter_replace_buf);
7019         if (status < 0)
7020                 return status;
7021
7022         /* For MPLSoGRE */
7023         memset(&filter_replace, 0,
7024                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7025         memset(&filter_replace_buf, 0,
7026                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7027
7028         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7029                 I40E_AQC_MIRROR_CLOUD_FILTER;
7030         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7031         filter_replace.new_filter_type =
7032                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7033         /* Prepare the buffer, 2 entries */
7034         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7035         filter_replace_buf.data[0] |=
7036                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7037         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7038         filter_replace_buf.data[4] |=
7039                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7040
7041         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7042                                                &filter_replace_buf);
7043         return status;
7044 }
7045
7046 int
7047 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7048                       struct i40e_tunnel_filter_conf *tunnel_filter,
7049                       uint8_t add)
7050 {
7051         uint16_t ip_type;
7052         uint32_t ipv4_addr;
7053         uint8_t i, tun_type = 0;
7054         /* internal variable to convert ipv6 byte order */
7055         uint32_t convert_ipv6[4];
7056         int val, ret = 0;
7057         struct i40e_pf_vf *vf = NULL;
7058         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7059         struct i40e_vsi *vsi;
7060         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7061         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7062         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7063         struct i40e_tunnel_filter *tunnel, *node;
7064         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7065         uint32_t teid_le;
7066         bool big_buffer = 0;
7067
7068         cld_filter = rte_zmalloc("tunnel_filter",
7069                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7070                          0);
7071
7072         if (cld_filter == NULL) {
7073                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7074                 return -ENOMEM;
7075         }
7076         pfilter = cld_filter;
7077
7078         ether_addr_copy(&tunnel_filter->outer_mac,
7079                         (struct ether_addr *)&pfilter->element.outer_mac);
7080         ether_addr_copy(&tunnel_filter->inner_mac,
7081                         (struct ether_addr *)&pfilter->element.inner_mac);
7082
7083         pfilter->element.inner_vlan =
7084                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7085         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7086                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7087                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7088                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7089                                 &rte_cpu_to_le_32(ipv4_addr),
7090                                 sizeof(pfilter->element.ipaddr.v4.data));
7091         } else {
7092                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7093                 for (i = 0; i < 4; i++) {
7094                         convert_ipv6[i] =
7095                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7096                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7097                 }
7098                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7099                            &convert_ipv6,
7100                            sizeof(pfilter->element.ipaddr.v6.data));
7101         }
7102
7103         /* check tunneled type */
7104         switch (tunnel_filter->tunnel_type) {
7105         case I40E_TUNNEL_TYPE_VXLAN:
7106                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7107                 break;
7108         case I40E_TUNNEL_TYPE_NVGRE:
7109                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7110                 break;
7111         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7112                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7113                 break;
7114         case I40E_TUNNEL_TYPE_MPLSoUDP:
7115                 if (!pf->mpls_replace_flag) {
7116                         i40e_replace_mpls_l1_filter(pf);
7117                         i40e_replace_mpls_cloud_filter(pf);
7118                         pf->mpls_replace_flag = 1;
7119                 }
7120                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7121                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7122                         teid_le >> 4;
7123                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7124                         (teid_le & 0xF) << 12;
7125                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7126                         0x40;
7127                 big_buffer = 1;
7128                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7129                 break;
7130         case I40E_TUNNEL_TYPE_MPLSoGRE:
7131                 if (!pf->mpls_replace_flag) {
7132                         i40e_replace_mpls_l1_filter(pf);
7133                         i40e_replace_mpls_cloud_filter(pf);
7134                         pf->mpls_replace_flag = 1;
7135                 }
7136                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7137                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7138                         teid_le >> 4;
7139                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7140                         (teid_le & 0xF) << 12;
7141                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7142                         0x0;
7143                 big_buffer = 1;
7144                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7145                 break;
7146         case I40E_TUNNEL_TYPE_QINQ:
7147                 if (!pf->qinq_replace_flag) {
7148                         ret = i40e_cloud_filter_qinq_create(pf);
7149                         if (ret < 0)
7150                                 PMD_DRV_LOG(ERR,
7151                                         "Failed to create a qinq tunnel filter.");
7152                         pf->qinq_replace_flag = 1;
7153                 }
7154                 /*      Add in the General fields the values of
7155                  *      the Outer and Inner VLAN
7156                  *      Big Buffer should be set, see changes in
7157                  *      i40e_aq_add_cloud_filters
7158                  */
7159                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7160                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7161                 big_buffer = 1;
7162                 break;
7163         default:
7164                 /* Other tunnel types is not supported. */
7165                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7166                 rte_free(cld_filter);
7167                 return -EINVAL;
7168         }
7169
7170         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7171                 pfilter->element.flags =
7172                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7173         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7174                 pfilter->element.flags =
7175                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7176         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7177                 pfilter->element.flags |=
7178                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7179         else {
7180                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7181                                                 &pfilter->element.flags);
7182                 if (val < 0) {
7183                         rte_free(cld_filter);
7184                         return -EINVAL;
7185                 }
7186         }
7187
7188         pfilter->element.flags |= rte_cpu_to_le_16(
7189                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7190                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7191         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7192         pfilter->element.queue_number =
7193                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7194
7195         if (!tunnel_filter->is_to_vf)
7196                 vsi = pf->main_vsi;
7197         else {
7198                 if (tunnel_filter->vf_id >= pf->vf_num) {
7199                         PMD_DRV_LOG(ERR, "Invalid argument.");
7200                         return -EINVAL;
7201                 }
7202                 vf = &pf->vfs[tunnel_filter->vf_id];
7203                 vsi = vf->vsi;
7204         }
7205
7206         /* Check if there is the filter in SW list */
7207         memset(&check_filter, 0, sizeof(check_filter));
7208         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7209         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7210         check_filter.vf_id = tunnel_filter->vf_id;
7211         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7212         if (add && node) {
7213                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7214                 return -EINVAL;
7215         }
7216
7217         if (!add && !node) {
7218                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7219                 return -EINVAL;
7220         }
7221
7222         if (add) {
7223                 if (big_buffer)
7224                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7225                                                    vsi->seid, cld_filter, 1);
7226                 else
7227                         ret = i40e_aq_add_cloud_filters(hw,
7228                                         vsi->seid, &cld_filter->element, 1);
7229                 if (ret < 0) {
7230                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7231                         return -ENOTSUP;
7232                 }
7233                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7234                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7235                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7236         } else {
7237                 if (big_buffer)
7238                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7239                                 hw, vsi->seid, cld_filter, 1);
7240                 else
7241                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7242                                                    &cld_filter->element, 1);
7243                 if (ret < 0) {
7244                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7245                         return -ENOTSUP;
7246                 }
7247                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7248         }
7249
7250         rte_free(cld_filter);
7251         return ret;
7252 }
7253
7254 static int
7255 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7256 {
7257         uint8_t i;
7258
7259         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7260                 if (pf->vxlan_ports[i] == port)
7261                         return i;
7262         }
7263
7264         return -1;
7265 }
7266
7267 static int
7268 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7269 {
7270         int  idx, ret;
7271         uint8_t filter_idx;
7272         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7273
7274         idx = i40e_get_vxlan_port_idx(pf, port);
7275
7276         /* Check if port already exists */
7277         if (idx >= 0) {
7278                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7279                 return -EINVAL;
7280         }
7281
7282         /* Now check if there is space to add the new port */
7283         idx = i40e_get_vxlan_port_idx(pf, 0);
7284         if (idx < 0) {
7285                 PMD_DRV_LOG(ERR,
7286                         "Maximum number of UDP ports reached, not adding port %d",
7287                         port);
7288                 return -ENOSPC;
7289         }
7290
7291         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7292                                         &filter_idx, NULL);
7293         if (ret < 0) {
7294                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7295                 return -1;
7296         }
7297
7298         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7299                          port,  filter_idx);
7300
7301         /* New port: add it and mark its index in the bitmap */
7302         pf->vxlan_ports[idx] = port;
7303         pf->vxlan_bitmap |= (1 << idx);
7304
7305         if (!(pf->flags & I40E_FLAG_VXLAN))
7306                 pf->flags |= I40E_FLAG_VXLAN;
7307
7308         return 0;
7309 }
7310
7311 static int
7312 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7313 {
7314         int idx;
7315         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7316
7317         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7318                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7319                 return -EINVAL;
7320         }
7321
7322         idx = i40e_get_vxlan_port_idx(pf, port);
7323
7324         if (idx < 0) {
7325                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7326                 return -EINVAL;
7327         }
7328
7329         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7330                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7331                 return -1;
7332         }
7333
7334         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7335                         port, idx);
7336
7337         pf->vxlan_ports[idx] = 0;
7338         pf->vxlan_bitmap &= ~(1 << idx);
7339
7340         if (!pf->vxlan_bitmap)
7341                 pf->flags &= ~I40E_FLAG_VXLAN;
7342
7343         return 0;
7344 }
7345
7346 /* Add UDP tunneling port */
7347 static int
7348 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7349                              struct rte_eth_udp_tunnel *udp_tunnel)
7350 {
7351         int ret = 0;
7352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7353
7354         if (udp_tunnel == NULL)
7355                 return -EINVAL;
7356
7357         switch (udp_tunnel->prot_type) {
7358         case RTE_TUNNEL_TYPE_VXLAN:
7359                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7360                 break;
7361
7362         case RTE_TUNNEL_TYPE_GENEVE:
7363         case RTE_TUNNEL_TYPE_TEREDO:
7364                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7365                 ret = -1;
7366                 break;
7367
7368         default:
7369                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7370                 ret = -1;
7371                 break;
7372         }
7373
7374         return ret;
7375 }
7376
7377 /* Remove UDP tunneling port */
7378 static int
7379 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7380                              struct rte_eth_udp_tunnel *udp_tunnel)
7381 {
7382         int ret = 0;
7383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7384
7385         if (udp_tunnel == NULL)
7386                 return -EINVAL;
7387
7388         switch (udp_tunnel->prot_type) {
7389         case RTE_TUNNEL_TYPE_VXLAN:
7390                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7391                 break;
7392         case RTE_TUNNEL_TYPE_GENEVE:
7393         case RTE_TUNNEL_TYPE_TEREDO:
7394                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7395                 ret = -1;
7396                 break;
7397         default:
7398                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7399                 ret = -1;
7400                 break;
7401         }
7402
7403         return ret;
7404 }
7405
7406 /* Calculate the maximum number of contiguous PF queues that are configured */
7407 static int
7408 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7409 {
7410         struct rte_eth_dev_data *data = pf->dev_data;
7411         int i, num;
7412         struct i40e_rx_queue *rxq;
7413
7414         num = 0;
7415         for (i = 0; i < pf->lan_nb_qps; i++) {
7416                 rxq = data->rx_queues[i];
7417                 if (rxq && rxq->q_set)
7418                         num++;
7419                 else
7420                         break;
7421         }
7422
7423         return num;
7424 }
7425
7426 /* Configure RSS */
7427 static int
7428 i40e_pf_config_rss(struct i40e_pf *pf)
7429 {
7430         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7431         struct rte_eth_rss_conf rss_conf;
7432         uint32_t i, lut = 0;
7433         uint16_t j, num;
7434
7435         /*
7436          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7437          * It's necessary to calulate the actual PF queues that are configured.
7438          */
7439         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7440                 num = i40e_pf_calc_configured_queues_num(pf);
7441         else
7442                 num = pf->dev_data->nb_rx_queues;
7443
7444         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7445         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7446                         num);
7447
7448         if (num == 0) {
7449                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7450                 return -ENOTSUP;
7451         }
7452
7453         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7454                 if (j == num)
7455                         j = 0;
7456                 lut = (lut << 8) | (j & ((0x1 <<
7457                         hw->func_caps.rss_table_entry_width) - 1));
7458                 if ((i & 3) == 3)
7459                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7460         }
7461
7462         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7463         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7464                 i40e_pf_disable_rss(pf);
7465                 return 0;
7466         }
7467         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7468                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7469                 /* Random default keys */
7470                 static uint32_t rss_key_default[] = {0x6b793944,
7471                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7472                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7473                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7474
7475                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7476                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7477                                                         sizeof(uint32_t);
7478         }
7479
7480         return i40e_hw_rss_hash_set(pf, &rss_conf);
7481 }
7482
7483 static int
7484 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7485                                struct rte_eth_tunnel_filter_conf *filter)
7486 {
7487         if (pf == NULL || filter == NULL) {
7488                 PMD_DRV_LOG(ERR, "Invalid parameter");
7489                 return -EINVAL;
7490         }
7491
7492         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7493                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7494                 return -EINVAL;
7495         }
7496
7497         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7498                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7499                 return -EINVAL;
7500         }
7501
7502         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7503                 (is_zero_ether_addr(&filter->outer_mac))) {
7504                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7505                 return -EINVAL;
7506         }
7507
7508         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7509                 (is_zero_ether_addr(&filter->inner_mac))) {
7510                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7511                 return -EINVAL;
7512         }
7513
7514         return 0;
7515 }
7516
7517 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7518 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7519 static int
7520 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7521 {
7522         uint32_t val, reg;
7523         int ret = -EINVAL;
7524
7525         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7526         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7527
7528         if (len == 3) {
7529                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7530         } else if (len == 4) {
7531                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7532         } else {
7533                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7534                 return ret;
7535         }
7536
7537         if (reg != val) {
7538                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7539                                                    reg, NULL);
7540                 if (ret != 0)
7541                         return ret;
7542         } else {
7543                 ret = 0;
7544         }
7545         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7546                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7547
7548         return ret;
7549 }
7550
7551 static int
7552 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7553 {
7554         int ret = -EINVAL;
7555
7556         if (!hw || !cfg)
7557                 return -EINVAL;
7558
7559         switch (cfg->cfg_type) {
7560         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7561                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7562                 break;
7563         default:
7564                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7565                 break;
7566         }
7567
7568         return ret;
7569 }
7570
7571 static int
7572 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7573                                enum rte_filter_op filter_op,
7574                                void *arg)
7575 {
7576         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7577         int ret = I40E_ERR_PARAM;
7578
7579         switch (filter_op) {
7580         case RTE_ETH_FILTER_SET:
7581                 ret = i40e_dev_global_config_set(hw,
7582                         (struct rte_eth_global_cfg *)arg);
7583                 break;
7584         default:
7585                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7586                 break;
7587         }
7588
7589         return ret;
7590 }
7591
7592 static int
7593 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7594                           enum rte_filter_op filter_op,
7595                           void *arg)
7596 {
7597         struct rte_eth_tunnel_filter_conf *filter;
7598         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7599         int ret = I40E_SUCCESS;
7600
7601         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7602
7603         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7604                 return I40E_ERR_PARAM;
7605
7606         switch (filter_op) {
7607         case RTE_ETH_FILTER_NOP:
7608                 if (!(pf->flags & I40E_FLAG_VXLAN))
7609                         ret = I40E_NOT_SUPPORTED;
7610                 break;
7611         case RTE_ETH_FILTER_ADD:
7612                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7613                 break;
7614         case RTE_ETH_FILTER_DELETE:
7615                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7616                 break;
7617         default:
7618                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7619                 ret = I40E_ERR_PARAM;
7620                 break;
7621         }
7622
7623         return ret;
7624 }
7625
7626 static int
7627 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7628 {
7629         int ret = 0;
7630         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7631
7632         /* RSS setup */
7633         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7634                 ret = i40e_pf_config_rss(pf);
7635         else
7636                 i40e_pf_disable_rss(pf);
7637
7638         return ret;
7639 }
7640
7641 /* Get the symmetric hash enable configurations per port */
7642 static void
7643 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7644 {
7645         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7646
7647         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7648 }
7649
7650 /* Set the symmetric hash enable configurations per port */
7651 static void
7652 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7653 {
7654         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7655
7656         if (enable > 0) {
7657                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7658                         PMD_DRV_LOG(INFO,
7659                                 "Symmetric hash has already been enabled");
7660                         return;
7661                 }
7662                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7663         } else {
7664                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7665                         PMD_DRV_LOG(INFO,
7666                                 "Symmetric hash has already been disabled");
7667                         return;
7668                 }
7669                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7670         }
7671         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7672         I40E_WRITE_FLUSH(hw);
7673 }
7674
7675 /*
7676  * Get global configurations of hash function type and symmetric hash enable
7677  * per flow type (pctype). Note that global configuration means it affects all
7678  * the ports on the same NIC.
7679  */
7680 static int
7681 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7682                                    struct rte_eth_hash_global_conf *g_cfg)
7683 {
7684         uint32_t reg, mask = I40E_FLOW_TYPES;
7685         uint16_t i;
7686         enum i40e_filter_pctype pctype;
7687
7688         memset(g_cfg, 0, sizeof(*g_cfg));
7689         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7690         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7691                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7692         else
7693                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7694         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7695                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7696
7697         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7698                 if (!(mask & (1UL << i)))
7699                         continue;
7700                 mask &= ~(1UL << i);
7701                 /* Bit set indicats the coresponding flow type is supported */
7702                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7703                 /* if flowtype is invalid, continue */
7704                 if (!I40E_VALID_FLOW(i))
7705                         continue;
7706                 pctype = i40e_flowtype_to_pctype(i);
7707                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7708                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7709                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7710         }
7711
7712         return 0;
7713 }
7714
7715 static int
7716 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7717 {
7718         uint32_t i;
7719         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7720
7721         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7722                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7723                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7724                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7725                                                 g_cfg->hash_func);
7726                 return -EINVAL;
7727         }
7728
7729         /*
7730          * As i40e supports less than 32 flow types, only first 32 bits need to
7731          * be checked.
7732          */
7733         mask0 = g_cfg->valid_bit_mask[0];
7734         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7735                 if (i == 0) {
7736                         /* Check if any unsupported flow type configured */
7737                         if ((mask0 | i40e_mask) ^ i40e_mask)
7738                                 goto mask_err;
7739                 } else {
7740                         if (g_cfg->valid_bit_mask[i])
7741                                 goto mask_err;
7742                 }
7743         }
7744
7745         return 0;
7746
7747 mask_err:
7748         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7749
7750         return -EINVAL;
7751 }
7752
7753 /*
7754  * Set global configurations of hash function type and symmetric hash enable
7755  * per flow type (pctype). Note any modifying global configuration will affect
7756  * all the ports on the same NIC.
7757  */
7758 static int
7759 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7760                                    struct rte_eth_hash_global_conf *g_cfg)
7761 {
7762         int ret;
7763         uint16_t i;
7764         uint32_t reg;
7765         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7766         enum i40e_filter_pctype pctype;
7767
7768         /* Check the input parameters */
7769         ret = i40e_hash_global_config_check(g_cfg);
7770         if (ret < 0)
7771                 return ret;
7772
7773         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7774                 if (!(mask0 & (1UL << i)))
7775                         continue;
7776                 mask0 &= ~(1UL << i);
7777                 /* if flowtype is invalid, continue */
7778                 if (!I40E_VALID_FLOW(i))
7779                         continue;
7780                 pctype = i40e_flowtype_to_pctype(i);
7781                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7782                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7783                 if (hw->mac.type == I40E_MAC_X722) {
7784                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7785                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7786                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7787                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7788                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7789                                   reg);
7790                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7791                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7792                                   reg);
7793                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7794                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7795                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7796                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7797                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7798                                   reg);
7799                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7800                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7801                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7802                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7803                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7804                                   reg);
7805                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7806                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7807                                   reg);
7808                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7809                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7810                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7811                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7812                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7813                                   reg);
7814                         } else {
7815                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7816                                   reg);
7817                         }
7818                 } else {
7819                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7820                 }
7821         }
7822
7823         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7824         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7825                 /* Toeplitz */
7826                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7827                         PMD_DRV_LOG(DEBUG,
7828                                 "Hash function already set to Toeplitz");
7829                         goto out;
7830                 }
7831                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7832         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7833                 /* Simple XOR */
7834                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7835                         PMD_DRV_LOG(DEBUG,
7836                                 "Hash function already set to Simple XOR");
7837                         goto out;
7838                 }
7839                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7840         } else
7841                 /* Use the default, and keep it as it is */
7842                 goto out;
7843
7844         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7845
7846 out:
7847         I40E_WRITE_FLUSH(hw);
7848
7849         return 0;
7850 }
7851
7852 /**
7853  * Valid input sets for hash and flow director filters per PCTYPE
7854  */
7855 static uint64_t
7856 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7857                 enum rte_filter_type filter)
7858 {
7859         uint64_t valid;
7860
7861         static const uint64_t valid_hash_inset_table[] = {
7862                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7863                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7864                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7865                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7866                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7867                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7868                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7869                         I40E_INSET_FLEX_PAYLOAD,
7870                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7871                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7872                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7873                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7874                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7875                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7876                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7877                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7878                         I40E_INSET_FLEX_PAYLOAD,
7879                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7880                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7881                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7882                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7883                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7884                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7885                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7886                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7887                         I40E_INSET_FLEX_PAYLOAD,
7888                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7889                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7890                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7891                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7892                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7893                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7894                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7895                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7896                         I40E_INSET_FLEX_PAYLOAD,
7897                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7898                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7899                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7900                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7901                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7902                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7903                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7904                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7905                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7906                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7907                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7908                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7909                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7910                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7911                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7912                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7913                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7914                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7915                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7916                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7917                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7918                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7919                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7920                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7921                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7922                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7923                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7924                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7925                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7926                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7927                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7928                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7929                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7930                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7931                         I40E_INSET_FLEX_PAYLOAD,
7932                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7933                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7934                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7935                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7936                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7937                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7938                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7939                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7940                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7941                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7942                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7943                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7944                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7945                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7946                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7947                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7948                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7949                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7950                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7951                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7952                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7953                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7954                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7955                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7956                         I40E_INSET_FLEX_PAYLOAD,
7957                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7958                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7959                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7960                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7961                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7962                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7963                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7964                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7965                         I40E_INSET_FLEX_PAYLOAD,
7966                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7967                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7968                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7969                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7970                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7971                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7972                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7973                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7974                         I40E_INSET_FLEX_PAYLOAD,
7975                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7976                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7977                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7978                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7979                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7980                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7981                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7982                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7983                         I40E_INSET_FLEX_PAYLOAD,
7984                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7985                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7986                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7987                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7988                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7989                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7990                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7991                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7992                         I40E_INSET_FLEX_PAYLOAD,
7993                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7994                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7995                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7996                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7997                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7998                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7999                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8000                         I40E_INSET_FLEX_PAYLOAD,
8001                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8002                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8003                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8005                         I40E_INSET_FLEX_PAYLOAD,
8006         };
8007
8008         /**
8009          * Flow director supports only fields defined in
8010          * union rte_eth_fdir_flow.
8011          */
8012         static const uint64_t valid_fdir_inset_table[] = {
8013                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8014                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8015                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8016                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8017                 I40E_INSET_IPV4_TTL,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8019                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8020                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8021                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8022                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8023                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8024                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8025                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8026                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8027                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8028                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8029                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8031                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8032                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8033                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8034                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8035                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8036                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8037                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8038                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8039                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8041                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8042                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8043                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8044                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8046                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8047                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8048                 I40E_INSET_SCTP_VT,
8049                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8050                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8051                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8052                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8053                 I40E_INSET_IPV4_TTL,
8054                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8055                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8056                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8057                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8058                 I40E_INSET_IPV6_HOP_LIMIT,
8059                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8060                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8061                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8062                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8063                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8064                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8065                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8067                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8068                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8069                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8070                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8071                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8072                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8073                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8074                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8075                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8076                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8077                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8078                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8079                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8080                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8082                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8083                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8084                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8085                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8086                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8087                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8088                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8089                 I40E_INSET_SCTP_VT,
8090                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8091                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8092                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8093                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8094                 I40E_INSET_IPV6_HOP_LIMIT,
8095                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8096                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8097                 I40E_INSET_LAST_ETHER_TYPE,
8098         };
8099
8100         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8101                 return 0;
8102         if (filter == RTE_ETH_FILTER_HASH)
8103                 valid = valid_hash_inset_table[pctype];
8104         else
8105                 valid = valid_fdir_inset_table[pctype];
8106
8107         return valid;
8108 }
8109
8110 /**
8111  * Validate if the input set is allowed for a specific PCTYPE
8112  */
8113 static int
8114 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8115                 enum rte_filter_type filter, uint64_t inset)
8116 {
8117         uint64_t valid;
8118
8119         valid = i40e_get_valid_input_set(pctype, filter);
8120         if (inset & (~valid))
8121                 return -EINVAL;
8122
8123         return 0;
8124 }
8125
8126 /* default input set fields combination per pctype */
8127 uint64_t
8128 i40e_get_default_input_set(uint16_t pctype)
8129 {
8130         static const uint64_t default_inset_table[] = {
8131                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8132                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8133                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8134                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8135                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8136                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8137                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8138                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8139                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8140                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8141                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8142                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8143                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8145                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8146                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8147                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8148                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8149                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8150                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8151                         I40E_INSET_SCTP_VT,
8152                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8153                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8154                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8155                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8156                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8157                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8158                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8159                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8160                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8161                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8162                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8163                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8165                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8166                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8167                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8168                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8169                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8170                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8172                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8173                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8174                         I40E_INSET_SCTP_VT,
8175                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8176                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8177                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8178                         I40E_INSET_LAST_ETHER_TYPE,
8179         };
8180
8181         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8182                 return 0;
8183
8184         return default_inset_table[pctype];
8185 }
8186
8187 /**
8188  * Parse the input set from index to logical bit masks
8189  */
8190 static int
8191 i40e_parse_input_set(uint64_t *inset,
8192                      enum i40e_filter_pctype pctype,
8193                      enum rte_eth_input_set_field *field,
8194                      uint16_t size)
8195 {
8196         uint16_t i, j;
8197         int ret = -EINVAL;
8198
8199         static const struct {
8200                 enum rte_eth_input_set_field field;
8201                 uint64_t inset;
8202         } inset_convert_table[] = {
8203                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8204                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8205                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8206                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8207                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8208                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8209                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8210                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8211                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8212                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8213                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8214                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8215                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8216                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8217                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8218                         I40E_INSET_IPV6_NEXT_HDR},
8219                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8220                         I40E_INSET_IPV6_HOP_LIMIT},
8221                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8222                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8223                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8224                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8225                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8226                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8227                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8228                         I40E_INSET_SCTP_VT},
8229                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8230                         I40E_INSET_TUNNEL_DMAC},
8231                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8232                         I40E_INSET_VLAN_TUNNEL},
8233                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8234                         I40E_INSET_TUNNEL_ID},
8235                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8236                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8237                         I40E_INSET_FLEX_PAYLOAD_W1},
8238                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8239                         I40E_INSET_FLEX_PAYLOAD_W2},
8240                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8241                         I40E_INSET_FLEX_PAYLOAD_W3},
8242                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8243                         I40E_INSET_FLEX_PAYLOAD_W4},
8244                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8245                         I40E_INSET_FLEX_PAYLOAD_W5},
8246                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8247                         I40E_INSET_FLEX_PAYLOAD_W6},
8248                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8249                         I40E_INSET_FLEX_PAYLOAD_W7},
8250                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8251                         I40E_INSET_FLEX_PAYLOAD_W8},
8252         };
8253
8254         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8255                 return ret;
8256
8257         /* Only one item allowed for default or all */
8258         if (size == 1) {
8259                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8260                         *inset = i40e_get_default_input_set(pctype);
8261                         return 0;
8262                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8263                         *inset = I40E_INSET_NONE;
8264                         return 0;
8265                 }
8266         }
8267
8268         for (i = 0, *inset = 0; i < size; i++) {
8269                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8270                         if (field[i] == inset_convert_table[j].field) {
8271                                 *inset |= inset_convert_table[j].inset;
8272                                 break;
8273                         }
8274                 }
8275
8276                 /* It contains unsupported input set, return immediately */
8277                 if (j == RTE_DIM(inset_convert_table))
8278                         return ret;
8279         }
8280
8281         return 0;
8282 }
8283
8284 /**
8285  * Translate the input set from bit masks to register aware bit masks
8286  * and vice versa
8287  */
8288 static uint64_t
8289 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8290 {
8291         uint64_t val = 0;
8292         uint16_t i;
8293
8294         struct inset_map {
8295                 uint64_t inset;
8296                 uint64_t inset_reg;
8297         };
8298
8299         static const struct inset_map inset_map_common[] = {
8300                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8301                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8302                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8303                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8304                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8305                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8306                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8307                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8308                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8309                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8310                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8311                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8312                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8313                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8314                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8315                 {I40E_INSET_TUNNEL_DMAC,
8316                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8317                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8318                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8319                 {I40E_INSET_TUNNEL_SRC_PORT,
8320                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8321                 {I40E_INSET_TUNNEL_DST_PORT,
8322                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8323                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8324                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8325                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8326                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8327                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8328                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8329                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8330                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8331                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8332         };
8333
8334     /* some different registers map in x722*/
8335         static const struct inset_map inset_map_diff_x722[] = {
8336                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8337                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8338                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8339                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8340         };
8341
8342         static const struct inset_map inset_map_diff_not_x722[] = {
8343                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8344                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8345                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8346                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8347         };
8348
8349         if (input == 0)
8350                 return val;
8351
8352         /* Translate input set to register aware inset */
8353         if (type == I40E_MAC_X722) {
8354                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8355                         if (input & inset_map_diff_x722[i].inset)
8356                                 val |= inset_map_diff_x722[i].inset_reg;
8357                 }
8358         } else {
8359                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8360                         if (input & inset_map_diff_not_x722[i].inset)
8361                                 val |= inset_map_diff_not_x722[i].inset_reg;
8362                 }
8363         }
8364
8365         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8366                 if (input & inset_map_common[i].inset)
8367                         val |= inset_map_common[i].inset_reg;
8368         }
8369
8370         return val;
8371 }
8372
8373 static int
8374 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8375 {
8376         uint8_t i, idx = 0;
8377         uint64_t inset_need_mask = inset;
8378
8379         static const struct {
8380                 uint64_t inset;
8381                 uint32_t mask;
8382         } inset_mask_map[] = {
8383                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8384                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8385                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8386                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8387                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8388                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8389                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8390                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8391         };
8392
8393         if (!inset || !mask || !nb_elem)
8394                 return 0;
8395
8396         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8397                 /* Clear the inset bit, if no MASK is required,
8398                  * for example proto + ttl
8399                  */
8400                 if ((inset & inset_mask_map[i].inset) ==
8401                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8402                         inset_need_mask &= ~inset_mask_map[i].inset;
8403                 if (!inset_need_mask)
8404                         return 0;
8405         }
8406         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8407                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8408                     inset_mask_map[i].inset) {
8409                         if (idx >= nb_elem) {
8410                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8411                                 return -EINVAL;
8412                         }
8413                         mask[idx] = inset_mask_map[i].mask;
8414                         idx++;
8415                 }
8416         }
8417
8418         return idx;
8419 }
8420
8421 static void
8422 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8423 {
8424         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8425
8426         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8427         if (reg != val)
8428                 i40e_write_rx_ctl(hw, addr, val);
8429         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8430                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8431 }
8432
8433 static void
8434 i40e_filter_input_set_init(struct i40e_pf *pf)
8435 {
8436         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8437         enum i40e_filter_pctype pctype;
8438         uint64_t input_set, inset_reg;
8439         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8440         int num, i;
8441
8442         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8443              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8444                 if (hw->mac.type == I40E_MAC_X722) {
8445                         if (!I40E_VALID_PCTYPE_X722(pctype))
8446                                 continue;
8447                 } else {
8448                         if (!I40E_VALID_PCTYPE(pctype))
8449                                 continue;
8450                 }
8451
8452                 input_set = i40e_get_default_input_set(pctype);
8453
8454                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8455                                                    I40E_INSET_MASK_NUM_REG);
8456                 if (num < 0)
8457                         return;
8458                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8459                                         input_set);
8460
8461                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8462                                       (uint32_t)(inset_reg & UINT32_MAX));
8463                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8464                                      (uint32_t)((inset_reg >>
8465                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8466                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8467                                       (uint32_t)(inset_reg & UINT32_MAX));
8468                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8469                                      (uint32_t)((inset_reg >>
8470                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8471
8472                 for (i = 0; i < num; i++) {
8473                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8474                                              mask_reg[i]);
8475                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8476                                              mask_reg[i]);
8477                 }
8478                 /*clear unused mask registers of the pctype */
8479                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8480                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8481                                              0);
8482                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8483                                              0);
8484                 }
8485                 I40E_WRITE_FLUSH(hw);
8486
8487                 /* store the default input set */
8488                 pf->hash_input_set[pctype] = input_set;
8489                 pf->fdir.input_set[pctype] = input_set;
8490         }
8491 }
8492
8493 int
8494 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8495                          struct rte_eth_input_set_conf *conf)
8496 {
8497         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8498         enum i40e_filter_pctype pctype;
8499         uint64_t input_set, inset_reg = 0;
8500         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8501         int ret, i, num;
8502
8503         if (!conf) {
8504                 PMD_DRV_LOG(ERR, "Invalid pointer");
8505                 return -EFAULT;
8506         }
8507         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8508             conf->op != RTE_ETH_INPUT_SET_ADD) {
8509                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8510                 return -EINVAL;
8511         }
8512
8513         if (!I40E_VALID_FLOW(conf->flow_type)) {
8514                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8515                 return -EINVAL;
8516         }
8517
8518         if (hw->mac.type == I40E_MAC_X722) {
8519                 /* get translated pctype value in fd pctype register */
8520                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8521                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8522                         conf->flow_type)));
8523         } else
8524                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8525
8526         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8527                                    conf->inset_size);
8528         if (ret) {
8529                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8530                 return -EINVAL;
8531         }
8532         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8533                                     input_set) != 0) {
8534                 PMD_DRV_LOG(ERR, "Invalid input set");
8535                 return -EINVAL;
8536         }
8537         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8538                 /* get inset value in register */
8539                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8540                 inset_reg <<= I40E_32_BIT_WIDTH;
8541                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8542                 input_set |= pf->hash_input_set[pctype];
8543         }
8544         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8545                                            I40E_INSET_MASK_NUM_REG);
8546         if (num < 0)
8547                 return -EINVAL;
8548
8549         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8550
8551         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8552                               (uint32_t)(inset_reg & UINT32_MAX));
8553         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8554                              (uint32_t)((inset_reg >>
8555                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8556
8557         for (i = 0; i < num; i++)
8558                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8559                                      mask_reg[i]);
8560         /*clear unused mask registers of the pctype */
8561         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8562                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8563                                      0);
8564         I40E_WRITE_FLUSH(hw);
8565
8566         pf->hash_input_set[pctype] = input_set;
8567         return 0;
8568 }
8569
8570 int
8571 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8572                          struct rte_eth_input_set_conf *conf)
8573 {
8574         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8575         enum i40e_filter_pctype pctype;
8576         uint64_t input_set, inset_reg = 0;
8577         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8578         int ret, i, num;
8579
8580         if (!hw || !conf) {
8581                 PMD_DRV_LOG(ERR, "Invalid pointer");
8582                 return -EFAULT;
8583         }
8584         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8585             conf->op != RTE_ETH_INPUT_SET_ADD) {
8586                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8587                 return -EINVAL;
8588         }
8589
8590         if (!I40E_VALID_FLOW(conf->flow_type)) {
8591                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8592                 return -EINVAL;
8593         }
8594
8595         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8596
8597         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8598                                    conf->inset_size);
8599         if (ret) {
8600                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8601                 return -EINVAL;
8602         }
8603         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8604                                     input_set) != 0) {
8605                 PMD_DRV_LOG(ERR, "Invalid input set");
8606                 return -EINVAL;
8607         }
8608
8609         /* get inset value in register */
8610         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8611         inset_reg <<= I40E_32_BIT_WIDTH;
8612         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8613
8614         /* Can not change the inset reg for flex payload for fdir,
8615          * it is done by writing I40E_PRTQF_FD_FLXINSET
8616          * in i40e_set_flex_mask_on_pctype.
8617          */
8618         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8619                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8620         else
8621                 input_set |= pf->fdir.input_set[pctype];
8622         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8623                                            I40E_INSET_MASK_NUM_REG);
8624         if (num < 0)
8625                 return -EINVAL;
8626
8627         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8628
8629         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8630                               (uint32_t)(inset_reg & UINT32_MAX));
8631         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8632                              (uint32_t)((inset_reg >>
8633                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8634
8635         for (i = 0; i < num; i++)
8636                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8637                                      mask_reg[i]);
8638         /*clear unused mask registers of the pctype */
8639         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8640                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8641                                      0);
8642         I40E_WRITE_FLUSH(hw);
8643
8644         pf->fdir.input_set[pctype] = input_set;
8645         return 0;
8646 }
8647
8648 static int
8649 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8650 {
8651         int ret = 0;
8652
8653         if (!hw || !info) {
8654                 PMD_DRV_LOG(ERR, "Invalid pointer");
8655                 return -EFAULT;
8656         }
8657
8658         switch (info->info_type) {
8659         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8660                 i40e_get_symmetric_hash_enable_per_port(hw,
8661                                         &(info->info.enable));
8662                 break;
8663         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8664                 ret = i40e_get_hash_filter_global_config(hw,
8665                                 &(info->info.global_conf));
8666                 break;
8667         default:
8668                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8669                                                         info->info_type);
8670                 ret = -EINVAL;
8671                 break;
8672         }
8673
8674         return ret;
8675 }
8676
8677 static int
8678 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8679 {
8680         int ret = 0;
8681
8682         if (!hw || !info) {
8683                 PMD_DRV_LOG(ERR, "Invalid pointer");
8684                 return -EFAULT;
8685         }
8686
8687         switch (info->info_type) {
8688         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8689                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8690                 break;
8691         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8692                 ret = i40e_set_hash_filter_global_config(hw,
8693                                 &(info->info.global_conf));
8694                 break;
8695         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8696                 ret = i40e_hash_filter_inset_select(hw,
8697                                                &(info->info.input_set_conf));
8698                 break;
8699
8700         default:
8701                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8702                                                         info->info_type);
8703                 ret = -EINVAL;
8704                 break;
8705         }
8706
8707         return ret;
8708 }
8709
8710 /* Operations for hash function */
8711 static int
8712 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8713                       enum rte_filter_op filter_op,
8714                       void *arg)
8715 {
8716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8717         int ret = 0;
8718
8719         switch (filter_op) {
8720         case RTE_ETH_FILTER_NOP:
8721                 break;
8722         case RTE_ETH_FILTER_GET:
8723                 ret = i40e_hash_filter_get(hw,
8724                         (struct rte_eth_hash_filter_info *)arg);
8725                 break;
8726         case RTE_ETH_FILTER_SET:
8727                 ret = i40e_hash_filter_set(hw,
8728                         (struct rte_eth_hash_filter_info *)arg);
8729                 break;
8730         default:
8731                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8732                                                                 filter_op);
8733                 ret = -ENOTSUP;
8734                 break;
8735         }
8736
8737         return ret;
8738 }
8739
8740 /* Convert ethertype filter structure */
8741 static int
8742 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8743                               struct i40e_ethertype_filter *filter)
8744 {
8745         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8746         filter->input.ether_type = input->ether_type;
8747         filter->flags = input->flags;
8748         filter->queue = input->queue;
8749
8750         return 0;
8751 }
8752
8753 /* Check if there exists the ehtertype filter */
8754 struct i40e_ethertype_filter *
8755 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8756                                 const struct i40e_ethertype_filter_input *input)
8757 {
8758         int ret;
8759
8760         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8761         if (ret < 0)
8762                 return NULL;
8763
8764         return ethertype_rule->hash_map[ret];
8765 }
8766
8767 /* Add ethertype filter in SW list */
8768 static int
8769 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8770                                 struct i40e_ethertype_filter *filter)
8771 {
8772         struct i40e_ethertype_rule *rule = &pf->ethertype;
8773         int ret;
8774
8775         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8776         if (ret < 0) {
8777                 PMD_DRV_LOG(ERR,
8778                             "Failed to insert ethertype filter"
8779                             " to hash table %d!",
8780                             ret);
8781                 return ret;
8782         }
8783         rule->hash_map[ret] = filter;
8784
8785         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8786
8787         return 0;
8788 }
8789
8790 /* Delete ethertype filter in SW list */
8791 int
8792 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8793                              struct i40e_ethertype_filter_input *input)
8794 {
8795         struct i40e_ethertype_rule *rule = &pf->ethertype;
8796         struct i40e_ethertype_filter *filter;
8797         int ret;
8798
8799         ret = rte_hash_del_key(rule->hash_table, input);
8800         if (ret < 0) {
8801                 PMD_DRV_LOG(ERR,
8802                             "Failed to delete ethertype filter"
8803                             " to hash table %d!",
8804                             ret);
8805                 return ret;
8806         }
8807         filter = rule->hash_map[ret];
8808         rule->hash_map[ret] = NULL;
8809
8810         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8811         rte_free(filter);
8812
8813         return 0;
8814 }
8815
8816 /*
8817  * Configure ethertype filter, which can director packet by filtering
8818  * with mac address and ether_type or only ether_type
8819  */
8820 int
8821 i40e_ethertype_filter_set(struct i40e_pf *pf,
8822                         struct rte_eth_ethertype_filter *filter,
8823                         bool add)
8824 {
8825         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8826         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8827         struct i40e_ethertype_filter *ethertype_filter, *node;
8828         struct i40e_ethertype_filter check_filter;
8829         struct i40e_control_filter_stats stats;
8830         uint16_t flags = 0;
8831         int ret;
8832
8833         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8834                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8835                 return -EINVAL;
8836         }
8837         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8838                 filter->ether_type == ETHER_TYPE_IPv6) {
8839                 PMD_DRV_LOG(ERR,
8840                         "unsupported ether_type(0x%04x) in control packet filter.",
8841                         filter->ether_type);
8842                 return -EINVAL;
8843         }
8844         if (filter->ether_type == ETHER_TYPE_VLAN)
8845                 PMD_DRV_LOG(WARNING,
8846                         "filter vlan ether_type in first tag is not supported.");
8847
8848         /* Check if there is the filter in SW list */
8849         memset(&check_filter, 0, sizeof(check_filter));
8850         i40e_ethertype_filter_convert(filter, &check_filter);
8851         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8852                                                &check_filter.input);
8853         if (add && node) {
8854                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8855                 return -EINVAL;
8856         }
8857
8858         if (!add && !node) {
8859                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8860                 return -EINVAL;
8861         }
8862
8863         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8864                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8865         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8866                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8867         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8868
8869         memset(&stats, 0, sizeof(stats));
8870         ret = i40e_aq_add_rem_control_packet_filter(hw,
8871                         filter->mac_addr.addr_bytes,
8872                         filter->ether_type, flags,
8873                         pf->main_vsi->seid,
8874                         filter->queue, add, &stats, NULL);
8875
8876         PMD_DRV_LOG(INFO,
8877                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8878                 ret, stats.mac_etype_used, stats.etype_used,
8879                 stats.mac_etype_free, stats.etype_free);
8880         if (ret < 0)
8881                 return -ENOSYS;
8882
8883         /* Add or delete a filter in SW list */
8884         if (add) {
8885                 ethertype_filter = rte_zmalloc("ethertype_filter",
8886                                        sizeof(*ethertype_filter), 0);
8887                 rte_memcpy(ethertype_filter, &check_filter,
8888                            sizeof(check_filter));
8889                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8890         } else {
8891                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8892         }
8893
8894         return ret;
8895 }
8896
8897 /*
8898  * Handle operations for ethertype filter.
8899  */
8900 static int
8901 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8902                                 enum rte_filter_op filter_op,
8903                                 void *arg)
8904 {
8905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8906         int ret = 0;
8907
8908         if (filter_op == RTE_ETH_FILTER_NOP)
8909                 return ret;
8910
8911         if (arg == NULL) {
8912                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8913                             filter_op);
8914                 return -EINVAL;
8915         }
8916
8917         switch (filter_op) {
8918         case RTE_ETH_FILTER_ADD:
8919                 ret = i40e_ethertype_filter_set(pf,
8920                         (struct rte_eth_ethertype_filter *)arg,
8921                         TRUE);
8922                 break;
8923         case RTE_ETH_FILTER_DELETE:
8924                 ret = i40e_ethertype_filter_set(pf,
8925                         (struct rte_eth_ethertype_filter *)arg,
8926                         FALSE);
8927                 break;
8928         default:
8929                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8930                 ret = -ENOSYS;
8931                 break;
8932         }
8933         return ret;
8934 }
8935
8936 static int
8937 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8938                      enum rte_filter_type filter_type,
8939                      enum rte_filter_op filter_op,
8940                      void *arg)
8941 {
8942         int ret = 0;
8943
8944         if (dev == NULL)
8945                 return -EINVAL;
8946
8947         switch (filter_type) {
8948         case RTE_ETH_FILTER_NONE:
8949                 /* For global configuration */
8950                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8951                 break;
8952         case RTE_ETH_FILTER_HASH:
8953                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8954                 break;
8955         case RTE_ETH_FILTER_MACVLAN:
8956                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8957                 break;
8958         case RTE_ETH_FILTER_ETHERTYPE:
8959                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8960                 break;
8961         case RTE_ETH_FILTER_TUNNEL:
8962                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8963                 break;
8964         case RTE_ETH_FILTER_FDIR:
8965                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8966                 break;
8967         case RTE_ETH_FILTER_GENERIC:
8968                 if (filter_op != RTE_ETH_FILTER_GET)
8969                         return -EINVAL;
8970                 *(const void **)arg = &i40e_flow_ops;
8971                 break;
8972         default:
8973                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8974                                                         filter_type);
8975                 ret = -EINVAL;
8976                 break;
8977         }
8978
8979         return ret;
8980 }
8981
8982 /*
8983  * Check and enable Extended Tag.
8984  * Enabling Extended Tag is important for 40G performance.
8985  */
8986 static void
8987 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8988 {
8989         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8990         uint32_t buf = 0;
8991         int ret;
8992
8993         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8994                                       PCI_DEV_CAP_REG);
8995         if (ret < 0) {
8996                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8997                             PCI_DEV_CAP_REG);
8998                 return;
8999         }
9000         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9001                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9002                 return;
9003         }
9004
9005         buf = 0;
9006         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
9007                                       PCI_DEV_CTRL_REG);
9008         if (ret < 0) {
9009                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9010                             PCI_DEV_CTRL_REG);
9011                 return;
9012         }
9013         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9014                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9015                 return;
9016         }
9017         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9018         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
9019                                        PCI_DEV_CTRL_REG);
9020         if (ret < 0) {
9021                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9022                             PCI_DEV_CTRL_REG);
9023                 return;
9024         }
9025 }
9026
9027 /*
9028  * As some registers wouldn't be reset unless a global hardware reset,
9029  * hardware initialization is needed to put those registers into an
9030  * expected initial state.
9031  */
9032 static void
9033 i40e_hw_init(struct rte_eth_dev *dev)
9034 {
9035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9036
9037         i40e_enable_extended_tag(dev);
9038
9039         /* clear the PF Queue Filter control register */
9040         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9041
9042         /* Disable symmetric hash per port */
9043         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9044 }
9045
9046 enum i40e_filter_pctype
9047 i40e_flowtype_to_pctype(uint16_t flow_type)
9048 {
9049         static const enum i40e_filter_pctype pctype_table[] = {
9050                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9051                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9052                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9053                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9054                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9055                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9056                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9057                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9058                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9059                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9060                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9061                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9062                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9063                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9064                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9065                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9066                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9067                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9068                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9069         };
9070
9071         return pctype_table[flow_type];
9072 }
9073
9074 uint16_t
9075 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9076 {
9077         static const uint16_t flowtype_table[] = {
9078                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9079                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9080                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9081                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9082                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9083                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9084                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9085                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9086                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9087                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9088                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9089                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9090                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9092                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9093                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9094                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9095                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9096                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9097                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9098                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9099                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9100                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9101                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9102                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9103                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9104                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9105                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9107                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9108                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9109         };
9110
9111         return flowtype_table[pctype];
9112 }
9113
9114 /*
9115  * On X710, performance number is far from the expectation on recent firmware
9116  * versions; on XL710, performance number is also far from the expectation on
9117  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9118  * mode is enabled and port MAC address is equal to the packet destination MAC
9119  * address. The fix for this issue may not be integrated in the following
9120  * firmware version. So the workaround in software driver is needed. It needs
9121  * to modify the initial values of 3 internal only registers for both X710 and
9122  * XL710. Note that the values for X710 or XL710 could be different, and the
9123  * workaround can be removed when it is fixed in firmware in the future.
9124  */
9125
9126 /* For both X710 and XL710 */
9127 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9128 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9129
9130 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9131 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9132
9133 /* For X722 */
9134 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9135 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9136
9137 /* For X710 */
9138 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9139 /* For XL710 */
9140 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9141 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9142
9143 static int
9144 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9145 {
9146         enum i40e_status_code status;
9147         struct i40e_aq_get_phy_abilities_resp phy_ab;
9148         int ret = -ENOTSUP;
9149
9150         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9151                                               NULL);
9152
9153         if (status)
9154                 return ret;
9155
9156         return 0;
9157 }
9158
9159 static void
9160 i40e_configure_registers(struct i40e_hw *hw)
9161 {
9162         static struct {
9163                 uint32_t addr;
9164                 uint64_t val;
9165         } reg_table[] = {
9166                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9167                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9168                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9169         };
9170         uint64_t reg;
9171         uint32_t i;
9172         int ret;
9173
9174         for (i = 0; i < RTE_DIM(reg_table); i++) {
9175                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9176                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9177                                 reg_table[i].val =
9178                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9179                         else /* For X710/XL710/XXV710 */
9180                                 reg_table[i].val =
9181                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9182                 }
9183
9184                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9185                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9186                                 reg_table[i].val =
9187                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9188                         else /* For X710/XL710/XXV710 */
9189                                 reg_table[i].val =
9190                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9191                 }
9192
9193                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9194                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9195                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9196                                 reg_table[i].val =
9197                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9198                         else /* For X710 */
9199                                 reg_table[i].val =
9200                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9201                 }
9202
9203                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9204                                                         &reg, NULL);
9205                 if (ret < 0) {
9206                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9207                                                         reg_table[i].addr);
9208                         break;
9209                 }
9210                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9211                                                 reg_table[i].addr, reg);
9212                 if (reg == reg_table[i].val)
9213                         continue;
9214
9215                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9216                                                 reg_table[i].val, NULL);
9217                 if (ret < 0) {
9218                         PMD_DRV_LOG(ERR,
9219                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9220                                 reg_table[i].val, reg_table[i].addr);
9221                         break;
9222                 }
9223                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9224                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9225         }
9226 }
9227
9228 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9229 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9230 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9231 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9232 static int
9233 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9234 {
9235         uint32_t reg;
9236         int ret;
9237
9238         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9239                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9240                 return -EINVAL;
9241         }
9242
9243         /* Configure for double VLAN RX stripping */
9244         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9245         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9246                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9247                 ret = i40e_aq_debug_write_register(hw,
9248                                                    I40E_VSI_TSR(vsi->vsi_id),
9249                                                    reg, NULL);
9250                 if (ret < 0) {
9251                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9252                                     vsi->vsi_id);
9253                         return I40E_ERR_CONFIG;
9254                 }
9255         }
9256
9257         /* Configure for double VLAN TX insertion */
9258         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9259         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9260                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9261                 ret = i40e_aq_debug_write_register(hw,
9262                                                    I40E_VSI_L2TAGSTXVALID(
9263                                                    vsi->vsi_id), reg, NULL);
9264                 if (ret < 0) {
9265                         PMD_DRV_LOG(ERR,
9266                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9267                                 vsi->vsi_id);
9268                         return I40E_ERR_CONFIG;
9269                 }
9270         }
9271
9272         return 0;
9273 }
9274
9275 /**
9276  * i40e_aq_add_mirror_rule
9277  * @hw: pointer to the hardware structure
9278  * @seid: VEB seid to add mirror rule to
9279  * @dst_id: destination vsi seid
9280  * @entries: Buffer which contains the entities to be mirrored
9281  * @count: number of entities contained in the buffer
9282  * @rule_id:the rule_id of the rule to be added
9283  *
9284  * Add a mirror rule for a given veb.
9285  *
9286  **/
9287 static enum i40e_status_code
9288 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9289                         uint16_t seid, uint16_t dst_id,
9290                         uint16_t rule_type, uint16_t *entries,
9291                         uint16_t count, uint16_t *rule_id)
9292 {
9293         struct i40e_aq_desc desc;
9294         struct i40e_aqc_add_delete_mirror_rule cmd;
9295         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9296                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9297                 &desc.params.raw;
9298         uint16_t buff_len;
9299         enum i40e_status_code status;
9300
9301         i40e_fill_default_direct_cmd_desc(&desc,
9302                                           i40e_aqc_opc_add_mirror_rule);
9303         memset(&cmd, 0, sizeof(cmd));
9304
9305         buff_len = sizeof(uint16_t) * count;
9306         desc.datalen = rte_cpu_to_le_16(buff_len);
9307         if (buff_len > 0)
9308                 desc.flags |= rte_cpu_to_le_16(
9309                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9310         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9311                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9312         cmd.num_entries = rte_cpu_to_le_16(count);
9313         cmd.seid = rte_cpu_to_le_16(seid);
9314         cmd.destination = rte_cpu_to_le_16(dst_id);
9315
9316         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9317         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9318         PMD_DRV_LOG(INFO,
9319                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9320                 hw->aq.asq_last_status, resp->rule_id,
9321                 resp->mirror_rules_used, resp->mirror_rules_free);
9322         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9323
9324         return status;
9325 }
9326
9327 /**
9328  * i40e_aq_del_mirror_rule
9329  * @hw: pointer to the hardware structure
9330  * @seid: VEB seid to add mirror rule to
9331  * @entries: Buffer which contains the entities to be mirrored
9332  * @count: number of entities contained in the buffer
9333  * @rule_id:the rule_id of the rule to be delete
9334  *
9335  * Delete a mirror rule for a given veb.
9336  *
9337  **/
9338 static enum i40e_status_code
9339 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9340                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9341                 uint16_t count, uint16_t rule_id)
9342 {
9343         struct i40e_aq_desc desc;
9344         struct i40e_aqc_add_delete_mirror_rule cmd;
9345         uint16_t buff_len = 0;
9346         enum i40e_status_code status;
9347         void *buff = NULL;
9348
9349         i40e_fill_default_direct_cmd_desc(&desc,
9350                                           i40e_aqc_opc_delete_mirror_rule);
9351         memset(&cmd, 0, sizeof(cmd));
9352         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9353                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9354                                                           I40E_AQ_FLAG_RD));
9355                 cmd.num_entries = count;
9356                 buff_len = sizeof(uint16_t) * count;
9357                 desc.datalen = rte_cpu_to_le_16(buff_len);
9358                 buff = (void *)entries;
9359         } else
9360                 /* rule id is filled in destination field for deleting mirror rule */
9361                 cmd.destination = rte_cpu_to_le_16(rule_id);
9362
9363         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9364                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9365         cmd.seid = rte_cpu_to_le_16(seid);
9366
9367         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9368         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9369
9370         return status;
9371 }
9372
9373 /**
9374  * i40e_mirror_rule_set
9375  * @dev: pointer to the hardware structure
9376  * @mirror_conf: mirror rule info
9377  * @sw_id: mirror rule's sw_id
9378  * @on: enable/disable
9379  *
9380  * set a mirror rule.
9381  *
9382  **/
9383 static int
9384 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9385                         struct rte_eth_mirror_conf *mirror_conf,
9386                         uint8_t sw_id, uint8_t on)
9387 {
9388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9390         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9391         struct i40e_mirror_rule *parent = NULL;
9392         uint16_t seid, dst_seid, rule_id;
9393         uint16_t i, j = 0;
9394         int ret;
9395
9396         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9397
9398         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9399                 PMD_DRV_LOG(ERR,
9400                         "mirror rule can not be configured without veb or vfs.");
9401                 return -ENOSYS;
9402         }
9403         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9404                 PMD_DRV_LOG(ERR, "mirror table is full.");
9405                 return -ENOSPC;
9406         }
9407         if (mirror_conf->dst_pool > pf->vf_num) {
9408                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9409                                  mirror_conf->dst_pool);
9410                 return -EINVAL;
9411         }
9412
9413         seid = pf->main_vsi->veb->seid;
9414
9415         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9416                 if (sw_id <= it->index) {
9417                         mirr_rule = it;
9418                         break;
9419                 }
9420                 parent = it;
9421         }
9422         if (mirr_rule && sw_id == mirr_rule->index) {
9423                 if (on) {
9424                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9425                         return -EEXIST;
9426                 } else {
9427                         ret = i40e_aq_del_mirror_rule(hw, seid,
9428                                         mirr_rule->rule_type,
9429                                         mirr_rule->entries,
9430                                         mirr_rule->num_entries, mirr_rule->id);
9431                         if (ret < 0) {
9432                                 PMD_DRV_LOG(ERR,
9433                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9434                                         ret, hw->aq.asq_last_status);
9435                                 return -ENOSYS;
9436                         }
9437                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9438                         rte_free(mirr_rule);
9439                         pf->nb_mirror_rule--;
9440                         return 0;
9441                 }
9442         } else if (!on) {
9443                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9444                 return -ENOENT;
9445         }
9446
9447         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9448                                 sizeof(struct i40e_mirror_rule) , 0);
9449         if (!mirr_rule) {
9450                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9451                 return I40E_ERR_NO_MEMORY;
9452         }
9453         switch (mirror_conf->rule_type) {
9454         case ETH_MIRROR_VLAN:
9455                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9456                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9457                                 mirr_rule->entries[j] =
9458                                         mirror_conf->vlan.vlan_id[i];
9459                                 j++;
9460                         }
9461                 }
9462                 if (j == 0) {
9463                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9464                         rte_free(mirr_rule);
9465                         return -EINVAL;
9466                 }
9467                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9468                 break;
9469         case ETH_MIRROR_VIRTUAL_POOL_UP:
9470         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9471                 /* check if the specified pool bit is out of range */
9472                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9473                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9474                         rte_free(mirr_rule);
9475                         return -EINVAL;
9476                 }
9477                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9478                         if (mirror_conf->pool_mask & (1ULL << i)) {
9479                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9480                                 j++;
9481                         }
9482                 }
9483                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9484                         /* add pf vsi to entries */
9485                         mirr_rule->entries[j] = pf->main_vsi_seid;
9486                         j++;
9487                 }
9488                 if (j == 0) {
9489                         PMD_DRV_LOG(ERR, "pool is not specified.");
9490                         rte_free(mirr_rule);
9491                         return -EINVAL;
9492                 }
9493                 /* egress and ingress in aq commands means from switch but not port */
9494                 mirr_rule->rule_type =
9495                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9496                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9497                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9498                 break;
9499         case ETH_MIRROR_UPLINK_PORT:
9500                 /* egress and ingress in aq commands means from switch but not port*/
9501                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9502                 break;
9503         case ETH_MIRROR_DOWNLINK_PORT:
9504                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9505                 break;
9506         default:
9507                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9508                         mirror_conf->rule_type);
9509                 rte_free(mirr_rule);
9510                 return -EINVAL;
9511         }
9512
9513         /* If the dst_pool is equal to vf_num, consider it as PF */
9514         if (mirror_conf->dst_pool == pf->vf_num)
9515                 dst_seid = pf->main_vsi_seid;
9516         else
9517                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9518
9519         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9520                                       mirr_rule->rule_type, mirr_rule->entries,
9521                                       j, &rule_id);
9522         if (ret < 0) {
9523                 PMD_DRV_LOG(ERR,
9524                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9525                         ret, hw->aq.asq_last_status);
9526                 rte_free(mirr_rule);
9527                 return -ENOSYS;
9528         }
9529
9530         mirr_rule->index = sw_id;
9531         mirr_rule->num_entries = j;
9532         mirr_rule->id = rule_id;
9533         mirr_rule->dst_vsi_seid = dst_seid;
9534
9535         if (parent)
9536                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9537         else
9538                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9539
9540         pf->nb_mirror_rule++;
9541         return 0;
9542 }
9543
9544 /**
9545  * i40e_mirror_rule_reset
9546  * @dev: pointer to the device
9547  * @sw_id: mirror rule's sw_id
9548  *
9549  * reset a mirror rule.
9550  *
9551  **/
9552 static int
9553 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9554 {
9555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9557         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9558         uint16_t seid;
9559         int ret;
9560
9561         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9562
9563         seid = pf->main_vsi->veb->seid;
9564
9565         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9566                 if (sw_id == it->index) {
9567                         mirr_rule = it;
9568                         break;
9569                 }
9570         }
9571         if (mirr_rule) {
9572                 ret = i40e_aq_del_mirror_rule(hw, seid,
9573                                 mirr_rule->rule_type,
9574                                 mirr_rule->entries,
9575                                 mirr_rule->num_entries, mirr_rule->id);
9576                 if (ret < 0) {
9577                         PMD_DRV_LOG(ERR,
9578                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9579                                 ret, hw->aq.asq_last_status);
9580                         return -ENOSYS;
9581                 }
9582                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9583                 rte_free(mirr_rule);
9584                 pf->nb_mirror_rule--;
9585         } else {
9586                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9587                 return -ENOENT;
9588         }
9589         return 0;
9590 }
9591
9592 static uint64_t
9593 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9594 {
9595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9596         uint64_t systim_cycles;
9597
9598         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9599         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9600                         << 32;
9601
9602         return systim_cycles;
9603 }
9604
9605 static uint64_t
9606 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9607 {
9608         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9609         uint64_t rx_tstamp;
9610
9611         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9612         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9613                         << 32;
9614
9615         return rx_tstamp;
9616 }
9617
9618 static uint64_t
9619 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9620 {
9621         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9622         uint64_t tx_tstamp;
9623
9624         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9625         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9626                         << 32;
9627
9628         return tx_tstamp;
9629 }
9630
9631 static void
9632 i40e_start_timecounters(struct rte_eth_dev *dev)
9633 {
9634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9635         struct i40e_adapter *adapter =
9636                         (struct i40e_adapter *)dev->data->dev_private;
9637         struct rte_eth_link link;
9638         uint32_t tsync_inc_l;
9639         uint32_t tsync_inc_h;
9640
9641         /* Get current link speed. */
9642         memset(&link, 0, sizeof(link));
9643         i40e_dev_link_update(dev, 1);
9644         rte_i40e_dev_atomic_read_link_status(dev, &link);
9645
9646         switch (link.link_speed) {
9647         case ETH_SPEED_NUM_40G:
9648                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9649                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9650                 break;
9651         case ETH_SPEED_NUM_10G:
9652                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9653                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9654                 break;
9655         case ETH_SPEED_NUM_1G:
9656                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9657                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9658                 break;
9659         default:
9660                 tsync_inc_l = 0x0;
9661                 tsync_inc_h = 0x0;
9662         }
9663
9664         /* Set the timesync increment value. */
9665         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9666         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9667
9668         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9669         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9670         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9671
9672         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9673         adapter->systime_tc.cc_shift = 0;
9674         adapter->systime_tc.nsec_mask = 0;
9675
9676         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9677         adapter->rx_tstamp_tc.cc_shift = 0;
9678         adapter->rx_tstamp_tc.nsec_mask = 0;
9679
9680         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9681         adapter->tx_tstamp_tc.cc_shift = 0;
9682         adapter->tx_tstamp_tc.nsec_mask = 0;
9683 }
9684
9685 static int
9686 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9687 {
9688         struct i40e_adapter *adapter =
9689                         (struct i40e_adapter *)dev->data->dev_private;
9690
9691         adapter->systime_tc.nsec += delta;
9692         adapter->rx_tstamp_tc.nsec += delta;
9693         adapter->tx_tstamp_tc.nsec += delta;
9694
9695         return 0;
9696 }
9697
9698 static int
9699 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9700 {
9701         uint64_t ns;
9702         struct i40e_adapter *adapter =
9703                         (struct i40e_adapter *)dev->data->dev_private;
9704
9705         ns = rte_timespec_to_ns(ts);
9706
9707         /* Set the timecounters to a new value. */
9708         adapter->systime_tc.nsec = ns;
9709         adapter->rx_tstamp_tc.nsec = ns;
9710         adapter->tx_tstamp_tc.nsec = ns;
9711
9712         return 0;
9713 }
9714
9715 static int
9716 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9717 {
9718         uint64_t ns, systime_cycles;
9719         struct i40e_adapter *adapter =
9720                         (struct i40e_adapter *)dev->data->dev_private;
9721
9722         systime_cycles = i40e_read_systime_cyclecounter(dev);
9723         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9724         *ts = rte_ns_to_timespec(ns);
9725
9726         return 0;
9727 }
9728
9729 static int
9730 i40e_timesync_enable(struct rte_eth_dev *dev)
9731 {
9732         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9733         uint32_t tsync_ctl_l;
9734         uint32_t tsync_ctl_h;
9735
9736         /* Stop the timesync system time. */
9737         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9738         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9739         /* Reset the timesync system time value. */
9740         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9741         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9742
9743         i40e_start_timecounters(dev);
9744
9745         /* Clear timesync registers. */
9746         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9747         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9748         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9749         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9750         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9751         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9752
9753         /* Enable timestamping of PTP packets. */
9754         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9755         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9756
9757         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9758         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9759         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9760
9761         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9762         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9763
9764         return 0;
9765 }
9766
9767 static int
9768 i40e_timesync_disable(struct rte_eth_dev *dev)
9769 {
9770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9771         uint32_t tsync_ctl_l;
9772         uint32_t tsync_ctl_h;
9773
9774         /* Disable timestamping of transmitted PTP packets. */
9775         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9776         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9777
9778         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9779         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9780
9781         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9782         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9783
9784         /* Reset the timesync increment value. */
9785         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9786         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9787
9788         return 0;
9789 }
9790
9791 static int
9792 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9793                                 struct timespec *timestamp, uint32_t flags)
9794 {
9795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9796         struct i40e_adapter *adapter =
9797                 (struct i40e_adapter *)dev->data->dev_private;
9798
9799         uint32_t sync_status;
9800         uint32_t index = flags & 0x03;
9801         uint64_t rx_tstamp_cycles;
9802         uint64_t ns;
9803
9804         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9805         if ((sync_status & (1 << index)) == 0)
9806                 return -EINVAL;
9807
9808         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9809         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9810         *timestamp = rte_ns_to_timespec(ns);
9811
9812         return 0;
9813 }
9814
9815 static int
9816 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9817                                 struct timespec *timestamp)
9818 {
9819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9820         struct i40e_adapter *adapter =
9821                 (struct i40e_adapter *)dev->data->dev_private;
9822
9823         uint32_t sync_status;
9824         uint64_t tx_tstamp_cycles;
9825         uint64_t ns;
9826
9827         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9828         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9829                 return -EINVAL;
9830
9831         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9832         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9833         *timestamp = rte_ns_to_timespec(ns);
9834
9835         return 0;
9836 }
9837
9838 /*
9839  * i40e_parse_dcb_configure - parse dcb configure from user
9840  * @dev: the device being configured
9841  * @dcb_cfg: pointer of the result of parse
9842  * @*tc_map: bit map of enabled traffic classes
9843  *
9844  * Returns 0 on success, negative value on failure
9845  */
9846 static int
9847 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9848                          struct i40e_dcbx_config *dcb_cfg,
9849                          uint8_t *tc_map)
9850 {
9851         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9852         uint8_t i, tc_bw, bw_lf;
9853
9854         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9855
9856         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9857         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9858                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9859                 return -EINVAL;
9860         }
9861
9862         /* assume each tc has the same bw */
9863         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9864         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9865                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9866         /* to ensure the sum of tcbw is equal to 100 */
9867         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9868         for (i = 0; i < bw_lf; i++)
9869                 dcb_cfg->etscfg.tcbwtable[i]++;
9870
9871         /* assume each tc has the same Transmission Selection Algorithm */
9872         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9873                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9874
9875         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9876                 dcb_cfg->etscfg.prioritytable[i] =
9877                                 dcb_rx_conf->dcb_tc[i];
9878
9879         /* FW needs one App to configure HW */
9880         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9881         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9882         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9883         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9884
9885         if (dcb_rx_conf->nb_tcs == 0)
9886                 *tc_map = 1; /* tc0 only */
9887         else
9888                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9889
9890         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9891                 dcb_cfg->pfc.willing = 0;
9892                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9893                 dcb_cfg->pfc.pfcenable = *tc_map;
9894         }
9895         return 0;
9896 }
9897
9898
9899 static enum i40e_status_code
9900 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9901                               struct i40e_aqc_vsi_properties_data *info,
9902                               uint8_t enabled_tcmap)
9903 {
9904         enum i40e_status_code ret;
9905         int i, total_tc = 0;
9906         uint16_t qpnum_per_tc, bsf, qp_idx;
9907         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9908         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9909         uint16_t used_queues;
9910
9911         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9912         if (ret != I40E_SUCCESS)
9913                 return ret;
9914
9915         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9916                 if (enabled_tcmap & (1 << i))
9917                         total_tc++;
9918         }
9919         if (total_tc == 0)
9920                 total_tc = 1;
9921         vsi->enabled_tc = enabled_tcmap;
9922
9923         /* different VSI has different queues assigned */
9924         if (vsi->type == I40E_VSI_MAIN)
9925                 used_queues = dev_data->nb_rx_queues -
9926                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9927         else if (vsi->type == I40E_VSI_VMDQ2)
9928                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9929         else {
9930                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9931                 return I40E_ERR_NO_AVAILABLE_VSI;
9932         }
9933
9934         qpnum_per_tc = used_queues / total_tc;
9935         /* Number of queues per enabled TC */
9936         if (qpnum_per_tc == 0) {
9937                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9938                 return I40E_ERR_INVALID_QP_ID;
9939         }
9940         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9941                                 I40E_MAX_Q_PER_TC);
9942         bsf = rte_bsf32(qpnum_per_tc);
9943
9944         /**
9945          * Configure TC and queue mapping parameters, for enabled TC,
9946          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9947          * default queue will serve it.
9948          */
9949         qp_idx = 0;
9950         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9951                 if (vsi->enabled_tc & (1 << i)) {
9952                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9953                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9954                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9955                         qp_idx += qpnum_per_tc;
9956                 } else
9957                         info->tc_mapping[i] = 0;
9958         }
9959
9960         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9961         if (vsi->type == I40E_VSI_SRIOV) {
9962                 info->mapping_flags |=
9963                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9964                 for (i = 0; i < vsi->nb_qps; i++)
9965                         info->queue_mapping[i] =
9966                                 rte_cpu_to_le_16(vsi->base_queue + i);
9967         } else {
9968                 info->mapping_flags |=
9969                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9970                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9971         }
9972         info->valid_sections |=
9973                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9974
9975         return I40E_SUCCESS;
9976 }
9977
9978 /*
9979  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9980  * @veb: VEB to be configured
9981  * @tc_map: enabled TC bitmap
9982  *
9983  * Returns 0 on success, negative value on failure
9984  */
9985 static enum i40e_status_code
9986 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9987 {
9988         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9989         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9990         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9991         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9992         enum i40e_status_code ret = I40E_SUCCESS;
9993         int i;
9994         uint32_t bw_max;
9995
9996         /* Check if enabled_tc is same as existing or new TCs */
9997         if (veb->enabled_tc == tc_map)
9998                 return ret;
9999
10000         /* configure tc bandwidth */
10001         memset(&veb_bw, 0, sizeof(veb_bw));
10002         veb_bw.tc_valid_bits = tc_map;
10003         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10004         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10005                 if (tc_map & BIT_ULL(i))
10006                         veb_bw.tc_bw_share_credits[i] = 1;
10007         }
10008         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10009                                                    &veb_bw, NULL);
10010         if (ret) {
10011                 PMD_INIT_LOG(ERR,
10012                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10013                         hw->aq.asq_last_status);
10014                 return ret;
10015         }
10016
10017         memset(&ets_query, 0, sizeof(ets_query));
10018         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10019                                                    &ets_query, NULL);
10020         if (ret != I40E_SUCCESS) {
10021                 PMD_DRV_LOG(ERR,
10022                         "Failed to get switch_comp ETS configuration %u",
10023                         hw->aq.asq_last_status);
10024                 return ret;
10025         }
10026         memset(&bw_query, 0, sizeof(bw_query));
10027         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10028                                                   &bw_query, NULL);
10029         if (ret != I40E_SUCCESS) {
10030                 PMD_DRV_LOG(ERR,
10031                         "Failed to get switch_comp bandwidth configuration %u",
10032                         hw->aq.asq_last_status);
10033                 return ret;
10034         }
10035
10036         /* store and print out BW info */
10037         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10038         veb->bw_info.bw_max = ets_query.tc_bw_max;
10039         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10040         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10041         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10042                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10043                      I40E_16_BIT_WIDTH);
10044         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10045                 veb->bw_info.bw_ets_share_credits[i] =
10046                                 bw_query.tc_bw_share_credits[i];
10047                 veb->bw_info.bw_ets_credits[i] =
10048                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10049                 /* 4 bits per TC, 4th bit is reserved */
10050                 veb->bw_info.bw_ets_max[i] =
10051                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10052                                   RTE_LEN2MASK(3, uint8_t));
10053                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10054                             veb->bw_info.bw_ets_share_credits[i]);
10055                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10056                             veb->bw_info.bw_ets_credits[i]);
10057                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10058                             veb->bw_info.bw_ets_max[i]);
10059         }
10060
10061         veb->enabled_tc = tc_map;
10062
10063         return ret;
10064 }
10065
10066
10067 /*
10068  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10069  * @vsi: VSI to be configured
10070  * @tc_map: enabled TC bitmap
10071  *
10072  * Returns 0 on success, negative value on failure
10073  */
10074 static enum i40e_status_code
10075 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10076 {
10077         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10078         struct i40e_vsi_context ctxt;
10079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10080         enum i40e_status_code ret = I40E_SUCCESS;
10081         int i;
10082
10083         /* Check if enabled_tc is same as existing or new TCs */
10084         if (vsi->enabled_tc == tc_map)
10085                 return ret;
10086
10087         /* configure tc bandwidth */
10088         memset(&bw_data, 0, sizeof(bw_data));
10089         bw_data.tc_valid_bits = tc_map;
10090         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10091         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10092                 if (tc_map & BIT_ULL(i))
10093                         bw_data.tc_bw_credits[i] = 1;
10094         }
10095         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10096         if (ret) {
10097                 PMD_INIT_LOG(ERR,
10098                         "AQ command Config VSI BW allocation per TC failed = %d",
10099                         hw->aq.asq_last_status);
10100                 goto out;
10101         }
10102         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10103                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10104
10105         /* Update Queue Pairs Mapping for currently enabled UPs */
10106         ctxt.seid = vsi->seid;
10107         ctxt.pf_num = hw->pf_id;
10108         ctxt.vf_num = 0;
10109         ctxt.uplink_seid = vsi->uplink_seid;
10110         ctxt.info = vsi->info;
10111         i40e_get_cap(hw);
10112         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10113         if (ret)
10114                 goto out;
10115
10116         /* Update the VSI after updating the VSI queue-mapping information */
10117         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10118         if (ret) {
10119                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10120                         hw->aq.asq_last_status);
10121                 goto out;
10122         }
10123         /* update the local VSI info with updated queue map */
10124         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10125                                         sizeof(vsi->info.tc_mapping));
10126         (void)rte_memcpy(&vsi->info.queue_mapping,
10127                         &ctxt.info.queue_mapping,
10128                 sizeof(vsi->info.queue_mapping));
10129         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10130         vsi->info.valid_sections = 0;
10131
10132         /* query and update current VSI BW information */
10133         ret = i40e_vsi_get_bw_config(vsi);
10134         if (ret) {
10135                 PMD_INIT_LOG(ERR,
10136                          "Failed updating vsi bw info, err %s aq_err %s",
10137                          i40e_stat_str(hw, ret),
10138                          i40e_aq_str(hw, hw->aq.asq_last_status));
10139                 goto out;
10140         }
10141
10142         vsi->enabled_tc = tc_map;
10143
10144 out:
10145         return ret;
10146 }
10147
10148 /*
10149  * i40e_dcb_hw_configure - program the dcb setting to hw
10150  * @pf: pf the configuration is taken on
10151  * @new_cfg: new configuration
10152  * @tc_map: enabled TC bitmap
10153  *
10154  * Returns 0 on success, negative value on failure
10155  */
10156 static enum i40e_status_code
10157 i40e_dcb_hw_configure(struct i40e_pf *pf,
10158                       struct i40e_dcbx_config *new_cfg,
10159                       uint8_t tc_map)
10160 {
10161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10162         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10163         struct i40e_vsi *main_vsi = pf->main_vsi;
10164         struct i40e_vsi_list *vsi_list;
10165         enum i40e_status_code ret;
10166         int i;
10167         uint32_t val;
10168
10169         /* Use the FW API if FW > v4.4*/
10170         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10171               (hw->aq.fw_maj_ver >= 5))) {
10172                 PMD_INIT_LOG(ERR,
10173                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10174                 return I40E_ERR_FIRMWARE_API_VERSION;
10175         }
10176
10177         /* Check if need reconfiguration */
10178         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10179                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10180                 return I40E_SUCCESS;
10181         }
10182
10183         /* Copy the new config to the current config */
10184         *old_cfg = *new_cfg;
10185         old_cfg->etsrec = old_cfg->etscfg;
10186         ret = i40e_set_dcb_config(hw);
10187         if (ret) {
10188                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10189                          i40e_stat_str(hw, ret),
10190                          i40e_aq_str(hw, hw->aq.asq_last_status));
10191                 return ret;
10192         }
10193         /* set receive Arbiter to RR mode and ETS scheme by default */
10194         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10195                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10196                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10197                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10198                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10199                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10200                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10201                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10202                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10203                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10204                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10205                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10206                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10207         }
10208         /* get local mib to check whether it is configured correctly */
10209         /* IEEE mode */
10210         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10211         /* Get Local DCB Config */
10212         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10213                                      &hw->local_dcbx_config);
10214
10215         /* if Veb is created, need to update TC of it at first */
10216         if (main_vsi->veb) {
10217                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10218                 if (ret)
10219                         PMD_INIT_LOG(WARNING,
10220                                  "Failed configuring TC for VEB seid=%d",
10221                                  main_vsi->veb->seid);
10222         }
10223         /* Update each VSI */
10224         i40e_vsi_config_tc(main_vsi, tc_map);
10225         if (main_vsi->veb) {
10226                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10227                         /* Beside main VSI and VMDQ VSIs, only enable default
10228                          * TC for other VSIs
10229                          */
10230                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10231                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10232                                                          tc_map);
10233                         else
10234                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10235                                                          I40E_DEFAULT_TCMAP);
10236                         if (ret)
10237                                 PMD_INIT_LOG(WARNING,
10238                                         "Failed configuring TC for VSI seid=%d",
10239                                         vsi_list->vsi->seid);
10240                         /* continue */
10241                 }
10242         }
10243         return I40E_SUCCESS;
10244 }
10245
10246 /*
10247  * i40e_dcb_init_configure - initial dcb config
10248  * @dev: device being configured
10249  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10250  *
10251  * Returns 0 on success, negative value on failure
10252  */
10253 static int
10254 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10255 {
10256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10258         int i, ret = 0;
10259
10260         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10261                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10262                 return -ENOTSUP;
10263         }
10264
10265         /* DCB initialization:
10266          * Update DCB configuration from the Firmware and configure
10267          * LLDP MIB change event.
10268          */
10269         if (sw_dcb == TRUE) {
10270                 ret = i40e_init_dcb(hw);
10271                 /* If lldp agent is stopped, the return value from
10272                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10273                  * adminq status. Otherwise, it should return success.
10274                  */
10275                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10276                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10277                         memset(&hw->local_dcbx_config, 0,
10278                                 sizeof(struct i40e_dcbx_config));
10279                         /* set dcb default configuration */
10280                         hw->local_dcbx_config.etscfg.willing = 0;
10281                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10282                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10283                         hw->local_dcbx_config.etscfg.tsatable[0] =
10284                                                 I40E_IEEE_TSA_ETS;
10285                         /* all UPs mapping to TC0 */
10286                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10287                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10288                         hw->local_dcbx_config.etsrec =
10289                                 hw->local_dcbx_config.etscfg;
10290                         hw->local_dcbx_config.pfc.willing = 0;
10291                         hw->local_dcbx_config.pfc.pfccap =
10292                                                 I40E_MAX_TRAFFIC_CLASS;
10293                         /* FW needs one App to configure HW */
10294                         hw->local_dcbx_config.numapps = 1;
10295                         hw->local_dcbx_config.app[0].selector =
10296                                                 I40E_APP_SEL_ETHTYPE;
10297                         hw->local_dcbx_config.app[0].priority = 3;
10298                         hw->local_dcbx_config.app[0].protocolid =
10299                                                 I40E_APP_PROTOID_FCOE;
10300                         ret = i40e_set_dcb_config(hw);
10301                         if (ret) {
10302                                 PMD_INIT_LOG(ERR,
10303                                         "default dcb config fails. err = %d, aq_err = %d.",
10304                                         ret, hw->aq.asq_last_status);
10305                                 return -ENOSYS;
10306                         }
10307                 } else {
10308                         PMD_INIT_LOG(ERR,
10309                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10310                                 ret, hw->aq.asq_last_status);
10311                         return -ENOTSUP;
10312                 }
10313         } else {
10314                 ret = i40e_aq_start_lldp(hw, NULL);
10315                 if (ret != I40E_SUCCESS)
10316                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10317
10318                 ret = i40e_init_dcb(hw);
10319                 if (!ret) {
10320                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10321                                 PMD_INIT_LOG(ERR,
10322                                         "HW doesn't support DCBX offload.");
10323                                 return -ENOTSUP;
10324                         }
10325                 } else {
10326                         PMD_INIT_LOG(ERR,
10327                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10328                                 ret, hw->aq.asq_last_status);
10329                         return -ENOTSUP;
10330                 }
10331         }
10332         return 0;
10333 }
10334
10335 /*
10336  * i40e_dcb_setup - setup dcb related config
10337  * @dev: device being configured
10338  *
10339  * Returns 0 on success, negative value on failure
10340  */
10341 static int
10342 i40e_dcb_setup(struct rte_eth_dev *dev)
10343 {
10344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10345         struct i40e_dcbx_config dcb_cfg;
10346         uint8_t tc_map = 0;
10347         int ret = 0;
10348
10349         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10350                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10351                 return -ENOTSUP;
10352         }
10353
10354         if (pf->vf_num != 0)
10355                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10356
10357         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10358         if (ret) {
10359                 PMD_INIT_LOG(ERR, "invalid dcb config");
10360                 return -EINVAL;
10361         }
10362         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10363         if (ret) {
10364                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10365                 return -ENOSYS;
10366         }
10367
10368         return 0;
10369 }
10370
10371 static int
10372 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10373                       struct rte_eth_dcb_info *dcb_info)
10374 {
10375         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10376         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10377         struct i40e_vsi *vsi = pf->main_vsi;
10378         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10379         uint16_t bsf, tc_mapping;
10380         int i, j = 0;
10381
10382         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10383                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10384         else
10385                 dcb_info->nb_tcs = 1;
10386         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10387                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10388         for (i = 0; i < dcb_info->nb_tcs; i++)
10389                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10390
10391         /* get queue mapping if vmdq is disabled */
10392         if (!pf->nb_cfg_vmdq_vsi) {
10393                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10394                         if (!(vsi->enabled_tc & (1 << i)))
10395                                 continue;
10396                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10397                         dcb_info->tc_queue.tc_rxq[j][i].base =
10398                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10399                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10400                         dcb_info->tc_queue.tc_txq[j][i].base =
10401                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10402                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10403                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10404                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10405                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10406                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10407                 }
10408                 return 0;
10409         }
10410
10411         /* get queue mapping if vmdq is enabled */
10412         do {
10413                 vsi = pf->vmdq[j].vsi;
10414                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10415                         if (!(vsi->enabled_tc & (1 << i)))
10416                                 continue;
10417                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10418                         dcb_info->tc_queue.tc_rxq[j][i].base =
10419                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10420                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10421                         dcb_info->tc_queue.tc_txq[j][i].base =
10422                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10423                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10424                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10425                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10426                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10427                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10428                 }
10429                 j++;
10430         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10431         return 0;
10432 }
10433
10434 static int
10435 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10436 {
10437         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10438         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10440         uint16_t interval =
10441                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10442         uint16_t msix_intr;
10443
10444         msix_intr = intr_handle->intr_vec[queue_id];
10445         if (msix_intr == I40E_MISC_VEC_ID)
10446                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10447                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10448                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10449                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10450                                (interval <<
10451                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10452         else
10453                 I40E_WRITE_REG(hw,
10454                                I40E_PFINT_DYN_CTLN(msix_intr -
10455                                                    I40E_RX_VEC_START),
10456                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10457                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10458                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10459                                (interval <<
10460                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10461
10462         I40E_WRITE_FLUSH(hw);
10463         rte_intr_enable(&pci_dev->intr_handle);
10464
10465         return 0;
10466 }
10467
10468 static int
10469 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10470 {
10471         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10472         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10474         uint16_t msix_intr;
10475
10476         msix_intr = intr_handle->intr_vec[queue_id];
10477         if (msix_intr == I40E_MISC_VEC_ID)
10478                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10479         else
10480                 I40E_WRITE_REG(hw,
10481                                I40E_PFINT_DYN_CTLN(msix_intr -
10482                                                    I40E_RX_VEC_START),
10483                                0);
10484         I40E_WRITE_FLUSH(hw);
10485
10486         return 0;
10487 }
10488
10489 static int i40e_get_regs(struct rte_eth_dev *dev,
10490                          struct rte_dev_reg_info *regs)
10491 {
10492         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10493         uint32_t *ptr_data = regs->data;
10494         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10495         const struct i40e_reg_info *reg_info;
10496
10497         if (ptr_data == NULL) {
10498                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10499                 regs->width = sizeof(uint32_t);
10500                 return 0;
10501         }
10502
10503         /* The first few registers have to be read using AQ operations */
10504         reg_idx = 0;
10505         while (i40e_regs_adminq[reg_idx].name) {
10506                 reg_info = &i40e_regs_adminq[reg_idx++];
10507                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10508                         for (arr_idx2 = 0;
10509                                         arr_idx2 <= reg_info->count2;
10510                                         arr_idx2++) {
10511                                 reg_offset = arr_idx * reg_info->stride1 +
10512                                         arr_idx2 * reg_info->stride2;
10513                                 reg_offset += reg_info->base_addr;
10514                                 ptr_data[reg_offset >> 2] =
10515                                         i40e_read_rx_ctl(hw, reg_offset);
10516                         }
10517         }
10518
10519         /* The remaining registers can be read using primitives */
10520         reg_idx = 0;
10521         while (i40e_regs_others[reg_idx].name) {
10522                 reg_info = &i40e_regs_others[reg_idx++];
10523                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10524                         for (arr_idx2 = 0;
10525                                         arr_idx2 <= reg_info->count2;
10526                                         arr_idx2++) {
10527                                 reg_offset = arr_idx * reg_info->stride1 +
10528                                         arr_idx2 * reg_info->stride2;
10529                                 reg_offset += reg_info->base_addr;
10530                                 ptr_data[reg_offset >> 2] =
10531                                         I40E_READ_REG(hw, reg_offset);
10532                         }
10533         }
10534
10535         return 0;
10536 }
10537
10538 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10539 {
10540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10541
10542         /* Convert word count to byte count */
10543         return hw->nvm.sr_size << 1;
10544 }
10545
10546 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10547                            struct rte_dev_eeprom_info *eeprom)
10548 {
10549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10550         uint16_t *data = eeprom->data;
10551         uint16_t offset, length, cnt_words;
10552         int ret_code;
10553
10554         offset = eeprom->offset >> 1;
10555         length = eeprom->length >> 1;
10556         cnt_words = length;
10557
10558         if (offset > hw->nvm.sr_size ||
10559                 offset + length > hw->nvm.sr_size) {
10560                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10561                 return -EINVAL;
10562         }
10563
10564         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10565
10566         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10567         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10568                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10569                 return -EIO;
10570         }
10571
10572         return 0;
10573 }
10574
10575 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10576                                       struct ether_addr *mac_addr)
10577 {
10578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10579
10580         if (!is_valid_assigned_ether_addr(mac_addr)) {
10581                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10582                 return;
10583         }
10584
10585         /* Flags: 0x3 updates port address */
10586         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10587 }
10588
10589 static int
10590 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10591 {
10592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10593         struct rte_eth_dev_data *dev_data = pf->dev_data;
10594         uint32_t frame_size = mtu + ETHER_HDR_LEN
10595                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10596         int ret = 0;
10597
10598         /* check if mtu is within the allowed range */
10599         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10600                 return -EINVAL;
10601
10602         /* mtu setting is forbidden if port is start */
10603         if (dev_data->dev_started) {
10604                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10605                             dev_data->port_id);
10606                 return -EBUSY;
10607         }
10608
10609         if (frame_size > ETHER_MAX_LEN)
10610                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10611         else
10612                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10613
10614         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10615
10616         return ret;
10617 }
10618
10619 /* Restore ethertype filter */
10620 static void
10621 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10622 {
10623         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10624         struct i40e_ethertype_filter_list
10625                 *ethertype_list = &pf->ethertype.ethertype_list;
10626         struct i40e_ethertype_filter *f;
10627         struct i40e_control_filter_stats stats;
10628         uint16_t flags;
10629
10630         TAILQ_FOREACH(f, ethertype_list, rules) {
10631                 flags = 0;
10632                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10633                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10634                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10635                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10636                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10637
10638                 memset(&stats, 0, sizeof(stats));
10639                 i40e_aq_add_rem_control_packet_filter(hw,
10640                                             f->input.mac_addr.addr_bytes,
10641                                             f->input.ether_type,
10642                                             flags, pf->main_vsi->seid,
10643                                             f->queue, 1, &stats, NULL);
10644         }
10645         PMD_DRV_LOG(INFO, "Ethertype filter:"
10646                     " mac_etype_used = %u, etype_used = %u,"
10647                     " mac_etype_free = %u, etype_free = %u",
10648                     stats.mac_etype_used, stats.etype_used,
10649                     stats.mac_etype_free, stats.etype_free);
10650 }
10651
10652 /* Restore tunnel filter */
10653 static void
10654 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10655 {
10656         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10657         struct i40e_vsi *vsi;
10658         struct i40e_pf_vf *vf;
10659         struct i40e_tunnel_filter_list
10660                 *tunnel_list = &pf->tunnel.tunnel_list;
10661         struct i40e_tunnel_filter *f;
10662         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10663         bool big_buffer = 0;
10664
10665         TAILQ_FOREACH(f, tunnel_list, rules) {
10666                 if (!f->is_to_vf)
10667                         vsi = pf->main_vsi;
10668                 else {
10669                         vf = &pf->vfs[f->vf_id];
10670                         vsi = vf->vsi;
10671                 }
10672                 memset(&cld_filter, 0, sizeof(cld_filter));
10673                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10674                         (struct ether_addr *)&cld_filter.element.outer_mac);
10675                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10676                         (struct ether_addr *)&cld_filter.element.inner_mac);
10677                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10678                 cld_filter.element.flags = f->input.flags;
10679                 cld_filter.element.tenant_id = f->input.tenant_id;
10680                 cld_filter.element.queue_number = f->queue;
10681                 rte_memcpy(cld_filter.general_fields,
10682                            f->input.general_fields,
10683                            sizeof(f->input.general_fields));
10684
10685                 if (((f->input.flags &
10686                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10687                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10688                     ((f->input.flags &
10689                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10690                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10691                     ((f->input.flags &
10692                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10693                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10694                         big_buffer = 1;
10695
10696                 if (big_buffer)
10697                         i40e_aq_add_cloud_filters_big_buffer(hw,
10698                                              vsi->seid, &cld_filter, 1);
10699                 else
10700                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10701                                                   &cld_filter.element, 1);
10702         }
10703 }
10704
10705 static void
10706 i40e_filter_restore(struct i40e_pf *pf)
10707 {
10708         i40e_ethertype_filter_restore(pf);
10709         i40e_tunnel_filter_restore(pf);
10710         i40e_fdir_filter_restore(pf);
10711 }
10712
10713 static bool
10714 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10715 {
10716         if (strcmp(dev->data->drv_name,
10717                    drv->driver.name))
10718                 return false;
10719
10720         return true;
10721 }
10722
10723 bool
10724 is_i40e_supported(struct rte_eth_dev *dev)
10725 {
10726         return is_device_supported(dev, &rte_i40e_pmd);
10727 }
10728
10729 /* Create a QinQ cloud filter
10730  *
10731  * The Fortville NIC has limited resources for tunnel filters,
10732  * so we can only reuse existing filters.
10733  *
10734  * In step 1 we define which Field Vector fields can be used for
10735  * filter types.
10736  * As we do not have the inner tag defined as a field,
10737  * we have to define it first, by reusing one of L1 entries.
10738  *
10739  * In step 2 we are replacing one of existing filter types with
10740  * a new one for QinQ.
10741  * As we reusing L1 and replacing L2, some of the default filter
10742  * types will disappear,which depends on L1 and L2 entries we reuse.
10743  *
10744  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10745  *
10746  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10747  *              later when we define the cloud filter.
10748  *      a.      Valid_flags.replace_cloud = 0
10749  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10750  *      c.      New_filter = 0x10
10751  *      d.      TR bit = 0xff (optional, not used here)
10752  *      e.      Buffer – 2 entries:
10753  *              i.      Byte 0 = 8 (outer vlan FV index).
10754  *                      Byte 1 = 0 (rsv)
10755  *                      Byte 2-3 = 0x0fff
10756  *              ii.     Byte 0 = 37 (inner vlan FV index).
10757  *                      Byte 1 =0 (rsv)
10758  *                      Byte 2-3 = 0x0fff
10759  *
10760  * Step 2:
10761  * 2.   Create cloud filter using two L1 filters entries: stag and
10762  *              new filter(outer vlan+ inner vlan)
10763  *      a.      Valid_flags.replace_cloud = 1
10764  *      b.      Old_filter = 1 (instead of outer IP)
10765  *      c.      New_filter = 0x10
10766  *      d.      Buffer – 2 entries:
10767  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10768  *                      Byte 1-3 = 0 (rsv)
10769  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10770  *                      Byte 9-11 = 0 (rsv)
10771  */
10772 static int
10773 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10774 {
10775         int ret = -ENOTSUP;
10776         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10777         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10779
10780         /* Init */
10781         memset(&filter_replace, 0,
10782                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10783         memset(&filter_replace_buf, 0,
10784                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10785
10786         /* create L1 filter */
10787         filter_replace.old_filter_type =
10788                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10789         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10790         filter_replace.tr_bit = 0;
10791
10792         /* Prepare the buffer, 2 entries */
10793         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10794         filter_replace_buf.data[0] |=
10795                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10796         /* Field Vector 12b mask */
10797         filter_replace_buf.data[2] = 0xff;
10798         filter_replace_buf.data[3] = 0x0f;
10799         filter_replace_buf.data[4] =
10800                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10801         filter_replace_buf.data[4] |=
10802                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10803         /* Field Vector 12b mask */
10804         filter_replace_buf.data[6] = 0xff;
10805         filter_replace_buf.data[7] = 0x0f;
10806         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10807                         &filter_replace_buf);
10808         if (ret != I40E_SUCCESS)
10809                 return ret;
10810
10811         /* Apply the second L2 cloud filter */
10812         memset(&filter_replace, 0,
10813                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10814         memset(&filter_replace_buf, 0,
10815                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10816
10817         /* create L2 filter, input for L2 filter will be L1 filter  */
10818         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10819         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10820         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10821
10822         /* Prepare the buffer, 2 entries */
10823         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10824         filter_replace_buf.data[0] |=
10825                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10826         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10827         filter_replace_buf.data[4] |=
10828                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10829         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10830                         &filter_replace_buf);
10831         return ret;
10832 }
10833
10834 RTE_INIT(i40e_init_log);
10835 static void
10836 i40e_init_log(void)
10837 {
10838         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10839         if (i40e_logtype_init >= 0)
10840                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10841         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10842         if (i40e_logtype_driver >= 0)
10843                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10844 }