drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 293                           struct ether_addr *mac_addr,
 294                           uint32_t index,
 295                           uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 321                                        void *param);
 322 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 323                                 uint32_t base, uint32_t num);
 324 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 325 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 326                         uint32_t base);
 327 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 328                         uint16_t num);
 329 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 330 static int i40e_veb_release(struct i40e_veb *veb);
 331 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 332                                                 struct i40e_vsi *vsi);
 333 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 334 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 335 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 336                                              struct i40e_macvlan_filter *mv_f,
 337                                              int num,
 338                                              struct ether_addr *addr);
 339 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 340                                              struct i40e_macvlan_filter *mv_f,
 341                                              int num,
 342                                              uint16_t vlan);
 343 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 344 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 345                                     struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 347                                       struct rte_eth_rss_conf *rss_conf);
 348 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 351                                         struct rte_eth_udp_tunnel *udp_tunnel);
 352 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 353 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 354                                 enum rte_filter_op filter_op,
 355                                 void *arg);
 356 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 357                                 enum rte_filter_type filter_type,
 358                                 enum rte_filter_op filter_op,
 359                                 void *arg);
 360 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 361                                   struct rte_eth_dcb_info *dcb_info);
 362 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 363 static void i40e_configure_registers(struct i40e_hw *hw);
 364 static void i40e_hw_init(struct rte_eth_dev *dev);
 365 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 367                         struct rte_eth_mirror_conf *mirror_conf,
 368                         uint8_t sw_id, uint8_t on);
 369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 370
 371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp,
 375                                            uint32_t flags);
 376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp);
 378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 379
 380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 381
 382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 383                                    struct timespec *timestamp);
 384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 385                                     const struct timespec *timestamp);
 386
 387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 388                                          uint16_t queue_id);
 389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 390                                           uint16_t queue_id);
 391
 392 static int i40e_get_regs(struct rte_eth_dev *dev,
 393                          struct rte_dev_reg_info *regs);
 394
 395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 396
 397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 398                            struct rte_dev_eeprom_info *eeprom);
 399
 400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 401                                       struct ether_addr *mac_addr);
 402
 403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 404
 405 static int i40e_ethertype_filter_convert(
 406         const struct rte_eth_ethertype_filter *input,
 407         struct i40e_ethertype_filter *filter);
 408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 409                                    struct i40e_ethertype_filter *filter);
 410
 411 static int i40e_tunnel_filter_convert(
 412         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 413         struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 415                                 struct i40e_tunnel_filter *tunnel_filter);
 416
 417 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 418 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 419 static void i40e_filter_restore(struct i40e_pf *pf);
 420
 421 static const struct rte_pci_id pci_id_i40e_map[] = {
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 442         { .vendor_id = 0, /* sentinel */ },
 443 };
 444
 445 static const struct eth_dev_ops i40e_eth_dev_ops = {
 446         .dev_configure                = i40e_dev_configure,
 447         .dev_start                    = i40e_dev_start,
 448         .dev_stop                     = i40e_dev_stop,
 449         .dev_close                    = i40e_dev_close,
 450         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 451         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 452         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 453         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 454         .dev_set_link_up              = i40e_dev_set_link_up,
 455         .dev_set_link_down            = i40e_dev_set_link_down,
 456         .link_update                  = i40e_dev_link_update,
 457         .stats_get                    = i40e_dev_stats_get,
 458         .xstats_get                   = i40e_dev_xstats_get,
 459         .xstats_get_names             = i40e_dev_xstats_get_names,
 460         .stats_reset                  = i40e_dev_stats_reset,
 461         .xstats_reset                 = i40e_dev_stats_reset,
 462         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 463         .fw_version_get               = i40e_fw_version_get,
 464         .dev_infos_get                = i40e_dev_info_get,
 465         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 466         .vlan_filter_set              = i40e_vlan_filter_set,
 467         .vlan_tpid_set                = i40e_vlan_tpid_set,
 468         .vlan_offload_set             = i40e_vlan_offload_set,
 469         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 470         .vlan_pvid_set                = i40e_vlan_pvid_set,
 471         .rx_queue_start               = i40e_dev_rx_queue_start,
 472         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 473         .tx_queue_start               = i40e_dev_tx_queue_start,
 474         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 475         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 476         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 477         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 478         .rx_queue_release             = i40e_dev_rx_queue_release,
 479         .rx_queue_count               = i40e_dev_rx_queue_count,
 480         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514 };
 515
 516 /* store statistics names and its offset in stats structure */
 517 struct rte_i40e_xstats_name_off {
 518         char name[RTE_ETH_XSTATS_NAME_SIZE];
 519         unsigned offset;
 520 };
 521
 522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 523         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 524         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 525         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 526         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 527         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 528                 rx_unknown_protocol)},
 529         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 530         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 531         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 532         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 533 };
 534
 535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 536                 sizeof(rte_i40e_stats_strings[0]))
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 539         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 540                 tx_dropped_link_down)},
 541         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 542         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 543                 illegal_bytes)},
 544         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 545         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_local_faults)},
 547         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_remote_faults)},
 549         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_length_errors)},
 551         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 552         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 553         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 554         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 555         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 556         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_127)},
 558         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_511)},
 562         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1023)},
 564         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1522)},
 566         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_big)},
 568         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_undersize)},
 570         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_oversize)},
 572         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 573                 mac_short_packet_dropped)},
 574         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_fragments)},
 576         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 577         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_127)},
 580         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_255)},
 582         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_511)},
 584         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1023)},
 586         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1522)},
 588         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_big)},
 590         {"rx_flow_director_atr_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 592         {"rx_flow_director_sb_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 594         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 tx_lpi_status)},
 596         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 rx_lpi_status)},
 598         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_count)},
 600         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_count)},
 602 };
 603
 604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 605                 sizeof(rte_i40e_hw_port_strings[0]))
 606
 607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 608         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xon_rx)},
 610         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xoff_rx)},
 612 };
 613
 614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 615                 sizeof(rte_i40e_rxq_prio_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_tx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_tx)},
 622         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_2_xoff)},
 624 };
 625
 626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 627                 sizeof(rte_i40e_txq_prio_strings[0]))
 628
 629 static struct eth_driver rte_i40e_pmd = {
 630         .pci_drv = {
 631                 .id_table = pci_id_i40e_map,
 632                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 633                 .probe = rte_eth_dev_pci_probe,
 634                 .remove = rte_eth_dev_pci_remove,
 635         },
 636         .eth_dev_init = eth_i40e_dev_init,
 637         .eth_dev_uninit = eth_i40e_dev_uninit,
 638         .dev_private_size = sizeof(struct i40e_adapter),
 639 };
 640
 641 static inline int
 642 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 643                                      struct rte_eth_link *link)
 644 {
 645         struct rte_eth_link *dst = link;
 646         struct rte_eth_link *src = &(dev->data->dev_link);
 647
 648         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 649                                         *(uint64_t *)src) == 0)
 650                 return -1;
 651
 652         return 0;
 653 }
 654
 655 static inline int
 656 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 657                                       struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = &(dev->data->dev_link);
 660         struct rte_eth_link *src = link;
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 670 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 671 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 672
 673 #ifndef I40E_GLQF_ORT
 674 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 675 #endif
 676 #ifndef I40E_GLQF_PIT
 677 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 678 #endif
 679
 680 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 681 {
 682         /*
 683          * Initialize registers for flexible payload, which should be set by NVM.
 684          * This should be removed from code once it is fixed in NVM.
 685          */
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 696         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 698
 699         /* Initialize registers for parsing packet type of QinQ */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 701         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 702 }
 703
 704 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 705
 706 /*
 707  * Add a ethertype filter to drop all flow control frames transmitted
 708  * from VSIs.
 709 */
 710 static void
 711 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 712 {
 713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 714         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 715                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 716                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 717         int ret;
 718
 719         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 720                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 721                                 pf->main_vsi_seid, 0,
 722                                 TRUE, NULL, NULL);
 723         if (ret)
 724                 PMD_INIT_LOG(ERR,
 725                         "Failed to add filter to drop flow control frames from VSIs.");
 726 }
 727
 728 static int
 729 floating_veb_list_handler(__rte_unused const char *key,
 730                           const char *floating_veb_value,
 731                           void *opaque)
 732 {
 733         int idx = 0;
 734         unsigned int count = 0;
 735         char *end = NULL;
 736         int min, max;
 737         bool *vf_floating_veb = opaque;
 738
 739         while (isblank(*floating_veb_value))
 740                 floating_veb_value++;
 741
 742         /* Reset floating VEB configuration for VFs */
 743         for (idx = 0; idx < I40E_MAX_VF; idx++)
 744                 vf_floating_veb[idx] = false;
 745
 746         min = I40E_MAX_VF;
 747         do {
 748                 while (isblank(*floating_veb_value))
 749                         floating_veb_value++;
 750                 if (*floating_veb_value == '\0')
 751                         return -1;
 752                 errno = 0;
 753                 idx = strtoul(floating_veb_value, &end, 10);
 754                 if (errno || end == NULL)
 755                         return -1;
 756                 while (isblank(*end))
 757                         end++;
 758                 if (*end == '-') {
 759                         min = idx;
 760                 } else if ((*end == ';') || (*end == '\0')) {
 761                         max = idx;
 762                         if (min == I40E_MAX_VF)
 763                                 min = idx;
 764                         if (max >= I40E_MAX_VF)
 765                                 max = I40E_MAX_VF - 1;
 766                         for (idx = min; idx <= max; idx++) {
 767                                 vf_floating_veb[idx] = true;
 768                                 count++;
 769                         }
 770                         min = I40E_MAX_VF;
 771                 } else {
 772                         return -1;
 773                 }
 774                 floating_veb_value = end + 1;
 775         } while (*end != '\0');
 776
 777         if (count == 0)
 778                 return -1;
 779
 780         return 0;
 781 }
 782
 783 static void
 784 config_vf_floating_veb(struct rte_devargs *devargs,
 785                        uint16_t floating_veb,
 786                        bool *vf_floating_veb)
 787 {
 788         struct rte_kvargs *kvlist;
 789         int i;
 790         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 791
 792         if (!floating_veb)
 793                 return;
 794         /* All the VFs attach to the floating VEB by default
 795          * when the floating VEB is enabled.
 796          */
 797         for (i = 0; i < I40E_MAX_VF; i++)
 798                 vf_floating_veb[i] = true;
 799
 800         if (devargs == NULL)
 801                 return;
 802
 803         kvlist = rte_kvargs_parse(devargs->args, NULL);
 804         if (kvlist == NULL)
 805                 return;
 806
 807         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 808                 rte_kvargs_free(kvlist);
 809                 return;
 810         }
 811         /* When the floating_veb_list parameter exists, all the VFs
 812          * will attach to the legacy VEB firstly, then configure VFs
 813          * to the floating VEB according to the floating_veb_list.
 814          */
 815         if (rte_kvargs_process(kvlist, floating_veb_list,
 816                                floating_veb_list_handler,
 817                                vf_floating_veb) < 0) {
 818                 rte_kvargs_free(kvlist);
 819                 return;
 820         }
 821         rte_kvargs_free(kvlist);
 822 }
 823
 824 static int
 825 i40e_check_floating_handler(__rte_unused const char *key,
 826                             const char *value,
 827                             __rte_unused void *opaque)
 828 {
 829         if (strcmp(value, "1"))
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static int
 836 is_floating_veb_supported(struct rte_devargs *devargs)
 837 {
 838         struct rte_kvargs *kvlist;
 839         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 840
 841         if (devargs == NULL)
 842                 return 0;
 843
 844         kvlist = rte_kvargs_parse(devargs->args, NULL);
 845         if (kvlist == NULL)
 846                 return 0;
 847
 848         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 849                 rte_kvargs_free(kvlist);
 850                 return 0;
 851         }
 852         /* Floating VEB is enabled when there's key-value:
 853          * enable_floating_veb=1
 854          */
 855         if (rte_kvargs_process(kvlist, floating_veb_key,
 856                                i40e_check_floating_handler, NULL) < 0) {
 857                 rte_kvargs_free(kvlist);
 858                 return 0;
 859         }
 860         rte_kvargs_free(kvlist);
 861
 862         return 1;
 863 }
 864
 865 static void
 866 config_floating_veb(struct rte_eth_dev *dev)
 867 {
 868         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 871
 872         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 873
 874         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 875                 pf->floating_veb =
 876                         is_floating_veb_supported(pci_dev->device.devargs);
 877                 config_vf_floating_veb(pci_dev->device.devargs,
 878                                        pf->floating_veb,
 879                                        pf->floating_veb_list);
 880         } else {
 881                 pf->floating_veb = false;
 882         }
 883 }
 884
 885 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 886 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 887
 888 static int
 889 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 890 {
 891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 892         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 893         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 894         int ret;
 895
 896         struct rte_hash_parameters ethertype_hash_params = {
 897                 .name = ethertype_hash_name,
 898                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 899                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 900                 .hash_func = rte_hash_crc,
 901         };
 902
 903         /* Initialize ethertype filter rule list and hash */
 904         TAILQ_INIT(&ethertype_rule->ethertype_list);
 905         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 906                  "ethertype_%s", dev->data->name);
 907         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 908         if (!ethertype_rule->hash_table) {
 909                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 910                 return -EINVAL;
 911         }
 912         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 913                                        sizeof(struct i40e_ethertype_filter *) *
 914                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 915                                        0);
 916         if (!ethertype_rule->hash_map) {
 917                 PMD_INIT_LOG(ERR,
 918                              "Failed to allocate memory for ethertype hash map!");
 919                 ret = -ENOMEM;
 920                 goto err_ethertype_hash_map_alloc;
 921         }
 922
 923         return 0;
 924
 925 err_ethertype_hash_map_alloc:
 926         rte_hash_free(ethertype_rule->hash_table);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 933 {
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 936         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 937         int ret;
 938
 939         struct rte_hash_parameters tunnel_hash_params = {
 940                 .name = tunnel_hash_name,
 941                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 942                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 943                 .hash_func = rte_hash_crc,
 944         };
 945
 946         /* Initialize tunnel filter rule list and hash */
 947         TAILQ_INIT(&tunnel_rule->tunnel_list);
 948         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 949                  "tunnel_%s", dev->data->name);
 950         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 951         if (!tunnel_rule->hash_table) {
 952                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 953                 return -EINVAL;
 954         }
 955         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 956                                     sizeof(struct i40e_tunnel_filter *) *
 957                                     I40E_MAX_TUNNEL_FILTER_NUM,
 958                                     0);
 959         if (!tunnel_rule->hash_map) {
 960                 PMD_INIT_LOG(ERR,
 961                              "Failed to allocate memory for tunnel hash map!");
 962                 ret = -ENOMEM;
 963                 goto err_tunnel_hash_map_alloc;
 964         }
 965
 966         return 0;
 967
 968 err_tunnel_hash_map_alloc:
 969         rte_hash_free(tunnel_rule->hash_table);
 970
 971         return ret;
 972 }
 973
 974 static int
 975 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 976 {
 977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 978         struct i40e_fdir_info *fdir_info = &pf->fdir;
 979         char fdir_hash_name[RTE_HASH_NAMESIZE];
 980         int ret;
 981
 982         struct rte_hash_parameters fdir_hash_params = {
 983                 .name = fdir_hash_name,
 984                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 985                 .key_len = sizeof(struct rte_eth_fdir_input),
 986                 .hash_func = rte_hash_crc,
 987         };
 988
 989         /* Initialize flow director filter rule list and hash */
 990         TAILQ_INIT(&fdir_info->fdir_list);
 991         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 992                  "fdir_%s", dev->data->name);
 993         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 994         if (!fdir_info->hash_table) {
 995                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 996                 return -EINVAL;
 997         }
 998         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 999                                           sizeof(struct i40e_fdir_filter *) *
1000                                           I40E_MAX_FDIR_FILTER_NUM,
1001                                           0);
1002         if (!fdir_info->hash_map) {
1003                 PMD_INIT_LOG(ERR,
1004                              "Failed to allocate memory for fdir hash map!");
1005                 ret = -ENOMEM;
1006                 goto err_fdir_hash_map_alloc;
1007         }
1008         return 0;
1009
1010 err_fdir_hash_map_alloc:
1011         rte_hash_free(fdir_info->hash_table);
1012
1013         return ret;
1014 }
1015
1016 static int
1017 eth_i40e_dev_init(struct rte_eth_dev *dev)
1018 {
1019         struct rte_pci_device *pci_dev;
1020         struct rte_intr_handle *intr_handle;
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023         struct i40e_vsi *vsi;
1024         int ret;
1025         uint32_t len;
1026         uint8_t aq_fail = 0;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         dev->dev_ops = &i40e_eth_dev_ops;
1031         dev->rx_pkt_burst = i40e_recv_pkts;
1032         dev->tx_pkt_burst = i40e_xmit_pkts;
1033         dev->tx_pkt_prepare = i40e_prep_pkts;
1034
1035         /* for secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX function */
1038         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1039                 i40e_set_rx_function(dev);
1040                 i40e_set_tx_function(dev);
1041                 return 0;
1042         }
1043         pci_dev = I40E_DEV_TO_PCI(dev);
1044         intr_handle = &pci_dev->intr_handle;
1045
1046         rte_eth_copy_pci_info(dev, pci_dev);
1047         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1048
1049         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1050         pf->adapter->eth_dev = dev;
1051         pf->dev_data = dev->data;
1052
1053         hw->back = I40E_PF_TO_ADAPTER(pf);
1054         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1055         if (!hw->hw_addr) {
1056                 PMD_INIT_LOG(ERR,
1057                         "Hardware is not available, as address is NULL");
1058                 return -ENODEV;
1059         }
1060
1061         hw->vendor_id = pci_dev->id.vendor_id;
1062         hw->device_id = pci_dev->id.device_id;
1063         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1064         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1065         hw->bus.device = pci_dev->addr.devid;
1066         hw->bus.func = pci_dev->addr.function;
1067         hw->adapter_stopped = 0;
1068
1069         /* Make sure all is clean before doing PF reset */
1070         i40e_clear_hw(hw);
1071
1072         /* Initialize the hardware */
1073         i40e_hw_init(dev);
1074
1075         /* Reset here to make sure all is clean for each PF */
1076         ret = i40e_pf_reset(hw);
1077         if (ret) {
1078                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1079                 return ret;
1080         }
1081
1082         /* Initialize the shared code (base driver) */
1083         ret = i40e_init_shared_code(hw);
1084         if (ret) {
1085                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1086                 return ret;
1087         }
1088
1089         /*
1090          * To work around the NVM issue, initialize registers
1091          * for flexible payload and packet type of QinQ by
1092          * software. It should be removed once issues are fixed
1093          * in NVM.
1094          */
1095         i40e_GLQF_reg_init(hw);
1096
1097         /* Initialize the input set for filters (hash and fd) to default value */
1098         i40e_filter_input_set_init(pf);
1099
1100         /* Initialize the parameters for adminq */
1101         i40e_init_adminq_parameter(hw);
1102         ret = i40e_init_adminq(hw);
1103         if (ret != I40E_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1105                 return -EIO;
1106         }
1107         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1108                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1109                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1110                      ((hw->nvm.version >> 12) & 0xf),
1111                      ((hw->nvm.version >> 4) & 0xff),
1112                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1113
1114         /* Need the special FW version to support floating VEB */
1115         config_floating_veb(dev);
1116         /* Clear PXE mode */
1117         i40e_clear_pxe_mode(hw);
1118         ret = i40e_dev_sync_phy_type(hw);
1119         if (ret) {
1120                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1121                 goto err_sync_phy_type;
1122         }
1123         /*
1124          * On X710, performance number is far from the expectation on recent
1125          * firmware versions. The fix for this issue may not be integrated in
1126          * the following firmware version. So the workaround in software driver
1127          * is needed. It needs to modify the initial values of 3 internal only
1128          * registers. Note that the workaround can be removed when it is fixed
1129          * in firmware in the future.
1130          */
1131         i40e_configure_registers(hw);
1132
1133         /* Get hw capabilities */
1134         ret = i40e_get_cap(hw);
1135         if (ret != I40E_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1137                 goto err_get_capabilities;
1138         }
1139
1140         /* Initialize parameters for PF */
1141         ret = i40e_pf_parameter_init(dev);
1142         if (ret != 0) {
1143                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1144                 goto err_parameter_init;
1145         }
1146
1147         /* Initialize the queue management */
1148         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1149         if (ret < 0) {
1150                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1151                 goto err_qp_pool_init;
1152         }
1153         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1154                                 hw->func_caps.num_msix_vectors - 1);
1155         if (ret < 0) {
1156                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1157                 goto err_msix_pool_init;
1158         }
1159
1160         /* Initialize lan hmc */
1161         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1162                                 hw->func_caps.num_rx_qp, 0, 0);
1163         if (ret != I40E_SUCCESS) {
1164                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1165                 goto err_init_lan_hmc;
1166         }
1167
1168         /* Configure lan hmc */
1169         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1170         if (ret != I40E_SUCCESS) {
1171                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1172                 goto err_configure_lan_hmc;
1173         }
1174
1175         /* Get and check the mac address */
1176         i40e_get_mac_addr(hw, hw->mac.addr);
1177         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "mac address is not valid");
1179                 ret = -EIO;
1180                 goto err_get_mac_addr;
1181         }
1182         /* Copy the permanent MAC address */
1183         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1184                         (struct ether_addr *) hw->mac.perm_addr);
1185
1186         /* Disable flow control */
1187         hw->fc.requested_mode = I40E_FC_NONE;
1188         i40e_set_fc(hw, &aq_fail, TRUE);
1189
1190         /* Set the global registers with default ether type value */
1191         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR,
1194                         "Failed to set the default outer VLAN ether type");
1195                 goto err_setup_pf_switch;
1196         }
1197
1198         /* PF setup, which includes VSI setup */
1199         ret = i40e_pf_setup(pf);
1200         if (ret) {
1201                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1202                 goto err_setup_pf_switch;
1203         }
1204
1205         /* reset all stats of the device, including pf and main vsi */
1206         i40e_dev_stats_reset(dev);
1207
1208         vsi = pf->main_vsi;
1209
1210         /* Disable double vlan by default */
1211         i40e_vsi_config_double_vlan(vsi, FALSE);
1212
1213         /* Disable S-TAG identification when floating_veb is disabled */
1214         if (!pf->floating_veb) {
1215                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1216                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1217                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1218                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1219                 }
1220         }
1221
1222         if (!vsi->max_macaddrs)
1223                 len = ETHER_ADDR_LEN;
1224         else
1225                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1226
1227         /* Should be after VSI initialized */
1228         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1229         if (!dev->data->mac_addrs) {
1230                 PMD_INIT_LOG(ERR,
1231                         "Failed to allocated memory for storing mac address");
1232                 goto err_mac_alloc;
1233         }
1234         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1235                                         &dev->data->mac_addrs[0]);
1236
1237         /* initialize pf host driver to setup SRIOV resource if applicable */
1238         i40e_pf_host_init(dev);
1239
1240         /* register callback func to eal lib */
1241         rte_intr_callback_register(intr_handle,
1242                                    i40e_dev_interrupt_handler, dev);
1243
1244         /* configure and enable device interrupt */
1245         i40e_pf_config_irq0(hw, TRUE);
1246         i40e_pf_enable_irq0(hw);
1247
1248         /* enable uio intr after callback register */
1249         rte_intr_enable(intr_handle);
1250         /*
1251          * Add an ethertype filter to drop all flow control frames transmitted
1252          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1253          * frames to wire.
1254          */
1255         i40e_add_tx_flow_control_drop_filter(pf);
1256
1257         /* Set the max frame size to 0x2600 by default,
1258          * in case other drivers changed the default value.
1259          */
1260         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1261
1262         /* initialize mirror rule list */
1263         TAILQ_INIT(&pf->mirror_list);
1264
1265         /* Init dcb to sw mode by default */
1266         ret = i40e_dcb_init_configure(dev, TRUE);
1267         if (ret != I40E_SUCCESS) {
1268                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1269                 pf->flags &= ~I40E_FLAG_DCB;
1270         }
1271
1272         ret = i40e_init_ethtype_filter_list(dev);
1273         if (ret < 0)
1274                 goto err_init_ethtype_filter_list;
1275         ret = i40e_init_tunnel_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_tunnel_filter_list;
1278         ret = i40e_init_fdir_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_fdir_filter_list;
1281
1282         return 0;
1283
1284 err_init_fdir_filter_list:
1285         rte_free(pf->tunnel.hash_table);
1286         rte_free(pf->tunnel.hash_map);
1287 err_init_tunnel_filter_list:
1288         rte_free(pf->ethertype.hash_table);
1289         rte_free(pf->ethertype.hash_map);
1290 err_init_ethtype_filter_list:
1291         rte_free(dev->data->mac_addrs);
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static void
1312 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1313 {
1314         struct i40e_ethertype_filter *p_ethertype;
1315         struct i40e_ethertype_rule *ethertype_rule;
1316
1317         ethertype_rule = &pf->ethertype;
1318         /* Remove all ethertype filter rules and hash */
1319         if (ethertype_rule->hash_map)
1320                 rte_free(ethertype_rule->hash_map);
1321         if (ethertype_rule->hash_table)
1322                 rte_hash_free(ethertype_rule->hash_table);
1323
1324         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1325                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1326                              p_ethertype, rules);
1327                 rte_free(p_ethertype);
1328         }
1329 }
1330
1331 static void
1332 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1333 {
1334         struct i40e_tunnel_filter *p_tunnel;
1335         struct i40e_tunnel_rule *tunnel_rule;
1336
1337         tunnel_rule = &pf->tunnel;
1338         /* Remove all tunnel director rules and hash */
1339         if (tunnel_rule->hash_map)
1340                 rte_free(tunnel_rule->hash_map);
1341         if (tunnel_rule->hash_table)
1342                 rte_hash_free(tunnel_rule->hash_table);
1343
1344         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1345                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1346                 rte_free(p_tunnel);
1347         }
1348 }
1349
1350 static void
1351 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1352 {
1353         struct i40e_fdir_filter *p_fdir;
1354         struct i40e_fdir_info *fdir_info;
1355
1356         fdir_info = &pf->fdir;
1357         /* Remove all flow director rules and hash */
1358         if (fdir_info->hash_map)
1359                 rte_free(fdir_info->hash_map);
1360         if (fdir_info->hash_table)
1361                 rte_hash_free(fdir_info->hash_table);
1362
1363         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1364                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1365                 rte_free(p_fdir);
1366         }
1367 }
1368
1369 static int
1370 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1371 {
1372         struct i40e_pf *pf;
1373         struct rte_pci_device *pci_dev;
1374         struct rte_intr_handle *intr_handle;
1375         struct i40e_hw *hw;
1376         struct i40e_filter_control_settings settings;
1377         struct rte_flow *p_flow;
1378         int ret;
1379         uint8_t aq_fail = 0;
1380
1381         PMD_INIT_FUNC_TRACE();
1382
1383         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1384                 return 0;
1385
1386         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         pci_dev = I40E_DEV_TO_PCI(dev);
1389         intr_handle = &pci_dev->intr_handle;
1390
1391         if (hw->adapter_stopped == 0)
1392                 i40e_dev_close(dev);
1393
1394         dev->dev_ops = NULL;
1395         dev->rx_pkt_burst = NULL;
1396         dev->tx_pkt_burst = NULL;
1397
1398         /* Clear PXE mode */
1399         i40e_clear_pxe_mode(hw);
1400
1401         /* Unconfigure filter control */
1402         memset(&settings, 0, sizeof(settings));
1403         ret = i40e_set_filter_control(hw, &settings);
1404         if (ret)
1405                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1406                                         ret);
1407
1408         /* Disable flow control */
1409         hw->fc.requested_mode = I40E_FC_NONE;
1410         i40e_set_fc(hw, &aq_fail, TRUE);
1411
1412         /* uninitialize pf host driver */
1413         i40e_pf_host_uninit(dev);
1414
1415         rte_free(dev->data->mac_addrs);
1416         dev->data->mac_addrs = NULL;
1417
1418         /* disable uio intr before callback unregister */
1419         rte_intr_disable(intr_handle);
1420
1421         /* register callback func to eal lib */
1422         rte_intr_callback_unregister(intr_handle,
1423                                      i40e_dev_interrupt_handler, dev);
1424
1425         i40e_rm_ethtype_filter_list(pf);
1426         i40e_rm_tunnel_filter_list(pf);
1427         i40e_rm_fdir_filter_list(pf);
1428
1429         /* Remove all flows */
1430         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1431                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1432                 rte_free(p_flow);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int
1439 i40e_dev_configure(struct rte_eth_dev *dev)
1440 {
1441         struct i40e_adapter *ad =
1442                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1445         int i, ret;
1446
1447         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1448          * bulk allocation or vector Rx preconditions we will reset it.
1449          */
1450         ad->rx_bulk_alloc_allowed = true;
1451         ad->rx_vec_allowed = true;
1452         ad->tx_simple_allowed = true;
1453         ad->tx_vec_allowed = true;
1454
1455         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1456                 ret = i40e_fdir_setup(pf);
1457                 if (ret != I40E_SUCCESS) {
1458                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1459                         return -ENOTSUP;
1460                 }
1461                 ret = i40e_fdir_configure(dev);
1462                 if (ret < 0) {
1463                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1464                         goto err;
1465                 }
1466         } else
1467                 i40e_fdir_teardown(pf);
1468
1469         ret = i40e_dev_init_vlan(dev);
1470         if (ret < 0)
1471                 goto err;
1472
1473         /* VMDQ setup.
1474          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1475          *  RSS setting have different requirements.
1476          *  General PMD driver call sequence are NIC init, configure,
1477          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1478          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1479          *  applicable. So, VMDQ setting has to be done before
1480          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1481          *  For RSS setting, it will try to calculate actual configured RX queue
1482          *  number, which will be available after rx_queue_setup(). dev_start()
1483          *  function is good to place RSS setup.
1484          */
1485         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1486                 ret = i40e_vmdq_setup(dev);
1487                 if (ret)
1488                         goto err;
1489         }
1490
1491         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1492                 ret = i40e_dcb_setup(dev);
1493                 if (ret) {
1494                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1495                         goto err_dcb;
1496                 }
1497         }
1498
1499         TAILQ_INIT(&pf->flow_list);
1500
1501         return 0;
1502
1503 err_dcb:
1504         /* need to release vmdq resource if exists */
1505         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1506                 i40e_vsi_release(pf->vmdq[i].vsi);
1507                 pf->vmdq[i].vsi = NULL;
1508         }
1509         rte_free(pf->vmdq);
1510         pf->vmdq = NULL;
1511 err:
1512         /* need to release fdir resource if exists */
1513         i40e_fdir_teardown(pf);
1514         return ret;
1515 }
1516
1517 void
1518 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1519 {
1520         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1521         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524         uint16_t msix_vect = vsi->msix_intr;
1525         uint16_t i;
1526
1527         for (i = 0; i < vsi->nb_qps; i++) {
1528                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1529                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1530                 rte_wmb();
1531         }
1532
1533         if (vsi->type != I40E_VSI_SRIOV) {
1534                 if (!rte_intr_allow_others(intr_handle)) {
1535                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1536                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1537                         I40E_WRITE_REG(hw,
1538                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1539                                        0);
1540                 } else {
1541                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1542                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1543                         I40E_WRITE_REG(hw,
1544                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1545                                                        msix_vect - 1), 0);
1546                 }
1547         } else {
1548                 uint32_t reg;
1549                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1550                         vsi->user_param + (msix_vect - 1);
1551
1552                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1553                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1554         }
1555         I40E_WRITE_FLUSH(hw);
1556 }
1557
1558 static void
1559 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1560                        int base_queue, int nb_queue)
1561 {
1562         int i;
1563         uint32_t val;
1564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565
1566         /* Bind all RX queues to allocated MSIX interrupt */
1567         for (i = 0; i < nb_queue; i++) {
1568                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1569                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1570                         ((base_queue + i + 1) <<
1571                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1572                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1573                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1574
1575                 if (i == nb_queue - 1)
1576                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1577                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1578         }
1579
1580         /* Write first RX queue to Link list register as the head element */
1581         if (vsi->type != I40E_VSI_SRIOV) {
1582                 uint16_t interval =
1583                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1584
1585                 if (msix_vect == I40E_MISC_VEC_ID) {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587                                        (base_queue <<
1588                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1589                                        (0x0 <<
1590                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1591                         I40E_WRITE_REG(hw,
1592                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1593                                        interval);
1594                 } else {
1595                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1596                                        (base_queue <<
1597                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1598                                        (0x0 <<
1599                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1600                         I40E_WRITE_REG(hw,
1601                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1602                                                        msix_vect - 1),
1603                                        interval);
1604                 }
1605         } else {
1606                 uint32_t reg;
1607
1608                 if (msix_vect == I40E_MISC_VEC_ID) {
1609                         I40E_WRITE_REG(hw,
1610                                        I40E_VPINT_LNKLST0(vsi->user_param),
1611                                        (base_queue <<
1612                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1613                                        (0x0 <<
1614                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1615                 } else {
1616                         /* num_msix_vectors_vf needs to minus irq0 */
1617                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1618                                 vsi->user_param + (msix_vect - 1);
1619
1620                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1621                                        (base_queue <<
1622                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1623                                        (0x0 <<
1624                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1625                 }
1626         }
1627
1628         I40E_WRITE_FLUSH(hw);
1629 }
1630
1631 void
1632 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1633 {
1634         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1635         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1638         uint16_t msix_vect = vsi->msix_intr;
1639         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1640         uint16_t queue_idx = 0;
1641         int record = 0;
1642         uint32_t val;
1643         int i;
1644
1645         for (i = 0; i < vsi->nb_qps; i++) {
1646                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1647                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1648         }
1649
1650         /* INTENA flag is not auto-cleared for interrupt */
1651         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1652         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1653                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1654                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1655         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1656
1657         /* VF bind interrupt */
1658         if (vsi->type == I40E_VSI_SRIOV) {
1659                 __vsi_queues_bind_intr(vsi, msix_vect,
1660                                        vsi->base_queue, vsi->nb_qps);
1661                 return;
1662         }
1663
1664         /* PF & VMDq bind interrupt */
1665         if (rte_intr_dp_is_en(intr_handle)) {
1666                 if (vsi->type == I40E_VSI_MAIN) {
1667                         queue_idx = 0;
1668                         record = 1;
1669                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1670                         struct i40e_vsi *main_vsi =
1671                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1672                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1673                         record = 1;
1674                 }
1675         }
1676
1677         for (i = 0; i < vsi->nb_used_qps; i++) {
1678                 if (nb_msix <= 1) {
1679                         if (!rte_intr_allow_others(intr_handle))
1680                                 /* allow to share MISC_VEC_ID */
1681                                 msix_vect = I40E_MISC_VEC_ID;
1682
1683                         /* no enough msix_vect, map all to one */
1684                         __vsi_queues_bind_intr(vsi, msix_vect,
1685                                                vsi->base_queue + i,
1686                                                vsi->nb_used_qps - i);
1687                         for (; !!record && i < vsi->nb_used_qps; i++)
1688                                 intr_handle->intr_vec[queue_idx + i] =
1689                                         msix_vect;
1690                         break;
1691                 }
1692                 /* 1:1 queue/msix_vect mapping */
1693                 __vsi_queues_bind_intr(vsi, msix_vect,
1694                                        vsi->base_queue + i, 1);
1695                 if (!!record)
1696                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1697
1698                 msix_vect++;
1699                 nb_msix--;
1700         }
1701 }
1702
1703 static void
1704 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1705 {
1706         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1707         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1710         uint16_t interval = i40e_calc_itr_interval(\
1711                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1712         uint16_t msix_intr, i;
1713
1714         if (rte_intr_allow_others(intr_handle))
1715                 for (i = 0; i < vsi->nb_msix; i++) {
1716                         msix_intr = vsi->msix_intr + i;
1717                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1718                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1719                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1720                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1721                                 (interval <<
1722                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1723                 }
1724         else
1725                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1726                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1727                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1728                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1729                                (interval <<
1730                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1731
1732         I40E_WRITE_FLUSH(hw);
1733 }
1734
1735 static void
1736 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1737 {
1738         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1739         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1742         uint16_t msix_intr, i;
1743
1744         if (rte_intr_allow_others(intr_handle))
1745                 for (i = 0; i < vsi->nb_msix; i++) {
1746                         msix_intr = vsi->msix_intr + i;
1747                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748                                        0);
1749                 }
1750         else
1751                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1752
1753         I40E_WRITE_FLUSH(hw);
1754 }
1755
1756 static inline uint8_t
1757 i40e_parse_link_speeds(uint16_t link_speeds)
1758 {
1759         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1760
1761         if (link_speeds & ETH_LINK_SPEED_40G)
1762                 link_speed |= I40E_LINK_SPEED_40GB;
1763         if (link_speeds & ETH_LINK_SPEED_25G)
1764                 link_speed |= I40E_LINK_SPEED_25GB;
1765         if (link_speeds & ETH_LINK_SPEED_20G)
1766                 link_speed |= I40E_LINK_SPEED_20GB;
1767         if (link_speeds & ETH_LINK_SPEED_10G)
1768                 link_speed |= I40E_LINK_SPEED_10GB;
1769         if (link_speeds & ETH_LINK_SPEED_1G)
1770                 link_speed |= I40E_LINK_SPEED_1GB;
1771         if (link_speeds & ETH_LINK_SPEED_100M)
1772                 link_speed |= I40E_LINK_SPEED_100MB;
1773
1774         return link_speed;
1775 }
1776
1777 static int
1778 i40e_phy_conf_link(struct i40e_hw *hw,
1779                    uint8_t abilities,
1780                    uint8_t force_speed)
1781 {
1782         enum i40e_status_code status;
1783         struct i40e_aq_get_phy_abilities_resp phy_ab;
1784         struct i40e_aq_set_phy_config phy_conf;
1785         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1786                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1787                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1788                         I40E_AQ_PHY_FLAG_LOW_POWER;
1789         const uint8_t advt = I40E_LINK_SPEED_40GB |
1790                         I40E_LINK_SPEED_25GB |
1791                         I40E_LINK_SPEED_10GB |
1792                         I40E_LINK_SPEED_1GB |
1793                         I40E_LINK_SPEED_100MB;
1794         int ret = -ENOTSUP;
1795
1796
1797         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1798                                               NULL);
1799         if (status)
1800                 return ret;
1801
1802         memset(&phy_conf, 0, sizeof(phy_conf));
1803
1804         /* bits 0-2 use the values from get_phy_abilities_resp */
1805         abilities &= ~mask;
1806         abilities |= phy_ab.abilities & mask;
1807
1808         /* update ablities and speed */
1809         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1810                 phy_conf.link_speed = advt;
1811         else
1812                 phy_conf.link_speed = force_speed;
1813
1814         phy_conf.abilities = abilities;
1815
1816         /* use get_phy_abilities_resp value for the rest */
1817         phy_conf.phy_type = phy_ab.phy_type;
1818         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1819         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1820         phy_conf.eee_capability = phy_ab.eee_capability;
1821         phy_conf.eeer = phy_ab.eeer_val;
1822         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1823
1824         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1825                     phy_ab.abilities, phy_ab.link_speed);
1826         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1827                     phy_conf.abilities, phy_conf.link_speed);
1828
1829         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1830         if (status)
1831                 return ret;
1832
1833         return I40E_SUCCESS;
1834 }
1835
1836 static int
1837 i40e_apply_link_speed(struct rte_eth_dev *dev)
1838 {
1839         uint8_t speed;
1840         uint8_t abilities = 0;
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct rte_eth_conf *conf = &dev->data->dev_conf;
1843
1844         speed = i40e_parse_link_speeds(conf->link_speeds);
1845         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1846         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1847                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1848         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1849
1850         /* Skip changing speed on 40G interfaces, FW does not support */
1851         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1852                 speed =  I40E_LINK_SPEED_UNKNOWN;
1853                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1854         }
1855
1856         return i40e_phy_conf_link(hw, abilities, speed);
1857 }
1858
1859 static int
1860 i40e_dev_start(struct rte_eth_dev *dev)
1861 {
1862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         struct i40e_vsi *main_vsi = pf->main_vsi;
1865         int ret, i;
1866         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1868         uint32_t intr_vector = 0;
1869
1870         hw->adapter_stopped = 0;
1871
1872         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1873                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1874                              dev->data->port_id);
1875                 return -EINVAL;
1876         }
1877
1878         rte_intr_disable(intr_handle);
1879
1880         if ((rte_intr_cap_multiple(intr_handle) ||
1881              !RTE_ETH_DEV_SRIOV(dev).active) &&
1882             dev->data->dev_conf.intr_conf.rxq != 0) {
1883                 intr_vector = dev->data->nb_rx_queues;
1884                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1885                 if (ret)
1886                         return ret;
1887         }
1888
1889         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1890                 intr_handle->intr_vec =
1891                         rte_zmalloc("intr_vec",
1892                                     dev->data->nb_rx_queues * sizeof(int),
1893                                     0);
1894                 if (!intr_handle->intr_vec) {
1895                         PMD_INIT_LOG(ERR,
1896                                 "Failed to allocate %d rx_queues intr_vec\n",
1897                                 dev->data->nb_rx_queues);
1898                         return -ENOMEM;
1899                 }
1900         }
1901
1902         /* Initialize VSI */
1903         ret = i40e_dev_rxtx_init(pf);
1904         if (ret != I40E_SUCCESS) {
1905                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1906                 goto err_up;
1907         }
1908
1909         /* Map queues with MSIX interrupt */
1910         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1911                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1912         i40e_vsi_queues_bind_intr(main_vsi);
1913         i40e_vsi_enable_queues_intr(main_vsi);
1914
1915         /* Map VMDQ VSI queues with MSIX interrupt */
1916         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1917                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1918                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1919                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1920         }
1921
1922         /* enable FDIR MSIX interrupt */
1923         if (pf->fdir.fdir_vsi) {
1924                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1925                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1926         }
1927
1928         /* Enable all queues which have been configured */
1929         ret = i40e_dev_switch_queues(pf, TRUE);
1930         if (ret != I40E_SUCCESS) {
1931                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1932                 goto err_up;
1933         }
1934
1935         /* Enable receiving broadcast packets */
1936         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1937         if (ret != I40E_SUCCESS)
1938                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1939
1940         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1941                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1942                                                 true, NULL);
1943                 if (ret != I40E_SUCCESS)
1944                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1945         }
1946
1947         /* Apply link configure */
1948         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1949                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1950                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1951                                 ETH_LINK_SPEED_40G)) {
1952                 PMD_DRV_LOG(ERR, "Invalid link setting");
1953                 goto err_up;
1954         }
1955         ret = i40e_apply_link_speed(dev);
1956         if (I40E_SUCCESS != ret) {
1957                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1958                 goto err_up;
1959         }
1960
1961         if (!rte_intr_allow_others(intr_handle)) {
1962                 rte_intr_callback_unregister(intr_handle,
1963                                              i40e_dev_interrupt_handler,
1964                                              (void *)dev);
1965                 /* configure and enable device interrupt */
1966                 i40e_pf_config_irq0(hw, FALSE);
1967                 i40e_pf_enable_irq0(hw);
1968
1969                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1970                         PMD_INIT_LOG(INFO,
1971                                 "lsc won't enable because of no intr multiplex\n");
1972         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1973                 ret = i40e_aq_set_phy_int_mask(hw,
1974                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1975                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1976                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1977                 if (ret != I40E_SUCCESS)
1978                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1979
1980                 /* Call get_link_info aq commond to enable LSE */
1981                 i40e_dev_link_update(dev, 0);
1982         }
1983
1984         /* enable uio intr after callback register */
1985         rte_intr_enable(intr_handle);
1986
1987         i40e_filter_restore(pf);
1988
1989         return I40E_SUCCESS;
1990
1991 err_up:
1992         i40e_dev_switch_queues(pf, FALSE);
1993         i40e_dev_clear_queues(dev);
1994
1995         return ret;
1996 }
1997
1998 static void
1999 i40e_dev_stop(struct rte_eth_dev *dev)
2000 {
2001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2002         struct i40e_vsi *main_vsi = pf->main_vsi;
2003         struct i40e_mirror_rule *p_mirror;
2004         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006         int i;
2007
2008         /* Disable all queues */
2009         i40e_dev_switch_queues(pf, FALSE);
2010
2011         /* un-map queues with interrupt registers */
2012         i40e_vsi_disable_queues_intr(main_vsi);
2013         i40e_vsi_queues_unbind_intr(main_vsi);
2014
2015         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2016                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2017                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2018         }
2019
2020         if (pf->fdir.fdir_vsi) {
2021                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2022                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2023         }
2024         /* Clear all queues and release memory */
2025         i40e_dev_clear_queues(dev);
2026
2027         /* Set link down */
2028         i40e_dev_set_link_down(dev);
2029
2030         /* Remove all mirror rules */
2031         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2032                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2033                 rte_free(p_mirror);
2034         }
2035         pf->nb_mirror_rule = 0;
2036
2037         if (!rte_intr_allow_others(intr_handle))
2038                 /* resume to the default handler */
2039                 rte_intr_callback_register(intr_handle,
2040                                            i40e_dev_interrupt_handler,
2041                                            (void *)dev);
2042
2043         /* Clean datapath event and queue/vec mapping */
2044         rte_intr_efd_disable(intr_handle);
2045         if (intr_handle->intr_vec) {
2046                 rte_free(intr_handle->intr_vec);
2047                 intr_handle->intr_vec = NULL;
2048         }
2049 }
2050
2051 static void
2052 i40e_dev_close(struct rte_eth_dev *dev)
2053 {
2054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         uint32_t reg;
2059         int i;
2060
2061         PMD_INIT_FUNC_TRACE();
2062
2063         i40e_dev_stop(dev);
2064         hw->adapter_stopped = 1;
2065         i40e_dev_free_queues(dev);
2066
2067         /* Disable interrupt */
2068         i40e_pf_disable_irq0(hw);
2069         rte_intr_disable(intr_handle);
2070
2071         /* shutdown and destroy the HMC */
2072         i40e_shutdown_lan_hmc(hw);
2073
2074         /* release all the existing VSIs and VEBs */
2075         i40e_fdir_teardown(pf);
2076         i40e_vsi_release(pf->main_vsi);
2077
2078         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2079                 i40e_vsi_release(pf->vmdq[i].vsi);
2080                 pf->vmdq[i].vsi = NULL;
2081         }
2082
2083         rte_free(pf->vmdq);
2084         pf->vmdq = NULL;
2085
2086         /* shutdown the adminq */
2087         i40e_aq_queue_shutdown(hw, true);
2088         i40e_shutdown_adminq(hw);
2089
2090         i40e_res_pool_destroy(&pf->qp_pool);
2091         i40e_res_pool_destroy(&pf->msix_pool);
2092
2093         /* force a PF reset to clean anything leftover */
2094         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2095         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2096                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static void
2101 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2102 {
2103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct i40e_vsi *vsi = pf->main_vsi;
2106         int status;
2107
2108         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2109                                                      true, NULL, true);
2110         if (status != I40E_SUCCESS)
2111                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2112
2113         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2114                                                         TRUE, NULL);
2115         if (status != I40E_SUCCESS)
2116                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2117
2118 }
2119
2120 static void
2121 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2122 {
2123         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct i40e_vsi *vsi = pf->main_vsi;
2126         int status;
2127
2128         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2129                                                      false, NULL, true);
2130         if (status != I40E_SUCCESS)
2131                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2132
2133         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2134                                                         false, NULL);
2135         if (status != I40E_SUCCESS)
2136                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2137 }
2138
2139 static void
2140 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2141 {
2142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct i40e_vsi *vsi = pf->main_vsi;
2145         int ret;
2146
2147         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2148         if (ret != I40E_SUCCESS)
2149                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2150 }
2151
2152 static void
2153 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2154 {
2155         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         struct i40e_vsi *vsi = pf->main_vsi;
2158         int ret;
2159
2160         if (dev->data->promiscuous == 1)
2161                 return; /* must remain in all_multicast mode */
2162
2163         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2164                                 vsi->seid, FALSE, NULL);
2165         if (ret != I40E_SUCCESS)
2166                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2167 }
2168
2169 /*
2170  * Set device link up.
2171  */
2172 static int
2173 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2174 {
2175         /* re-apply link speed setting */
2176         return i40e_apply_link_speed(dev);
2177 }
2178
2179 /*
2180  * Set device link down.
2181  */
2182 static int
2183 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2184 {
2185         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2186         uint8_t abilities = 0;
2187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188
2189         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2190         return i40e_phy_conf_link(hw, abilities, speed);
2191 }
2192
2193 int
2194 i40e_dev_link_update(struct rte_eth_dev *dev,
2195                      int wait_to_complete)
2196 {
2197 #define CHECK_INTERVAL 100  /* 100ms */
2198 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct i40e_link_status link_status;
2201         struct rte_eth_link link, old;
2202         int status;
2203         unsigned rep_cnt = MAX_REPEAT_TIME;
2204         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2205
2206         memset(&link, 0, sizeof(link));
2207         memset(&old, 0, sizeof(old));
2208         memset(&link_status, 0, sizeof(link_status));
2209         rte_i40e_dev_atomic_read_link_status(dev, &old);
2210
2211         do {
2212                 /* Get link status information from hardware */
2213                 status = i40e_aq_get_link_info(hw, enable_lse,
2214                                                 &link_status, NULL);
2215                 if (status != I40E_SUCCESS) {
2216                         link.link_speed = ETH_SPEED_NUM_100M;
2217                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2218                         PMD_DRV_LOG(ERR, "Failed to get link info");
2219                         goto out;
2220                 }
2221
2222                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2223                 if (!wait_to_complete)
2224                         break;
2225
2226                 rte_delay_ms(CHECK_INTERVAL);
2227         } while (!link.link_status && rep_cnt--);
2228
2229         if (!link.link_status)
2230                 goto out;
2231
2232         /* i40e uses full duplex only */
2233         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2234
2235         /* Parse the link status */
2236         switch (link_status.link_speed) {
2237         case I40E_LINK_SPEED_100MB:
2238                 link.link_speed = ETH_SPEED_NUM_100M;
2239                 break;
2240         case I40E_LINK_SPEED_1GB:
2241                 link.link_speed = ETH_SPEED_NUM_1G;
2242                 break;
2243         case I40E_LINK_SPEED_10GB:
2244                 link.link_speed = ETH_SPEED_NUM_10G;
2245                 break;
2246         case I40E_LINK_SPEED_20GB:
2247                 link.link_speed = ETH_SPEED_NUM_20G;
2248                 break;
2249         case I40E_LINK_SPEED_25GB:
2250                 link.link_speed = ETH_SPEED_NUM_25G;
2251                 break;
2252         case I40E_LINK_SPEED_40GB:
2253                 link.link_speed = ETH_SPEED_NUM_40G;
2254                 break;
2255         default:
2256                 link.link_speed = ETH_SPEED_NUM_100M;
2257                 break;
2258         }
2259
2260         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2261                         ETH_LINK_SPEED_FIXED);
2262
2263 out:
2264         rte_i40e_dev_atomic_write_link_status(dev, &link);
2265         if (link.link_status == old.link_status)
2266                 return -1;
2267
2268         return 0;
2269 }
2270
2271 /* Get all the statistics of a VSI */
2272 void
2273 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2274 {
2275         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2276         struct i40e_eth_stats *nes = &vsi->eth_stats;
2277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2278         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2279
2280         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2281                             vsi->offset_loaded, &oes->rx_bytes,
2282                             &nes->rx_bytes);
2283         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2284                             vsi->offset_loaded, &oes->rx_unicast,
2285                             &nes->rx_unicast);
2286         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2287                             vsi->offset_loaded, &oes->rx_multicast,
2288                             &nes->rx_multicast);
2289         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2290                             vsi->offset_loaded, &oes->rx_broadcast,
2291                             &nes->rx_broadcast);
2292         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2293                             &oes->rx_discards, &nes->rx_discards);
2294         /* GLV_REPC not supported */
2295         /* GLV_RMPC not supported */
2296         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2297                             &oes->rx_unknown_protocol,
2298                             &nes->rx_unknown_protocol);
2299         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2300                             vsi->offset_loaded, &oes->tx_bytes,
2301                             &nes->tx_bytes);
2302         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2303                             vsi->offset_loaded, &oes->tx_unicast,
2304                             &nes->tx_unicast);
2305         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2306                             vsi->offset_loaded, &oes->tx_multicast,
2307                             &nes->tx_multicast);
2308         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2309                             vsi->offset_loaded,  &oes->tx_broadcast,
2310                             &nes->tx_broadcast);
2311         /* GLV_TDPC not supported */
2312         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2313                             &oes->tx_errors, &nes->tx_errors);
2314         vsi->offset_loaded = true;
2315
2316         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2317                     vsi->vsi_id);
2318         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2319         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2320         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2321         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2322         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2323         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2324                     nes->rx_unknown_protocol);
2325         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2326         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2327         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2328         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2329         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2330         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2331         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2332                     vsi->vsi_id);
2333 }
2334
2335 static void
2336 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2337 {
2338         unsigned int i;
2339         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2340         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2341
2342         /* Get statistics of struct i40e_eth_stats */
2343         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2344                             I40E_GLPRT_GORCL(hw->port),
2345                             pf->offset_loaded, &os->eth.rx_bytes,
2346                             &ns->eth.rx_bytes);
2347         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2348                             I40E_GLPRT_UPRCL(hw->port),
2349                             pf->offset_loaded, &os->eth.rx_unicast,
2350                             &ns->eth.rx_unicast);
2351         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2352                             I40E_GLPRT_MPRCL(hw->port),
2353                             pf->offset_loaded, &os->eth.rx_multicast,
2354                             &ns->eth.rx_multicast);
2355         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2356                             I40E_GLPRT_BPRCL(hw->port),
2357                             pf->offset_loaded, &os->eth.rx_broadcast,
2358                             &ns->eth.rx_broadcast);
2359         /* Workaround: CRC size should not be included in byte statistics,
2360          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2361          */
2362         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2363                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2364
2365         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2366                             pf->offset_loaded, &os->eth.rx_discards,
2367                             &ns->eth.rx_discards);
2368         /* GLPRT_REPC not supported */
2369         /* GLPRT_RMPC not supported */
2370         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2371                             pf->offset_loaded,
2372                             &os->eth.rx_unknown_protocol,
2373                             &ns->eth.rx_unknown_protocol);
2374         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2375                             I40E_GLPRT_GOTCL(hw->port),
2376                             pf->offset_loaded, &os->eth.tx_bytes,
2377                             &ns->eth.tx_bytes);
2378         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2379                             I40E_GLPRT_UPTCL(hw->port),
2380                             pf->offset_loaded, &os->eth.tx_unicast,
2381                             &ns->eth.tx_unicast);
2382         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2383                             I40E_GLPRT_MPTCL(hw->port),
2384                             pf->offset_loaded, &os->eth.tx_multicast,
2385                             &ns->eth.tx_multicast);
2386         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2387                             I40E_GLPRT_BPTCL(hw->port),
2388                             pf->offset_loaded, &os->eth.tx_broadcast,
2389                             &ns->eth.tx_broadcast);
2390         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2391                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2392         /* GLPRT_TEPC not supported */
2393
2394         /* additional port specific stats */
2395         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2396                             pf->offset_loaded, &os->tx_dropped_link_down,
2397                             &ns->tx_dropped_link_down);
2398         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2399                             pf->offset_loaded, &os->crc_errors,
2400                             &ns->crc_errors);
2401         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2402                             pf->offset_loaded, &os->illegal_bytes,
2403                             &ns->illegal_bytes);
2404         /* GLPRT_ERRBC not supported */
2405         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2406                             pf->offset_loaded, &os->mac_local_faults,
2407                             &ns->mac_local_faults);
2408         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2409                             pf->offset_loaded, &os->mac_remote_faults,
2410                             &ns->mac_remote_faults);
2411         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2412                             pf->offset_loaded, &os->rx_length_errors,
2413                             &ns->rx_length_errors);
2414         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2415                             pf->offset_loaded, &os->link_xon_rx,
2416                             &ns->link_xon_rx);
2417         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2418                             pf->offset_loaded, &os->link_xoff_rx,
2419                             &ns->link_xoff_rx);
2420         for (i = 0; i < 8; i++) {
2421                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2422                                     pf->offset_loaded,
2423                                     &os->priority_xon_rx[i],
2424                                     &ns->priority_xon_rx[i]);
2425                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2426                                     pf->offset_loaded,
2427                                     &os->priority_xoff_rx[i],
2428                                     &ns->priority_xoff_rx[i]);
2429         }
2430         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2431                             pf->offset_loaded, &os->link_xon_tx,
2432                             &ns->link_xon_tx);
2433         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2434                             pf->offset_loaded, &os->link_xoff_tx,
2435                             &ns->link_xoff_tx);
2436         for (i = 0; i < 8; i++) {
2437                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2438                                     pf->offset_loaded,
2439                                     &os->priority_xon_tx[i],
2440                                     &ns->priority_xon_tx[i]);
2441                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2442                                     pf->offset_loaded,
2443                                     &os->priority_xoff_tx[i],
2444                                     &ns->priority_xoff_tx[i]);
2445                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2446                                     pf->offset_loaded,
2447                                     &os->priority_xon_2_xoff[i],
2448                                     &ns->priority_xon_2_xoff[i]);
2449         }
2450         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2451                             I40E_GLPRT_PRC64L(hw->port),
2452                             pf->offset_loaded, &os->rx_size_64,
2453                             &ns->rx_size_64);
2454         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2455                             I40E_GLPRT_PRC127L(hw->port),
2456                             pf->offset_loaded, &os->rx_size_127,
2457                             &ns->rx_size_127);
2458         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2459                             I40E_GLPRT_PRC255L(hw->port),
2460                             pf->offset_loaded, &os->rx_size_255,
2461                             &ns->rx_size_255);
2462         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2463                             I40E_GLPRT_PRC511L(hw->port),
2464                             pf->offset_loaded, &os->rx_size_511,
2465                             &ns->rx_size_511);
2466         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2467                             I40E_GLPRT_PRC1023L(hw->port),
2468                             pf->offset_loaded, &os->rx_size_1023,
2469                             &ns->rx_size_1023);
2470         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2471                             I40E_GLPRT_PRC1522L(hw->port),
2472                             pf->offset_loaded, &os->rx_size_1522,
2473                             &ns->rx_size_1522);
2474         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2475                             I40E_GLPRT_PRC9522L(hw->port),
2476                             pf->offset_loaded, &os->rx_size_big,
2477                             &ns->rx_size_big);
2478         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2479                             pf->offset_loaded, &os->rx_undersize,
2480                             &ns->rx_undersize);
2481         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2482                             pf->offset_loaded, &os->rx_fragments,
2483                             &ns->rx_fragments);
2484         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2485                             pf->offset_loaded, &os->rx_oversize,
2486                             &ns->rx_oversize);
2487         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2488                             pf->offset_loaded, &os->rx_jabber,
2489                             &ns->rx_jabber);
2490         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2491                             I40E_GLPRT_PTC64L(hw->port),
2492                             pf->offset_loaded, &os->tx_size_64,
2493                             &ns->tx_size_64);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2495                             I40E_GLPRT_PTC127L(hw->port),
2496                             pf->offset_loaded, &os->tx_size_127,
2497                             &ns->tx_size_127);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2499                             I40E_GLPRT_PTC255L(hw->port),
2500                             pf->offset_loaded, &os->tx_size_255,
2501                             &ns->tx_size_255);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2503                             I40E_GLPRT_PTC511L(hw->port),
2504                             pf->offset_loaded, &os->tx_size_511,
2505                             &ns->tx_size_511);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2507                             I40E_GLPRT_PTC1023L(hw->port),
2508                             pf->offset_loaded, &os->tx_size_1023,
2509                             &ns->tx_size_1023);
2510         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2511                             I40E_GLPRT_PTC1522L(hw->port),
2512                             pf->offset_loaded, &os->tx_size_1522,
2513                             &ns->tx_size_1522);
2514         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2515                             I40E_GLPRT_PTC9522L(hw->port),
2516                             pf->offset_loaded, &os->tx_size_big,
2517                             &ns->tx_size_big);
2518         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2519                            pf->offset_loaded,
2520                            &os->fd_sb_match, &ns->fd_sb_match);
2521         /* GLPRT_MSPDC not supported */
2522         /* GLPRT_XEC not supported */
2523
2524         pf->offset_loaded = true;
2525
2526         if (pf->main_vsi)
2527                 i40e_update_vsi_stats(pf->main_vsi);
2528 }
2529
2530 /* Get all statistics of a port */
2531 static void
2532 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2533 {
2534         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2537         unsigned i;
2538
2539         /* call read registers - updates values, now write them to struct */
2540         i40e_read_stats_registers(pf, hw);
2541
2542         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2543                         pf->main_vsi->eth_stats.rx_multicast +
2544                         pf->main_vsi->eth_stats.rx_broadcast -
2545                         pf->main_vsi->eth_stats.rx_discards;
2546         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2547                         pf->main_vsi->eth_stats.tx_multicast +
2548                         pf->main_vsi->eth_stats.tx_broadcast;
2549         stats->ibytes   = ns->eth.rx_bytes;
2550         stats->obytes   = ns->eth.tx_bytes;
2551         stats->oerrors  = ns->eth.tx_errors +
2552                         pf->main_vsi->eth_stats.tx_errors;
2553
2554         /* Rx Errors */
2555         stats->imissed  = ns->eth.rx_discards +
2556                         pf->main_vsi->eth_stats.rx_discards;
2557         stats->ierrors  = ns->crc_errors +
2558                         ns->rx_length_errors + ns->rx_undersize +
2559                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2560
2561         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2562         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2563         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2564         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2565         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2566         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2567         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2568                     ns->eth.rx_unknown_protocol);
2569         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2570         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2571         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2572         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2573         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2574         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2575
2576         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2577                     ns->tx_dropped_link_down);
2578         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2579         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2580                     ns->illegal_bytes);
2581         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2582         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2583                     ns->mac_local_faults);
2584         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2585                     ns->mac_remote_faults);
2586         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2587                     ns->rx_length_errors);
2588         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2589         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2590         for (i = 0; i < 8; i++) {
2591                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2592                                 i, ns->priority_xon_rx[i]);
2593                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2594                                 i, ns->priority_xoff_rx[i]);
2595         }
2596         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2597         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2598         for (i = 0; i < 8; i++) {
2599                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2600                                 i, ns->priority_xon_tx[i]);
2601                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2602                                 i, ns->priority_xoff_tx[i]);
2603                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2604                                 i, ns->priority_xon_2_xoff[i]);
2605         }
2606         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2607         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2608         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2609         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2610         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2611         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2612         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2613         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2614         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2615         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2616         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2617         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2618         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2619         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2620         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2621         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2622         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2623         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2624         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2625                         ns->mac_short_packet_dropped);
2626         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2627                     ns->checksum_error);
2628         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2629         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2630 }
2631
2632 /* Reset the statistics */
2633 static void
2634 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2635 {
2636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638
2639         /* Mark PF and VSI stats to update the offset, aka "reset" */
2640         pf->offset_loaded = false;
2641         if (pf->main_vsi)
2642                 pf->main_vsi->offset_loaded = false;
2643
2644         /* read the stats, reading current register values into offset */
2645         i40e_read_stats_registers(pf, hw);
2646 }
2647
2648 static uint32_t
2649 i40e_xstats_calc_num(void)
2650 {
2651         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2652                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2653                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2654 }
2655
2656 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2657                                      struct rte_eth_xstat_name *xstats_names,
2658                                      __rte_unused unsigned limit)
2659 {
2660         unsigned count = 0;
2661         unsigned i, prio;
2662
2663         if (xstats_names == NULL)
2664                 return i40e_xstats_calc_num();
2665
2666         /* Note: limit checked in rte_eth_xstats_names() */
2667
2668         /* Get stats from i40e_eth_stats struct */
2669         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2670                 snprintf(xstats_names[count].name,
2671                          sizeof(xstats_names[count].name),
2672                          "%s", rte_i40e_stats_strings[i].name);
2673                 count++;
2674         }
2675
2676         /* Get individiual stats from i40e_hw_port struct */
2677         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2678                 snprintf(xstats_names[count].name,
2679                         sizeof(xstats_names[count].name),
2680                          "%s", rte_i40e_hw_port_strings[i].name);
2681                 count++;
2682         }
2683
2684         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2685                 for (prio = 0; prio < 8; prio++) {
2686                         snprintf(xstats_names[count].name,
2687                                  sizeof(xstats_names[count].name),
2688                                  "rx_priority%u_%s", prio,
2689                                  rte_i40e_rxq_prio_strings[i].name);
2690                         count++;
2691                 }
2692         }
2693
2694         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2695                 for (prio = 0; prio < 8; prio++) {
2696                         snprintf(xstats_names[count].name,
2697                                  sizeof(xstats_names[count].name),
2698                                  "tx_priority%u_%s", prio,
2699                                  rte_i40e_txq_prio_strings[i].name);
2700                         count++;
2701                 }
2702         }
2703         return count;
2704 }
2705
2706 static int
2707 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2708                     unsigned n)
2709 {
2710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         unsigned i, count, prio;
2713         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2714
2715         count = i40e_xstats_calc_num();
2716         if (n < count)
2717                 return count;
2718
2719         i40e_read_stats_registers(pf, hw);
2720
2721         if (xstats == NULL)
2722                 return 0;
2723
2724         count = 0;
2725
2726         /* Get stats from i40e_eth_stats struct */
2727         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2728                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2729                         rte_i40e_stats_strings[i].offset);
2730                 xstats[count].id = count;
2731                 count++;
2732         }
2733
2734         /* Get individiual stats from i40e_hw_port struct */
2735         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2736                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2737                         rte_i40e_hw_port_strings[i].offset);
2738                 xstats[count].id = count;
2739                 count++;
2740         }
2741
2742         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2743                 for (prio = 0; prio < 8; prio++) {
2744                         xstats[count].value =
2745                                 *(uint64_t *)(((char *)hw_stats) +
2746                                 rte_i40e_rxq_prio_strings[i].offset +
2747                                 (sizeof(uint64_t) * prio));
2748                         xstats[count].id = count;
2749                         count++;
2750                 }
2751         }
2752
2753         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2754                 for (prio = 0; prio < 8; prio++) {
2755                         xstats[count].value =
2756                                 *(uint64_t *)(((char *)hw_stats) +
2757                                 rte_i40e_txq_prio_strings[i].offset +
2758                                 (sizeof(uint64_t) * prio));
2759                         xstats[count].id = count;
2760                         count++;
2761                 }
2762         }
2763
2764         return count;
2765 }
2766
2767 static int
2768 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2769                                  __rte_unused uint16_t queue_id,
2770                                  __rte_unused uint8_t stat_idx,
2771                                  __rte_unused uint8_t is_rx)
2772 {
2773         PMD_INIT_FUNC_TRACE();
2774
2775         return -ENOSYS;
2776 }
2777
2778 static int
2779 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         u32 full_ver;
2783         u8 ver, patch;
2784         u16 build;
2785         int ret;
2786
2787         full_ver = hw->nvm.oem_ver;
2788         ver = (u8)(full_ver >> 24);
2789         build = (u16)((full_ver >> 8) & 0xffff);
2790         patch = (u8)(full_ver & 0xff);
2791
2792         ret = snprintf(fw_version, fw_size,
2793                  "%d.%d%d 0x%08x %d.%d.%d",
2794                  ((hw->nvm.version >> 12) & 0xf),
2795                  ((hw->nvm.version >> 4) & 0xff),
2796                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2797                  ver, build, patch);
2798
2799         ret += 1; /* add the size of '\0' */
2800         if (fw_size < (u32)ret)
2801                 return ret;
2802         else
2803                 return 0;
2804 }
2805
2806 static void
2807 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2808 {
2809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct i40e_vsi *vsi = pf->main_vsi;
2812         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2813
2814         dev_info->pci_dev = pci_dev;
2815         dev_info->max_rx_queues = vsi->nb_qps;
2816         dev_info->max_tx_queues = vsi->nb_qps;
2817         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2818         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2819         dev_info->max_mac_addrs = vsi->max_macaddrs;
2820         dev_info->max_vfs = pci_dev->max_vfs;
2821         dev_info->rx_offload_capa =
2822                 DEV_RX_OFFLOAD_VLAN_STRIP |
2823                 DEV_RX_OFFLOAD_QINQ_STRIP |
2824                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2825                 DEV_RX_OFFLOAD_UDP_CKSUM |
2826                 DEV_RX_OFFLOAD_TCP_CKSUM;
2827         dev_info->tx_offload_capa =
2828                 DEV_TX_OFFLOAD_VLAN_INSERT |
2829                 DEV_TX_OFFLOAD_QINQ_INSERT |
2830                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2831                 DEV_TX_OFFLOAD_UDP_CKSUM |
2832                 DEV_TX_OFFLOAD_TCP_CKSUM |
2833                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2834                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2835                 DEV_TX_OFFLOAD_TCP_TSO |
2836                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2837                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2838                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2839                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2840         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2841                                                 sizeof(uint32_t);
2842         dev_info->reta_size = pf->hash_lut_size;
2843         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2844
2845         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2846                 .rx_thresh = {
2847                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2848                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2849                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2850                 },
2851                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2852                 .rx_drop_en = 0,
2853         };
2854
2855         dev_info->default_txconf = (struct rte_eth_txconf) {
2856                 .tx_thresh = {
2857                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2858                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2859                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2860                 },
2861                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2862                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2863                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2864                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2865         };
2866
2867         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2868                 .nb_max = I40E_MAX_RING_DESC,
2869                 .nb_min = I40E_MIN_RING_DESC,
2870                 .nb_align = I40E_ALIGN_RING_DESC,
2871         };
2872
2873         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2874                 .nb_max = I40E_MAX_RING_DESC,
2875                 .nb_min = I40E_MIN_RING_DESC,
2876                 .nb_align = I40E_ALIGN_RING_DESC,
2877                 .nb_seg_max = I40E_TX_MAX_SEG,
2878                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2879         };
2880
2881         if (pf->flags & I40E_FLAG_VMDQ) {
2882                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2883                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2884                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2885                                                 pf->max_nb_vmdq_vsi;
2886                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2887                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2888                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2889         }
2890
2891         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2892                 /* For XL710 */
2893                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2894         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2895                 /* For XXV710 */
2896                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2897         else
2898                 /* For X710 */
2899                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2900 }
2901
2902 static int
2903 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2904 {
2905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2906         struct i40e_vsi *vsi = pf->main_vsi;
2907         PMD_INIT_FUNC_TRACE();
2908
2909         if (on)
2910                 return i40e_vsi_add_vlan(vsi, vlan_id);
2911         else
2912                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2913 }
2914
2915 static int
2916 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2917                    enum rte_vlan_type vlan_type,
2918                    uint16_t tpid)
2919 {
2920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint64_t reg_r = 0, reg_w = 0;
2922         uint16_t reg_id = 0;
2923         int ret = 0;
2924         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2925
2926         switch (vlan_type) {
2927         case ETH_VLAN_TYPE_OUTER:
2928                 if (qinq)
2929                         reg_id = 2;
2930                 else
2931                         reg_id = 3;
2932                 break;
2933         case ETH_VLAN_TYPE_INNER:
2934                 if (qinq)
2935                         reg_id = 3;
2936                 else {
2937                         ret = -EINVAL;
2938                         PMD_DRV_LOG(ERR,
2939                                 "Unsupported vlan type in single vlan.\n");
2940                         return ret;
2941                 }
2942                 break;
2943         default:
2944                 ret = -EINVAL;
2945                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2946                 return ret;
2947         }
2948         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2949                                           &reg_r, NULL);
2950         if (ret != I40E_SUCCESS) {
2951                 PMD_DRV_LOG(ERR,
2952                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2953                            reg_id);
2954                 ret = -EIO;
2955                 return ret;
2956         }
2957         PMD_DRV_LOG(DEBUG,
2958                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2959                 reg_id, reg_r);
2960
2961         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2962         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2963         if (reg_r == reg_w) {
2964                 ret = 0;
2965                 PMD_DRV_LOG(DEBUG, "No need to write");
2966                 return ret;
2967         }
2968
2969         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2970                                            reg_w, NULL);
2971         if (ret != I40E_SUCCESS) {
2972                 ret = -EIO;
2973                 PMD_DRV_LOG(ERR,
2974                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2975                         reg_id);
2976                 return ret;
2977         }
2978         PMD_DRV_LOG(DEBUG,
2979                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2980                 reg_w, reg_id);
2981
2982         return ret;
2983 }
2984
2985 static void
2986 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2987 {
2988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2989         struct i40e_vsi *vsi = pf->main_vsi;
2990
2991         if (mask & ETH_VLAN_FILTER_MASK) {
2992                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2993                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2994                 else
2995                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2996         }
2997
2998         if (mask & ETH_VLAN_STRIP_MASK) {
2999                 /* Enable or disable VLAN stripping */
3000                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3001                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3002                 else
3003                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3004         }
3005
3006         if (mask & ETH_VLAN_EXTEND_MASK) {
3007                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3008                         i40e_vsi_config_double_vlan(vsi, TRUE);
3009                         /* Set global registers with default ether type value */
3010                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3011                                            ETHER_TYPE_VLAN);
3012                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3013                                            ETHER_TYPE_VLAN);
3014                 }
3015                 else
3016                         i40e_vsi_config_double_vlan(vsi, FALSE);
3017         }
3018 }
3019
3020 static void
3021 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3022                           __rte_unused uint16_t queue,
3023                           __rte_unused int on)
3024 {
3025         PMD_INIT_FUNC_TRACE();
3026 }
3027
3028 static int
3029 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3030 {
3031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032         struct i40e_vsi *vsi = pf->main_vsi;
3033         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3034         struct i40e_vsi_vlan_pvid_info info;
3035
3036         memset(&info, 0, sizeof(info));
3037         info.on = on;
3038         if (info.on)
3039                 info.config.pvid = pvid;
3040         else {
3041                 info.config.reject.tagged =
3042                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3043                 info.config.reject.untagged =
3044                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3045         }
3046
3047         return i40e_vsi_vlan_pvid_set(vsi, &info);
3048 }
3049
3050 static int
3051 i40e_dev_led_on(struct rte_eth_dev *dev)
3052 {
3053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         uint32_t mode = i40e_led_get(hw);
3055
3056         if (mode == 0)
3057                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3058
3059         return 0;
3060 }
3061
3062 static int
3063 i40e_dev_led_off(struct rte_eth_dev *dev)
3064 {
3065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         uint32_t mode = i40e_led_get(hw);
3067
3068         if (mode != 0)
3069                 i40e_led_set(hw, 0, false);
3070
3071         return 0;
3072 }
3073
3074 static int
3075 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3076 {
3077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3079
3080         fc_conf->pause_time = pf->fc_conf.pause_time;
3081         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3082         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3083
3084          /* Return current mode according to actual setting*/
3085         switch (hw->fc.current_mode) {
3086         case I40E_FC_FULL:
3087                 fc_conf->mode = RTE_FC_FULL;
3088                 break;
3089         case I40E_FC_TX_PAUSE:
3090                 fc_conf->mode = RTE_FC_TX_PAUSE;
3091                 break;
3092         case I40E_FC_RX_PAUSE:
3093                 fc_conf->mode = RTE_FC_RX_PAUSE;
3094                 break;
3095         case I40E_FC_NONE:
3096         default:
3097                 fc_conf->mode = RTE_FC_NONE;
3098         };
3099
3100         return 0;
3101 }
3102
3103 static int
3104 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3105 {
3106         uint32_t mflcn_reg, fctrl_reg, reg;
3107         uint32_t max_high_water;
3108         uint8_t i, aq_failure;
3109         int err;
3110         struct i40e_hw *hw;
3111         struct i40e_pf *pf;
3112         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3113                 [RTE_FC_NONE] = I40E_FC_NONE,
3114                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3115                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3116                 [RTE_FC_FULL] = I40E_FC_FULL
3117         };
3118
3119         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3120
3121         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3122         if ((fc_conf->high_water > max_high_water) ||
3123                         (fc_conf->high_water < fc_conf->low_water)) {
3124                 PMD_INIT_LOG(ERR,
3125                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3126                         max_high_water);
3127                 return -EINVAL;
3128         }
3129
3130         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3133
3134         pf->fc_conf.pause_time = fc_conf->pause_time;
3135         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3136         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3137
3138         PMD_INIT_FUNC_TRACE();
3139
3140         /* All the link flow control related enable/disable register
3141          * configuration is handle by the F/W
3142          */
3143         err = i40e_set_fc(hw, &aq_failure, true);
3144         if (err < 0)
3145                 return -ENOSYS;
3146
3147         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3148                 /* Configure flow control refresh threshold,
3149                  * the value for stat_tx_pause_refresh_timer[8]
3150                  * is used for global pause operation.
3151                  */
3152
3153                 I40E_WRITE_REG(hw,
3154                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3155                                pf->fc_conf.pause_time);
3156
3157                 /* configure the timer value included in transmitted pause
3158                  * frame,
3159                  * the value for stat_tx_pause_quanta[8] is used for global
3160                  * pause operation
3161                  */
3162                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3163                                pf->fc_conf.pause_time);
3164
3165                 fctrl_reg = I40E_READ_REG(hw,
3166                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3167
3168                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3169                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3170                 else
3171                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3172
3173                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3174                                fctrl_reg);
3175         } else {
3176                 /* Configure pause time (2 TCs per register) */
3177                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3178                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3179                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3180
3181                 /* Configure flow control refresh threshold value */
3182                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3183                                pf->fc_conf.pause_time / 2);
3184
3185                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3186
3187                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3188                  *depending on configuration
3189                  */
3190                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3191                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3192                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3193                 } else {
3194                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3195                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3196                 }
3197
3198                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3199         }
3200
3201         /* config the water marker both based on the packets and bytes */
3202         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3203                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3204                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3205         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3206                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3207                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3208         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3209                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3210                        << I40E_KILOSHIFT);
3211         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3212                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3213                        << I40E_KILOSHIFT);
3214
3215         I40E_WRITE_FLUSH(hw);
3216
3217         return 0;
3218 }
3219
3220 static int
3221 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3222                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3223 {
3224         PMD_INIT_FUNC_TRACE();
3225
3226         return -ENOSYS;
3227 }
3228
3229 /* Add a MAC address, and update filters */
3230 static void
3231 i40e_macaddr_add(struct rte_eth_dev *dev,
3232                  struct ether_addr *mac_addr,
3233                  __rte_unused uint32_t index,
3234                  uint32_t pool)
3235 {
3236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         struct i40e_mac_filter_info mac_filter;
3238         struct i40e_vsi *vsi;
3239         int ret;
3240
3241         /* If VMDQ not enabled or configured, return */
3242         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3243                           !pf->nb_cfg_vmdq_vsi)) {
3244                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3245                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3246                         pool);
3247                 return;
3248         }
3249
3250         if (pool > pf->nb_cfg_vmdq_vsi) {
3251                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3252                                 pool, pf->nb_cfg_vmdq_vsi);
3253                 return;
3254         }
3255
3256         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3257         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3258                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3259         else
3260                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3261
3262         if (pool == 0)
3263                 vsi = pf->main_vsi;
3264         else
3265                 vsi = pf->vmdq[pool - 1].vsi;
3266
3267         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3268         if (ret != I40E_SUCCESS) {
3269                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3270                 return;
3271         }
3272 }
3273
3274 /* Remove a MAC address, and update filters */
3275 static void
3276 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3277 {
3278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279         struct i40e_vsi *vsi;
3280         struct rte_eth_dev_data *data = dev->data;
3281         struct ether_addr *macaddr;
3282         int ret;
3283         uint32_t i;
3284         uint64_t pool_sel;
3285
3286         macaddr = &(data->mac_addrs[index]);
3287
3288         pool_sel = dev->data->mac_pool_sel[index];
3289
3290         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3291                 if (pool_sel & (1ULL << i)) {
3292                         if (i == 0)
3293                                 vsi = pf->main_vsi;
3294                         else {
3295                                 /* No VMDQ pool enabled or configured */
3296                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3297                                         (i > pf->nb_cfg_vmdq_vsi)) {
3298                                         PMD_DRV_LOG(ERR,
3299                                                 "No VMDQ pool enabled/configured");
3300                                         return;
3301                                 }
3302                                 vsi = pf->vmdq[i - 1].vsi;
3303                         }
3304                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3305
3306                         if (ret) {
3307                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3308                                 return;
3309                         }
3310                 }
3311         }
3312 }
3313
3314 /* Set perfect match or hash match of MAC and VLAN for a VF */
3315 static int
3316 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3317                  struct rte_eth_mac_filter *filter,
3318                  bool add)
3319 {
3320         struct i40e_hw *hw;
3321         struct i40e_mac_filter_info mac_filter;
3322         struct ether_addr old_mac;
3323         struct ether_addr *new_mac;
3324         struct i40e_pf_vf *vf = NULL;
3325         uint16_t vf_id;
3326         int ret;
3327
3328         if (pf == NULL) {
3329                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3330                 return -EINVAL;
3331         }
3332         hw = I40E_PF_TO_HW(pf);
3333
3334         if (filter == NULL) {
3335                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3336                 return -EINVAL;
3337         }
3338
3339         new_mac = &filter->mac_addr;
3340
3341         if (is_zero_ether_addr(new_mac)) {
3342                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3343                 return -EINVAL;
3344         }
3345
3346         vf_id = filter->dst_id;
3347
3348         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3349                 PMD_DRV_LOG(ERR, "Invalid argument.");
3350                 return -EINVAL;
3351         }
3352         vf = &pf->vfs[vf_id];
3353
3354         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3355                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3356                 return -EINVAL;
3357         }
3358
3359         if (add) {
3360                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3361                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3362                                 ETHER_ADDR_LEN);
3363                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3364                                  ETHER_ADDR_LEN);
3365
3366                 mac_filter.filter_type = filter->filter_type;
3367                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3368                 if (ret != I40E_SUCCESS) {
3369                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3370                         return -1;
3371                 }
3372                 ether_addr_copy(new_mac, &pf->dev_addr);
3373         } else {
3374                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3375                                 ETHER_ADDR_LEN);
3376                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3377                 if (ret != I40E_SUCCESS) {
3378                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3379                         return -1;
3380                 }
3381
3382                 /* Clear device address as it has been removed */
3383                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3384                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3385         }
3386
3387         return 0;
3388 }
3389
3390 /* MAC filter handle */
3391 static int
3392 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3393                 void *arg)
3394 {
3395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396         struct rte_eth_mac_filter *filter;
3397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3398         int ret = I40E_NOT_SUPPORTED;
3399
3400         filter = (struct rte_eth_mac_filter *)(arg);
3401
3402         switch (filter_op) {
3403         case RTE_ETH_FILTER_NOP:
3404                 ret = I40E_SUCCESS;
3405                 break;
3406         case RTE_ETH_FILTER_ADD:
3407                 i40e_pf_disable_irq0(hw);
3408                 if (filter->is_vf)
3409                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3410                 i40e_pf_enable_irq0(hw);
3411                 break;
3412         case RTE_ETH_FILTER_DELETE:
3413                 i40e_pf_disable_irq0(hw);
3414                 if (filter->is_vf)
3415                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3416                 i40e_pf_enable_irq0(hw);
3417                 break;
3418         default:
3419                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3420                 ret = I40E_ERR_PARAM;
3421                 break;
3422         }
3423
3424         return ret;
3425 }
3426
3427 static int
3428 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3429 {
3430         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3431         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3432         int ret;
3433
3434         if (!lut)
3435                 return -EINVAL;
3436
3437         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3438                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3439                                           lut, lut_size);
3440                 if (ret) {
3441                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3442                         return ret;
3443                 }
3444         } else {
3445                 uint32_t *lut_dw = (uint32_t *)lut;
3446                 uint16_t i, lut_size_dw = lut_size / 4;
3447
3448                 for (i = 0; i < lut_size_dw; i++)
3449                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3450         }
3451
3452         return 0;
3453 }
3454
3455 static int
3456 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3457 {
3458         struct i40e_pf *pf;
3459         struct i40e_hw *hw;
3460         int ret;
3461
3462         if (!vsi || !lut)
3463                 return -EINVAL;
3464
3465         pf = I40E_VSI_TO_PF(vsi);
3466         hw = I40E_VSI_TO_HW(vsi);
3467
3468         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3469                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3470                                           lut, lut_size);
3471                 if (ret) {
3472                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3473                         return ret;
3474                 }
3475         } else {
3476                 uint32_t *lut_dw = (uint32_t *)lut;
3477                 uint16_t i, lut_size_dw = lut_size / 4;
3478
3479                 for (i = 0; i < lut_size_dw; i++)
3480                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3481                 I40E_WRITE_FLUSH(hw);
3482         }
3483
3484         return 0;
3485 }
3486
3487 static int
3488 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3489                          struct rte_eth_rss_reta_entry64 *reta_conf,
3490                          uint16_t reta_size)
3491 {
3492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493         uint16_t i, lut_size = pf->hash_lut_size;
3494         uint16_t idx, shift;
3495         uint8_t *lut;
3496         int ret;
3497
3498         if (reta_size != lut_size ||
3499                 reta_size > ETH_RSS_RETA_SIZE_512) {
3500                 PMD_DRV_LOG(ERR,
3501                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3502                         reta_size, lut_size);
3503                 return -EINVAL;
3504         }
3505
3506         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3507         if (!lut) {
3508                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3509                 return -ENOMEM;
3510         }
3511         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3512         if (ret)
3513                 goto out;
3514         for (i = 0; i < reta_size; i++) {
3515                 idx = i / RTE_RETA_GROUP_SIZE;
3516                 shift = i % RTE_RETA_GROUP_SIZE;
3517                 if (reta_conf[idx].mask & (1ULL << shift))
3518                         lut[i] = reta_conf[idx].reta[shift];
3519         }
3520         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3521
3522 out:
3523         rte_free(lut);
3524
3525         return ret;
3526 }
3527
3528 static int
3529 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3530                         struct rte_eth_rss_reta_entry64 *reta_conf,
3531                         uint16_t reta_size)
3532 {
3533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534         uint16_t i, lut_size = pf->hash_lut_size;
3535         uint16_t idx, shift;
3536         uint8_t *lut;
3537         int ret;
3538
3539         if (reta_size != lut_size ||
3540                 reta_size > ETH_RSS_RETA_SIZE_512) {
3541                 PMD_DRV_LOG(ERR,
3542                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3543                         reta_size, lut_size);
3544                 return -EINVAL;
3545         }
3546
3547         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3548         if (!lut) {
3549                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3550                 return -ENOMEM;
3551         }
3552
3553         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3554         if (ret)
3555                 goto out;
3556         for (i = 0; i < reta_size; i++) {
3557                 idx = i / RTE_RETA_GROUP_SIZE;
3558                 shift = i % RTE_RETA_GROUP_SIZE;
3559                 if (reta_conf[idx].mask & (1ULL << shift))
3560                         reta_conf[idx].reta[shift] = lut[i];
3561         }
3562
3563 out:
3564         rte_free(lut);
3565
3566         return ret;
3567 }
3568
3569 /**
3570  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3571  * @hw:   pointer to the HW structure
3572  * @mem:  pointer to mem struct to fill out
3573  * @size: size of memory requested
3574  * @alignment: what to align the allocation to
3575  **/
3576 enum i40e_status_code
3577 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3578                         struct i40e_dma_mem *mem,
3579                         u64 size,
3580                         u32 alignment)
3581 {
3582         const struct rte_memzone *mz = NULL;
3583         char z_name[RTE_MEMZONE_NAMESIZE];
3584
3585         if (!mem)
3586                 return I40E_ERR_PARAM;
3587
3588         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3589         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3590                                          alignment, RTE_PGSIZE_2M);
3591         if (!mz)
3592                 return I40E_ERR_NO_MEMORY;
3593
3594         mem->size = size;
3595         mem->va = mz->addr;
3596         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3597         mem->zone = (const void *)mz;
3598         PMD_DRV_LOG(DEBUG,
3599                 "memzone %s allocated with physical address: %"PRIu64,
3600                 mz->name, mem->pa);
3601
3602         return I40E_SUCCESS;
3603 }
3604
3605 /**
3606  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3607  * @hw:   pointer to the HW structure
3608  * @mem:  ptr to mem struct to free
3609  **/
3610 enum i40e_status_code
3611 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3612                     struct i40e_dma_mem *mem)
3613 {
3614         if (!mem)
3615                 return I40E_ERR_PARAM;
3616
3617         PMD_DRV_LOG(DEBUG,
3618                 "memzone %s to be freed with physical address: %"PRIu64,
3619                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3620         rte_memzone_free((const struct rte_memzone *)mem->zone);
3621         mem->zone = NULL;
3622         mem->va = NULL;
3623         mem->pa = (u64)0;
3624
3625         return I40E_SUCCESS;
3626 }
3627
3628 /**
3629  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3630  * @hw:   pointer to the HW structure
3631  * @mem:  pointer to mem struct to fill out
3632  * @size: size of memory requested
3633  **/
3634 enum i40e_status_code
3635 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3636                          struct i40e_virt_mem *mem,
3637                          u32 size)
3638 {
3639         if (!mem)
3640                 return I40E_ERR_PARAM;
3641
3642         mem->size = size;
3643         mem->va = rte_zmalloc("i40e", size, 0);
3644
3645         if (mem->va)
3646                 return I40E_SUCCESS;
3647         else
3648                 return I40E_ERR_NO_MEMORY;
3649 }
3650
3651 /**
3652  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3653  * @hw:   pointer to the HW structure
3654  * @mem:  pointer to mem struct to free
3655  **/
3656 enum i40e_status_code
3657 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3658                      struct i40e_virt_mem *mem)
3659 {
3660         if (!mem)
3661                 return I40E_ERR_PARAM;
3662
3663         rte_free(mem->va);
3664         mem->va = NULL;
3665
3666         return I40E_SUCCESS;
3667 }
3668
3669 void
3670 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3671 {
3672         rte_spinlock_init(&sp->spinlock);
3673 }
3674
3675 void
3676 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3677 {
3678         rte_spinlock_lock(&sp->spinlock);
3679 }
3680
3681 void
3682 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3683 {
3684         rte_spinlock_unlock(&sp->spinlock);
3685 }
3686
3687 void
3688 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3689 {
3690         return;
3691 }
3692
3693 /**
3694  * Get the hardware capabilities, which will be parsed
3695  * and saved into struct i40e_hw.
3696  */
3697 static int
3698 i40e_get_cap(struct i40e_hw *hw)
3699 {
3700         struct i40e_aqc_list_capabilities_element_resp *buf;
3701         uint16_t len, size = 0;
3702         int ret;
3703
3704         /* Calculate a huge enough buff for saving response data temporarily */
3705         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3706                                                 I40E_MAX_CAP_ELE_NUM;
3707         buf = rte_zmalloc("i40e", len, 0);
3708         if (!buf) {
3709                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3710                 return I40E_ERR_NO_MEMORY;
3711         }
3712
3713         /* Get, parse the capabilities and save it to hw */
3714         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3715                         i40e_aqc_opc_list_func_capabilities, NULL);
3716         if (ret != I40E_SUCCESS)
3717                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3718
3719         /* Free the temporary buffer after being used */
3720         rte_free(buf);
3721
3722         return ret;
3723 }
3724
3725 static int
3726 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3727 {
3728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3730         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3731         uint16_t qp_count = 0, vsi_count = 0;
3732
3733         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3734                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3735                 return -EINVAL;
3736         }
3737         /* Add the parameter init for LFC */
3738         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3739         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3740         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3741
3742         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3743         pf->max_num_vsi = hw->func_caps.num_vsis;
3744         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3745         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3746         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3747
3748         /* FDir queue/VSI allocation */
3749         pf->fdir_qp_offset = 0;
3750         if (hw->func_caps.fd) {
3751                 pf->flags |= I40E_FLAG_FDIR;
3752                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3753         } else {
3754                 pf->fdir_nb_qps = 0;
3755         }
3756         qp_count += pf->fdir_nb_qps;
3757         vsi_count += 1;
3758
3759         /* LAN queue/VSI allocation */
3760         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3761         if (!hw->func_caps.rss) {
3762                 pf->lan_nb_qps = 1;
3763         } else {
3764                 pf->flags |= I40E_FLAG_RSS;
3765                 if (hw->mac.type == I40E_MAC_X722)
3766                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3767                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3768         }
3769         qp_count += pf->lan_nb_qps;
3770         vsi_count += 1;
3771
3772         /* VF queue/VSI allocation */
3773         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3774         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3775                 pf->flags |= I40E_FLAG_SRIOV;
3776                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3777                 pf->vf_num = pci_dev->max_vfs;
3778                 PMD_DRV_LOG(DEBUG,
3779                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3780                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3781         } else {
3782                 pf->vf_nb_qps = 0;
3783                 pf->vf_num = 0;
3784         }
3785         qp_count += pf->vf_nb_qps * pf->vf_num;
3786         vsi_count += pf->vf_num;
3787
3788         /* VMDq queue/VSI allocation */
3789         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3790         pf->vmdq_nb_qps = 0;
3791         pf->max_nb_vmdq_vsi = 0;
3792         if (hw->func_caps.vmdq) {
3793                 if (qp_count < hw->func_caps.num_tx_qp &&
3794                         vsi_count < hw->func_caps.num_vsis) {
3795                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3796                                 qp_count) / pf->vmdq_nb_qp_max;
3797
3798                         /* Limit the maximum number of VMDq vsi to the maximum
3799                          * ethdev can support
3800                          */
3801                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3802                                 hw->func_caps.num_vsis - vsi_count);
3803                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3804                                 ETH_64_POOLS);
3805                         if (pf->max_nb_vmdq_vsi) {
3806                                 pf->flags |= I40E_FLAG_VMDQ;
3807                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3808                                 PMD_DRV_LOG(DEBUG,
3809                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3810                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3811                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3812                         } else {
3813                                 PMD_DRV_LOG(INFO,
3814                                         "No enough queues left for VMDq");
3815                         }
3816                 } else {
3817                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3818                 }
3819         }
3820         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3821         vsi_count += pf->max_nb_vmdq_vsi;
3822
3823         if (hw->func_caps.dcb)
3824                 pf->flags |= I40E_FLAG_DCB;
3825
3826         if (qp_count > hw->func_caps.num_tx_qp) {
3827                 PMD_DRV_LOG(ERR,
3828                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3829                         qp_count, hw->func_caps.num_tx_qp);
3830                 return -EINVAL;
3831         }
3832         if (vsi_count > hw->func_caps.num_vsis) {
3833                 PMD_DRV_LOG(ERR,
3834                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3835                         vsi_count, hw->func_caps.num_vsis);
3836                 return -EINVAL;
3837         }
3838
3839         return 0;
3840 }
3841
3842 static int
3843 i40e_pf_get_switch_config(struct i40e_pf *pf)
3844 {
3845         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3846         struct i40e_aqc_get_switch_config_resp *switch_config;
3847         struct i40e_aqc_switch_config_element_resp *element;
3848         uint16_t start_seid = 0, num_reported;
3849         int ret;
3850
3851         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3852                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3853         if (!switch_config) {
3854                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3855                 return -ENOMEM;
3856         }
3857
3858         /* Get the switch configurations */
3859         ret = i40e_aq_get_switch_config(hw, switch_config,
3860                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3861         if (ret != I40E_SUCCESS) {
3862                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3863                 goto fail;
3864         }
3865         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3866         if (num_reported != 1) { /* The number should be 1 */
3867                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3868                 goto fail;
3869         }
3870
3871         /* Parse the switch configuration elements */
3872         element = &(switch_config->element[0]);
3873         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3874                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3875                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3876         } else
3877                 PMD_DRV_LOG(INFO, "Unknown element type");
3878
3879 fail:
3880         rte_free(switch_config);
3881
3882         return ret;
3883 }
3884
3885 static int
3886 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3887                         uint32_t num)
3888 {
3889         struct pool_entry *entry;
3890
3891         if (pool == NULL || num == 0)
3892                 return -EINVAL;
3893
3894         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3895         if (entry == NULL) {
3896                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3897                 return -ENOMEM;
3898         }
3899
3900         /* queue heap initialize */
3901         pool->num_free = num;
3902         pool->num_alloc = 0;
3903         pool->base = base;
3904         LIST_INIT(&pool->alloc_list);
3905         LIST_INIT(&pool->free_list);
3906
3907         /* Initialize element  */
3908         entry->base = 0;
3909         entry->len = num;
3910
3911         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3912         return 0;
3913 }
3914
3915 static void
3916 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3917 {
3918         struct pool_entry *entry, *next_entry;
3919
3920         if (pool == NULL)
3921                 return;
3922
3923         for (entry = LIST_FIRST(&pool->alloc_list);
3924                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3925                         entry = next_entry) {
3926                 LIST_REMOVE(entry, next);
3927                 rte_free(entry);
3928         }
3929
3930         for (entry = LIST_FIRST(&pool->free_list);
3931                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3932                         entry = next_entry) {
3933                 LIST_REMOVE(entry, next);
3934                 rte_free(entry);
3935         }
3936
3937         pool->num_free = 0;
3938         pool->num_alloc = 0;
3939         pool->base = 0;
3940         LIST_INIT(&pool->alloc_list);
3941         LIST_INIT(&pool->free_list);
3942 }
3943
3944 static int
3945 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3946                        uint32_t base)
3947 {
3948         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3949         uint32_t pool_offset;
3950         int insert;
3951
3952         if (pool == NULL) {
3953                 PMD_DRV_LOG(ERR, "Invalid parameter");
3954                 return -EINVAL;
3955         }
3956
3957         pool_offset = base - pool->base;
3958         /* Lookup in alloc list */
3959         LIST_FOREACH(entry, &pool->alloc_list, next) {
3960                 if (entry->base == pool_offset) {
3961                         valid_entry = entry;
3962                         LIST_REMOVE(entry, next);
3963                         break;
3964                 }
3965         }
3966
3967         /* Not find, return */
3968         if (valid_entry == NULL) {
3969                 PMD_DRV_LOG(ERR, "Failed to find entry");
3970                 return -EINVAL;
3971         }
3972
3973         /**
3974          * Found it, move it to free list  and try to merge.
3975          * In order to make merge easier, always sort it by qbase.
3976          * Find adjacent prev and last entries.
3977          */
3978         prev = next = NULL;
3979         LIST_FOREACH(entry, &pool->free_list, next) {
3980                 if (entry->base > valid_entry->base) {
3981                         next = entry;
3982                         break;
3983                 }
3984                 prev = entry;
3985         }
3986
3987         insert = 0;
3988         /* Try to merge with next one*/
3989         if (next != NULL) {
3990                 /* Merge with next one */
3991                 if (valid_entry->base + valid_entry->len == next->base) {
3992                         next->base = valid_entry->base;
3993                         next->len += valid_entry->len;
3994                         rte_free(valid_entry);
3995                         valid_entry = next;
3996                         insert = 1;
3997                 }
3998         }
3999
4000         if (prev != NULL) {
4001                 /* Merge with previous one */
4002                 if (prev->base + prev->len == valid_entry->base) {
4003                         prev->len += valid_entry->len;
4004                         /* If it merge with next one, remove next node */
4005                         if (insert == 1) {
4006                                 LIST_REMOVE(valid_entry, next);
4007                                 rte_free(valid_entry);
4008                         } else {
4009                                 rte_free(valid_entry);
4010                                 insert = 1;
4011                         }
4012                 }
4013         }
4014
4015         /* Not find any entry to merge, insert */
4016         if (insert == 0) {
4017                 if (prev != NULL)
4018                         LIST_INSERT_AFTER(prev, valid_entry, next);
4019                 else if (next != NULL)
4020                         LIST_INSERT_BEFORE(next, valid_entry, next);
4021                 else /* It's empty list, insert to head */
4022                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4023         }
4024
4025         pool->num_free += valid_entry->len;
4026         pool->num_alloc -= valid_entry->len;
4027
4028         return 0;
4029 }
4030
4031 static int
4032 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4033                        uint16_t num)
4034 {
4035         struct pool_entry *entry, *valid_entry;
4036
4037         if (pool == NULL || num == 0) {
4038                 PMD_DRV_LOG(ERR, "Invalid parameter");
4039                 return -EINVAL;
4040         }
4041
4042         if (pool->num_free < num) {
4043                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4044                             num, pool->num_free);
4045                 return -ENOMEM;
4046         }
4047
4048         valid_entry = NULL;
4049         /* Lookup  in free list and find most fit one */
4050         LIST_FOREACH(entry, &pool->free_list, next) {
4051                 if (entry->len >= num) {
4052                         /* Find best one */
4053                         if (entry->len == num) {
4054                                 valid_entry = entry;
4055                                 break;
4056                         }
4057                         if (valid_entry == NULL || valid_entry->len > entry->len)
4058                                 valid_entry = entry;
4059                 }
4060         }
4061
4062         /* Not find one to satisfy the request, return */
4063         if (valid_entry == NULL) {
4064                 PMD_DRV_LOG(ERR, "No valid entry found");
4065                 return -ENOMEM;
4066         }
4067         /**
4068          * The entry have equal queue number as requested,
4069          * remove it from alloc_list.
4070          */
4071         if (valid_entry->len == num) {
4072                 LIST_REMOVE(valid_entry, next);
4073         } else {
4074                 /**
4075                  * The entry have more numbers than requested,
4076                  * create a new entry for alloc_list and minus its
4077                  * queue base and number in free_list.
4078                  */
4079                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4080                 if (entry == NULL) {
4081                         PMD_DRV_LOG(ERR,
4082                                 "Failed to allocate memory for resource pool");
4083                         return -ENOMEM;
4084                 }
4085                 entry->base = valid_entry->base;
4086                 entry->len = num;
4087                 valid_entry->base += num;
4088                 valid_entry->len -= num;
4089                 valid_entry = entry;
4090         }
4091
4092         /* Insert it into alloc list, not sorted */
4093         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4094
4095         pool->num_free -= valid_entry->len;
4096         pool->num_alloc += valid_entry->len;
4097
4098         return valid_entry->base + pool->base;
4099 }
4100
4101 /**
4102  * bitmap_is_subset - Check whether src2 is subset of src1
4103  **/
4104 static inline int
4105 bitmap_is_subset(uint8_t src1, uint8_t src2)
4106 {
4107         return !((src1 ^ src2) & src2);
4108 }
4109
4110 static enum i40e_status_code
4111 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4112 {
4113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4114
4115         /* If DCB is not supported, only default TC is supported */
4116         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4117                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4118                 return I40E_NOT_SUPPORTED;
4119         }
4120
4121         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4122                 PMD_DRV_LOG(ERR,
4123                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4124                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4125                 return I40E_NOT_SUPPORTED;
4126         }
4127         return I40E_SUCCESS;
4128 }
4129
4130 int
4131 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4132                                 struct i40e_vsi_vlan_pvid_info *info)
4133 {
4134         struct i40e_hw *hw;
4135         struct i40e_vsi_context ctxt;
4136         uint8_t vlan_flags = 0;
4137         int ret;
4138
4139         if (vsi == NULL || info == NULL) {
4140                 PMD_DRV_LOG(ERR, "invalid parameters");
4141                 return I40E_ERR_PARAM;
4142         }
4143
4144         if (info->on) {
4145                 vsi->info.pvid = info->config.pvid;
4146                 /**
4147                  * If insert pvid is enabled, only tagged pkts are
4148                  * allowed to be sent out.
4149                  */
4150                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4151                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4152         } else {
4153                 vsi->info.pvid = 0;
4154                 if (info->config.reject.tagged == 0)
4155                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4156
4157                 if (info->config.reject.untagged == 0)
4158                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4159         }
4160         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4161                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4162         vsi->info.port_vlan_flags |= vlan_flags;
4163         vsi->info.valid_sections =
4164                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4165         memset(&ctxt, 0, sizeof(ctxt));
4166         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4167         ctxt.seid = vsi->seid;
4168
4169         hw = I40E_VSI_TO_HW(vsi);
4170         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4171         if (ret != I40E_SUCCESS)
4172                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4173
4174         return ret;
4175 }
4176
4177 static int
4178 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4179 {
4180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4181         int i, ret;
4182         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4183
4184         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4185         if (ret != I40E_SUCCESS)
4186                 return ret;
4187
4188         if (!vsi->seid) {
4189                 PMD_DRV_LOG(ERR, "seid not valid");
4190                 return -EINVAL;
4191         }
4192
4193         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4194         tc_bw_data.tc_valid_bits = enabled_tcmap;
4195         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4196                 tc_bw_data.tc_bw_credits[i] =
4197                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4198
4199         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4200         if (ret != I40E_SUCCESS) {
4201                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4202                 return ret;
4203         }
4204
4205         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4206                                         sizeof(vsi->info.qs_handle));
4207         return I40E_SUCCESS;
4208 }
4209
4210 static enum i40e_status_code
4211 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4212                                  struct i40e_aqc_vsi_properties_data *info,
4213                                  uint8_t enabled_tcmap)
4214 {
4215         enum i40e_status_code ret;
4216         int i, total_tc = 0;
4217         uint16_t qpnum_per_tc, bsf, qp_idx;
4218
4219         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4220         if (ret != I40E_SUCCESS)
4221                 return ret;
4222
4223         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4224                 if (enabled_tcmap & (1 << i))
4225                         total_tc++;
4226         vsi->enabled_tc = enabled_tcmap;
4227
4228         /* Number of queues per enabled TC */
4229         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4230         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4231         bsf = rte_bsf32(qpnum_per_tc);
4232
4233         /* Adjust the queue number to actual queues that can be applied */
4234         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4235                 vsi->nb_qps = qpnum_per_tc * total_tc;
4236
4237         /**
4238          * Configure TC and queue mapping parameters, for enabled TC,
4239          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4240          * default queue will serve it.
4241          */
4242         qp_idx = 0;
4243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4244                 if (vsi->enabled_tc & (1 << i)) {
4245                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4246                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4247                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4248                         qp_idx += qpnum_per_tc;
4249                 } else
4250                         info->tc_mapping[i] = 0;
4251         }
4252
4253         /* Associate queue number with VSI */
4254         if (vsi->type == I40E_VSI_SRIOV) {
4255                 info->mapping_flags |=
4256                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4257                 for (i = 0; i < vsi->nb_qps; i++)
4258                         info->queue_mapping[i] =
4259                                 rte_cpu_to_le_16(vsi->base_queue + i);
4260         } else {
4261                 info->mapping_flags |=
4262                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4263                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4264         }
4265         info->valid_sections |=
4266                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4267
4268         return I40E_SUCCESS;
4269 }
4270
4271 static int
4272 i40e_veb_release(struct i40e_veb *veb)
4273 {
4274         struct i40e_vsi *vsi;
4275         struct i40e_hw *hw;
4276
4277         if (veb == NULL)
4278                 return -EINVAL;
4279
4280         if (!TAILQ_EMPTY(&veb->head)) {
4281                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4282                 return -EACCES;
4283         }
4284         /* associate_vsi field is NULL for floating VEB */
4285         if (veb->associate_vsi != NULL) {
4286                 vsi = veb->associate_vsi;
4287                 hw = I40E_VSI_TO_HW(vsi);
4288
4289                 vsi->uplink_seid = veb->uplink_seid;
4290                 vsi->veb = NULL;
4291         } else {
4292                 veb->associate_pf->main_vsi->floating_veb = NULL;
4293                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4294         }
4295
4296         i40e_aq_delete_element(hw, veb->seid, NULL);
4297         rte_free(veb);
4298         return I40E_SUCCESS;
4299 }
4300
4301 /* Setup a veb */
4302 static struct i40e_veb *
4303 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4304 {
4305         struct i40e_veb *veb;
4306         int ret;
4307         struct i40e_hw *hw;
4308
4309         if (pf == NULL) {
4310                 PMD_DRV_LOG(ERR,
4311                             "veb setup failed, associated PF shouldn't null");
4312                 return NULL;
4313         }
4314         hw = I40E_PF_TO_HW(pf);
4315
4316         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4317         if (!veb) {
4318                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4319                 goto fail;
4320         }
4321
4322         veb->associate_vsi = vsi;
4323         veb->associate_pf = pf;
4324         TAILQ_INIT(&veb->head);
4325         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4326
4327         /* create floating veb if vsi is NULL */
4328         if (vsi != NULL) {
4329                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4330                                       I40E_DEFAULT_TCMAP, false,
4331                                       &veb->seid, false, NULL);
4332         } else {
4333                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4334                                       true, &veb->seid, false, NULL);
4335         }
4336
4337         if (ret != I40E_SUCCESS) {
4338                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4339                             hw->aq.asq_last_status);
4340                 goto fail;
4341         }
4342
4343         /* get statistics index */
4344         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4345                                 &veb->stats_idx, NULL, NULL, NULL);
4346         if (ret != I40E_SUCCESS) {
4347                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4348                             hw->aq.asq_last_status);
4349                 goto fail;
4350         }
4351         /* Get VEB bandwidth, to be implemented */
4352         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4353         if (vsi)
4354                 vsi->uplink_seid = veb->seid;
4355
4356         return veb;
4357 fail:
4358         rte_free(veb);
4359         return NULL;
4360 }
4361
4362 int
4363 i40e_vsi_release(struct i40e_vsi *vsi)
4364 {
4365         struct i40e_pf *pf;
4366         struct i40e_hw *hw;
4367         struct i40e_vsi_list *vsi_list;
4368         void *temp;
4369         int ret;
4370         struct i40e_mac_filter *f;
4371         uint16_t user_param;
4372
4373         if (!vsi)
4374                 return I40E_SUCCESS;
4375
4376         user_param = vsi->user_param;
4377
4378         pf = I40E_VSI_TO_PF(vsi);
4379         hw = I40E_VSI_TO_HW(vsi);
4380
4381         /* VSI has child to attach, release child first */
4382         if (vsi->veb) {
4383                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4384                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4385                                 return -1;
4386                 }
4387                 i40e_veb_release(vsi->veb);
4388         }
4389
4390         if (vsi->floating_veb) {
4391                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4392                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4393                                 return -1;
4394                 }
4395         }
4396
4397         /* Remove all macvlan filters of the VSI */
4398         i40e_vsi_remove_all_macvlan_filter(vsi);
4399         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4400                 rte_free(f);
4401
4402         if (vsi->type != I40E_VSI_MAIN &&
4403             ((vsi->type != I40E_VSI_SRIOV) ||
4404             !pf->floating_veb_list[user_param])) {
4405                 /* Remove vsi from parent's sibling list */
4406                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4407                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4408                         return I40E_ERR_PARAM;
4409                 }
4410                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4411                                 &vsi->sib_vsi_list, list);
4412
4413                 /* Remove all switch element of the VSI */
4414                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4415                 if (ret != I40E_SUCCESS)
4416                         PMD_DRV_LOG(ERR, "Failed to delete element");
4417         }
4418
4419         if ((vsi->type == I40E_VSI_SRIOV) &&
4420             pf->floating_veb_list[user_param]) {
4421                 /* Remove vsi from parent's sibling list */
4422                 if (vsi->parent_vsi == NULL ||
4423                     vsi->parent_vsi->floating_veb == NULL) {
4424                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4425                         return I40E_ERR_PARAM;
4426                 }
4427                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4428                              &vsi->sib_vsi_list, list);
4429
4430                 /* Remove all switch element of the VSI */
4431                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4432                 if (ret != I40E_SUCCESS)
4433                         PMD_DRV_LOG(ERR, "Failed to delete element");
4434         }
4435
4436         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4437
4438         if (vsi->type != I40E_VSI_SRIOV)
4439                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4440         rte_free(vsi);
4441
4442         return I40E_SUCCESS;
4443 }
4444
4445 static int
4446 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4447 {
4448         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4449         struct i40e_aqc_remove_macvlan_element_data def_filter;
4450         struct i40e_mac_filter_info filter;
4451         int ret;
4452
4453         if (vsi->type != I40E_VSI_MAIN)
4454                 return I40E_ERR_CONFIG;
4455         memset(&def_filter, 0, sizeof(def_filter));
4456         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4457                                         ETH_ADDR_LEN);
4458         def_filter.vlan_tag = 0;
4459         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4460                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4461         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4462         if (ret != I40E_SUCCESS) {
4463                 struct i40e_mac_filter *f;
4464                 struct ether_addr *mac;
4465
4466                 PMD_DRV_LOG(WARNING,
4467                         "Cannot remove the default macvlan filter");
4468                 /* It needs to add the permanent mac into mac list */
4469                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4470                 if (f == NULL) {
4471                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4472                         return I40E_ERR_NO_MEMORY;
4473                 }
4474                 mac = &f->mac_info.mac_addr;
4475                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4476                                 ETH_ADDR_LEN);
4477                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4478                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4479                 vsi->mac_num++;
4480
4481                 return ret;
4482         }
4483         (void)rte_memcpy(&filter.mac_addr,
4484                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4485         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4486         return i40e_vsi_add_mac(vsi, &filter);
4487 }
4488
4489 /*
4490  * i40e_vsi_get_bw_config - Query VSI BW Information
4491  * @vsi: the VSI to be queried
4492  *
4493  * Returns 0 on success, negative value on failure
4494  */
4495 static enum i40e_status_code
4496 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4497 {
4498         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4499         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4500         struct i40e_hw *hw = &vsi->adapter->hw;
4501         i40e_status ret;
4502         int i;
4503         uint32_t bw_max;
4504
4505         memset(&bw_config, 0, sizeof(bw_config));
4506         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4507         if (ret != I40E_SUCCESS) {
4508                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4509                             hw->aq.asq_last_status);
4510                 return ret;
4511         }
4512
4513         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4514         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4515                                         &ets_sla_config, NULL);
4516         if (ret != I40E_SUCCESS) {
4517                 PMD_DRV_LOG(ERR,
4518                         "VSI failed to get TC bandwdith configuration %u",
4519                         hw->aq.asq_last_status);
4520                 return ret;
4521         }
4522
4523         /* store and print out BW info */
4524         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4525         vsi->bw_info.bw_max = bw_config.max_bw;
4526         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4527         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4528         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4529                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4530                      I40E_16_BIT_WIDTH);
4531         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4532                 vsi->bw_info.bw_ets_share_credits[i] =
4533                                 ets_sla_config.share_credits[i];
4534                 vsi->bw_info.bw_ets_credits[i] =
4535                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4536                 /* 4 bits per TC, 4th bit is reserved */
4537                 vsi->bw_info.bw_ets_max[i] =
4538                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4539                                   RTE_LEN2MASK(3, uint8_t));
4540                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4541                             vsi->bw_info.bw_ets_share_credits[i]);
4542                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4543                             vsi->bw_info.bw_ets_credits[i]);
4544                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4545                             vsi->bw_info.bw_ets_max[i]);
4546         }
4547
4548         return I40E_SUCCESS;
4549 }
4550
4551 /* i40e_enable_pf_lb
4552  * @pf: pointer to the pf structure
4553  *
4554  * allow loopback on pf
4555  */
4556 static inline void
4557 i40e_enable_pf_lb(struct i40e_pf *pf)
4558 {
4559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4560         struct i40e_vsi_context ctxt;
4561         int ret;
4562
4563         /* Use the FW API if FW >= v5.0 */
4564         if (hw->aq.fw_maj_ver < 5) {
4565                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4566                 return;
4567         }
4568
4569         memset(&ctxt, 0, sizeof(ctxt));
4570         ctxt.seid = pf->main_vsi_seid;
4571         ctxt.pf_num = hw->pf_id;
4572         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4573         if (ret) {
4574                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4575                             ret, hw->aq.asq_last_status);
4576                 return;
4577         }
4578         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4579         ctxt.info.valid_sections =
4580                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4581         ctxt.info.switch_id |=
4582                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4583
4584         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4585         if (ret)
4586                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4587                             hw->aq.asq_last_status);
4588 }
4589
4590 /* Setup a VSI */
4591 struct i40e_vsi *
4592 i40e_vsi_setup(struct i40e_pf *pf,
4593                enum i40e_vsi_type type,
4594                struct i40e_vsi *uplink_vsi,
4595                uint16_t user_param)
4596 {
4597         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4598         struct i40e_vsi *vsi;
4599         struct i40e_mac_filter_info filter;
4600         int ret;
4601         struct i40e_vsi_context ctxt;
4602         struct ether_addr broadcast =
4603                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4604
4605         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4606             uplink_vsi == NULL) {
4607                 PMD_DRV_LOG(ERR,
4608                         "VSI setup failed, VSI link shouldn't be NULL");
4609                 return NULL;
4610         }
4611
4612         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4613                 PMD_DRV_LOG(ERR,
4614                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4615                 return NULL;
4616         }
4617
4618         /* two situations
4619          * 1.type is not MAIN and uplink vsi is not NULL
4620          * If uplink vsi didn't setup VEB, create one first under veb field
4621          * 2.type is SRIOV and the uplink is NULL
4622          * If floating VEB is NULL, create one veb under floating veb field
4623          */
4624
4625         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4626             uplink_vsi->veb == NULL) {
4627                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4628
4629                 if (uplink_vsi->veb == NULL) {
4630                         PMD_DRV_LOG(ERR, "VEB setup failed");
4631                         return NULL;
4632                 }
4633                 /* set ALLOWLOOPBACk on pf, when veb is created */
4634                 i40e_enable_pf_lb(pf);
4635         }
4636
4637         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4638             pf->main_vsi->floating_veb == NULL) {
4639                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4640
4641                 if (pf->main_vsi->floating_veb == NULL) {
4642                         PMD_DRV_LOG(ERR, "VEB setup failed");
4643                         return NULL;
4644                 }
4645         }
4646
4647         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4648         if (!vsi) {
4649                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4650                 return NULL;
4651         }
4652         TAILQ_INIT(&vsi->mac_list);
4653         vsi->type = type;
4654         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4655         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4656         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4657         vsi->user_param = user_param;
4658         /* Allocate queues */
4659         switch (vsi->type) {
4660         case I40E_VSI_MAIN  :
4661                 vsi->nb_qps = pf->lan_nb_qps;
4662                 break;
4663         case I40E_VSI_SRIOV :
4664                 vsi->nb_qps = pf->vf_nb_qps;
4665                 break;
4666         case I40E_VSI_VMDQ2:
4667                 vsi->nb_qps = pf->vmdq_nb_qps;
4668                 break;
4669         case I40E_VSI_FDIR:
4670                 vsi->nb_qps = pf->fdir_nb_qps;
4671                 break;
4672         default:
4673                 goto fail_mem;
4674         }
4675         /*
4676          * The filter status descriptor is reported in rx queue 0,
4677          * while the tx queue for fdir filter programming has no
4678          * such constraints, can be non-zero queues.
4679          * To simplify it, choose FDIR vsi use queue 0 pair.
4680          * To make sure it will use queue 0 pair, queue allocation
4681          * need be done before this function is called
4682          */
4683         if (type != I40E_VSI_FDIR) {
4684                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4685                         if (ret < 0) {
4686                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4687                                                 vsi->seid, ret);
4688                                 goto fail_mem;
4689                         }
4690                         vsi->base_queue = ret;
4691         } else
4692                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4693
4694         /* VF has MSIX interrupt in VF range, don't allocate here */
4695         if (type == I40E_VSI_MAIN) {
4696                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4697                                           RTE_MIN(vsi->nb_qps,
4698                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4699                 if (ret < 0) {
4700                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4701                                     vsi->seid, ret);
4702                         goto fail_queue_alloc;
4703                 }
4704                 vsi->msix_intr = ret;
4705                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4706         } else if (type != I40E_VSI_SRIOV) {
4707                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4708                 if (ret < 0) {
4709                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4710                         goto fail_queue_alloc;
4711                 }
4712                 vsi->msix_intr = ret;
4713                 vsi->nb_msix = 1;
4714         } else {
4715                 vsi->msix_intr = 0;
4716                 vsi->nb_msix = 0;
4717         }
4718
4719         /* Add VSI */
4720         if (type == I40E_VSI_MAIN) {
4721                 /* For main VSI, no need to add since it's default one */
4722                 vsi->uplink_seid = pf->mac_seid;
4723                 vsi->seid = pf->main_vsi_seid;
4724                 /* Bind queues with specific MSIX interrupt */
4725                 /**
4726                  * Needs 2 interrupt at least, one for misc cause which will
4727                  * enabled from OS side, Another for queues binding the
4728                  * interrupt from device side only.
4729                  */
4730
4731                 /* Get default VSI parameters from hardware */
4732                 memset(&ctxt, 0, sizeof(ctxt));
4733                 ctxt.seid = vsi->seid;
4734                 ctxt.pf_num = hw->pf_id;
4735                 ctxt.uplink_seid = vsi->uplink_seid;
4736                 ctxt.vf_num = 0;
4737                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4738                 if (ret != I40E_SUCCESS) {
4739                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4740                         goto fail_msix_alloc;
4741                 }
4742                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4743                         sizeof(struct i40e_aqc_vsi_properties_data));
4744                 vsi->vsi_id = ctxt.vsi_number;
4745                 vsi->info.valid_sections = 0;
4746
4747                 /* Configure tc, enabled TC0 only */
4748                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4749                         I40E_SUCCESS) {
4750                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4751                         goto fail_msix_alloc;
4752                 }
4753
4754                 /* TC, queue mapping */
4755                 memset(&ctxt, 0, sizeof(ctxt));
4756                 vsi->info.valid_sections |=
4757                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4758                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4759                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4760                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4761                         sizeof(struct i40e_aqc_vsi_properties_data));
4762                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4763                                                 I40E_DEFAULT_TCMAP);
4764                 if (ret != I40E_SUCCESS) {
4765                         PMD_DRV_LOG(ERR,
4766                                 "Failed to configure TC queue mapping");
4767                         goto fail_msix_alloc;
4768                 }
4769                 ctxt.seid = vsi->seid;
4770                 ctxt.pf_num = hw->pf_id;
4771                 ctxt.uplink_seid = vsi->uplink_seid;
4772                 ctxt.vf_num = 0;
4773
4774                 /* Update VSI parameters */
4775                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4776                 if (ret != I40E_SUCCESS) {
4777                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4778                         goto fail_msix_alloc;
4779                 }
4780
4781                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4782                                                 sizeof(vsi->info.tc_mapping));
4783                 (void)rte_memcpy(&vsi->info.queue_mapping,
4784                                 &ctxt.info.queue_mapping,
4785                         sizeof(vsi->info.queue_mapping));
4786                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4787                 vsi->info.valid_sections = 0;
4788
4789                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4790                                 ETH_ADDR_LEN);
4791
4792                 /**
4793                  * Updating default filter settings are necessary to prevent
4794                  * reception of tagged packets.
4795                  * Some old firmware configurations load a default macvlan
4796                  * filter which accepts both tagged and untagged packets.
4797                  * The updating is to use a normal filter instead if needed.
4798                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4799                  * The firmware with correct configurations load the default
4800                  * macvlan filter which is expected and cannot be removed.
4801                  */
4802                 i40e_update_default_filter_setting(vsi);
4803                 i40e_config_qinq(hw, vsi);
4804         } else if (type == I40E_VSI_SRIOV) {
4805                 memset(&ctxt, 0, sizeof(ctxt));
4806                 /**
4807                  * For other VSI, the uplink_seid equals to uplink VSI's
4808                  * uplink_seid since they share same VEB
4809                  */
4810                 if (uplink_vsi == NULL)
4811                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4812                 else
4813                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4814                 ctxt.pf_num = hw->pf_id;
4815                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4816                 ctxt.uplink_seid = vsi->uplink_seid;
4817                 ctxt.connection_type = 0x1;
4818                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4819
4820                 /* Use the VEB configuration if FW >= v5.0 */
4821                 if (hw->aq.fw_maj_ver >= 5) {
4822                         /* Configure switch ID */
4823                         ctxt.info.valid_sections |=
4824                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4825                         ctxt.info.switch_id =
4826                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4827                 }
4828
4829                 /* Configure port/vlan */
4830                 ctxt.info.valid_sections |=
4831                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4832                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4833                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4834                                                 I40E_DEFAULT_TCMAP);
4835                 if (ret != I40E_SUCCESS) {
4836                         PMD_DRV_LOG(ERR,
4837                                 "Failed to configure TC queue mapping");
4838                         goto fail_msix_alloc;
4839                 }
4840                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4841                 ctxt.info.valid_sections |=
4842                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4843                 /**
4844                  * Since VSI is not created yet, only configure parameter,
4845                  * will add vsi below.
4846                  */
4847
4848                 i40e_config_qinq(hw, vsi);
4849         } else if (type == I40E_VSI_VMDQ2) {
4850                 memset(&ctxt, 0, sizeof(ctxt));
4851                 /*
4852                  * For other VSI, the uplink_seid equals to uplink VSI's
4853                  * uplink_seid since they share same VEB
4854                  */
4855                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4856                 ctxt.pf_num = hw->pf_id;
4857                 ctxt.vf_num = 0;
4858                 ctxt.uplink_seid = vsi->uplink_seid;
4859                 ctxt.connection_type = 0x1;
4860                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4861
4862                 ctxt.info.valid_sections |=
4863                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4864                 /* user_param carries flag to enable loop back */
4865                 if (user_param) {
4866                         ctxt.info.switch_id =
4867                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4868                         ctxt.info.switch_id |=
4869                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4870                 }
4871
4872                 /* Configure port/vlan */
4873                 ctxt.info.valid_sections |=
4874                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4875                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4876                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4877                                                 I40E_DEFAULT_TCMAP);
4878                 if (ret != I40E_SUCCESS) {
4879                         PMD_DRV_LOG(ERR,
4880                                 "Failed to configure TC queue mapping");
4881                         goto fail_msix_alloc;
4882                 }
4883                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4884                 ctxt.info.valid_sections |=
4885                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4886         } else if (type == I40E_VSI_FDIR) {
4887                 memset(&ctxt, 0, sizeof(ctxt));
4888                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4889                 ctxt.pf_num = hw->pf_id;
4890                 ctxt.vf_num = 0;
4891                 ctxt.uplink_seid = vsi->uplink_seid;
4892                 ctxt.connection_type = 0x1;     /* regular data port */
4893                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4894                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4895                                                 I40E_DEFAULT_TCMAP);
4896                 if (ret != I40E_SUCCESS) {
4897                         PMD_DRV_LOG(ERR,
4898                                 "Failed to configure TC queue mapping.");
4899                         goto fail_msix_alloc;
4900                 }
4901                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4902                 ctxt.info.valid_sections |=
4903                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4904         } else {
4905                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4906                 goto fail_msix_alloc;
4907         }
4908
4909         if (vsi->type != I40E_VSI_MAIN) {
4910                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4911                 if (ret != I40E_SUCCESS) {
4912                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4913                                     hw->aq.asq_last_status);
4914                         goto fail_msix_alloc;
4915                 }
4916                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4917                 vsi->info.valid_sections = 0;
4918                 vsi->seid = ctxt.seid;
4919                 vsi->vsi_id = ctxt.vsi_number;
4920                 vsi->sib_vsi_list.vsi = vsi;
4921                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4922                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4923                                           &vsi->sib_vsi_list, list);
4924                 } else {
4925                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4926                                           &vsi->sib_vsi_list, list);
4927                 }
4928         }
4929
4930         /* MAC/VLAN configuration */
4931         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4932         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4933
4934         ret = i40e_vsi_add_mac(vsi, &filter);
4935         if (ret != I40E_SUCCESS) {
4936                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4937                 goto fail_msix_alloc;
4938         }
4939
4940         /* Get VSI BW information */
4941         i40e_vsi_get_bw_config(vsi);
4942         return vsi;
4943 fail_msix_alloc:
4944         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4945 fail_queue_alloc:
4946         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4947 fail_mem:
4948         rte_free(vsi);
4949         return NULL;
4950 }
4951
4952 /* Configure vlan filter on or off */
4953 int
4954 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4955 {
4956         int i, num;
4957         struct i40e_mac_filter *f;
4958         void *temp;
4959         struct i40e_mac_filter_info *mac_filter;
4960         enum rte_mac_filter_type desired_filter;
4961         int ret = I40E_SUCCESS;
4962
4963         if (on) {
4964                 /* Filter to match MAC and VLAN */
4965                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4966         } else {
4967                 /* Filter to match only MAC */
4968                 desired_filter = RTE_MAC_PERFECT_MATCH;
4969         }
4970
4971         num = vsi->mac_num;
4972
4973         mac_filter = rte_zmalloc("mac_filter_info_data",
4974                                  num * sizeof(*mac_filter), 0);
4975         if (mac_filter == NULL) {
4976                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4977                 return I40E_ERR_NO_MEMORY;
4978         }
4979
4980         i = 0;
4981
4982         /* Remove all existing mac */
4983         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4984                 mac_filter[i] = f->mac_info;
4985                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4986                 if (ret) {
4987                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4988                                     on ? "enable" : "disable");
4989                         goto DONE;
4990                 }
4991                 i++;
4992         }
4993
4994         /* Override with new filter */
4995         for (i = 0; i < num; i++) {
4996                 mac_filter[i].filter_type = desired_filter;
4997                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4998                 if (ret) {
4999                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5000                                     on ? "enable" : "disable");
5001                         goto DONE;
5002                 }
5003         }
5004
5005 DONE:
5006         rte_free(mac_filter);
5007         return ret;
5008 }
5009
5010 /* Configure vlan stripping on or off */
5011 int
5012 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5013 {
5014         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5015         struct i40e_vsi_context ctxt;
5016         uint8_t vlan_flags;
5017         int ret = I40E_SUCCESS;
5018
5019         /* Check if it has been already on or off */
5020         if (vsi->info.valid_sections &
5021                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5022                 if (on) {
5023                         if ((vsi->info.port_vlan_flags &
5024                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5025                                 return 0; /* already on */
5026                 } else {
5027                         if ((vsi->info.port_vlan_flags &
5028                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5029                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5030                                 return 0; /* already off */
5031                 }
5032         }
5033
5034         if (on)
5035                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5036         else
5037                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5038         vsi->info.valid_sections =
5039                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5040         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5041         vsi->info.port_vlan_flags |= vlan_flags;
5042         ctxt.seid = vsi->seid;
5043         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5044         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5045         if (ret)
5046                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5047                             on ? "enable" : "disable");
5048
5049         return ret;
5050 }
5051
5052 static int
5053 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5054 {
5055         struct rte_eth_dev_data *data = dev->data;
5056         int ret;
5057         int mask = 0;
5058
5059         /* Apply vlan offload setting */
5060         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5061         i40e_vlan_offload_set(dev, mask);
5062
5063         /* Apply double-vlan setting, not implemented yet */
5064
5065         /* Apply pvid setting */
5066         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5067                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5068         if (ret)
5069                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5070
5071         return ret;
5072 }
5073
5074 static int
5075 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5076 {
5077         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5078
5079         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5080 }
5081
5082 static int
5083 i40e_update_flow_control(struct i40e_hw *hw)
5084 {
5085 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5086         struct i40e_link_status link_status;
5087         uint32_t rxfc = 0, txfc = 0, reg;
5088         uint8_t an_info;
5089         int ret;
5090
5091         memset(&link_status, 0, sizeof(link_status));
5092         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5093         if (ret != I40E_SUCCESS) {
5094                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5095                 goto write_reg; /* Disable flow control */
5096         }
5097
5098         an_info = hw->phy.link_info.an_info;
5099         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5100                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5101                 ret = I40E_ERR_NOT_READY;
5102                 goto write_reg; /* Disable flow control */
5103         }
5104         /**
5105          * If link auto negotiation is enabled, flow control needs to
5106          * be configured according to it
5107          */
5108         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5109         case I40E_LINK_PAUSE_RXTX:
5110                 rxfc = 1;
5111                 txfc = 1;
5112                 hw->fc.current_mode = I40E_FC_FULL;
5113                 break;
5114         case I40E_AQ_LINK_PAUSE_RX:
5115                 rxfc = 1;
5116                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5117                 break;
5118         case I40E_AQ_LINK_PAUSE_TX:
5119                 txfc = 1;
5120                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5121                 break;
5122         default:
5123                 hw->fc.current_mode = I40E_FC_NONE;
5124                 break;
5125         }
5126
5127 write_reg:
5128         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5129                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5130         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5131         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5132         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5133         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5134
5135         return ret;
5136 }
5137
5138 /* PF setup */
5139 static int
5140 i40e_pf_setup(struct i40e_pf *pf)
5141 {
5142         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5143         struct i40e_filter_control_settings settings;
5144         struct i40e_vsi *vsi;
5145         int ret;
5146
5147         /* Clear all stats counters */
5148         pf->offset_loaded = FALSE;
5149         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5150         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5151
5152         ret = i40e_pf_get_switch_config(pf);
5153         if (ret != I40E_SUCCESS) {
5154                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5155                 return ret;
5156         }
5157         if (pf->flags & I40E_FLAG_FDIR) {
5158                 /* make queue allocated first, let FDIR use queue pair 0*/
5159                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5160                 if (ret != I40E_FDIR_QUEUE_ID) {
5161                         PMD_DRV_LOG(ERR,
5162                                 "queue allocation fails for FDIR: ret =%d",
5163                                 ret);
5164                         pf->flags &= ~I40E_FLAG_FDIR;
5165                 }
5166         }
5167         /*  main VSI setup */
5168         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5169         if (!vsi) {
5170                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5171                 return I40E_ERR_NOT_READY;
5172         }
5173         pf->main_vsi = vsi;
5174
5175         /* Configure filter control */
5176         memset(&settings, 0, sizeof(settings));
5177         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5178                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5179         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5180                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5181         else {
5182                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5183                                                 hw->func_caps.rss_table_size);
5184                 return I40E_ERR_PARAM;
5185         }
5186         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u\n",
5187                 hw->func_caps.rss_table_size);
5188         pf->hash_lut_size = hw->func_caps.rss_table_size;
5189
5190         /* Enable ethtype and macvlan filters */
5191         settings.enable_ethtype = TRUE;
5192         settings.enable_macvlan = TRUE;
5193         ret = i40e_set_filter_control(hw, &settings);
5194         if (ret)
5195                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5196                                                                 ret);
5197
5198         /* Update flow control according to the auto negotiation */
5199         i40e_update_flow_control(hw);
5200
5201         return I40E_SUCCESS;
5202 }
5203
5204 int
5205 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5206 {
5207         uint32_t reg;
5208         uint16_t j;
5209
5210         /**
5211          * Set or clear TX Queue Disable flags,
5212          * which is required by hardware.
5213          */
5214         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5215         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5216
5217         /* Wait until the request is finished */
5218         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5219                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5220                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5221                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5222                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5223                                                         & 0x1))) {
5224                         break;
5225                 }
5226         }
5227         if (on) {
5228                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5229                         return I40E_SUCCESS; /* already on, skip next steps */
5230
5231                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5232                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5233         } else {
5234                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5235                         return I40E_SUCCESS; /* already off, skip next steps */
5236                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5237         }
5238         /* Write the register */
5239         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5240         /* Check the result */
5241         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5242                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5243                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5244                 if (on) {
5245                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5246                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5247                                 break;
5248                 } else {
5249                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5250                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5251                                 break;
5252                 }
5253         }
5254         /* Check if it is timeout */
5255         if (j >= I40E_CHK_Q_ENA_COUNT) {
5256                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5257                             (on ? "enable" : "disable"), q_idx);
5258                 return I40E_ERR_TIMEOUT;
5259         }
5260
5261         return I40E_SUCCESS;
5262 }
5263
5264 /* Swith on or off the tx queues */
5265 static int
5266 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5267 {
5268         struct rte_eth_dev_data *dev_data = pf->dev_data;
5269         struct i40e_tx_queue *txq;
5270         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5271         uint16_t i;
5272         int ret;
5273
5274         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5275                 txq = dev_data->tx_queues[i];
5276                 /* Don't operate the queue if not configured or
5277                  * if starting only per queue */
5278                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5279                         continue;
5280                 if (on)
5281                         ret = i40e_dev_tx_queue_start(dev, i);
5282                 else
5283                         ret = i40e_dev_tx_queue_stop(dev, i);
5284                 if ( ret != I40E_SUCCESS)
5285                         return ret;
5286         }
5287
5288         return I40E_SUCCESS;
5289 }
5290
5291 int
5292 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5293 {
5294         uint32_t reg;
5295         uint16_t j;
5296
5297         /* Wait until the request is finished */
5298         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5299                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5300                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5301                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5302                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5303                         break;
5304         }
5305
5306         if (on) {
5307                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5308                         return I40E_SUCCESS; /* Already on, skip next steps */
5309                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5310         } else {
5311                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5312                         return I40E_SUCCESS; /* Already off, skip next steps */
5313                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5314         }
5315
5316         /* Write the register */
5317         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5318         /* Check the result */
5319         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5320                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5321                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5322                 if (on) {
5323                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5324                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5325                                 break;
5326                 } else {
5327                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5328                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5329                                 break;
5330                 }
5331         }
5332
5333         /* Check if it is timeout */
5334         if (j >= I40E_CHK_Q_ENA_COUNT) {
5335                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5336                             (on ? "enable" : "disable"), q_idx);
5337                 return I40E_ERR_TIMEOUT;
5338         }
5339
5340         return I40E_SUCCESS;
5341 }
5342 /* Switch on or off the rx queues */
5343 static int
5344 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5345 {
5346         struct rte_eth_dev_data *dev_data = pf->dev_data;
5347         struct i40e_rx_queue *rxq;
5348         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5349         uint16_t i;
5350         int ret;
5351
5352         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5353                 rxq = dev_data->rx_queues[i];
5354                 /* Don't operate the queue if not configured or
5355                  * if starting only per queue */
5356                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5357                         continue;
5358                 if (on)
5359                         ret = i40e_dev_rx_queue_start(dev, i);
5360                 else
5361                         ret = i40e_dev_rx_queue_stop(dev, i);
5362                 if (ret != I40E_SUCCESS)
5363                         return ret;
5364         }
5365
5366         return I40E_SUCCESS;
5367 }
5368
5369 /* Switch on or off all the rx/tx queues */
5370 int
5371 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5372 {
5373         int ret;
5374
5375         if (on) {
5376                 /* enable rx queues before enabling tx queues */
5377                 ret = i40e_dev_switch_rx_queues(pf, on);
5378                 if (ret) {
5379                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5380                         return ret;
5381                 }
5382                 ret = i40e_dev_switch_tx_queues(pf, on);
5383         } else {
5384                 /* Stop tx queues before stopping rx queues */
5385                 ret = i40e_dev_switch_tx_queues(pf, on);
5386                 if (ret) {
5387                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5388                         return ret;
5389                 }
5390                 ret = i40e_dev_switch_rx_queues(pf, on);
5391         }
5392
5393         return ret;
5394 }
5395
5396 /* Initialize VSI for TX */
5397 static int
5398 i40e_dev_tx_init(struct i40e_pf *pf)
5399 {
5400         struct rte_eth_dev_data *data = pf->dev_data;
5401         uint16_t i;
5402         uint32_t ret = I40E_SUCCESS;
5403         struct i40e_tx_queue *txq;
5404
5405         for (i = 0; i < data->nb_tx_queues; i++) {
5406                 txq = data->tx_queues[i];
5407                 if (!txq || !txq->q_set)
5408                         continue;
5409                 ret = i40e_tx_queue_init(txq);
5410                 if (ret != I40E_SUCCESS)
5411                         break;
5412         }
5413         if (ret == I40E_SUCCESS)
5414                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5415                                      ->eth_dev);
5416
5417         return ret;
5418 }
5419
5420 /* Initialize VSI for RX */
5421 static int
5422 i40e_dev_rx_init(struct i40e_pf *pf)
5423 {
5424         struct rte_eth_dev_data *data = pf->dev_data;
5425         int ret = I40E_SUCCESS;
5426         uint16_t i;
5427         struct i40e_rx_queue *rxq;
5428
5429         i40e_pf_config_mq_rx(pf);
5430         for (i = 0; i < data->nb_rx_queues; i++) {
5431                 rxq = data->rx_queues[i];
5432                 if (!rxq || !rxq->q_set)
5433                         continue;
5434
5435                 ret = i40e_rx_queue_init(rxq);
5436                 if (ret != I40E_SUCCESS) {
5437                         PMD_DRV_LOG(ERR,
5438                                 "Failed to do RX queue initialization");
5439                         break;
5440                 }
5441         }
5442         if (ret == I40E_SUCCESS)
5443                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5444                                      ->eth_dev);
5445
5446         return ret;
5447 }
5448
5449 static int
5450 i40e_dev_rxtx_init(struct i40e_pf *pf)
5451 {
5452         int err;
5453
5454         err = i40e_dev_tx_init(pf);
5455         if (err) {
5456                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5457                 return err;
5458         }
5459         err = i40e_dev_rx_init(pf);
5460         if (err) {
5461                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5462                 return err;
5463         }
5464
5465         return err;
5466 }
5467
5468 static int
5469 i40e_vmdq_setup(struct rte_eth_dev *dev)
5470 {
5471         struct rte_eth_conf *conf = &dev->data->dev_conf;
5472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5473         int i, err, conf_vsis, j, loop;
5474         struct i40e_vsi *vsi;
5475         struct i40e_vmdq_info *vmdq_info;
5476         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5478
5479         /*
5480          * Disable interrupt to avoid message from VF. Furthermore, it will
5481          * avoid race condition in VSI creation/destroy.
5482          */
5483         i40e_pf_disable_irq0(hw);
5484
5485         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5486                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5487                 return -ENOTSUP;
5488         }
5489
5490         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5491         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5492                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5493                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5494                         pf->max_nb_vmdq_vsi);
5495                 return -ENOTSUP;
5496         }
5497
5498         if (pf->vmdq != NULL) {
5499                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5500                 return 0;
5501         }
5502
5503         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5504                                 sizeof(*vmdq_info) * conf_vsis, 0);
5505
5506         if (pf->vmdq == NULL) {
5507                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5508                 return -ENOMEM;
5509         }
5510
5511         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5512
5513         /* Create VMDQ VSI */
5514         for (i = 0; i < conf_vsis; i++) {
5515                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5516                                 vmdq_conf->enable_loop_back);
5517                 if (vsi == NULL) {
5518                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5519                         err = -1;
5520                         goto err_vsi_setup;
5521                 }
5522                 vmdq_info = &pf->vmdq[i];
5523                 vmdq_info->pf = pf;
5524                 vmdq_info->vsi = vsi;
5525         }
5526         pf->nb_cfg_vmdq_vsi = conf_vsis;
5527
5528         /* Configure Vlan */
5529         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5530         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5531                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5532                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5533                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5534                                         vmdq_conf->pool_map[i].vlan_id, j);
5535
5536                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5537                                                 vmdq_conf->pool_map[i].vlan_id);
5538                                 if (err) {
5539                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5540                                         err = -1;
5541                                         goto err_vsi_setup;
5542                                 }
5543                         }
5544                 }
5545         }
5546
5547         i40e_pf_enable_irq0(hw);
5548
5549         return 0;
5550
5551 err_vsi_setup:
5552         for (i = 0; i < conf_vsis; i++)
5553                 if (pf->vmdq[i].vsi == NULL)
5554                         break;
5555                 else
5556                         i40e_vsi_release(pf->vmdq[i].vsi);
5557
5558         rte_free(pf->vmdq);
5559         pf->vmdq = NULL;
5560         i40e_pf_enable_irq0(hw);
5561         return err;
5562 }
5563
5564 static void
5565 i40e_stat_update_32(struct i40e_hw *hw,
5566                    uint32_t reg,
5567                    bool offset_loaded,
5568                    uint64_t *offset,
5569                    uint64_t *stat)
5570 {
5571         uint64_t new_data;
5572
5573         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5574         if (!offset_loaded)
5575                 *offset = new_data;
5576
5577         if (new_data >= *offset)
5578                 *stat = (uint64_t)(new_data - *offset);
5579         else
5580                 *stat = (uint64_t)((new_data +
5581                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5582 }
5583
5584 static void
5585 i40e_stat_update_48(struct i40e_hw *hw,
5586                    uint32_t hireg,
5587                    uint32_t loreg,
5588                    bool offset_loaded,
5589                    uint64_t *offset,
5590                    uint64_t *stat)
5591 {
5592         uint64_t new_data;
5593
5594         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5595         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5596                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5597
5598         if (!offset_loaded)
5599                 *offset = new_data;
5600
5601         if (new_data >= *offset)
5602                 *stat = new_data - *offset;
5603         else
5604                 *stat = (uint64_t)((new_data +
5605                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5606
5607         *stat &= I40E_48_BIT_MASK;
5608 }
5609
5610 /* Disable IRQ0 */
5611 void
5612 i40e_pf_disable_irq0(struct i40e_hw *hw)
5613 {
5614         /* Disable all interrupt types */
5615         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5616         I40E_WRITE_FLUSH(hw);
5617 }
5618
5619 /* Enable IRQ0 */
5620 void
5621 i40e_pf_enable_irq0(struct i40e_hw *hw)
5622 {
5623         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5624                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5625                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5626                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5627         I40E_WRITE_FLUSH(hw);
5628 }
5629
5630 static void
5631 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5632 {
5633         /* read pending request and disable first */
5634         i40e_pf_disable_irq0(hw);
5635         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5636         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5637                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5638
5639         if (no_queue)
5640                 /* Link no queues with irq0 */
5641                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5642                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5643 }
5644
5645 static void
5646 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5647 {
5648         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5650         int i;
5651         uint16_t abs_vf_id;
5652         uint32_t index, offset, val;
5653
5654         if (!pf->vfs)
5655                 return;
5656         /**
5657          * Try to find which VF trigger a reset, use absolute VF id to access
5658          * since the reg is global register.
5659          */
5660         for (i = 0; i < pf->vf_num; i++) {
5661                 abs_vf_id = hw->func_caps.vf_base_id + i;
5662                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5663                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5664                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5665                 /* VFR event occured */
5666                 if (val & (0x1 << offset)) {
5667                         int ret;
5668
5669                         /* Clear the event first */
5670                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5671                                                         (0x1 << offset));
5672                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5673                         /**
5674                          * Only notify a VF reset event occured,
5675                          * don't trigger another SW reset
5676                          */
5677                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5678                         if (ret != I40E_SUCCESS)
5679                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5680                 }
5681         }
5682 }
5683
5684 static void
5685 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5686 {
5687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5688         struct i40e_virtchnl_pf_event event;
5689         int i;
5690
5691         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5692         event.event_data.link_event.link_status =
5693                 dev->data->dev_link.link_status;
5694         event.event_data.link_event.link_speed =
5695                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5696
5697         for (i = 0; i < pf->vf_num; i++)
5698                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5699                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5700 }
5701
5702 static void
5703 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5704 {
5705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706         struct i40e_arq_event_info info;
5707         uint16_t pending, opcode;
5708         int ret;
5709
5710         info.buf_len = I40E_AQ_BUF_SZ;
5711         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5712         if (!info.msg_buf) {
5713                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5714                 return;
5715         }
5716
5717         pending = 1;
5718         while (pending) {
5719                 ret = i40e_clean_arq_element(hw, &info, &pending);
5720
5721                 if (ret != I40E_SUCCESS) {
5722                         PMD_DRV_LOG(INFO,
5723                                 "Failed to read msg from AdminQ, aq_err: %u",
5724                                 hw->aq.asq_last_status);
5725                         break;
5726                 }
5727                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5728
5729                 switch (opcode) {
5730                 case i40e_aqc_opc_send_msg_to_pf:
5731                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5732                         i40e_pf_host_handle_vf_msg(dev,
5733                                         rte_le_to_cpu_16(info.desc.retval),
5734                                         rte_le_to_cpu_32(info.desc.cookie_high),
5735                                         rte_le_to_cpu_32(info.desc.cookie_low),
5736                                         info.msg_buf,
5737                                         info.msg_len);
5738                         break;
5739                 case i40e_aqc_opc_get_link_status:
5740                         ret = i40e_dev_link_update(dev, 0);
5741                         if (!ret) {
5742                                 i40e_notify_all_vfs_link_status(dev);
5743                                 _rte_eth_dev_callback_process(dev,
5744                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5745                         }
5746                         break;
5747                 default:
5748                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5749                                     opcode);
5750                         break;
5751                 }
5752         }
5753         rte_free(info.msg_buf);
5754 }
5755
5756 /**
5757  * Interrupt handler triggered by NIC  for handling
5758  * specific interrupt.
5759  *
5760  * @param handle
5761  *  Pointer to interrupt handle.
5762  * @param param
5763  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5764  *
5765  * @return
5766  *  void
5767  */
5768 static void
5769 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5770                            void *param)
5771 {
5772         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5773         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5774         uint32_t icr0;
5775
5776         /* Disable interrupt */
5777         i40e_pf_disable_irq0(hw);
5778
5779         /* read out interrupt causes */
5780         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5781
5782         /* No interrupt event indicated */
5783         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5784                 PMD_DRV_LOG(INFO, "No interrupt event");
5785                 goto done;
5786         }
5787 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5788         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5789                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5790         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5791                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5792         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5793                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5794         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5795                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5796         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5797                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5798         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5799                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5800         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5801                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5802 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5803
5804         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5805                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5806                 i40e_dev_handle_vfr_event(dev);
5807         }
5808         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5809                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5810                 i40e_dev_handle_aq_msg(dev);
5811         }
5812
5813 done:
5814         /* Enable interrupt */
5815         i40e_pf_enable_irq0(hw);
5816         rte_intr_enable(intr_handle);
5817 }
5818
5819 static int
5820 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5821                          struct i40e_macvlan_filter *filter,
5822                          int total)
5823 {
5824         int ele_num, ele_buff_size;
5825         int num, actual_num, i;
5826         uint16_t flags;
5827         int ret = I40E_SUCCESS;
5828         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5829         struct i40e_aqc_add_macvlan_element_data *req_list;
5830
5831         if (filter == NULL  || total == 0)
5832                 return I40E_ERR_PARAM;
5833         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5834         ele_buff_size = hw->aq.asq_buf_size;
5835
5836         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5837         if (req_list == NULL) {
5838                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5839                 return I40E_ERR_NO_MEMORY;
5840         }
5841
5842         num = 0;
5843         do {
5844                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5845                 memset(req_list, 0, ele_buff_size);
5846
5847                 for (i = 0; i < actual_num; i++) {
5848                         (void)rte_memcpy(req_list[i].mac_addr,
5849                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5850                         req_list[i].vlan_tag =
5851                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5852
5853                         switch (filter[num + i].filter_type) {
5854                         case RTE_MAC_PERFECT_MATCH:
5855                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5856                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5857                                 break;
5858                         case RTE_MACVLAN_PERFECT_MATCH:
5859                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5860                                 break;
5861                         case RTE_MAC_HASH_MATCH:
5862                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5863                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5864                                 break;
5865                         case RTE_MACVLAN_HASH_MATCH:
5866                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5867                                 break;
5868                         default:
5869                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5870                                 ret = I40E_ERR_PARAM;
5871                                 goto DONE;
5872                         }
5873
5874                         req_list[i].queue_number = 0;
5875
5876                         req_list[i].flags = rte_cpu_to_le_16(flags);
5877                 }
5878
5879                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5880                                                 actual_num, NULL);
5881                 if (ret != I40E_SUCCESS) {
5882                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5883                         goto DONE;
5884                 }
5885                 num += actual_num;
5886         } while (num < total);
5887
5888 DONE:
5889         rte_free(req_list);
5890         return ret;
5891 }
5892
5893 static int
5894 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5895                             struct i40e_macvlan_filter *filter,
5896                             int total)
5897 {
5898         int ele_num, ele_buff_size;
5899         int num, actual_num, i;
5900         uint16_t flags;
5901         int ret = I40E_SUCCESS;
5902         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5903         struct i40e_aqc_remove_macvlan_element_data *req_list;
5904
5905         if (filter == NULL  || total == 0)
5906                 return I40E_ERR_PARAM;
5907
5908         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5909         ele_buff_size = hw->aq.asq_buf_size;
5910
5911         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5912         if (req_list == NULL) {
5913                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5914                 return I40E_ERR_NO_MEMORY;
5915         }
5916
5917         num = 0;
5918         do {
5919                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5920                 memset(req_list, 0, ele_buff_size);
5921
5922                 for (i = 0; i < actual_num; i++) {
5923                         (void)rte_memcpy(req_list[i].mac_addr,
5924                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5925                         req_list[i].vlan_tag =
5926                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5927
5928                         switch (filter[num + i].filter_type) {
5929                         case RTE_MAC_PERFECT_MATCH:
5930                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5931                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5932                                 break;
5933                         case RTE_MACVLAN_PERFECT_MATCH:
5934                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5935                                 break;
5936                         case RTE_MAC_HASH_MATCH:
5937                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5938                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5939                                 break;
5940                         case RTE_MACVLAN_HASH_MATCH:
5941                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5942                                 break;
5943                         default:
5944                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5945                                 ret = I40E_ERR_PARAM;
5946                                 goto DONE;
5947                         }
5948                         req_list[i].flags = rte_cpu_to_le_16(flags);
5949                 }
5950
5951                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5952                                                 actual_num, NULL);
5953                 if (ret != I40E_SUCCESS) {
5954                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5955                         goto DONE;
5956                 }
5957                 num += actual_num;
5958         } while (num < total);
5959
5960 DONE:
5961         rte_free(req_list);
5962         return ret;
5963 }
5964
5965 /* Find out specific MAC filter */
5966 static struct i40e_mac_filter *
5967 i40e_find_mac_filter(struct i40e_vsi *vsi,
5968                          struct ether_addr *macaddr)
5969 {
5970         struct i40e_mac_filter *f;
5971
5972         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5973                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5974                         return f;
5975         }
5976
5977         return NULL;
5978 }
5979
5980 static bool
5981 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5982                          uint16_t vlan_id)
5983 {
5984         uint32_t vid_idx, vid_bit;
5985
5986         if (vlan_id > ETH_VLAN_ID_MAX)
5987                 return 0;
5988
5989         vid_idx = I40E_VFTA_IDX(vlan_id);
5990         vid_bit = I40E_VFTA_BIT(vlan_id);
5991
5992         if (vsi->vfta[vid_idx] & vid_bit)
5993                 return 1;
5994         else
5995                 return 0;
5996 }
5997
5998 static void
5999 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6000                          uint16_t vlan_id, bool on)
6001 {
6002         uint32_t vid_idx, vid_bit;
6003
6004         if (vlan_id > ETH_VLAN_ID_MAX)
6005                 return;
6006
6007         vid_idx = I40E_VFTA_IDX(vlan_id);
6008         vid_bit = I40E_VFTA_BIT(vlan_id);
6009
6010         if (on)
6011                 vsi->vfta[vid_idx] |= vid_bit;
6012         else
6013                 vsi->vfta[vid_idx] &= ~vid_bit;
6014 }
6015
6016 /**
6017  * Find all vlan options for specific mac addr,
6018  * return with actual vlan found.
6019  */
6020 static inline int
6021 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6022                            struct i40e_macvlan_filter *mv_f,
6023                            int num, struct ether_addr *addr)
6024 {
6025         int i;
6026         uint32_t j, k;
6027
6028         /**
6029          * Not to use i40e_find_vlan_filter to decrease the loop time,
6030          * although the code looks complex.
6031           */
6032         if (num < vsi->vlan_num)
6033                 return I40E_ERR_PARAM;
6034
6035         i = 0;
6036         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6037                 if (vsi->vfta[j]) {
6038                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6039                                 if (vsi->vfta[j] & (1 << k)) {
6040                                         if (i > num - 1) {
6041                                                 PMD_DRV_LOG(ERR,
6042                                                         "vlan number doesn't match");
6043                                                 return I40E_ERR_PARAM;
6044                                         }
6045                                         (void)rte_memcpy(&mv_f[i].macaddr,
6046                                                         addr, ETH_ADDR_LEN);
6047                                         mv_f[i].vlan_id =
6048                                                 j * I40E_UINT32_BIT_SIZE + k;
6049                                         i++;
6050                                 }
6051                         }
6052                 }
6053         }
6054         return I40E_SUCCESS;
6055 }
6056
6057 static inline int
6058 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6059                            struct i40e_macvlan_filter *mv_f,
6060                            int num,
6061                            uint16_t vlan)
6062 {
6063         int i = 0;
6064         struct i40e_mac_filter *f;
6065
6066         if (num < vsi->mac_num)
6067                 return I40E_ERR_PARAM;
6068
6069         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6070                 if (i > num - 1) {
6071                         PMD_DRV_LOG(ERR, "buffer number not match");
6072                         return I40E_ERR_PARAM;
6073                 }
6074                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6075                                 ETH_ADDR_LEN);
6076                 mv_f[i].vlan_id = vlan;
6077                 mv_f[i].filter_type = f->mac_info.filter_type;
6078                 i++;
6079         }
6080
6081         return I40E_SUCCESS;
6082 }
6083
6084 static int
6085 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6086 {
6087         int i, num;
6088         struct i40e_mac_filter *f;
6089         struct i40e_macvlan_filter *mv_f;
6090         int ret = I40E_SUCCESS;
6091
6092         if (vsi == NULL || vsi->mac_num == 0)
6093                 return I40E_ERR_PARAM;
6094
6095         /* Case that no vlan is set */
6096         if (vsi->vlan_num == 0)
6097                 num = vsi->mac_num;
6098         else
6099                 num = vsi->mac_num * vsi->vlan_num;
6100
6101         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6102         if (mv_f == NULL) {
6103                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6104                 return I40E_ERR_NO_MEMORY;
6105         }
6106
6107         i = 0;
6108         if (vsi->vlan_num == 0) {
6109                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6110                         (void)rte_memcpy(&mv_f[i].macaddr,
6111                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6112                         mv_f[i].vlan_id = 0;
6113                         i++;
6114                 }
6115         } else {
6116                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6117                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6118                                         vsi->vlan_num, &f->mac_info.mac_addr);
6119                         if (ret != I40E_SUCCESS)
6120                                 goto DONE;
6121                         i += vsi->vlan_num;
6122                 }
6123         }
6124
6125         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6126 DONE:
6127         rte_free(mv_f);
6128
6129         return ret;
6130 }
6131
6132 int
6133 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6134 {
6135         struct i40e_macvlan_filter *mv_f;
6136         int mac_num;
6137         int ret = I40E_SUCCESS;
6138
6139         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6140                 return I40E_ERR_PARAM;
6141
6142         /* If it's already set, just return */
6143         if (i40e_find_vlan_filter(vsi,vlan))
6144                 return I40E_SUCCESS;
6145
6146         mac_num = vsi->mac_num;
6147
6148         if (mac_num == 0) {
6149                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6150                 return I40E_ERR_PARAM;
6151         }
6152
6153         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6154
6155         if (mv_f == NULL) {
6156                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6157                 return I40E_ERR_NO_MEMORY;
6158         }
6159
6160         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6161
6162         if (ret != I40E_SUCCESS)
6163                 goto DONE;
6164
6165         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6166
6167         if (ret != I40E_SUCCESS)
6168                 goto DONE;
6169
6170         i40e_set_vlan_filter(vsi, vlan, 1);
6171
6172         vsi->vlan_num++;
6173         ret = I40E_SUCCESS;
6174 DONE:
6175         rte_free(mv_f);
6176         return ret;
6177 }
6178
6179 int
6180 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6181 {
6182         struct i40e_macvlan_filter *mv_f;
6183         int mac_num;
6184         int ret = I40E_SUCCESS;
6185
6186         /**
6187          * Vlan 0 is the generic filter for untagged packets
6188          * and can't be removed.
6189          */
6190         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6191                 return I40E_ERR_PARAM;
6192
6193         /* If can't find it, just return */
6194         if (!i40e_find_vlan_filter(vsi, vlan))
6195                 return I40E_ERR_PARAM;
6196
6197         mac_num = vsi->mac_num;
6198
6199         if (mac_num == 0) {
6200                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6201                 return I40E_ERR_PARAM;
6202         }
6203
6204         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6205
6206         if (mv_f == NULL) {
6207                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6208                 return I40E_ERR_NO_MEMORY;
6209         }
6210
6211         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6212
6213         if (ret != I40E_SUCCESS)
6214                 goto DONE;
6215
6216         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6217
6218         if (ret != I40E_SUCCESS)
6219                 goto DONE;
6220
6221         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6222         if (vsi->vlan_num == 1) {
6223                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6224                 if (ret != I40E_SUCCESS)
6225                         goto DONE;
6226
6227                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6228                 if (ret != I40E_SUCCESS)
6229                         goto DONE;
6230         }
6231
6232         i40e_set_vlan_filter(vsi, vlan, 0);
6233
6234         vsi->vlan_num--;
6235         ret = I40E_SUCCESS;
6236 DONE:
6237         rte_free(mv_f);
6238         return ret;
6239 }
6240
6241 int
6242 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6243 {
6244         struct i40e_mac_filter *f;
6245         struct i40e_macvlan_filter *mv_f;
6246         int i, vlan_num = 0;
6247         int ret = I40E_SUCCESS;
6248
6249         /* If it's add and we've config it, return */
6250         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6251         if (f != NULL)
6252                 return I40E_SUCCESS;
6253         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6254                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6255
6256                 /**
6257                  * If vlan_num is 0, that's the first time to add mac,
6258                  * set mask for vlan_id 0.
6259                  */
6260                 if (vsi->vlan_num == 0) {
6261                         i40e_set_vlan_filter(vsi, 0, 1);
6262                         vsi->vlan_num = 1;
6263                 }
6264                 vlan_num = vsi->vlan_num;
6265         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6266                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6267                 vlan_num = 1;
6268
6269         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6270         if (mv_f == NULL) {
6271                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6272                 return I40E_ERR_NO_MEMORY;
6273         }
6274
6275         for (i = 0; i < vlan_num; i++) {
6276                 mv_f[i].filter_type = mac_filter->filter_type;
6277                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6278                                 ETH_ADDR_LEN);
6279         }
6280
6281         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6282                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6283                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6284                                         &mac_filter->mac_addr);
6285                 if (ret != I40E_SUCCESS)
6286                         goto DONE;
6287         }
6288
6289         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6290         if (ret != I40E_SUCCESS)
6291                 goto DONE;
6292
6293         /* Add the mac addr into mac list */
6294         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6295         if (f == NULL) {
6296                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6297                 ret = I40E_ERR_NO_MEMORY;
6298                 goto DONE;
6299         }
6300         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6301                         ETH_ADDR_LEN);
6302         f->mac_info.filter_type = mac_filter->filter_type;
6303         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6304         vsi->mac_num++;
6305
6306         ret = I40E_SUCCESS;
6307 DONE:
6308         rte_free(mv_f);
6309
6310         return ret;
6311 }
6312
6313 int
6314 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6315 {
6316         struct i40e_mac_filter *f;
6317         struct i40e_macvlan_filter *mv_f;
6318         int i, vlan_num;
6319         enum rte_mac_filter_type filter_type;
6320         int ret = I40E_SUCCESS;
6321
6322         /* Can't find it, return an error */
6323         f = i40e_find_mac_filter(vsi, addr);
6324         if (f == NULL)
6325                 return I40E_ERR_PARAM;
6326
6327         vlan_num = vsi->vlan_num;
6328         filter_type = f->mac_info.filter_type;
6329         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6330                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6331                 if (vlan_num == 0) {
6332                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6333                         return I40E_ERR_PARAM;
6334                 }
6335         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6336                         filter_type == RTE_MAC_HASH_MATCH)
6337                 vlan_num = 1;
6338
6339         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6340         if (mv_f == NULL) {
6341                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6342                 return I40E_ERR_NO_MEMORY;
6343         }
6344
6345         for (i = 0; i < vlan_num; i++) {
6346                 mv_f[i].filter_type = filter_type;
6347                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6348                                 ETH_ADDR_LEN);
6349         }
6350         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6351                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6352                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6353                 if (ret != I40E_SUCCESS)
6354                         goto DONE;
6355         }
6356
6357         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6358         if (ret != I40E_SUCCESS)
6359                 goto DONE;
6360
6361         /* Remove the mac addr into mac list */
6362         TAILQ_REMOVE(&vsi->mac_list, f, next);
6363         rte_free(f);
6364         vsi->mac_num--;
6365
6366         ret = I40E_SUCCESS;
6367 DONE:
6368         rte_free(mv_f);
6369         return ret;
6370 }
6371
6372 /* Configure hash enable flags for RSS */
6373 uint64_t
6374 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6375 {
6376         uint64_t hena = 0;
6377
6378         if (!flags)
6379                 return hena;
6380
6381         if (flags & ETH_RSS_FRAG_IPV4)
6382                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6383         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6384                 if (type == I40E_MAC_X722) {
6385                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6386                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6387                 } else
6388                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6389         }
6390         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6391                 if (type == I40E_MAC_X722) {
6392                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6393                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6394                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6395                 } else
6396                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6397         }
6398         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6399                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6400         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6401                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6402         if (flags & ETH_RSS_FRAG_IPV6)
6403                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6404         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6405                 if (type == I40E_MAC_X722) {
6406                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6407                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6408                 } else
6409                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6410         }
6411         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6412                 if (type == I40E_MAC_X722) {
6413                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6414                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6415                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6416                 } else
6417                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6418         }
6419         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6420                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6421         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6422                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6423         if (flags & ETH_RSS_L2_PAYLOAD)
6424                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6425
6426         return hena;
6427 }
6428
6429 /* Parse the hash enable flags */
6430 uint64_t
6431 i40e_parse_hena(uint64_t flags)
6432 {
6433         uint64_t rss_hf = 0;
6434
6435         if (!flags)
6436                 return rss_hf;
6437         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6438                 rss_hf |= ETH_RSS_FRAG_IPV4;
6439         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6440                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6441         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6442                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6443         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6444                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6445         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6446                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6447         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6448                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6449         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6450                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6451         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6452                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6453         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6454                 rss_hf |= ETH_RSS_FRAG_IPV6;
6455         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6456                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6457         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6458                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6459         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6460                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6461         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6462                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6463         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6464                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6465         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6466                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6467         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6468                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6469         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6470                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6471
6472         return rss_hf;
6473 }
6474
6475 /* Disable RSS */
6476 static void
6477 i40e_pf_disable_rss(struct i40e_pf *pf)
6478 {
6479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6480         uint64_t hena;
6481
6482         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6483         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6484         if (hw->mac.type == I40E_MAC_X722)
6485                 hena &= ~I40E_RSS_HENA_ALL_X722;
6486         else
6487                 hena &= ~I40E_RSS_HENA_ALL;
6488         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6489         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6490         I40E_WRITE_FLUSH(hw);
6491 }
6492
6493 static int
6494 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6495 {
6496         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6497         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6498         int ret = 0;
6499
6500         if (!key || key_len == 0) {
6501                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6502                 return 0;
6503         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6504                 sizeof(uint32_t)) {
6505                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6506                 return -EINVAL;
6507         }
6508
6509         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6510                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6511                         (struct i40e_aqc_get_set_rss_key_data *)key;
6512
6513                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6514                 if (ret)
6515                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6516         } else {
6517                 uint32_t *hash_key = (uint32_t *)key;
6518                 uint16_t i;
6519
6520                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6521                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6522                 I40E_WRITE_FLUSH(hw);
6523         }
6524
6525         return ret;
6526 }
6527
6528 static int
6529 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6530 {
6531         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6533         int ret;
6534
6535         if (!key || !key_len)
6536                 return -EINVAL;
6537
6538         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6539                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6540                         (struct i40e_aqc_get_set_rss_key_data *)key);
6541                 if (ret) {
6542                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6543                         return ret;
6544                 }
6545         } else {
6546                 uint32_t *key_dw = (uint32_t *)key;
6547                 uint16_t i;
6548
6549                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6550                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6551         }
6552         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6553
6554         return 0;
6555 }
6556
6557 static int
6558 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6559 {
6560         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6561         uint64_t rss_hf;
6562         uint64_t hena;
6563         int ret;
6564
6565         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6566                                rss_conf->rss_key_len);
6567         if (ret)
6568                 return ret;
6569
6570         rss_hf = rss_conf->rss_hf;
6571         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6572         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6573         if (hw->mac.type == I40E_MAC_X722)
6574                 hena &= ~I40E_RSS_HENA_ALL_X722;
6575         else
6576                 hena &= ~I40E_RSS_HENA_ALL;
6577         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6578         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6579         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6580         I40E_WRITE_FLUSH(hw);
6581
6582         return 0;
6583 }
6584
6585 static int
6586 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6587                          struct rte_eth_rss_conf *rss_conf)
6588 {
6589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6590         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6591         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6592         uint64_t hena;
6593
6594         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6595         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6596         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6597                  ? I40E_RSS_HENA_ALL_X722
6598                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6599                 if (rss_hf != 0) /* Enable RSS */
6600                         return -EINVAL;
6601                 return 0; /* Nothing to do */
6602         }
6603         /* RSS enabled */
6604         if (rss_hf == 0) /* Disable RSS */
6605                 return -EINVAL;
6606
6607         return i40e_hw_rss_hash_set(pf, rss_conf);
6608 }
6609
6610 static int
6611 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6612                            struct rte_eth_rss_conf *rss_conf)
6613 {
6614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6616         uint64_t hena;
6617
6618         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6619                          &rss_conf->rss_key_len);
6620
6621         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6622         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6623         rss_conf->rss_hf = i40e_parse_hena(hena);
6624
6625         return 0;
6626 }
6627
6628 static int
6629 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6630 {
6631         switch (filter_type) {
6632         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6633                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6634                 break;
6635         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6636                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6637                 break;
6638         case RTE_TUNNEL_FILTER_IMAC_TENID:
6639                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6640                 break;
6641         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6642                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6643                 break;
6644         case ETH_TUNNEL_FILTER_IMAC:
6645                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6646                 break;
6647         case ETH_TUNNEL_FILTER_OIP:
6648                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6649                 break;
6650         case ETH_TUNNEL_FILTER_IIP:
6651                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6652                 break;
6653         default:
6654                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6655                 return -EINVAL;
6656         }
6657
6658         return 0;
6659 }
6660
6661 /* Convert tunnel filter structure */
6662 static int
6663 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6664                            *cld_filter,
6665                            struct i40e_tunnel_filter *tunnel_filter)
6666 {
6667         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6668                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6669         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6670                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6671         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6672         tunnel_filter->input.flags = cld_filter->flags;
6673         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6674         tunnel_filter->queue = cld_filter->queue_number;
6675
6676         return 0;
6677 }
6678
6679 /* Check if there exists the tunnel filter */
6680 struct i40e_tunnel_filter *
6681 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6682                              const struct i40e_tunnel_filter_input *input)
6683 {
6684         int ret;
6685
6686         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6687         if (ret < 0)
6688                 return NULL;
6689
6690         return tunnel_rule->hash_map[ret];
6691 }
6692
6693 /* Add a tunnel filter into the SW list */
6694 static int
6695 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6696                              struct i40e_tunnel_filter *tunnel_filter)
6697 {
6698         struct i40e_tunnel_rule *rule = &pf->tunnel;
6699         int ret;
6700
6701         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6702         if (ret < 0) {
6703                 PMD_DRV_LOG(ERR,
6704                             "Failed to insert tunnel filter to hash table %d!",
6705                             ret);
6706                 return ret;
6707         }
6708         rule->hash_map[ret] = tunnel_filter;
6709
6710         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6711
6712         return 0;
6713 }
6714
6715 /* Delete a tunnel filter from the SW list */
6716 int
6717 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6718                           struct i40e_tunnel_filter_input *input)
6719 {
6720         struct i40e_tunnel_rule *rule = &pf->tunnel;
6721         struct i40e_tunnel_filter *tunnel_filter;
6722         int ret;
6723
6724         ret = rte_hash_del_key(rule->hash_table, input);
6725         if (ret < 0) {
6726                 PMD_DRV_LOG(ERR,
6727                             "Failed to delete tunnel filter to hash table %d!",
6728                             ret);
6729                 return ret;
6730         }
6731         tunnel_filter = rule->hash_map[ret];
6732         rule->hash_map[ret] = NULL;
6733
6734         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6735         rte_free(tunnel_filter);
6736
6737         return 0;
6738 }
6739
6740 int
6741 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6742                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6743                         uint8_t add)
6744 {
6745         uint16_t ip_type;
6746         uint32_t ipv4_addr;
6747         uint8_t i, tun_type = 0;
6748         /* internal varialbe to convert ipv6 byte order */
6749         uint32_t convert_ipv6[4];
6750         int val, ret = 0;
6751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6752         struct i40e_vsi *vsi = pf->main_vsi;
6753         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6754         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6755         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6756         struct i40e_tunnel_filter *tunnel, *node;
6757         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6758
6759         cld_filter = rte_zmalloc("tunnel_filter",
6760                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6761                 0);
6762
6763         if (NULL == cld_filter) {
6764                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6765                 return -EINVAL;
6766         }
6767         pfilter = cld_filter;
6768
6769         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6770         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6771
6772         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6773         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6774                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6775                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6776                 rte_memcpy(&pfilter->ipaddr.v4.data,
6777                                 &rte_cpu_to_le_32(ipv4_addr),
6778                                 sizeof(pfilter->ipaddr.v4.data));
6779         } else {
6780                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6781                 for (i = 0; i < 4; i++) {
6782                         convert_ipv6[i] =
6783                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6784                 }
6785                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6786                                 sizeof(pfilter->ipaddr.v6.data));
6787         }
6788
6789         /* check tunneled type */
6790         switch (tunnel_filter->tunnel_type) {
6791         case RTE_TUNNEL_TYPE_VXLAN:
6792                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6793                 break;
6794         case RTE_TUNNEL_TYPE_NVGRE:
6795                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6796                 break;
6797         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6798                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6799                 break;
6800         default:
6801                 /* Other tunnel types is not supported. */
6802                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6803                 rte_free(cld_filter);
6804                 return -EINVAL;
6805         }
6806
6807         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6808                                                 &pfilter->flags);
6809         if (val < 0) {
6810                 rte_free(cld_filter);
6811                 return -EINVAL;
6812         }
6813
6814         pfilter->flags |= rte_cpu_to_le_16(
6815                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6816                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6817         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6818         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6819
6820         /* Check if there is the filter in SW list */
6821         memset(&check_filter, 0, sizeof(check_filter));
6822         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6823         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6824         if (add && node) {
6825                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6826                 return -EINVAL;
6827         }
6828
6829         if (!add && !node) {
6830                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6831                 return -EINVAL;
6832         }
6833
6834         if (add) {
6835                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6836                 if (ret < 0) {
6837                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6838                         return ret;
6839                 }
6840                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6841                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6842                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6843         } else {
6844                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6845                                                    cld_filter, 1);
6846                 if (ret < 0) {
6847                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6848                         return ret;
6849                 }
6850                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6851         }
6852
6853         rte_free(cld_filter);
6854         return ret;
6855 }
6856
6857 static int
6858 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6859 {
6860         uint8_t i;
6861
6862         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6863                 if (pf->vxlan_ports[i] == port)
6864                         return i;
6865         }
6866
6867         return -1;
6868 }
6869
6870 static int
6871 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6872 {
6873         int  idx, ret;
6874         uint8_t filter_idx;
6875         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6876
6877         idx = i40e_get_vxlan_port_idx(pf, port);
6878
6879         /* Check if port already exists */
6880         if (idx >= 0) {
6881                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6882                 return -EINVAL;
6883         }
6884
6885         /* Now check if there is space to add the new port */
6886         idx = i40e_get_vxlan_port_idx(pf, 0);
6887         if (idx < 0) {
6888                 PMD_DRV_LOG(ERR,
6889                         "Maximum number of UDP ports reached, not adding port %d",
6890                         port);
6891                 return -ENOSPC;
6892         }
6893
6894         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6895                                         &filter_idx, NULL);
6896         if (ret < 0) {
6897                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6898                 return -1;
6899         }
6900
6901         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6902                          port,  filter_idx);
6903
6904         /* New port: add it and mark its index in the bitmap */
6905         pf->vxlan_ports[idx] = port;
6906         pf->vxlan_bitmap |= (1 << idx);
6907
6908         if (!(pf->flags & I40E_FLAG_VXLAN))
6909                 pf->flags |= I40E_FLAG_VXLAN;
6910
6911         return 0;
6912 }
6913
6914 static int
6915 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6916 {
6917         int idx;
6918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6919
6920         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6921                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6922                 return -EINVAL;
6923         }
6924
6925         idx = i40e_get_vxlan_port_idx(pf, port);
6926
6927         if (idx < 0) {
6928                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6929                 return -EINVAL;
6930         }
6931
6932         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6933                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6934                 return -1;
6935         }
6936
6937         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6938                         port, idx);
6939
6940         pf->vxlan_ports[idx] = 0;
6941         pf->vxlan_bitmap &= ~(1 << idx);
6942
6943         if (!pf->vxlan_bitmap)
6944                 pf->flags &= ~I40E_FLAG_VXLAN;
6945
6946         return 0;
6947 }
6948
6949 /* Add UDP tunneling port */
6950 static int
6951 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6952                              struct rte_eth_udp_tunnel *udp_tunnel)
6953 {
6954         int ret = 0;
6955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6956
6957         if (udp_tunnel == NULL)
6958                 return -EINVAL;
6959
6960         switch (udp_tunnel->prot_type) {
6961         case RTE_TUNNEL_TYPE_VXLAN:
6962                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6963                 break;
6964
6965         case RTE_TUNNEL_TYPE_GENEVE:
6966         case RTE_TUNNEL_TYPE_TEREDO:
6967                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6968                 ret = -1;
6969                 break;
6970
6971         default:
6972                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6973                 ret = -1;
6974                 break;
6975         }
6976
6977         return ret;
6978 }
6979
6980 /* Remove UDP tunneling port */
6981 static int
6982 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6983                              struct rte_eth_udp_tunnel *udp_tunnel)
6984 {
6985         int ret = 0;
6986         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6987
6988         if (udp_tunnel == NULL)
6989                 return -EINVAL;
6990
6991         switch (udp_tunnel->prot_type) {
6992         case RTE_TUNNEL_TYPE_VXLAN:
6993                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6994                 break;
6995         case RTE_TUNNEL_TYPE_GENEVE:
6996         case RTE_TUNNEL_TYPE_TEREDO:
6997                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6998                 ret = -1;
6999                 break;
7000         default:
7001                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7002                 ret = -1;
7003                 break;
7004         }
7005
7006         return ret;
7007 }
7008
7009 /* Calculate the maximum number of contiguous PF queues that are configured */
7010 static int
7011 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7012 {
7013         struct rte_eth_dev_data *data = pf->dev_data;
7014         int i, num;
7015         struct i40e_rx_queue *rxq;
7016
7017         num = 0;
7018         for (i = 0; i < pf->lan_nb_qps; i++) {
7019                 rxq = data->rx_queues[i];
7020                 if (rxq && rxq->q_set)
7021                         num++;
7022                 else
7023                         break;
7024         }
7025
7026         return num;
7027 }
7028
7029 /* Configure RSS */
7030 static int
7031 i40e_pf_config_rss(struct i40e_pf *pf)
7032 {
7033         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7034         struct rte_eth_rss_conf rss_conf;
7035         uint32_t i, lut = 0;
7036         uint16_t j, num;
7037
7038         /*
7039          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7040          * It's necessary to calulate the actual PF queues that are configured.
7041          */
7042         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7043                 num = i40e_pf_calc_configured_queues_num(pf);
7044         else
7045                 num = pf->dev_data->nb_rx_queues;
7046
7047         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7048         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7049                         num);
7050
7051         if (num == 0) {
7052                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7053                 return -ENOTSUP;
7054         }
7055
7056         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7057                 if (j == num)
7058                         j = 0;
7059                 lut = (lut << 8) | (j & ((0x1 <<
7060                         hw->func_caps.rss_table_entry_width) - 1));
7061                 if ((i & 3) == 3)
7062                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7063         }
7064
7065         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7066         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7067                 i40e_pf_disable_rss(pf);
7068                 return 0;
7069         }
7070         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7071                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7072                 /* Random default keys */
7073                 static uint32_t rss_key_default[] = {0x6b793944,
7074                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7075                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7076                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7077
7078                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7079                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7080                                                         sizeof(uint32_t);
7081         }
7082
7083         return i40e_hw_rss_hash_set(pf, &rss_conf);
7084 }
7085
7086 static int
7087 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7088                                struct rte_eth_tunnel_filter_conf *filter)
7089 {
7090         if (pf == NULL || filter == NULL) {
7091                 PMD_DRV_LOG(ERR, "Invalid parameter");
7092                 return -EINVAL;
7093         }
7094
7095         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7096                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7097                 return -EINVAL;
7098         }
7099
7100         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7101                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7102                 return -EINVAL;
7103         }
7104
7105         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7106                 (is_zero_ether_addr(&filter->outer_mac))) {
7107                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7108                 return -EINVAL;
7109         }
7110
7111         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7112                 (is_zero_ether_addr(&filter->inner_mac))) {
7113                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7114                 return -EINVAL;
7115         }
7116
7117         return 0;
7118 }
7119
7120 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7121 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7122 static int
7123 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7124 {
7125         uint32_t val, reg;
7126         int ret = -EINVAL;
7127
7128         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7129         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7130
7131         if (len == 3) {
7132                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7133         } else if (len == 4) {
7134                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7135         } else {
7136                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7137                 return ret;
7138         }
7139
7140         if (reg != val) {
7141                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7142                                                    reg, NULL);
7143                 if (ret != 0)
7144                         return ret;
7145         } else {
7146                 ret = 0;
7147         }
7148         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7149                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7150
7151         return ret;
7152 }
7153
7154 static int
7155 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7156 {
7157         int ret = -EINVAL;
7158
7159         if (!hw || !cfg)
7160                 return -EINVAL;
7161
7162         switch (cfg->cfg_type) {
7163         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7164                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7165                 break;
7166         default:
7167                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7168                 break;
7169         }
7170
7171         return ret;
7172 }
7173
7174 static int
7175 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7176                                enum rte_filter_op filter_op,
7177                                void *arg)
7178 {
7179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7180         int ret = I40E_ERR_PARAM;
7181
7182         switch (filter_op) {
7183         case RTE_ETH_FILTER_SET:
7184                 ret = i40e_dev_global_config_set(hw,
7185                         (struct rte_eth_global_cfg *)arg);
7186                 break;
7187         default:
7188                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7189                 break;
7190         }
7191
7192         return ret;
7193 }
7194
7195 static int
7196 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7197                           enum rte_filter_op filter_op,
7198                           void *arg)
7199 {
7200         struct rte_eth_tunnel_filter_conf *filter;
7201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7202         int ret = I40E_SUCCESS;
7203
7204         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7205
7206         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7207                 return I40E_ERR_PARAM;
7208
7209         switch (filter_op) {
7210         case RTE_ETH_FILTER_NOP:
7211                 if (!(pf->flags & I40E_FLAG_VXLAN))
7212                         ret = I40E_NOT_SUPPORTED;
7213                 break;
7214         case RTE_ETH_FILTER_ADD:
7215                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7216                 break;
7217         case RTE_ETH_FILTER_DELETE:
7218                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7219                 break;
7220         default:
7221                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7222                 ret = I40E_ERR_PARAM;
7223                 break;
7224         }
7225
7226         return ret;
7227 }
7228
7229 static int
7230 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7231 {
7232         int ret = 0;
7233         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7234
7235         /* RSS setup */
7236         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7237                 ret = i40e_pf_config_rss(pf);
7238         else
7239                 i40e_pf_disable_rss(pf);
7240
7241         return ret;
7242 }
7243
7244 /* Get the symmetric hash enable configurations per port */
7245 static void
7246 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7247 {
7248         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7249
7250         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7251 }
7252
7253 /* Set the symmetric hash enable configurations per port */
7254 static void
7255 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7256 {
7257         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7258
7259         if (enable > 0) {
7260                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7261                         PMD_DRV_LOG(INFO,
7262                                 "Symmetric hash has already been enabled");
7263                         return;
7264                 }
7265                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7266         } else {
7267                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7268                         PMD_DRV_LOG(INFO,
7269                                 "Symmetric hash has already been disabled");
7270                         return;
7271                 }
7272                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7273         }
7274         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7275         I40E_WRITE_FLUSH(hw);
7276 }
7277
7278 /*
7279  * Get global configurations of hash function type and symmetric hash enable
7280  * per flow type (pctype). Note that global configuration means it affects all
7281  * the ports on the same NIC.
7282  */
7283 static int
7284 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7285                                    struct rte_eth_hash_global_conf *g_cfg)
7286 {
7287         uint32_t reg, mask = I40E_FLOW_TYPES;
7288         uint16_t i;
7289         enum i40e_filter_pctype pctype;
7290
7291         memset(g_cfg, 0, sizeof(*g_cfg));
7292         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7293         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7294                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7295         else
7296                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7297         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7298                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7299
7300         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7301                 if (!(mask & (1UL << i)))
7302                         continue;
7303                 mask &= ~(1UL << i);
7304                 /* Bit set indicats the coresponding flow type is supported */
7305                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7306                 /* if flowtype is invalid, continue */
7307                 if (!I40E_VALID_FLOW(i))
7308                         continue;
7309                 pctype = i40e_flowtype_to_pctype(i);
7310                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7311                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7312                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7313         }
7314
7315         return 0;
7316 }
7317
7318 static int
7319 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7320 {
7321         uint32_t i;
7322         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7323
7324         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7325                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7326                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7327                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7328                                                 g_cfg->hash_func);
7329                 return -EINVAL;
7330         }
7331
7332         /*
7333          * As i40e supports less than 32 flow types, only first 32 bits need to
7334          * be checked.
7335          */
7336         mask0 = g_cfg->valid_bit_mask[0];
7337         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7338                 if (i == 0) {
7339                         /* Check if any unsupported flow type configured */
7340                         if ((mask0 | i40e_mask) ^ i40e_mask)
7341                                 goto mask_err;
7342                 } else {
7343                         if (g_cfg->valid_bit_mask[i])
7344                                 goto mask_err;
7345                 }
7346         }
7347
7348         return 0;
7349
7350 mask_err:
7351         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7352
7353         return -EINVAL;
7354 }
7355
7356 /*
7357  * Set global configurations of hash function type and symmetric hash enable
7358  * per flow type (pctype). Note any modifying global configuration will affect
7359  * all the ports on the same NIC.
7360  */
7361 static int
7362 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7363                                    struct rte_eth_hash_global_conf *g_cfg)
7364 {
7365         int ret;
7366         uint16_t i;
7367         uint32_t reg;
7368         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7369         enum i40e_filter_pctype pctype;
7370
7371         /* Check the input parameters */
7372         ret = i40e_hash_global_config_check(g_cfg);
7373         if (ret < 0)
7374                 return ret;
7375
7376         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7377                 if (!(mask0 & (1UL << i)))
7378                         continue;
7379                 mask0 &= ~(1UL << i);
7380                 /* if flowtype is invalid, continue */
7381                 if (!I40E_VALID_FLOW(i))
7382                         continue;
7383                 pctype = i40e_flowtype_to_pctype(i);
7384                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7385                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7386                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7387         }
7388
7389         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7390         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7391                 /* Toeplitz */
7392                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7393                         PMD_DRV_LOG(DEBUG,
7394                                 "Hash function already set to Toeplitz");
7395                         goto out;
7396                 }
7397                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7398         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7399                 /* Simple XOR */
7400                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7401                         PMD_DRV_LOG(DEBUG,
7402                                 "Hash function already set to Simple XOR");
7403                         goto out;
7404                 }
7405                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7406         } else
7407                 /* Use the default, and keep it as it is */
7408                 goto out;
7409
7410         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7411
7412 out:
7413         I40E_WRITE_FLUSH(hw);
7414
7415         return 0;
7416 }
7417
7418 /**
7419  * Valid input sets for hash and flow director filters per PCTYPE
7420  */
7421 static uint64_t
7422 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7423                 enum rte_filter_type filter)
7424 {
7425         uint64_t valid;
7426
7427         static const uint64_t valid_hash_inset_table[] = {
7428                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7429                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7430                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7431                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7432                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7433                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7434                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7435                         I40E_INSET_FLEX_PAYLOAD,
7436                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7437                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7438                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7439                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7440                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7441                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7442                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7443                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7444                         I40E_INSET_FLEX_PAYLOAD,
7445                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7446                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7447                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7448                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7449                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7450                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7451                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7452                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7453                         I40E_INSET_FLEX_PAYLOAD,
7454                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7455                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7456                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7457                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7458                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7459                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7460                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7461                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7462                         I40E_INSET_FLEX_PAYLOAD,
7463                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7464                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7465                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7466                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7467                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7468                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7469                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7470                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7471                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7472                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7473                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7474                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7475                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7476                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7477                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7478                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7479                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7480                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7481                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7485                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7486                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7487                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7488                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7489                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7490                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7494                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7495                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7496                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7497                         I40E_INSET_FLEX_PAYLOAD,
7498                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7502                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7503                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7504                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7505                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7506                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7507                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7508                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7509                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7510                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7511                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7512                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7513                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7514                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7518                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7519                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7520                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7521                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7522                         I40E_INSET_FLEX_PAYLOAD,
7523                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7527                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7528                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7529                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7530                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7531                         I40E_INSET_FLEX_PAYLOAD,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7536                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7537                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7538                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7539                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7540                         I40E_INSET_FLEX_PAYLOAD,
7541                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7542                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7543                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7544                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7545                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7546                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7547                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7548                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7549                         I40E_INSET_FLEX_PAYLOAD,
7550                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7551                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7552                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7553                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7554                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7555                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7556                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7557                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7558                         I40E_INSET_FLEX_PAYLOAD,
7559                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7560                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7561                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7562                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7563                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7564                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7565                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7566                         I40E_INSET_FLEX_PAYLOAD,
7567                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7568                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7569                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7570                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7571                         I40E_INSET_FLEX_PAYLOAD,
7572         };
7573
7574         /**
7575          * Flow director supports only fields defined in
7576          * union rte_eth_fdir_flow.
7577          */
7578         static const uint64_t valid_fdir_inset_table[] = {
7579                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7580                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7581                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7582                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7583                 I40E_INSET_IPV4_TTL,
7584                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7585                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7587                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7588                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7589                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7590                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7591                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7592                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7593                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7594                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7595                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7597                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7598                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7599                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7602                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7603                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7604                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7606                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7607                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7608                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7609                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7610                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7611                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7612                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7613                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7614                 I40E_INSET_SCTP_VT,
7615                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7616                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7617                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7618                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7619                 I40E_INSET_IPV4_TTL,
7620                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7621                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7622                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7623                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7624                 I40E_INSET_IPV6_HOP_LIMIT,
7625                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7626                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7627                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7628                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7629                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7630                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7633                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7634                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7635                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7636                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7637                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7638                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7639                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7641                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7642                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7643                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7644                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7645                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7646                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7647                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7648                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7649                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7650                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7651                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7652                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7653                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7654                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7655                 I40E_INSET_SCTP_VT,
7656                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7657                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7658                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7659                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7660                 I40E_INSET_IPV6_HOP_LIMIT,
7661                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7662                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7663                 I40E_INSET_LAST_ETHER_TYPE,
7664         };
7665
7666         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7667                 return 0;
7668         if (filter == RTE_ETH_FILTER_HASH)
7669                 valid = valid_hash_inset_table[pctype];
7670         else
7671                 valid = valid_fdir_inset_table[pctype];
7672
7673         return valid;
7674 }
7675
7676 /**
7677  * Validate if the input set is allowed for a specific PCTYPE
7678  */
7679 static int
7680 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7681                 enum rte_filter_type filter, uint64_t inset)
7682 {
7683         uint64_t valid;
7684
7685         valid = i40e_get_valid_input_set(pctype, filter);
7686         if (inset & (~valid))
7687                 return -EINVAL;
7688
7689         return 0;
7690 }
7691
7692 /* default input set fields combination per pctype */
7693 uint64_t
7694 i40e_get_default_input_set(uint16_t pctype)
7695 {
7696         static const uint64_t default_inset_table[] = {
7697                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7698                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7699                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7700                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7701                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7702                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7703                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7704                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7705                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7706                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7707                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7708                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7709                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7710                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7711                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7712                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7713                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7714                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7715                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7716                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7717                         I40E_INSET_SCTP_VT,
7718                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7719                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7720                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7721                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7722                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7723                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7724                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7725                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7726                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7727                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7728                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7729                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7730                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7731                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7732                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7733                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7734                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7735                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7736                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7737                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7738                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7739                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7740                         I40E_INSET_SCTP_VT,
7741                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7742                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7743                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7744                         I40E_INSET_LAST_ETHER_TYPE,
7745         };
7746
7747         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7748                 return 0;
7749
7750         return default_inset_table[pctype];
7751 }
7752
7753 /**
7754  * Parse the input set from index to logical bit masks
7755  */
7756 static int
7757 i40e_parse_input_set(uint64_t *inset,
7758                      enum i40e_filter_pctype pctype,
7759                      enum rte_eth_input_set_field *field,
7760                      uint16_t size)
7761 {
7762         uint16_t i, j;
7763         int ret = -EINVAL;
7764
7765         static const struct {
7766                 enum rte_eth_input_set_field field;
7767                 uint64_t inset;
7768         } inset_convert_table[] = {
7769                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7770                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7771                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7772                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7773                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7774                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7775                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7776                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7777                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7778                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7779                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7780                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7781                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7782                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7783                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7784                         I40E_INSET_IPV6_NEXT_HDR},
7785                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7786                         I40E_INSET_IPV6_HOP_LIMIT},
7787                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7788                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7789                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7790                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7791                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7792                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7793                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7794                         I40E_INSET_SCTP_VT},
7795                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7796                         I40E_INSET_TUNNEL_DMAC},
7797                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7798                         I40E_INSET_VLAN_TUNNEL},
7799                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7800                         I40E_INSET_TUNNEL_ID},
7801                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7802                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7803                         I40E_INSET_FLEX_PAYLOAD_W1},
7804                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7805                         I40E_INSET_FLEX_PAYLOAD_W2},
7806                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7807                         I40E_INSET_FLEX_PAYLOAD_W3},
7808                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7809                         I40E_INSET_FLEX_PAYLOAD_W4},
7810                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7811                         I40E_INSET_FLEX_PAYLOAD_W5},
7812                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7813                         I40E_INSET_FLEX_PAYLOAD_W6},
7814                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7815                         I40E_INSET_FLEX_PAYLOAD_W7},
7816                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7817                         I40E_INSET_FLEX_PAYLOAD_W8},
7818         };
7819
7820         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7821                 return ret;
7822
7823         /* Only one item allowed for default or all */
7824         if (size == 1) {
7825                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7826                         *inset = i40e_get_default_input_set(pctype);
7827                         return 0;
7828                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7829                         *inset = I40E_INSET_NONE;
7830                         return 0;
7831                 }
7832         }
7833
7834         for (i = 0, *inset = 0; i < size; i++) {
7835                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7836                         if (field[i] == inset_convert_table[j].field) {
7837                                 *inset |= inset_convert_table[j].inset;
7838                                 break;
7839                         }
7840                 }
7841
7842                 /* It contains unsupported input set, return immediately */
7843                 if (j == RTE_DIM(inset_convert_table))
7844                         return ret;
7845         }
7846
7847         return 0;
7848 }
7849
7850 /**
7851  * Translate the input set from bit masks to register aware bit masks
7852  * and vice versa
7853  */
7854 static uint64_t
7855 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7856 {
7857         uint64_t val = 0;
7858         uint16_t i;
7859
7860         struct inset_map {
7861                 uint64_t inset;
7862                 uint64_t inset_reg;
7863         };
7864
7865         static const struct inset_map inset_map_common[] = {
7866                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7867                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7868                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7869                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7870                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7871                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7872                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7873                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7874                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7875                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7876                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7877                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7878                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7879                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7880                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7881                 {I40E_INSET_TUNNEL_DMAC,
7882                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7883                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7884                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7885                 {I40E_INSET_TUNNEL_SRC_PORT,
7886                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7887                 {I40E_INSET_TUNNEL_DST_PORT,
7888                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7889                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7890                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7891                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7892                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7893                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7894                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7895                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7896                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7897                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7898         };
7899
7900     /* some different registers map in x722*/
7901         static const struct inset_map inset_map_diff_x722[] = {
7902                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7903                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7904                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7905                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7906         };
7907
7908         static const struct inset_map inset_map_diff_not_x722[] = {
7909                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7910                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7911                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7912                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7913         };
7914
7915         if (input == 0)
7916                 return val;
7917
7918         /* Translate input set to register aware inset */
7919         if (type == I40E_MAC_X722) {
7920                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7921                         if (input & inset_map_diff_x722[i].inset)
7922                                 val |= inset_map_diff_x722[i].inset_reg;
7923                 }
7924         } else {
7925                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7926                         if (input & inset_map_diff_not_x722[i].inset)
7927                                 val |= inset_map_diff_not_x722[i].inset_reg;
7928                 }
7929         }
7930
7931         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7932                 if (input & inset_map_common[i].inset)
7933                         val |= inset_map_common[i].inset_reg;
7934         }
7935
7936         return val;
7937 }
7938
7939 static int
7940 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7941 {
7942         uint8_t i, idx = 0;
7943         uint64_t inset_need_mask = inset;
7944
7945         static const struct {
7946                 uint64_t inset;
7947                 uint32_t mask;
7948         } inset_mask_map[] = {
7949                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7950                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7951                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7952                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7953                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7954                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7955                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7956                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7957         };
7958
7959         if (!inset || !mask || !nb_elem)
7960                 return 0;
7961
7962         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7963                 /* Clear the inset bit, if no MASK is required,
7964                  * for example proto + ttl
7965                  */
7966                 if ((inset & inset_mask_map[i].inset) ==
7967                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7968                         inset_need_mask &= ~inset_mask_map[i].inset;
7969                 if (!inset_need_mask)
7970                         return 0;
7971         }
7972         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7973                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7974                     inset_mask_map[i].inset) {
7975                         if (idx >= nb_elem) {
7976                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7977                                 return -EINVAL;
7978                         }
7979                         mask[idx] = inset_mask_map[i].mask;
7980                         idx++;
7981                 }
7982         }
7983
7984         return idx;
7985 }
7986
7987 static void
7988 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7989 {
7990         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7991
7992         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7993         if (reg != val)
7994                 i40e_write_rx_ctl(hw, addr, val);
7995         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7996                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7997 }
7998
7999 static void
8000 i40e_filter_input_set_init(struct i40e_pf *pf)
8001 {
8002         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8003         enum i40e_filter_pctype pctype;
8004         uint64_t input_set, inset_reg;
8005         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8006         int num, i;
8007
8008         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8009              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8010                 if (hw->mac.type == I40E_MAC_X722) {
8011                         if (!I40E_VALID_PCTYPE_X722(pctype))
8012                                 continue;
8013                 } else {
8014                         if (!I40E_VALID_PCTYPE(pctype))
8015                                 continue;
8016                 }
8017
8018                 input_set = i40e_get_default_input_set(pctype);
8019
8020                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8021                                                    I40E_INSET_MASK_NUM_REG);
8022                 if (num < 0)
8023                         return;
8024                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8025                                         input_set);
8026
8027                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8028                                       (uint32_t)(inset_reg & UINT32_MAX));
8029                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8030                                      (uint32_t)((inset_reg >>
8031                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8032                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8033                                       (uint32_t)(inset_reg & UINT32_MAX));
8034                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8035                                      (uint32_t)((inset_reg >>
8036                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8037
8038                 for (i = 0; i < num; i++) {
8039                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8040                                              mask_reg[i]);
8041                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8042                                              mask_reg[i]);
8043                 }
8044                 /*clear unused mask registers of the pctype */
8045                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8046                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8047                                              0);
8048                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8049                                              0);
8050                 }
8051                 I40E_WRITE_FLUSH(hw);
8052
8053                 /* store the default input set */
8054                 pf->hash_input_set[pctype] = input_set;
8055                 pf->fdir.input_set[pctype] = input_set;
8056         }
8057 }
8058
8059 int
8060 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8061                          struct rte_eth_input_set_conf *conf)
8062 {
8063         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8064         enum i40e_filter_pctype pctype;
8065         uint64_t input_set, inset_reg = 0;
8066         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8067         int ret, i, num;
8068
8069         if (!conf) {
8070                 PMD_DRV_LOG(ERR, "Invalid pointer");
8071                 return -EFAULT;
8072         }
8073         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8074             conf->op != RTE_ETH_INPUT_SET_ADD) {
8075                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8076                 return -EINVAL;
8077         }
8078
8079         if (!I40E_VALID_FLOW(conf->flow_type)) {
8080                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8081                 return -EINVAL;
8082         }
8083
8084         if (hw->mac.type == I40E_MAC_X722) {
8085                 /* get translated pctype value in fd pctype register */
8086                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8087                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8088                         conf->flow_type)));
8089         } else
8090                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8091
8092         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8093                                    conf->inset_size);
8094         if (ret) {
8095                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8096                 return -EINVAL;
8097         }
8098         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8099                                     input_set) != 0) {
8100                 PMD_DRV_LOG(ERR, "Invalid input set");
8101                 return -EINVAL;
8102         }
8103         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8104                 /* get inset value in register */
8105                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8106                 inset_reg <<= I40E_32_BIT_WIDTH;
8107                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8108                 input_set |= pf->hash_input_set[pctype];
8109         }
8110         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8111                                            I40E_INSET_MASK_NUM_REG);
8112         if (num < 0)
8113                 return -EINVAL;
8114
8115         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8116
8117         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8118                               (uint32_t)(inset_reg & UINT32_MAX));
8119         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8120                              (uint32_t)((inset_reg >>
8121                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8122
8123         for (i = 0; i < num; i++)
8124                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8125                                      mask_reg[i]);
8126         /*clear unused mask registers of the pctype */
8127         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8128                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8129                                      0);
8130         I40E_WRITE_FLUSH(hw);
8131
8132         pf->hash_input_set[pctype] = input_set;
8133         return 0;
8134 }
8135
8136 int
8137 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8138                          struct rte_eth_input_set_conf *conf)
8139 {
8140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8141         enum i40e_filter_pctype pctype;
8142         uint64_t input_set, inset_reg = 0;
8143         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8144         int ret, i, num;
8145
8146         if (!hw || !conf) {
8147                 PMD_DRV_LOG(ERR, "Invalid pointer");
8148                 return -EFAULT;
8149         }
8150         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8151             conf->op != RTE_ETH_INPUT_SET_ADD) {
8152                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8153                 return -EINVAL;
8154         }
8155
8156         if (!I40E_VALID_FLOW(conf->flow_type)) {
8157                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8158                 return -EINVAL;
8159         }
8160
8161         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8162
8163         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8164                                    conf->inset_size);
8165         if (ret) {
8166                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8167                 return -EINVAL;
8168         }
8169         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8170                                     input_set) != 0) {
8171                 PMD_DRV_LOG(ERR, "Invalid input set");
8172                 return -EINVAL;
8173         }
8174
8175         /* get inset value in register */
8176         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8177         inset_reg <<= I40E_32_BIT_WIDTH;
8178         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8179
8180         /* Can not change the inset reg for flex payload for fdir,
8181          * it is done by writing I40E_PRTQF_FD_FLXINSET
8182          * in i40e_set_flex_mask_on_pctype.
8183          */
8184         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8185                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8186         else
8187                 input_set |= pf->fdir.input_set[pctype];
8188         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8189                                            I40E_INSET_MASK_NUM_REG);
8190         if (num < 0)
8191                 return -EINVAL;
8192
8193         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8194
8195         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8196                               (uint32_t)(inset_reg & UINT32_MAX));
8197         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8198                              (uint32_t)((inset_reg >>
8199                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8200
8201         for (i = 0; i < num; i++)
8202                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8203                                      mask_reg[i]);
8204         /*clear unused mask registers of the pctype */
8205         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8206                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8207                                      0);
8208         I40E_WRITE_FLUSH(hw);
8209
8210         pf->fdir.input_set[pctype] = input_set;
8211         return 0;
8212 }
8213
8214 static int
8215 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8216 {
8217         int ret = 0;
8218
8219         if (!hw || !info) {
8220                 PMD_DRV_LOG(ERR, "Invalid pointer");
8221                 return -EFAULT;
8222         }
8223
8224         switch (info->info_type) {
8225         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8226                 i40e_get_symmetric_hash_enable_per_port(hw,
8227                                         &(info->info.enable));
8228                 break;
8229         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8230                 ret = i40e_get_hash_filter_global_config(hw,
8231                                 &(info->info.global_conf));
8232                 break;
8233         default:
8234                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8235                                                         info->info_type);
8236                 ret = -EINVAL;
8237                 break;
8238         }
8239
8240         return ret;
8241 }
8242
8243 static int
8244 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8245 {
8246         int ret = 0;
8247
8248         if (!hw || !info) {
8249                 PMD_DRV_LOG(ERR, "Invalid pointer");
8250                 return -EFAULT;
8251         }
8252
8253         switch (info->info_type) {
8254         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8255                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8256                 break;
8257         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8258                 ret = i40e_set_hash_filter_global_config(hw,
8259                                 &(info->info.global_conf));
8260                 break;
8261         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8262                 ret = i40e_hash_filter_inset_select(hw,
8263                                                &(info->info.input_set_conf));
8264                 break;
8265
8266         default:
8267                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8268                                                         info->info_type);
8269                 ret = -EINVAL;
8270                 break;
8271         }
8272
8273         return ret;
8274 }
8275
8276 /* Operations for hash function */
8277 static int
8278 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8279                       enum rte_filter_op filter_op,
8280                       void *arg)
8281 {
8282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8283         int ret = 0;
8284
8285         switch (filter_op) {
8286         case RTE_ETH_FILTER_NOP:
8287                 break;
8288         case RTE_ETH_FILTER_GET:
8289                 ret = i40e_hash_filter_get(hw,
8290                         (struct rte_eth_hash_filter_info *)arg);
8291                 break;
8292         case RTE_ETH_FILTER_SET:
8293                 ret = i40e_hash_filter_set(hw,
8294                         (struct rte_eth_hash_filter_info *)arg);
8295                 break;
8296         default:
8297                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8298                                                                 filter_op);
8299                 ret = -ENOTSUP;
8300                 break;
8301         }
8302
8303         return ret;
8304 }
8305
8306 /* Convert ethertype filter structure */
8307 static int
8308 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8309                               struct i40e_ethertype_filter *filter)
8310 {
8311         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8312         filter->input.ether_type = input->ether_type;
8313         filter->flags = input->flags;
8314         filter->queue = input->queue;
8315
8316         return 0;
8317 }
8318
8319 /* Check if there exists the ehtertype filter */
8320 struct i40e_ethertype_filter *
8321 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8322                                 const struct i40e_ethertype_filter_input *input)
8323 {
8324         int ret;
8325
8326         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8327         if (ret < 0)
8328                 return NULL;
8329
8330         return ethertype_rule->hash_map[ret];
8331 }
8332
8333 /* Add ethertype filter in SW list */
8334 static int
8335 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8336                                 struct i40e_ethertype_filter *filter)
8337 {
8338         struct i40e_ethertype_rule *rule = &pf->ethertype;
8339         int ret;
8340
8341         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8342         if (ret < 0) {
8343                 PMD_DRV_LOG(ERR,
8344                             "Failed to insert ethertype filter"
8345                             " to hash table %d!",
8346                             ret);
8347                 return ret;
8348         }
8349         rule->hash_map[ret] = filter;
8350
8351         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8352
8353         return 0;
8354 }
8355
8356 /* Delete ethertype filter in SW list */
8357 int
8358 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8359                              struct i40e_ethertype_filter_input *input)
8360 {
8361         struct i40e_ethertype_rule *rule = &pf->ethertype;
8362         struct i40e_ethertype_filter *filter;
8363         int ret;
8364
8365         ret = rte_hash_del_key(rule->hash_table, input);
8366         if (ret < 0) {
8367                 PMD_DRV_LOG(ERR,
8368                             "Failed to delete ethertype filter"
8369                             " to hash table %d!",
8370                             ret);
8371                 return ret;
8372         }
8373         filter = rule->hash_map[ret];
8374         rule->hash_map[ret] = NULL;
8375
8376         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8377         rte_free(filter);
8378
8379         return 0;
8380 }
8381
8382 /*
8383  * Configure ethertype filter, which can director packet by filtering
8384  * with mac address and ether_type or only ether_type
8385  */
8386 int
8387 i40e_ethertype_filter_set(struct i40e_pf *pf,
8388                         struct rte_eth_ethertype_filter *filter,
8389                         bool add)
8390 {
8391         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8392         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8393         struct i40e_ethertype_filter *ethertype_filter, *node;
8394         struct i40e_ethertype_filter check_filter;
8395         struct i40e_control_filter_stats stats;
8396         uint16_t flags = 0;
8397         int ret;
8398
8399         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8400                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8401                 return -EINVAL;
8402         }
8403         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8404                 filter->ether_type == ETHER_TYPE_IPv6) {
8405                 PMD_DRV_LOG(ERR,
8406                         "unsupported ether_type(0x%04x) in control packet filter.",
8407                         filter->ether_type);
8408                 return -EINVAL;
8409         }
8410         if (filter->ether_type == ETHER_TYPE_VLAN)
8411                 PMD_DRV_LOG(WARNING,
8412                         "filter vlan ether_type in first tag is not supported.");
8413
8414         /* Check if there is the filter in SW list */
8415         memset(&check_filter, 0, sizeof(check_filter));
8416         i40e_ethertype_filter_convert(filter, &check_filter);
8417         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8418                                                &check_filter.input);
8419         if (add && node) {
8420                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8421                 return -EINVAL;
8422         }
8423
8424         if (!add && !node) {
8425                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8426                 return -EINVAL;
8427         }
8428
8429         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8430                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8431         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8432                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8433         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8434
8435         memset(&stats, 0, sizeof(stats));
8436         ret = i40e_aq_add_rem_control_packet_filter(hw,
8437                         filter->mac_addr.addr_bytes,
8438                         filter->ether_type, flags,
8439                         pf->main_vsi->seid,
8440                         filter->queue, add, &stats, NULL);
8441
8442         PMD_DRV_LOG(INFO,
8443                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u\n",
8444                 ret, stats.mac_etype_used, stats.etype_used,
8445                 stats.mac_etype_free, stats.etype_free);
8446         if (ret < 0)
8447                 return -ENOSYS;
8448
8449         /* Add or delete a filter in SW list */
8450         if (add) {
8451                 ethertype_filter = rte_zmalloc("ethertype_filter",
8452                                        sizeof(*ethertype_filter), 0);
8453                 rte_memcpy(ethertype_filter, &check_filter,
8454                            sizeof(check_filter));
8455                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8456         } else {
8457                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8458         }
8459
8460         return ret;
8461 }
8462
8463 /*
8464  * Handle operations for ethertype filter.
8465  */
8466 static int
8467 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8468                                 enum rte_filter_op filter_op,
8469                                 void *arg)
8470 {
8471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8472         int ret = 0;
8473
8474         if (filter_op == RTE_ETH_FILTER_NOP)
8475                 return ret;
8476
8477         if (arg == NULL) {
8478                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8479                             filter_op);
8480                 return -EINVAL;
8481         }
8482
8483         switch (filter_op) {
8484         case RTE_ETH_FILTER_ADD:
8485                 ret = i40e_ethertype_filter_set(pf,
8486                         (struct rte_eth_ethertype_filter *)arg,
8487                         TRUE);
8488                 break;
8489         case RTE_ETH_FILTER_DELETE:
8490                 ret = i40e_ethertype_filter_set(pf,
8491                         (struct rte_eth_ethertype_filter *)arg,
8492                         FALSE);
8493                 break;
8494         default:
8495                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8496                 ret = -ENOSYS;
8497                 break;
8498         }
8499         return ret;
8500 }
8501
8502 static int
8503 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8504                      enum rte_filter_type filter_type,
8505                      enum rte_filter_op filter_op,
8506                      void *arg)
8507 {
8508         int ret = 0;
8509
8510         if (dev == NULL)
8511                 return -EINVAL;
8512
8513         switch (filter_type) {
8514         case RTE_ETH_FILTER_NONE:
8515                 /* For global configuration */
8516                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8517                 break;
8518         case RTE_ETH_FILTER_HASH:
8519                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8520                 break;
8521         case RTE_ETH_FILTER_MACVLAN:
8522                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8523                 break;
8524         case RTE_ETH_FILTER_ETHERTYPE:
8525                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8526                 break;
8527         case RTE_ETH_FILTER_TUNNEL:
8528                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8529                 break;
8530         case RTE_ETH_FILTER_FDIR:
8531                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8532                 break;
8533         case RTE_ETH_FILTER_GENERIC:
8534                 if (filter_op != RTE_ETH_FILTER_GET)
8535                         return -EINVAL;
8536                 *(const void **)arg = &i40e_flow_ops;
8537                 break;
8538         default:
8539                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8540                                                         filter_type);
8541                 ret = -EINVAL;
8542                 break;
8543         }
8544
8545         return ret;
8546 }
8547
8548 /*
8549  * Check and enable Extended Tag.
8550  * Enabling Extended Tag is important for 40G performance.
8551  */
8552 static void
8553 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8554 {
8555         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8556         uint32_t buf = 0;
8557         int ret;
8558
8559         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8560                                       PCI_DEV_CAP_REG);
8561         if (ret < 0) {
8562                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8563                             PCI_DEV_CAP_REG);
8564                 return;
8565         }
8566         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8567                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8568                 return;
8569         }
8570
8571         buf = 0;
8572         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8573                                       PCI_DEV_CTRL_REG);
8574         if (ret < 0) {
8575                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8576                             PCI_DEV_CTRL_REG);
8577                 return;
8578         }
8579         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8580                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8581                 return;
8582         }
8583         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8584         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8585                                        PCI_DEV_CTRL_REG);
8586         if (ret < 0) {
8587                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8588                             PCI_DEV_CTRL_REG);
8589                 return;
8590         }
8591 }
8592
8593 /*
8594  * As some registers wouldn't be reset unless a global hardware reset,
8595  * hardware initialization is needed to put those registers into an
8596  * expected initial state.
8597  */
8598 static void
8599 i40e_hw_init(struct rte_eth_dev *dev)
8600 {
8601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8602
8603         i40e_enable_extended_tag(dev);
8604
8605         /* clear the PF Queue Filter control register */
8606         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8607
8608         /* Disable symmetric hash per port */
8609         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8610 }
8611
8612 enum i40e_filter_pctype
8613 i40e_flowtype_to_pctype(uint16_t flow_type)
8614 {
8615         static const enum i40e_filter_pctype pctype_table[] = {
8616                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8617                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8618                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8619                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8620                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8621                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8622                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8623                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8624                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8625                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8626                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8627                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8628                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8629                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8630                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8631                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8632                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8633                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8634                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8635         };
8636
8637         return pctype_table[flow_type];
8638 }
8639
8640 uint16_t
8641 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8642 {
8643         static const uint16_t flowtype_table[] = {
8644                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8645                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8646                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8647                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8648                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8649                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8650                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8651                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8652                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8653                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8654                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8655                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8656                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8657                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8658                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8659                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8660                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8661                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8662                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8663                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8664                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8665                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8666                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8667                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8668                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8669                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8670                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8671                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8672                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8673                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8674                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8675         };
8676
8677         return flowtype_table[pctype];
8678 }
8679
8680 /*
8681  * On X710, performance number is far from the expectation on recent firmware
8682  * versions; on XL710, performance number is also far from the expectation on
8683  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8684  * mode is enabled and port MAC address is equal to the packet destination MAC
8685  * address. The fix for this issue may not be integrated in the following
8686  * firmware version. So the workaround in software driver is needed. It needs
8687  * to modify the initial values of 3 internal only registers for both X710 and
8688  * XL710. Note that the values for X710 or XL710 could be different, and the
8689  * workaround can be removed when it is fixed in firmware in the future.
8690  */
8691
8692 /* For both X710 and XL710 */
8693 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8694 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8695
8696 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8697 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8698
8699 /* For X710 */
8700 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8701 /* For XL710 */
8702 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8703 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8704
8705 static int
8706 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8707 {
8708         enum i40e_status_code status;
8709         struct i40e_aq_get_phy_abilities_resp phy_ab;
8710         int ret = -ENOTSUP;
8711
8712         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8713                                               NULL);
8714
8715         if (status)
8716                 return ret;
8717
8718         return 0;
8719 }
8720
8721
8722 static void
8723 i40e_configure_registers(struct i40e_hw *hw)
8724 {
8725         static struct {
8726                 uint32_t addr;
8727                 uint64_t val;
8728         } reg_table[] = {
8729                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8730                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8731                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8732         };
8733         uint64_t reg;
8734         uint32_t i;
8735         int ret;
8736
8737         for (i = 0; i < RTE_DIM(reg_table); i++) {
8738                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8739                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8740                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8741                                 reg_table[i].val =
8742                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8743                         else /* For X710 */
8744                                 reg_table[i].val =
8745                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8746                 }
8747
8748                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8749                                                         &reg, NULL);
8750                 if (ret < 0) {
8751                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8752                                                         reg_table[i].addr);
8753                         break;
8754                 }
8755                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8756                                                 reg_table[i].addr, reg);
8757                 if (reg == reg_table[i].val)
8758                         continue;
8759
8760                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8761                                                 reg_table[i].val, NULL);
8762                 if (ret < 0) {
8763                         PMD_DRV_LOG(ERR,
8764                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8765                                 reg_table[i].val, reg_table[i].addr);
8766                         break;
8767                 }
8768                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8769                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8770         }
8771 }
8772
8773 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8774 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8775 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8776 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8777 static int
8778 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8779 {
8780         uint32_t reg;
8781         int ret;
8782
8783         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8784                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8785                 return -EINVAL;
8786         }
8787
8788         /* Configure for double VLAN RX stripping */
8789         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8790         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8791                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8792                 ret = i40e_aq_debug_write_register(hw,
8793                                                    I40E_VSI_TSR(vsi->vsi_id),
8794                                                    reg, NULL);
8795                 if (ret < 0) {
8796                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8797                                     vsi->vsi_id);
8798                         return I40E_ERR_CONFIG;
8799                 }
8800         }
8801
8802         /* Configure for double VLAN TX insertion */
8803         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8804         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8805                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8806                 ret = i40e_aq_debug_write_register(hw,
8807                                                    I40E_VSI_L2TAGSTXVALID(
8808                                                    vsi->vsi_id), reg, NULL);
8809                 if (ret < 0) {
8810                         PMD_DRV_LOG(ERR,
8811                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8812                                 vsi->vsi_id);
8813                         return I40E_ERR_CONFIG;
8814                 }
8815         }
8816
8817         return 0;
8818 }
8819
8820 /**
8821  * i40e_aq_add_mirror_rule
8822  * @hw: pointer to the hardware structure
8823  * @seid: VEB seid to add mirror rule to
8824  * @dst_id: destination vsi seid
8825  * @entries: Buffer which contains the entities to be mirrored
8826  * @count: number of entities contained in the buffer
8827  * @rule_id:the rule_id of the rule to be added
8828  *
8829  * Add a mirror rule for a given veb.
8830  *
8831  **/
8832 static enum i40e_status_code
8833 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8834                         uint16_t seid, uint16_t dst_id,
8835                         uint16_t rule_type, uint16_t *entries,
8836                         uint16_t count, uint16_t *rule_id)
8837 {
8838         struct i40e_aq_desc desc;
8839         struct i40e_aqc_add_delete_mirror_rule cmd;
8840         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8841                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8842                 &desc.params.raw;
8843         uint16_t buff_len;
8844         enum i40e_status_code status;
8845
8846         i40e_fill_default_direct_cmd_desc(&desc,
8847                                           i40e_aqc_opc_add_mirror_rule);
8848         memset(&cmd, 0, sizeof(cmd));
8849
8850         buff_len = sizeof(uint16_t) * count;
8851         desc.datalen = rte_cpu_to_le_16(buff_len);
8852         if (buff_len > 0)
8853                 desc.flags |= rte_cpu_to_le_16(
8854                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8855         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8856                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8857         cmd.num_entries = rte_cpu_to_le_16(count);
8858         cmd.seid = rte_cpu_to_le_16(seid);
8859         cmd.destination = rte_cpu_to_le_16(dst_id);
8860
8861         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8862         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8863         PMD_DRV_LOG(INFO,
8864                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8865                 hw->aq.asq_last_status, resp->rule_id,
8866                 resp->mirror_rules_used, resp->mirror_rules_free);
8867         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8868
8869         return status;
8870 }
8871
8872 /**
8873  * i40e_aq_del_mirror_rule
8874  * @hw: pointer to the hardware structure
8875  * @seid: VEB seid to add mirror rule to
8876  * @entries: Buffer which contains the entities to be mirrored
8877  * @count: number of entities contained in the buffer
8878  * @rule_id:the rule_id of the rule to be delete
8879  *
8880  * Delete a mirror rule for a given veb.
8881  *
8882  **/
8883 static enum i40e_status_code
8884 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8885                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8886                 uint16_t count, uint16_t rule_id)
8887 {
8888         struct i40e_aq_desc desc;
8889         struct i40e_aqc_add_delete_mirror_rule cmd;
8890         uint16_t buff_len = 0;
8891         enum i40e_status_code status;
8892         void *buff = NULL;
8893
8894         i40e_fill_default_direct_cmd_desc(&desc,
8895                                           i40e_aqc_opc_delete_mirror_rule);
8896         memset(&cmd, 0, sizeof(cmd));
8897         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8898                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8899                                                           I40E_AQ_FLAG_RD));
8900                 cmd.num_entries = count;
8901                 buff_len = sizeof(uint16_t) * count;
8902                 desc.datalen = rte_cpu_to_le_16(buff_len);
8903                 buff = (void *)entries;
8904         } else
8905                 /* rule id is filled in destination field for deleting mirror rule */
8906                 cmd.destination = rte_cpu_to_le_16(rule_id);
8907
8908         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8909                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8910         cmd.seid = rte_cpu_to_le_16(seid);
8911
8912         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8913         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8914
8915         return status;
8916 }
8917
8918 /**
8919  * i40e_mirror_rule_set
8920  * @dev: pointer to the hardware structure
8921  * @mirror_conf: mirror rule info
8922  * @sw_id: mirror rule's sw_id
8923  * @on: enable/disable
8924  *
8925  * set a mirror rule.
8926  *
8927  **/
8928 static int
8929 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8930                         struct rte_eth_mirror_conf *mirror_conf,
8931                         uint8_t sw_id, uint8_t on)
8932 {
8933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8935         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8936         struct i40e_mirror_rule *parent = NULL;
8937         uint16_t seid, dst_seid, rule_id;
8938         uint16_t i, j = 0;
8939         int ret;
8940
8941         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8942
8943         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8944                 PMD_DRV_LOG(ERR,
8945                         "mirror rule can not be configured without veb or vfs.");
8946                 return -ENOSYS;
8947         }
8948         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8949                 PMD_DRV_LOG(ERR, "mirror table is full.");
8950                 return -ENOSPC;
8951         }
8952         if (mirror_conf->dst_pool > pf->vf_num) {
8953                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8954                                  mirror_conf->dst_pool);
8955                 return -EINVAL;
8956         }
8957
8958         seid = pf->main_vsi->veb->seid;
8959
8960         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8961                 if (sw_id <= it->index) {
8962                         mirr_rule = it;
8963                         break;
8964                 }
8965                 parent = it;
8966         }
8967         if (mirr_rule && sw_id == mirr_rule->index) {
8968                 if (on) {
8969                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8970                         return -EEXIST;
8971                 } else {
8972                         ret = i40e_aq_del_mirror_rule(hw, seid,
8973                                         mirr_rule->rule_type,
8974                                         mirr_rule->entries,
8975                                         mirr_rule->num_entries, mirr_rule->id);
8976                         if (ret < 0) {
8977                                 PMD_DRV_LOG(ERR,
8978                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
8979                                         ret, hw->aq.asq_last_status);
8980                                 return -ENOSYS;
8981                         }
8982                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8983                         rte_free(mirr_rule);
8984                         pf->nb_mirror_rule--;
8985                         return 0;
8986                 }
8987         } else if (!on) {
8988                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8989                 return -ENOENT;
8990         }
8991
8992         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8993                                 sizeof(struct i40e_mirror_rule) , 0);
8994         if (!mirr_rule) {
8995                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8996                 return I40E_ERR_NO_MEMORY;
8997         }
8998         switch (mirror_conf->rule_type) {
8999         case ETH_MIRROR_VLAN:
9000                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9001                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9002                                 mirr_rule->entries[j] =
9003                                         mirror_conf->vlan.vlan_id[i];
9004                                 j++;
9005                         }
9006                 }
9007                 if (j == 0) {
9008                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9009                         rte_free(mirr_rule);
9010                         return -EINVAL;
9011                 }
9012                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9013                 break;
9014         case ETH_MIRROR_VIRTUAL_POOL_UP:
9015         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9016                 /* check if the specified pool bit is out of range */
9017                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9018                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9019                         rte_free(mirr_rule);
9020                         return -EINVAL;
9021                 }
9022                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9023                         if (mirror_conf->pool_mask & (1ULL << i)) {
9024                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9025                                 j++;
9026                         }
9027                 }
9028                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9029                         /* add pf vsi to entries */
9030                         mirr_rule->entries[j] = pf->main_vsi_seid;
9031                         j++;
9032                 }
9033                 if (j == 0) {
9034                         PMD_DRV_LOG(ERR, "pool is not specified.");
9035                         rte_free(mirr_rule);
9036                         return -EINVAL;
9037                 }
9038                 /* egress and ingress in aq commands means from switch but not port */
9039                 mirr_rule->rule_type =
9040                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9041                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9042                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9043                 break;
9044         case ETH_MIRROR_UPLINK_PORT:
9045                 /* egress and ingress in aq commands means from switch but not port*/
9046                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9047                 break;
9048         case ETH_MIRROR_DOWNLINK_PORT:
9049                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9050                 break;
9051         default:
9052                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9053                         mirror_conf->rule_type);
9054                 rte_free(mirr_rule);
9055                 return -EINVAL;
9056         }
9057
9058         /* If the dst_pool is equal to vf_num, consider it as PF */
9059         if (mirror_conf->dst_pool == pf->vf_num)
9060                 dst_seid = pf->main_vsi_seid;
9061         else
9062                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9063
9064         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9065                                       mirr_rule->rule_type, mirr_rule->entries,
9066                                       j, &rule_id);
9067         if (ret < 0) {
9068                 PMD_DRV_LOG(ERR,
9069                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9070                         ret, hw->aq.asq_last_status);
9071                 rte_free(mirr_rule);
9072                 return -ENOSYS;
9073         }
9074
9075         mirr_rule->index = sw_id;
9076         mirr_rule->num_entries = j;
9077         mirr_rule->id = rule_id;
9078         mirr_rule->dst_vsi_seid = dst_seid;
9079
9080         if (parent)
9081                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9082         else
9083                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9084
9085         pf->nb_mirror_rule++;
9086         return 0;
9087 }
9088
9089 /**
9090  * i40e_mirror_rule_reset
9091  * @dev: pointer to the device
9092  * @sw_id: mirror rule's sw_id
9093  *
9094  * reset a mirror rule.
9095  *
9096  **/
9097 static int
9098 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9099 {
9100         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9102         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9103         uint16_t seid;
9104         int ret;
9105
9106         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9107
9108         seid = pf->main_vsi->veb->seid;
9109
9110         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9111                 if (sw_id == it->index) {
9112                         mirr_rule = it;
9113                         break;
9114                 }
9115         }
9116         if (mirr_rule) {
9117                 ret = i40e_aq_del_mirror_rule(hw, seid,
9118                                 mirr_rule->rule_type,
9119                                 mirr_rule->entries,
9120                                 mirr_rule->num_entries, mirr_rule->id);
9121                 if (ret < 0) {
9122                         PMD_DRV_LOG(ERR,
9123                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9124                                 ret, hw->aq.asq_last_status);
9125                         return -ENOSYS;
9126                 }
9127                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9128                 rte_free(mirr_rule);
9129                 pf->nb_mirror_rule--;
9130         } else {
9131                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9132                 return -ENOENT;
9133         }
9134         return 0;
9135 }
9136
9137 static uint64_t
9138 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9139 {
9140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9141         uint64_t systim_cycles;
9142
9143         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9144         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9145                         << 32;
9146
9147         return systim_cycles;
9148 }
9149
9150 static uint64_t
9151 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9152 {
9153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9154         uint64_t rx_tstamp;
9155
9156         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9157         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9158                         << 32;
9159
9160         return rx_tstamp;
9161 }
9162
9163 static uint64_t
9164 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9165 {
9166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9167         uint64_t tx_tstamp;
9168
9169         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9170         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9171                         << 32;
9172
9173         return tx_tstamp;
9174 }
9175
9176 static void
9177 i40e_start_timecounters(struct rte_eth_dev *dev)
9178 {
9179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9180         struct i40e_adapter *adapter =
9181                         (struct i40e_adapter *)dev->data->dev_private;
9182         struct rte_eth_link link;
9183         uint32_t tsync_inc_l;
9184         uint32_t tsync_inc_h;
9185
9186         /* Get current link speed. */
9187         memset(&link, 0, sizeof(link));
9188         i40e_dev_link_update(dev, 1);
9189         rte_i40e_dev_atomic_read_link_status(dev, &link);
9190
9191         switch (link.link_speed) {
9192         case ETH_SPEED_NUM_40G:
9193                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9194                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9195                 break;
9196         case ETH_SPEED_NUM_10G:
9197                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9198                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9199                 break;
9200         case ETH_SPEED_NUM_1G:
9201                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9202                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9203                 break;
9204         default:
9205                 tsync_inc_l = 0x0;
9206                 tsync_inc_h = 0x0;
9207         }
9208
9209         /* Set the timesync increment value. */
9210         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9211         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9212
9213         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9214         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9215         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9216
9217         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9218         adapter->systime_tc.cc_shift = 0;
9219         adapter->systime_tc.nsec_mask = 0;
9220
9221         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9222         adapter->rx_tstamp_tc.cc_shift = 0;
9223         adapter->rx_tstamp_tc.nsec_mask = 0;
9224
9225         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9226         adapter->tx_tstamp_tc.cc_shift = 0;
9227         adapter->tx_tstamp_tc.nsec_mask = 0;
9228 }
9229
9230 static int
9231 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9232 {
9233         struct i40e_adapter *adapter =
9234                         (struct i40e_adapter *)dev->data->dev_private;
9235
9236         adapter->systime_tc.nsec += delta;
9237         adapter->rx_tstamp_tc.nsec += delta;
9238         adapter->tx_tstamp_tc.nsec += delta;
9239
9240         return 0;
9241 }
9242
9243 static int
9244 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9245 {
9246         uint64_t ns;
9247         struct i40e_adapter *adapter =
9248                         (struct i40e_adapter *)dev->data->dev_private;
9249
9250         ns = rte_timespec_to_ns(ts);
9251
9252         /* Set the timecounters to a new value. */
9253         adapter->systime_tc.nsec = ns;
9254         adapter->rx_tstamp_tc.nsec = ns;
9255         adapter->tx_tstamp_tc.nsec = ns;
9256
9257         return 0;
9258 }
9259
9260 static int
9261 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9262 {
9263         uint64_t ns, systime_cycles;
9264         struct i40e_adapter *adapter =
9265                         (struct i40e_adapter *)dev->data->dev_private;
9266
9267         systime_cycles = i40e_read_systime_cyclecounter(dev);
9268         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9269         *ts = rte_ns_to_timespec(ns);
9270
9271         return 0;
9272 }
9273
9274 static int
9275 i40e_timesync_enable(struct rte_eth_dev *dev)
9276 {
9277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9278         uint32_t tsync_ctl_l;
9279         uint32_t tsync_ctl_h;
9280
9281         /* Stop the timesync system time. */
9282         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9283         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9284         /* Reset the timesync system time value. */
9285         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9286         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9287
9288         i40e_start_timecounters(dev);
9289
9290         /* Clear timesync registers. */
9291         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9292         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9293         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9294         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9295         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9296         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9297
9298         /* Enable timestamping of PTP packets. */
9299         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9300         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9301
9302         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9303         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9304         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9305
9306         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9307         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9308
9309         return 0;
9310 }
9311
9312 static int
9313 i40e_timesync_disable(struct rte_eth_dev *dev)
9314 {
9315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9316         uint32_t tsync_ctl_l;
9317         uint32_t tsync_ctl_h;
9318
9319         /* Disable timestamping of transmitted PTP packets. */
9320         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9321         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9322
9323         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9324         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9325
9326         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9327         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9328
9329         /* Reset the timesync increment value. */
9330         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9331         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9332
9333         return 0;
9334 }
9335
9336 static int
9337 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9338                                 struct timespec *timestamp, uint32_t flags)
9339 {
9340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9341         struct i40e_adapter *adapter =
9342                 (struct i40e_adapter *)dev->data->dev_private;
9343
9344         uint32_t sync_status;
9345         uint32_t index = flags & 0x03;
9346         uint64_t rx_tstamp_cycles;
9347         uint64_t ns;
9348
9349         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9350         if ((sync_status & (1 << index)) == 0)
9351                 return -EINVAL;
9352
9353         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9354         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9355         *timestamp = rte_ns_to_timespec(ns);
9356
9357         return 0;
9358 }
9359
9360 static int
9361 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9362                                 struct timespec *timestamp)
9363 {
9364         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9365         struct i40e_adapter *adapter =
9366                 (struct i40e_adapter *)dev->data->dev_private;
9367
9368         uint32_t sync_status;
9369         uint64_t tx_tstamp_cycles;
9370         uint64_t ns;
9371
9372         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9373         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9374                 return -EINVAL;
9375
9376         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9377         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9378         *timestamp = rte_ns_to_timespec(ns);
9379
9380         return 0;
9381 }
9382
9383 /*
9384  * i40e_parse_dcb_configure - parse dcb configure from user
9385  * @dev: the device being configured
9386  * @dcb_cfg: pointer of the result of parse
9387  * @*tc_map: bit map of enabled traffic classes
9388  *
9389  * Returns 0 on success, negative value on failure
9390  */
9391 static int
9392 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9393                          struct i40e_dcbx_config *dcb_cfg,
9394                          uint8_t *tc_map)
9395 {
9396         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9397         uint8_t i, tc_bw, bw_lf;
9398
9399         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9400
9401         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9402         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9403                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9404                 return -EINVAL;
9405         }
9406
9407         /* assume each tc has the same bw */
9408         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9409         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9410                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9411         /* to ensure the sum of tcbw is equal to 100 */
9412         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9413         for (i = 0; i < bw_lf; i++)
9414                 dcb_cfg->etscfg.tcbwtable[i]++;
9415
9416         /* assume each tc has the same Transmission Selection Algorithm */
9417         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9418                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9419
9420         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9421                 dcb_cfg->etscfg.prioritytable[i] =
9422                                 dcb_rx_conf->dcb_tc[i];
9423
9424         /* FW needs one App to configure HW */
9425         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9426         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9427         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9428         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9429
9430         if (dcb_rx_conf->nb_tcs == 0)
9431                 *tc_map = 1; /* tc0 only */
9432         else
9433                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9434
9435         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9436                 dcb_cfg->pfc.willing = 0;
9437                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9438                 dcb_cfg->pfc.pfcenable = *tc_map;
9439         }
9440         return 0;
9441 }
9442
9443
9444 static enum i40e_status_code
9445 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9446                               struct i40e_aqc_vsi_properties_data *info,
9447                               uint8_t enabled_tcmap)
9448 {
9449         enum i40e_status_code ret;
9450         int i, total_tc = 0;
9451         uint16_t qpnum_per_tc, bsf, qp_idx;
9452         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9453         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9454         uint16_t used_queues;
9455
9456         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9457         if (ret != I40E_SUCCESS)
9458                 return ret;
9459
9460         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9461                 if (enabled_tcmap & (1 << i))
9462                         total_tc++;
9463         }
9464         if (total_tc == 0)
9465                 total_tc = 1;
9466         vsi->enabled_tc = enabled_tcmap;
9467
9468         /* different VSI has different queues assigned */
9469         if (vsi->type == I40E_VSI_MAIN)
9470                 used_queues = dev_data->nb_rx_queues -
9471                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9472         else if (vsi->type == I40E_VSI_VMDQ2)
9473                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9474         else {
9475                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9476                 return I40E_ERR_NO_AVAILABLE_VSI;
9477         }
9478
9479         qpnum_per_tc = used_queues / total_tc;
9480         /* Number of queues per enabled TC */
9481         if (qpnum_per_tc == 0) {
9482                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9483                 return I40E_ERR_INVALID_QP_ID;
9484         }
9485         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9486                                 I40E_MAX_Q_PER_TC);
9487         bsf = rte_bsf32(qpnum_per_tc);
9488
9489         /**
9490          * Configure TC and queue mapping parameters, for enabled TC,
9491          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9492          * default queue will serve it.
9493          */
9494         qp_idx = 0;
9495         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9496                 if (vsi->enabled_tc & (1 << i)) {
9497                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9498                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9499                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9500                         qp_idx += qpnum_per_tc;
9501                 } else
9502                         info->tc_mapping[i] = 0;
9503         }
9504
9505         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9506         if (vsi->type == I40E_VSI_SRIOV) {
9507                 info->mapping_flags |=
9508                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9509                 for (i = 0; i < vsi->nb_qps; i++)
9510                         info->queue_mapping[i] =
9511                                 rte_cpu_to_le_16(vsi->base_queue + i);
9512         } else {
9513                 info->mapping_flags |=
9514                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9515                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9516         }
9517         info->valid_sections |=
9518                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9519
9520         return I40E_SUCCESS;
9521 }
9522
9523 /*
9524  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9525  * @veb: VEB to be configured
9526  * @tc_map: enabled TC bitmap
9527  *
9528  * Returns 0 on success, negative value on failure
9529  */
9530 static enum i40e_status_code
9531 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9532 {
9533         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9534         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9535         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9536         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9537         enum i40e_status_code ret = I40E_SUCCESS;
9538         int i;
9539         uint32_t bw_max;
9540
9541         /* Check if enabled_tc is same as existing or new TCs */
9542         if (veb->enabled_tc == tc_map)
9543                 return ret;
9544
9545         /* configure tc bandwidth */
9546         memset(&veb_bw, 0, sizeof(veb_bw));
9547         veb_bw.tc_valid_bits = tc_map;
9548         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9549         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9550                 if (tc_map & BIT_ULL(i))
9551                         veb_bw.tc_bw_share_credits[i] = 1;
9552         }
9553         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9554                                                    &veb_bw, NULL);
9555         if (ret) {
9556                 PMD_INIT_LOG(ERR,
9557                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9558                         hw->aq.asq_last_status);
9559                 return ret;
9560         }
9561
9562         memset(&ets_query, 0, sizeof(ets_query));
9563         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9564                                                    &ets_query, NULL);
9565         if (ret != I40E_SUCCESS) {
9566                 PMD_DRV_LOG(ERR,
9567                         "Failed to get switch_comp ETS configuration %u",
9568                         hw->aq.asq_last_status);
9569                 return ret;
9570         }
9571         memset(&bw_query, 0, sizeof(bw_query));
9572         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9573                                                   &bw_query, NULL);
9574         if (ret != I40E_SUCCESS) {
9575                 PMD_DRV_LOG(ERR,
9576                         "Failed to get switch_comp bandwidth configuration %u",
9577                         hw->aq.asq_last_status);
9578                 return ret;
9579         }
9580
9581         /* store and print out BW info */
9582         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9583         veb->bw_info.bw_max = ets_query.tc_bw_max;
9584         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9585         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9586         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9587                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9588                      I40E_16_BIT_WIDTH);
9589         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9590                 veb->bw_info.bw_ets_share_credits[i] =
9591                                 bw_query.tc_bw_share_credits[i];
9592                 veb->bw_info.bw_ets_credits[i] =
9593                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9594                 /* 4 bits per TC, 4th bit is reserved */
9595                 veb->bw_info.bw_ets_max[i] =
9596                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9597                                   RTE_LEN2MASK(3, uint8_t));
9598                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9599                             veb->bw_info.bw_ets_share_credits[i]);
9600                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9601                             veb->bw_info.bw_ets_credits[i]);
9602                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9603                             veb->bw_info.bw_ets_max[i]);
9604         }
9605
9606         veb->enabled_tc = tc_map;
9607
9608         return ret;
9609 }
9610
9611
9612 /*
9613  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9614  * @vsi: VSI to be configured
9615  * @tc_map: enabled TC bitmap
9616  *
9617  * Returns 0 on success, negative value on failure
9618  */
9619 static enum i40e_status_code
9620 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9621 {
9622         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9623         struct i40e_vsi_context ctxt;
9624         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9625         enum i40e_status_code ret = I40E_SUCCESS;
9626         int i;
9627
9628         /* Check if enabled_tc is same as existing or new TCs */
9629         if (vsi->enabled_tc == tc_map)
9630                 return ret;
9631
9632         /* configure tc bandwidth */
9633         memset(&bw_data, 0, sizeof(bw_data));
9634         bw_data.tc_valid_bits = tc_map;
9635         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9636         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9637                 if (tc_map & BIT_ULL(i))
9638                         bw_data.tc_bw_credits[i] = 1;
9639         }
9640         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9641         if (ret) {
9642                 PMD_INIT_LOG(ERR,
9643                         "AQ command Config VSI BW allocation per TC failed = %d",
9644                         hw->aq.asq_last_status);
9645                 goto out;
9646         }
9647         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9648                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9649
9650         /* Update Queue Pairs Mapping for currently enabled UPs */
9651         ctxt.seid = vsi->seid;
9652         ctxt.pf_num = hw->pf_id;
9653         ctxt.vf_num = 0;
9654         ctxt.uplink_seid = vsi->uplink_seid;
9655         ctxt.info = vsi->info;
9656         i40e_get_cap(hw);
9657         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9658         if (ret)
9659                 goto out;
9660
9661         /* Update the VSI after updating the VSI queue-mapping information */
9662         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9663         if (ret) {
9664                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9665                         hw->aq.asq_last_status);
9666                 goto out;
9667         }
9668         /* update the local VSI info with updated queue map */
9669         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9670                                         sizeof(vsi->info.tc_mapping));
9671         (void)rte_memcpy(&vsi->info.queue_mapping,
9672                         &ctxt.info.queue_mapping,
9673                 sizeof(vsi->info.queue_mapping));
9674         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9675         vsi->info.valid_sections = 0;
9676
9677         /* query and update current VSI BW information */
9678         ret = i40e_vsi_get_bw_config(vsi);
9679         if (ret) {
9680                 PMD_INIT_LOG(ERR,
9681                          "Failed updating vsi bw info, err %s aq_err %s",
9682                          i40e_stat_str(hw, ret),
9683                          i40e_aq_str(hw, hw->aq.asq_last_status));
9684                 goto out;
9685         }
9686
9687         vsi->enabled_tc = tc_map;
9688
9689 out:
9690         return ret;
9691 }
9692
9693 /*
9694  * i40e_dcb_hw_configure - program the dcb setting to hw
9695  * @pf: pf the configuration is taken on
9696  * @new_cfg: new configuration
9697  * @tc_map: enabled TC bitmap
9698  *
9699  * Returns 0 on success, negative value on failure
9700  */
9701 static enum i40e_status_code
9702 i40e_dcb_hw_configure(struct i40e_pf *pf,
9703                       struct i40e_dcbx_config *new_cfg,
9704                       uint8_t tc_map)
9705 {
9706         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9707         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9708         struct i40e_vsi *main_vsi = pf->main_vsi;
9709         struct i40e_vsi_list *vsi_list;
9710         enum i40e_status_code ret;
9711         int i;
9712         uint32_t val;
9713
9714         /* Use the FW API if FW > v4.4*/
9715         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9716               (hw->aq.fw_maj_ver >= 5))) {
9717                 PMD_INIT_LOG(ERR,
9718                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9719                 return I40E_ERR_FIRMWARE_API_VERSION;
9720         }
9721
9722         /* Check if need reconfiguration */
9723         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9724                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9725                 return I40E_SUCCESS;
9726         }
9727
9728         /* Copy the new config to the current config */
9729         *old_cfg = *new_cfg;
9730         old_cfg->etsrec = old_cfg->etscfg;
9731         ret = i40e_set_dcb_config(hw);
9732         if (ret) {
9733                 PMD_INIT_LOG(ERR,
9734                          "Set DCB Config failed, err %s aq_err %s\n",
9735                          i40e_stat_str(hw, ret),
9736                          i40e_aq_str(hw, hw->aq.asq_last_status));
9737                 return ret;
9738         }
9739         /* set receive Arbiter to RR mode and ETS scheme by default */
9740         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9741                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9742                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9743                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9744                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9745                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9746                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9747                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9748                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9749                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9750                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9751                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9752                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9753         }
9754         /* get local mib to check whether it is configured correctly */
9755         /* IEEE mode */
9756         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9757         /* Get Local DCB Config */
9758         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9759                                      &hw->local_dcbx_config);
9760
9761         /* if Veb is created, need to update TC of it at first */
9762         if (main_vsi->veb) {
9763                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9764                 if (ret)
9765                         PMD_INIT_LOG(WARNING,
9766                                  "Failed configuring TC for VEB seid=%d\n",
9767                                  main_vsi->veb->seid);
9768         }
9769         /* Update each VSI */
9770         i40e_vsi_config_tc(main_vsi, tc_map);
9771         if (main_vsi->veb) {
9772                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9773                         /* Beside main VSI and VMDQ VSIs, only enable default
9774                          * TC for other VSIs
9775                          */
9776                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9777                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9778                                                          tc_map);
9779                         else
9780                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9781                                                          I40E_DEFAULT_TCMAP);
9782                         if (ret)
9783                                 PMD_INIT_LOG(WARNING,
9784                                         "Failed configuring TC for VSI seid=%d\n",
9785                                         vsi_list->vsi->seid);
9786                         /* continue */
9787                 }
9788         }
9789         return I40E_SUCCESS;
9790 }
9791
9792 /*
9793  * i40e_dcb_init_configure - initial dcb config
9794  * @dev: device being configured
9795  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9796  *
9797  * Returns 0 on success, negative value on failure
9798  */
9799 static int
9800 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9801 {
9802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9804         int ret = 0;
9805
9806         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9807                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9808                 return -ENOTSUP;
9809         }
9810
9811         /* DCB initialization:
9812          * Update DCB configuration from the Firmware and configure
9813          * LLDP MIB change event.
9814          */
9815         if (sw_dcb == TRUE) {
9816                 ret = i40e_init_dcb(hw);
9817                 /* If lldp agent is stopped, the return value from
9818                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9819                  * adminq status. Otherwise, it should return success.
9820                  */
9821                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9822                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9823                         memset(&hw->local_dcbx_config, 0,
9824                                 sizeof(struct i40e_dcbx_config));
9825                         /* set dcb default configuration */
9826                         hw->local_dcbx_config.etscfg.willing = 0;
9827                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9828                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9829                         hw->local_dcbx_config.etscfg.tsatable[0] =
9830                                                 I40E_IEEE_TSA_ETS;
9831                         hw->local_dcbx_config.etsrec =
9832                                 hw->local_dcbx_config.etscfg;
9833                         hw->local_dcbx_config.pfc.willing = 0;
9834                         hw->local_dcbx_config.pfc.pfccap =
9835                                                 I40E_MAX_TRAFFIC_CLASS;
9836                         /* FW needs one App to configure HW */
9837                         hw->local_dcbx_config.numapps = 1;
9838                         hw->local_dcbx_config.app[0].selector =
9839                                                 I40E_APP_SEL_ETHTYPE;
9840                         hw->local_dcbx_config.app[0].priority = 3;
9841                         hw->local_dcbx_config.app[0].protocolid =
9842                                                 I40E_APP_PROTOID_FCOE;
9843                         ret = i40e_set_dcb_config(hw);
9844                         if (ret) {
9845                                 PMD_INIT_LOG(ERR,
9846                                         "default dcb config fails. err = %d, aq_err = %d.",
9847                                         ret, hw->aq.asq_last_status);
9848                                 return -ENOSYS;
9849                         }
9850                 } else {
9851                         PMD_INIT_LOG(ERR,
9852                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9853                                 ret, hw->aq.asq_last_status);
9854                         return -ENOTSUP;
9855                 }
9856         } else {
9857                 ret = i40e_aq_start_lldp(hw, NULL);
9858                 if (ret != I40E_SUCCESS)
9859                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9860
9861                 ret = i40e_init_dcb(hw);
9862                 if (!ret) {
9863                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9864                                 PMD_INIT_LOG(ERR,
9865                                         "HW doesn't support DCBX offload.");
9866                                 return -ENOTSUP;
9867                         }
9868                 } else {
9869                         PMD_INIT_LOG(ERR,
9870                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9871                                 ret, hw->aq.asq_last_status);
9872                         return -ENOTSUP;
9873                 }
9874         }
9875         return 0;
9876 }
9877
9878 /*
9879  * i40e_dcb_setup - setup dcb related config
9880  * @dev: device being configured
9881  *
9882  * Returns 0 on success, negative value on failure
9883  */
9884 static int
9885 i40e_dcb_setup(struct rte_eth_dev *dev)
9886 {
9887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9888         struct i40e_dcbx_config dcb_cfg;
9889         uint8_t tc_map = 0;
9890         int ret = 0;
9891
9892         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9893                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9894                 return -ENOTSUP;
9895         }
9896
9897         if (pf->vf_num != 0)
9898                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9899
9900         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9901         if (ret) {
9902                 PMD_INIT_LOG(ERR, "invalid dcb config");
9903                 return -EINVAL;
9904         }
9905         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9906         if (ret) {
9907                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9908                 return -ENOSYS;
9909         }
9910
9911         return 0;
9912 }
9913
9914 static int
9915 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9916                       struct rte_eth_dcb_info *dcb_info)
9917 {
9918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9920         struct i40e_vsi *vsi = pf->main_vsi;
9921         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9922         uint16_t bsf, tc_mapping;
9923         int i, j = 0;
9924
9925         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9926                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9927         else
9928                 dcb_info->nb_tcs = 1;
9929         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9930                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9931         for (i = 0; i < dcb_info->nb_tcs; i++)
9932                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9933
9934         /* get queue mapping if vmdq is disabled */
9935         if (!pf->nb_cfg_vmdq_vsi) {
9936                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9937                         if (!(vsi->enabled_tc & (1 << i)))
9938                                 continue;
9939                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9940                         dcb_info->tc_queue.tc_rxq[j][i].base =
9941                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9942                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9943                         dcb_info->tc_queue.tc_txq[j][i].base =
9944                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9945                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9946                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9947                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9948                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9949                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9950                 }
9951                 return 0;
9952         }
9953
9954         /* get queue mapping if vmdq is enabled */
9955         do {
9956                 vsi = pf->vmdq[j].vsi;
9957                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9958                         if (!(vsi->enabled_tc & (1 << i)))
9959                                 continue;
9960                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9961                         dcb_info->tc_queue.tc_rxq[j][i].base =
9962                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9963                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9964                         dcb_info->tc_queue.tc_txq[j][i].base =
9965                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9966                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9967                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9968                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9969                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9970                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9971                 }
9972                 j++;
9973         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9974         return 0;
9975 }
9976
9977 static int
9978 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9979 {
9980         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9981         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9983         uint16_t interval =
9984                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9985         uint16_t msix_intr;
9986
9987         msix_intr = intr_handle->intr_vec[queue_id];
9988         if (msix_intr == I40E_MISC_VEC_ID)
9989                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9990                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9991                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9992                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9993                                (interval <<
9994                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9995         else
9996                 I40E_WRITE_REG(hw,
9997                                I40E_PFINT_DYN_CTLN(msix_intr -
9998                                                    I40E_RX_VEC_START),
9999                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10000                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10001                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10002                                (interval <<
10003                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10004
10005         I40E_WRITE_FLUSH(hw);
10006         rte_intr_enable(&pci_dev->intr_handle);
10007
10008         return 0;
10009 }
10010
10011 static int
10012 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10013 {
10014         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10015         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10017         uint16_t msix_intr;
10018
10019         msix_intr = intr_handle->intr_vec[queue_id];
10020         if (msix_intr == I40E_MISC_VEC_ID)
10021                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10022         else
10023                 I40E_WRITE_REG(hw,
10024                                I40E_PFINT_DYN_CTLN(msix_intr -
10025                                                    I40E_RX_VEC_START),
10026                                0);
10027         I40E_WRITE_FLUSH(hw);
10028
10029         return 0;
10030 }
10031
10032 static int i40e_get_regs(struct rte_eth_dev *dev,
10033                          struct rte_dev_reg_info *regs)
10034 {
10035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10036         uint32_t *ptr_data = regs->data;
10037         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10038         const struct i40e_reg_info *reg_info;
10039
10040         if (ptr_data == NULL) {
10041                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10042                 regs->width = sizeof(uint32_t);
10043                 return 0;
10044         }
10045
10046         /* The first few registers have to be read using AQ operations */
10047         reg_idx = 0;
10048         while (i40e_regs_adminq[reg_idx].name) {
10049                 reg_info = &i40e_regs_adminq[reg_idx++];
10050                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10051                         for (arr_idx2 = 0;
10052                                         arr_idx2 <= reg_info->count2;
10053                                         arr_idx2++) {
10054                                 reg_offset = arr_idx * reg_info->stride1 +
10055                                         arr_idx2 * reg_info->stride2;
10056                                 reg_offset += reg_info->base_addr;
10057                                 ptr_data[reg_offset >> 2] =
10058                                         i40e_read_rx_ctl(hw, reg_offset);
10059                         }
10060         }
10061
10062         /* The remaining registers can be read using primitives */
10063         reg_idx = 0;
10064         while (i40e_regs_others[reg_idx].name) {
10065                 reg_info = &i40e_regs_others[reg_idx++];
10066                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10067                         for (arr_idx2 = 0;
10068                                         arr_idx2 <= reg_info->count2;
10069                                         arr_idx2++) {
10070                                 reg_offset = arr_idx * reg_info->stride1 +
10071                                         arr_idx2 * reg_info->stride2;
10072                                 reg_offset += reg_info->base_addr;
10073                                 ptr_data[reg_offset >> 2] =
10074                                         I40E_READ_REG(hw, reg_offset);
10075                         }
10076         }
10077
10078         return 0;
10079 }
10080
10081 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10082 {
10083         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10084
10085         /* Convert word count to byte count */
10086         return hw->nvm.sr_size << 1;
10087 }
10088
10089 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10090                            struct rte_dev_eeprom_info *eeprom)
10091 {
10092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10093         uint16_t *data = eeprom->data;
10094         uint16_t offset, length, cnt_words;
10095         int ret_code;
10096
10097         offset = eeprom->offset >> 1;
10098         length = eeprom->length >> 1;
10099         cnt_words = length;
10100
10101         if (offset > hw->nvm.sr_size ||
10102                 offset + length > hw->nvm.sr_size) {
10103                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10104                 return -EINVAL;
10105         }
10106
10107         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10108
10109         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10110         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10111                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10112                 return -EIO;
10113         }
10114
10115         return 0;
10116 }
10117
10118 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10119                                       struct ether_addr *mac_addr)
10120 {
10121         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10122
10123         if (!is_valid_assigned_ether_addr(mac_addr)) {
10124                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10125                 return;
10126         }
10127
10128         /* Flags: 0x3 updates port address */
10129         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10130 }
10131
10132 static int
10133 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10134 {
10135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10136         struct rte_eth_dev_data *dev_data = pf->dev_data;
10137         uint32_t frame_size = mtu + ETHER_HDR_LEN
10138                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10139         int ret = 0;
10140
10141         /* check if mtu is within the allowed range */
10142         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10143                 return -EINVAL;
10144
10145         /* mtu setting is forbidden if port is start */
10146         if (dev_data->dev_started) {
10147                 PMD_DRV_LOG(ERR,
10148                             "port %d must be stopped before configuration\n",
10149                             dev_data->port_id);
10150                 return -EBUSY;
10151         }
10152
10153         if (frame_size > ETHER_MAX_LEN)
10154                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10155         else
10156                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10157
10158         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10159
10160         return ret;
10161 }
10162
10163 /* Restore ethertype filter */
10164 static void
10165 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10166 {
10167         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10168         struct i40e_ethertype_filter_list
10169                 *ethertype_list = &pf->ethertype.ethertype_list;
10170         struct i40e_ethertype_filter *f;
10171         struct i40e_control_filter_stats stats;
10172         uint16_t flags;
10173
10174         TAILQ_FOREACH(f, ethertype_list, rules) {
10175                 flags = 0;
10176                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10177                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10178                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10179                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10180                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10181
10182                 memset(&stats, 0, sizeof(stats));
10183                 i40e_aq_add_rem_control_packet_filter(hw,
10184                                             f->input.mac_addr.addr_bytes,
10185                                             f->input.ether_type,
10186                                             flags, pf->main_vsi->seid,
10187                                             f->queue, 1, &stats, NULL);
10188         }
10189         PMD_DRV_LOG(INFO, "Ethertype filter:"
10190                     " mac_etype_used = %u, etype_used = %u,"
10191                     " mac_etype_free = %u, etype_free = %u\n",
10192                     stats.mac_etype_used, stats.etype_used,
10193                     stats.mac_etype_free, stats.etype_free);
10194 }
10195
10196 /* Restore tunnel filter */
10197 static void
10198 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10199 {
10200         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10201         struct i40e_vsi *vsi = pf->main_vsi;
10202         struct i40e_tunnel_filter_list
10203                 *tunnel_list = &pf->tunnel.tunnel_list;
10204         struct i40e_tunnel_filter *f;
10205         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10206
10207         TAILQ_FOREACH(f, tunnel_list, rules) {
10208                 memset(&cld_filter, 0, sizeof(cld_filter));
10209                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10210                 cld_filter.queue_number = f->queue;
10211                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10212         }
10213 }
10214
10215 static void
10216 i40e_filter_restore(struct i40e_pf *pf)
10217 {
10218         i40e_ethertype_filter_restore(pf);
10219         i40e_tunnel_filter_restore(pf);
10220         i40e_fdir_filter_restore(pf);
10221 }