1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 /* Check if need to support multi-driver */
1328 i40e_support_multi_driver(dev);
1329 /* Check if users want the latest supported vec path */
1330 i40e_use_latest_vec(dev);
1332 /* Make sure all is clean before doing PF reset */
1335 /* Reset here to make sure all is clean for each PF */
1336 ret = i40e_pf_reset(hw);
1338 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1342 /* Initialize the shared code (base driver) */
1343 ret = i40e_init_shared_code(hw);
1345 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1349 /* Initialize the parameters for adminq */
1350 i40e_init_adminq_parameter(hw);
1351 ret = i40e_init_adminq(hw);
1352 if (ret != I40E_SUCCESS) {
1353 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1356 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1357 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1358 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1359 ((hw->nvm.version >> 12) & 0xf),
1360 ((hw->nvm.version >> 4) & 0xff),
1361 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1363 /* Initialize the hardware */
1366 i40e_config_automask(pf);
1368 i40e_set_default_pctype_table(dev);
1371 * To work around the NVM issue, initialize registers
1372 * for packet type of QinQ by software.
1373 * It should be removed once issues are fixed in NVM.
1375 if (!pf->support_multi_driver)
1376 i40e_GLQF_reg_init(hw);
1378 /* Initialize the input set for filters (hash and fd) to default value */
1379 i40e_filter_input_set_init(pf);
1381 /* initialise the L3_MAP register */
1382 if (!pf->support_multi_driver) {
1383 ret = i40e_aq_debug_write_global_register(hw,
1384 I40E_GLQF_L3_MAP(40),
1387 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1390 "Global register 0x%08x is changed with 0x28",
1391 I40E_GLQF_L3_MAP(40));
1394 /* Need the special FW version to support floating VEB */
1395 config_floating_veb(dev);
1396 /* Clear PXE mode */
1397 i40e_clear_pxe_mode(hw);
1398 i40e_dev_sync_phy_type(hw);
1401 * On X710, performance number is far from the expectation on recent
1402 * firmware versions. The fix for this issue may not be integrated in
1403 * the following firmware version. So the workaround in software driver
1404 * is needed. It needs to modify the initial values of 3 internal only
1405 * registers. Note that the workaround can be removed when it is fixed
1406 * in firmware in the future.
1408 i40e_configure_registers(hw);
1410 /* Get hw capabilities */
1411 ret = i40e_get_cap(hw);
1412 if (ret != I40E_SUCCESS) {
1413 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1414 goto err_get_capabilities;
1417 /* Initialize parameters for PF */
1418 ret = i40e_pf_parameter_init(dev);
1420 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1421 goto err_parameter_init;
1424 /* Initialize the queue management */
1425 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1427 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1428 goto err_qp_pool_init;
1430 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1431 hw->func_caps.num_msix_vectors - 1);
1433 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1434 goto err_msix_pool_init;
1437 /* Initialize lan hmc */
1438 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1439 hw->func_caps.num_rx_qp, 0, 0);
1440 if (ret != I40E_SUCCESS) {
1441 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1442 goto err_init_lan_hmc;
1445 /* Configure lan hmc */
1446 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1447 if (ret != I40E_SUCCESS) {
1448 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1449 goto err_configure_lan_hmc;
1452 /* Get and check the mac address */
1453 i40e_get_mac_addr(hw, hw->mac.addr);
1454 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1455 PMD_INIT_LOG(ERR, "mac address is not valid");
1457 goto err_get_mac_addr;
1459 /* Copy the permanent MAC address */
1460 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1461 (struct ether_addr *) hw->mac.perm_addr);
1463 /* Disable flow control */
1464 hw->fc.requested_mode = I40E_FC_NONE;
1465 i40e_set_fc(hw, &aq_fail, TRUE);
1467 /* Set the global registers with default ether type value */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1471 if (ret != I40E_SUCCESS) {
1473 "Failed to set the default outer "
1475 goto err_setup_pf_switch;
1479 /* PF setup, which includes VSI setup */
1480 ret = i40e_pf_setup(pf);
1482 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1483 goto err_setup_pf_switch;
1486 /* reset all stats of the device, including pf and main vsi */
1487 i40e_dev_stats_reset(dev);
1491 /* Disable double vlan by default */
1492 i40e_vsi_config_double_vlan(vsi, FALSE);
1494 /* Disable S-TAG identification when floating_veb is disabled */
1495 if (!pf->floating_veb) {
1496 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1497 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1498 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1499 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1503 if (!vsi->max_macaddrs)
1504 len = ETHER_ADDR_LEN;
1506 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1508 /* Should be after VSI initialized */
1509 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1510 if (!dev->data->mac_addrs) {
1512 "Failed to allocated memory for storing mac address");
1515 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1516 &dev->data->mac_addrs[0]);
1518 /* Init dcb to sw mode by default */
1519 ret = i40e_dcb_init_configure(dev, TRUE);
1520 if (ret != I40E_SUCCESS) {
1521 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1522 pf->flags &= ~I40E_FLAG_DCB;
1524 /* Update HW struct after DCB configuration */
1527 /* initialize pf host driver to setup SRIOV resource if applicable */
1528 i40e_pf_host_init(dev);
1530 /* register callback func to eal lib */
1531 rte_intr_callback_register(intr_handle,
1532 i40e_dev_interrupt_handler, dev);
1534 /* configure and enable device interrupt */
1535 i40e_pf_config_irq0(hw, TRUE);
1536 i40e_pf_enable_irq0(hw);
1538 /* enable uio intr after callback register */
1539 rte_intr_enable(intr_handle);
1541 /* By default disable flexible payload in global configuration */
1542 if (!pf->support_multi_driver)
1543 i40e_flex_payload_reg_set_default(hw);
1546 * Add an ethertype filter to drop all flow control frames transmitted
1547 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1550 i40e_add_tx_flow_control_drop_filter(pf);
1552 /* Set the max frame size to 0x2600 by default,
1553 * in case other drivers changed the default value.
1555 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1557 /* initialize mirror rule list */
1558 TAILQ_INIT(&pf->mirror_list);
1560 /* initialize Traffic Manager configuration */
1561 i40e_tm_conf_init(dev);
1563 /* Initialize customized information */
1564 i40e_init_customized_info(pf);
1566 ret = i40e_init_ethtype_filter_list(dev);
1568 goto err_init_ethtype_filter_list;
1569 ret = i40e_init_tunnel_filter_list(dev);
1571 goto err_init_tunnel_filter_list;
1572 ret = i40e_init_fdir_filter_list(dev);
1574 goto err_init_fdir_filter_list;
1576 /* initialize queue region configuration */
1577 i40e_init_queue_region_conf(dev);
1579 /* initialize rss configuration from rte_flow */
1580 memset(&pf->rss_info, 0,
1581 sizeof(struct i40e_rte_flow_rss_conf));
1585 err_init_fdir_filter_list:
1586 rte_free(pf->tunnel.hash_table);
1587 rte_free(pf->tunnel.hash_map);
1588 err_init_tunnel_filter_list:
1589 rte_free(pf->ethertype.hash_table);
1590 rte_free(pf->ethertype.hash_map);
1591 err_init_ethtype_filter_list:
1592 rte_free(dev->data->mac_addrs);
1594 i40e_vsi_release(pf->main_vsi);
1595 err_setup_pf_switch:
1597 err_configure_lan_hmc:
1598 (void)i40e_shutdown_lan_hmc(hw);
1600 i40e_res_pool_destroy(&pf->msix_pool);
1602 i40e_res_pool_destroy(&pf->qp_pool);
1605 err_get_capabilities:
1606 (void)i40e_shutdown_adminq(hw);
1612 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1614 struct i40e_ethertype_filter *p_ethertype;
1615 struct i40e_ethertype_rule *ethertype_rule;
1617 ethertype_rule = &pf->ethertype;
1618 /* Remove all ethertype filter rules and hash */
1619 if (ethertype_rule->hash_map)
1620 rte_free(ethertype_rule->hash_map);
1621 if (ethertype_rule->hash_table)
1622 rte_hash_free(ethertype_rule->hash_table);
1624 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1625 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1626 p_ethertype, rules);
1627 rte_free(p_ethertype);
1632 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1634 struct i40e_tunnel_filter *p_tunnel;
1635 struct i40e_tunnel_rule *tunnel_rule;
1637 tunnel_rule = &pf->tunnel;
1638 /* Remove all tunnel director rules and hash */
1639 if (tunnel_rule->hash_map)
1640 rte_free(tunnel_rule->hash_map);
1641 if (tunnel_rule->hash_table)
1642 rte_hash_free(tunnel_rule->hash_table);
1644 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1645 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1651 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1653 struct i40e_fdir_filter *p_fdir;
1654 struct i40e_fdir_info *fdir_info;
1656 fdir_info = &pf->fdir;
1657 /* Remove all flow director rules and hash */
1658 if (fdir_info->hash_map)
1659 rte_free(fdir_info->hash_map);
1660 if (fdir_info->hash_table)
1661 rte_hash_free(fdir_info->hash_table);
1663 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1664 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1669 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1672 * Disable by default flexible payload
1673 * for corresponding L2/L3/L4 layers.
1675 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1676 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1677 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1681 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1684 struct rte_pci_device *pci_dev;
1685 struct rte_intr_handle *intr_handle;
1687 struct i40e_filter_control_settings settings;
1688 struct rte_flow *p_flow;
1690 uint8_t aq_fail = 0;
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1701 intr_handle = &pci_dev->intr_handle;
1703 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1705 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1707 if (hw->adapter_stopped == 0)
1708 i40e_dev_close(dev);
1710 dev->dev_ops = NULL;
1711 dev->rx_pkt_burst = NULL;
1712 dev->tx_pkt_burst = NULL;
1714 /* Clear PXE mode */
1715 i40e_clear_pxe_mode(hw);
1717 /* Unconfigure filter control */
1718 memset(&settings, 0, sizeof(settings));
1719 ret = i40e_set_filter_control(hw, &settings);
1721 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1724 /* Disable flow control */
1725 hw->fc.requested_mode = I40E_FC_NONE;
1726 i40e_set_fc(hw, &aq_fail, TRUE);
1728 /* uninitialize pf host driver */
1729 i40e_pf_host_uninit(dev);
1731 rte_free(dev->data->mac_addrs);
1732 dev->data->mac_addrs = NULL;
1734 /* disable uio intr before callback unregister */
1735 rte_intr_disable(intr_handle);
1737 /* unregister callback func to eal lib */
1739 ret = rte_intr_callback_unregister(intr_handle,
1740 i40e_dev_interrupt_handler, dev);
1743 } else if (ret != -EAGAIN) {
1745 "intr callback unregister failed: %d",
1749 i40e_msec_delay(500);
1750 } while (retries++ < 5);
1752 i40e_rm_ethtype_filter_list(pf);
1753 i40e_rm_tunnel_filter_list(pf);
1754 i40e_rm_fdir_filter_list(pf);
1756 /* Remove all flows */
1757 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1758 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1762 /* Remove all Traffic Manager configuration */
1763 i40e_tm_conf_uninit(dev);
1769 i40e_dev_configure(struct rte_eth_dev *dev)
1771 struct i40e_adapter *ad =
1772 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1773 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1778 ret = i40e_dev_sync_phy_type(hw);
1782 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1783 * bulk allocation or vector Rx preconditions we will reset it.
1785 ad->rx_bulk_alloc_allowed = true;
1786 ad->rx_vec_allowed = true;
1787 ad->tx_simple_allowed = true;
1788 ad->tx_vec_allowed = true;
1790 /* Only legacy filter API needs the following fdir config. So when the
1791 * legacy filter API is deprecated, the following codes should also be
1794 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1795 ret = i40e_fdir_setup(pf);
1796 if (ret != I40E_SUCCESS) {
1797 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1800 ret = i40e_fdir_configure(dev);
1802 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1806 i40e_fdir_teardown(pf);
1808 ret = i40e_dev_init_vlan(dev);
1813 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1814 * RSS setting have different requirements.
1815 * General PMD driver call sequence are NIC init, configure,
1816 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1817 * will try to lookup the VSI that specific queue belongs to if VMDQ
1818 * applicable. So, VMDQ setting has to be done before
1819 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1820 * For RSS setting, it will try to calculate actual configured RX queue
1821 * number, which will be available after rx_queue_setup(). dev_start()
1822 * function is good to place RSS setup.
1824 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1825 ret = i40e_vmdq_setup(dev);
1830 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1831 ret = i40e_dcb_setup(dev);
1833 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1838 TAILQ_INIT(&pf->flow_list);
1843 /* need to release vmdq resource if exists */
1844 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1845 i40e_vsi_release(pf->vmdq[i].vsi);
1846 pf->vmdq[i].vsi = NULL;
1851 /* Need to release fdir resource if exists.
1852 * Only legacy filter API needs the following fdir config. So when the
1853 * legacy filter API is deprecated, the following code should also be
1856 i40e_fdir_teardown(pf);
1861 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1863 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1864 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1866 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1867 uint16_t msix_vect = vsi->msix_intr;
1870 for (i = 0; i < vsi->nb_qps; i++) {
1871 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1872 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1876 if (vsi->type != I40E_VSI_SRIOV) {
1877 if (!rte_intr_allow_others(intr_handle)) {
1878 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1879 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1881 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1885 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1892 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1893 vsi->user_param + (msix_vect - 1);
1895 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1896 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1898 I40E_WRITE_FLUSH(hw);
1902 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1903 int base_queue, int nb_queue,
1908 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1909 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1911 /* Bind all RX queues to allocated MSIX interrupt */
1912 for (i = 0; i < nb_queue; i++) {
1913 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1914 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1915 ((base_queue + i + 1) <<
1916 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1917 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1918 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1920 if (i == nb_queue - 1)
1921 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1922 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1925 /* Write first RX queue to Link list register as the head element */
1926 if (vsi->type != I40E_VSI_SRIOV) {
1928 i40e_calc_itr_interval(1, pf->support_multi_driver);
1930 if (msix_vect == I40E_MISC_VEC_ID) {
1931 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1933 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1935 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1937 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1940 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1942 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1944 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1946 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1953 if (msix_vect == I40E_MISC_VEC_ID) {
1955 I40E_VPINT_LNKLST0(vsi->user_param),
1957 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1959 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1961 /* num_msix_vectors_vf needs to minus irq0 */
1962 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1963 vsi->user_param + (msix_vect - 1);
1965 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1967 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1969 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1973 I40E_WRITE_FLUSH(hw);
1977 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1979 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1980 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1981 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1982 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1983 uint16_t msix_vect = vsi->msix_intr;
1984 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1985 uint16_t queue_idx = 0;
1989 for (i = 0; i < vsi->nb_qps; i++) {
1990 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1991 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1994 /* VF bind interrupt */
1995 if (vsi->type == I40E_VSI_SRIOV) {
1996 __vsi_queues_bind_intr(vsi, msix_vect,
1997 vsi->base_queue, vsi->nb_qps,
2002 /* PF & VMDq bind interrupt */
2003 if (rte_intr_dp_is_en(intr_handle)) {
2004 if (vsi->type == I40E_VSI_MAIN) {
2007 } else if (vsi->type == I40E_VSI_VMDQ2) {
2008 struct i40e_vsi *main_vsi =
2009 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2010 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2015 for (i = 0; i < vsi->nb_used_qps; i++) {
2017 if (!rte_intr_allow_others(intr_handle))
2018 /* allow to share MISC_VEC_ID */
2019 msix_vect = I40E_MISC_VEC_ID;
2021 /* no enough msix_vect, map all to one */
2022 __vsi_queues_bind_intr(vsi, msix_vect,
2023 vsi->base_queue + i,
2024 vsi->nb_used_qps - i,
2026 for (; !!record && i < vsi->nb_used_qps; i++)
2027 intr_handle->intr_vec[queue_idx + i] =
2031 /* 1:1 queue/msix_vect mapping */
2032 __vsi_queues_bind_intr(vsi, msix_vect,
2033 vsi->base_queue + i, 1,
2036 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2046 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2047 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2048 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2049 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2050 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2051 uint16_t msix_intr, i;
2053 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2054 for (i = 0; i < vsi->nb_msix; i++) {
2055 msix_intr = vsi->msix_intr + i;
2056 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2057 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2058 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2059 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2063 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2064 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2067 I40E_WRITE_FLUSH(hw);
2071 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2073 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2075 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2077 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2078 uint16_t msix_intr, i;
2080 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2081 for (i = 0; i < vsi->nb_msix; i++) {
2082 msix_intr = vsi->msix_intr + i;
2083 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2084 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2087 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2088 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2090 I40E_WRITE_FLUSH(hw);
2093 static inline uint8_t
2094 i40e_parse_link_speeds(uint16_t link_speeds)
2096 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2098 if (link_speeds & ETH_LINK_SPEED_40G)
2099 link_speed |= I40E_LINK_SPEED_40GB;
2100 if (link_speeds & ETH_LINK_SPEED_25G)
2101 link_speed |= I40E_LINK_SPEED_25GB;
2102 if (link_speeds & ETH_LINK_SPEED_20G)
2103 link_speed |= I40E_LINK_SPEED_20GB;
2104 if (link_speeds & ETH_LINK_SPEED_10G)
2105 link_speed |= I40E_LINK_SPEED_10GB;
2106 if (link_speeds & ETH_LINK_SPEED_1G)
2107 link_speed |= I40E_LINK_SPEED_1GB;
2108 if (link_speeds & ETH_LINK_SPEED_100M)
2109 link_speed |= I40E_LINK_SPEED_100MB;
2115 i40e_phy_conf_link(struct i40e_hw *hw,
2117 uint8_t force_speed,
2120 enum i40e_status_code status;
2121 struct i40e_aq_get_phy_abilities_resp phy_ab;
2122 struct i40e_aq_set_phy_config phy_conf;
2123 enum i40e_aq_phy_type cnt;
2124 uint8_t avail_speed;
2125 uint32_t phy_type_mask = 0;
2127 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2128 I40E_AQ_PHY_FLAG_PAUSE_RX |
2129 I40E_AQ_PHY_FLAG_PAUSE_RX |
2130 I40E_AQ_PHY_FLAG_LOW_POWER;
2133 /* To get phy capabilities of available speeds. */
2134 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2137 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2141 avail_speed = phy_ab.link_speed;
2143 /* To get the current phy config. */
2144 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2147 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2152 /* If link needs to go up and it is in autoneg mode the speed is OK,
2153 * no need to set up again.
2155 if (is_up && phy_ab.phy_type != 0 &&
2156 abilities & I40E_AQ_PHY_AN_ENABLED &&
2157 phy_ab.link_speed != 0)
2158 return I40E_SUCCESS;
2160 memset(&phy_conf, 0, sizeof(phy_conf));
2162 /* bits 0-2 use the values from get_phy_abilities_resp */
2164 abilities |= phy_ab.abilities & mask;
2166 phy_conf.abilities = abilities;
2168 /* If link needs to go up, but the force speed is not supported,
2169 * Warn users and config the default available speeds.
2171 if (is_up && !(force_speed & avail_speed)) {
2172 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2173 phy_conf.link_speed = avail_speed;
2175 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2178 /* PHY type mask needs to include each type except PHY type extension */
2179 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2180 phy_type_mask |= 1 << cnt;
2182 /* use get_phy_abilities_resp value for the rest */
2183 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2184 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2185 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2186 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2187 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2188 phy_conf.eee_capability = phy_ab.eee_capability;
2189 phy_conf.eeer = phy_ab.eeer_val;
2190 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2192 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2193 phy_ab.abilities, phy_ab.link_speed);
2194 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2195 phy_conf.abilities, phy_conf.link_speed);
2197 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2201 return I40E_SUCCESS;
2205 i40e_apply_link_speed(struct rte_eth_dev *dev)
2208 uint8_t abilities = 0;
2209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210 struct rte_eth_conf *conf = &dev->data->dev_conf;
2212 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2213 conf->link_speeds = ETH_LINK_SPEED_40G |
2214 ETH_LINK_SPEED_25G |
2215 ETH_LINK_SPEED_20G |
2216 ETH_LINK_SPEED_10G |
2218 ETH_LINK_SPEED_100M;
2220 speed = i40e_parse_link_speeds(conf->link_speeds);
2221 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2222 I40E_AQ_PHY_AN_ENABLED |
2223 I40E_AQ_PHY_LINK_ENABLED;
2225 return i40e_phy_conf_link(hw, abilities, speed, true);
2229 i40e_dev_start(struct rte_eth_dev *dev)
2231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233 struct i40e_vsi *main_vsi = pf->main_vsi;
2235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2237 uint32_t intr_vector = 0;
2238 struct i40e_vsi *vsi;
2240 hw->adapter_stopped = 0;
2242 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2244 "Invalid link_speeds for port %u, autonegotiation disabled",
2245 dev->data->port_id);
2249 rte_intr_disable(intr_handle);
2251 if ((rte_intr_cap_multiple(intr_handle) ||
2252 !RTE_ETH_DEV_SRIOV(dev).active) &&
2253 dev->data->dev_conf.intr_conf.rxq != 0) {
2254 intr_vector = dev->data->nb_rx_queues;
2255 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2260 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2261 intr_handle->intr_vec =
2262 rte_zmalloc("intr_vec",
2263 dev->data->nb_rx_queues * sizeof(int),
2265 if (!intr_handle->intr_vec) {
2267 "Failed to allocate %d rx_queues intr_vec",
2268 dev->data->nb_rx_queues);
2273 /* Initialize VSI */
2274 ret = i40e_dev_rxtx_init(pf);
2275 if (ret != I40E_SUCCESS) {
2276 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2280 /* Map queues with MSIX interrupt */
2281 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2282 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2283 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2284 i40e_vsi_enable_queues_intr(main_vsi);
2286 /* Map VMDQ VSI queues with MSIX interrupt */
2287 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2288 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2290 I40E_ITR_INDEX_DEFAULT);
2291 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2294 /* enable FDIR MSIX interrupt */
2295 if (pf->fdir.fdir_vsi) {
2296 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2297 I40E_ITR_INDEX_NONE);
2298 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2301 /* Enable all queues which have been configured */
2302 ret = i40e_dev_switch_queues(pf, TRUE);
2303 if (ret != I40E_SUCCESS) {
2304 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2308 /* Enable receiving broadcast packets */
2309 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2310 if (ret != I40E_SUCCESS)
2311 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2313 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2314 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2320 /* Enable the VLAN promiscuous mode. */
2322 for (i = 0; i < pf->vf_num; i++) {
2323 vsi = pf->vfs[i].vsi;
2324 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2329 /* Enable mac loopback mode */
2330 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2331 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2332 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2333 if (ret != I40E_SUCCESS) {
2334 PMD_DRV_LOG(ERR, "fail to set loopback link");
2339 /* Apply link configure */
2340 ret = i40e_apply_link_speed(dev);
2341 if (I40E_SUCCESS != ret) {
2342 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2346 if (!rte_intr_allow_others(intr_handle)) {
2347 rte_intr_callback_unregister(intr_handle,
2348 i40e_dev_interrupt_handler,
2350 /* configure and enable device interrupt */
2351 i40e_pf_config_irq0(hw, FALSE);
2352 i40e_pf_enable_irq0(hw);
2354 if (dev->data->dev_conf.intr_conf.lsc != 0)
2356 "lsc won't enable because of no intr multiplex");
2358 ret = i40e_aq_set_phy_int_mask(hw,
2359 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2360 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2361 I40E_AQ_EVENT_MEDIA_NA), NULL);
2362 if (ret != I40E_SUCCESS)
2363 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2365 /* Call get_link_info aq commond to enable/disable LSE */
2366 i40e_dev_link_update(dev, 0);
2369 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2370 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2371 i40e_dev_alarm_handler, dev);
2373 /* enable uio intr after callback register */
2374 rte_intr_enable(intr_handle);
2377 i40e_filter_restore(pf);
2379 if (pf->tm_conf.root && !pf->tm_conf.committed)
2380 PMD_DRV_LOG(WARNING,
2381 "please call hierarchy_commit() "
2382 "before starting the port");
2384 return I40E_SUCCESS;
2387 i40e_dev_switch_queues(pf, FALSE);
2388 i40e_dev_clear_queues(dev);
2394 i40e_dev_stop(struct rte_eth_dev *dev)
2396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 struct i40e_vsi *main_vsi = pf->main_vsi;
2399 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2400 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2403 if (hw->adapter_stopped == 1)
2406 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2407 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2408 rte_intr_enable(intr_handle);
2411 /* Disable all queues */
2412 i40e_dev_switch_queues(pf, FALSE);
2414 /* un-map queues with interrupt registers */
2415 i40e_vsi_disable_queues_intr(main_vsi);
2416 i40e_vsi_queues_unbind_intr(main_vsi);
2418 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2419 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2420 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2423 if (pf->fdir.fdir_vsi) {
2424 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2425 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2427 /* Clear all queues and release memory */
2428 i40e_dev_clear_queues(dev);
2431 i40e_dev_set_link_down(dev);
2433 if (!rte_intr_allow_others(intr_handle))
2434 /* resume to the default handler */
2435 rte_intr_callback_register(intr_handle,
2436 i40e_dev_interrupt_handler,
2439 /* Clean datapath event and queue/vec mapping */
2440 rte_intr_efd_disable(intr_handle);
2441 if (intr_handle->intr_vec) {
2442 rte_free(intr_handle->intr_vec);
2443 intr_handle->intr_vec = NULL;
2446 /* reset hierarchy commit */
2447 pf->tm_conf.committed = false;
2449 hw->adapter_stopped = 1;
2453 i40e_dev_close(struct rte_eth_dev *dev)
2455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2456 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2458 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2459 struct i40e_mirror_rule *p_mirror;
2464 PMD_INIT_FUNC_TRACE();
2468 /* Remove all mirror rules */
2469 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2470 ret = i40e_aq_del_mirror_rule(hw,
2471 pf->main_vsi->veb->seid,
2472 p_mirror->rule_type,
2474 p_mirror->num_entries,
2477 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2478 "status = %d, aq_err = %d.", ret,
2479 hw->aq.asq_last_status);
2481 /* remove mirror software resource anyway */
2482 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2484 pf->nb_mirror_rule--;
2487 i40e_dev_free_queues(dev);
2489 /* Disable interrupt */
2490 i40e_pf_disable_irq0(hw);
2491 rte_intr_disable(intr_handle);
2494 * Only legacy filter API needs the following fdir config. So when the
2495 * legacy filter API is deprecated, the following code should also be
2498 i40e_fdir_teardown(pf);
2500 /* shutdown and destroy the HMC */
2501 i40e_shutdown_lan_hmc(hw);
2503 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2504 i40e_vsi_release(pf->vmdq[i].vsi);
2505 pf->vmdq[i].vsi = NULL;
2510 /* release all the existing VSIs and VEBs */
2511 i40e_vsi_release(pf->main_vsi);
2513 /* shutdown the adminq */
2514 i40e_aq_queue_shutdown(hw, true);
2515 i40e_shutdown_adminq(hw);
2517 i40e_res_pool_destroy(&pf->qp_pool);
2518 i40e_res_pool_destroy(&pf->msix_pool);
2520 /* Disable flexible payload in global configuration */
2521 if (!pf->support_multi_driver)
2522 i40e_flex_payload_reg_set_default(hw);
2524 /* force a PF reset to clean anything leftover */
2525 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2526 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2527 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2528 I40E_WRITE_FLUSH(hw);
2532 * Reset PF device only to re-initialize resources in PMD layer
2535 i40e_dev_reset(struct rte_eth_dev *dev)
2539 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2540 * its VF to make them align with it. The detailed notification
2541 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2542 * To avoid unexpected behavior in VF, currently reset of PF with
2543 * SR-IOV activation is not supported. It might be supported later.
2545 if (dev->data->sriov.active)
2548 ret = eth_i40e_dev_uninit(dev);
2552 ret = eth_i40e_dev_init(dev, NULL);
2558 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2560 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2561 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 struct i40e_vsi *vsi = pf->main_vsi;
2565 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2567 if (status != I40E_SUCCESS)
2568 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2570 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2572 if (status != I40E_SUCCESS)
2573 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2578 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2580 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2581 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582 struct i40e_vsi *vsi = pf->main_vsi;
2585 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2587 if (status != I40E_SUCCESS)
2588 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2590 /* must remain in all_multicast mode */
2591 if (dev->data->all_multicast == 1)
2594 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2596 if (status != I40E_SUCCESS)
2597 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2601 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2603 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605 struct i40e_vsi *vsi = pf->main_vsi;
2608 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2609 if (ret != I40E_SUCCESS)
2610 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2614 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2616 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618 struct i40e_vsi *vsi = pf->main_vsi;
2621 if (dev->data->promiscuous == 1)
2622 return; /* must remain in all_multicast mode */
2624 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2625 vsi->seid, FALSE, NULL);
2626 if (ret != I40E_SUCCESS)
2627 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2631 * Set device link up.
2634 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2636 /* re-apply link speed setting */
2637 return i40e_apply_link_speed(dev);
2641 * Set device link down.
2644 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2646 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2647 uint8_t abilities = 0;
2648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2651 return i40e_phy_conf_link(hw, abilities, speed, false);
2654 static __rte_always_inline void
2655 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2657 /* Link status registers and values*/
2658 #define I40E_PRTMAC_LINKSTA 0x001E2420
2659 #define I40E_REG_LINK_UP 0x40000080
2660 #define I40E_PRTMAC_MACC 0x001E24E0
2661 #define I40E_REG_MACC_25GB 0x00020000
2662 #define I40E_REG_SPEED_MASK 0x38000000
2663 #define I40E_REG_SPEED_100MB 0x00000000
2664 #define I40E_REG_SPEED_1GB 0x08000000
2665 #define I40E_REG_SPEED_10GB 0x10000000
2666 #define I40E_REG_SPEED_20GB 0x20000000
2667 #define I40E_REG_SPEED_25_40GB 0x18000000
2668 uint32_t link_speed;
2671 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2672 link_speed = reg_val & I40E_REG_SPEED_MASK;
2673 reg_val &= I40E_REG_LINK_UP;
2674 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2676 if (unlikely(link->link_status == 0))
2679 /* Parse the link status */
2680 switch (link_speed) {
2681 case I40E_REG_SPEED_100MB:
2682 link->link_speed = ETH_SPEED_NUM_100M;
2684 case I40E_REG_SPEED_1GB:
2685 link->link_speed = ETH_SPEED_NUM_1G;
2687 case I40E_REG_SPEED_10GB:
2688 link->link_speed = ETH_SPEED_NUM_10G;
2690 case I40E_REG_SPEED_20GB:
2691 link->link_speed = ETH_SPEED_NUM_20G;
2693 case I40E_REG_SPEED_25_40GB:
2694 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2696 if (reg_val & I40E_REG_MACC_25GB)
2697 link->link_speed = ETH_SPEED_NUM_25G;
2699 link->link_speed = ETH_SPEED_NUM_40G;
2703 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2708 static __rte_always_inline void
2709 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2710 bool enable_lse, int wait_to_complete)
2712 #define CHECK_INTERVAL 100 /* 100ms */
2713 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2714 uint32_t rep_cnt = MAX_REPEAT_TIME;
2715 struct i40e_link_status link_status;
2718 memset(&link_status, 0, sizeof(link_status));
2721 memset(&link_status, 0, sizeof(link_status));
2723 /* Get link status information from hardware */
2724 status = i40e_aq_get_link_info(hw, enable_lse,
2725 &link_status, NULL);
2726 if (unlikely(status != I40E_SUCCESS)) {
2727 link->link_speed = ETH_SPEED_NUM_100M;
2728 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2729 PMD_DRV_LOG(ERR, "Failed to get link info");
2733 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2734 if (!wait_to_complete || link->link_status)
2737 rte_delay_ms(CHECK_INTERVAL);
2738 } while (--rep_cnt);
2740 /* Parse the link status */
2741 switch (link_status.link_speed) {
2742 case I40E_LINK_SPEED_100MB:
2743 link->link_speed = ETH_SPEED_NUM_100M;
2745 case I40E_LINK_SPEED_1GB:
2746 link->link_speed = ETH_SPEED_NUM_1G;
2748 case I40E_LINK_SPEED_10GB:
2749 link->link_speed = ETH_SPEED_NUM_10G;
2751 case I40E_LINK_SPEED_20GB:
2752 link->link_speed = ETH_SPEED_NUM_20G;
2754 case I40E_LINK_SPEED_25GB:
2755 link->link_speed = ETH_SPEED_NUM_25G;
2757 case I40E_LINK_SPEED_40GB:
2758 link->link_speed = ETH_SPEED_NUM_40G;
2761 link->link_speed = ETH_SPEED_NUM_100M;
2767 i40e_dev_link_update(struct rte_eth_dev *dev,
2768 int wait_to_complete)
2770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771 struct rte_eth_link link;
2772 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2775 memset(&link, 0, sizeof(link));
2777 /* i40e uses full duplex only */
2778 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2779 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2780 ETH_LINK_SPEED_FIXED);
2782 if (!wait_to_complete && !enable_lse)
2783 update_link_reg(hw, &link);
2785 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2787 ret = rte_eth_linkstatus_set(dev, &link);
2788 i40e_notify_all_vfs_link_status(dev);
2793 /* Get all the statistics of a VSI */
2795 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2797 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2798 struct i40e_eth_stats *nes = &vsi->eth_stats;
2799 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2800 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2802 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2803 vsi->offset_loaded, &oes->rx_bytes,
2805 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2806 vsi->offset_loaded, &oes->rx_unicast,
2808 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2809 vsi->offset_loaded, &oes->rx_multicast,
2810 &nes->rx_multicast);
2811 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2812 vsi->offset_loaded, &oes->rx_broadcast,
2813 &nes->rx_broadcast);
2814 /* exclude CRC bytes */
2815 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2816 nes->rx_broadcast) * ETHER_CRC_LEN;
2818 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2819 &oes->rx_discards, &nes->rx_discards);
2820 /* GLV_REPC not supported */
2821 /* GLV_RMPC not supported */
2822 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2823 &oes->rx_unknown_protocol,
2824 &nes->rx_unknown_protocol);
2825 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2826 vsi->offset_loaded, &oes->tx_bytes,
2828 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2829 vsi->offset_loaded, &oes->tx_unicast,
2831 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2832 vsi->offset_loaded, &oes->tx_multicast,
2833 &nes->tx_multicast);
2834 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2835 vsi->offset_loaded, &oes->tx_broadcast,
2836 &nes->tx_broadcast);
2837 /* GLV_TDPC not supported */
2838 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2839 &oes->tx_errors, &nes->tx_errors);
2840 vsi->offset_loaded = true;
2842 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2844 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2845 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2846 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2847 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2848 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2849 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2850 nes->rx_unknown_protocol);
2851 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2852 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2853 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2854 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2855 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2856 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2857 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2862 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2865 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2866 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2868 /* Get rx/tx bytes of internal transfer packets */
2869 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2870 I40E_GLV_GORCL(hw->port),
2872 &pf->internal_stats_offset.rx_bytes,
2873 &pf->internal_stats.rx_bytes);
2875 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2876 I40E_GLV_GOTCL(hw->port),
2878 &pf->internal_stats_offset.tx_bytes,
2879 &pf->internal_stats.tx_bytes);
2880 /* Get total internal rx packet count */
2881 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2882 I40E_GLV_UPRCL(hw->port),
2884 &pf->internal_stats_offset.rx_unicast,
2885 &pf->internal_stats.rx_unicast);
2886 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2887 I40E_GLV_MPRCL(hw->port),
2889 &pf->internal_stats_offset.rx_multicast,
2890 &pf->internal_stats.rx_multicast);
2891 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2892 I40E_GLV_BPRCL(hw->port),
2894 &pf->internal_stats_offset.rx_broadcast,
2895 &pf->internal_stats.rx_broadcast);
2896 /* Get total internal tx packet count */
2897 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2898 I40E_GLV_UPTCL(hw->port),
2900 &pf->internal_stats_offset.tx_unicast,
2901 &pf->internal_stats.tx_unicast);
2902 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2903 I40E_GLV_MPTCL(hw->port),
2905 &pf->internal_stats_offset.tx_multicast,
2906 &pf->internal_stats.tx_multicast);
2907 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2908 I40E_GLV_BPTCL(hw->port),
2910 &pf->internal_stats_offset.tx_broadcast,
2911 &pf->internal_stats.tx_broadcast);
2913 /* exclude CRC size */
2914 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2915 pf->internal_stats.rx_multicast +
2916 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2918 /* Get statistics of struct i40e_eth_stats */
2919 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2920 I40E_GLPRT_GORCL(hw->port),
2921 pf->offset_loaded, &os->eth.rx_bytes,
2923 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2924 I40E_GLPRT_UPRCL(hw->port),
2925 pf->offset_loaded, &os->eth.rx_unicast,
2926 &ns->eth.rx_unicast);
2927 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2928 I40E_GLPRT_MPRCL(hw->port),
2929 pf->offset_loaded, &os->eth.rx_multicast,
2930 &ns->eth.rx_multicast);
2931 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2932 I40E_GLPRT_BPRCL(hw->port),
2933 pf->offset_loaded, &os->eth.rx_broadcast,
2934 &ns->eth.rx_broadcast);
2935 /* Workaround: CRC size should not be included in byte statistics,
2936 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2938 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2939 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2941 /* exclude internal rx bytes
2942 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2943 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2945 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2947 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2948 ns->eth.rx_bytes = 0;
2950 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2952 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2953 ns->eth.rx_unicast = 0;
2955 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2957 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2958 ns->eth.rx_multicast = 0;
2960 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2962 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2963 ns->eth.rx_broadcast = 0;
2965 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2967 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2968 pf->offset_loaded, &os->eth.rx_discards,
2969 &ns->eth.rx_discards);
2970 /* GLPRT_REPC not supported */
2971 /* GLPRT_RMPC not supported */
2972 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2974 &os->eth.rx_unknown_protocol,
2975 &ns->eth.rx_unknown_protocol);
2976 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2977 I40E_GLPRT_GOTCL(hw->port),
2978 pf->offset_loaded, &os->eth.tx_bytes,
2980 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2981 I40E_GLPRT_UPTCL(hw->port),
2982 pf->offset_loaded, &os->eth.tx_unicast,
2983 &ns->eth.tx_unicast);
2984 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2985 I40E_GLPRT_MPTCL(hw->port),
2986 pf->offset_loaded, &os->eth.tx_multicast,
2987 &ns->eth.tx_multicast);
2988 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2989 I40E_GLPRT_BPTCL(hw->port),
2990 pf->offset_loaded, &os->eth.tx_broadcast,
2991 &ns->eth.tx_broadcast);
2992 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2993 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2995 /* exclude internal tx bytes
2996 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2997 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2999 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3001 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3002 ns->eth.tx_bytes = 0;
3004 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3006 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3007 ns->eth.tx_unicast = 0;
3009 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3011 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3012 ns->eth.tx_multicast = 0;
3014 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3016 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3017 ns->eth.tx_broadcast = 0;
3019 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3021 /* GLPRT_TEPC not supported */
3023 /* additional port specific stats */
3024 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3025 pf->offset_loaded, &os->tx_dropped_link_down,
3026 &ns->tx_dropped_link_down);
3027 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3028 pf->offset_loaded, &os->crc_errors,
3030 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3031 pf->offset_loaded, &os->illegal_bytes,
3032 &ns->illegal_bytes);
3033 /* GLPRT_ERRBC not supported */
3034 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3035 pf->offset_loaded, &os->mac_local_faults,
3036 &ns->mac_local_faults);
3037 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3038 pf->offset_loaded, &os->mac_remote_faults,
3039 &ns->mac_remote_faults);
3040 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3041 pf->offset_loaded, &os->rx_length_errors,
3042 &ns->rx_length_errors);
3043 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3044 pf->offset_loaded, &os->link_xon_rx,
3046 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3047 pf->offset_loaded, &os->link_xoff_rx,
3049 for (i = 0; i < 8; i++) {
3050 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3052 &os->priority_xon_rx[i],
3053 &ns->priority_xon_rx[i]);
3054 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3056 &os->priority_xoff_rx[i],
3057 &ns->priority_xoff_rx[i]);
3059 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3060 pf->offset_loaded, &os->link_xon_tx,
3062 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3063 pf->offset_loaded, &os->link_xoff_tx,
3065 for (i = 0; i < 8; i++) {
3066 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3068 &os->priority_xon_tx[i],
3069 &ns->priority_xon_tx[i]);
3070 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3072 &os->priority_xoff_tx[i],
3073 &ns->priority_xoff_tx[i]);
3074 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3076 &os->priority_xon_2_xoff[i],
3077 &ns->priority_xon_2_xoff[i]);
3079 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3080 I40E_GLPRT_PRC64L(hw->port),
3081 pf->offset_loaded, &os->rx_size_64,
3083 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3084 I40E_GLPRT_PRC127L(hw->port),
3085 pf->offset_loaded, &os->rx_size_127,
3087 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3088 I40E_GLPRT_PRC255L(hw->port),
3089 pf->offset_loaded, &os->rx_size_255,
3091 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3092 I40E_GLPRT_PRC511L(hw->port),
3093 pf->offset_loaded, &os->rx_size_511,
3095 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3096 I40E_GLPRT_PRC1023L(hw->port),
3097 pf->offset_loaded, &os->rx_size_1023,
3099 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3100 I40E_GLPRT_PRC1522L(hw->port),
3101 pf->offset_loaded, &os->rx_size_1522,
3103 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3104 I40E_GLPRT_PRC9522L(hw->port),
3105 pf->offset_loaded, &os->rx_size_big,
3107 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3108 pf->offset_loaded, &os->rx_undersize,
3110 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3111 pf->offset_loaded, &os->rx_fragments,
3113 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3114 pf->offset_loaded, &os->rx_oversize,
3116 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3117 pf->offset_loaded, &os->rx_jabber,
3119 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3120 I40E_GLPRT_PTC64L(hw->port),
3121 pf->offset_loaded, &os->tx_size_64,
3123 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3124 I40E_GLPRT_PTC127L(hw->port),
3125 pf->offset_loaded, &os->tx_size_127,
3127 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3128 I40E_GLPRT_PTC255L(hw->port),
3129 pf->offset_loaded, &os->tx_size_255,
3131 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3132 I40E_GLPRT_PTC511L(hw->port),
3133 pf->offset_loaded, &os->tx_size_511,
3135 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3136 I40E_GLPRT_PTC1023L(hw->port),
3137 pf->offset_loaded, &os->tx_size_1023,
3139 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3140 I40E_GLPRT_PTC1522L(hw->port),
3141 pf->offset_loaded, &os->tx_size_1522,
3143 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3144 I40E_GLPRT_PTC9522L(hw->port),
3145 pf->offset_loaded, &os->tx_size_big,
3147 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3149 &os->fd_sb_match, &ns->fd_sb_match);
3150 /* GLPRT_MSPDC not supported */
3151 /* GLPRT_XEC not supported */
3153 pf->offset_loaded = true;
3156 i40e_update_vsi_stats(pf->main_vsi);
3159 /* Get all statistics of a port */
3161 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3164 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3168 /* call read registers - updates values, now write them to struct */
3169 i40e_read_stats_registers(pf, hw);
3171 stats->ipackets = ns->eth.rx_unicast +
3172 ns->eth.rx_multicast +
3173 ns->eth.rx_broadcast -
3174 ns->eth.rx_discards -
3175 pf->main_vsi->eth_stats.rx_discards;
3176 stats->opackets = ns->eth.tx_unicast +
3177 ns->eth.tx_multicast +
3178 ns->eth.tx_broadcast;
3179 stats->ibytes = ns->eth.rx_bytes;
3180 stats->obytes = ns->eth.tx_bytes;
3181 stats->oerrors = ns->eth.tx_errors +
3182 pf->main_vsi->eth_stats.tx_errors;
3185 stats->imissed = ns->eth.rx_discards +
3186 pf->main_vsi->eth_stats.rx_discards;
3187 stats->ierrors = ns->crc_errors +
3188 ns->rx_length_errors + ns->rx_undersize +
3189 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3191 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3192 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3193 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3194 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3195 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3196 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3197 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3198 ns->eth.rx_unknown_protocol);
3199 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3200 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3201 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3202 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3203 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3204 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3206 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3207 ns->tx_dropped_link_down);
3208 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3209 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3211 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3212 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3213 ns->mac_local_faults);
3214 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3215 ns->mac_remote_faults);
3216 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3217 ns->rx_length_errors);
3218 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3219 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3220 for (i = 0; i < 8; i++) {
3221 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3222 i, ns->priority_xon_rx[i]);
3223 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3224 i, ns->priority_xoff_rx[i]);
3226 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3227 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3228 for (i = 0; i < 8; i++) {
3229 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3230 i, ns->priority_xon_tx[i]);
3231 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3232 i, ns->priority_xoff_tx[i]);
3233 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3234 i, ns->priority_xon_2_xoff[i]);
3236 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3237 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3238 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3239 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3240 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3241 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3242 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3243 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3244 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3245 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3246 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3247 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3248 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3249 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3250 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3251 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3252 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3253 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3254 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3255 ns->mac_short_packet_dropped);
3256 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3257 ns->checksum_error);
3258 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3259 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3263 /* Reset the statistics */
3265 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3267 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3268 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270 /* Mark PF and VSI stats to update the offset, aka "reset" */
3271 pf->offset_loaded = false;
3273 pf->main_vsi->offset_loaded = false;
3275 /* read the stats, reading current register values into offset */
3276 i40e_read_stats_registers(pf, hw);
3280 i40e_xstats_calc_num(void)
3282 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3283 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3284 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3287 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3288 struct rte_eth_xstat_name *xstats_names,
3289 __rte_unused unsigned limit)
3294 if (xstats_names == NULL)
3295 return i40e_xstats_calc_num();
3297 /* Note: limit checked in rte_eth_xstats_names() */
3299 /* Get stats from i40e_eth_stats struct */
3300 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3301 snprintf(xstats_names[count].name,
3302 sizeof(xstats_names[count].name),
3303 "%s", rte_i40e_stats_strings[i].name);
3307 /* Get individiual stats from i40e_hw_port struct */
3308 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3309 snprintf(xstats_names[count].name,
3310 sizeof(xstats_names[count].name),
3311 "%s", rte_i40e_hw_port_strings[i].name);
3315 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3316 for (prio = 0; prio < 8; prio++) {
3317 snprintf(xstats_names[count].name,
3318 sizeof(xstats_names[count].name),
3319 "rx_priority%u_%s", prio,
3320 rte_i40e_rxq_prio_strings[i].name);
3325 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3326 for (prio = 0; prio < 8; prio++) {
3327 snprintf(xstats_names[count].name,
3328 sizeof(xstats_names[count].name),
3329 "tx_priority%u_%s", prio,
3330 rte_i40e_txq_prio_strings[i].name);
3338 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343 unsigned i, count, prio;
3344 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3346 count = i40e_xstats_calc_num();
3350 i40e_read_stats_registers(pf, hw);
3357 /* Get stats from i40e_eth_stats struct */
3358 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3359 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3360 rte_i40e_stats_strings[i].offset);
3361 xstats[count].id = count;
3365 /* Get individiual stats from i40e_hw_port struct */
3366 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3367 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3368 rte_i40e_hw_port_strings[i].offset);
3369 xstats[count].id = count;
3373 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3374 for (prio = 0; prio < 8; prio++) {
3375 xstats[count].value =
3376 *(uint64_t *)(((char *)hw_stats) +
3377 rte_i40e_rxq_prio_strings[i].offset +
3378 (sizeof(uint64_t) * prio));
3379 xstats[count].id = count;
3384 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3385 for (prio = 0; prio < 8; prio++) {
3386 xstats[count].value =
3387 *(uint64_t *)(((char *)hw_stats) +
3388 rte_i40e_txq_prio_strings[i].offset +
3389 (sizeof(uint64_t) * prio));
3390 xstats[count].id = count;
3399 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3400 __rte_unused uint16_t queue_id,
3401 __rte_unused uint8_t stat_idx,
3402 __rte_unused uint8_t is_rx)
3404 PMD_INIT_FUNC_TRACE();
3410 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3412 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418 full_ver = hw->nvm.oem_ver;
3419 ver = (u8)(full_ver >> 24);
3420 build = (u16)((full_ver >> 8) & 0xffff);
3421 patch = (u8)(full_ver & 0xff);
3423 ret = snprintf(fw_version, fw_size,
3424 "%d.%d%d 0x%08x %d.%d.%d",
3425 ((hw->nvm.version >> 12) & 0xf),
3426 ((hw->nvm.version >> 4) & 0xff),
3427 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3430 ret += 1; /* add the size of '\0' */
3431 if (fw_size < (u32)ret)
3438 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3440 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 struct i40e_vsi *vsi = pf->main_vsi;
3443 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3445 dev_info->max_rx_queues = vsi->nb_qps;
3446 dev_info->max_tx_queues = vsi->nb_qps;
3447 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3448 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3449 dev_info->max_mac_addrs = vsi->max_macaddrs;
3450 dev_info->max_vfs = pci_dev->max_vfs;
3451 dev_info->rx_queue_offload_capa = 0;
3452 dev_info->rx_offload_capa =
3453 DEV_RX_OFFLOAD_VLAN_STRIP |
3454 DEV_RX_OFFLOAD_QINQ_STRIP |
3455 DEV_RX_OFFLOAD_IPV4_CKSUM |
3456 DEV_RX_OFFLOAD_UDP_CKSUM |
3457 DEV_RX_OFFLOAD_TCP_CKSUM |
3458 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3459 DEV_RX_OFFLOAD_KEEP_CRC |
3460 DEV_RX_OFFLOAD_SCATTER |
3461 DEV_RX_OFFLOAD_VLAN_EXTEND |
3462 DEV_RX_OFFLOAD_VLAN_FILTER |
3463 DEV_RX_OFFLOAD_JUMBO_FRAME;
3465 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3466 dev_info->tx_offload_capa =
3467 DEV_TX_OFFLOAD_VLAN_INSERT |
3468 DEV_TX_OFFLOAD_QINQ_INSERT |
3469 DEV_TX_OFFLOAD_IPV4_CKSUM |
3470 DEV_TX_OFFLOAD_UDP_CKSUM |
3471 DEV_TX_OFFLOAD_TCP_CKSUM |
3472 DEV_TX_OFFLOAD_SCTP_CKSUM |
3473 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3474 DEV_TX_OFFLOAD_TCP_TSO |
3475 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3476 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3477 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3478 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3479 DEV_TX_OFFLOAD_MULTI_SEGS |
3480 dev_info->tx_queue_offload_capa;
3481 dev_info->dev_capa =
3482 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3483 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3485 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3487 dev_info->reta_size = pf->hash_lut_size;
3488 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3490 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3492 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3493 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3494 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3496 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3501 dev_info->default_txconf = (struct rte_eth_txconf) {
3503 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3504 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3505 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3507 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3508 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3512 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3513 .nb_max = I40E_MAX_RING_DESC,
3514 .nb_min = I40E_MIN_RING_DESC,
3515 .nb_align = I40E_ALIGN_RING_DESC,
3518 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3519 .nb_max = I40E_MAX_RING_DESC,
3520 .nb_min = I40E_MIN_RING_DESC,
3521 .nb_align = I40E_ALIGN_RING_DESC,
3522 .nb_seg_max = I40E_TX_MAX_SEG,
3523 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3526 if (pf->flags & I40E_FLAG_VMDQ) {
3527 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3528 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3529 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3530 pf->max_nb_vmdq_vsi;
3531 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3532 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3533 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3536 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3538 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3539 dev_info->default_rxportconf.nb_queues = 2;
3540 dev_info->default_txportconf.nb_queues = 2;
3541 if (dev->data->nb_rx_queues == 1)
3542 dev_info->default_rxportconf.ring_size = 2048;
3544 dev_info->default_rxportconf.ring_size = 1024;
3545 if (dev->data->nb_tx_queues == 1)
3546 dev_info->default_txportconf.ring_size = 1024;
3548 dev_info->default_txportconf.ring_size = 512;
3550 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3552 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3553 dev_info->default_rxportconf.nb_queues = 1;
3554 dev_info->default_txportconf.nb_queues = 1;
3555 dev_info->default_rxportconf.ring_size = 256;
3556 dev_info->default_txportconf.ring_size = 256;
3559 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3560 dev_info->default_rxportconf.nb_queues = 1;
3561 dev_info->default_txportconf.nb_queues = 1;
3562 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3563 dev_info->default_rxportconf.ring_size = 512;
3564 dev_info->default_txportconf.ring_size = 256;
3566 dev_info->default_rxportconf.ring_size = 256;
3567 dev_info->default_txportconf.ring_size = 256;
3570 dev_info->default_rxportconf.burst_size = 32;
3571 dev_info->default_txportconf.burst_size = 32;
3575 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3578 struct i40e_vsi *vsi = pf->main_vsi;
3579 PMD_INIT_FUNC_TRACE();
3582 return i40e_vsi_add_vlan(vsi, vlan_id);
3584 return i40e_vsi_delete_vlan(vsi, vlan_id);
3588 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3589 enum rte_vlan_type vlan_type,
3590 uint16_t tpid, int qinq)
3592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 uint16_t reg_id = 3;
3599 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3603 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3605 if (ret != I40E_SUCCESS) {
3607 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3612 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3615 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3616 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3617 if (reg_r == reg_w) {
3618 PMD_DRV_LOG(DEBUG, "No need to write");
3622 ret = i40e_aq_debug_write_global_register(hw,
3623 I40E_GL_SWT_L2TAGCTRL(reg_id),
3625 if (ret != I40E_SUCCESS) {
3627 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3632 "Global register 0x%08x is changed with value 0x%08x",
3633 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3639 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3640 enum rte_vlan_type vlan_type,
3643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3645 int qinq = dev->data->dev_conf.rxmode.offloads &
3646 DEV_RX_OFFLOAD_VLAN_EXTEND;
3649 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3650 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3651 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3653 "Unsupported vlan type.");
3657 if (pf->support_multi_driver) {
3658 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3662 /* 802.1ad frames ability is added in NVM API 1.7*/
3663 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3665 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3666 hw->first_tag = rte_cpu_to_le_16(tpid);
3667 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3668 hw->second_tag = rte_cpu_to_le_16(tpid);
3670 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3671 hw->second_tag = rte_cpu_to_le_16(tpid);
3673 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3674 if (ret != I40E_SUCCESS) {
3676 "Set switch config failed aq_err: %d",
3677 hw->aq.asq_last_status);
3681 /* If NVM API < 1.7, keep the register setting */
3682 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3689 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3692 struct i40e_vsi *vsi = pf->main_vsi;
3693 struct rte_eth_rxmode *rxmode;
3695 rxmode = &dev->data->dev_conf.rxmode;
3696 if (mask & ETH_VLAN_FILTER_MASK) {
3697 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3698 i40e_vsi_config_vlan_filter(vsi, TRUE);
3700 i40e_vsi_config_vlan_filter(vsi, FALSE);
3703 if (mask & ETH_VLAN_STRIP_MASK) {
3704 /* Enable or disable VLAN stripping */
3705 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3706 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3708 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3711 if (mask & ETH_VLAN_EXTEND_MASK) {
3712 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3713 i40e_vsi_config_double_vlan(vsi, TRUE);
3714 /* Set global registers with default ethertype. */
3715 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3717 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3721 i40e_vsi_config_double_vlan(vsi, FALSE);
3728 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3729 __rte_unused uint16_t queue,
3730 __rte_unused int on)
3732 PMD_INIT_FUNC_TRACE();
3736 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3738 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3739 struct i40e_vsi *vsi = pf->main_vsi;
3740 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3741 struct i40e_vsi_vlan_pvid_info info;
3743 memset(&info, 0, sizeof(info));
3746 info.config.pvid = pvid;
3748 info.config.reject.tagged =
3749 data->dev_conf.txmode.hw_vlan_reject_tagged;
3750 info.config.reject.untagged =
3751 data->dev_conf.txmode.hw_vlan_reject_untagged;
3754 return i40e_vsi_vlan_pvid_set(vsi, &info);
3758 i40e_dev_led_on(struct rte_eth_dev *dev)
3760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3761 uint32_t mode = i40e_led_get(hw);
3764 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3770 i40e_dev_led_off(struct rte_eth_dev *dev)
3772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773 uint32_t mode = i40e_led_get(hw);
3776 i40e_led_set(hw, 0, false);
3782 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3787 fc_conf->pause_time = pf->fc_conf.pause_time;
3789 /* read out from register, in case they are modified by other port */
3790 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3791 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3792 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3793 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3795 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3796 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3798 /* Return current mode according to actual setting*/
3799 switch (hw->fc.current_mode) {
3801 fc_conf->mode = RTE_FC_FULL;
3803 case I40E_FC_TX_PAUSE:
3804 fc_conf->mode = RTE_FC_TX_PAUSE;
3806 case I40E_FC_RX_PAUSE:
3807 fc_conf->mode = RTE_FC_RX_PAUSE;
3811 fc_conf->mode = RTE_FC_NONE;
3818 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3820 uint32_t mflcn_reg, fctrl_reg, reg;
3821 uint32_t max_high_water;
3822 uint8_t i, aq_failure;
3826 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3827 [RTE_FC_NONE] = I40E_FC_NONE,
3828 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3829 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3830 [RTE_FC_FULL] = I40E_FC_FULL
3833 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3835 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3836 if ((fc_conf->high_water > max_high_water) ||
3837 (fc_conf->high_water < fc_conf->low_water)) {
3839 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3844 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3848 pf->fc_conf.pause_time = fc_conf->pause_time;
3849 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3850 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3852 PMD_INIT_FUNC_TRACE();
3854 /* All the link flow control related enable/disable register
3855 * configuration is handle by the F/W
3857 err = i40e_set_fc(hw, &aq_failure, true);
3861 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3862 /* Configure flow control refresh threshold,
3863 * the value for stat_tx_pause_refresh_timer[8]
3864 * is used for global pause operation.
3868 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3869 pf->fc_conf.pause_time);
3871 /* configure the timer value included in transmitted pause
3873 * the value for stat_tx_pause_quanta[8] is used for global
3876 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3877 pf->fc_conf.pause_time);
3879 fctrl_reg = I40E_READ_REG(hw,
3880 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3882 if (fc_conf->mac_ctrl_frame_fwd != 0)
3883 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3885 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3887 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3890 /* Configure pause time (2 TCs per register) */
3891 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3892 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3893 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3895 /* Configure flow control refresh threshold value */
3896 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3897 pf->fc_conf.pause_time / 2);
3899 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3901 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3902 *depending on configuration
3904 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3905 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3906 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3908 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3909 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3912 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3915 if (!pf->support_multi_driver) {
3916 /* config water marker both based on the packets and bytes */
3917 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3918 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3919 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3920 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3921 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3922 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3923 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3924 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3926 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3927 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3931 "Water marker configuration is not supported.");
3934 I40E_WRITE_FLUSH(hw);
3940 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3941 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3943 PMD_INIT_FUNC_TRACE();
3948 /* Add a MAC address, and update filters */
3950 i40e_macaddr_add(struct rte_eth_dev *dev,
3951 struct ether_addr *mac_addr,
3952 __rte_unused uint32_t index,
3955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3956 struct i40e_mac_filter_info mac_filter;
3957 struct i40e_vsi *vsi;
3958 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3961 /* If VMDQ not enabled or configured, return */
3962 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3963 !pf->nb_cfg_vmdq_vsi)) {
3964 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3965 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3970 if (pool > pf->nb_cfg_vmdq_vsi) {
3971 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3972 pool, pf->nb_cfg_vmdq_vsi);
3976 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3977 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3978 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3980 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3985 vsi = pf->vmdq[pool - 1].vsi;
3987 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3988 if (ret != I40E_SUCCESS) {
3989 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3995 /* Remove a MAC address, and update filters */
3997 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3999 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4000 struct i40e_vsi *vsi;
4001 struct rte_eth_dev_data *data = dev->data;
4002 struct ether_addr *macaddr;
4007 macaddr = &(data->mac_addrs[index]);
4009 pool_sel = dev->data->mac_pool_sel[index];
4011 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4012 if (pool_sel & (1ULL << i)) {
4016 /* No VMDQ pool enabled or configured */
4017 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4018 (i > pf->nb_cfg_vmdq_vsi)) {
4020 "No VMDQ pool enabled/configured");
4023 vsi = pf->vmdq[i - 1].vsi;
4025 ret = i40e_vsi_delete_mac(vsi, macaddr);
4028 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4035 /* Set perfect match or hash match of MAC and VLAN for a VF */
4037 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4038 struct rte_eth_mac_filter *filter,
4042 struct i40e_mac_filter_info mac_filter;
4043 struct ether_addr old_mac;
4044 struct ether_addr *new_mac;
4045 struct i40e_pf_vf *vf = NULL;
4050 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4053 hw = I40E_PF_TO_HW(pf);
4055 if (filter == NULL) {
4056 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4060 new_mac = &filter->mac_addr;
4062 if (is_zero_ether_addr(new_mac)) {
4063 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4067 vf_id = filter->dst_id;
4069 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4070 PMD_DRV_LOG(ERR, "Invalid argument.");
4073 vf = &pf->vfs[vf_id];
4075 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4076 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4081 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4082 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4084 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4087 mac_filter.filter_type = filter->filter_type;
4088 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4089 if (ret != I40E_SUCCESS) {
4090 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4093 ether_addr_copy(new_mac, &pf->dev_addr);
4095 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4097 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4098 if (ret != I40E_SUCCESS) {
4099 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4103 /* Clear device address as it has been removed */
4104 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4105 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4111 /* MAC filter handle */
4113 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4116 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4117 struct rte_eth_mac_filter *filter;
4118 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4119 int ret = I40E_NOT_SUPPORTED;
4121 filter = (struct rte_eth_mac_filter *)(arg);
4123 switch (filter_op) {
4124 case RTE_ETH_FILTER_NOP:
4127 case RTE_ETH_FILTER_ADD:
4128 i40e_pf_disable_irq0(hw);
4130 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4131 i40e_pf_enable_irq0(hw);
4133 case RTE_ETH_FILTER_DELETE:
4134 i40e_pf_disable_irq0(hw);
4136 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4137 i40e_pf_enable_irq0(hw);
4140 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4141 ret = I40E_ERR_PARAM;
4149 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4151 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4152 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4160 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4163 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4167 uint32_t *lut_dw = (uint32_t *)lut;
4168 uint16_t i, lut_size_dw = lut_size / 4;
4170 if (vsi->type == I40E_VSI_SRIOV) {
4171 for (i = 0; i <= lut_size_dw; i++) {
4172 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4173 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4176 for (i = 0; i < lut_size_dw; i++)
4177 lut_dw[i] = I40E_READ_REG(hw,
4186 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4195 pf = I40E_VSI_TO_PF(vsi);
4196 hw = I40E_VSI_TO_HW(vsi);
4198 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4199 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4202 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4206 uint32_t *lut_dw = (uint32_t *)lut;
4207 uint16_t i, lut_size_dw = lut_size / 4;
4209 if (vsi->type == I40E_VSI_SRIOV) {
4210 for (i = 0; i < lut_size_dw; i++)
4213 I40E_VFQF_HLUT1(i, vsi->user_param),
4216 for (i = 0; i < lut_size_dw; i++)
4217 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4220 I40E_WRITE_FLUSH(hw);
4227 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4228 struct rte_eth_rss_reta_entry64 *reta_conf,
4231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4232 uint16_t i, lut_size = pf->hash_lut_size;
4233 uint16_t idx, shift;
4237 if (reta_size != lut_size ||
4238 reta_size > ETH_RSS_RETA_SIZE_512) {
4240 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4241 reta_size, lut_size);
4245 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4247 PMD_DRV_LOG(ERR, "No memory can be allocated");
4250 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4253 for (i = 0; i < reta_size; i++) {
4254 idx = i / RTE_RETA_GROUP_SIZE;
4255 shift = i % RTE_RETA_GROUP_SIZE;
4256 if (reta_conf[idx].mask & (1ULL << shift))
4257 lut[i] = reta_conf[idx].reta[shift];
4259 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4268 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4269 struct rte_eth_rss_reta_entry64 *reta_conf,
4272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4273 uint16_t i, lut_size = pf->hash_lut_size;
4274 uint16_t idx, shift;
4278 if (reta_size != lut_size ||
4279 reta_size > ETH_RSS_RETA_SIZE_512) {
4281 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4282 reta_size, lut_size);
4286 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4288 PMD_DRV_LOG(ERR, "No memory can be allocated");
4292 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4295 for (i = 0; i < reta_size; i++) {
4296 idx = i / RTE_RETA_GROUP_SIZE;
4297 shift = i % RTE_RETA_GROUP_SIZE;
4298 if (reta_conf[idx].mask & (1ULL << shift))
4299 reta_conf[idx].reta[shift] = lut[i];
4309 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4310 * @hw: pointer to the HW structure
4311 * @mem: pointer to mem struct to fill out
4312 * @size: size of memory requested
4313 * @alignment: what to align the allocation to
4315 enum i40e_status_code
4316 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4317 struct i40e_dma_mem *mem,
4321 const struct rte_memzone *mz = NULL;
4322 char z_name[RTE_MEMZONE_NAMESIZE];
4325 return I40E_ERR_PARAM;
4327 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4328 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4329 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4331 return I40E_ERR_NO_MEMORY;
4336 mem->zone = (const void *)mz;
4338 "memzone %s allocated with physical address: %"PRIu64,
4341 return I40E_SUCCESS;
4345 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4346 * @hw: pointer to the HW structure
4347 * @mem: ptr to mem struct to free
4349 enum i40e_status_code
4350 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4351 struct i40e_dma_mem *mem)
4354 return I40E_ERR_PARAM;
4357 "memzone %s to be freed with physical address: %"PRIu64,
4358 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4359 rte_memzone_free((const struct rte_memzone *)mem->zone);
4364 return I40E_SUCCESS;
4368 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4369 * @hw: pointer to the HW structure
4370 * @mem: pointer to mem struct to fill out
4371 * @size: size of memory requested
4373 enum i40e_status_code
4374 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4375 struct i40e_virt_mem *mem,
4379 return I40E_ERR_PARAM;
4382 mem->va = rte_zmalloc("i40e", size, 0);
4385 return I40E_SUCCESS;
4387 return I40E_ERR_NO_MEMORY;
4391 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4392 * @hw: pointer to the HW structure
4393 * @mem: pointer to mem struct to free
4395 enum i40e_status_code
4396 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4397 struct i40e_virt_mem *mem)
4400 return I40E_ERR_PARAM;
4405 return I40E_SUCCESS;
4409 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4411 rte_spinlock_init(&sp->spinlock);
4415 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4417 rte_spinlock_lock(&sp->spinlock);
4421 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4423 rte_spinlock_unlock(&sp->spinlock);
4427 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4433 * Get the hardware capabilities, which will be parsed
4434 * and saved into struct i40e_hw.
4437 i40e_get_cap(struct i40e_hw *hw)
4439 struct i40e_aqc_list_capabilities_element_resp *buf;
4440 uint16_t len, size = 0;
4443 /* Calculate a huge enough buff for saving response data temporarily */
4444 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4445 I40E_MAX_CAP_ELE_NUM;
4446 buf = rte_zmalloc("i40e", len, 0);
4448 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4449 return I40E_ERR_NO_MEMORY;
4452 /* Get, parse the capabilities and save it to hw */
4453 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4454 i40e_aqc_opc_list_func_capabilities, NULL);
4455 if (ret != I40E_SUCCESS)
4456 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4458 /* Free the temporary buffer after being used */
4464 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4466 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4474 pf = (struct i40e_pf *)opaque;
4478 num = strtoul(value, &end, 0);
4479 if (errno != 0 || end == value || *end != 0) {
4480 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4481 "kept the value = %hu", value, pf->vf_nb_qp_max);
4485 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4486 pf->vf_nb_qp_max = (uint16_t)num;
4488 /* here return 0 to make next valid same argument work */
4489 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4490 "power of 2 and equal or less than 16 !, Now it is "
4491 "kept the value = %hu", num, pf->vf_nb_qp_max);
4496 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4499 struct rte_kvargs *kvlist;
4502 /* set default queue number per VF as 4 */
4503 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4505 if (dev->device->devargs == NULL)
4508 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4512 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4513 if (!kvargs_count) {
4514 rte_kvargs_free(kvlist);
4518 if (kvargs_count > 1)
4519 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4520 "the first invalid or last valid one is used !",
4521 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4523 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4524 i40e_pf_parse_vf_queue_number_handler, pf);
4526 rte_kvargs_free(kvlist);
4532 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4535 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4536 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4537 uint16_t qp_count = 0, vsi_count = 0;
4539 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4540 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4544 i40e_pf_config_vf_rxq_number(dev);
4546 /* Add the parameter init for LFC */
4547 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4548 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4549 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4551 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4552 pf->max_num_vsi = hw->func_caps.num_vsis;
4553 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4554 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4556 /* FDir queue/VSI allocation */
4557 pf->fdir_qp_offset = 0;
4558 if (hw->func_caps.fd) {
4559 pf->flags |= I40E_FLAG_FDIR;
4560 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4562 pf->fdir_nb_qps = 0;
4564 qp_count += pf->fdir_nb_qps;
4567 /* LAN queue/VSI allocation */
4568 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4569 if (!hw->func_caps.rss) {
4572 pf->flags |= I40E_FLAG_RSS;
4573 if (hw->mac.type == I40E_MAC_X722)
4574 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4575 pf->lan_nb_qps = pf->lan_nb_qp_max;
4577 qp_count += pf->lan_nb_qps;
4580 /* VF queue/VSI allocation */
4581 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4582 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4583 pf->flags |= I40E_FLAG_SRIOV;
4584 pf->vf_nb_qps = pf->vf_nb_qp_max;
4585 pf->vf_num = pci_dev->max_vfs;
4587 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4588 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4593 qp_count += pf->vf_nb_qps * pf->vf_num;
4594 vsi_count += pf->vf_num;
4596 /* VMDq queue/VSI allocation */
4597 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4598 pf->vmdq_nb_qps = 0;
4599 pf->max_nb_vmdq_vsi = 0;
4600 if (hw->func_caps.vmdq) {
4601 if (qp_count < hw->func_caps.num_tx_qp &&
4602 vsi_count < hw->func_caps.num_vsis) {
4603 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4604 qp_count) / pf->vmdq_nb_qp_max;
4606 /* Limit the maximum number of VMDq vsi to the maximum
4607 * ethdev can support
4609 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4610 hw->func_caps.num_vsis - vsi_count);
4611 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4613 if (pf->max_nb_vmdq_vsi) {
4614 pf->flags |= I40E_FLAG_VMDQ;
4615 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4617 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4618 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4619 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4622 "No enough queues left for VMDq");
4625 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4628 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4629 vsi_count += pf->max_nb_vmdq_vsi;
4631 if (hw->func_caps.dcb)
4632 pf->flags |= I40E_FLAG_DCB;
4634 if (qp_count > hw->func_caps.num_tx_qp) {
4636 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4637 qp_count, hw->func_caps.num_tx_qp);
4640 if (vsi_count > hw->func_caps.num_vsis) {
4642 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4643 vsi_count, hw->func_caps.num_vsis);
4651 i40e_pf_get_switch_config(struct i40e_pf *pf)
4653 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4654 struct i40e_aqc_get_switch_config_resp *switch_config;
4655 struct i40e_aqc_switch_config_element_resp *element;
4656 uint16_t start_seid = 0, num_reported;
4659 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4660 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4661 if (!switch_config) {
4662 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4666 /* Get the switch configurations */
4667 ret = i40e_aq_get_switch_config(hw, switch_config,
4668 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4669 if (ret != I40E_SUCCESS) {
4670 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4673 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4674 if (num_reported != 1) { /* The number should be 1 */
4675 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4679 /* Parse the switch configuration elements */
4680 element = &(switch_config->element[0]);
4681 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4682 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4683 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4685 PMD_DRV_LOG(INFO, "Unknown element type");
4688 rte_free(switch_config);
4694 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4697 struct pool_entry *entry;
4699 if (pool == NULL || num == 0)
4702 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4703 if (entry == NULL) {
4704 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4708 /* queue heap initialize */
4709 pool->num_free = num;
4710 pool->num_alloc = 0;
4712 LIST_INIT(&pool->alloc_list);
4713 LIST_INIT(&pool->free_list);
4715 /* Initialize element */
4719 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4724 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4726 struct pool_entry *entry, *next_entry;
4731 for (entry = LIST_FIRST(&pool->alloc_list);
4732 entry && (next_entry = LIST_NEXT(entry, next), 1);
4733 entry = next_entry) {
4734 LIST_REMOVE(entry, next);
4738 for (entry = LIST_FIRST(&pool->free_list);
4739 entry && (next_entry = LIST_NEXT(entry, next), 1);
4740 entry = next_entry) {
4741 LIST_REMOVE(entry, next);
4746 pool->num_alloc = 0;
4748 LIST_INIT(&pool->alloc_list);
4749 LIST_INIT(&pool->free_list);
4753 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4756 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4757 uint32_t pool_offset;
4761 PMD_DRV_LOG(ERR, "Invalid parameter");
4765 pool_offset = base - pool->base;
4766 /* Lookup in alloc list */
4767 LIST_FOREACH(entry, &pool->alloc_list, next) {
4768 if (entry->base == pool_offset) {
4769 valid_entry = entry;
4770 LIST_REMOVE(entry, next);
4775 /* Not find, return */
4776 if (valid_entry == NULL) {
4777 PMD_DRV_LOG(ERR, "Failed to find entry");
4782 * Found it, move it to free list and try to merge.
4783 * In order to make merge easier, always sort it by qbase.
4784 * Find adjacent prev and last entries.
4787 LIST_FOREACH(entry, &pool->free_list, next) {
4788 if (entry->base > valid_entry->base) {
4796 /* Try to merge with next one*/
4798 /* Merge with next one */
4799 if (valid_entry->base + valid_entry->len == next->base) {
4800 next->base = valid_entry->base;
4801 next->len += valid_entry->len;
4802 rte_free(valid_entry);
4809 /* Merge with previous one */
4810 if (prev->base + prev->len == valid_entry->base) {
4811 prev->len += valid_entry->len;
4812 /* If it merge with next one, remove next node */
4814 LIST_REMOVE(valid_entry, next);
4815 rte_free(valid_entry);
4817 rte_free(valid_entry);
4823 /* Not find any entry to merge, insert */
4826 LIST_INSERT_AFTER(prev, valid_entry, next);
4827 else if (next != NULL)
4828 LIST_INSERT_BEFORE(next, valid_entry, next);
4829 else /* It's empty list, insert to head */
4830 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4833 pool->num_free += valid_entry->len;
4834 pool->num_alloc -= valid_entry->len;
4840 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4843 struct pool_entry *entry, *valid_entry;
4845 if (pool == NULL || num == 0) {
4846 PMD_DRV_LOG(ERR, "Invalid parameter");
4850 if (pool->num_free < num) {
4851 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4852 num, pool->num_free);
4857 /* Lookup in free list and find most fit one */
4858 LIST_FOREACH(entry, &pool->free_list, next) {
4859 if (entry->len >= num) {
4861 if (entry->len == num) {
4862 valid_entry = entry;
4865 if (valid_entry == NULL || valid_entry->len > entry->len)
4866 valid_entry = entry;
4870 /* Not find one to satisfy the request, return */
4871 if (valid_entry == NULL) {
4872 PMD_DRV_LOG(ERR, "No valid entry found");
4876 * The entry have equal queue number as requested,
4877 * remove it from alloc_list.
4879 if (valid_entry->len == num) {
4880 LIST_REMOVE(valid_entry, next);
4883 * The entry have more numbers than requested,
4884 * create a new entry for alloc_list and minus its
4885 * queue base and number in free_list.
4887 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4888 if (entry == NULL) {
4890 "Failed to allocate memory for resource pool");
4893 entry->base = valid_entry->base;
4895 valid_entry->base += num;
4896 valid_entry->len -= num;
4897 valid_entry = entry;
4900 /* Insert it into alloc list, not sorted */
4901 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4903 pool->num_free -= valid_entry->len;
4904 pool->num_alloc += valid_entry->len;
4906 return valid_entry->base + pool->base;
4910 * bitmap_is_subset - Check whether src2 is subset of src1
4913 bitmap_is_subset(uint8_t src1, uint8_t src2)
4915 return !((src1 ^ src2) & src2);
4918 static enum i40e_status_code
4919 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4921 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4923 /* If DCB is not supported, only default TC is supported */
4924 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4925 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4926 return I40E_NOT_SUPPORTED;
4929 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4931 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4932 hw->func_caps.enabled_tcmap, enabled_tcmap);
4933 return I40E_NOT_SUPPORTED;
4935 return I40E_SUCCESS;
4939 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4940 struct i40e_vsi_vlan_pvid_info *info)
4943 struct i40e_vsi_context ctxt;
4944 uint8_t vlan_flags = 0;
4947 if (vsi == NULL || info == NULL) {
4948 PMD_DRV_LOG(ERR, "invalid parameters");
4949 return I40E_ERR_PARAM;
4953 vsi->info.pvid = info->config.pvid;
4955 * If insert pvid is enabled, only tagged pkts are
4956 * allowed to be sent out.
4958 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4959 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4962 if (info->config.reject.tagged == 0)
4963 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4965 if (info->config.reject.untagged == 0)
4966 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4968 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4969 I40E_AQ_VSI_PVLAN_MODE_MASK);
4970 vsi->info.port_vlan_flags |= vlan_flags;
4971 vsi->info.valid_sections =
4972 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4973 memset(&ctxt, 0, sizeof(ctxt));
4974 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4975 ctxt.seid = vsi->seid;
4977 hw = I40E_VSI_TO_HW(vsi);
4978 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4979 if (ret != I40E_SUCCESS)
4980 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4986 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4990 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4992 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4993 if (ret != I40E_SUCCESS)
4997 PMD_DRV_LOG(ERR, "seid not valid");
5001 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5002 tc_bw_data.tc_valid_bits = enabled_tcmap;
5003 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5004 tc_bw_data.tc_bw_credits[i] =
5005 (enabled_tcmap & (1 << i)) ? 1 : 0;
5007 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5008 if (ret != I40E_SUCCESS) {
5009 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5013 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5014 sizeof(vsi->info.qs_handle));
5015 return I40E_SUCCESS;
5018 static enum i40e_status_code
5019 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5020 struct i40e_aqc_vsi_properties_data *info,
5021 uint8_t enabled_tcmap)
5023 enum i40e_status_code ret;
5024 int i, total_tc = 0;
5025 uint16_t qpnum_per_tc, bsf, qp_idx;
5027 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5028 if (ret != I40E_SUCCESS)
5031 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5032 if (enabled_tcmap & (1 << i))
5036 vsi->enabled_tc = enabled_tcmap;
5038 /* Number of queues per enabled TC */
5039 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5040 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5041 bsf = rte_bsf32(qpnum_per_tc);
5043 /* Adjust the queue number to actual queues that can be applied */
5044 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5045 vsi->nb_qps = qpnum_per_tc * total_tc;
5048 * Configure TC and queue mapping parameters, for enabled TC,
5049 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5050 * default queue will serve it.
5053 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5054 if (vsi->enabled_tc & (1 << i)) {
5055 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5056 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5057 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5058 qp_idx += qpnum_per_tc;
5060 info->tc_mapping[i] = 0;
5063 /* Associate queue number with VSI */
5064 if (vsi->type == I40E_VSI_SRIOV) {
5065 info->mapping_flags |=
5066 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5067 for (i = 0; i < vsi->nb_qps; i++)
5068 info->queue_mapping[i] =
5069 rte_cpu_to_le_16(vsi->base_queue + i);
5071 info->mapping_flags |=
5072 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5073 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5075 info->valid_sections |=
5076 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5078 return I40E_SUCCESS;
5082 i40e_veb_release(struct i40e_veb *veb)
5084 struct i40e_vsi *vsi;
5090 if (!TAILQ_EMPTY(&veb->head)) {
5091 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5094 /* associate_vsi field is NULL for floating VEB */
5095 if (veb->associate_vsi != NULL) {
5096 vsi = veb->associate_vsi;
5097 hw = I40E_VSI_TO_HW(vsi);
5099 vsi->uplink_seid = veb->uplink_seid;
5102 veb->associate_pf->main_vsi->floating_veb = NULL;
5103 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5106 i40e_aq_delete_element(hw, veb->seid, NULL);
5108 return I40E_SUCCESS;
5112 static struct i40e_veb *
5113 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5115 struct i40e_veb *veb;
5121 "veb setup failed, associated PF shouldn't null");
5124 hw = I40E_PF_TO_HW(pf);
5126 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5128 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5132 veb->associate_vsi = vsi;
5133 veb->associate_pf = pf;
5134 TAILQ_INIT(&veb->head);
5135 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5137 /* create floating veb if vsi is NULL */
5139 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5140 I40E_DEFAULT_TCMAP, false,
5141 &veb->seid, false, NULL);
5143 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5144 true, &veb->seid, false, NULL);
5147 if (ret != I40E_SUCCESS) {
5148 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5149 hw->aq.asq_last_status);
5152 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5154 /* get statistics index */
5155 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5156 &veb->stats_idx, NULL, NULL, NULL);
5157 if (ret != I40E_SUCCESS) {
5158 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5159 hw->aq.asq_last_status);
5162 /* Get VEB bandwidth, to be implemented */
5163 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5165 vsi->uplink_seid = veb->seid;
5174 i40e_vsi_release(struct i40e_vsi *vsi)
5178 struct i40e_vsi_list *vsi_list;
5181 struct i40e_mac_filter *f;
5182 uint16_t user_param;
5185 return I40E_SUCCESS;
5190 user_param = vsi->user_param;
5192 pf = I40E_VSI_TO_PF(vsi);
5193 hw = I40E_VSI_TO_HW(vsi);
5195 /* VSI has child to attach, release child first */
5197 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5198 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5201 i40e_veb_release(vsi->veb);
5204 if (vsi->floating_veb) {
5205 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5206 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5211 /* Remove all macvlan filters of the VSI */
5212 i40e_vsi_remove_all_macvlan_filter(vsi);
5213 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5216 if (vsi->type != I40E_VSI_MAIN &&
5217 ((vsi->type != I40E_VSI_SRIOV) ||
5218 !pf->floating_veb_list[user_param])) {
5219 /* Remove vsi from parent's sibling list */
5220 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5221 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5222 return I40E_ERR_PARAM;
5224 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5225 &vsi->sib_vsi_list, list);
5227 /* Remove all switch element of the VSI */
5228 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5229 if (ret != I40E_SUCCESS)
5230 PMD_DRV_LOG(ERR, "Failed to delete element");
5233 if ((vsi->type == I40E_VSI_SRIOV) &&
5234 pf->floating_veb_list[user_param]) {
5235 /* Remove vsi from parent's sibling list */
5236 if (vsi->parent_vsi == NULL ||
5237 vsi->parent_vsi->floating_veb == NULL) {
5238 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5239 return I40E_ERR_PARAM;
5241 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5242 &vsi->sib_vsi_list, list);
5244 /* Remove all switch element of the VSI */
5245 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5246 if (ret != I40E_SUCCESS)
5247 PMD_DRV_LOG(ERR, "Failed to delete element");
5250 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5252 if (vsi->type != I40E_VSI_SRIOV)
5253 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5256 return I40E_SUCCESS;
5260 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5262 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5263 struct i40e_aqc_remove_macvlan_element_data def_filter;
5264 struct i40e_mac_filter_info filter;
5267 if (vsi->type != I40E_VSI_MAIN)
5268 return I40E_ERR_CONFIG;
5269 memset(&def_filter, 0, sizeof(def_filter));
5270 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5272 def_filter.vlan_tag = 0;
5273 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5274 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5275 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5276 if (ret != I40E_SUCCESS) {
5277 struct i40e_mac_filter *f;
5278 struct ether_addr *mac;
5281 "Cannot remove the default macvlan filter");
5282 /* It needs to add the permanent mac into mac list */
5283 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5285 PMD_DRV_LOG(ERR, "failed to allocate memory");
5286 return I40E_ERR_NO_MEMORY;
5288 mac = &f->mac_info.mac_addr;
5289 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5291 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5292 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5297 rte_memcpy(&filter.mac_addr,
5298 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5299 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5300 return i40e_vsi_add_mac(vsi, &filter);
5304 * i40e_vsi_get_bw_config - Query VSI BW Information
5305 * @vsi: the VSI to be queried
5307 * Returns 0 on success, negative value on failure
5309 static enum i40e_status_code
5310 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5312 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5313 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5314 struct i40e_hw *hw = &vsi->adapter->hw;
5319 memset(&bw_config, 0, sizeof(bw_config));
5320 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5321 if (ret != I40E_SUCCESS) {
5322 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5323 hw->aq.asq_last_status);
5327 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5328 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5329 &ets_sla_config, NULL);
5330 if (ret != I40E_SUCCESS) {
5332 "VSI failed to get TC bandwdith configuration %u",
5333 hw->aq.asq_last_status);
5337 /* store and print out BW info */
5338 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5339 vsi->bw_info.bw_max = bw_config.max_bw;
5340 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5341 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5342 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5343 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5345 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5346 vsi->bw_info.bw_ets_share_credits[i] =
5347 ets_sla_config.share_credits[i];
5348 vsi->bw_info.bw_ets_credits[i] =
5349 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5350 /* 4 bits per TC, 4th bit is reserved */
5351 vsi->bw_info.bw_ets_max[i] =
5352 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5353 RTE_LEN2MASK(3, uint8_t));
5354 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5355 vsi->bw_info.bw_ets_share_credits[i]);
5356 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5357 vsi->bw_info.bw_ets_credits[i]);
5358 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5359 vsi->bw_info.bw_ets_max[i]);
5362 return I40E_SUCCESS;
5365 /* i40e_enable_pf_lb
5366 * @pf: pointer to the pf structure
5368 * allow loopback on pf
5371 i40e_enable_pf_lb(struct i40e_pf *pf)
5373 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5374 struct i40e_vsi_context ctxt;
5377 /* Use the FW API if FW >= v5.0 */
5378 if (hw->aq.fw_maj_ver < 5) {
5379 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5383 memset(&ctxt, 0, sizeof(ctxt));
5384 ctxt.seid = pf->main_vsi_seid;
5385 ctxt.pf_num = hw->pf_id;
5386 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5388 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5389 ret, hw->aq.asq_last_status);
5392 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5393 ctxt.info.valid_sections =
5394 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5395 ctxt.info.switch_id |=
5396 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5398 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5400 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5401 hw->aq.asq_last_status);
5406 i40e_vsi_setup(struct i40e_pf *pf,
5407 enum i40e_vsi_type type,
5408 struct i40e_vsi *uplink_vsi,
5409 uint16_t user_param)
5411 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5412 struct i40e_vsi *vsi;
5413 struct i40e_mac_filter_info filter;
5415 struct i40e_vsi_context ctxt;
5416 struct ether_addr broadcast =
5417 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5419 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5420 uplink_vsi == NULL) {
5422 "VSI setup failed, VSI link shouldn't be NULL");
5426 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5428 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5433 * 1.type is not MAIN and uplink vsi is not NULL
5434 * If uplink vsi didn't setup VEB, create one first under veb field
5435 * 2.type is SRIOV and the uplink is NULL
5436 * If floating VEB is NULL, create one veb under floating veb field
5439 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5440 uplink_vsi->veb == NULL) {
5441 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5443 if (uplink_vsi->veb == NULL) {
5444 PMD_DRV_LOG(ERR, "VEB setup failed");
5447 /* set ALLOWLOOPBACk on pf, when veb is created */
5448 i40e_enable_pf_lb(pf);
5451 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5452 pf->main_vsi->floating_veb == NULL) {
5453 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5455 if (pf->main_vsi->floating_veb == NULL) {
5456 PMD_DRV_LOG(ERR, "VEB setup failed");
5461 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5463 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5466 TAILQ_INIT(&vsi->mac_list);
5468 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5469 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5470 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5471 vsi->user_param = user_param;
5472 vsi->vlan_anti_spoof_on = 0;
5473 vsi->vlan_filter_on = 0;
5474 /* Allocate queues */
5475 switch (vsi->type) {
5476 case I40E_VSI_MAIN :
5477 vsi->nb_qps = pf->lan_nb_qps;
5479 case I40E_VSI_SRIOV :
5480 vsi->nb_qps = pf->vf_nb_qps;
5482 case I40E_VSI_VMDQ2:
5483 vsi->nb_qps = pf->vmdq_nb_qps;
5486 vsi->nb_qps = pf->fdir_nb_qps;
5492 * The filter status descriptor is reported in rx queue 0,
5493 * while the tx queue for fdir filter programming has no
5494 * such constraints, can be non-zero queues.
5495 * To simplify it, choose FDIR vsi use queue 0 pair.
5496 * To make sure it will use queue 0 pair, queue allocation
5497 * need be done before this function is called
5499 if (type != I40E_VSI_FDIR) {
5500 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5502 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5506 vsi->base_queue = ret;
5508 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5510 /* VF has MSIX interrupt in VF range, don't allocate here */
5511 if (type == I40E_VSI_MAIN) {
5512 if (pf->support_multi_driver) {
5513 /* If support multi-driver, need to use INT0 instead of
5514 * allocating from msix pool. The Msix pool is init from
5515 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5516 * to 1 without calling i40e_res_pool_alloc.
5521 ret = i40e_res_pool_alloc(&pf->msix_pool,
5522 RTE_MIN(vsi->nb_qps,
5523 RTE_MAX_RXTX_INTR_VEC_ID));
5526 "VSI MAIN %d get heap failed %d",
5528 goto fail_queue_alloc;
5530 vsi->msix_intr = ret;
5531 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5532 RTE_MAX_RXTX_INTR_VEC_ID);
5534 } else if (type != I40E_VSI_SRIOV) {
5535 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5537 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5538 goto fail_queue_alloc;
5540 vsi->msix_intr = ret;
5548 if (type == I40E_VSI_MAIN) {
5549 /* For main VSI, no need to add since it's default one */
5550 vsi->uplink_seid = pf->mac_seid;
5551 vsi->seid = pf->main_vsi_seid;
5552 /* Bind queues with specific MSIX interrupt */
5554 * Needs 2 interrupt at least, one for misc cause which will
5555 * enabled from OS side, Another for queues binding the
5556 * interrupt from device side only.
5559 /* Get default VSI parameters from hardware */
5560 memset(&ctxt, 0, sizeof(ctxt));
5561 ctxt.seid = vsi->seid;
5562 ctxt.pf_num = hw->pf_id;
5563 ctxt.uplink_seid = vsi->uplink_seid;
5565 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5566 if (ret != I40E_SUCCESS) {
5567 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5568 goto fail_msix_alloc;
5570 rte_memcpy(&vsi->info, &ctxt.info,
5571 sizeof(struct i40e_aqc_vsi_properties_data));
5572 vsi->vsi_id = ctxt.vsi_number;
5573 vsi->info.valid_sections = 0;
5575 /* Configure tc, enabled TC0 only */
5576 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5578 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5579 goto fail_msix_alloc;
5582 /* TC, queue mapping */
5583 memset(&ctxt, 0, sizeof(ctxt));
5584 vsi->info.valid_sections |=
5585 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5586 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5587 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5588 rte_memcpy(&ctxt.info, &vsi->info,
5589 sizeof(struct i40e_aqc_vsi_properties_data));
5590 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5591 I40E_DEFAULT_TCMAP);
5592 if (ret != I40E_SUCCESS) {
5594 "Failed to configure TC queue mapping");
5595 goto fail_msix_alloc;
5597 ctxt.seid = vsi->seid;
5598 ctxt.pf_num = hw->pf_id;
5599 ctxt.uplink_seid = vsi->uplink_seid;
5602 /* Update VSI parameters */
5603 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5604 if (ret != I40E_SUCCESS) {
5605 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5606 goto fail_msix_alloc;
5609 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5610 sizeof(vsi->info.tc_mapping));
5611 rte_memcpy(&vsi->info.queue_mapping,
5612 &ctxt.info.queue_mapping,
5613 sizeof(vsi->info.queue_mapping));
5614 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5615 vsi->info.valid_sections = 0;
5617 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5621 * Updating default filter settings are necessary to prevent
5622 * reception of tagged packets.
5623 * Some old firmware configurations load a default macvlan
5624 * filter which accepts both tagged and untagged packets.
5625 * The updating is to use a normal filter instead if needed.
5626 * For NVM 4.2.2 or after, the updating is not needed anymore.
5627 * The firmware with correct configurations load the default
5628 * macvlan filter which is expected and cannot be removed.
5630 i40e_update_default_filter_setting(vsi);
5631 i40e_config_qinq(hw, vsi);
5632 } else if (type == I40E_VSI_SRIOV) {
5633 memset(&ctxt, 0, sizeof(ctxt));
5635 * For other VSI, the uplink_seid equals to uplink VSI's
5636 * uplink_seid since they share same VEB
5638 if (uplink_vsi == NULL)
5639 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5641 vsi->uplink_seid = uplink_vsi->uplink_seid;
5642 ctxt.pf_num = hw->pf_id;
5643 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5644 ctxt.uplink_seid = vsi->uplink_seid;
5645 ctxt.connection_type = 0x1;
5646 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5648 /* Use the VEB configuration if FW >= v5.0 */
5649 if (hw->aq.fw_maj_ver >= 5) {
5650 /* Configure switch ID */
5651 ctxt.info.valid_sections |=
5652 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5653 ctxt.info.switch_id =
5654 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5657 /* Configure port/vlan */
5658 ctxt.info.valid_sections |=
5659 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5660 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5661 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5662 hw->func_caps.enabled_tcmap);
5663 if (ret != I40E_SUCCESS) {
5665 "Failed to configure TC queue mapping");
5666 goto fail_msix_alloc;
5669 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5670 ctxt.info.valid_sections |=
5671 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5673 * Since VSI is not created yet, only configure parameter,
5674 * will add vsi below.
5677 i40e_config_qinq(hw, vsi);
5678 } else if (type == I40E_VSI_VMDQ2) {
5679 memset(&ctxt, 0, sizeof(ctxt));
5681 * For other VSI, the uplink_seid equals to uplink VSI's
5682 * uplink_seid since they share same VEB
5684 vsi->uplink_seid = uplink_vsi->uplink_seid;
5685 ctxt.pf_num = hw->pf_id;
5687 ctxt.uplink_seid = vsi->uplink_seid;
5688 ctxt.connection_type = 0x1;
5689 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5691 ctxt.info.valid_sections |=
5692 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5693 /* user_param carries flag to enable loop back */
5695 ctxt.info.switch_id =
5696 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5697 ctxt.info.switch_id |=
5698 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5701 /* Configure port/vlan */
5702 ctxt.info.valid_sections |=
5703 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5704 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5705 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5706 I40E_DEFAULT_TCMAP);
5707 if (ret != I40E_SUCCESS) {
5709 "Failed to configure TC queue mapping");
5710 goto fail_msix_alloc;
5712 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5713 ctxt.info.valid_sections |=
5714 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5715 } else if (type == I40E_VSI_FDIR) {
5716 memset(&ctxt, 0, sizeof(ctxt));
5717 vsi->uplink_seid = uplink_vsi->uplink_seid;
5718 ctxt.pf_num = hw->pf_id;
5720 ctxt.uplink_seid = vsi->uplink_seid;
5721 ctxt.connection_type = 0x1; /* regular data port */
5722 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5723 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5724 I40E_DEFAULT_TCMAP);
5725 if (ret != I40E_SUCCESS) {
5727 "Failed to configure TC queue mapping.");
5728 goto fail_msix_alloc;
5730 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5731 ctxt.info.valid_sections |=
5732 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5734 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5735 goto fail_msix_alloc;
5738 if (vsi->type != I40E_VSI_MAIN) {
5739 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5740 if (ret != I40E_SUCCESS) {
5741 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5742 hw->aq.asq_last_status);
5743 goto fail_msix_alloc;
5745 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5746 vsi->info.valid_sections = 0;
5747 vsi->seid = ctxt.seid;
5748 vsi->vsi_id = ctxt.vsi_number;
5749 vsi->sib_vsi_list.vsi = vsi;
5750 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5751 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5752 &vsi->sib_vsi_list, list);
5754 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5755 &vsi->sib_vsi_list, list);
5759 /* MAC/VLAN configuration */
5760 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5761 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5763 ret = i40e_vsi_add_mac(vsi, &filter);
5764 if (ret != I40E_SUCCESS) {
5765 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5766 goto fail_msix_alloc;
5769 /* Get VSI BW information */
5770 i40e_vsi_get_bw_config(vsi);
5773 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5775 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5781 /* Configure vlan filter on or off */
5783 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5786 struct i40e_mac_filter *f;
5788 struct i40e_mac_filter_info *mac_filter;
5789 enum rte_mac_filter_type desired_filter;
5790 int ret = I40E_SUCCESS;
5793 /* Filter to match MAC and VLAN */
5794 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5796 /* Filter to match only MAC */
5797 desired_filter = RTE_MAC_PERFECT_MATCH;
5802 mac_filter = rte_zmalloc("mac_filter_info_data",
5803 num * sizeof(*mac_filter), 0);
5804 if (mac_filter == NULL) {
5805 PMD_DRV_LOG(ERR, "failed to allocate memory");
5806 return I40E_ERR_NO_MEMORY;
5811 /* Remove all existing mac */
5812 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5813 mac_filter[i] = f->mac_info;
5814 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5816 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5817 on ? "enable" : "disable");
5823 /* Override with new filter */
5824 for (i = 0; i < num; i++) {
5825 mac_filter[i].filter_type = desired_filter;
5826 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5828 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5829 on ? "enable" : "disable");
5835 rte_free(mac_filter);
5839 /* Configure vlan stripping on or off */
5841 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5843 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5844 struct i40e_vsi_context ctxt;
5846 int ret = I40E_SUCCESS;
5848 /* Check if it has been already on or off */
5849 if (vsi->info.valid_sections &
5850 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5852 if ((vsi->info.port_vlan_flags &
5853 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5854 return 0; /* already on */
5856 if ((vsi->info.port_vlan_flags &
5857 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5858 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5859 return 0; /* already off */
5864 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5866 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5867 vsi->info.valid_sections =
5868 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5869 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5870 vsi->info.port_vlan_flags |= vlan_flags;
5871 ctxt.seid = vsi->seid;
5872 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5873 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5875 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5876 on ? "enable" : "disable");
5882 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5884 struct rte_eth_dev_data *data = dev->data;
5888 /* Apply vlan offload setting */
5889 mask = ETH_VLAN_STRIP_MASK |
5890 ETH_VLAN_FILTER_MASK |
5891 ETH_VLAN_EXTEND_MASK;
5892 ret = i40e_vlan_offload_set(dev, mask);
5894 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5898 /* Apply pvid setting */
5899 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5900 data->dev_conf.txmode.hw_vlan_insert_pvid);
5902 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5908 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5910 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5912 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5916 i40e_update_flow_control(struct i40e_hw *hw)
5918 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5919 struct i40e_link_status link_status;
5920 uint32_t rxfc = 0, txfc = 0, reg;
5924 memset(&link_status, 0, sizeof(link_status));
5925 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5926 if (ret != I40E_SUCCESS) {
5927 PMD_DRV_LOG(ERR, "Failed to get link status information");
5928 goto write_reg; /* Disable flow control */
5931 an_info = hw->phy.link_info.an_info;
5932 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5933 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5934 ret = I40E_ERR_NOT_READY;
5935 goto write_reg; /* Disable flow control */
5938 * If link auto negotiation is enabled, flow control needs to
5939 * be configured according to it
5941 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5942 case I40E_LINK_PAUSE_RXTX:
5945 hw->fc.current_mode = I40E_FC_FULL;
5947 case I40E_AQ_LINK_PAUSE_RX:
5949 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5951 case I40E_AQ_LINK_PAUSE_TX:
5953 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5956 hw->fc.current_mode = I40E_FC_NONE;
5961 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5962 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5963 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5964 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5965 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5966 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5973 i40e_pf_setup(struct i40e_pf *pf)
5975 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5976 struct i40e_filter_control_settings settings;
5977 struct i40e_vsi *vsi;
5980 /* Clear all stats counters */
5981 pf->offset_loaded = FALSE;
5982 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5983 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5984 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5985 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5987 ret = i40e_pf_get_switch_config(pf);
5988 if (ret != I40E_SUCCESS) {
5989 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5993 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5995 PMD_INIT_LOG(WARNING,
5996 "failed to allocate switch domain for device %d", ret);
5998 if (pf->flags & I40E_FLAG_FDIR) {
5999 /* make queue allocated first, let FDIR use queue pair 0*/
6000 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6001 if (ret != I40E_FDIR_QUEUE_ID) {
6003 "queue allocation fails for FDIR: ret =%d",
6005 pf->flags &= ~I40E_FLAG_FDIR;
6008 /* main VSI setup */
6009 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6011 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6012 return I40E_ERR_NOT_READY;
6016 /* Configure filter control */
6017 memset(&settings, 0, sizeof(settings));
6018 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6019 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6020 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6021 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6023 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6024 hw->func_caps.rss_table_size);
6025 return I40E_ERR_PARAM;
6027 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6028 hw->func_caps.rss_table_size);
6029 pf->hash_lut_size = hw->func_caps.rss_table_size;
6031 /* Enable ethtype and macvlan filters */
6032 settings.enable_ethtype = TRUE;
6033 settings.enable_macvlan = TRUE;
6034 ret = i40e_set_filter_control(hw, &settings);
6036 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6039 /* Update flow control according to the auto negotiation */
6040 i40e_update_flow_control(hw);
6042 return I40E_SUCCESS;
6046 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6052 * Set or clear TX Queue Disable flags,
6053 * which is required by hardware.
6055 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6056 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6058 /* Wait until the request is finished */
6059 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6060 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6061 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6062 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6063 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6069 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6070 return I40E_SUCCESS; /* already on, skip next steps */
6072 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6073 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6075 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6076 return I40E_SUCCESS; /* already off, skip next steps */
6077 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6079 /* Write the register */
6080 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6081 /* Check the result */
6082 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6083 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6084 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6086 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6087 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6090 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6091 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6095 /* Check if it is timeout */
6096 if (j >= I40E_CHK_Q_ENA_COUNT) {
6097 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6098 (on ? "enable" : "disable"), q_idx);
6099 return I40E_ERR_TIMEOUT;
6102 return I40E_SUCCESS;
6105 /* Swith on or off the tx queues */
6107 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6109 struct rte_eth_dev_data *dev_data = pf->dev_data;
6110 struct i40e_tx_queue *txq;
6111 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6115 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6116 txq = dev_data->tx_queues[i];
6117 /* Don't operate the queue if not configured or
6118 * if starting only per queue */
6119 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6122 ret = i40e_dev_tx_queue_start(dev, i);
6124 ret = i40e_dev_tx_queue_stop(dev, i);
6125 if ( ret != I40E_SUCCESS)
6129 return I40E_SUCCESS;
6133 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6138 /* Wait until the request is finished */
6139 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6140 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6141 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6142 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6143 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6148 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6149 return I40E_SUCCESS; /* Already on, skip next steps */
6150 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6152 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6153 return I40E_SUCCESS; /* Already off, skip next steps */
6154 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6157 /* Write the register */
6158 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6159 /* Check the result */
6160 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6161 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6162 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6164 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6165 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6168 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6169 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6174 /* Check if it is timeout */
6175 if (j >= I40E_CHK_Q_ENA_COUNT) {
6176 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6177 (on ? "enable" : "disable"), q_idx);
6178 return I40E_ERR_TIMEOUT;
6181 return I40E_SUCCESS;
6183 /* Switch on or off the rx queues */
6185 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6187 struct rte_eth_dev_data *dev_data = pf->dev_data;
6188 struct i40e_rx_queue *rxq;
6189 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6193 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6194 rxq = dev_data->rx_queues[i];
6195 /* Don't operate the queue if not configured or
6196 * if starting only per queue */
6197 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6200 ret = i40e_dev_rx_queue_start(dev, i);
6202 ret = i40e_dev_rx_queue_stop(dev, i);
6203 if (ret != I40E_SUCCESS)
6207 return I40E_SUCCESS;
6210 /* Switch on or off all the rx/tx queues */
6212 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6217 /* enable rx queues before enabling tx queues */
6218 ret = i40e_dev_switch_rx_queues(pf, on);
6220 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6223 ret = i40e_dev_switch_tx_queues(pf, on);
6225 /* Stop tx queues before stopping rx queues */
6226 ret = i40e_dev_switch_tx_queues(pf, on);
6228 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6231 ret = i40e_dev_switch_rx_queues(pf, on);
6237 /* Initialize VSI for TX */
6239 i40e_dev_tx_init(struct i40e_pf *pf)
6241 struct rte_eth_dev_data *data = pf->dev_data;
6243 uint32_t ret = I40E_SUCCESS;
6244 struct i40e_tx_queue *txq;
6246 for (i = 0; i < data->nb_tx_queues; i++) {
6247 txq = data->tx_queues[i];
6248 if (!txq || !txq->q_set)
6250 ret = i40e_tx_queue_init(txq);
6251 if (ret != I40E_SUCCESS)
6254 if (ret == I40E_SUCCESS)
6255 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6261 /* Initialize VSI for RX */
6263 i40e_dev_rx_init(struct i40e_pf *pf)
6265 struct rte_eth_dev_data *data = pf->dev_data;
6266 int ret = I40E_SUCCESS;
6268 struct i40e_rx_queue *rxq;
6270 i40e_pf_config_mq_rx(pf);
6271 for (i = 0; i < data->nb_rx_queues; i++) {
6272 rxq = data->rx_queues[i];
6273 if (!rxq || !rxq->q_set)
6276 ret = i40e_rx_queue_init(rxq);
6277 if (ret != I40E_SUCCESS) {
6279 "Failed to do RX queue initialization");
6283 if (ret == I40E_SUCCESS)
6284 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6291 i40e_dev_rxtx_init(struct i40e_pf *pf)
6295 err = i40e_dev_tx_init(pf);
6297 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6300 err = i40e_dev_rx_init(pf);
6302 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6310 i40e_vmdq_setup(struct rte_eth_dev *dev)
6312 struct rte_eth_conf *conf = &dev->data->dev_conf;
6313 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6314 int i, err, conf_vsis, j, loop;
6315 struct i40e_vsi *vsi;
6316 struct i40e_vmdq_info *vmdq_info;
6317 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6318 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6321 * Disable interrupt to avoid message from VF. Furthermore, it will
6322 * avoid race condition in VSI creation/destroy.
6324 i40e_pf_disable_irq0(hw);
6326 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6327 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6331 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6332 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6333 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6334 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6335 pf->max_nb_vmdq_vsi);
6339 if (pf->vmdq != NULL) {
6340 PMD_INIT_LOG(INFO, "VMDQ already configured");
6344 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6345 sizeof(*vmdq_info) * conf_vsis, 0);
6347 if (pf->vmdq == NULL) {
6348 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6352 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6354 /* Create VMDQ VSI */
6355 for (i = 0; i < conf_vsis; i++) {
6356 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6357 vmdq_conf->enable_loop_back);
6359 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6363 vmdq_info = &pf->vmdq[i];
6365 vmdq_info->vsi = vsi;
6367 pf->nb_cfg_vmdq_vsi = conf_vsis;
6369 /* Configure Vlan */
6370 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6371 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6372 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6373 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6374 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6375 vmdq_conf->pool_map[i].vlan_id, j);
6377 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6378 vmdq_conf->pool_map[i].vlan_id);
6380 PMD_INIT_LOG(ERR, "Failed to add vlan");
6388 i40e_pf_enable_irq0(hw);
6393 for (i = 0; i < conf_vsis; i++)
6394 if (pf->vmdq[i].vsi == NULL)
6397 i40e_vsi_release(pf->vmdq[i].vsi);
6401 i40e_pf_enable_irq0(hw);
6406 i40e_stat_update_32(struct i40e_hw *hw,
6414 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6418 if (new_data >= *offset)
6419 *stat = (uint64_t)(new_data - *offset);
6421 *stat = (uint64_t)((new_data +
6422 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6426 i40e_stat_update_48(struct i40e_hw *hw,
6435 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6436 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6437 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6442 if (new_data >= *offset)
6443 *stat = new_data - *offset;
6445 *stat = (uint64_t)((new_data +
6446 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6448 *stat &= I40E_48_BIT_MASK;
6453 i40e_pf_disable_irq0(struct i40e_hw *hw)
6455 /* Disable all interrupt types */
6456 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6457 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6458 I40E_WRITE_FLUSH(hw);
6463 i40e_pf_enable_irq0(struct i40e_hw *hw)
6465 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6466 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6467 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6468 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6469 I40E_WRITE_FLUSH(hw);
6473 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6475 /* read pending request and disable first */
6476 i40e_pf_disable_irq0(hw);
6477 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6478 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6479 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6482 /* Link no queues with irq0 */
6483 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6484 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6488 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6494 uint32_t index, offset, val;
6499 * Try to find which VF trigger a reset, use absolute VF id to access
6500 * since the reg is global register.
6502 for (i = 0; i < pf->vf_num; i++) {
6503 abs_vf_id = hw->func_caps.vf_base_id + i;
6504 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6505 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6506 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6507 /* VFR event occurred */
6508 if (val & (0x1 << offset)) {
6511 /* Clear the event first */
6512 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6514 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6516 * Only notify a VF reset event occurred,
6517 * don't trigger another SW reset
6519 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6520 if (ret != I40E_SUCCESS)
6521 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6527 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6532 for (i = 0; i < pf->vf_num; i++)
6533 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6537 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6540 struct i40e_arq_event_info info;
6541 uint16_t pending, opcode;
6544 info.buf_len = I40E_AQ_BUF_SZ;
6545 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6546 if (!info.msg_buf) {
6547 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6553 ret = i40e_clean_arq_element(hw, &info, &pending);
6555 if (ret != I40E_SUCCESS) {
6557 "Failed to read msg from AdminQ, aq_err: %u",
6558 hw->aq.asq_last_status);
6561 opcode = rte_le_to_cpu_16(info.desc.opcode);
6564 case i40e_aqc_opc_send_msg_to_pf:
6565 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6566 i40e_pf_host_handle_vf_msg(dev,
6567 rte_le_to_cpu_16(info.desc.retval),
6568 rte_le_to_cpu_32(info.desc.cookie_high),
6569 rte_le_to_cpu_32(info.desc.cookie_low),
6573 case i40e_aqc_opc_get_link_status:
6574 ret = i40e_dev_link_update(dev, 0);
6576 _rte_eth_dev_callback_process(dev,
6577 RTE_ETH_EVENT_INTR_LSC, NULL);
6580 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6585 rte_free(info.msg_buf);
6589 * Interrupt handler triggered by NIC for handling
6590 * specific interrupt.
6593 * Pointer to interrupt handle.
6595 * The address of parameter (struct rte_eth_dev *) regsitered before.
6601 i40e_dev_interrupt_handler(void *param)
6603 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6607 /* Disable interrupt */
6608 i40e_pf_disable_irq0(hw);
6610 /* read out interrupt causes */
6611 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6613 /* No interrupt event indicated */
6614 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6615 PMD_DRV_LOG(INFO, "No interrupt event");
6618 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6619 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6620 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6621 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6622 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6623 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6624 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6625 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6626 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6627 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6628 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6629 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6630 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6631 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6633 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6634 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6635 i40e_dev_handle_vfr_event(dev);
6637 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6638 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6639 i40e_dev_handle_aq_msg(dev);
6643 /* Enable interrupt */
6644 i40e_pf_enable_irq0(hw);
6648 i40e_dev_alarm_handler(void *param)
6650 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6654 /* Disable interrupt */
6655 i40e_pf_disable_irq0(hw);
6657 /* read out interrupt causes */
6658 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6660 /* No interrupt event indicated */
6661 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6663 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6664 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6665 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6666 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6667 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6668 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6669 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6670 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6671 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6672 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6673 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6674 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6675 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6676 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6678 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6679 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6680 i40e_dev_handle_vfr_event(dev);
6682 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6683 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6684 i40e_dev_handle_aq_msg(dev);
6688 /* Enable interrupt */
6689 i40e_pf_enable_irq0(hw);
6690 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6691 i40e_dev_alarm_handler, dev);
6695 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6696 struct i40e_macvlan_filter *filter,
6699 int ele_num, ele_buff_size;
6700 int num, actual_num, i;
6702 int ret = I40E_SUCCESS;
6703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6704 struct i40e_aqc_add_macvlan_element_data *req_list;
6706 if (filter == NULL || total == 0)
6707 return I40E_ERR_PARAM;
6708 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6709 ele_buff_size = hw->aq.asq_buf_size;
6711 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6712 if (req_list == NULL) {
6713 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6714 return I40E_ERR_NO_MEMORY;
6719 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6720 memset(req_list, 0, ele_buff_size);
6722 for (i = 0; i < actual_num; i++) {
6723 rte_memcpy(req_list[i].mac_addr,
6724 &filter[num + i].macaddr, ETH_ADDR_LEN);
6725 req_list[i].vlan_tag =
6726 rte_cpu_to_le_16(filter[num + i].vlan_id);
6728 switch (filter[num + i].filter_type) {
6729 case RTE_MAC_PERFECT_MATCH:
6730 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6731 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6733 case RTE_MACVLAN_PERFECT_MATCH:
6734 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6736 case RTE_MAC_HASH_MATCH:
6737 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6738 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6740 case RTE_MACVLAN_HASH_MATCH:
6741 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6744 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6745 ret = I40E_ERR_PARAM;
6749 req_list[i].queue_number = 0;
6751 req_list[i].flags = rte_cpu_to_le_16(flags);
6754 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6756 if (ret != I40E_SUCCESS) {
6757 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6761 } while (num < total);
6769 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6770 struct i40e_macvlan_filter *filter,
6773 int ele_num, ele_buff_size;
6774 int num, actual_num, i;
6776 int ret = I40E_SUCCESS;
6777 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6778 struct i40e_aqc_remove_macvlan_element_data *req_list;
6780 if (filter == NULL || total == 0)
6781 return I40E_ERR_PARAM;
6783 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6784 ele_buff_size = hw->aq.asq_buf_size;
6786 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6787 if (req_list == NULL) {
6788 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6789 return I40E_ERR_NO_MEMORY;
6794 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6795 memset(req_list, 0, ele_buff_size);
6797 for (i = 0; i < actual_num; i++) {
6798 rte_memcpy(req_list[i].mac_addr,
6799 &filter[num + i].macaddr, ETH_ADDR_LEN);
6800 req_list[i].vlan_tag =
6801 rte_cpu_to_le_16(filter[num + i].vlan_id);
6803 switch (filter[num + i].filter_type) {
6804 case RTE_MAC_PERFECT_MATCH:
6805 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6806 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6808 case RTE_MACVLAN_PERFECT_MATCH:
6809 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6811 case RTE_MAC_HASH_MATCH:
6812 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6813 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6815 case RTE_MACVLAN_HASH_MATCH:
6816 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6819 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6820 ret = I40E_ERR_PARAM;
6823 req_list[i].flags = rte_cpu_to_le_16(flags);
6826 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6828 if (ret != I40E_SUCCESS) {
6829 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6833 } while (num < total);
6840 /* Find out specific MAC filter */
6841 static struct i40e_mac_filter *
6842 i40e_find_mac_filter(struct i40e_vsi *vsi,
6843 struct ether_addr *macaddr)
6845 struct i40e_mac_filter *f;
6847 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6848 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6856 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6859 uint32_t vid_idx, vid_bit;
6861 if (vlan_id > ETH_VLAN_ID_MAX)
6864 vid_idx = I40E_VFTA_IDX(vlan_id);
6865 vid_bit = I40E_VFTA_BIT(vlan_id);
6867 if (vsi->vfta[vid_idx] & vid_bit)
6874 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6875 uint16_t vlan_id, bool on)
6877 uint32_t vid_idx, vid_bit;
6879 vid_idx = I40E_VFTA_IDX(vlan_id);
6880 vid_bit = I40E_VFTA_BIT(vlan_id);
6883 vsi->vfta[vid_idx] |= vid_bit;
6885 vsi->vfta[vid_idx] &= ~vid_bit;
6889 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6890 uint16_t vlan_id, bool on)
6892 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6893 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6896 if (vlan_id > ETH_VLAN_ID_MAX)
6899 i40e_store_vlan_filter(vsi, vlan_id, on);
6901 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6904 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6907 ret = i40e_aq_add_vlan(hw, vsi->seid,
6908 &vlan_data, 1, NULL);
6909 if (ret != I40E_SUCCESS)
6910 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6912 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6913 &vlan_data, 1, NULL);
6914 if (ret != I40E_SUCCESS)
6916 "Failed to remove vlan filter");
6921 * Find all vlan options for specific mac addr,
6922 * return with actual vlan found.
6925 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6926 struct i40e_macvlan_filter *mv_f,
6927 int num, struct ether_addr *addr)
6933 * Not to use i40e_find_vlan_filter to decrease the loop time,
6934 * although the code looks complex.
6936 if (num < vsi->vlan_num)
6937 return I40E_ERR_PARAM;
6940 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6942 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6943 if (vsi->vfta[j] & (1 << k)) {
6946 "vlan number doesn't match");
6947 return I40E_ERR_PARAM;
6949 rte_memcpy(&mv_f[i].macaddr,
6950 addr, ETH_ADDR_LEN);
6952 j * I40E_UINT32_BIT_SIZE + k;
6958 return I40E_SUCCESS;
6962 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6963 struct i40e_macvlan_filter *mv_f,
6968 struct i40e_mac_filter *f;
6970 if (num < vsi->mac_num)
6971 return I40E_ERR_PARAM;
6973 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6975 PMD_DRV_LOG(ERR, "buffer number not match");
6976 return I40E_ERR_PARAM;
6978 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6980 mv_f[i].vlan_id = vlan;
6981 mv_f[i].filter_type = f->mac_info.filter_type;
6985 return I40E_SUCCESS;
6989 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6992 struct i40e_mac_filter *f;
6993 struct i40e_macvlan_filter *mv_f;
6994 int ret = I40E_SUCCESS;
6996 if (vsi == NULL || vsi->mac_num == 0)
6997 return I40E_ERR_PARAM;
6999 /* Case that no vlan is set */
7000 if (vsi->vlan_num == 0)
7003 num = vsi->mac_num * vsi->vlan_num;
7005 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7007 PMD_DRV_LOG(ERR, "failed to allocate memory");
7008 return I40E_ERR_NO_MEMORY;
7012 if (vsi->vlan_num == 0) {
7013 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7014 rte_memcpy(&mv_f[i].macaddr,
7015 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7016 mv_f[i].filter_type = f->mac_info.filter_type;
7017 mv_f[i].vlan_id = 0;
7021 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7022 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7023 vsi->vlan_num, &f->mac_info.mac_addr);
7024 if (ret != I40E_SUCCESS)
7026 for (j = i; j < i + vsi->vlan_num; j++)
7027 mv_f[j].filter_type = f->mac_info.filter_type;
7032 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7040 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7042 struct i40e_macvlan_filter *mv_f;
7044 int ret = I40E_SUCCESS;
7046 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7047 return I40E_ERR_PARAM;
7049 /* If it's already set, just return */
7050 if (i40e_find_vlan_filter(vsi,vlan))
7051 return I40E_SUCCESS;
7053 mac_num = vsi->mac_num;
7056 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7057 return I40E_ERR_PARAM;
7060 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7063 PMD_DRV_LOG(ERR, "failed to allocate memory");
7064 return I40E_ERR_NO_MEMORY;
7067 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7069 if (ret != I40E_SUCCESS)
7072 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7074 if (ret != I40E_SUCCESS)
7077 i40e_set_vlan_filter(vsi, vlan, 1);
7087 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7089 struct i40e_macvlan_filter *mv_f;
7091 int ret = I40E_SUCCESS;
7094 * Vlan 0 is the generic filter for untagged packets
7095 * and can't be removed.
7097 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7098 return I40E_ERR_PARAM;
7100 /* If can't find it, just return */
7101 if (!i40e_find_vlan_filter(vsi, vlan))
7102 return I40E_ERR_PARAM;
7104 mac_num = vsi->mac_num;
7107 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7108 return I40E_ERR_PARAM;
7111 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7114 PMD_DRV_LOG(ERR, "failed to allocate memory");
7115 return I40E_ERR_NO_MEMORY;
7118 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7120 if (ret != I40E_SUCCESS)
7123 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7125 if (ret != I40E_SUCCESS)
7128 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7129 if (vsi->vlan_num == 1) {
7130 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7131 if (ret != I40E_SUCCESS)
7134 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7135 if (ret != I40E_SUCCESS)
7139 i40e_set_vlan_filter(vsi, vlan, 0);
7149 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7151 struct i40e_mac_filter *f;
7152 struct i40e_macvlan_filter *mv_f;
7153 int i, vlan_num = 0;
7154 int ret = I40E_SUCCESS;
7156 /* If it's add and we've config it, return */
7157 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7159 return I40E_SUCCESS;
7160 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7161 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7164 * If vlan_num is 0, that's the first time to add mac,
7165 * set mask for vlan_id 0.
7167 if (vsi->vlan_num == 0) {
7168 i40e_set_vlan_filter(vsi, 0, 1);
7171 vlan_num = vsi->vlan_num;
7172 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7173 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7176 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7178 PMD_DRV_LOG(ERR, "failed to allocate memory");
7179 return I40E_ERR_NO_MEMORY;
7182 for (i = 0; i < vlan_num; i++) {
7183 mv_f[i].filter_type = mac_filter->filter_type;
7184 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7188 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7189 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7190 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7191 &mac_filter->mac_addr);
7192 if (ret != I40E_SUCCESS)
7196 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7197 if (ret != I40E_SUCCESS)
7200 /* Add the mac addr into mac list */
7201 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7203 PMD_DRV_LOG(ERR, "failed to allocate memory");
7204 ret = I40E_ERR_NO_MEMORY;
7207 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7209 f->mac_info.filter_type = mac_filter->filter_type;
7210 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7221 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7223 struct i40e_mac_filter *f;
7224 struct i40e_macvlan_filter *mv_f;
7226 enum rte_mac_filter_type filter_type;
7227 int ret = I40E_SUCCESS;
7229 /* Can't find it, return an error */
7230 f = i40e_find_mac_filter(vsi, addr);
7232 return I40E_ERR_PARAM;
7234 vlan_num = vsi->vlan_num;
7235 filter_type = f->mac_info.filter_type;
7236 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7237 filter_type == RTE_MACVLAN_HASH_MATCH) {
7238 if (vlan_num == 0) {
7239 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7240 return I40E_ERR_PARAM;
7242 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7243 filter_type == RTE_MAC_HASH_MATCH)
7246 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7248 PMD_DRV_LOG(ERR, "failed to allocate memory");
7249 return I40E_ERR_NO_MEMORY;
7252 for (i = 0; i < vlan_num; i++) {
7253 mv_f[i].filter_type = filter_type;
7254 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7257 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7258 filter_type == RTE_MACVLAN_HASH_MATCH) {
7259 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7260 if (ret != I40E_SUCCESS)
7264 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7265 if (ret != I40E_SUCCESS)
7268 /* Remove the mac addr into mac list */
7269 TAILQ_REMOVE(&vsi->mac_list, f, next);
7279 /* Configure hash enable flags for RSS */
7281 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7289 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7290 if (flags & (1ULL << i))
7291 hena |= adapter->pctypes_tbl[i];
7297 /* Parse the hash enable flags */
7299 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7301 uint64_t rss_hf = 0;
7307 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7308 if (flags & adapter->pctypes_tbl[i])
7309 rss_hf |= (1ULL << i);
7316 i40e_pf_disable_rss(struct i40e_pf *pf)
7318 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7320 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7321 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7322 I40E_WRITE_FLUSH(hw);
7326 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7328 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7329 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7330 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7331 I40E_VFQF_HKEY_MAX_INDEX :
7332 I40E_PFQF_HKEY_MAX_INDEX;
7335 if (!key || key_len == 0) {
7336 PMD_DRV_LOG(DEBUG, "No key to be configured");
7338 } else if (key_len != (key_idx + 1) *
7340 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7344 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7345 struct i40e_aqc_get_set_rss_key_data *key_dw =
7346 (struct i40e_aqc_get_set_rss_key_data *)key;
7348 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7350 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7352 uint32_t *hash_key = (uint32_t *)key;
7355 if (vsi->type == I40E_VSI_SRIOV) {
7356 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7359 I40E_VFQF_HKEY1(i, vsi->user_param),
7363 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7364 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7367 I40E_WRITE_FLUSH(hw);
7374 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7376 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7377 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7381 if (!key || !key_len)
7384 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7385 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7386 (struct i40e_aqc_get_set_rss_key_data *)key);
7388 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7392 uint32_t *key_dw = (uint32_t *)key;
7395 if (vsi->type == I40E_VSI_SRIOV) {
7396 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7397 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7398 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7400 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7403 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7404 reg = I40E_PFQF_HKEY(i);
7405 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7407 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7415 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7417 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7421 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7422 rss_conf->rss_key_len);
7426 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7427 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7428 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7429 I40E_WRITE_FLUSH(hw);
7435 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7436 struct rte_eth_rss_conf *rss_conf)
7438 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7439 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7443 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7444 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7446 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7447 if (rss_hf != 0) /* Enable RSS */
7449 return 0; /* Nothing to do */
7452 if (rss_hf == 0) /* Disable RSS */
7455 return i40e_hw_rss_hash_set(pf, rss_conf);
7459 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7460 struct rte_eth_rss_conf *rss_conf)
7462 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7463 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7466 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7467 &rss_conf->rss_key_len);
7469 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7470 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7471 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7477 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7479 switch (filter_type) {
7480 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7481 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7483 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7484 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7486 case RTE_TUNNEL_FILTER_IMAC_TENID:
7487 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7489 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7490 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7492 case ETH_TUNNEL_FILTER_IMAC:
7493 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7495 case ETH_TUNNEL_FILTER_OIP:
7496 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7498 case ETH_TUNNEL_FILTER_IIP:
7499 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7502 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7509 /* Convert tunnel filter structure */
7511 i40e_tunnel_filter_convert(
7512 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7513 struct i40e_tunnel_filter *tunnel_filter)
7515 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7516 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7517 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7518 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7519 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7520 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7521 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7522 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7523 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7525 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7526 tunnel_filter->input.flags = cld_filter->element.flags;
7527 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7528 tunnel_filter->queue = cld_filter->element.queue_number;
7529 rte_memcpy(tunnel_filter->input.general_fields,
7530 cld_filter->general_fields,
7531 sizeof(cld_filter->general_fields));
7536 /* Check if there exists the tunnel filter */
7537 struct i40e_tunnel_filter *
7538 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7539 const struct i40e_tunnel_filter_input *input)
7543 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7547 return tunnel_rule->hash_map[ret];
7550 /* Add a tunnel filter into the SW list */
7552 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7553 struct i40e_tunnel_filter *tunnel_filter)
7555 struct i40e_tunnel_rule *rule = &pf->tunnel;
7558 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7561 "Failed to insert tunnel filter to hash table %d!",
7565 rule->hash_map[ret] = tunnel_filter;
7567 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7572 /* Delete a tunnel filter from the SW list */
7574 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7575 struct i40e_tunnel_filter_input *input)
7577 struct i40e_tunnel_rule *rule = &pf->tunnel;
7578 struct i40e_tunnel_filter *tunnel_filter;
7581 ret = rte_hash_del_key(rule->hash_table, input);
7584 "Failed to delete tunnel filter to hash table %d!",
7588 tunnel_filter = rule->hash_map[ret];
7589 rule->hash_map[ret] = NULL;
7591 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7592 rte_free(tunnel_filter);
7598 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7599 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7603 uint32_t ipv4_addr, ipv4_addr_le;
7604 uint8_t i, tun_type = 0;
7605 /* internal varialbe to convert ipv6 byte order */
7606 uint32_t convert_ipv6[4];
7608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7609 struct i40e_vsi *vsi = pf->main_vsi;
7610 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7611 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7612 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7613 struct i40e_tunnel_filter *tunnel, *node;
7614 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7616 cld_filter = rte_zmalloc("tunnel_filter",
7617 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7620 if (NULL == cld_filter) {
7621 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7624 pfilter = cld_filter;
7626 ether_addr_copy(&tunnel_filter->outer_mac,
7627 (struct ether_addr *)&pfilter->element.outer_mac);
7628 ether_addr_copy(&tunnel_filter->inner_mac,
7629 (struct ether_addr *)&pfilter->element.inner_mac);
7631 pfilter->element.inner_vlan =
7632 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7633 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7634 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7635 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7636 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7637 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7639 sizeof(pfilter->element.ipaddr.v4.data));
7641 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7642 for (i = 0; i < 4; i++) {
7644 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7646 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7648 sizeof(pfilter->element.ipaddr.v6.data));
7651 /* check tunneled type */
7652 switch (tunnel_filter->tunnel_type) {
7653 case RTE_TUNNEL_TYPE_VXLAN:
7654 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7656 case RTE_TUNNEL_TYPE_NVGRE:
7657 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7659 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7660 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7663 /* Other tunnel types is not supported. */
7664 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7665 rte_free(cld_filter);
7669 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7670 &pfilter->element.flags);
7672 rte_free(cld_filter);
7676 pfilter->element.flags |= rte_cpu_to_le_16(
7677 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7678 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7679 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7680 pfilter->element.queue_number =
7681 rte_cpu_to_le_16(tunnel_filter->queue_id);
7683 /* Check if there is the filter in SW list */
7684 memset(&check_filter, 0, sizeof(check_filter));
7685 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7686 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7688 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7689 rte_free(cld_filter);
7693 if (!add && !node) {
7694 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7695 rte_free(cld_filter);
7700 ret = i40e_aq_add_cloud_filters(hw,
7701 vsi->seid, &cld_filter->element, 1);
7703 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7704 rte_free(cld_filter);
7707 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7708 if (tunnel == NULL) {
7709 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7710 rte_free(cld_filter);
7714 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7715 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7719 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7720 &cld_filter->element, 1);
7722 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7723 rte_free(cld_filter);
7726 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7729 rte_free(cld_filter);
7733 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7734 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7735 #define I40E_TR_GENEVE_KEY_MASK 0x8
7736 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7737 #define I40E_TR_GRE_KEY_MASK 0x400
7738 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7739 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7742 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7744 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7745 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7747 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7748 enum i40e_status_code status = I40E_SUCCESS;
7750 if (pf->support_multi_driver) {
7751 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7752 return I40E_NOT_SUPPORTED;
7755 memset(&filter_replace, 0,
7756 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7757 memset(&filter_replace_buf, 0,
7758 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7760 /* create L1 filter */
7761 filter_replace.old_filter_type =
7762 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7763 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7764 filter_replace.tr_bit = 0;
7766 /* Prepare the buffer, 3 entries */
7767 filter_replace_buf.data[0] =
7768 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7769 filter_replace_buf.data[0] |=
7770 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7771 filter_replace_buf.data[2] = 0xFF;
7772 filter_replace_buf.data[3] = 0xFF;
7773 filter_replace_buf.data[4] =
7774 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7775 filter_replace_buf.data[4] |=
7776 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7777 filter_replace_buf.data[7] = 0xF0;
7778 filter_replace_buf.data[8]
7779 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7780 filter_replace_buf.data[8] |=
7781 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7782 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7783 I40E_TR_GENEVE_KEY_MASK |
7784 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7785 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7786 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7787 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7789 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7790 &filter_replace_buf);
7791 if (!status && (filter_replace.old_filter_type !=
7792 filter_replace.new_filter_type))
7793 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7794 " original: 0x%x, new: 0x%x",
7796 filter_replace.old_filter_type,
7797 filter_replace.new_filter_type);
7803 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7805 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7806 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7807 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7808 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7809 enum i40e_status_code status = I40E_SUCCESS;
7811 if (pf->support_multi_driver) {
7812 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7813 return I40E_NOT_SUPPORTED;
7817 memset(&filter_replace, 0,
7818 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7819 memset(&filter_replace_buf, 0,
7820 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7821 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7822 I40E_AQC_MIRROR_CLOUD_FILTER;
7823 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7824 filter_replace.new_filter_type =
7825 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7826 /* Prepare the buffer, 2 entries */
7827 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7828 filter_replace_buf.data[0] |=
7829 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7830 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7831 filter_replace_buf.data[4] |=
7832 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7833 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7834 &filter_replace_buf);
7837 if (filter_replace.old_filter_type !=
7838 filter_replace.new_filter_type)
7839 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7840 " original: 0x%x, new: 0x%x",
7842 filter_replace.old_filter_type,
7843 filter_replace.new_filter_type);
7846 memset(&filter_replace, 0,
7847 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7848 memset(&filter_replace_buf, 0,
7849 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7851 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7852 I40E_AQC_MIRROR_CLOUD_FILTER;
7853 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7854 filter_replace.new_filter_type =
7855 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7856 /* Prepare the buffer, 2 entries */
7857 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7858 filter_replace_buf.data[0] |=
7859 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7860 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7861 filter_replace_buf.data[4] |=
7862 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7864 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7865 &filter_replace_buf);
7866 if (!status && (filter_replace.old_filter_type !=
7867 filter_replace.new_filter_type))
7868 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7869 " original: 0x%x, new: 0x%x",
7871 filter_replace.old_filter_type,
7872 filter_replace.new_filter_type);
7877 static enum i40e_status_code
7878 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7880 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7881 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7882 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7883 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7884 enum i40e_status_code status = I40E_SUCCESS;
7886 if (pf->support_multi_driver) {
7887 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7888 return I40E_NOT_SUPPORTED;
7892 memset(&filter_replace, 0,
7893 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7894 memset(&filter_replace_buf, 0,
7895 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7896 /* create L1 filter */
7897 filter_replace.old_filter_type =
7898 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7899 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7900 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7901 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7902 /* Prepare the buffer, 2 entries */
7903 filter_replace_buf.data[0] =
7904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7905 filter_replace_buf.data[0] |=
7906 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7907 filter_replace_buf.data[2] = 0xFF;
7908 filter_replace_buf.data[3] = 0xFF;
7909 filter_replace_buf.data[4] =
7910 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7911 filter_replace_buf.data[4] |=
7912 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7913 filter_replace_buf.data[6] = 0xFF;
7914 filter_replace_buf.data[7] = 0xFF;
7915 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7916 &filter_replace_buf);
7919 if (filter_replace.old_filter_type !=
7920 filter_replace.new_filter_type)
7921 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7922 " original: 0x%x, new: 0x%x",
7924 filter_replace.old_filter_type,
7925 filter_replace.new_filter_type);
7928 memset(&filter_replace, 0,
7929 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7930 memset(&filter_replace_buf, 0,
7931 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7932 /* create L1 filter */
7933 filter_replace.old_filter_type =
7934 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7935 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7936 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7937 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7938 /* Prepare the buffer, 2 entries */
7939 filter_replace_buf.data[0] =
7940 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7941 filter_replace_buf.data[0] |=
7942 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7943 filter_replace_buf.data[2] = 0xFF;
7944 filter_replace_buf.data[3] = 0xFF;
7945 filter_replace_buf.data[4] =
7946 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7947 filter_replace_buf.data[4] |=
7948 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7949 filter_replace_buf.data[6] = 0xFF;
7950 filter_replace_buf.data[7] = 0xFF;
7952 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7953 &filter_replace_buf);
7954 if (!status && (filter_replace.old_filter_type !=
7955 filter_replace.new_filter_type))
7956 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7957 " original: 0x%x, new: 0x%x",
7959 filter_replace.old_filter_type,
7960 filter_replace.new_filter_type);
7966 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7968 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7969 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7970 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7971 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7972 enum i40e_status_code status = I40E_SUCCESS;
7974 if (pf->support_multi_driver) {
7975 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7976 return I40E_NOT_SUPPORTED;
7980 memset(&filter_replace, 0,
7981 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7982 memset(&filter_replace_buf, 0,
7983 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7984 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7985 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7986 filter_replace.new_filter_type =
7987 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7988 /* Prepare the buffer, 2 entries */
7989 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7990 filter_replace_buf.data[0] |=
7991 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7992 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7993 filter_replace_buf.data[4] |=
7994 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7995 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7996 &filter_replace_buf);
7999 if (filter_replace.old_filter_type !=
8000 filter_replace.new_filter_type)
8001 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8002 " original: 0x%x, new: 0x%x",
8004 filter_replace.old_filter_type,
8005 filter_replace.new_filter_type);
8008 memset(&filter_replace, 0,
8009 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8010 memset(&filter_replace_buf, 0,
8011 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8012 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8013 filter_replace.old_filter_type =
8014 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8015 filter_replace.new_filter_type =
8016 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8017 /* Prepare the buffer, 2 entries */
8018 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8019 filter_replace_buf.data[0] |=
8020 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8021 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8022 filter_replace_buf.data[4] |=
8023 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8025 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8026 &filter_replace_buf);
8027 if (!status && (filter_replace.old_filter_type !=
8028 filter_replace.new_filter_type))
8029 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8030 " original: 0x%x, new: 0x%x",
8032 filter_replace.old_filter_type,
8033 filter_replace.new_filter_type);
8039 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8040 struct i40e_tunnel_filter_conf *tunnel_filter,
8044 uint32_t ipv4_addr, ipv4_addr_le;
8045 uint8_t i, tun_type = 0;
8046 /* internal variable to convert ipv6 byte order */
8047 uint32_t convert_ipv6[4];
8049 struct i40e_pf_vf *vf = NULL;
8050 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8051 struct i40e_vsi *vsi;
8052 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8053 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8054 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8055 struct i40e_tunnel_filter *tunnel, *node;
8056 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8058 bool big_buffer = 0;
8060 cld_filter = rte_zmalloc("tunnel_filter",
8061 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8064 if (cld_filter == NULL) {
8065 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8068 pfilter = cld_filter;
8070 ether_addr_copy(&tunnel_filter->outer_mac,
8071 (struct ether_addr *)&pfilter->element.outer_mac);
8072 ether_addr_copy(&tunnel_filter->inner_mac,
8073 (struct ether_addr *)&pfilter->element.inner_mac);
8075 pfilter->element.inner_vlan =
8076 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8077 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8078 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8079 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8080 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8081 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8083 sizeof(pfilter->element.ipaddr.v4.data));
8085 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8086 for (i = 0; i < 4; i++) {
8088 rte_cpu_to_le_32(rte_be_to_cpu_32(
8089 tunnel_filter->ip_addr.ipv6_addr[i]));
8091 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8093 sizeof(pfilter->element.ipaddr.v6.data));
8096 /* check tunneled type */
8097 switch (tunnel_filter->tunnel_type) {
8098 case I40E_TUNNEL_TYPE_VXLAN:
8099 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8101 case I40E_TUNNEL_TYPE_NVGRE:
8102 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8104 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8105 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8107 case I40E_TUNNEL_TYPE_MPLSoUDP:
8108 if (!pf->mpls_replace_flag) {
8109 i40e_replace_mpls_l1_filter(pf);
8110 i40e_replace_mpls_cloud_filter(pf);
8111 pf->mpls_replace_flag = 1;
8113 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8114 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8116 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8117 (teid_le & 0xF) << 12;
8118 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8121 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8123 case I40E_TUNNEL_TYPE_MPLSoGRE:
8124 if (!pf->mpls_replace_flag) {
8125 i40e_replace_mpls_l1_filter(pf);
8126 i40e_replace_mpls_cloud_filter(pf);
8127 pf->mpls_replace_flag = 1;
8129 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8130 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8132 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8133 (teid_le & 0xF) << 12;
8134 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8137 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8139 case I40E_TUNNEL_TYPE_GTPC:
8140 if (!pf->gtp_replace_flag) {
8141 i40e_replace_gtp_l1_filter(pf);
8142 i40e_replace_gtp_cloud_filter(pf);
8143 pf->gtp_replace_flag = 1;
8145 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8146 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8147 (teid_le >> 16) & 0xFFFF;
8148 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8154 case I40E_TUNNEL_TYPE_GTPU:
8155 if (!pf->gtp_replace_flag) {
8156 i40e_replace_gtp_l1_filter(pf);
8157 i40e_replace_gtp_cloud_filter(pf);
8158 pf->gtp_replace_flag = 1;
8160 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8161 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8162 (teid_le >> 16) & 0xFFFF;
8163 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8165 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8169 case I40E_TUNNEL_TYPE_QINQ:
8170 if (!pf->qinq_replace_flag) {
8171 ret = i40e_cloud_filter_qinq_create(pf);
8174 "QinQ tunnel filter already created.");
8175 pf->qinq_replace_flag = 1;
8177 /* Add in the General fields the values of
8178 * the Outer and Inner VLAN
8179 * Big Buffer should be set, see changes in
8180 * i40e_aq_add_cloud_filters
8182 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8183 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8187 /* Other tunnel types is not supported. */
8188 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8189 rte_free(cld_filter);
8193 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8194 pfilter->element.flags =
8195 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8196 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8197 pfilter->element.flags =
8198 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8199 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8200 pfilter->element.flags =
8201 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8202 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8203 pfilter->element.flags =
8204 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8205 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8206 pfilter->element.flags |=
8207 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8209 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8210 &pfilter->element.flags);
8212 rte_free(cld_filter);
8217 pfilter->element.flags |= rte_cpu_to_le_16(
8218 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8219 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8220 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8221 pfilter->element.queue_number =
8222 rte_cpu_to_le_16(tunnel_filter->queue_id);
8224 if (!tunnel_filter->is_to_vf)
8227 if (tunnel_filter->vf_id >= pf->vf_num) {
8228 PMD_DRV_LOG(ERR, "Invalid argument.");
8229 rte_free(cld_filter);
8232 vf = &pf->vfs[tunnel_filter->vf_id];
8236 /* Check if there is the filter in SW list */
8237 memset(&check_filter, 0, sizeof(check_filter));
8238 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8239 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8240 check_filter.vf_id = tunnel_filter->vf_id;
8241 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8243 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8244 rte_free(cld_filter);
8248 if (!add && !node) {
8249 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8250 rte_free(cld_filter);
8256 ret = i40e_aq_add_cloud_filters_bb(hw,
8257 vsi->seid, cld_filter, 1);
8259 ret = i40e_aq_add_cloud_filters(hw,
8260 vsi->seid, &cld_filter->element, 1);
8262 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8263 rte_free(cld_filter);
8266 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8267 if (tunnel == NULL) {
8268 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8269 rte_free(cld_filter);
8273 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8274 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8279 ret = i40e_aq_rem_cloud_filters_bb(
8280 hw, vsi->seid, cld_filter, 1);
8282 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8283 &cld_filter->element, 1);
8285 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8286 rte_free(cld_filter);
8289 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8292 rte_free(cld_filter);
8297 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8301 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8302 if (pf->vxlan_ports[i] == port)
8310 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8314 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8316 idx = i40e_get_vxlan_port_idx(pf, port);
8318 /* Check if port already exists */
8320 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8324 /* Now check if there is space to add the new port */
8325 idx = i40e_get_vxlan_port_idx(pf, 0);
8328 "Maximum number of UDP ports reached, not adding port %d",
8333 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8336 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8340 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8343 /* New port: add it and mark its index in the bitmap */
8344 pf->vxlan_ports[idx] = port;
8345 pf->vxlan_bitmap |= (1 << idx);
8347 if (!(pf->flags & I40E_FLAG_VXLAN))
8348 pf->flags |= I40E_FLAG_VXLAN;
8354 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8357 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8359 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8360 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8364 idx = i40e_get_vxlan_port_idx(pf, port);
8367 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8371 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8372 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8376 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8379 pf->vxlan_ports[idx] = 0;
8380 pf->vxlan_bitmap &= ~(1 << idx);
8382 if (!pf->vxlan_bitmap)
8383 pf->flags &= ~I40E_FLAG_VXLAN;
8388 /* Add UDP tunneling port */
8390 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8391 struct rte_eth_udp_tunnel *udp_tunnel)
8394 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8396 if (udp_tunnel == NULL)
8399 switch (udp_tunnel->prot_type) {
8400 case RTE_TUNNEL_TYPE_VXLAN:
8401 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8404 case RTE_TUNNEL_TYPE_GENEVE:
8405 case RTE_TUNNEL_TYPE_TEREDO:
8406 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8411 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8419 /* Remove UDP tunneling port */
8421 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8422 struct rte_eth_udp_tunnel *udp_tunnel)
8425 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8427 if (udp_tunnel == NULL)
8430 switch (udp_tunnel->prot_type) {
8431 case RTE_TUNNEL_TYPE_VXLAN:
8432 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8434 case RTE_TUNNEL_TYPE_GENEVE:
8435 case RTE_TUNNEL_TYPE_TEREDO:
8436 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8440 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8448 /* Calculate the maximum number of contiguous PF queues that are configured */
8450 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8452 struct rte_eth_dev_data *data = pf->dev_data;
8454 struct i40e_rx_queue *rxq;
8457 for (i = 0; i < pf->lan_nb_qps; i++) {
8458 rxq = data->rx_queues[i];
8459 if (rxq && rxq->q_set)
8470 i40e_pf_config_rss(struct i40e_pf *pf)
8472 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8473 struct rte_eth_rss_conf rss_conf;
8474 uint32_t i, lut = 0;
8478 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8479 * It's necessary to calculate the actual PF queues that are configured.
8481 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8482 num = i40e_pf_calc_configured_queues_num(pf);
8484 num = pf->dev_data->nb_rx_queues;
8486 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8487 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8491 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8495 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8498 lut = (lut << 8) | (j & ((0x1 <<
8499 hw->func_caps.rss_table_entry_width) - 1));
8501 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8504 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8505 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8506 i40e_pf_disable_rss(pf);
8509 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8510 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8511 /* Random default keys */
8512 static uint32_t rss_key_default[] = {0x6b793944,
8513 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8514 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8515 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8517 rss_conf.rss_key = (uint8_t *)rss_key_default;
8518 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8522 return i40e_hw_rss_hash_set(pf, &rss_conf);
8526 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8527 struct rte_eth_tunnel_filter_conf *filter)
8529 if (pf == NULL || filter == NULL) {
8530 PMD_DRV_LOG(ERR, "Invalid parameter");
8534 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8535 PMD_DRV_LOG(ERR, "Invalid queue ID");
8539 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8540 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8544 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8545 (is_zero_ether_addr(&filter->outer_mac))) {
8546 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8550 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8551 (is_zero_ether_addr(&filter->inner_mac))) {
8552 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8559 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8560 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8562 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8564 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8568 if (pf->support_multi_driver) {
8569 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8573 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8574 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8577 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8578 } else if (len == 4) {
8579 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8581 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8586 ret = i40e_aq_debug_write_global_register(hw,
8587 I40E_GL_PRS_FVBM(2),
8591 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8592 "with value 0x%08x",
8593 I40E_GL_PRS_FVBM(2), reg);
8597 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8598 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8604 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8611 switch (cfg->cfg_type) {
8612 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8613 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8616 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8624 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8625 enum rte_filter_op filter_op,
8628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8629 int ret = I40E_ERR_PARAM;
8631 switch (filter_op) {
8632 case RTE_ETH_FILTER_SET:
8633 ret = i40e_dev_global_config_set(hw,
8634 (struct rte_eth_global_cfg *)arg);
8637 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8645 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8646 enum rte_filter_op filter_op,
8649 struct rte_eth_tunnel_filter_conf *filter;
8650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8651 int ret = I40E_SUCCESS;
8653 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8655 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8656 return I40E_ERR_PARAM;
8658 switch (filter_op) {
8659 case RTE_ETH_FILTER_NOP:
8660 if (!(pf->flags & I40E_FLAG_VXLAN))
8661 ret = I40E_NOT_SUPPORTED;
8663 case RTE_ETH_FILTER_ADD:
8664 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8666 case RTE_ETH_FILTER_DELETE:
8667 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8670 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8671 ret = I40E_ERR_PARAM;
8679 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8682 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8685 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8686 ret = i40e_pf_config_rss(pf);
8688 i40e_pf_disable_rss(pf);
8693 /* Get the symmetric hash enable configurations per port */
8695 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8697 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8699 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8702 /* Set the symmetric hash enable configurations per port */
8704 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8706 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8709 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8711 "Symmetric hash has already been enabled");
8714 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8716 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8718 "Symmetric hash has already been disabled");
8721 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8723 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8724 I40E_WRITE_FLUSH(hw);
8728 * Get global configurations of hash function type and symmetric hash enable
8729 * per flow type (pctype). Note that global configuration means it affects all
8730 * the ports on the same NIC.
8733 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8734 struct rte_eth_hash_global_conf *g_cfg)
8736 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8740 memset(g_cfg, 0, sizeof(*g_cfg));
8741 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8742 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8743 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8745 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8746 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8747 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8750 * As i40e supports less than 64 flow types, only first 64 bits need to
8753 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8754 g_cfg->valid_bit_mask[i] = 0ULL;
8755 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8758 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8760 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8761 if (!adapter->pctypes_tbl[i])
8763 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8764 j < I40E_FILTER_PCTYPE_MAX; j++) {
8765 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8766 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8767 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8768 g_cfg->sym_hash_enable_mask[0] |=
8779 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8780 const struct rte_eth_hash_global_conf *g_cfg)
8783 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8785 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8786 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8787 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8788 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8794 * As i40e supports less than 64 flow types, only first 64 bits need to
8797 mask0 = g_cfg->valid_bit_mask[0];
8798 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8800 /* Check if any unsupported flow type configured */
8801 if ((mask0 | i40e_mask) ^ i40e_mask)
8804 if (g_cfg->valid_bit_mask[i])
8812 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8818 * Set global configurations of hash function type and symmetric hash enable
8819 * per flow type (pctype). Note any modifying global configuration will affect
8820 * all the ports on the same NIC.
8823 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8824 struct rte_eth_hash_global_conf *g_cfg)
8826 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8827 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8831 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8833 if (pf->support_multi_driver) {
8834 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8838 /* Check the input parameters */
8839 ret = i40e_hash_global_config_check(adapter, g_cfg);
8844 * As i40e supports less than 64 flow types, only first 64 bits need to
8847 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8848 if (mask0 & (1UL << i)) {
8849 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8850 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8852 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8853 j < I40E_FILTER_PCTYPE_MAX; j++) {
8854 if (adapter->pctypes_tbl[i] & (1ULL << j))
8855 i40e_write_global_rx_ctl(hw,
8862 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8863 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8865 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8867 "Hash function already set to Toeplitz");
8870 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8871 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8873 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8875 "Hash function already set to Simple XOR");
8878 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8880 /* Use the default, and keep it as it is */
8883 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8886 I40E_WRITE_FLUSH(hw);
8892 * Valid input sets for hash and flow director filters per PCTYPE
8895 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8896 enum rte_filter_type filter)
8900 static const uint64_t valid_hash_inset_table[] = {
8901 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8902 I40E_INSET_DMAC | I40E_INSET_SMAC |
8903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8904 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8905 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8906 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8907 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8908 I40E_INSET_FLEX_PAYLOAD,
8909 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8910 I40E_INSET_DMAC | I40E_INSET_SMAC |
8911 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8912 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8913 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8914 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8915 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8916 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8917 I40E_INSET_FLEX_PAYLOAD,
8918 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8919 I40E_INSET_DMAC | I40E_INSET_SMAC |
8920 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8921 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8922 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8923 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8924 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8925 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8926 I40E_INSET_FLEX_PAYLOAD,
8927 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8928 I40E_INSET_DMAC | I40E_INSET_SMAC |
8929 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8930 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8931 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8932 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8933 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8934 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8935 I40E_INSET_FLEX_PAYLOAD,
8936 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8937 I40E_INSET_DMAC | I40E_INSET_SMAC |
8938 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8939 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8940 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8941 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8942 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8943 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8944 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8945 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8946 I40E_INSET_DMAC | I40E_INSET_SMAC |
8947 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8948 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8949 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8950 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8951 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8952 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8953 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8954 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8955 I40E_INSET_DMAC | I40E_INSET_SMAC |
8956 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8957 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8958 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8959 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8960 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8961 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8962 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8963 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8964 I40E_INSET_DMAC | I40E_INSET_SMAC |
8965 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8966 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8967 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8968 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8969 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8970 I40E_INSET_FLEX_PAYLOAD,
8971 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8972 I40E_INSET_DMAC | I40E_INSET_SMAC |
8973 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8974 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8975 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8976 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8977 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8978 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8979 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8980 I40E_INSET_DMAC | I40E_INSET_SMAC |
8981 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8982 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8983 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8984 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8985 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8986 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8987 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8988 I40E_INSET_DMAC | I40E_INSET_SMAC |
8989 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8990 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8991 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8992 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8993 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8994 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8995 I40E_INSET_FLEX_PAYLOAD,
8996 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8997 I40E_INSET_DMAC | I40E_INSET_SMAC |
8998 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8999 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9000 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9001 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9002 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9003 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9004 I40E_INSET_FLEX_PAYLOAD,
9005 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9006 I40E_INSET_DMAC | I40E_INSET_SMAC |
9007 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9008 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9009 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9010 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9011 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9012 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9013 I40E_INSET_FLEX_PAYLOAD,
9014 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9015 I40E_INSET_DMAC | I40E_INSET_SMAC |
9016 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9017 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9018 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9019 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9020 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9021 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9022 I40E_INSET_FLEX_PAYLOAD,
9023 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9024 I40E_INSET_DMAC | I40E_INSET_SMAC |
9025 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9026 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9027 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9028 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9029 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9030 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9031 I40E_INSET_FLEX_PAYLOAD,
9032 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9033 I40E_INSET_DMAC | I40E_INSET_SMAC |
9034 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9035 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9036 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9037 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9038 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9039 I40E_INSET_FLEX_PAYLOAD,
9040 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9041 I40E_INSET_DMAC | I40E_INSET_SMAC |
9042 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9043 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9044 I40E_INSET_FLEX_PAYLOAD,
9048 * Flow director supports only fields defined in
9049 * union rte_eth_fdir_flow.
9051 static const uint64_t valid_fdir_inset_table[] = {
9052 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9055 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9056 I40E_INSET_IPV4_TTL,
9057 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9058 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9060 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9061 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9062 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9065 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9066 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9067 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9070 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9071 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9072 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9073 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9074 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9075 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9076 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9077 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9078 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9079 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9080 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9081 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9082 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9083 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9084 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9085 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9086 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9088 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9091 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9092 I40E_INSET_IPV4_TTL,
9093 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9094 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9095 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9096 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9097 I40E_INSET_IPV6_HOP_LIMIT,
9098 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9099 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9100 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9101 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9102 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9103 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9106 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9107 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9108 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9110 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9111 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9112 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9113 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9114 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9115 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9116 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9117 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9118 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9120 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9121 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9122 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9123 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9124 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9125 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9126 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9127 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9129 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9132 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9133 I40E_INSET_IPV6_HOP_LIMIT,
9134 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136 I40E_INSET_LAST_ETHER_TYPE,
9139 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9141 if (filter == RTE_ETH_FILTER_HASH)
9142 valid = valid_hash_inset_table[pctype];
9144 valid = valid_fdir_inset_table[pctype];
9150 * Validate if the input set is allowed for a specific PCTYPE
9153 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9154 enum rte_filter_type filter, uint64_t inset)
9158 valid = i40e_get_valid_input_set(pctype, filter);
9159 if (inset & (~valid))
9165 /* default input set fields combination per pctype */
9167 i40e_get_default_input_set(uint16_t pctype)
9169 static const uint64_t default_inset_table[] = {
9170 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9171 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9172 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9175 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9176 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9177 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9178 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9179 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9180 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9181 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9182 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9183 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9184 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9187 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9188 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9189 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9191 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9193 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9194 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9195 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9196 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9199 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9200 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9201 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9202 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9203 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9204 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9205 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9206 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9207 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9208 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9210 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9211 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9212 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9214 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9215 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9216 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9217 I40E_INSET_LAST_ETHER_TYPE,
9220 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9223 return default_inset_table[pctype];
9227 * Parse the input set from index to logical bit masks
9230 i40e_parse_input_set(uint64_t *inset,
9231 enum i40e_filter_pctype pctype,
9232 enum rte_eth_input_set_field *field,
9238 static const struct {
9239 enum rte_eth_input_set_field field;
9241 } inset_convert_table[] = {
9242 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9243 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9244 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9245 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9246 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9247 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9248 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9249 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9250 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9251 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9252 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9253 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9254 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9255 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9256 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9257 I40E_INSET_IPV6_NEXT_HDR},
9258 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9259 I40E_INSET_IPV6_HOP_LIMIT},
9260 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9261 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9262 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9263 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9264 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9265 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9266 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9267 I40E_INSET_SCTP_VT},
9268 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9269 I40E_INSET_TUNNEL_DMAC},
9270 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9271 I40E_INSET_VLAN_TUNNEL},
9272 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9273 I40E_INSET_TUNNEL_ID},
9274 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9275 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9276 I40E_INSET_FLEX_PAYLOAD_W1},
9277 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9278 I40E_INSET_FLEX_PAYLOAD_W2},
9279 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9280 I40E_INSET_FLEX_PAYLOAD_W3},
9281 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9282 I40E_INSET_FLEX_PAYLOAD_W4},
9283 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9284 I40E_INSET_FLEX_PAYLOAD_W5},
9285 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9286 I40E_INSET_FLEX_PAYLOAD_W6},
9287 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9288 I40E_INSET_FLEX_PAYLOAD_W7},
9289 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9290 I40E_INSET_FLEX_PAYLOAD_W8},
9293 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9296 /* Only one item allowed for default or all */
9298 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9299 *inset = i40e_get_default_input_set(pctype);
9301 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9302 *inset = I40E_INSET_NONE;
9307 for (i = 0, *inset = 0; i < size; i++) {
9308 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9309 if (field[i] == inset_convert_table[j].field) {
9310 *inset |= inset_convert_table[j].inset;
9315 /* It contains unsupported input set, return immediately */
9316 if (j == RTE_DIM(inset_convert_table))
9324 * Translate the input set from bit masks to register aware bit masks
9328 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9338 static const struct inset_map inset_map_common[] = {
9339 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9340 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9341 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9342 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9343 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9344 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9345 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9346 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9347 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9348 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9349 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9350 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9351 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9352 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9353 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9354 {I40E_INSET_TUNNEL_DMAC,
9355 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9356 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9357 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9358 {I40E_INSET_TUNNEL_SRC_PORT,
9359 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9360 {I40E_INSET_TUNNEL_DST_PORT,
9361 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9362 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9363 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9364 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9365 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9366 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9367 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9368 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9369 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9370 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9373 /* some different registers map in x722*/
9374 static const struct inset_map inset_map_diff_x722[] = {
9375 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9376 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9377 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9378 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9381 static const struct inset_map inset_map_diff_not_x722[] = {
9382 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9383 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9384 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9385 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9391 /* Translate input set to register aware inset */
9392 if (type == I40E_MAC_X722) {
9393 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9394 if (input & inset_map_diff_x722[i].inset)
9395 val |= inset_map_diff_x722[i].inset_reg;
9398 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9399 if (input & inset_map_diff_not_x722[i].inset)
9400 val |= inset_map_diff_not_x722[i].inset_reg;
9404 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9405 if (input & inset_map_common[i].inset)
9406 val |= inset_map_common[i].inset_reg;
9413 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9416 uint64_t inset_need_mask = inset;
9418 static const struct {
9421 } inset_mask_map[] = {
9422 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9423 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9424 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9425 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9426 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9427 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9428 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9429 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9432 if (!inset || !mask || !nb_elem)
9435 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9436 /* Clear the inset bit, if no MASK is required,
9437 * for example proto + ttl
9439 if ((inset & inset_mask_map[i].inset) ==
9440 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9441 inset_need_mask &= ~inset_mask_map[i].inset;
9442 if (!inset_need_mask)
9445 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9446 if ((inset_need_mask & inset_mask_map[i].inset) ==
9447 inset_mask_map[i].inset) {
9448 if (idx >= nb_elem) {
9449 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9452 mask[idx] = inset_mask_map[i].mask;
9461 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9463 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9465 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9467 i40e_write_rx_ctl(hw, addr, val);
9468 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9469 (uint32_t)i40e_read_rx_ctl(hw, addr));
9473 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9475 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9476 struct rte_eth_dev *dev;
9478 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9480 i40e_write_rx_ctl(hw, addr, val);
9481 PMD_DRV_LOG(WARNING,
9482 "i40e device %s changed global register [0x%08x]."
9483 " original: 0x%08x, new: 0x%08x",
9484 dev->device->name, addr, reg,
9485 (uint32_t)i40e_read_rx_ctl(hw, addr));
9490 i40e_filter_input_set_init(struct i40e_pf *pf)
9492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9493 enum i40e_filter_pctype pctype;
9494 uint64_t input_set, inset_reg;
9495 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9499 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9500 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9501 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9503 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9506 input_set = i40e_get_default_input_set(pctype);
9508 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9509 I40E_INSET_MASK_NUM_REG);
9512 if (pf->support_multi_driver && num > 0) {
9513 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9516 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9519 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9520 (uint32_t)(inset_reg & UINT32_MAX));
9521 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9522 (uint32_t)((inset_reg >>
9523 I40E_32_BIT_WIDTH) & UINT32_MAX));
9524 if (!pf->support_multi_driver) {
9525 i40e_check_write_global_reg(hw,
9526 I40E_GLQF_HASH_INSET(0, pctype),
9527 (uint32_t)(inset_reg & UINT32_MAX));
9528 i40e_check_write_global_reg(hw,
9529 I40E_GLQF_HASH_INSET(1, pctype),
9530 (uint32_t)((inset_reg >>
9531 I40E_32_BIT_WIDTH) & UINT32_MAX));
9533 for (i = 0; i < num; i++) {
9534 i40e_check_write_global_reg(hw,
9535 I40E_GLQF_FD_MSK(i, pctype),
9537 i40e_check_write_global_reg(hw,
9538 I40E_GLQF_HASH_MSK(i, pctype),
9541 /*clear unused mask registers of the pctype */
9542 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9543 i40e_check_write_global_reg(hw,
9544 I40E_GLQF_FD_MSK(i, pctype),
9546 i40e_check_write_global_reg(hw,
9547 I40E_GLQF_HASH_MSK(i, pctype),
9551 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9553 I40E_WRITE_FLUSH(hw);
9555 /* store the default input set */
9556 if (!pf->support_multi_driver)
9557 pf->hash_input_set[pctype] = input_set;
9558 pf->fdir.input_set[pctype] = input_set;
9563 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9564 struct rte_eth_input_set_conf *conf)
9566 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9567 enum i40e_filter_pctype pctype;
9568 uint64_t input_set, inset_reg = 0;
9569 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9573 PMD_DRV_LOG(ERR, "Invalid pointer");
9576 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9577 conf->op != RTE_ETH_INPUT_SET_ADD) {
9578 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9582 if (pf->support_multi_driver) {
9583 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9587 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9588 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9589 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9593 if (hw->mac.type == I40E_MAC_X722) {
9594 /* get translated pctype value in fd pctype register */
9595 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9596 I40E_GLQF_FD_PCTYPES((int)pctype));
9599 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9602 PMD_DRV_LOG(ERR, "Failed to parse input set");
9606 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9607 /* get inset value in register */
9608 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9609 inset_reg <<= I40E_32_BIT_WIDTH;
9610 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9611 input_set |= pf->hash_input_set[pctype];
9613 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9614 I40E_INSET_MASK_NUM_REG);
9618 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9620 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9621 (uint32_t)(inset_reg & UINT32_MAX));
9622 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9623 (uint32_t)((inset_reg >>
9624 I40E_32_BIT_WIDTH) & UINT32_MAX));
9626 for (i = 0; i < num; i++)
9627 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9629 /*clear unused mask registers of the pctype */
9630 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9631 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9633 I40E_WRITE_FLUSH(hw);
9635 pf->hash_input_set[pctype] = input_set;
9640 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9641 struct rte_eth_input_set_conf *conf)
9643 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9644 enum i40e_filter_pctype pctype;
9645 uint64_t input_set, inset_reg = 0;
9646 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9650 PMD_DRV_LOG(ERR, "Invalid pointer");
9653 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9654 conf->op != RTE_ETH_INPUT_SET_ADD) {
9655 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9659 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9661 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9662 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9666 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9669 PMD_DRV_LOG(ERR, "Failed to parse input set");
9673 /* get inset value in register */
9674 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9675 inset_reg <<= I40E_32_BIT_WIDTH;
9676 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9678 /* Can not change the inset reg for flex payload for fdir,
9679 * it is done by writing I40E_PRTQF_FD_FLXINSET
9680 * in i40e_set_flex_mask_on_pctype.
9682 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9683 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9685 input_set |= pf->fdir.input_set[pctype];
9686 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9687 I40E_INSET_MASK_NUM_REG);
9690 if (pf->support_multi_driver && num > 0) {
9691 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9695 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9697 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9698 (uint32_t)(inset_reg & UINT32_MAX));
9699 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9700 (uint32_t)((inset_reg >>
9701 I40E_32_BIT_WIDTH) & UINT32_MAX));
9703 if (!pf->support_multi_driver) {
9704 for (i = 0; i < num; i++)
9705 i40e_check_write_global_reg(hw,
9706 I40E_GLQF_FD_MSK(i, pctype),
9708 /*clear unused mask registers of the pctype */
9709 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9710 i40e_check_write_global_reg(hw,
9711 I40E_GLQF_FD_MSK(i, pctype),
9714 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9716 I40E_WRITE_FLUSH(hw);
9718 pf->fdir.input_set[pctype] = input_set;
9723 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9728 PMD_DRV_LOG(ERR, "Invalid pointer");
9732 switch (info->info_type) {
9733 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9734 i40e_get_symmetric_hash_enable_per_port(hw,
9735 &(info->info.enable));
9737 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9738 ret = i40e_get_hash_filter_global_config(hw,
9739 &(info->info.global_conf));
9742 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9752 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9757 PMD_DRV_LOG(ERR, "Invalid pointer");
9761 switch (info->info_type) {
9762 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9763 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9765 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9766 ret = i40e_set_hash_filter_global_config(hw,
9767 &(info->info.global_conf));
9769 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9770 ret = i40e_hash_filter_inset_select(hw,
9771 &(info->info.input_set_conf));
9775 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9784 /* Operations for hash function */
9786 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9787 enum rte_filter_op filter_op,
9790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9793 switch (filter_op) {
9794 case RTE_ETH_FILTER_NOP:
9796 case RTE_ETH_FILTER_GET:
9797 ret = i40e_hash_filter_get(hw,
9798 (struct rte_eth_hash_filter_info *)arg);
9800 case RTE_ETH_FILTER_SET:
9801 ret = i40e_hash_filter_set(hw,
9802 (struct rte_eth_hash_filter_info *)arg);
9805 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9814 /* Convert ethertype filter structure */
9816 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9817 struct i40e_ethertype_filter *filter)
9819 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9820 filter->input.ether_type = input->ether_type;
9821 filter->flags = input->flags;
9822 filter->queue = input->queue;
9827 /* Check if there exists the ehtertype filter */
9828 struct i40e_ethertype_filter *
9829 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9830 const struct i40e_ethertype_filter_input *input)
9834 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9838 return ethertype_rule->hash_map[ret];
9841 /* Add ethertype filter in SW list */
9843 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9844 struct i40e_ethertype_filter *filter)
9846 struct i40e_ethertype_rule *rule = &pf->ethertype;
9849 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9852 "Failed to insert ethertype filter"
9853 " to hash table %d!",
9857 rule->hash_map[ret] = filter;
9859 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9864 /* Delete ethertype filter in SW list */
9866 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9867 struct i40e_ethertype_filter_input *input)
9869 struct i40e_ethertype_rule *rule = &pf->ethertype;
9870 struct i40e_ethertype_filter *filter;
9873 ret = rte_hash_del_key(rule->hash_table, input);
9876 "Failed to delete ethertype filter"
9877 " to hash table %d!",
9881 filter = rule->hash_map[ret];
9882 rule->hash_map[ret] = NULL;
9884 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9891 * Configure ethertype filter, which can director packet by filtering
9892 * with mac address and ether_type or only ether_type
9895 i40e_ethertype_filter_set(struct i40e_pf *pf,
9896 struct rte_eth_ethertype_filter *filter,
9899 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9900 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9901 struct i40e_ethertype_filter *ethertype_filter, *node;
9902 struct i40e_ethertype_filter check_filter;
9903 struct i40e_control_filter_stats stats;
9907 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9908 PMD_DRV_LOG(ERR, "Invalid queue ID");
9911 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9912 filter->ether_type == ETHER_TYPE_IPv6) {
9914 "unsupported ether_type(0x%04x) in control packet filter.",
9915 filter->ether_type);
9918 if (filter->ether_type == ETHER_TYPE_VLAN)
9919 PMD_DRV_LOG(WARNING,
9920 "filter vlan ether_type in first tag is not supported.");
9922 /* Check if there is the filter in SW list */
9923 memset(&check_filter, 0, sizeof(check_filter));
9924 i40e_ethertype_filter_convert(filter, &check_filter);
9925 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9926 &check_filter.input);
9928 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9932 if (!add && !node) {
9933 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9937 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9938 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9939 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9940 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9941 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9943 memset(&stats, 0, sizeof(stats));
9944 ret = i40e_aq_add_rem_control_packet_filter(hw,
9945 filter->mac_addr.addr_bytes,
9946 filter->ether_type, flags,
9948 filter->queue, add, &stats, NULL);
9951 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9952 ret, stats.mac_etype_used, stats.etype_used,
9953 stats.mac_etype_free, stats.etype_free);
9957 /* Add or delete a filter in SW list */
9959 ethertype_filter = rte_zmalloc("ethertype_filter",
9960 sizeof(*ethertype_filter), 0);
9961 if (ethertype_filter == NULL) {
9962 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9966 rte_memcpy(ethertype_filter, &check_filter,
9967 sizeof(check_filter));
9968 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9970 rte_free(ethertype_filter);
9972 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9979 * Handle operations for ethertype filter.
9982 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9983 enum rte_filter_op filter_op,
9986 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9989 if (filter_op == RTE_ETH_FILTER_NOP)
9993 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9998 switch (filter_op) {
9999 case RTE_ETH_FILTER_ADD:
10000 ret = i40e_ethertype_filter_set(pf,
10001 (struct rte_eth_ethertype_filter *)arg,
10004 case RTE_ETH_FILTER_DELETE:
10005 ret = i40e_ethertype_filter_set(pf,
10006 (struct rte_eth_ethertype_filter *)arg,
10010 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10018 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10019 enum rte_filter_type filter_type,
10020 enum rte_filter_op filter_op,
10028 switch (filter_type) {
10029 case RTE_ETH_FILTER_NONE:
10030 /* For global configuration */
10031 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10033 case RTE_ETH_FILTER_HASH:
10034 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10036 case RTE_ETH_FILTER_MACVLAN:
10037 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10039 case RTE_ETH_FILTER_ETHERTYPE:
10040 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10042 case RTE_ETH_FILTER_TUNNEL:
10043 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10045 case RTE_ETH_FILTER_FDIR:
10046 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10048 case RTE_ETH_FILTER_GENERIC:
10049 if (filter_op != RTE_ETH_FILTER_GET)
10051 *(const void **)arg = &i40e_flow_ops;
10054 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10064 * Check and enable Extended Tag.
10065 * Enabling Extended Tag is important for 40G performance.
10068 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10070 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10074 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10077 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10081 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10082 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10087 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10090 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10094 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10095 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10098 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10099 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10102 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10109 * As some registers wouldn't be reset unless a global hardware reset,
10110 * hardware initialization is needed to put those registers into an
10111 * expected initial state.
10114 i40e_hw_init(struct rte_eth_dev *dev)
10116 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10118 i40e_enable_extended_tag(dev);
10120 /* clear the PF Queue Filter control register */
10121 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10123 /* Disable symmetric hash per port */
10124 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10128 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10129 * however this function will return only one highest pctype index,
10130 * which is not quite correct. This is known problem of i40e driver
10131 * and needs to be fixed later.
10133 enum i40e_filter_pctype
10134 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10137 uint64_t pctype_mask;
10139 if (flow_type < I40E_FLOW_TYPE_MAX) {
10140 pctype_mask = adapter->pctypes_tbl[flow_type];
10141 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10142 if (pctype_mask & (1ULL << i))
10143 return (enum i40e_filter_pctype)i;
10146 return I40E_FILTER_PCTYPE_INVALID;
10150 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10151 enum i40e_filter_pctype pctype)
10154 uint64_t pctype_mask = 1ULL << pctype;
10156 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10158 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10162 return RTE_ETH_FLOW_UNKNOWN;
10166 * On X710, performance number is far from the expectation on recent firmware
10167 * versions; on XL710, performance number is also far from the expectation on
10168 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10169 * mode is enabled and port MAC address is equal to the packet destination MAC
10170 * address. The fix for this issue may not be integrated in the following
10171 * firmware version. So the workaround in software driver is needed. It needs
10172 * to modify the initial values of 3 internal only registers for both X710 and
10173 * XL710. Note that the values for X710 or XL710 could be different, and the
10174 * workaround can be removed when it is fixed in firmware in the future.
10177 /* For both X710 and XL710 */
10178 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10179 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10180 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10182 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10183 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10186 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10187 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10190 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10192 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10193 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10196 * GL_SWR_PM_UP_THR:
10197 * The value is not impacted from the link speed, its value is set according
10198 * to the total number of ports for a better pipe-monitor configuration.
10201 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10203 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10204 .device_id = (dev), \
10205 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10207 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10208 .device_id = (dev), \
10209 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10211 static const struct {
10212 uint16_t device_id;
10214 } swr_pm_table[] = {
10215 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10216 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10217 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10218 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10220 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10221 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10222 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10223 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10224 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10225 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10226 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10230 if (value == NULL) {
10231 PMD_DRV_LOG(ERR, "value is NULL");
10235 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10236 if (hw->device_id == swr_pm_table[i].device_id) {
10237 *value = swr_pm_table[i].val;
10239 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10241 hw->device_id, *value);
10250 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10252 enum i40e_status_code status;
10253 struct i40e_aq_get_phy_abilities_resp phy_ab;
10254 int ret = -ENOTSUP;
10257 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10261 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10264 rte_delay_us(100000);
10266 status = i40e_aq_get_phy_capabilities(hw, false,
10267 true, &phy_ab, NULL);
10275 i40e_configure_registers(struct i40e_hw *hw)
10281 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10282 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10283 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10289 for (i = 0; i < RTE_DIM(reg_table); i++) {
10290 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10291 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10293 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10294 else /* For X710/XL710/XXV710 */
10295 if (hw->aq.fw_maj_ver < 6)
10297 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10300 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10303 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10304 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10306 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10307 else /* For X710/XL710/XXV710 */
10309 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10312 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10315 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10316 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10317 "GL_SWR_PM_UP_THR value fixup",
10322 reg_table[i].val = cfg_val;
10325 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10328 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10329 reg_table[i].addr);
10332 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10333 reg_table[i].addr, reg);
10334 if (reg == reg_table[i].val)
10337 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10338 reg_table[i].val, NULL);
10341 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10342 reg_table[i].val, reg_table[i].addr);
10345 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10346 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10350 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10351 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10352 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10353 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10355 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10360 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10361 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10365 /* Configure for double VLAN RX stripping */
10366 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10367 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10368 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10369 ret = i40e_aq_debug_write_register(hw,
10370 I40E_VSI_TSR(vsi->vsi_id),
10373 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10375 return I40E_ERR_CONFIG;
10379 /* Configure for double VLAN TX insertion */
10380 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10381 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10382 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10383 ret = i40e_aq_debug_write_register(hw,
10384 I40E_VSI_L2TAGSTXVALID(
10385 vsi->vsi_id), reg, NULL);
10388 "Failed to update VSI_L2TAGSTXVALID[%d]",
10390 return I40E_ERR_CONFIG;
10398 * i40e_aq_add_mirror_rule
10399 * @hw: pointer to the hardware structure
10400 * @seid: VEB seid to add mirror rule to
10401 * @dst_id: destination vsi seid
10402 * @entries: Buffer which contains the entities to be mirrored
10403 * @count: number of entities contained in the buffer
10404 * @rule_id:the rule_id of the rule to be added
10406 * Add a mirror rule for a given veb.
10409 static enum i40e_status_code
10410 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10411 uint16_t seid, uint16_t dst_id,
10412 uint16_t rule_type, uint16_t *entries,
10413 uint16_t count, uint16_t *rule_id)
10415 struct i40e_aq_desc desc;
10416 struct i40e_aqc_add_delete_mirror_rule cmd;
10417 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10418 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10421 enum i40e_status_code status;
10423 i40e_fill_default_direct_cmd_desc(&desc,
10424 i40e_aqc_opc_add_mirror_rule);
10425 memset(&cmd, 0, sizeof(cmd));
10427 buff_len = sizeof(uint16_t) * count;
10428 desc.datalen = rte_cpu_to_le_16(buff_len);
10430 desc.flags |= rte_cpu_to_le_16(
10431 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10432 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10433 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10434 cmd.num_entries = rte_cpu_to_le_16(count);
10435 cmd.seid = rte_cpu_to_le_16(seid);
10436 cmd.destination = rte_cpu_to_le_16(dst_id);
10438 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10439 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10441 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10442 hw->aq.asq_last_status, resp->rule_id,
10443 resp->mirror_rules_used, resp->mirror_rules_free);
10444 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10450 * i40e_aq_del_mirror_rule
10451 * @hw: pointer to the hardware structure
10452 * @seid: VEB seid to add mirror rule to
10453 * @entries: Buffer which contains the entities to be mirrored
10454 * @count: number of entities contained in the buffer
10455 * @rule_id:the rule_id of the rule to be delete
10457 * Delete a mirror rule for a given veb.
10460 static enum i40e_status_code
10461 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10462 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10463 uint16_t count, uint16_t rule_id)
10465 struct i40e_aq_desc desc;
10466 struct i40e_aqc_add_delete_mirror_rule cmd;
10467 uint16_t buff_len = 0;
10468 enum i40e_status_code status;
10471 i40e_fill_default_direct_cmd_desc(&desc,
10472 i40e_aqc_opc_delete_mirror_rule);
10473 memset(&cmd, 0, sizeof(cmd));
10474 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10475 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10477 cmd.num_entries = count;
10478 buff_len = sizeof(uint16_t) * count;
10479 desc.datalen = rte_cpu_to_le_16(buff_len);
10480 buff = (void *)entries;
10482 /* rule id is filled in destination field for deleting mirror rule */
10483 cmd.destination = rte_cpu_to_le_16(rule_id);
10485 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10486 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10487 cmd.seid = rte_cpu_to_le_16(seid);
10489 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10490 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10496 * i40e_mirror_rule_set
10497 * @dev: pointer to the hardware structure
10498 * @mirror_conf: mirror rule info
10499 * @sw_id: mirror rule's sw_id
10500 * @on: enable/disable
10502 * set a mirror rule.
10506 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10507 struct rte_eth_mirror_conf *mirror_conf,
10508 uint8_t sw_id, uint8_t on)
10510 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10511 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10512 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10513 struct i40e_mirror_rule *parent = NULL;
10514 uint16_t seid, dst_seid, rule_id;
10518 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10520 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10522 "mirror rule can not be configured without veb or vfs.");
10525 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10526 PMD_DRV_LOG(ERR, "mirror table is full.");
10529 if (mirror_conf->dst_pool > pf->vf_num) {
10530 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10531 mirror_conf->dst_pool);
10535 seid = pf->main_vsi->veb->seid;
10537 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10538 if (sw_id <= it->index) {
10544 if (mirr_rule && sw_id == mirr_rule->index) {
10546 PMD_DRV_LOG(ERR, "mirror rule exists.");
10549 ret = i40e_aq_del_mirror_rule(hw, seid,
10550 mirr_rule->rule_type,
10551 mirr_rule->entries,
10552 mirr_rule->num_entries, mirr_rule->id);
10555 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10556 ret, hw->aq.asq_last_status);
10559 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10560 rte_free(mirr_rule);
10561 pf->nb_mirror_rule--;
10565 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10569 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10570 sizeof(struct i40e_mirror_rule) , 0);
10572 PMD_DRV_LOG(ERR, "failed to allocate memory");
10573 return I40E_ERR_NO_MEMORY;
10575 switch (mirror_conf->rule_type) {
10576 case ETH_MIRROR_VLAN:
10577 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10578 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10579 mirr_rule->entries[j] =
10580 mirror_conf->vlan.vlan_id[i];
10585 PMD_DRV_LOG(ERR, "vlan is not specified.");
10586 rte_free(mirr_rule);
10589 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10591 case ETH_MIRROR_VIRTUAL_POOL_UP:
10592 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10593 /* check if the specified pool bit is out of range */
10594 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10595 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10596 rte_free(mirr_rule);
10599 for (i = 0, j = 0; i < pf->vf_num; i++) {
10600 if (mirror_conf->pool_mask & (1ULL << i)) {
10601 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10605 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10606 /* add pf vsi to entries */
10607 mirr_rule->entries[j] = pf->main_vsi_seid;
10611 PMD_DRV_LOG(ERR, "pool is not specified.");
10612 rte_free(mirr_rule);
10615 /* egress and ingress in aq commands means from switch but not port */
10616 mirr_rule->rule_type =
10617 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10618 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10619 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10621 case ETH_MIRROR_UPLINK_PORT:
10622 /* egress and ingress in aq commands means from switch but not port*/
10623 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10625 case ETH_MIRROR_DOWNLINK_PORT:
10626 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10629 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10630 mirror_conf->rule_type);
10631 rte_free(mirr_rule);
10635 /* If the dst_pool is equal to vf_num, consider it as PF */
10636 if (mirror_conf->dst_pool == pf->vf_num)
10637 dst_seid = pf->main_vsi_seid;
10639 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10641 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10642 mirr_rule->rule_type, mirr_rule->entries,
10646 "failed to add mirror rule: ret = %d, aq_err = %d.",
10647 ret, hw->aq.asq_last_status);
10648 rte_free(mirr_rule);
10652 mirr_rule->index = sw_id;
10653 mirr_rule->num_entries = j;
10654 mirr_rule->id = rule_id;
10655 mirr_rule->dst_vsi_seid = dst_seid;
10658 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10660 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10662 pf->nb_mirror_rule++;
10667 * i40e_mirror_rule_reset
10668 * @dev: pointer to the device
10669 * @sw_id: mirror rule's sw_id
10671 * reset a mirror rule.
10675 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10677 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10679 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10683 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10685 seid = pf->main_vsi->veb->seid;
10687 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10688 if (sw_id == it->index) {
10694 ret = i40e_aq_del_mirror_rule(hw, seid,
10695 mirr_rule->rule_type,
10696 mirr_rule->entries,
10697 mirr_rule->num_entries, mirr_rule->id);
10700 "failed to remove mirror rule: status = %d, aq_err = %d.",
10701 ret, hw->aq.asq_last_status);
10704 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10705 rte_free(mirr_rule);
10706 pf->nb_mirror_rule--;
10708 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10715 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10718 uint64_t systim_cycles;
10720 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10721 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10724 return systim_cycles;
10728 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10731 uint64_t rx_tstamp;
10733 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10734 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10741 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10743 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10744 uint64_t tx_tstamp;
10746 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10747 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10754 i40e_start_timecounters(struct rte_eth_dev *dev)
10756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10757 struct i40e_adapter *adapter =
10758 (struct i40e_adapter *)dev->data->dev_private;
10759 struct rte_eth_link link;
10760 uint32_t tsync_inc_l;
10761 uint32_t tsync_inc_h;
10763 /* Get current link speed. */
10764 i40e_dev_link_update(dev, 1);
10765 rte_eth_linkstatus_get(dev, &link);
10767 switch (link.link_speed) {
10768 case ETH_SPEED_NUM_40G:
10769 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10770 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10772 case ETH_SPEED_NUM_10G:
10773 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10774 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10776 case ETH_SPEED_NUM_1G:
10777 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10778 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10785 /* Set the timesync increment value. */
10786 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10787 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10789 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10790 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10791 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10793 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10794 adapter->systime_tc.cc_shift = 0;
10795 adapter->systime_tc.nsec_mask = 0;
10797 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10798 adapter->rx_tstamp_tc.cc_shift = 0;
10799 adapter->rx_tstamp_tc.nsec_mask = 0;
10801 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10802 adapter->tx_tstamp_tc.cc_shift = 0;
10803 adapter->tx_tstamp_tc.nsec_mask = 0;
10807 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10809 struct i40e_adapter *adapter =
10810 (struct i40e_adapter *)dev->data->dev_private;
10812 adapter->systime_tc.nsec += delta;
10813 adapter->rx_tstamp_tc.nsec += delta;
10814 adapter->tx_tstamp_tc.nsec += delta;
10820 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10823 struct i40e_adapter *adapter =
10824 (struct i40e_adapter *)dev->data->dev_private;
10826 ns = rte_timespec_to_ns(ts);
10828 /* Set the timecounters to a new value. */
10829 adapter->systime_tc.nsec = ns;
10830 adapter->rx_tstamp_tc.nsec = ns;
10831 adapter->tx_tstamp_tc.nsec = ns;
10837 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10839 uint64_t ns, systime_cycles;
10840 struct i40e_adapter *adapter =
10841 (struct i40e_adapter *)dev->data->dev_private;
10843 systime_cycles = i40e_read_systime_cyclecounter(dev);
10844 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10845 *ts = rte_ns_to_timespec(ns);
10851 i40e_timesync_enable(struct rte_eth_dev *dev)
10853 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10854 uint32_t tsync_ctl_l;
10855 uint32_t tsync_ctl_h;
10857 /* Stop the timesync system time. */
10858 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10859 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10860 /* Reset the timesync system time value. */
10861 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10862 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10864 i40e_start_timecounters(dev);
10866 /* Clear timesync registers. */
10867 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10868 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10869 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10870 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10871 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10872 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10874 /* Enable timestamping of PTP packets. */
10875 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10876 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10878 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10879 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10880 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10882 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10883 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10889 i40e_timesync_disable(struct rte_eth_dev *dev)
10891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10892 uint32_t tsync_ctl_l;
10893 uint32_t tsync_ctl_h;
10895 /* Disable timestamping of transmitted PTP packets. */
10896 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10897 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10899 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10900 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10902 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10903 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10905 /* Reset the timesync increment value. */
10906 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10907 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10913 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10914 struct timespec *timestamp, uint32_t flags)
10916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10917 struct i40e_adapter *adapter =
10918 (struct i40e_adapter *)dev->data->dev_private;
10920 uint32_t sync_status;
10921 uint32_t index = flags & 0x03;
10922 uint64_t rx_tstamp_cycles;
10925 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10926 if ((sync_status & (1 << index)) == 0)
10929 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10930 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10931 *timestamp = rte_ns_to_timespec(ns);
10937 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10938 struct timespec *timestamp)
10940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10941 struct i40e_adapter *adapter =
10942 (struct i40e_adapter *)dev->data->dev_private;
10944 uint32_t sync_status;
10945 uint64_t tx_tstamp_cycles;
10948 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10949 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10952 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10953 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10954 *timestamp = rte_ns_to_timespec(ns);
10960 * i40e_parse_dcb_configure - parse dcb configure from user
10961 * @dev: the device being configured
10962 * @dcb_cfg: pointer of the result of parse
10963 * @*tc_map: bit map of enabled traffic classes
10965 * Returns 0 on success, negative value on failure
10968 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10969 struct i40e_dcbx_config *dcb_cfg,
10972 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10973 uint8_t i, tc_bw, bw_lf;
10975 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10977 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10978 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10979 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10983 /* assume each tc has the same bw */
10984 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10985 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10986 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10987 /* to ensure the sum of tcbw is equal to 100 */
10988 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10989 for (i = 0; i < bw_lf; i++)
10990 dcb_cfg->etscfg.tcbwtable[i]++;
10992 /* assume each tc has the same Transmission Selection Algorithm */
10993 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10994 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10996 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10997 dcb_cfg->etscfg.prioritytable[i] =
10998 dcb_rx_conf->dcb_tc[i];
11000 /* FW needs one App to configure HW */
11001 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11002 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11003 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11004 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11006 if (dcb_rx_conf->nb_tcs == 0)
11007 *tc_map = 1; /* tc0 only */
11009 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11011 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11012 dcb_cfg->pfc.willing = 0;
11013 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11014 dcb_cfg->pfc.pfcenable = *tc_map;
11020 static enum i40e_status_code
11021 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11022 struct i40e_aqc_vsi_properties_data *info,
11023 uint8_t enabled_tcmap)
11025 enum i40e_status_code ret;
11026 int i, total_tc = 0;
11027 uint16_t qpnum_per_tc, bsf, qp_idx;
11028 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11029 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11030 uint16_t used_queues;
11032 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11033 if (ret != I40E_SUCCESS)
11036 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11037 if (enabled_tcmap & (1 << i))
11042 vsi->enabled_tc = enabled_tcmap;
11044 /* different VSI has different queues assigned */
11045 if (vsi->type == I40E_VSI_MAIN)
11046 used_queues = dev_data->nb_rx_queues -
11047 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11048 else if (vsi->type == I40E_VSI_VMDQ2)
11049 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11051 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11052 return I40E_ERR_NO_AVAILABLE_VSI;
11055 qpnum_per_tc = used_queues / total_tc;
11056 /* Number of queues per enabled TC */
11057 if (qpnum_per_tc == 0) {
11058 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11059 return I40E_ERR_INVALID_QP_ID;
11061 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11062 I40E_MAX_Q_PER_TC);
11063 bsf = rte_bsf32(qpnum_per_tc);
11066 * Configure TC and queue mapping parameters, for enabled TC,
11067 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11068 * default queue will serve it.
11071 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11072 if (vsi->enabled_tc & (1 << i)) {
11073 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11074 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11075 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11076 qp_idx += qpnum_per_tc;
11078 info->tc_mapping[i] = 0;
11081 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11082 if (vsi->type == I40E_VSI_SRIOV) {
11083 info->mapping_flags |=
11084 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11085 for (i = 0; i < vsi->nb_qps; i++)
11086 info->queue_mapping[i] =
11087 rte_cpu_to_le_16(vsi->base_queue + i);
11089 info->mapping_flags |=
11090 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11091 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11093 info->valid_sections |=
11094 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11096 return I40E_SUCCESS;
11100 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11101 * @veb: VEB to be configured
11102 * @tc_map: enabled TC bitmap
11104 * Returns 0 on success, negative value on failure
11106 static enum i40e_status_code
11107 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11109 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11110 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11111 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11112 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11113 enum i40e_status_code ret = I40E_SUCCESS;
11117 /* Check if enabled_tc is same as existing or new TCs */
11118 if (veb->enabled_tc == tc_map)
11121 /* configure tc bandwidth */
11122 memset(&veb_bw, 0, sizeof(veb_bw));
11123 veb_bw.tc_valid_bits = tc_map;
11124 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11125 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11126 if (tc_map & BIT_ULL(i))
11127 veb_bw.tc_bw_share_credits[i] = 1;
11129 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11133 "AQ command Config switch_comp BW allocation per TC failed = %d",
11134 hw->aq.asq_last_status);
11138 memset(&ets_query, 0, sizeof(ets_query));
11139 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11141 if (ret != I40E_SUCCESS) {
11143 "Failed to get switch_comp ETS configuration %u",
11144 hw->aq.asq_last_status);
11147 memset(&bw_query, 0, sizeof(bw_query));
11148 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11150 if (ret != I40E_SUCCESS) {
11152 "Failed to get switch_comp bandwidth configuration %u",
11153 hw->aq.asq_last_status);
11157 /* store and print out BW info */
11158 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11159 veb->bw_info.bw_max = ets_query.tc_bw_max;
11160 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11161 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11162 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11163 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11164 I40E_16_BIT_WIDTH);
11165 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11166 veb->bw_info.bw_ets_share_credits[i] =
11167 bw_query.tc_bw_share_credits[i];
11168 veb->bw_info.bw_ets_credits[i] =
11169 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11170 /* 4 bits per TC, 4th bit is reserved */
11171 veb->bw_info.bw_ets_max[i] =
11172 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11173 RTE_LEN2MASK(3, uint8_t));
11174 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11175 veb->bw_info.bw_ets_share_credits[i]);
11176 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11177 veb->bw_info.bw_ets_credits[i]);
11178 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11179 veb->bw_info.bw_ets_max[i]);
11182 veb->enabled_tc = tc_map;
11189 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11190 * @vsi: VSI to be configured
11191 * @tc_map: enabled TC bitmap
11193 * Returns 0 on success, negative value on failure
11195 static enum i40e_status_code
11196 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11198 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11199 struct i40e_vsi_context ctxt;
11200 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11201 enum i40e_status_code ret = I40E_SUCCESS;
11204 /* Check if enabled_tc is same as existing or new TCs */
11205 if (vsi->enabled_tc == tc_map)
11208 /* configure tc bandwidth */
11209 memset(&bw_data, 0, sizeof(bw_data));
11210 bw_data.tc_valid_bits = tc_map;
11211 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11212 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11213 if (tc_map & BIT_ULL(i))
11214 bw_data.tc_bw_credits[i] = 1;
11216 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11219 "AQ command Config VSI BW allocation per TC failed = %d",
11220 hw->aq.asq_last_status);
11223 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11224 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11226 /* Update Queue Pairs Mapping for currently enabled UPs */
11227 ctxt.seid = vsi->seid;
11228 ctxt.pf_num = hw->pf_id;
11230 ctxt.uplink_seid = vsi->uplink_seid;
11231 ctxt.info = vsi->info;
11233 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11237 /* Update the VSI after updating the VSI queue-mapping information */
11238 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11240 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11241 hw->aq.asq_last_status);
11244 /* update the local VSI info with updated queue map */
11245 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11246 sizeof(vsi->info.tc_mapping));
11247 rte_memcpy(&vsi->info.queue_mapping,
11248 &ctxt.info.queue_mapping,
11249 sizeof(vsi->info.queue_mapping));
11250 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11251 vsi->info.valid_sections = 0;
11253 /* query and update current VSI BW information */
11254 ret = i40e_vsi_get_bw_config(vsi);
11257 "Failed updating vsi bw info, err %s aq_err %s",
11258 i40e_stat_str(hw, ret),
11259 i40e_aq_str(hw, hw->aq.asq_last_status));
11263 vsi->enabled_tc = tc_map;
11270 * i40e_dcb_hw_configure - program the dcb setting to hw
11271 * @pf: pf the configuration is taken on
11272 * @new_cfg: new configuration
11273 * @tc_map: enabled TC bitmap
11275 * Returns 0 on success, negative value on failure
11277 static enum i40e_status_code
11278 i40e_dcb_hw_configure(struct i40e_pf *pf,
11279 struct i40e_dcbx_config *new_cfg,
11282 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11283 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11284 struct i40e_vsi *main_vsi = pf->main_vsi;
11285 struct i40e_vsi_list *vsi_list;
11286 enum i40e_status_code ret;
11290 /* Use the FW API if FW > v4.4*/
11291 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11292 (hw->aq.fw_maj_ver >= 5))) {
11294 "FW < v4.4, can not use FW LLDP API to configure DCB");
11295 return I40E_ERR_FIRMWARE_API_VERSION;
11298 /* Check if need reconfiguration */
11299 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11300 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11301 return I40E_SUCCESS;
11304 /* Copy the new config to the current config */
11305 *old_cfg = *new_cfg;
11306 old_cfg->etsrec = old_cfg->etscfg;
11307 ret = i40e_set_dcb_config(hw);
11309 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11310 i40e_stat_str(hw, ret),
11311 i40e_aq_str(hw, hw->aq.asq_last_status));
11314 /* set receive Arbiter to RR mode and ETS scheme by default */
11315 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11316 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11317 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11318 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11319 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11320 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11321 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11322 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11323 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11324 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11325 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11326 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11327 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11329 /* get local mib to check whether it is configured correctly */
11331 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11332 /* Get Local DCB Config */
11333 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11334 &hw->local_dcbx_config);
11336 /* if Veb is created, need to update TC of it at first */
11337 if (main_vsi->veb) {
11338 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11340 PMD_INIT_LOG(WARNING,
11341 "Failed configuring TC for VEB seid=%d",
11342 main_vsi->veb->seid);
11344 /* Update each VSI */
11345 i40e_vsi_config_tc(main_vsi, tc_map);
11346 if (main_vsi->veb) {
11347 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11348 /* Beside main VSI and VMDQ VSIs, only enable default
11349 * TC for other VSIs
11351 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11352 ret = i40e_vsi_config_tc(vsi_list->vsi,
11355 ret = i40e_vsi_config_tc(vsi_list->vsi,
11356 I40E_DEFAULT_TCMAP);
11358 PMD_INIT_LOG(WARNING,
11359 "Failed configuring TC for VSI seid=%d",
11360 vsi_list->vsi->seid);
11364 return I40E_SUCCESS;
11368 * i40e_dcb_init_configure - initial dcb config
11369 * @dev: device being configured
11370 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11372 * Returns 0 on success, negative value on failure
11375 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11377 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11378 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11381 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11382 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11386 /* DCB initialization:
11387 * Update DCB configuration from the Firmware and configure
11388 * LLDP MIB change event.
11390 if (sw_dcb == TRUE) {
11391 /* When using NVM 6.01 or later, the RX data path does
11392 * not hang if the FW LLDP is stopped.
11394 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11395 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11396 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11397 if (ret != I40E_SUCCESS)
11398 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11401 ret = i40e_init_dcb(hw);
11402 /* If lldp agent is stopped, the return value from
11403 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11404 * adminq status. Otherwise, it should return success.
11406 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11407 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11408 memset(&hw->local_dcbx_config, 0,
11409 sizeof(struct i40e_dcbx_config));
11410 /* set dcb default configuration */
11411 hw->local_dcbx_config.etscfg.willing = 0;
11412 hw->local_dcbx_config.etscfg.maxtcs = 0;
11413 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11414 hw->local_dcbx_config.etscfg.tsatable[0] =
11416 /* all UPs mapping to TC0 */
11417 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11418 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11419 hw->local_dcbx_config.etsrec =
11420 hw->local_dcbx_config.etscfg;
11421 hw->local_dcbx_config.pfc.willing = 0;
11422 hw->local_dcbx_config.pfc.pfccap =
11423 I40E_MAX_TRAFFIC_CLASS;
11424 /* FW needs one App to configure HW */
11425 hw->local_dcbx_config.numapps = 1;
11426 hw->local_dcbx_config.app[0].selector =
11427 I40E_APP_SEL_ETHTYPE;
11428 hw->local_dcbx_config.app[0].priority = 3;
11429 hw->local_dcbx_config.app[0].protocolid =
11430 I40E_APP_PROTOID_FCOE;
11431 ret = i40e_set_dcb_config(hw);
11434 "default dcb config fails. err = %d, aq_err = %d.",
11435 ret, hw->aq.asq_last_status);
11440 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11441 ret, hw->aq.asq_last_status);
11445 ret = i40e_aq_start_lldp(hw, NULL);
11446 if (ret != I40E_SUCCESS)
11447 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11449 ret = i40e_init_dcb(hw);
11451 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11453 "HW doesn't support DCBX offload.");
11458 "DCBX configuration failed, err = %d, aq_err = %d.",
11459 ret, hw->aq.asq_last_status);
11467 * i40e_dcb_setup - setup dcb related config
11468 * @dev: device being configured
11470 * Returns 0 on success, negative value on failure
11473 i40e_dcb_setup(struct rte_eth_dev *dev)
11475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11476 struct i40e_dcbx_config dcb_cfg;
11477 uint8_t tc_map = 0;
11480 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11481 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11485 if (pf->vf_num != 0)
11486 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11488 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11490 PMD_INIT_LOG(ERR, "invalid dcb config");
11493 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11495 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11503 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11504 struct rte_eth_dcb_info *dcb_info)
11506 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11507 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11508 struct i40e_vsi *vsi = pf->main_vsi;
11509 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11510 uint16_t bsf, tc_mapping;
11513 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11514 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11516 dcb_info->nb_tcs = 1;
11517 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11518 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11519 for (i = 0; i < dcb_info->nb_tcs; i++)
11520 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11522 /* get queue mapping if vmdq is disabled */
11523 if (!pf->nb_cfg_vmdq_vsi) {
11524 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11525 if (!(vsi->enabled_tc & (1 << i)))
11527 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11528 dcb_info->tc_queue.tc_rxq[j][i].base =
11529 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11530 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11531 dcb_info->tc_queue.tc_txq[j][i].base =
11532 dcb_info->tc_queue.tc_rxq[j][i].base;
11533 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11534 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11535 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11536 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11537 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11542 /* get queue mapping if vmdq is enabled */
11544 vsi = pf->vmdq[j].vsi;
11545 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11546 if (!(vsi->enabled_tc & (1 << i)))
11548 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11549 dcb_info->tc_queue.tc_rxq[j][i].base =
11550 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11551 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11552 dcb_info->tc_queue.tc_txq[j][i].base =
11553 dcb_info->tc_queue.tc_rxq[j][i].base;
11554 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11555 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11556 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11557 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11558 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11561 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11566 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11568 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11569 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11570 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11571 uint16_t msix_intr;
11573 msix_intr = intr_handle->intr_vec[queue_id];
11574 if (msix_intr == I40E_MISC_VEC_ID)
11575 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11576 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11577 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11578 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11581 I40E_PFINT_DYN_CTLN(msix_intr -
11582 I40E_RX_VEC_START),
11583 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11584 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11585 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11587 I40E_WRITE_FLUSH(hw);
11588 rte_intr_enable(&pci_dev->intr_handle);
11594 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11597 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11599 uint16_t msix_intr;
11601 msix_intr = intr_handle->intr_vec[queue_id];
11602 if (msix_intr == I40E_MISC_VEC_ID)
11603 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11604 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11607 I40E_PFINT_DYN_CTLN(msix_intr -
11608 I40E_RX_VEC_START),
11609 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11610 I40E_WRITE_FLUSH(hw);
11615 static int i40e_get_regs(struct rte_eth_dev *dev,
11616 struct rte_dev_reg_info *regs)
11618 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11619 uint32_t *ptr_data = regs->data;
11620 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11621 const struct i40e_reg_info *reg_info;
11623 if (ptr_data == NULL) {
11624 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11625 regs->width = sizeof(uint32_t);
11629 /* The first few registers have to be read using AQ operations */
11631 while (i40e_regs_adminq[reg_idx].name) {
11632 reg_info = &i40e_regs_adminq[reg_idx++];
11633 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11635 arr_idx2 <= reg_info->count2;
11637 reg_offset = arr_idx * reg_info->stride1 +
11638 arr_idx2 * reg_info->stride2;
11639 reg_offset += reg_info->base_addr;
11640 ptr_data[reg_offset >> 2] =
11641 i40e_read_rx_ctl(hw, reg_offset);
11645 /* The remaining registers can be read using primitives */
11647 while (i40e_regs_others[reg_idx].name) {
11648 reg_info = &i40e_regs_others[reg_idx++];
11649 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11651 arr_idx2 <= reg_info->count2;
11653 reg_offset = arr_idx * reg_info->stride1 +
11654 arr_idx2 * reg_info->stride2;
11655 reg_offset += reg_info->base_addr;
11656 ptr_data[reg_offset >> 2] =
11657 I40E_READ_REG(hw, reg_offset);
11664 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11668 /* Convert word count to byte count */
11669 return hw->nvm.sr_size << 1;
11672 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11673 struct rte_dev_eeprom_info *eeprom)
11675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11676 uint16_t *data = eeprom->data;
11677 uint16_t offset, length, cnt_words;
11680 offset = eeprom->offset >> 1;
11681 length = eeprom->length >> 1;
11682 cnt_words = length;
11684 if (offset > hw->nvm.sr_size ||
11685 offset + length > hw->nvm.sr_size) {
11686 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11690 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11692 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11693 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11694 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11701 static int i40e_get_module_info(struct rte_eth_dev *dev,
11702 struct rte_eth_dev_module_info *modinfo)
11704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11705 uint32_t sff8472_comp = 0;
11706 uint32_t sff8472_swap = 0;
11707 uint32_t sff8636_rev = 0;
11708 i40e_status status;
11711 /* Check if firmware supports reading module EEPROM. */
11712 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11714 "Module EEPROM memory read not supported. "
11715 "Please update the NVM image.\n");
11719 status = i40e_update_link_info(hw);
11723 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11725 "Cannot read module EEPROM memory. "
11726 "No module connected.\n");
11730 type = hw->phy.link_info.module_type[0];
11733 case I40E_MODULE_TYPE_SFP:
11734 status = i40e_aq_get_phy_register(hw,
11735 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11736 I40E_I2C_EEPROM_DEV_ADDR, 1,
11737 I40E_MODULE_SFF_8472_COMP,
11738 &sff8472_comp, NULL);
11742 status = i40e_aq_get_phy_register(hw,
11743 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11744 I40E_I2C_EEPROM_DEV_ADDR, 1,
11745 I40E_MODULE_SFF_8472_SWAP,
11746 &sff8472_swap, NULL);
11750 /* Check if the module requires address swap to access
11751 * the other EEPROM memory page.
11753 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11754 PMD_DRV_LOG(WARNING,
11755 "Module address swap to access "
11756 "page 0xA2 is not supported.\n");
11757 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11758 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11759 } else if (sff8472_comp == 0x00) {
11760 /* Module is not SFF-8472 compliant */
11761 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11762 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11764 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11765 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11768 case I40E_MODULE_TYPE_QSFP_PLUS:
11769 /* Read from memory page 0. */
11770 status = i40e_aq_get_phy_register(hw,
11771 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11773 I40E_MODULE_REVISION_ADDR,
11774 &sff8636_rev, NULL);
11777 /* Determine revision compliance byte */
11778 if (sff8636_rev > 0x02) {
11779 /* Module is SFF-8636 compliant */
11780 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11781 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11783 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11784 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11787 case I40E_MODULE_TYPE_QSFP28:
11788 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11789 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11792 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11798 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11799 struct rte_dev_eeprom_info *info)
11801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11802 bool is_sfp = false;
11803 i40e_status status;
11804 uint8_t *data = info->data;
11805 uint32_t value = 0;
11808 if (!info || !info->length || !data)
11811 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11814 for (i = 0; i < info->length; i++) {
11815 u32 offset = i + info->offset;
11816 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11818 /* Check if we need to access the other memory page */
11820 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11821 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11822 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11825 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11826 /* Compute memory page number and offset. */
11827 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11831 status = i40e_aq_get_phy_register(hw,
11832 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11833 addr, offset, 1, &value, NULL);
11836 data[i] = (uint8_t)value;
11841 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11842 struct ether_addr *mac_addr)
11844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11845 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11846 struct i40e_vsi *vsi = pf->main_vsi;
11847 struct i40e_mac_filter_info mac_filter;
11848 struct i40e_mac_filter *f;
11851 if (!is_valid_assigned_ether_addr(mac_addr)) {
11852 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11856 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11857 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11862 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11866 mac_filter = f->mac_info;
11867 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11868 if (ret != I40E_SUCCESS) {
11869 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11872 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11873 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11874 if (ret != I40E_SUCCESS) {
11875 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11878 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11880 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11881 mac_addr->addr_bytes, NULL);
11882 if (ret != I40E_SUCCESS) {
11883 PMD_DRV_LOG(ERR, "Failed to change mac");
11891 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11893 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11894 struct rte_eth_dev_data *dev_data = pf->dev_data;
11895 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11898 /* check if mtu is within the allowed range */
11899 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11902 /* mtu setting is forbidden if port is start */
11903 if (dev_data->dev_started) {
11904 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11905 dev_data->port_id);
11909 if (frame_size > ETHER_MAX_LEN)
11910 dev_data->dev_conf.rxmode.offloads |=
11911 DEV_RX_OFFLOAD_JUMBO_FRAME;
11913 dev_data->dev_conf.rxmode.offloads &=
11914 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11916 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11921 /* Restore ethertype filter */
11923 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11925 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11926 struct i40e_ethertype_filter_list
11927 *ethertype_list = &pf->ethertype.ethertype_list;
11928 struct i40e_ethertype_filter *f;
11929 struct i40e_control_filter_stats stats;
11932 TAILQ_FOREACH(f, ethertype_list, rules) {
11934 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11935 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11936 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11937 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11938 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11940 memset(&stats, 0, sizeof(stats));
11941 i40e_aq_add_rem_control_packet_filter(hw,
11942 f->input.mac_addr.addr_bytes,
11943 f->input.ether_type,
11944 flags, pf->main_vsi->seid,
11945 f->queue, 1, &stats, NULL);
11947 PMD_DRV_LOG(INFO, "Ethertype filter:"
11948 " mac_etype_used = %u, etype_used = %u,"
11949 " mac_etype_free = %u, etype_free = %u",
11950 stats.mac_etype_used, stats.etype_used,
11951 stats.mac_etype_free, stats.etype_free);
11954 /* Restore tunnel filter */
11956 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11958 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11959 struct i40e_vsi *vsi;
11960 struct i40e_pf_vf *vf;
11961 struct i40e_tunnel_filter_list
11962 *tunnel_list = &pf->tunnel.tunnel_list;
11963 struct i40e_tunnel_filter *f;
11964 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11965 bool big_buffer = 0;
11967 TAILQ_FOREACH(f, tunnel_list, rules) {
11969 vsi = pf->main_vsi;
11971 vf = &pf->vfs[f->vf_id];
11974 memset(&cld_filter, 0, sizeof(cld_filter));
11975 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11976 (struct ether_addr *)&cld_filter.element.outer_mac);
11977 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11978 (struct ether_addr *)&cld_filter.element.inner_mac);
11979 cld_filter.element.inner_vlan = f->input.inner_vlan;
11980 cld_filter.element.flags = f->input.flags;
11981 cld_filter.element.tenant_id = f->input.tenant_id;
11982 cld_filter.element.queue_number = f->queue;
11983 rte_memcpy(cld_filter.general_fields,
11984 f->input.general_fields,
11985 sizeof(f->input.general_fields));
11987 if (((f->input.flags &
11988 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11989 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11991 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11992 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11994 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11995 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11999 i40e_aq_add_cloud_filters_bb(hw,
12000 vsi->seid, &cld_filter, 1);
12002 i40e_aq_add_cloud_filters(hw, vsi->seid,
12003 &cld_filter.element, 1);
12007 /* Restore rss filter */
12009 i40e_rss_filter_restore(struct i40e_pf *pf)
12011 struct i40e_rte_flow_rss_conf *conf =
12013 if (conf->conf.queue_num)
12014 i40e_config_rss_filter(pf, conf, TRUE);
12018 i40e_filter_restore(struct i40e_pf *pf)
12020 i40e_ethertype_filter_restore(pf);
12021 i40e_tunnel_filter_restore(pf);
12022 i40e_fdir_filter_restore(pf);
12023 i40e_rss_filter_restore(pf);
12027 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12029 if (strcmp(dev->device->driver->name, drv->driver.name))
12036 is_i40e_supported(struct rte_eth_dev *dev)
12038 return is_device_supported(dev, &rte_i40e_pmd);
12041 struct i40e_customized_pctype*
12042 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12046 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12047 if (pf->customized_pctype[i].index == index)
12048 return &pf->customized_pctype[i];
12054 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12055 uint32_t pkg_size, uint32_t proto_num,
12056 struct rte_pmd_i40e_proto_info *proto,
12057 enum rte_pmd_i40e_package_op op)
12059 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12060 uint32_t pctype_num;
12061 struct rte_pmd_i40e_ptype_info *pctype;
12062 uint32_t buff_size;
12063 struct i40e_customized_pctype *new_pctype = NULL;
12065 uint8_t pctype_value;
12070 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12071 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12072 PMD_DRV_LOG(ERR, "Unsupported operation.");
12076 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12077 (uint8_t *)&pctype_num, sizeof(pctype_num),
12078 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12080 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12084 PMD_DRV_LOG(INFO, "No new pctype added");
12088 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12089 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12091 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12094 /* get information about new pctype list */
12095 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12096 (uint8_t *)pctype, buff_size,
12097 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12099 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12104 /* Update customized pctype. */
12105 for (i = 0; i < pctype_num; i++) {
12106 pctype_value = pctype[i].ptype_id;
12107 memset(name, 0, sizeof(name));
12108 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12109 proto_id = pctype[i].protocols[j];
12110 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12112 for (n = 0; n < proto_num; n++) {
12113 if (proto[n].proto_id != proto_id)
12115 strcat(name, proto[n].name);
12120 name[strlen(name) - 1] = '\0';
12121 if (!strcmp(name, "GTPC"))
12123 i40e_find_customized_pctype(pf,
12124 I40E_CUSTOMIZED_GTPC);
12125 else if (!strcmp(name, "GTPU_IPV4"))
12127 i40e_find_customized_pctype(pf,
12128 I40E_CUSTOMIZED_GTPU_IPV4);
12129 else if (!strcmp(name, "GTPU_IPV6"))
12131 i40e_find_customized_pctype(pf,
12132 I40E_CUSTOMIZED_GTPU_IPV6);
12133 else if (!strcmp(name, "GTPU"))
12135 i40e_find_customized_pctype(pf,
12136 I40E_CUSTOMIZED_GTPU);
12138 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12139 new_pctype->pctype = pctype_value;
12140 new_pctype->valid = true;
12142 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12143 new_pctype->valid = false;
12153 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12154 uint32_t pkg_size, uint32_t proto_num,
12155 struct rte_pmd_i40e_proto_info *proto,
12156 enum rte_pmd_i40e_package_op op)
12158 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12159 uint16_t port_id = dev->data->port_id;
12160 uint32_t ptype_num;
12161 struct rte_pmd_i40e_ptype_info *ptype;
12162 uint32_t buff_size;
12164 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12169 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12170 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12171 PMD_DRV_LOG(ERR, "Unsupported operation.");
12175 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12176 rte_pmd_i40e_ptype_mapping_reset(port_id);
12180 /* get information about new ptype num */
12181 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12182 (uint8_t *)&ptype_num, sizeof(ptype_num),
12183 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12185 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12189 PMD_DRV_LOG(INFO, "No new ptype added");
12193 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12194 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12196 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12200 /* get information about new ptype list */
12201 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12202 (uint8_t *)ptype, buff_size,
12203 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12205 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12210 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12211 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12212 if (!ptype_mapping) {
12213 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12218 /* Update ptype mapping table. */
12219 for (i = 0; i < ptype_num; i++) {
12220 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12221 ptype_mapping[i].sw_ptype = 0;
12223 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12224 proto_id = ptype[i].protocols[j];
12225 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12227 for (n = 0; n < proto_num; n++) {
12228 if (proto[n].proto_id != proto_id)
12230 memset(name, 0, sizeof(name));
12231 strcpy(name, proto[n].name);
12232 if (!strncasecmp(name, "PPPOE", 5))
12233 ptype_mapping[i].sw_ptype |=
12234 RTE_PTYPE_L2_ETHER_PPPOE;
12235 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12237 ptype_mapping[i].sw_ptype |=
12238 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12239 ptype_mapping[i].sw_ptype |=
12241 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12243 ptype_mapping[i].sw_ptype |=
12244 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12245 ptype_mapping[i].sw_ptype |=
12246 RTE_PTYPE_INNER_L4_FRAG;
12247 } else if (!strncasecmp(name, "OIPV4", 5)) {
12248 ptype_mapping[i].sw_ptype |=
12249 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12251 } else if (!strncasecmp(name, "IPV4", 4) &&
12253 ptype_mapping[i].sw_ptype |=
12254 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12255 else if (!strncasecmp(name, "IPV4", 4) &&
12257 ptype_mapping[i].sw_ptype |=
12258 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12259 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12261 ptype_mapping[i].sw_ptype |=
12262 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12263 ptype_mapping[i].sw_ptype |=
12265 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12267 ptype_mapping[i].sw_ptype |=
12268 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12269 ptype_mapping[i].sw_ptype |=
12270 RTE_PTYPE_INNER_L4_FRAG;
12271 } else if (!strncasecmp(name, "OIPV6", 5)) {
12272 ptype_mapping[i].sw_ptype |=
12273 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12275 } else if (!strncasecmp(name, "IPV6", 4) &&
12277 ptype_mapping[i].sw_ptype |=
12278 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12279 else if (!strncasecmp(name, "IPV6", 4) &&
12281 ptype_mapping[i].sw_ptype |=
12282 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12283 else if (!strncasecmp(name, "UDP", 3) &&
12285 ptype_mapping[i].sw_ptype |=
12287 else if (!strncasecmp(name, "UDP", 3) &&
12289 ptype_mapping[i].sw_ptype |=
12290 RTE_PTYPE_INNER_L4_UDP;
12291 else if (!strncasecmp(name, "TCP", 3) &&
12293 ptype_mapping[i].sw_ptype |=
12295 else if (!strncasecmp(name, "TCP", 3) &&
12297 ptype_mapping[i].sw_ptype |=
12298 RTE_PTYPE_INNER_L4_TCP;
12299 else if (!strncasecmp(name, "SCTP", 4) &&
12301 ptype_mapping[i].sw_ptype |=
12303 else if (!strncasecmp(name, "SCTP", 4) &&
12305 ptype_mapping[i].sw_ptype |=
12306 RTE_PTYPE_INNER_L4_SCTP;
12307 else if ((!strncasecmp(name, "ICMP", 4) ||
12308 !strncasecmp(name, "ICMPV6", 6)) &&
12310 ptype_mapping[i].sw_ptype |=
12312 else if ((!strncasecmp(name, "ICMP", 4) ||
12313 !strncasecmp(name, "ICMPV6", 6)) &&
12315 ptype_mapping[i].sw_ptype |=
12316 RTE_PTYPE_INNER_L4_ICMP;
12317 else if (!strncasecmp(name, "GTPC", 4)) {
12318 ptype_mapping[i].sw_ptype |=
12319 RTE_PTYPE_TUNNEL_GTPC;
12321 } else if (!strncasecmp(name, "GTPU", 4)) {
12322 ptype_mapping[i].sw_ptype |=
12323 RTE_PTYPE_TUNNEL_GTPU;
12325 } else if (!strncasecmp(name, "GRENAT", 6)) {
12326 ptype_mapping[i].sw_ptype |=
12327 RTE_PTYPE_TUNNEL_GRENAT;
12329 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12330 !strncasecmp(name, "L2TPV2", 6)) {
12331 ptype_mapping[i].sw_ptype |=
12332 RTE_PTYPE_TUNNEL_L2TP;
12341 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12344 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12346 rte_free(ptype_mapping);
12352 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12353 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12356 uint32_t proto_num;
12357 struct rte_pmd_i40e_proto_info *proto;
12358 uint32_t buff_size;
12362 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12363 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12364 PMD_DRV_LOG(ERR, "Unsupported operation.");
12368 /* get information about protocol number */
12369 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12370 (uint8_t *)&proto_num, sizeof(proto_num),
12371 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12373 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12377 PMD_DRV_LOG(INFO, "No new protocol added");
12381 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12382 proto = rte_zmalloc("new_proto", buff_size, 0);
12384 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12388 /* get information about protocol list */
12389 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12390 (uint8_t *)proto, buff_size,
12391 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12393 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12398 /* Check if GTP is supported. */
12399 for (i = 0; i < proto_num; i++) {
12400 if (!strncmp(proto[i].name, "GTP", 3)) {
12401 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12402 pf->gtp_support = true;
12404 pf->gtp_support = false;
12409 /* Update customized pctype info */
12410 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12411 proto_num, proto, op);
12413 PMD_DRV_LOG(INFO, "No pctype is updated.");
12415 /* Update customized ptype info */
12416 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12417 proto_num, proto, op);
12419 PMD_DRV_LOG(INFO, "No ptype is updated.");
12424 /* Create a QinQ cloud filter
12426 * The Fortville NIC has limited resources for tunnel filters,
12427 * so we can only reuse existing filters.
12429 * In step 1 we define which Field Vector fields can be used for
12431 * As we do not have the inner tag defined as a field,
12432 * we have to define it first, by reusing one of L1 entries.
12434 * In step 2 we are replacing one of existing filter types with
12435 * a new one for QinQ.
12436 * As we reusing L1 and replacing L2, some of the default filter
12437 * types will disappear,which depends on L1 and L2 entries we reuse.
12439 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12441 * 1. Create L1 filter of outer vlan (12b) which will be in use
12442 * later when we define the cloud filter.
12443 * a. Valid_flags.replace_cloud = 0
12444 * b. Old_filter = 10 (Stag_Inner_Vlan)
12445 * c. New_filter = 0x10
12446 * d. TR bit = 0xff (optional, not used here)
12447 * e. Buffer – 2 entries:
12448 * i. Byte 0 = 8 (outer vlan FV index).
12450 * Byte 2-3 = 0x0fff
12451 * ii. Byte 0 = 37 (inner vlan FV index).
12453 * Byte 2-3 = 0x0fff
12456 * 2. Create cloud filter using two L1 filters entries: stag and
12457 * new filter(outer vlan+ inner vlan)
12458 * a. Valid_flags.replace_cloud = 1
12459 * b. Old_filter = 1 (instead of outer IP)
12460 * c. New_filter = 0x10
12461 * d. Buffer – 2 entries:
12462 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12463 * Byte 1-3 = 0 (rsv)
12464 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12465 * Byte 9-11 = 0 (rsv)
12468 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12470 int ret = -ENOTSUP;
12471 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12472 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12473 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12474 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12476 if (pf->support_multi_driver) {
12477 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12482 memset(&filter_replace, 0,
12483 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12484 memset(&filter_replace_buf, 0,
12485 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12487 /* create L1 filter */
12488 filter_replace.old_filter_type =
12489 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12490 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12491 filter_replace.tr_bit = 0;
12493 /* Prepare the buffer, 2 entries */
12494 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12495 filter_replace_buf.data[0] |=
12496 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12497 /* Field Vector 12b mask */
12498 filter_replace_buf.data[2] = 0xff;
12499 filter_replace_buf.data[3] = 0x0f;
12500 filter_replace_buf.data[4] =
12501 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12502 filter_replace_buf.data[4] |=
12503 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12504 /* Field Vector 12b mask */
12505 filter_replace_buf.data[6] = 0xff;
12506 filter_replace_buf.data[7] = 0x0f;
12507 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12508 &filter_replace_buf);
12509 if (ret != I40E_SUCCESS)
12512 if (filter_replace.old_filter_type !=
12513 filter_replace.new_filter_type)
12514 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12515 " original: 0x%x, new: 0x%x",
12517 filter_replace.old_filter_type,
12518 filter_replace.new_filter_type);
12520 /* Apply the second L2 cloud filter */
12521 memset(&filter_replace, 0,
12522 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12523 memset(&filter_replace_buf, 0,
12524 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12526 /* create L2 filter, input for L2 filter will be L1 filter */
12527 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12528 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12529 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12531 /* Prepare the buffer, 2 entries */
12532 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12533 filter_replace_buf.data[0] |=
12534 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12535 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12536 filter_replace_buf.data[4] |=
12537 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12538 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12539 &filter_replace_buf);
12540 if (!ret && (filter_replace.old_filter_type !=
12541 filter_replace.new_filter_type))
12542 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12543 " original: 0x%x, new: 0x%x",
12545 filter_replace.old_filter_type,
12546 filter_replace.new_filter_type);
12552 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12553 const struct rte_flow_action_rss *in)
12555 if (in->key_len > RTE_DIM(out->key) ||
12556 in->queue_num > RTE_DIM(out->queue))
12558 out->conf = (struct rte_flow_action_rss){
12560 .level = in->level,
12561 .types = in->types,
12562 .key_len = in->key_len,
12563 .queue_num = in->queue_num,
12564 .key = memcpy(out->key, in->key, in->key_len),
12565 .queue = memcpy(out->queue, in->queue,
12566 sizeof(*in->queue) * in->queue_num),
12572 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12573 const struct rte_flow_action_rss *with)
12575 return (comp->func == with->func &&
12576 comp->level == with->level &&
12577 comp->types == with->types &&
12578 comp->key_len == with->key_len &&
12579 comp->queue_num == with->queue_num &&
12580 !memcmp(comp->key, with->key, with->key_len) &&
12581 !memcmp(comp->queue, with->queue,
12582 sizeof(*with->queue) * with->queue_num));
12586 i40e_config_rss_filter(struct i40e_pf *pf,
12587 struct i40e_rte_flow_rss_conf *conf, bool add)
12589 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12590 uint32_t i, lut = 0;
12592 struct rte_eth_rss_conf rss_conf = {
12593 .rss_key = conf->conf.key_len ?
12594 (void *)(uintptr_t)conf->conf.key : NULL,
12595 .rss_key_len = conf->conf.key_len,
12596 .rss_hf = conf->conf.types,
12598 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12601 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12602 i40e_pf_disable_rss(pf);
12603 memset(rss_info, 0,
12604 sizeof(struct i40e_rte_flow_rss_conf));
12610 if (rss_info->conf.queue_num)
12613 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12614 * It's necessary to calculate the actual PF queues that are configured.
12616 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12617 num = i40e_pf_calc_configured_queues_num(pf);
12619 num = pf->dev_data->nb_rx_queues;
12621 num = RTE_MIN(num, conf->conf.queue_num);
12622 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12626 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12630 /* Fill in redirection table */
12631 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12634 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12635 hw->func_caps.rss_table_entry_width) - 1));
12637 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12640 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12641 i40e_pf_disable_rss(pf);
12644 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12645 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12646 /* Random default keys */
12647 static uint32_t rss_key_default[] = {0x6b793944,
12648 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12649 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12650 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12652 rss_conf.rss_key = (uint8_t *)rss_key_default;
12653 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12657 i40e_hw_rss_hash_set(pf, &rss_conf);
12659 if (i40e_rss_conf_init(rss_info, &conf->conf))
12665 RTE_INIT(i40e_init_log)
12667 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12668 if (i40e_logtype_init >= 0)
12669 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12670 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12671 if (i40e_logtype_driver >= 0)
12672 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12675 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12676 ETH_I40E_FLOATING_VEB_ARG "=1"
12677 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12678 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12679 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12680 ETH_I40E_USE_LATEST_VEC "=0|1");