drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 110 static int i40e_dev_configure(struct rte_eth_dev *dev);
 111 static int i40e_dev_start(struct rte_eth_dev *dev);
 112 static void i40e_dev_stop(struct rte_eth_dev *dev);
 113 static void i40e_dev_close(struct rte_eth_dev *dev);
 114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 121                                struct rte_eth_stats *stats);
 122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 124                                             uint16_t queue_id,
 125                                             uint8_t stat_idx,
 126                                             uint8_t is_rx);
 127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 128                               struct rte_eth_dev_info *dev_info);
 129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 130                                 uint16_t vlan_id,
 131                                 int on);
 132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 135                                       uint16_t queue,
 136                                       int on);
 137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 141                               struct rte_eth_fc_conf *fc_conf);
 142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                        struct rte_eth_pfc_conf *pfc_conf);
 144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 145                           struct ether_addr *mac_addr,
 146                           uint32_t index,
 147                           uint32_t pool);
 148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 150                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                     uint16_t reta_size);
 152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 153                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 154                                    uint16_t reta_size);
 155
 156 static int i40e_get_cap(struct i40e_hw *hw);
 157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 158 static int i40e_pf_setup(struct i40e_pf *pf);
 159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 162                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 163 static void i40e_stat_update_48(struct i40e_hw *hw,
 164                                uint32_t hireg,
 165                                uint32_t loreg,
 166                                bool offset_loaded,
 167                                uint64_t *offset,
 168                                uint64_t *stat);
 169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 170 static void i40e_dev_interrupt_handler(
 171                 __rte_unused struct rte_intr_handle *handle, void *param);
 172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 173                                 uint32_t base, uint32_t num);
 174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 176                         uint32_t base);
 177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 178                         uint16_t num);
 179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 180 static int i40e_veb_release(struct i40e_veb *veb);
 181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 182                                                 struct i40e_vsi *vsi);
 183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 186                                              struct i40e_macvlan_filter *mv_f,
 187                                              int num,
 188                                              struct ether_addr *addr);
 189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 190                                              struct i40e_macvlan_filter *mv_f,
 191                                              int num,
 192                                              uint16_t vlan);
 193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 195                                     struct rte_eth_rss_conf *rss_conf);
 196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 197                                       struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 199                                 struct rte_eth_udp_tunnel *udp_tunnel);
 200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 203                         struct rte_eth_ethertype_filter *filter,
 204                         bool add);
 205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 206                                 enum rte_filter_op filter_op,
 207                                 void *arg);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static void i40e_configure_registers(struct i40e_hw *hw);
 213 static void i40e_hw_init(struct i40e_hw *hw);
 214 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 215 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 216                         struct rte_eth_mirror_conf *mirror_conf,
 217                         uint8_t sw_id, uint8_t on);
 218 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 219
 220 static const struct rte_pci_id pci_id_i40e_map[] = {
 221 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 222 #include "rte_pci_dev_ids.h"
 223 { .vendor_id = 0, /* sentinel */ },
 224 };
 225
 226 static const struct eth_dev_ops i40e_eth_dev_ops = {
 227         .dev_configure                = i40e_dev_configure,
 228         .dev_start                    = i40e_dev_start,
 229         .dev_stop                     = i40e_dev_stop,
 230         .dev_close                    = i40e_dev_close,
 231         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 232         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 233         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 234         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 235         .dev_set_link_up              = i40e_dev_set_link_up,
 236         .dev_set_link_down            = i40e_dev_set_link_down,
 237         .link_update                  = i40e_dev_link_update,
 238         .stats_get                    = i40e_dev_stats_get,
 239         .stats_reset                  = i40e_dev_stats_reset,
 240         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 241         .dev_infos_get                = i40e_dev_info_get,
 242         .vlan_filter_set              = i40e_vlan_filter_set,
 243         .vlan_tpid_set                = i40e_vlan_tpid_set,
 244         .vlan_offload_set             = i40e_vlan_offload_set,
 245         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 246         .vlan_pvid_set                = i40e_vlan_pvid_set,
 247         .rx_queue_start               = i40e_dev_rx_queue_start,
 248         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 249         .tx_queue_start               = i40e_dev_tx_queue_start,
 250         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 251         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 252         .rx_queue_release             = i40e_dev_rx_queue_release,
 253         .rx_queue_count               = i40e_dev_rx_queue_count,
 254         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 255         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 256         .tx_queue_release             = i40e_dev_tx_queue_release,
 257         .dev_led_on                   = i40e_dev_led_on,
 258         .dev_led_off                  = i40e_dev_led_off,
 259         .flow_ctrl_set                = i40e_flow_ctrl_set,
 260         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 261         .mac_addr_add                 = i40e_macaddr_add,
 262         .mac_addr_remove              = i40e_macaddr_remove,
 263         .reta_update                  = i40e_dev_rss_reta_update,
 264         .reta_query                   = i40e_dev_rss_reta_query,
 265         .rss_hash_update              = i40e_dev_rss_hash_update,
 266         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 267         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 268         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 269         .filter_ctrl                  = i40e_dev_filter_ctrl,
 270         .mirror_rule_set              = i40e_mirror_rule_set,
 271         .mirror_rule_reset            = i40e_mirror_rule_reset,
 272 };
 273
 274 static struct eth_driver rte_i40e_pmd = {
 275         .pci_drv = {
 276                 .name = "rte_i40e_pmd",
 277                 .id_table = pci_id_i40e_map,
 278                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 279         },
 280         .eth_dev_init = eth_i40e_dev_init,
 281         .dev_private_size = sizeof(struct i40e_adapter),
 282 };
 283
 284 static inline int
 285 i40e_align_floor(int n)
 286 {
 287         if (n == 0)
 288                 return 0;
 289         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 290 }
 291
 292 static inline int
 293 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 294                                      struct rte_eth_link *link)
 295 {
 296         struct rte_eth_link *dst = link;
 297         struct rte_eth_link *src = &(dev->data->dev_link);
 298
 299         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 300                                         *(uint64_t *)src) == 0)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 static inline int
 307 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 308                                       struct rte_eth_link *link)
 309 {
 310         struct rte_eth_link *dst = &(dev->data->dev_link);
 311         struct rte_eth_link *src = link;
 312
 313         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 314                                         *(uint64_t *)src) == 0)
 315                 return -1;
 316
 317         return 0;
 318 }
 319
 320 /*
 321  * Driver initialization routine.
 322  * Invoked once at EAL init time.
 323  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 324  */
 325 static int
 326 rte_i40e_pmd_init(const char *name __rte_unused,
 327                   const char *params __rte_unused)
 328 {
 329         PMD_INIT_FUNC_TRACE();
 330         rte_eth_driver_register(&rte_i40e_pmd);
 331
 332         return 0;
 333 }
 334
 335 static struct rte_driver rte_i40e_driver = {
 336         .type = PMD_PDEV,
 337         .init = rte_i40e_pmd_init,
 338 };
 339
 340 PMD_REGISTER_DRIVER(rte_i40e_driver);
 341
 342 /*
 343  * Initialize registers for flexible payload, which should be set by NVM.
 344  * This should be removed from code once it is fixed in NVM.
 345  */
 346 #ifndef I40E_GLQF_ORT
 347 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 348 #endif
 349 #ifndef I40E_GLQF_PIT
 350 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 351 #endif
 352
 353 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 354 {
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 359         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 360         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 361         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 362         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 363         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 364         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 365
 366         /* GLQF_PIT Registers */
 367         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 368         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 369 }
 370
 371 static int
 372 eth_i40e_dev_init(struct rte_eth_dev *dev)
 373 {
 374         struct rte_pci_device *pci_dev;
 375         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 376         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 377         struct i40e_vsi *vsi;
 378         int ret;
 379         uint32_t len;
 380         uint8_t aq_fail = 0;
 381
 382         PMD_INIT_FUNC_TRACE();
 383
 384         dev->dev_ops = &i40e_eth_dev_ops;
 385         dev->rx_pkt_burst = i40e_recv_pkts;
 386         dev->tx_pkt_burst = i40e_xmit_pkts;
 387
 388         /* for secondary processes, we don't initialise any further as primary
 389          * has already done this work. Only check we don't need a different
 390          * RX function */
 391         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 392                 if (dev->data->scattered_rx)
 393                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 394                 return 0;
 395         }
 396         pci_dev = dev->pci_dev;
 397         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 398         pf->adapter->eth_dev = dev;
 399         pf->dev_data = dev->data;
 400
 401         hw->back = I40E_PF_TO_ADAPTER(pf);
 402         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 403         if (!hw->hw_addr) {
 404                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 405                              "as address is NULL");
 406                 return -ENODEV;
 407         }
 408
 409         hw->vendor_id = pci_dev->id.vendor_id;
 410         hw->device_id = pci_dev->id.device_id;
 411         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 412         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 413         hw->bus.device = pci_dev->addr.devid;
 414         hw->bus.func = pci_dev->addr.function;
 415
 416         /* Make sure all is clean before doing PF reset */
 417         i40e_clear_hw(hw);
 418
 419         /* Initialize the hardware */
 420         i40e_hw_init(hw);
 421
 422         /* Reset here to make sure all is clean for each PF */
 423         ret = i40e_pf_reset(hw);
 424         if (ret) {
 425                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 426                 return ret;
 427         }
 428
 429         /* Initialize the shared code (base driver) */
 430         ret = i40e_init_shared_code(hw);
 431         if (ret) {
 432                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 433                 return ret;
 434         }
 435
 436         /*
 437          * To work around the NVM issue,initialize registers
 438          * for flexible payload by software.
 439          * It should be removed once issues are fixed in NVM.
 440          */
 441         i40e_flex_payload_reg_init(hw);
 442
 443         /* Initialize the parameters for adminq */
 444         i40e_init_adminq_parameter(hw);
 445         ret = i40e_init_adminq(hw);
 446         if (ret != I40E_SUCCESS) {
 447                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 448                 return -EIO;
 449         }
 450         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 451                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 452                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 453                      ((hw->nvm.version >> 12) & 0xf),
 454                      ((hw->nvm.version >> 4) & 0xff),
 455                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 456
 457         /* Disable LLDP */
 458         ret = i40e_aq_stop_lldp(hw, true, NULL);
 459         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 460                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 461
 462         /* Clear PXE mode */
 463         i40e_clear_pxe_mode(hw);
 464
 465         /*
 466          * On X710, performance number is far from the expectation on recent
 467          * firmware versions. The fix for this issue may not be integrated in
 468          * the following firmware version. So the workaround in software driver
 469          * is needed. It needs to modify the initial values of 3 internal only
 470          * registers. Note that the workaround can be removed when it is fixed
 471          * in firmware in the future.
 472          */
 473         i40e_configure_registers(hw);
 474
 475         /* Get hw capabilities */
 476         ret = i40e_get_cap(hw);
 477         if (ret != I40E_SUCCESS) {
 478                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 479                 goto err_get_capabilities;
 480         }
 481
 482         /* Initialize parameters for PF */
 483         ret = i40e_pf_parameter_init(dev);
 484         if (ret != 0) {
 485                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 486                 goto err_parameter_init;
 487         }
 488
 489         /* Initialize the queue management */
 490         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 491         if (ret < 0) {
 492                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 493                 goto err_qp_pool_init;
 494         }
 495         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 496                                 hw->func_caps.num_msix_vectors - 1);
 497         if (ret < 0) {
 498                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 499                 goto err_msix_pool_init;
 500         }
 501
 502         /* Initialize lan hmc */
 503         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 504                                 hw->func_caps.num_rx_qp, 0, 0);
 505         if (ret != I40E_SUCCESS) {
 506                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 507                 goto err_init_lan_hmc;
 508         }
 509
 510         /* Configure lan hmc */
 511         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 512         if (ret != I40E_SUCCESS) {
 513                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 514                 goto err_configure_lan_hmc;
 515         }
 516
 517         /* Get and check the mac address */
 518         i40e_get_mac_addr(hw, hw->mac.addr);
 519         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 520                 PMD_INIT_LOG(ERR, "mac address is not valid");
 521                 ret = -EIO;
 522                 goto err_get_mac_addr;
 523         }
 524         /* Copy the permanent MAC address */
 525         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 526                         (struct ether_addr *) hw->mac.perm_addr);
 527
 528         /* Disable flow control */
 529         hw->fc.requested_mode = I40E_FC_NONE;
 530         i40e_set_fc(hw, &aq_fail, TRUE);
 531
 532         /* PF setup, which includes VSI setup */
 533         ret = i40e_pf_setup(pf);
 534         if (ret) {
 535                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 536                 goto err_setup_pf_switch;
 537         }
 538
 539         vsi = pf->main_vsi;
 540
 541         /* Disable double vlan by default */
 542         i40e_vsi_config_double_vlan(vsi, FALSE);
 543
 544         if (!vsi->max_macaddrs)
 545                 len = ETHER_ADDR_LEN;
 546         else
 547                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 548
 549         /* Should be after VSI initialized */
 550         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 551         if (!dev->data->mac_addrs) {
 552                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 553                                         "for storing mac address");
 554                 goto err_mac_alloc;
 555         }
 556         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 557                                         &dev->data->mac_addrs[0]);
 558
 559         /* initialize pf host driver to setup SRIOV resource if applicable */
 560         i40e_pf_host_init(dev);
 561
 562         /* register callback func to eal lib */
 563         rte_intr_callback_register(&(pci_dev->intr_handle),
 564                 i40e_dev_interrupt_handler, (void *)dev);
 565
 566         /* configure and enable device interrupt */
 567         i40e_pf_config_irq0(hw);
 568         i40e_pf_enable_irq0(hw);
 569
 570         /* enable uio intr after callback register */
 571         rte_intr_enable(&(pci_dev->intr_handle));
 572
 573         /* initialize mirror rule list */
 574         TAILQ_INIT(&pf->mirror_list);
 575
 576         return 0;
 577
 578 err_mac_alloc:
 579         i40e_vsi_release(pf->main_vsi);
 580 err_setup_pf_switch:
 581 err_get_mac_addr:
 582 err_configure_lan_hmc:
 583         (void)i40e_shutdown_lan_hmc(hw);
 584 err_init_lan_hmc:
 585         i40e_res_pool_destroy(&pf->msix_pool);
 586 err_msix_pool_init:
 587         i40e_res_pool_destroy(&pf->qp_pool);
 588 err_qp_pool_init:
 589 err_parameter_init:
 590 err_get_capabilities:
 591         (void)i40e_shutdown_adminq(hw);
 592
 593         return ret;
 594 }
 595
 596 static int
 597 i40e_dev_configure(struct rte_eth_dev *dev)
 598 {
 599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 600         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 601         int ret;
 602
 603         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 604                 ret = i40e_fdir_setup(pf);
 605                 if (ret != I40E_SUCCESS) {
 606                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 607                         return -ENOTSUP;
 608                 }
 609                 ret = i40e_fdir_configure(dev);
 610                 if (ret < 0) {
 611                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 612                         goto err;
 613                 }
 614         } else
 615                 i40e_fdir_teardown(pf);
 616
 617         ret = i40e_dev_init_vlan(dev);
 618         if (ret < 0)
 619                 goto err;
 620
 621         /* VMDQ setup.
 622          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 623          *  RSS setting have different requirements.
 624          *  General PMD driver call sequence are NIC init, configure,
 625          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 626          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 627          *  applicable. So, VMDQ setting has to be done before
 628          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 629          *  For RSS setting, it will try to calculate actual configured RX queue
 630          *  number, which will be available after rx_queue_setup(). dev_start()
 631          *  function is good to place RSS setup.
 632          */
 633         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 634                 ret = i40e_vmdq_setup(dev);
 635                 if (ret)
 636                         goto err;
 637         }
 638         return 0;
 639 err:
 640         i40e_fdir_teardown(pf);
 641         return ret;
 642 }
 643
 644 void
 645 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 646 {
 647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 648         uint16_t msix_vect = vsi->msix_intr;
 649         uint16_t i;
 650
 651         for (i = 0; i < vsi->nb_qps; i++) {
 652                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 653                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 654                 rte_wmb();
 655         }
 656
 657         if (vsi->type != I40E_VSI_SRIOV) {
 658                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 659                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 660                                 msix_vect - 1), 0);
 661         } else {
 662                 uint32_t reg;
 663                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 664                         vsi->user_param + (msix_vect - 1);
 665
 666                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 667         }
 668         I40E_WRITE_FLUSH(hw);
 669 }
 670
 671 static inline uint16_t
 672 i40e_calc_itr_interval(int16_t interval)
 673 {
 674         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 675                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 676
 677         /* Convert to hardware count, as writing each 1 represents 2 us */
 678         return (interval/2);
 679 }
 680
 681 void
 682 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 683 {
 684         uint32_t val;
 685         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 686         uint16_t msix_vect = vsi->msix_intr;
 687         int i;
 688
 689         for (i = 0; i < vsi->nb_qps; i++)
 690                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 691
 692         /* Bind all RX queues to allocated MSIX interrupt */
 693         for (i = 0; i < vsi->nb_qps; i++) {
 694                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 695                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 696                         ((vsi->base_queue + i + 1) <<
 697                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 698                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 699                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 700
 701                 if (i == vsi->nb_qps - 1)
 702                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 703                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 704         }
 705
 706         /* Write first RX queue to Link list register as the head element */
 707         if (vsi->type != I40E_VSI_SRIOV) {
 708                 uint16_t interval =
 709                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 710
 711                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 712                                                 (vsi->base_queue <<
 713                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 714                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 715
 716                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 717                                                 msix_vect - 1), interval);
 718
 719 #ifndef I40E_GLINT_CTL
 720 #define I40E_GLINT_CTL                     0x0003F800
 721 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 722 #endif
 723                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 724                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 725                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 726         } else {
 727                 uint32_t reg;
 728
 729                 /* num_msix_vectors_vf needs to minus irq0 */
 730                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 731                         vsi->user_param + (msix_vect - 1);
 732
 733                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 734                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 735                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 736         }
 737
 738         I40E_WRITE_FLUSH(hw);
 739 }
 740
 741 static void
 742 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 743 {
 744         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 745         uint16_t interval = i40e_calc_itr_interval(\
 746                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 747
 748         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 749                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 750                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 751                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 752                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 753 }
 754
 755 static void
 756 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 757 {
 758         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 759
 760         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 761 }
 762
 763 static inline uint8_t
 764 i40e_parse_link_speed(uint16_t eth_link_speed)
 765 {
 766         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 767
 768         switch (eth_link_speed) {
 769         case ETH_LINK_SPEED_40G:
 770                 link_speed = I40E_LINK_SPEED_40GB;
 771                 break;
 772         case ETH_LINK_SPEED_20G:
 773                 link_speed = I40E_LINK_SPEED_20GB;
 774                 break;
 775         case ETH_LINK_SPEED_10G:
 776                 link_speed = I40E_LINK_SPEED_10GB;
 777                 break;
 778         case ETH_LINK_SPEED_1000:
 779                 link_speed = I40E_LINK_SPEED_1GB;
 780                 break;
 781         case ETH_LINK_SPEED_100:
 782                 link_speed = I40E_LINK_SPEED_100MB;
 783                 break;
 784         }
 785
 786         return link_speed;
 787 }
 788
 789 static int
 790 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 791 {
 792         enum i40e_status_code status;
 793         struct i40e_aq_get_phy_abilities_resp phy_ab;
 794         struct i40e_aq_set_phy_config phy_conf;
 795         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 796                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 797                         I40E_AQ_PHY_FLAG_LOW_POWER;
 798         const uint8_t advt = I40E_LINK_SPEED_40GB |
 799                         I40E_LINK_SPEED_10GB |
 800                         I40E_LINK_SPEED_1GB |
 801                         I40E_LINK_SPEED_100MB;
 802         int ret = -ENOTSUP;
 803
 804         /* Skip it on 40G interfaces, as a workaround for the link issue */
 805         if (i40e_is_40G_device(hw->device_id))
 806                 return I40E_SUCCESS;
 807
 808         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 809                                               NULL);
 810         if (status)
 811                 return ret;
 812
 813         memset(&phy_conf, 0, sizeof(phy_conf));
 814
 815         /* bits 0-2 use the values from get_phy_abilities_resp */
 816         abilities &= ~mask;
 817         abilities |= phy_ab.abilities & mask;
 818
 819         /* update ablities and speed */
 820         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 821                 phy_conf.link_speed = advt;
 822         else
 823                 phy_conf.link_speed = force_speed;
 824
 825         phy_conf.abilities = abilities;
 826
 827         /* use get_phy_abilities_resp value for the rest */
 828         phy_conf.phy_type = phy_ab.phy_type;
 829         phy_conf.eee_capability = phy_ab.eee_capability;
 830         phy_conf.eeer = phy_ab.eeer_val;
 831         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 832
 833         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 834                     phy_ab.abilities, phy_ab.link_speed);
 835         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 836                     phy_conf.abilities, phy_conf.link_speed);
 837
 838         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 839         if (status)
 840                 return ret;
 841
 842         return I40E_SUCCESS;
 843 }
 844
 845 static int
 846 i40e_apply_link_speed(struct rte_eth_dev *dev)
 847 {
 848         uint8_t speed;
 849         uint8_t abilities = 0;
 850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 851         struct rte_eth_conf *conf = &dev->data->dev_conf;
 852
 853         speed = i40e_parse_link_speed(conf->link_speed);
 854         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 855         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 856                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 857         else
 858                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 859
 860         return i40e_phy_conf_link(hw, abilities, speed);
 861 }
 862
 863 static int
 864 i40e_dev_start(struct rte_eth_dev *dev)
 865 {
 866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 868         struct i40e_vsi *main_vsi = pf->main_vsi;
 869         int ret, i;
 870
 871         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 872                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 873                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 874                              dev->data->dev_conf.link_duplex,
 875                              dev->data->port_id);
 876                 return -EINVAL;
 877         }
 878
 879         /* Initialize VSI */
 880         ret = i40e_dev_rxtx_init(pf);
 881         if (ret != I40E_SUCCESS) {
 882                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 883                 goto err_up;
 884         }
 885
 886         /* Map queues with MSIX interrupt */
 887         i40e_vsi_queues_bind_intr(main_vsi);
 888         i40e_vsi_enable_queues_intr(main_vsi);
 889
 890         /* Map VMDQ VSI queues with MSIX interrupt */
 891         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 892                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 893                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 894         }
 895
 896         /* enable FDIR MSIX interrupt */
 897         if (pf->fdir.fdir_vsi) {
 898                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 899                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 900         }
 901
 902         /* Enable all queues which have been configured */
 903         ret = i40e_dev_switch_queues(pf, TRUE);
 904         if (ret != I40E_SUCCESS) {
 905                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 906                 goto err_up;
 907         }
 908
 909         /* Enable receiving broadcast packets */
 910         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 911         if (ret != I40E_SUCCESS)
 912                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 913
 914         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 915                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 916                                                 true, NULL);
 917                 if (ret != I40E_SUCCESS)
 918                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 919         }
 920
 921         /* Apply link configure */
 922         ret = i40e_apply_link_speed(dev);
 923         if (I40E_SUCCESS != ret) {
 924                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 925                 goto err_up;
 926         }
 927
 928         return I40E_SUCCESS;
 929
 930 err_up:
 931         i40e_dev_switch_queues(pf, FALSE);
 932         i40e_dev_clear_queues(dev);
 933
 934         return ret;
 935 }
 936
 937 static void
 938 i40e_dev_stop(struct rte_eth_dev *dev)
 939 {
 940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 941         struct i40e_vsi *main_vsi = pf->main_vsi;
 942         struct i40e_mirror_rule *p_mirror;
 943         int i;
 944
 945         /* Disable all queues */
 946         i40e_dev_switch_queues(pf, FALSE);
 947
 948         /* un-map queues with interrupt registers */
 949         i40e_vsi_disable_queues_intr(main_vsi);
 950         i40e_vsi_queues_unbind_intr(main_vsi);
 951
 952         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 953                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 954                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 955         }
 956
 957         if (pf->fdir.fdir_vsi) {
 958                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 959                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 960         }
 961         /* Clear all queues and release memory */
 962         i40e_dev_clear_queues(dev);
 963
 964         /* Set link down */
 965         i40e_dev_set_link_down(dev);
 966
 967         /* Remove all mirror rules */
 968         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
 969                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
 970                 rte_free(p_mirror);
 971         }
 972         pf->nb_mirror_rule = 0;
 973
 974 }
 975
 976 static void
 977 i40e_dev_close(struct rte_eth_dev *dev)
 978 {
 979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 980         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         uint32_t reg;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         i40e_dev_stop(dev);
 986
 987         /* Disable interrupt */
 988         i40e_pf_disable_irq0(hw);
 989         rte_intr_disable(&(dev->pci_dev->intr_handle));
 990
 991         /* shutdown and destroy the HMC */
 992         i40e_shutdown_lan_hmc(hw);
 993
 994         /* release all the existing VSIs and VEBs */
 995         i40e_fdir_teardown(pf);
 996         i40e_vsi_release(pf->main_vsi);
 997
 998         /* shutdown the adminq */
 999         i40e_aq_queue_shutdown(hw, true);
1000         i40e_shutdown_adminq(hw);
1001
1002         i40e_res_pool_destroy(&pf->qp_pool);
1003         i40e_res_pool_destroy(&pf->msix_pool);
1004
1005         /* force a PF reset to clean anything leftover */
1006         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1007         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1008                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1009         I40E_WRITE_FLUSH(hw);
1010 }
1011
1012 static void
1013 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1014 {
1015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct i40e_vsi *vsi = pf->main_vsi;
1018         int status;
1019
1020         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1021                                                         true, NULL);
1022         if (status != I40E_SUCCESS)
1023                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1024
1025         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1026                                                         TRUE, NULL);
1027         if (status != I40E_SUCCESS)
1028                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1029
1030 }
1031
1032 static void
1033 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi = pf->main_vsi;
1038         int status;
1039
1040         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1041                                                         false, NULL);
1042         if (status != I40E_SUCCESS)
1043                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1044
1045         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1046                                                         false, NULL);
1047         if (status != I40E_SUCCESS)
1048                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1049 }
1050
1051 static void
1052 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1053 {
1054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         struct i40e_vsi *vsi = pf->main_vsi;
1057         int ret;
1058
1059         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1060         if (ret != I40E_SUCCESS)
1061                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1062 }
1063
1064 static void
1065 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1066 {
1067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1069         struct i40e_vsi *vsi = pf->main_vsi;
1070         int ret;
1071
1072         if (dev->data->promiscuous == 1)
1073                 return; /* must remain in all_multicast mode */
1074
1075         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1076                                 vsi->seid, FALSE, NULL);
1077         if (ret != I40E_SUCCESS)
1078                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1079 }
1080
1081 /*
1082  * Set device link up.
1083  */
1084 static int
1085 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1086 {
1087         /* re-apply link speed setting */
1088         return i40e_apply_link_speed(dev);
1089 }
1090
1091 /*
1092  * Set device link down.
1093  */
1094 static int
1095 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1096 {
1097         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1098         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100
1101         return i40e_phy_conf_link(hw, abilities, speed);
1102 }
1103
1104 int
1105 i40e_dev_link_update(struct rte_eth_dev *dev,
1106                      int wait_to_complete)
1107 {
1108 #define CHECK_INTERVAL 100  /* 100ms */
1109 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         struct i40e_link_status link_status;
1112         struct rte_eth_link link, old;
1113         int status;
1114         unsigned rep_cnt = MAX_REPEAT_TIME;
1115
1116         memset(&link, 0, sizeof(link));
1117         memset(&old, 0, sizeof(old));
1118         memset(&link_status, 0, sizeof(link_status));
1119         rte_i40e_dev_atomic_read_link_status(dev, &old);
1120
1121         do {
1122                 /* Get link status information from hardware */
1123                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1124                 if (status != I40E_SUCCESS) {
1125                         link.link_speed = ETH_LINK_SPEED_100;
1126                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1127                         PMD_DRV_LOG(ERR, "Failed to get link info");
1128                         goto out;
1129                 }
1130
1131                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1132                 if (!wait_to_complete)
1133                         break;
1134
1135                 rte_delay_ms(CHECK_INTERVAL);
1136         } while (!link.link_status && rep_cnt--);
1137
1138         if (!link.link_status)
1139                 goto out;
1140
1141         /* i40e uses full duplex only */
1142         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1143
1144         /* Parse the link status */
1145         switch (link_status.link_speed) {
1146         case I40E_LINK_SPEED_100MB:
1147                 link.link_speed = ETH_LINK_SPEED_100;
1148                 break;
1149         case I40E_LINK_SPEED_1GB:
1150                 link.link_speed = ETH_LINK_SPEED_1000;
1151                 break;
1152         case I40E_LINK_SPEED_10GB:
1153                 link.link_speed = ETH_LINK_SPEED_10G;
1154                 break;
1155         case I40E_LINK_SPEED_20GB:
1156                 link.link_speed = ETH_LINK_SPEED_20G;
1157                 break;
1158         case I40E_LINK_SPEED_40GB:
1159                 link.link_speed = ETH_LINK_SPEED_40G;
1160                 break;
1161         default:
1162                 link.link_speed = ETH_LINK_SPEED_100;
1163                 break;
1164         }
1165
1166 out:
1167         rte_i40e_dev_atomic_write_link_status(dev, &link);
1168         if (link.link_status == old.link_status)
1169                 return -1;
1170
1171         return 0;
1172 }
1173
1174 /* Get all the statistics of a VSI */
1175 void
1176 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1177 {
1178         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1179         struct i40e_eth_stats *nes = &vsi->eth_stats;
1180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1181         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1182
1183         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1184                             vsi->offset_loaded, &oes->rx_bytes,
1185                             &nes->rx_bytes);
1186         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1187                             vsi->offset_loaded, &oes->rx_unicast,
1188                             &nes->rx_unicast);
1189         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1190                             vsi->offset_loaded, &oes->rx_multicast,
1191                             &nes->rx_multicast);
1192         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1193                             vsi->offset_loaded, &oes->rx_broadcast,
1194                             &nes->rx_broadcast);
1195         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1196                             &oes->rx_discards, &nes->rx_discards);
1197         /* GLV_REPC not supported */
1198         /* GLV_RMPC not supported */
1199         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1200                             &oes->rx_unknown_protocol,
1201                             &nes->rx_unknown_protocol);
1202         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1203                             vsi->offset_loaded, &oes->tx_bytes,
1204                             &nes->tx_bytes);
1205         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1206                             vsi->offset_loaded, &oes->tx_unicast,
1207                             &nes->tx_unicast);
1208         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1209                             vsi->offset_loaded, &oes->tx_multicast,
1210                             &nes->tx_multicast);
1211         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1212                             vsi->offset_loaded,  &oes->tx_broadcast,
1213                             &nes->tx_broadcast);
1214         /* GLV_TDPC not supported */
1215         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1216                             &oes->tx_errors, &nes->tx_errors);
1217         vsi->offset_loaded = true;
1218
1219         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1220                     vsi->vsi_id);
1221         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1222         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1223         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1224         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1225         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1226         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1227                     nes->rx_unknown_protocol);
1228         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1229         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1230         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1231         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1232         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1233         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1234         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1235                     vsi->vsi_id);
1236 }
1237
1238 /* Get all statistics of a port */
1239 static void
1240 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1241 {
1242         uint32_t i;
1243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1246         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1247
1248         /* Get statistics of struct i40e_eth_stats */
1249         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1250                             I40E_GLPRT_GORCL(hw->port),
1251                             pf->offset_loaded, &os->eth.rx_bytes,
1252                             &ns->eth.rx_bytes);
1253         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1254                             I40E_GLPRT_UPRCL(hw->port),
1255                             pf->offset_loaded, &os->eth.rx_unicast,
1256                             &ns->eth.rx_unicast);
1257         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1258                             I40E_GLPRT_MPRCL(hw->port),
1259                             pf->offset_loaded, &os->eth.rx_multicast,
1260                             &ns->eth.rx_multicast);
1261         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1262                             I40E_GLPRT_BPRCL(hw->port),
1263                             pf->offset_loaded, &os->eth.rx_broadcast,
1264                             &ns->eth.rx_broadcast);
1265         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1266                             pf->offset_loaded, &os->eth.rx_discards,
1267                             &ns->eth.rx_discards);
1268         /* GLPRT_REPC not supported */
1269         /* GLPRT_RMPC not supported */
1270         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1271                             pf->offset_loaded,
1272                             &os->eth.rx_unknown_protocol,
1273                             &ns->eth.rx_unknown_protocol);
1274         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1275                             I40E_GLPRT_GOTCL(hw->port),
1276                             pf->offset_loaded, &os->eth.tx_bytes,
1277                             &ns->eth.tx_bytes);
1278         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1279                             I40E_GLPRT_UPTCL(hw->port),
1280                             pf->offset_loaded, &os->eth.tx_unicast,
1281                             &ns->eth.tx_unicast);
1282         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1283                             I40E_GLPRT_MPTCL(hw->port),
1284                             pf->offset_loaded, &os->eth.tx_multicast,
1285                             &ns->eth.tx_multicast);
1286         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1287                             I40E_GLPRT_BPTCL(hw->port),
1288                             pf->offset_loaded, &os->eth.tx_broadcast,
1289                             &ns->eth.tx_broadcast);
1290         /* GLPRT_TEPC not supported */
1291
1292         /* additional port specific stats */
1293         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1294                             pf->offset_loaded, &os->tx_dropped_link_down,
1295                             &ns->tx_dropped_link_down);
1296         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1297                             pf->offset_loaded, &os->crc_errors,
1298                             &ns->crc_errors);
1299         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1300                             pf->offset_loaded, &os->illegal_bytes,
1301                             &ns->illegal_bytes);
1302         /* GLPRT_ERRBC not supported */
1303         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1304                             pf->offset_loaded, &os->mac_local_faults,
1305                             &ns->mac_local_faults);
1306         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1307                             pf->offset_loaded, &os->mac_remote_faults,
1308                             &ns->mac_remote_faults);
1309         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1310                             pf->offset_loaded, &os->rx_length_errors,
1311                             &ns->rx_length_errors);
1312         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1313                             pf->offset_loaded, &os->link_xon_rx,
1314                             &ns->link_xon_rx);
1315         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1316                             pf->offset_loaded, &os->link_xoff_rx,
1317                             &ns->link_xoff_rx);
1318         for (i = 0; i < 8; i++) {
1319                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1320                                     pf->offset_loaded,
1321                                     &os->priority_xon_rx[i],
1322                                     &ns->priority_xon_rx[i]);
1323                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1324                                     pf->offset_loaded,
1325                                     &os->priority_xoff_rx[i],
1326                                     &ns->priority_xoff_rx[i]);
1327         }
1328         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1329                             pf->offset_loaded, &os->link_xon_tx,
1330                             &ns->link_xon_tx);
1331         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1332                             pf->offset_loaded, &os->link_xoff_tx,
1333                             &ns->link_xoff_tx);
1334         for (i = 0; i < 8; i++) {
1335                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1336                                     pf->offset_loaded,
1337                                     &os->priority_xon_tx[i],
1338                                     &ns->priority_xon_tx[i]);
1339                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1340                                     pf->offset_loaded,
1341                                     &os->priority_xoff_tx[i],
1342                                     &ns->priority_xoff_tx[i]);
1343                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1344                                     pf->offset_loaded,
1345                                     &os->priority_xon_2_xoff[i],
1346                                     &ns->priority_xon_2_xoff[i]);
1347         }
1348         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1349                             I40E_GLPRT_PRC64L(hw->port),
1350                             pf->offset_loaded, &os->rx_size_64,
1351                             &ns->rx_size_64);
1352         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1353                             I40E_GLPRT_PRC127L(hw->port),
1354                             pf->offset_loaded, &os->rx_size_127,
1355                             &ns->rx_size_127);
1356         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1357                             I40E_GLPRT_PRC255L(hw->port),
1358                             pf->offset_loaded, &os->rx_size_255,
1359                             &ns->rx_size_255);
1360         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1361                             I40E_GLPRT_PRC511L(hw->port),
1362                             pf->offset_loaded, &os->rx_size_511,
1363                             &ns->rx_size_511);
1364         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1365                             I40E_GLPRT_PRC1023L(hw->port),
1366                             pf->offset_loaded, &os->rx_size_1023,
1367                             &ns->rx_size_1023);
1368         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1369                             I40E_GLPRT_PRC1522L(hw->port),
1370                             pf->offset_loaded, &os->rx_size_1522,
1371                             &ns->rx_size_1522);
1372         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1373                             I40E_GLPRT_PRC9522L(hw->port),
1374                             pf->offset_loaded, &os->rx_size_big,
1375                             &ns->rx_size_big);
1376         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1377                             pf->offset_loaded, &os->rx_undersize,
1378                             &ns->rx_undersize);
1379         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1380                             pf->offset_loaded, &os->rx_fragments,
1381                             &ns->rx_fragments);
1382         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1383                             pf->offset_loaded, &os->rx_oversize,
1384                             &ns->rx_oversize);
1385         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1386                             pf->offset_loaded, &os->rx_jabber,
1387                             &ns->rx_jabber);
1388         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1389                             I40E_GLPRT_PTC64L(hw->port),
1390                             pf->offset_loaded, &os->tx_size_64,
1391                             &ns->tx_size_64);
1392         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1393                             I40E_GLPRT_PTC127L(hw->port),
1394                             pf->offset_loaded, &os->tx_size_127,
1395                             &ns->tx_size_127);
1396         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1397                             I40E_GLPRT_PTC255L(hw->port),
1398                             pf->offset_loaded, &os->tx_size_255,
1399                             &ns->tx_size_255);
1400         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1401                             I40E_GLPRT_PTC511L(hw->port),
1402                             pf->offset_loaded, &os->tx_size_511,
1403                             &ns->tx_size_511);
1404         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1405                             I40E_GLPRT_PTC1023L(hw->port),
1406                             pf->offset_loaded, &os->tx_size_1023,
1407                             &ns->tx_size_1023);
1408         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1409                             I40E_GLPRT_PTC1522L(hw->port),
1410                             pf->offset_loaded, &os->tx_size_1522,
1411                             &ns->tx_size_1522);
1412         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1413                             I40E_GLPRT_PTC9522L(hw->port),
1414                             pf->offset_loaded, &os->tx_size_big,
1415                             &ns->tx_size_big);
1416         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1417                            pf->offset_loaded,
1418                            &os->fd_sb_match, &ns->fd_sb_match);
1419         /* GLPRT_MSPDC not supported */
1420         /* GLPRT_XEC not supported */
1421
1422         pf->offset_loaded = true;
1423
1424         if (pf->main_vsi)
1425                 i40e_update_vsi_stats(pf->main_vsi);
1426
1427         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1428                                                 ns->eth.rx_broadcast;
1429         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1430                                                 ns->eth.tx_broadcast;
1431         stats->ibytes   = ns->eth.rx_bytes;
1432         stats->obytes   = ns->eth.tx_bytes;
1433         stats->oerrors  = ns->eth.tx_errors;
1434         stats->imcasts  = ns->eth.rx_multicast;
1435         stats->fdirmatch = ns->fd_sb_match;
1436
1437         /* Rx Errors */
1438         stats->ibadcrc  = ns->crc_errors;
1439         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1440                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1441         stats->imissed  = ns->eth.rx_discards;
1442         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1443
1444         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1445         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1446         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1447         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1448         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1449         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1450         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1451                     ns->eth.rx_unknown_protocol);
1452         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1453         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1454         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1455         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1456         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1457         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1458
1459         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1460                     ns->tx_dropped_link_down);
1461         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1462         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1463                     ns->illegal_bytes);
1464         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1465         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1466                     ns->mac_local_faults);
1467         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1468                     ns->mac_remote_faults);
1469         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1470                     ns->rx_length_errors);
1471         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1472         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1473         for (i = 0; i < 8; i++) {
1474                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1475                                 i, ns->priority_xon_rx[i]);
1476                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1477                                 i, ns->priority_xoff_rx[i]);
1478         }
1479         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1480         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1481         for (i = 0; i < 8; i++) {
1482                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1483                                 i, ns->priority_xon_tx[i]);
1484                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1485                                 i, ns->priority_xoff_tx[i]);
1486                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1487                                 i, ns->priority_xon_2_xoff[i]);
1488         }
1489         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1490         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1491         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1492         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1493         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1494         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1495         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1496         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1497         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1498         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1499         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1500         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1501         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1502         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1503         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1504         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1505         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1506         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1507         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1508                         ns->mac_short_packet_dropped);
1509         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1510                     ns->checksum_error);
1511         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1512         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1513 }
1514
1515 /* Reset the statistics */
1516 static void
1517 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1518 {
1519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1520
1521         /* It results in reloading the start point of each counter */
1522         pf->offset_loaded = false;
1523 }
1524
1525 static int
1526 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1527                                  __rte_unused uint16_t queue_id,
1528                                  __rte_unused uint8_t stat_idx,
1529                                  __rte_unused uint8_t is_rx)
1530 {
1531         PMD_INIT_FUNC_TRACE();
1532
1533         return -ENOSYS;
1534 }
1535
1536 static void
1537 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1538 {
1539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1540         struct i40e_vsi *vsi = pf->main_vsi;
1541
1542         dev_info->max_rx_queues = vsi->nb_qps;
1543         dev_info->max_tx_queues = vsi->nb_qps;
1544         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1545         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1546         dev_info->max_mac_addrs = vsi->max_macaddrs;
1547         dev_info->max_vfs = dev->pci_dev->max_vfs;
1548         dev_info->rx_offload_capa =
1549                 DEV_RX_OFFLOAD_VLAN_STRIP |
1550                 DEV_RX_OFFLOAD_QINQ_STRIP |
1551                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1552                 DEV_RX_OFFLOAD_UDP_CKSUM |
1553                 DEV_RX_OFFLOAD_TCP_CKSUM;
1554         dev_info->tx_offload_capa =
1555                 DEV_TX_OFFLOAD_VLAN_INSERT |
1556                 DEV_TX_OFFLOAD_QINQ_INSERT |
1557                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1558                 DEV_TX_OFFLOAD_UDP_CKSUM |
1559                 DEV_TX_OFFLOAD_TCP_CKSUM |
1560                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1561                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1562                 DEV_TX_OFFLOAD_TCP_TSO;
1563         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1564                                                 sizeof(uint32_t);
1565         dev_info->reta_size = pf->hash_lut_size;
1566         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1567
1568         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1569                 .rx_thresh = {
1570                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1571                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1572                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1573                 },
1574                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1575                 .rx_drop_en = 0,
1576         };
1577
1578         dev_info->default_txconf = (struct rte_eth_txconf) {
1579                 .tx_thresh = {
1580                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1581                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1582                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1583                 },
1584                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1585                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1586                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1587                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1588         };
1589
1590         if (pf->flags & I40E_FLAG_VMDQ) {
1591                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1592                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1593                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1594                                                 pf->max_nb_vmdq_vsi;
1595                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1596                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1597                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1598         }
1599 }
1600
1601 static int
1602 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1603 {
1604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1605         struct i40e_vsi *vsi = pf->main_vsi;
1606         PMD_INIT_FUNC_TRACE();
1607
1608         if (on)
1609                 return i40e_vsi_add_vlan(vsi, vlan_id);
1610         else
1611                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1612 }
1613
1614 static void
1615 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1616                    __rte_unused uint16_t tpid)
1617 {
1618         PMD_INIT_FUNC_TRACE();
1619 }
1620
1621 static void
1622 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1623 {
1624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct i40e_vsi *vsi = pf->main_vsi;
1626
1627         if (mask & ETH_VLAN_STRIP_MASK) {
1628                 /* Enable or disable VLAN stripping */
1629                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1630                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1631                 else
1632                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1633         }
1634
1635         if (mask & ETH_VLAN_EXTEND_MASK) {
1636                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1637                         i40e_vsi_config_double_vlan(vsi, TRUE);
1638                 else
1639                         i40e_vsi_config_double_vlan(vsi, FALSE);
1640         }
1641 }
1642
1643 static void
1644 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1645                           __rte_unused uint16_t queue,
1646                           __rte_unused int on)
1647 {
1648         PMD_INIT_FUNC_TRACE();
1649 }
1650
1651 static int
1652 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1653 {
1654         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1655         struct i40e_vsi *vsi = pf->main_vsi;
1656         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1657         struct i40e_vsi_vlan_pvid_info info;
1658
1659         memset(&info, 0, sizeof(info));
1660         info.on = on;
1661         if (info.on)
1662                 info.config.pvid = pvid;
1663         else {
1664                 info.config.reject.tagged =
1665                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1666                 info.config.reject.untagged =
1667                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1668         }
1669
1670         return i40e_vsi_vlan_pvid_set(vsi, &info);
1671 }
1672
1673 static int
1674 i40e_dev_led_on(struct rte_eth_dev *dev)
1675 {
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t mode = i40e_led_get(hw);
1678
1679         if (mode == 0)
1680                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1681
1682         return 0;
1683 }
1684
1685 static int
1686 i40e_dev_led_off(struct rte_eth_dev *dev)
1687 {
1688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t mode = i40e_led_get(hw);
1690
1691         if (mode != 0)
1692                 i40e_led_set(hw, 0, false);
1693
1694         return 0;
1695 }
1696
1697 static int
1698 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1699                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1700 {
1701         PMD_INIT_FUNC_TRACE();
1702
1703         return -ENOSYS;
1704 }
1705
1706 static int
1707 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1708                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1709 {
1710         PMD_INIT_FUNC_TRACE();
1711
1712         return -ENOSYS;
1713 }
1714
1715 /* Add a MAC address, and update filters */
1716 static void
1717 i40e_macaddr_add(struct rte_eth_dev *dev,
1718                  struct ether_addr *mac_addr,
1719                  __rte_unused uint32_t index,
1720                  uint32_t pool)
1721 {
1722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1723         struct i40e_mac_filter_info mac_filter;
1724         struct i40e_vsi *vsi;
1725         int ret;
1726
1727         /* If VMDQ not enabled or configured, return */
1728         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1729                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1730                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1731                         pool);
1732                 return;
1733         }
1734
1735         if (pool > pf->nb_cfg_vmdq_vsi) {
1736                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1737                                 pool, pf->nb_cfg_vmdq_vsi);
1738                 return;
1739         }
1740
1741         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1742         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1743
1744         if (pool == 0)
1745                 vsi = pf->main_vsi;
1746         else
1747                 vsi = pf->vmdq[pool - 1].vsi;
1748
1749         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1750         if (ret != I40E_SUCCESS) {
1751                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1752                 return;
1753         }
1754 }
1755
1756 /* Remove a MAC address, and update filters */
1757 static void
1758 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1759 {
1760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1761         struct i40e_vsi *vsi;
1762         struct rte_eth_dev_data *data = dev->data;
1763         struct ether_addr *macaddr;
1764         int ret;
1765         uint32_t i;
1766         uint64_t pool_sel;
1767
1768         macaddr = &(data->mac_addrs[index]);
1769
1770         pool_sel = dev->data->mac_pool_sel[index];
1771
1772         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1773                 if (pool_sel & (1ULL << i)) {
1774                         if (i == 0)
1775                                 vsi = pf->main_vsi;
1776                         else {
1777                                 /* No VMDQ pool enabled or configured */
1778                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1779                                         (i > pf->nb_cfg_vmdq_vsi)) {
1780                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1781                                                         "/configured");
1782                                         return;
1783                                 }
1784                                 vsi = pf->vmdq[i - 1].vsi;
1785                         }
1786                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1787
1788                         if (ret) {
1789                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1790                                 return;
1791                         }
1792                 }
1793         }
1794 }
1795
1796 /* Set perfect match or hash match of MAC and VLAN for a VF */
1797 static int
1798 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1799                  struct rte_eth_mac_filter *filter,
1800                  bool add)
1801 {
1802         struct i40e_hw *hw;
1803         struct i40e_mac_filter_info mac_filter;
1804         struct ether_addr old_mac;
1805         struct ether_addr *new_mac;
1806         struct i40e_pf_vf *vf = NULL;
1807         uint16_t vf_id;
1808         int ret;
1809
1810         if (pf == NULL) {
1811                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1812                 return -EINVAL;
1813         }
1814         hw = I40E_PF_TO_HW(pf);
1815
1816         if (filter == NULL) {
1817                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1818                 return -EINVAL;
1819         }
1820
1821         new_mac = &filter->mac_addr;
1822
1823         if (is_zero_ether_addr(new_mac)) {
1824                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1825                 return -EINVAL;
1826         }
1827
1828         vf_id = filter->dst_id;
1829
1830         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1831                 PMD_DRV_LOG(ERR, "Invalid argument.");
1832                 return -EINVAL;
1833         }
1834         vf = &pf->vfs[vf_id];
1835
1836         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1837                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1838                 return -EINVAL;
1839         }
1840
1841         if (add) {
1842                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1843                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1844                                 ETHER_ADDR_LEN);
1845                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1846                                  ETHER_ADDR_LEN);
1847
1848                 mac_filter.filter_type = filter->filter_type;
1849                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1850                 if (ret != I40E_SUCCESS) {
1851                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1852                         return -1;
1853                 }
1854                 ether_addr_copy(new_mac, &pf->dev_addr);
1855         } else {
1856                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1857                                 ETHER_ADDR_LEN);
1858                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1859                 if (ret != I40E_SUCCESS) {
1860                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1861                         return -1;
1862                 }
1863
1864                 /* Clear device address as it has been removed */
1865                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1866                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1867         }
1868
1869         return 0;
1870 }
1871
1872 /* MAC filter handle */
1873 static int
1874 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1875                 void *arg)
1876 {
1877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1878         struct rte_eth_mac_filter *filter;
1879         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1880         int ret = I40E_NOT_SUPPORTED;
1881
1882         filter = (struct rte_eth_mac_filter *)(arg);
1883
1884         switch (filter_op) {
1885         case RTE_ETH_FILTER_NOP:
1886                 ret = I40E_SUCCESS;
1887                 break;
1888         case RTE_ETH_FILTER_ADD:
1889                 i40e_pf_disable_irq0(hw);
1890                 if (filter->is_vf)
1891                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1892                 i40e_pf_enable_irq0(hw);
1893                 break;
1894         case RTE_ETH_FILTER_DELETE:
1895                 i40e_pf_disable_irq0(hw);
1896                 if (filter->is_vf)
1897                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1898                 i40e_pf_enable_irq0(hw);
1899                 break;
1900         default:
1901                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1902                 ret = I40E_ERR_PARAM;
1903                 break;
1904         }
1905
1906         return ret;
1907 }
1908
1909 static int
1910 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1911                          struct rte_eth_rss_reta_entry64 *reta_conf,
1912                          uint16_t reta_size)
1913 {
1914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         uint32_t lut, l;
1917         uint16_t i, j, lut_size = pf->hash_lut_size;
1918         uint16_t idx, shift;
1919         uint8_t mask;
1920
1921         if (reta_size != lut_size ||
1922                 reta_size > ETH_RSS_RETA_SIZE_512) {
1923                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1924                         "(%d) doesn't match the number hardware can supported "
1925                                         "(%d)\n", reta_size, lut_size);
1926                 return -EINVAL;
1927         }
1928
1929         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1930                 idx = i / RTE_RETA_GROUP_SIZE;
1931                 shift = i % RTE_RETA_GROUP_SIZE;
1932                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1933                                                 I40E_4_BIT_MASK);
1934                 if (!mask)
1935                         continue;
1936                 if (mask == I40E_4_BIT_MASK)
1937                         l = 0;
1938                 else
1939                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1940                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1941                         if (mask & (0x1 << j))
1942                                 lut |= reta_conf[idx].reta[shift + j] <<
1943                                                         (CHAR_BIT * j);
1944                         else
1945                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1946                 }
1947                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1948         }
1949
1950         return 0;
1951 }
1952
1953 static int
1954 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1955                         struct rte_eth_rss_reta_entry64 *reta_conf,
1956                         uint16_t reta_size)
1957 {
1958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960         uint32_t lut;
1961         uint16_t i, j, lut_size = pf->hash_lut_size;
1962         uint16_t idx, shift;
1963         uint8_t mask;
1964
1965         if (reta_size != lut_size ||
1966                 reta_size > ETH_RSS_RETA_SIZE_512) {
1967                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1968                         "(%d) doesn't match the number hardware can supported "
1969                                         "(%d)\n", reta_size, lut_size);
1970                 return -EINVAL;
1971         }
1972
1973         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1974                 idx = i / RTE_RETA_GROUP_SIZE;
1975                 shift = i % RTE_RETA_GROUP_SIZE;
1976                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1977                                                 I40E_4_BIT_MASK);
1978                 if (!mask)
1979                         continue;
1980
1981                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1982                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1983                         if (mask & (0x1 << j))
1984                                 reta_conf[idx].reta[shift + j] = ((lut >>
1985                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1986                 }
1987         }
1988
1989         return 0;
1990 }
1991
1992 /**
1993  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1994  * @hw:   pointer to the HW structure
1995  * @mem:  pointer to mem struct to fill out
1996  * @size: size of memory requested
1997  * @alignment: what to align the allocation to
1998  **/
1999 enum i40e_status_code
2000 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2001                         struct i40e_dma_mem *mem,
2002                         u64 size,
2003                         u32 alignment)
2004 {
2005         static uint64_t id = 0;
2006         const struct rte_memzone *mz = NULL;
2007         char z_name[RTE_MEMZONE_NAMESIZE];
2008
2009         if (!mem)
2010                 return I40E_ERR_PARAM;
2011
2012         id++;
2013         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2014 #ifdef RTE_LIBRTE_XEN_DOM0
2015         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2016                                                         RTE_PGSIZE_2M);
2017 #else
2018         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2019 #endif
2020         if (!mz)
2021                 return I40E_ERR_NO_MEMORY;
2022
2023         mem->id = id;
2024         mem->size = size;
2025         mem->va = mz->addr;
2026 #ifdef RTE_LIBRTE_XEN_DOM0
2027         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2028 #else
2029         mem->pa = mz->phys_addr;
2030 #endif
2031
2032         return I40E_SUCCESS;
2033 }
2034
2035 /**
2036  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2037  * @hw:   pointer to the HW structure
2038  * @mem:  ptr to mem struct to free
2039  **/
2040 enum i40e_status_code
2041 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2042                     struct i40e_dma_mem *mem)
2043 {
2044         if (!mem || !mem->va)
2045                 return I40E_ERR_PARAM;
2046
2047         mem->va = NULL;
2048         mem->pa = (u64)0;
2049
2050         return I40E_SUCCESS;
2051 }
2052
2053 /**
2054  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2055  * @hw:   pointer to the HW structure
2056  * @mem:  pointer to mem struct to fill out
2057  * @size: size of memory requested
2058  **/
2059 enum i40e_status_code
2060 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2061                          struct i40e_virt_mem *mem,
2062                          u32 size)
2063 {
2064         if (!mem)
2065                 return I40E_ERR_PARAM;
2066
2067         mem->size = size;
2068         mem->va = rte_zmalloc("i40e", size, 0);
2069
2070         if (mem->va)
2071                 return I40E_SUCCESS;
2072         else
2073                 return I40E_ERR_NO_MEMORY;
2074 }
2075
2076 /**
2077  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2078  * @hw:   pointer to the HW structure
2079  * @mem:  pointer to mem struct to free
2080  **/
2081 enum i40e_status_code
2082 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2083                      struct i40e_virt_mem *mem)
2084 {
2085         if (!mem)
2086                 return I40E_ERR_PARAM;
2087
2088         rte_free(mem->va);
2089         mem->va = NULL;
2090
2091         return I40E_SUCCESS;
2092 }
2093
2094 void
2095 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2096 {
2097         rte_spinlock_init(&sp->spinlock);
2098 }
2099
2100 void
2101 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2102 {
2103         rte_spinlock_lock(&sp->spinlock);
2104 }
2105
2106 void
2107 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2108 {
2109         rte_spinlock_unlock(&sp->spinlock);
2110 }
2111
2112 void
2113 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2114 {
2115         return;
2116 }
2117
2118 /**
2119  * Get the hardware capabilities, which will be parsed
2120  * and saved into struct i40e_hw.
2121  */
2122 static int
2123 i40e_get_cap(struct i40e_hw *hw)
2124 {
2125         struct i40e_aqc_list_capabilities_element_resp *buf;
2126         uint16_t len, size = 0;
2127         int ret;
2128
2129         /* Calculate a huge enough buff for saving response data temporarily */
2130         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2131                                                 I40E_MAX_CAP_ELE_NUM;
2132         buf = rte_zmalloc("i40e", len, 0);
2133         if (!buf) {
2134                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2135                 return I40E_ERR_NO_MEMORY;
2136         }
2137
2138         /* Get, parse the capabilities and save it to hw */
2139         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2140                         i40e_aqc_opc_list_func_capabilities, NULL);
2141         if (ret != I40E_SUCCESS)
2142                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2143
2144         /* Free the temporary buffer after being used */
2145         rte_free(buf);
2146
2147         return ret;
2148 }
2149
2150 static int
2151 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2152 {
2153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2155         uint16_t sum_queues = 0, sum_vsis, left_queues;
2156
2157         /* First check if FW support SRIOV */
2158         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2159                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2160                 return -EINVAL;
2161         }
2162
2163         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2164         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2165         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2166         /* Allocate queues for pf */
2167         if (hw->func_caps.rss) {
2168                 pf->flags |= I40E_FLAG_RSS;
2169                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2170                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2171                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2172         } else
2173                 pf->lan_nb_qps = 1;
2174         sum_queues = pf->lan_nb_qps;
2175         /* Default VSI is not counted in */
2176         sum_vsis = 0;
2177         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2178
2179         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2180                 pf->flags |= I40E_FLAG_SRIOV;
2181                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2182                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2183                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2184                                      "max supported %u.",
2185                                      dev->pci_dev->max_vfs,
2186                                      hw->func_caps.num_vfs);
2187                         return -EINVAL;
2188                 }
2189                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2190                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2191                                      "max support %u queues.",
2192                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2193                         return -EINVAL;
2194                 }
2195                 pf->vf_num = dev->pci_dev->max_vfs;
2196                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2197                 sum_vsis   += pf->vf_num;
2198                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2199                              pf->vf_num, pf->vf_nb_qps);
2200         } else
2201                 pf->vf_num = 0;
2202
2203         if (hw->func_caps.vmdq) {
2204                 pf->flags |= I40E_FLAG_VMDQ;
2205                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2206                 pf->max_nb_vmdq_vsi = 1;
2207                 /*
2208                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2209                  * later.
2210                  */
2211                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2212                 sum_vsis += pf->max_nb_vmdq_vsi;
2213         } else {
2214                 pf->vmdq_nb_qps = 0;
2215                 pf->max_nb_vmdq_vsi = 0;
2216         }
2217         pf->nb_cfg_vmdq_vsi = 0;
2218
2219         if (hw->func_caps.fd) {
2220                 pf->flags |= I40E_FLAG_FDIR;
2221                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2222                 /**
2223                  * Each flow director consumes one VSI and one queue,
2224                  * but can't calculate out predictably here.
2225                  */
2226         }
2227
2228         if (sum_vsis > pf->max_num_vsi ||
2229                 sum_queues > hw->func_caps.num_rx_qp) {
2230                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2231                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2232                              pf->max_num_vsi, sum_vsis);
2233                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2234                              hw->func_caps.num_rx_qp, sum_queues);
2235                 return -EINVAL;
2236         }
2237
2238         /* Adjust VMDQ setting to support as many VMs as possible */
2239         if (pf->flags & I40E_FLAG_VMDQ) {
2240                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2241
2242                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2243                                         pf->max_num_vsi - sum_vsis);
2244
2245                 /* Limit the max VMDQ number that rte_ether that can support  */
2246                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2247                                         ETH_64_POOLS - 1);
2248
2249                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2250                                 pf->max_nb_vmdq_vsi);
2251                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2252         }
2253
2254         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2255          * cause */
2256         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2257                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2258                              sum_vsis, hw->func_caps.num_msix_vectors);
2259                 return -EINVAL;
2260         }
2261         return I40E_SUCCESS;
2262 }
2263
2264 static int
2265 i40e_pf_get_switch_config(struct i40e_pf *pf)
2266 {
2267         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2268         struct i40e_aqc_get_switch_config_resp *switch_config;
2269         struct i40e_aqc_switch_config_element_resp *element;
2270         uint16_t start_seid = 0, num_reported;
2271         int ret;
2272
2273         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2274                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2275         if (!switch_config) {
2276                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2277                 return -ENOMEM;
2278         }
2279
2280         /* Get the switch configurations */
2281         ret = i40e_aq_get_switch_config(hw, switch_config,
2282                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2283         if (ret != I40E_SUCCESS) {
2284                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2285                 goto fail;
2286         }
2287         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2288         if (num_reported != 1) { /* The number should be 1 */
2289                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2290                 goto fail;
2291         }
2292
2293         /* Parse the switch configuration elements */
2294         element = &(switch_config->element[0]);
2295         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2296                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2297                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2298         } else
2299                 PMD_DRV_LOG(INFO, "Unknown element type");
2300
2301 fail:
2302         rte_free(switch_config);
2303
2304         return ret;
2305 }
2306
2307 static int
2308 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2309                         uint32_t num)
2310 {
2311         struct pool_entry *entry;
2312
2313         if (pool == NULL || num == 0)
2314                 return -EINVAL;
2315
2316         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2317         if (entry == NULL) {
2318                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2319                 return -ENOMEM;
2320         }
2321
2322         /* queue heap initialize */
2323         pool->num_free = num;
2324         pool->num_alloc = 0;
2325         pool->base = base;
2326         LIST_INIT(&pool->alloc_list);
2327         LIST_INIT(&pool->free_list);
2328
2329         /* Initialize element  */
2330         entry->base = 0;
2331         entry->len = num;
2332
2333         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2334         return 0;
2335 }
2336
2337 static void
2338 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2339 {
2340         struct pool_entry *entry;
2341
2342         if (pool == NULL)
2343                 return;
2344
2345         LIST_FOREACH(entry, &pool->alloc_list, next) {
2346                 LIST_REMOVE(entry, next);
2347                 rte_free(entry);
2348         }
2349
2350         LIST_FOREACH(entry, &pool->free_list, next) {
2351                 LIST_REMOVE(entry, next);
2352                 rte_free(entry);
2353         }
2354
2355         pool->num_free = 0;
2356         pool->num_alloc = 0;
2357         pool->base = 0;
2358         LIST_INIT(&pool->alloc_list);
2359         LIST_INIT(&pool->free_list);
2360 }
2361
2362 static int
2363 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2364                        uint32_t base)
2365 {
2366         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2367         uint32_t pool_offset;
2368         int insert;
2369
2370         if (pool == NULL) {
2371                 PMD_DRV_LOG(ERR, "Invalid parameter");
2372                 return -EINVAL;
2373         }
2374
2375         pool_offset = base - pool->base;
2376         /* Lookup in alloc list */
2377         LIST_FOREACH(entry, &pool->alloc_list, next) {
2378                 if (entry->base == pool_offset) {
2379                         valid_entry = entry;
2380                         LIST_REMOVE(entry, next);
2381                         break;
2382                 }
2383         }
2384
2385         /* Not find, return */
2386         if (valid_entry == NULL) {
2387                 PMD_DRV_LOG(ERR, "Failed to find entry");
2388                 return -EINVAL;
2389         }
2390
2391         /**
2392          * Found it, move it to free list  and try to merge.
2393          * In order to make merge easier, always sort it by qbase.
2394          * Find adjacent prev and last entries.
2395          */
2396         prev = next = NULL;
2397         LIST_FOREACH(entry, &pool->free_list, next) {
2398                 if (entry->base > valid_entry->base) {
2399                         next = entry;
2400                         break;
2401                 }
2402                 prev = entry;
2403         }
2404
2405         insert = 0;
2406         /* Try to merge with next one*/
2407         if (next != NULL) {
2408                 /* Merge with next one */
2409                 if (valid_entry->base + valid_entry->len == next->base) {
2410                         next->base = valid_entry->base;
2411                         next->len += valid_entry->len;
2412                         rte_free(valid_entry);
2413                         valid_entry = next;
2414                         insert = 1;
2415                 }
2416         }
2417
2418         if (prev != NULL) {
2419                 /* Merge with previous one */
2420                 if (prev->base + prev->len == valid_entry->base) {
2421                         prev->len += valid_entry->len;
2422                         /* If it merge with next one, remove next node */
2423                         if (insert == 1) {
2424                                 LIST_REMOVE(valid_entry, next);
2425                                 rte_free(valid_entry);
2426                         } else {
2427                                 rte_free(valid_entry);
2428                                 insert = 1;
2429                         }
2430                 }
2431         }
2432
2433         /* Not find any entry to merge, insert */
2434         if (insert == 0) {
2435                 if (prev != NULL)
2436                         LIST_INSERT_AFTER(prev, valid_entry, next);
2437                 else if (next != NULL)
2438                         LIST_INSERT_BEFORE(next, valid_entry, next);
2439                 else /* It's empty list, insert to head */
2440                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2441         }
2442
2443         pool->num_free += valid_entry->len;
2444         pool->num_alloc -= valid_entry->len;
2445
2446         return 0;
2447 }
2448
2449 static int
2450 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2451                        uint16_t num)
2452 {
2453         struct pool_entry *entry, *valid_entry;
2454
2455         if (pool == NULL || num == 0) {
2456                 PMD_DRV_LOG(ERR, "Invalid parameter");
2457                 return -EINVAL;
2458         }
2459
2460         if (pool->num_free < num) {
2461                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2462                             num, pool->num_free);
2463                 return -ENOMEM;
2464         }
2465
2466         valid_entry = NULL;
2467         /* Lookup  in free list and find most fit one */
2468         LIST_FOREACH(entry, &pool->free_list, next) {
2469                 if (entry->len >= num) {
2470                         /* Find best one */
2471                         if (entry->len == num) {
2472                                 valid_entry = entry;
2473                                 break;
2474                         }
2475                         if (valid_entry == NULL || valid_entry->len > entry->len)
2476                                 valid_entry = entry;
2477                 }
2478         }
2479
2480         /* Not find one to satisfy the request, return */
2481         if (valid_entry == NULL) {
2482                 PMD_DRV_LOG(ERR, "No valid entry found");
2483                 return -ENOMEM;
2484         }
2485         /**
2486          * The entry have equal queue number as requested,
2487          * remove it from alloc_list.
2488          */
2489         if (valid_entry->len == num) {
2490                 LIST_REMOVE(valid_entry, next);
2491         } else {
2492                 /**
2493                  * The entry have more numbers than requested,
2494                  * create a new entry for alloc_list and minus its
2495                  * queue base and number in free_list.
2496                  */
2497                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2498                 if (entry == NULL) {
2499                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2500                                     "resource pool");
2501                         return -ENOMEM;
2502                 }
2503                 entry->base = valid_entry->base;
2504                 entry->len = num;
2505                 valid_entry->base += num;
2506                 valid_entry->len -= num;
2507                 valid_entry = entry;
2508         }
2509
2510         /* Insert it into alloc list, not sorted */
2511         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2512
2513         pool->num_free -= valid_entry->len;
2514         pool->num_alloc += valid_entry->len;
2515
2516         return (valid_entry->base + pool->base);
2517 }
2518
2519 /**
2520  * bitmap_is_subset - Check whether src2 is subset of src1
2521  **/
2522 static inline int
2523 bitmap_is_subset(uint8_t src1, uint8_t src2)
2524 {
2525         return !((src1 ^ src2) & src2);
2526 }
2527
2528 static int
2529 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2530 {
2531         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2532
2533         /* If DCB is not supported, only default TC is supported */
2534         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2535                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2536                 return -EINVAL;
2537         }
2538
2539         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2540                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2541                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2542                             enabled_tcmap);
2543                 return -EINVAL;
2544         }
2545         return I40E_SUCCESS;
2546 }
2547
2548 int
2549 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2550                                 struct i40e_vsi_vlan_pvid_info *info)
2551 {
2552         struct i40e_hw *hw;
2553         struct i40e_vsi_context ctxt;
2554         uint8_t vlan_flags = 0;
2555         int ret;
2556
2557         if (vsi == NULL || info == NULL) {
2558                 PMD_DRV_LOG(ERR, "invalid parameters");
2559                 return I40E_ERR_PARAM;
2560         }
2561
2562         if (info->on) {
2563                 vsi->info.pvid = info->config.pvid;
2564                 /**
2565                  * If insert pvid is enabled, only tagged pkts are
2566                  * allowed to be sent out.
2567                  */
2568                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2569                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2570         } else {
2571                 vsi->info.pvid = 0;
2572                 if (info->config.reject.tagged == 0)
2573                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2574
2575                 if (info->config.reject.untagged == 0)
2576                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2577         }
2578         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2579                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2580         vsi->info.port_vlan_flags |= vlan_flags;
2581         vsi->info.valid_sections =
2582                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2583         memset(&ctxt, 0, sizeof(ctxt));
2584         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2585         ctxt.seid = vsi->seid;
2586
2587         hw = I40E_VSI_TO_HW(vsi);
2588         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2589         if (ret != I40E_SUCCESS)
2590                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2591
2592         return ret;
2593 }
2594
2595 static int
2596 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2597 {
2598         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2599         int i, ret;
2600         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2601
2602         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2603         if (ret != I40E_SUCCESS)
2604                 return ret;
2605
2606         if (!vsi->seid) {
2607                 PMD_DRV_LOG(ERR, "seid not valid");
2608                 return -EINVAL;
2609         }
2610
2611         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2612         tc_bw_data.tc_valid_bits = enabled_tcmap;
2613         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2614                 tc_bw_data.tc_bw_credits[i] =
2615                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2616
2617         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2618         if (ret != I40E_SUCCESS) {
2619                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2620                 return ret;
2621         }
2622
2623         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2624                                         sizeof(vsi->info.qs_handle));
2625         return I40E_SUCCESS;
2626 }
2627
2628 static int
2629 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2630                                  struct i40e_aqc_vsi_properties_data *info,
2631                                  uint8_t enabled_tcmap)
2632 {
2633         int ret, total_tc = 0, i;
2634         uint16_t qpnum_per_tc, bsf, qp_idx;
2635
2636         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2637         if (ret != I40E_SUCCESS)
2638                 return ret;
2639
2640         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2641                 if (enabled_tcmap & (1 << i))
2642                         total_tc++;
2643         vsi->enabled_tc = enabled_tcmap;
2644
2645         /* Number of queues per enabled TC */
2646         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2647         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2648         bsf = rte_bsf32(qpnum_per_tc);
2649
2650         /* Adjust the queue number to actual queues that can be applied */
2651         vsi->nb_qps = qpnum_per_tc * total_tc;
2652
2653         /**
2654          * Configure TC and queue mapping parameters, for enabled TC,
2655          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2656          * default queue will serve it.
2657          */
2658         qp_idx = 0;
2659         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2660                 if (vsi->enabled_tc & (1 << i)) {
2661                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2662                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2663                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2664                         qp_idx += qpnum_per_tc;
2665                 } else
2666                         info->tc_mapping[i] = 0;
2667         }
2668
2669         /* Associate queue number with VSI */
2670         if (vsi->type == I40E_VSI_SRIOV) {
2671                 info->mapping_flags |=
2672                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2673                 for (i = 0; i < vsi->nb_qps; i++)
2674                         info->queue_mapping[i] =
2675                                 rte_cpu_to_le_16(vsi->base_queue + i);
2676         } else {
2677                 info->mapping_flags |=
2678                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2679                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2680         }
2681         info->valid_sections |=
2682                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2683
2684         return I40E_SUCCESS;
2685 }
2686
2687 static int
2688 i40e_veb_release(struct i40e_veb *veb)
2689 {
2690         struct i40e_vsi *vsi;
2691         struct i40e_hw *hw;
2692
2693         if (veb == NULL || veb->associate_vsi == NULL)
2694                 return -EINVAL;
2695
2696         if (!TAILQ_EMPTY(&veb->head)) {
2697                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2698                 return -EACCES;
2699         }
2700
2701         vsi = veb->associate_vsi;
2702         hw = I40E_VSI_TO_HW(vsi);
2703
2704         vsi->uplink_seid = veb->uplink_seid;
2705         i40e_aq_delete_element(hw, veb->seid, NULL);
2706         rte_free(veb);
2707         vsi->veb = NULL;
2708         return I40E_SUCCESS;
2709 }
2710
2711 /* Setup a veb */
2712 static struct i40e_veb *
2713 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2714 {
2715         struct i40e_veb *veb;
2716         int ret;
2717         struct i40e_hw *hw;
2718
2719         if (NULL == pf || vsi == NULL) {
2720                 PMD_DRV_LOG(ERR, "veb setup failed, "
2721                             "associated VSI shouldn't null");
2722                 return NULL;
2723         }
2724         hw = I40E_PF_TO_HW(pf);
2725
2726         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2727         if (!veb) {
2728                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2729                 goto fail;
2730         }
2731
2732         veb->associate_vsi = vsi;
2733         TAILQ_INIT(&veb->head);
2734         veb->uplink_seid = vsi->uplink_seid;
2735
2736         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2737                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2738
2739         if (ret != I40E_SUCCESS) {
2740                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2741                             hw->aq.asq_last_status);
2742                 goto fail;
2743         }
2744
2745         /* get statistics index */
2746         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2747                                 &veb->stats_idx, NULL, NULL, NULL);
2748         if (ret != I40E_SUCCESS) {
2749                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2750                             hw->aq.asq_last_status);
2751                 goto fail;
2752         }
2753
2754         /* Get VEB bandwidth, to be implemented */
2755         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2756         vsi->uplink_seid = veb->seid;
2757
2758         return veb;
2759 fail:
2760         rte_free(veb);
2761         return NULL;
2762 }
2763
2764 int
2765 i40e_vsi_release(struct i40e_vsi *vsi)
2766 {
2767         struct i40e_pf *pf;
2768         struct i40e_hw *hw;
2769         struct i40e_vsi_list *vsi_list;
2770         int ret;
2771         struct i40e_mac_filter *f;
2772
2773         if (!vsi)
2774                 return I40E_SUCCESS;
2775
2776         pf = I40E_VSI_TO_PF(vsi);
2777         hw = I40E_VSI_TO_HW(vsi);
2778
2779         /* VSI has child to attach, release child first */
2780         if (vsi->veb) {
2781                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2782                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2783                                 return -1;
2784                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2785                 }
2786                 i40e_veb_release(vsi->veb);
2787         }
2788
2789         /* Remove all macvlan filters of the VSI */
2790         i40e_vsi_remove_all_macvlan_filter(vsi);
2791         TAILQ_FOREACH(f, &vsi->mac_list, next)
2792                 rte_free(f);
2793
2794         if (vsi->type != I40E_VSI_MAIN) {
2795                 /* Remove vsi from parent's sibling list */
2796                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2797                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2798                         return I40E_ERR_PARAM;
2799                 }
2800                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2801                                 &vsi->sib_vsi_list, list);
2802
2803                 /* Remove all switch element of the VSI */
2804                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2805                 if (ret != I40E_SUCCESS)
2806                         PMD_DRV_LOG(ERR, "Failed to delete element");
2807         }
2808         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2809
2810         if (vsi->type != I40E_VSI_SRIOV)
2811                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2812         rte_free(vsi);
2813
2814         return I40E_SUCCESS;
2815 }
2816
2817 static int
2818 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2819 {
2820         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2821         struct i40e_aqc_remove_macvlan_element_data def_filter;
2822         struct i40e_mac_filter_info filter;
2823         int ret;
2824
2825         if (vsi->type != I40E_VSI_MAIN)
2826                 return I40E_ERR_CONFIG;
2827         memset(&def_filter, 0, sizeof(def_filter));
2828         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2829                                         ETH_ADDR_LEN);
2830         def_filter.vlan_tag = 0;
2831         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2832                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2833         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2834         if (ret != I40E_SUCCESS) {
2835                 struct i40e_mac_filter *f;
2836                 struct ether_addr *mac;
2837
2838                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2839                             "macvlan filter");
2840                 /* It needs to add the permanent mac into mac list */
2841                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2842                 if (f == NULL) {
2843                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2844                         return I40E_ERR_NO_MEMORY;
2845                 }
2846                 mac = &f->mac_info.mac_addr;
2847                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2848                                 ETH_ADDR_LEN);
2849                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2850                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2851                 vsi->mac_num++;
2852
2853                 return ret;
2854         }
2855         (void)rte_memcpy(&filter.mac_addr,
2856                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2857         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2858         return i40e_vsi_add_mac(vsi, &filter);
2859 }
2860
2861 static int
2862 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2863 {
2864         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2865         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2866         struct i40e_hw *hw = &vsi->adapter->hw;
2867         i40e_status ret;
2868         int i;
2869
2870         memset(&bw_config, 0, sizeof(bw_config));
2871         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2872         if (ret != I40E_SUCCESS) {
2873                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2874                             hw->aq.asq_last_status);
2875                 return ret;
2876         }
2877
2878         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2879         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2880                                         &ets_sla_config, NULL);
2881         if (ret != I40E_SUCCESS) {
2882                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2883                             "configuration %u", hw->aq.asq_last_status);
2884                 return ret;
2885         }
2886
2887         /* Not store the info yet, just print out */
2888         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2889         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2890         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2891                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2892                             ets_sla_config.share_credits[i]);
2893                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2894                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2895                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2896                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2897                             (i * 4));
2898         }
2899
2900         return 0;
2901 }
2902
2903 /* Setup a VSI */
2904 struct i40e_vsi *
2905 i40e_vsi_setup(struct i40e_pf *pf,
2906                enum i40e_vsi_type type,
2907                struct i40e_vsi *uplink_vsi,
2908                uint16_t user_param)
2909 {
2910         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2911         struct i40e_vsi *vsi;
2912         struct i40e_mac_filter_info filter;
2913         int ret;
2914         struct i40e_vsi_context ctxt;
2915         struct ether_addr broadcast =
2916                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2917
2918         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2919                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2920                             "VSI link shouldn't be NULL");
2921                 return NULL;
2922         }
2923
2924         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2925                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2926                             "uplink VSI should be NULL");
2927                 return NULL;
2928         }
2929
2930         /* If uplink vsi didn't setup VEB, create one first */
2931         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2932                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2933
2934                 if (NULL == uplink_vsi->veb) {
2935                         PMD_DRV_LOG(ERR, "VEB setup failed");
2936                         return NULL;
2937                 }
2938         }
2939
2940         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2941         if (!vsi) {
2942                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2943                 return NULL;
2944         }
2945         TAILQ_INIT(&vsi->mac_list);
2946         vsi->type = type;
2947         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2948         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2949         vsi->parent_vsi = uplink_vsi;
2950         vsi->user_param = user_param;
2951         /* Allocate queues */
2952         switch (vsi->type) {
2953         case I40E_VSI_MAIN  :
2954                 vsi->nb_qps = pf->lan_nb_qps;
2955                 break;
2956         case I40E_VSI_SRIOV :
2957                 vsi->nb_qps = pf->vf_nb_qps;
2958                 break;
2959         case I40E_VSI_VMDQ2:
2960                 vsi->nb_qps = pf->vmdq_nb_qps;
2961                 break;
2962         case I40E_VSI_FDIR:
2963                 vsi->nb_qps = pf->fdir_nb_qps;
2964                 break;
2965         default:
2966                 goto fail_mem;
2967         }
2968         /*
2969          * The filter status descriptor is reported in rx queue 0,
2970          * while the tx queue for fdir filter programming has no
2971          * such constraints, can be non-zero queues.
2972          * To simplify it, choose FDIR vsi use queue 0 pair.
2973          * To make sure it will use queue 0 pair, queue allocation
2974          * need be done before this function is called
2975          */
2976         if (type != I40E_VSI_FDIR) {
2977                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2978                         if (ret < 0) {
2979                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2980                                                 vsi->seid, ret);
2981                                 goto fail_mem;
2982                         }
2983                         vsi->base_queue = ret;
2984         } else
2985                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2986
2987         /* VF has MSIX interrupt in VF range, don't allocate here */
2988         if (type != I40E_VSI_SRIOV) {
2989                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2990                 if (ret < 0) {
2991                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2992                         goto fail_queue_alloc;
2993                 }
2994                 vsi->msix_intr = ret;
2995         } else
2996                 vsi->msix_intr = 0;
2997         /* Add VSI */
2998         if (type == I40E_VSI_MAIN) {
2999                 /* For main VSI, no need to add since it's default one */
3000                 vsi->uplink_seid = pf->mac_seid;
3001                 vsi->seid = pf->main_vsi_seid;
3002                 /* Bind queues with specific MSIX interrupt */
3003                 /**
3004                  * Needs 2 interrupt at least, one for misc cause which will
3005                  * enabled from OS side, Another for queues binding the
3006                  * interrupt from device side only.
3007                  */
3008
3009                 /* Get default VSI parameters from hardware */
3010                 memset(&ctxt, 0, sizeof(ctxt));
3011                 ctxt.seid = vsi->seid;
3012                 ctxt.pf_num = hw->pf_id;
3013                 ctxt.uplink_seid = vsi->uplink_seid;
3014                 ctxt.vf_num = 0;
3015                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3016                 if (ret != I40E_SUCCESS) {
3017                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3018                         goto fail_msix_alloc;
3019                 }
3020                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3021                         sizeof(struct i40e_aqc_vsi_properties_data));
3022                 vsi->vsi_id = ctxt.vsi_number;
3023                 vsi->info.valid_sections = 0;
3024
3025                 /* Configure tc, enabled TC0 only */
3026                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3027                         I40E_SUCCESS) {
3028                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3029                         goto fail_msix_alloc;
3030                 }
3031
3032                 /* TC, queue mapping */
3033                 memset(&ctxt, 0, sizeof(ctxt));
3034                 vsi->info.valid_sections |=
3035                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3036                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3037                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3038                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3039                         sizeof(struct i40e_aqc_vsi_properties_data));
3040                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3041                                                 I40E_DEFAULT_TCMAP);
3042                 if (ret != I40E_SUCCESS) {
3043                         PMD_DRV_LOG(ERR, "Failed to configure "
3044                                     "TC queue mapping");
3045                         goto fail_msix_alloc;
3046                 }
3047                 ctxt.seid = vsi->seid;
3048                 ctxt.pf_num = hw->pf_id;
3049                 ctxt.uplink_seid = vsi->uplink_seid;
3050                 ctxt.vf_num = 0;
3051
3052                 /* Update VSI parameters */
3053                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3054                 if (ret != I40E_SUCCESS) {
3055                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3056                         goto fail_msix_alloc;
3057                 }
3058
3059                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3060                                                 sizeof(vsi->info.tc_mapping));
3061                 (void)rte_memcpy(&vsi->info.queue_mapping,
3062                                 &ctxt.info.queue_mapping,
3063                         sizeof(vsi->info.queue_mapping));
3064                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3065                 vsi->info.valid_sections = 0;
3066
3067                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3068                                 ETH_ADDR_LEN);
3069
3070                 /**
3071                  * Updating default filter settings are necessary to prevent
3072                  * reception of tagged packets.
3073                  * Some old firmware configurations load a default macvlan
3074                  * filter which accepts both tagged and untagged packets.
3075                  * The updating is to use a normal filter instead if needed.
3076                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3077                  * The firmware with correct configurations load the default
3078                  * macvlan filter which is expected and cannot be removed.
3079                  */
3080                 i40e_update_default_filter_setting(vsi);
3081                 i40e_config_qinq(hw, vsi);
3082         } else if (type == I40E_VSI_SRIOV) {
3083                 memset(&ctxt, 0, sizeof(ctxt));
3084                 /**
3085                  * For other VSI, the uplink_seid equals to uplink VSI's
3086                  * uplink_seid since they share same VEB
3087                  */
3088                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3089                 ctxt.pf_num = hw->pf_id;
3090                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3091                 ctxt.uplink_seid = vsi->uplink_seid;
3092                 ctxt.connection_type = 0x1;
3093                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3094
3095                 /**
3096                  * Do not configure switch ID to enable VEB switch by
3097                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3098                  * if the source mac address of packet sent from VF is not
3099                  * listed in the VEB's mac table, the VEB will switch the
3100                  * packet back to the VF. Need to enable it when HW issue
3101                  * is fixed.
3102                  */
3103
3104                 /* Configure port/vlan */
3105                 ctxt.info.valid_sections |=
3106                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3107                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3108                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3109                                                 I40E_DEFAULT_TCMAP);
3110                 if (ret != I40E_SUCCESS) {
3111                         PMD_DRV_LOG(ERR, "Failed to configure "
3112                                     "TC queue mapping");
3113                         goto fail_msix_alloc;
3114                 }
3115                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3116                 ctxt.info.valid_sections |=
3117                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3118                 /**
3119                  * Since VSI is not created yet, only configure parameter,
3120                  * will add vsi below.
3121                  */
3122
3123                 i40e_config_qinq(hw, vsi);
3124         } else if (type == I40E_VSI_VMDQ2) {
3125                 memset(&ctxt, 0, sizeof(ctxt));
3126                 /*
3127                  * For other VSI, the uplink_seid equals to uplink VSI's
3128                  * uplink_seid since they share same VEB
3129                  */
3130                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3131                 ctxt.pf_num = hw->pf_id;
3132                 ctxt.vf_num = 0;
3133                 ctxt.uplink_seid = vsi->uplink_seid;
3134                 ctxt.connection_type = 0x1;
3135                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3136
3137                 ctxt.info.valid_sections |=
3138                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3139                 /* user_param carries flag to enable loop back */
3140                 if (user_param) {
3141                         ctxt.info.switch_id =
3142                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3143                         ctxt.info.switch_id |=
3144                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3145                 }
3146
3147                 /* Configure port/vlan */
3148                 ctxt.info.valid_sections |=
3149                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3150                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3151                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3152                                                 I40E_DEFAULT_TCMAP);
3153                 if (ret != I40E_SUCCESS) {
3154                         PMD_DRV_LOG(ERR, "Failed to configure "
3155                                         "TC queue mapping");
3156                         goto fail_msix_alloc;
3157                 }
3158                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3159                 ctxt.info.valid_sections |=
3160                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3161         } else if (type == I40E_VSI_FDIR) {
3162                 memset(&ctxt, 0, sizeof(ctxt));
3163                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3164                 ctxt.pf_num = hw->pf_id;
3165                 ctxt.vf_num = 0;
3166                 ctxt.uplink_seid = vsi->uplink_seid;
3167                 ctxt.connection_type = 0x1;     /* regular data port */
3168                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3169                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3170                                                 I40E_DEFAULT_TCMAP);
3171                 if (ret != I40E_SUCCESS) {
3172                         PMD_DRV_LOG(ERR, "Failed to configure "
3173                                         "TC queue mapping.");
3174                         goto fail_msix_alloc;
3175                 }
3176                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3177                 ctxt.info.valid_sections |=
3178                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3179         } else {
3180                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3181                 goto fail_msix_alloc;
3182         }
3183
3184         if (vsi->type != I40E_VSI_MAIN) {
3185                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3186                 if (ret != I40E_SUCCESS) {
3187                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3188                                     hw->aq.asq_last_status);
3189                         goto fail_msix_alloc;
3190                 }
3191                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3192                 vsi->info.valid_sections = 0;
3193                 vsi->seid = ctxt.seid;
3194                 vsi->vsi_id = ctxt.vsi_number;
3195                 vsi->sib_vsi_list.vsi = vsi;
3196                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3197                                 &vsi->sib_vsi_list, list);
3198         }
3199
3200         /* MAC/VLAN configuration */
3201         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3202         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3203
3204         ret = i40e_vsi_add_mac(vsi, &filter);
3205         if (ret != I40E_SUCCESS) {
3206                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3207                 goto fail_msix_alloc;
3208         }
3209
3210         /* Get VSI BW information */
3211         i40e_vsi_dump_bw_config(vsi);
3212         return vsi;
3213 fail_msix_alloc:
3214         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3215 fail_queue_alloc:
3216         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3217 fail_mem:
3218         rte_free(vsi);
3219         return NULL;
3220 }
3221
3222 /* Configure vlan stripping on or off */
3223 int
3224 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3225 {
3226         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3227         struct i40e_vsi_context ctxt;
3228         uint8_t vlan_flags;
3229         int ret = I40E_SUCCESS;
3230
3231         /* Check if it has been already on or off */
3232         if (vsi->info.valid_sections &
3233                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3234                 if (on) {
3235                         if ((vsi->info.port_vlan_flags &
3236                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3237                                 return 0; /* already on */
3238                 } else {
3239                         if ((vsi->info.port_vlan_flags &
3240                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3241                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3242                                 return 0; /* already off */
3243                 }
3244         }
3245
3246         if (on)
3247                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3248         else
3249                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3250         vsi->info.valid_sections =
3251                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3252         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3253         vsi->info.port_vlan_flags |= vlan_flags;
3254         ctxt.seid = vsi->seid;
3255         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3256         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3257         if (ret)
3258                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3259                             on ? "enable" : "disable");
3260
3261         return ret;
3262 }
3263
3264 static int
3265 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3266 {
3267         struct rte_eth_dev_data *data = dev->data;
3268         int ret;
3269
3270         /* Apply vlan offload setting */
3271         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3272
3273         /* Apply double-vlan setting, not implemented yet */
3274
3275         /* Apply pvid setting */
3276         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3277                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3278         if (ret)
3279                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3280
3281         return ret;
3282 }
3283
3284 static int
3285 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3286 {
3287         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3288
3289         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3290 }
3291
3292 static int
3293 i40e_update_flow_control(struct i40e_hw *hw)
3294 {
3295 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3296         struct i40e_link_status link_status;
3297         uint32_t rxfc = 0, txfc = 0, reg;
3298         uint8_t an_info;
3299         int ret;
3300
3301         memset(&link_status, 0, sizeof(link_status));
3302         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3303         if (ret != I40E_SUCCESS) {
3304                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3305                 goto write_reg; /* Disable flow control */
3306         }
3307
3308         an_info = hw->phy.link_info.an_info;
3309         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3310                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3311                 ret = I40E_ERR_NOT_READY;
3312                 goto write_reg; /* Disable flow control */
3313         }
3314         /**
3315          * If link auto negotiation is enabled, flow control needs to
3316          * be configured according to it
3317          */
3318         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3319         case I40E_LINK_PAUSE_RXTX:
3320                 rxfc = 1;
3321                 txfc = 1;
3322                 hw->fc.current_mode = I40E_FC_FULL;
3323                 break;
3324         case I40E_AQ_LINK_PAUSE_RX:
3325                 rxfc = 1;
3326                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3327                 break;
3328         case I40E_AQ_LINK_PAUSE_TX:
3329                 txfc = 1;
3330                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3331                 break;
3332         default:
3333                 hw->fc.current_mode = I40E_FC_NONE;
3334                 break;
3335         }
3336
3337 write_reg:
3338         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3339                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3340         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3341         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3342         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3343         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3344
3345         return ret;
3346 }
3347
3348 /* PF setup */
3349 static int
3350 i40e_pf_setup(struct i40e_pf *pf)
3351 {
3352         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3353         struct i40e_filter_control_settings settings;
3354         struct i40e_vsi *vsi;
3355         int ret;
3356
3357         /* Clear all stats counters */
3358         pf->offset_loaded = FALSE;
3359         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3360         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3361
3362         ret = i40e_pf_get_switch_config(pf);
3363         if (ret != I40E_SUCCESS) {
3364                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3365                 return ret;
3366         }
3367         if (pf->flags & I40E_FLAG_FDIR) {
3368                 /* make queue allocated first, let FDIR use queue pair 0*/
3369                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3370                 if (ret != I40E_FDIR_QUEUE_ID) {
3371                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3372                                     " ret =%d", ret);
3373                         pf->flags &= ~I40E_FLAG_FDIR;
3374                 }
3375         }
3376         /*  main VSI setup */
3377         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3378         if (!vsi) {
3379                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3380                 return I40E_ERR_NOT_READY;
3381         }
3382         pf->main_vsi = vsi;
3383
3384         /* Configure filter control */
3385         memset(&settings, 0, sizeof(settings));
3386         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3387                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3388         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3389                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3390         else {
3391                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3392                                                 hw->func_caps.rss_table_size);
3393                 return I40E_ERR_PARAM;
3394         }
3395         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3396                         "size: %u\n", hw->func_caps.rss_table_size);
3397         pf->hash_lut_size = hw->func_caps.rss_table_size;
3398
3399         /* Enable ethtype and macvlan filters */
3400         settings.enable_ethtype = TRUE;
3401         settings.enable_macvlan = TRUE;
3402         ret = i40e_set_filter_control(hw, &settings);
3403         if (ret)
3404                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3405                                                                 ret);
3406
3407         /* Update flow control according to the auto negotiation */
3408         i40e_update_flow_control(hw);
3409
3410         return I40E_SUCCESS;
3411 }
3412
3413 int
3414 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3415 {
3416         uint32_t reg;
3417         uint16_t j;
3418
3419         /**
3420          * Set or clear TX Queue Disable flags,
3421          * which is required by hardware.
3422          */
3423         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3424         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3425
3426         /* Wait until the request is finished */
3427         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3428                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3429                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3430                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3431                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3432                                                         & 0x1))) {
3433                         break;
3434                 }
3435         }
3436         if (on) {
3437                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3438                         return I40E_SUCCESS; /* already on, skip next steps */
3439
3440                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3441                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3442         } else {
3443                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3444                         return I40E_SUCCESS; /* already off, skip next steps */
3445                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3446         }
3447         /* Write the register */
3448         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3449         /* Check the result */
3450         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3451                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3452                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3453                 if (on) {
3454                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3455                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3456                                 break;
3457                 } else {
3458                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3459                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3460                                 break;
3461                 }
3462         }
3463         /* Check if it is timeout */
3464         if (j >= I40E_CHK_Q_ENA_COUNT) {
3465                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3466                             (on ? "enable" : "disable"), q_idx);
3467                 return I40E_ERR_TIMEOUT;
3468         }
3469
3470         return I40E_SUCCESS;
3471 }
3472
3473 /* Swith on or off the tx queues */
3474 static int
3475 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3476 {
3477         struct rte_eth_dev_data *dev_data = pf->dev_data;
3478         struct i40e_tx_queue *txq;
3479         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3480         uint16_t i;
3481         int ret;
3482
3483         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3484                 txq = dev_data->tx_queues[i];
3485                 /* Don't operate the queue if not configured or
3486                  * if starting only per queue */
3487                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3488                         continue;
3489                 if (on)
3490                         ret = i40e_dev_tx_queue_start(dev, i);
3491                 else
3492                         ret = i40e_dev_tx_queue_stop(dev, i);
3493                 if ( ret != I40E_SUCCESS)
3494                         return ret;
3495         }
3496
3497         return I40E_SUCCESS;
3498 }
3499
3500 int
3501 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3502 {
3503         uint32_t reg;
3504         uint16_t j;
3505
3506         /* Wait until the request is finished */
3507         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3508                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3509                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3510                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3511                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3512                         break;
3513         }
3514
3515         if (on) {
3516                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3517                         return I40E_SUCCESS; /* Already on, skip next steps */
3518                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3519         } else {
3520                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3521                         return I40E_SUCCESS; /* Already off, skip next steps */
3522                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3523         }
3524
3525         /* Write the register */
3526         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3527         /* Check the result */
3528         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3529                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3530                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3531                 if (on) {
3532                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3533                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3534                                 break;
3535                 } else {
3536                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3537                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3538                                 break;
3539                 }
3540         }
3541
3542         /* Check if it is timeout */
3543         if (j >= I40E_CHK_Q_ENA_COUNT) {
3544                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3545                             (on ? "enable" : "disable"), q_idx);
3546                 return I40E_ERR_TIMEOUT;
3547         }
3548
3549         return I40E_SUCCESS;
3550 }
3551 /* Switch on or off the rx queues */
3552 static int
3553 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3554 {
3555         struct rte_eth_dev_data *dev_data = pf->dev_data;
3556         struct i40e_rx_queue *rxq;
3557         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3558         uint16_t i;
3559         int ret;
3560
3561         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3562                 rxq = dev_data->rx_queues[i];
3563                 /* Don't operate the queue if not configured or
3564                  * if starting only per queue */
3565                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3566                         continue;
3567                 if (on)
3568                         ret = i40e_dev_rx_queue_start(dev, i);
3569                 else
3570                         ret = i40e_dev_rx_queue_stop(dev, i);
3571                 if (ret != I40E_SUCCESS)
3572                         return ret;
3573         }
3574
3575         return I40E_SUCCESS;
3576 }
3577
3578 /* Switch on or off all the rx/tx queues */
3579 int
3580 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3581 {
3582         int ret;
3583
3584         if (on) {
3585                 /* enable rx queues before enabling tx queues */
3586                 ret = i40e_dev_switch_rx_queues(pf, on);
3587                 if (ret) {
3588                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3589                         return ret;
3590                 }
3591                 ret = i40e_dev_switch_tx_queues(pf, on);
3592         } else {
3593                 /* Stop tx queues before stopping rx queues */
3594                 ret = i40e_dev_switch_tx_queues(pf, on);
3595                 if (ret) {
3596                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3597                         return ret;
3598                 }
3599                 ret = i40e_dev_switch_rx_queues(pf, on);
3600         }
3601
3602         return ret;
3603 }
3604
3605 /* Initialize VSI for TX */
3606 static int
3607 i40e_dev_tx_init(struct i40e_pf *pf)
3608 {
3609         struct rte_eth_dev_data *data = pf->dev_data;
3610         uint16_t i;
3611         uint32_t ret = I40E_SUCCESS;
3612         struct i40e_tx_queue *txq;
3613
3614         for (i = 0; i < data->nb_tx_queues; i++) {
3615                 txq = data->tx_queues[i];
3616                 if (!txq || !txq->q_set)
3617                         continue;
3618                 ret = i40e_tx_queue_init(txq);
3619                 if (ret != I40E_SUCCESS)
3620                         break;
3621         }
3622
3623         return ret;
3624 }
3625
3626 /* Initialize VSI for RX */
3627 static int
3628 i40e_dev_rx_init(struct i40e_pf *pf)
3629 {
3630         struct rte_eth_dev_data *data = pf->dev_data;
3631         int ret = I40E_SUCCESS;
3632         uint16_t i;
3633         struct i40e_rx_queue *rxq;
3634
3635         i40e_pf_config_mq_rx(pf);
3636         for (i = 0; i < data->nb_rx_queues; i++) {
3637                 rxq = data->rx_queues[i];
3638                 if (!rxq || !rxq->q_set)
3639                         continue;
3640
3641                 ret = i40e_rx_queue_init(rxq);
3642                 if (ret != I40E_SUCCESS) {
3643                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3644                                     "initialization");
3645                         break;
3646                 }
3647         }
3648
3649         return ret;
3650 }
3651
3652 static int
3653 i40e_dev_rxtx_init(struct i40e_pf *pf)
3654 {
3655         int err;
3656
3657         err = i40e_dev_tx_init(pf);
3658         if (err) {
3659                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3660                 return err;
3661         }
3662         err = i40e_dev_rx_init(pf);
3663         if (err) {
3664                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3665                 return err;
3666         }
3667
3668         return err;
3669 }
3670
3671 static int
3672 i40e_vmdq_setup(struct rte_eth_dev *dev)
3673 {
3674         struct rte_eth_conf *conf = &dev->data->dev_conf;
3675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3676         int i, err, conf_vsis, j, loop;
3677         struct i40e_vsi *vsi;
3678         struct i40e_vmdq_info *vmdq_info;
3679         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3680         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3681
3682         /*
3683          * Disable interrupt to avoid message from VF. Furthermore, it will
3684          * avoid race condition in VSI creation/destroy.
3685          */
3686         i40e_pf_disable_irq0(hw);
3687
3688         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3689                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3690                 return -ENOTSUP;
3691         }
3692
3693         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3694         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3695                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3696                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3697                         pf->max_nb_vmdq_vsi);
3698                 return -ENOTSUP;
3699         }
3700
3701         if (pf->vmdq != NULL) {
3702                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3703                 return 0;
3704         }
3705
3706         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3707                                 sizeof(*vmdq_info) * conf_vsis, 0);
3708
3709         if (pf->vmdq == NULL) {
3710                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3711                 return -ENOMEM;
3712         }
3713
3714         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3715
3716         /* Create VMDQ VSI */
3717         for (i = 0; i < conf_vsis; i++) {
3718                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3719                                 vmdq_conf->enable_loop_back);
3720                 if (vsi == NULL) {
3721                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3722                         err = -1;
3723                         goto err_vsi_setup;
3724                 }
3725                 vmdq_info = &pf->vmdq[i];
3726                 vmdq_info->pf = pf;
3727                 vmdq_info->vsi = vsi;
3728         }
3729         pf->nb_cfg_vmdq_vsi = conf_vsis;
3730
3731         /* Configure Vlan */
3732         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3733         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3734                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3735                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3736                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3737                                         vmdq_conf->pool_map[i].vlan_id, j);
3738
3739                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3740                                                 vmdq_conf->pool_map[i].vlan_id);
3741                                 if (err) {
3742                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3743                                         err = -1;
3744                                         goto err_vsi_setup;
3745                                 }
3746                         }
3747                 }
3748         }
3749
3750         i40e_pf_enable_irq0(hw);
3751
3752         return 0;
3753
3754 err_vsi_setup:
3755         for (i = 0; i < conf_vsis; i++)
3756                 if (pf->vmdq[i].vsi == NULL)
3757                         break;
3758                 else
3759                         i40e_vsi_release(pf->vmdq[i].vsi);
3760
3761         rte_free(pf->vmdq);
3762         pf->vmdq = NULL;
3763         i40e_pf_enable_irq0(hw);
3764         return err;
3765 }
3766
3767 static void
3768 i40e_stat_update_32(struct i40e_hw *hw,
3769                    uint32_t reg,
3770                    bool offset_loaded,
3771                    uint64_t *offset,
3772                    uint64_t *stat)
3773 {
3774         uint64_t new_data;
3775
3776         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3777         if (!offset_loaded)
3778                 *offset = new_data;
3779
3780         if (new_data >= *offset)
3781                 *stat = (uint64_t)(new_data - *offset);
3782         else
3783                 *stat = (uint64_t)((new_data +
3784                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3785 }
3786
3787 static void
3788 i40e_stat_update_48(struct i40e_hw *hw,
3789                    uint32_t hireg,
3790                    uint32_t loreg,
3791                    bool offset_loaded,
3792                    uint64_t *offset,
3793                    uint64_t *stat)
3794 {
3795         uint64_t new_data;
3796
3797         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3798         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3799                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3800
3801         if (!offset_loaded)
3802                 *offset = new_data;
3803
3804         if (new_data >= *offset)
3805                 *stat = new_data - *offset;
3806         else
3807                 *stat = (uint64_t)((new_data +
3808                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3809
3810         *stat &= I40E_48_BIT_MASK;
3811 }
3812
3813 /* Disable IRQ0 */
3814 void
3815 i40e_pf_disable_irq0(struct i40e_hw *hw)
3816 {
3817         /* Disable all interrupt types */
3818         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3819         I40E_WRITE_FLUSH(hw);
3820 }
3821
3822 /* Enable IRQ0 */
3823 void
3824 i40e_pf_enable_irq0(struct i40e_hw *hw)
3825 {
3826         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3827                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3828                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3829                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3830         I40E_WRITE_FLUSH(hw);
3831 }
3832
3833 static void
3834 i40e_pf_config_irq0(struct i40e_hw *hw)
3835 {
3836         /* read pending request and disable first */
3837         i40e_pf_disable_irq0(hw);
3838         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3839         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3840                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3841
3842         /* Link no queues with irq0 */
3843         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3844                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3845 }
3846
3847 static void
3848 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3849 {
3850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3852         int i;
3853         uint16_t abs_vf_id;
3854         uint32_t index, offset, val;
3855
3856         if (!pf->vfs)
3857                 return;
3858         /**
3859          * Try to find which VF trigger a reset, use absolute VF id to access
3860          * since the reg is global register.
3861          */
3862         for (i = 0; i < pf->vf_num; i++) {
3863                 abs_vf_id = hw->func_caps.vf_base_id + i;
3864                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3865                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3866                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3867                 /* VFR event occured */
3868                 if (val & (0x1 << offset)) {
3869                         int ret;
3870
3871                         /* Clear the event first */
3872                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3873                                                         (0x1 << offset));
3874                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3875                         /**
3876                          * Only notify a VF reset event occured,
3877                          * don't trigger another SW reset
3878                          */
3879                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3880                         if (ret != I40E_SUCCESS)
3881                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3882                 }
3883         }
3884 }
3885
3886 static void
3887 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3888 {
3889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3890         struct i40e_arq_event_info info;
3891         uint16_t pending, opcode;
3892         int ret;
3893
3894         info.buf_len = I40E_AQ_BUF_SZ;
3895         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3896         if (!info.msg_buf) {
3897                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3898                 return;
3899         }
3900
3901         pending = 1;
3902         while (pending) {
3903                 ret = i40e_clean_arq_element(hw, &info, &pending);
3904
3905                 if (ret != I40E_SUCCESS) {
3906                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3907                                     "aq_err: %u", hw->aq.asq_last_status);
3908                         break;
3909                 }
3910                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3911
3912                 switch (opcode) {
3913                 case i40e_aqc_opc_send_msg_to_pf:
3914                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3915                         i40e_pf_host_handle_vf_msg(dev,
3916                                         rte_le_to_cpu_16(info.desc.retval),
3917                                         rte_le_to_cpu_32(info.desc.cookie_high),
3918                                         rte_le_to_cpu_32(info.desc.cookie_low),
3919                                         info.msg_buf,
3920                                         info.msg_len);
3921                         break;
3922                 default:
3923                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3924                                     opcode);
3925                         break;
3926                 }
3927         }
3928         rte_free(info.msg_buf);
3929 }
3930
3931 /*
3932  * Interrupt handler is registered as the alarm callback for handling LSC
3933  * interrupt in a definite of time, in order to wait the NIC into a stable
3934  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3935  * no need for link down interrupt.
3936  */
3937 static void
3938 i40e_dev_interrupt_delayed_handler(void *param)
3939 {
3940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3942         uint32_t icr0;
3943
3944         /* read interrupt causes again */
3945         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3946
3947 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3948         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3949                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3950         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3951                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3952         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3953                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3954         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3955                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3956         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3957                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3958                                                                 "state\n");
3959         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3960                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3961         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3962                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3963 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3964
3965         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3966                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3967                 i40e_dev_handle_vfr_event(dev);
3968         }
3969         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3970                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3971                 i40e_dev_handle_aq_msg(dev);
3972         }
3973
3974         /* handle the link up interrupt in an alarm callback */
3975         i40e_dev_link_update(dev, 0);
3976         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3977
3978         i40e_pf_enable_irq0(hw);
3979         rte_intr_enable(&(dev->pci_dev->intr_handle));
3980 }
3981
3982 /**
3983  * Interrupt handler triggered by NIC  for handling
3984  * specific interrupt.
3985  *
3986  * @param handle
3987  *  Pointer to interrupt handle.
3988  * @param param
3989  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3990  *
3991  * @return
3992  *  void
3993  */
3994 static void
3995 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3996                            void *param)
3997 {
3998         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000         uint32_t icr0;
4001
4002         /* Disable interrupt */
4003         i40e_pf_disable_irq0(hw);
4004
4005         /* read out interrupt causes */
4006         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4007
4008         /* No interrupt event indicated */
4009         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4010                 PMD_DRV_LOG(INFO, "No interrupt event");
4011                 goto done;
4012         }
4013 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4014         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4015                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4016         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4017                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4018         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4019                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4020         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4021                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4022         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4023                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4024         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4025                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4026         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4027                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4028 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4029
4030         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4031                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4032                 i40e_dev_handle_vfr_event(dev);
4033         }
4034         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4035                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4036                 i40e_dev_handle_aq_msg(dev);
4037         }
4038
4039         /* Link Status Change interrupt */
4040         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4041 #define I40E_US_PER_SECOND 1000000
4042                 struct rte_eth_link link;
4043
4044                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4045                 memset(&link, 0, sizeof(link));
4046                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4047                 i40e_dev_link_update(dev, 0);
4048
4049                 /*
4050                  * For link up interrupt, it needs to wait 1 second to let the
4051                  * hardware be a stable state. Otherwise several consecutive
4052                  * interrupts can be observed.
4053                  * For link down interrupt, no need to wait.
4054                  */
4055                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4056                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4057                         return;
4058                 else
4059                         _rte_eth_dev_callback_process(dev,
4060                                 RTE_ETH_EVENT_INTR_LSC);
4061         }
4062
4063 done:
4064         /* Enable interrupt */
4065         i40e_pf_enable_irq0(hw);
4066         rte_intr_enable(&(dev->pci_dev->intr_handle));
4067 }
4068
4069 static int
4070 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4071                          struct i40e_macvlan_filter *filter,
4072                          int total)
4073 {
4074         int ele_num, ele_buff_size;
4075         int num, actual_num, i;
4076         uint16_t flags;
4077         int ret = I40E_SUCCESS;
4078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4079         struct i40e_aqc_add_macvlan_element_data *req_list;
4080
4081         if (filter == NULL  || total == 0)
4082                 return I40E_ERR_PARAM;
4083         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4084         ele_buff_size = hw->aq.asq_buf_size;
4085
4086         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4087         if (req_list == NULL) {
4088                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4089                 return I40E_ERR_NO_MEMORY;
4090         }
4091
4092         num = 0;
4093         do {
4094                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4095                 memset(req_list, 0, ele_buff_size);
4096
4097                 for (i = 0; i < actual_num; i++) {
4098                         (void)rte_memcpy(req_list[i].mac_addr,
4099                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4100                         req_list[i].vlan_tag =
4101                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4102
4103                         switch (filter[num + i].filter_type) {
4104                         case RTE_MAC_PERFECT_MATCH:
4105                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4106                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4107                                 break;
4108                         case RTE_MACVLAN_PERFECT_MATCH:
4109                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4110                                 break;
4111                         case RTE_MAC_HASH_MATCH:
4112                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4113                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4114                                 break;
4115                         case RTE_MACVLAN_HASH_MATCH:
4116                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4117                                 break;
4118                         default:
4119                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4120                                 ret = I40E_ERR_PARAM;
4121                                 goto DONE;
4122                         }
4123
4124                         req_list[i].queue_number = 0;
4125
4126                         req_list[i].flags = rte_cpu_to_le_16(flags);
4127                 }
4128
4129                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4130                                                 actual_num, NULL);
4131                 if (ret != I40E_SUCCESS) {
4132                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4133                         goto DONE;
4134                 }
4135                 num += actual_num;
4136         } while (num < total);
4137
4138 DONE:
4139         rte_free(req_list);
4140         return ret;
4141 }
4142
4143 static int
4144 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4145                             struct i40e_macvlan_filter *filter,
4146                             int total)
4147 {
4148         int ele_num, ele_buff_size;
4149         int num, actual_num, i;
4150         uint16_t flags;
4151         int ret = I40E_SUCCESS;
4152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4153         struct i40e_aqc_remove_macvlan_element_data *req_list;
4154
4155         if (filter == NULL  || total == 0)
4156                 return I40E_ERR_PARAM;
4157
4158         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4159         ele_buff_size = hw->aq.asq_buf_size;
4160
4161         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4162         if (req_list == NULL) {
4163                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4164                 return I40E_ERR_NO_MEMORY;
4165         }
4166
4167         num = 0;
4168         do {
4169                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4170                 memset(req_list, 0, ele_buff_size);
4171
4172                 for (i = 0; i < actual_num; i++) {
4173                         (void)rte_memcpy(req_list[i].mac_addr,
4174                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4175                         req_list[i].vlan_tag =
4176                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4177
4178                         switch (filter[num + i].filter_type) {
4179                         case RTE_MAC_PERFECT_MATCH:
4180                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4181                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4182                                 break;
4183                         case RTE_MACVLAN_PERFECT_MATCH:
4184                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4185                                 break;
4186                         case RTE_MAC_HASH_MATCH:
4187                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4188                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4189                                 break;
4190                         case RTE_MACVLAN_HASH_MATCH:
4191                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4192                                 break;
4193                         default:
4194                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4195                                 ret = I40E_ERR_PARAM;
4196                                 goto DONE;
4197                         }
4198                         req_list[i].flags = rte_cpu_to_le_16(flags);
4199                 }
4200
4201                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4202                                                 actual_num, NULL);
4203                 if (ret != I40E_SUCCESS) {
4204                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4205                         goto DONE;
4206                 }
4207                 num += actual_num;
4208         } while (num < total);
4209
4210 DONE:
4211         rte_free(req_list);
4212         return ret;
4213 }
4214
4215 /* Find out specific MAC filter */
4216 static struct i40e_mac_filter *
4217 i40e_find_mac_filter(struct i40e_vsi *vsi,
4218                          struct ether_addr *macaddr)
4219 {
4220         struct i40e_mac_filter *f;
4221
4222         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4223                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4224                         return f;
4225         }
4226
4227         return NULL;
4228 }
4229
4230 static bool
4231 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4232                          uint16_t vlan_id)
4233 {
4234         uint32_t vid_idx, vid_bit;
4235
4236         if (vlan_id > ETH_VLAN_ID_MAX)
4237                 return 0;
4238
4239         vid_idx = I40E_VFTA_IDX(vlan_id);
4240         vid_bit = I40E_VFTA_BIT(vlan_id);
4241
4242         if (vsi->vfta[vid_idx] & vid_bit)
4243                 return 1;
4244         else
4245                 return 0;
4246 }
4247
4248 static void
4249 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4250                          uint16_t vlan_id, bool on)
4251 {
4252         uint32_t vid_idx, vid_bit;
4253
4254         if (vlan_id > ETH_VLAN_ID_MAX)
4255                 return;
4256
4257         vid_idx = I40E_VFTA_IDX(vlan_id);
4258         vid_bit = I40E_VFTA_BIT(vlan_id);
4259
4260         if (on)
4261                 vsi->vfta[vid_idx] |= vid_bit;
4262         else
4263                 vsi->vfta[vid_idx] &= ~vid_bit;
4264 }
4265
4266 /**
4267  * Find all vlan options for specific mac addr,
4268  * return with actual vlan found.
4269  */
4270 static inline int
4271 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4272                            struct i40e_macvlan_filter *mv_f,
4273                            int num, struct ether_addr *addr)
4274 {
4275         int i;
4276         uint32_t j, k;
4277
4278         /**
4279          * Not to use i40e_find_vlan_filter to decrease the loop time,
4280          * although the code looks complex.
4281           */
4282         if (num < vsi->vlan_num)
4283                 return I40E_ERR_PARAM;
4284
4285         i = 0;
4286         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4287                 if (vsi->vfta[j]) {
4288                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4289                                 if (vsi->vfta[j] & (1 << k)) {
4290                                         if (i > num - 1) {
4291                                                 PMD_DRV_LOG(ERR, "vlan number "
4292                                                             "not match");
4293                                                 return I40E_ERR_PARAM;
4294                                         }
4295                                         (void)rte_memcpy(&mv_f[i].macaddr,
4296                                                         addr, ETH_ADDR_LEN);
4297                                         mv_f[i].vlan_id =
4298                                                 j * I40E_UINT32_BIT_SIZE + k;
4299                                         i++;
4300                                 }
4301                         }
4302                 }
4303         }
4304         return I40E_SUCCESS;
4305 }
4306
4307 static inline int
4308 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4309                            struct i40e_macvlan_filter *mv_f,
4310                            int num,
4311                            uint16_t vlan)
4312 {
4313         int i = 0;
4314         struct i40e_mac_filter *f;
4315
4316         if (num < vsi->mac_num)
4317                 return I40E_ERR_PARAM;
4318
4319         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4320                 if (i > num - 1) {
4321                         PMD_DRV_LOG(ERR, "buffer number not match");
4322                         return I40E_ERR_PARAM;
4323                 }
4324                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4325                                 ETH_ADDR_LEN);
4326                 mv_f[i].vlan_id = vlan;
4327                 mv_f[i].filter_type = f->mac_info.filter_type;
4328                 i++;
4329         }
4330
4331         return I40E_SUCCESS;
4332 }
4333
4334 static int
4335 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4336 {
4337         int i, num;
4338         struct i40e_mac_filter *f;
4339         struct i40e_macvlan_filter *mv_f;
4340         int ret = I40E_SUCCESS;
4341
4342         if (vsi == NULL || vsi->mac_num == 0)
4343                 return I40E_ERR_PARAM;
4344
4345         /* Case that no vlan is set */
4346         if (vsi->vlan_num == 0)
4347                 num = vsi->mac_num;
4348         else
4349                 num = vsi->mac_num * vsi->vlan_num;
4350
4351         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4352         if (mv_f == NULL) {
4353                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4354                 return I40E_ERR_NO_MEMORY;
4355         }
4356
4357         i = 0;
4358         if (vsi->vlan_num == 0) {
4359                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4360                         (void)rte_memcpy(&mv_f[i].macaddr,
4361                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4362                         mv_f[i].vlan_id = 0;
4363                         i++;
4364                 }
4365         } else {
4366                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4367                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4368                                         vsi->vlan_num, &f->mac_info.mac_addr);
4369                         if (ret != I40E_SUCCESS)
4370                                 goto DONE;
4371                         i += vsi->vlan_num;
4372                 }
4373         }
4374
4375         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4376 DONE:
4377         rte_free(mv_f);
4378
4379         return ret;
4380 }
4381
4382 int
4383 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4384 {
4385         struct i40e_macvlan_filter *mv_f;
4386         int mac_num;
4387         int ret = I40E_SUCCESS;
4388
4389         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4390                 return I40E_ERR_PARAM;
4391
4392         /* If it's already set, just return */
4393         if (i40e_find_vlan_filter(vsi,vlan))
4394                 return I40E_SUCCESS;
4395
4396         mac_num = vsi->mac_num;
4397
4398         if (mac_num == 0) {
4399                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4400                 return I40E_ERR_PARAM;
4401         }
4402
4403         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4404
4405         if (mv_f == NULL) {
4406                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4407                 return I40E_ERR_NO_MEMORY;
4408         }
4409
4410         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4411
4412         if (ret != I40E_SUCCESS)
4413                 goto DONE;
4414
4415         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4416
4417         if (ret != I40E_SUCCESS)
4418                 goto DONE;
4419
4420         i40e_set_vlan_filter(vsi, vlan, 1);
4421
4422         vsi->vlan_num++;
4423         ret = I40E_SUCCESS;
4424 DONE:
4425         rte_free(mv_f);
4426         return ret;
4427 }
4428
4429 int
4430 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4431 {
4432         struct i40e_macvlan_filter *mv_f;
4433         int mac_num;
4434         int ret = I40E_SUCCESS;
4435
4436         /**
4437          * Vlan 0 is the generic filter for untagged packets
4438          * and can't be removed.
4439          */
4440         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4441                 return I40E_ERR_PARAM;
4442
4443         /* If can't find it, just return */
4444         if (!i40e_find_vlan_filter(vsi, vlan))
4445                 return I40E_ERR_PARAM;
4446
4447         mac_num = vsi->mac_num;
4448
4449         if (mac_num == 0) {
4450                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4451                 return I40E_ERR_PARAM;
4452         }
4453
4454         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4455
4456         if (mv_f == NULL) {
4457                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4458                 return I40E_ERR_NO_MEMORY;
4459         }
4460
4461         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4462
4463         if (ret != I40E_SUCCESS)
4464                 goto DONE;
4465
4466         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4467
4468         if (ret != I40E_SUCCESS)
4469                 goto DONE;
4470
4471         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4472         if (vsi->vlan_num == 1) {
4473                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4474                 if (ret != I40E_SUCCESS)
4475                         goto DONE;
4476
4477                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4478                 if (ret != I40E_SUCCESS)
4479                         goto DONE;
4480         }
4481
4482         i40e_set_vlan_filter(vsi, vlan, 0);
4483
4484         vsi->vlan_num--;
4485         ret = I40E_SUCCESS;
4486 DONE:
4487         rte_free(mv_f);
4488         return ret;
4489 }
4490
4491 int
4492 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4493 {
4494         struct i40e_mac_filter *f;
4495         struct i40e_macvlan_filter *mv_f;
4496         int i, vlan_num = 0;
4497         int ret = I40E_SUCCESS;
4498
4499         /* If it's add and we've config it, return */
4500         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4501         if (f != NULL)
4502                 return I40E_SUCCESS;
4503         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4504                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4505
4506                 /**
4507                  * If vlan_num is 0, that's the first time to add mac,
4508                  * set mask for vlan_id 0.
4509                  */
4510                 if (vsi->vlan_num == 0) {
4511                         i40e_set_vlan_filter(vsi, 0, 1);
4512                         vsi->vlan_num = 1;
4513                 }
4514                 vlan_num = vsi->vlan_num;
4515         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4516                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4517                 vlan_num = 1;
4518
4519         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4520         if (mv_f == NULL) {
4521                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4522                 return I40E_ERR_NO_MEMORY;
4523         }
4524
4525         for (i = 0; i < vlan_num; i++) {
4526                 mv_f[i].filter_type = mac_filter->filter_type;
4527                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4528                                 ETH_ADDR_LEN);
4529         }
4530
4531         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4532                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4533                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4534                                         &mac_filter->mac_addr);
4535                 if (ret != I40E_SUCCESS)
4536                         goto DONE;
4537         }
4538
4539         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4540         if (ret != I40E_SUCCESS)
4541                 goto DONE;
4542
4543         /* Add the mac addr into mac list */
4544         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4545         if (f == NULL) {
4546                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4547                 ret = I40E_ERR_NO_MEMORY;
4548                 goto DONE;
4549         }
4550         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4551                         ETH_ADDR_LEN);
4552         f->mac_info.filter_type = mac_filter->filter_type;
4553         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4554         vsi->mac_num++;
4555
4556         ret = I40E_SUCCESS;
4557 DONE:
4558         rte_free(mv_f);
4559
4560         return ret;
4561 }
4562
4563 int
4564 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4565 {
4566         struct i40e_mac_filter *f;
4567         struct i40e_macvlan_filter *mv_f;
4568         int i, vlan_num;
4569         enum rte_mac_filter_type filter_type;
4570         int ret = I40E_SUCCESS;
4571
4572         /* Can't find it, return an error */
4573         f = i40e_find_mac_filter(vsi, addr);
4574         if (f == NULL)
4575                 return I40E_ERR_PARAM;
4576
4577         vlan_num = vsi->vlan_num;
4578         filter_type = f->mac_info.filter_type;
4579         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4580                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4581                 if (vlan_num == 0) {
4582                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4583                         return I40E_ERR_PARAM;
4584                 }
4585         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4586                         filter_type == RTE_MAC_HASH_MATCH)
4587                 vlan_num = 1;
4588
4589         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4590         if (mv_f == NULL) {
4591                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4592                 return I40E_ERR_NO_MEMORY;
4593         }
4594
4595         for (i = 0; i < vlan_num; i++) {
4596                 mv_f[i].filter_type = filter_type;
4597                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4598                                 ETH_ADDR_LEN);
4599         }
4600         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4601                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4602                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4603                 if (ret != I40E_SUCCESS)
4604                         goto DONE;
4605         }
4606
4607         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4608         if (ret != I40E_SUCCESS)
4609                 goto DONE;
4610
4611         /* Remove the mac addr into mac list */
4612         TAILQ_REMOVE(&vsi->mac_list, f, next);
4613         rte_free(f);
4614         vsi->mac_num--;
4615
4616         ret = I40E_SUCCESS;
4617 DONE:
4618         rte_free(mv_f);
4619         return ret;
4620 }
4621
4622 /* Configure hash enable flags for RSS */
4623 uint64_t
4624 i40e_config_hena(uint64_t flags)
4625 {
4626         uint64_t hena = 0;
4627
4628         if (!flags)
4629                 return hena;
4630
4631         if (flags & ETH_RSS_FRAG_IPV4)
4632                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4633         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4634                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4635         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4636                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4637         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4638                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4639         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4640                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4641         if (flags & ETH_RSS_FRAG_IPV6)
4642                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4643         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4644                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4645         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4646                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4647         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4648                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4649         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4650                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4651         if (flags & ETH_RSS_L2_PAYLOAD)
4652                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4653
4654         return hena;
4655 }
4656
4657 /* Parse the hash enable flags */
4658 uint64_t
4659 i40e_parse_hena(uint64_t flags)
4660 {
4661         uint64_t rss_hf = 0;
4662
4663         if (!flags)
4664                 return rss_hf;
4665         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4666                 rss_hf |= ETH_RSS_FRAG_IPV4;
4667         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4668                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4669         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4670                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4671         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4672                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4673         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4674                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4675         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4676                 rss_hf |= ETH_RSS_FRAG_IPV6;
4677         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4678                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4679         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4680                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4681         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4682                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4683         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4684                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4685         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4686                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4687
4688         return rss_hf;
4689 }
4690
4691 /* Disable RSS */
4692 static void
4693 i40e_pf_disable_rss(struct i40e_pf *pf)
4694 {
4695         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4696         uint64_t hena;
4697
4698         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4699         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4700         hena &= ~I40E_RSS_HENA_ALL;
4701         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4702         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4703         I40E_WRITE_FLUSH(hw);
4704 }
4705
4706 static int
4707 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4708 {
4709         uint32_t *hash_key;
4710         uint8_t hash_key_len;
4711         uint64_t rss_hf;
4712         uint16_t i;
4713         uint64_t hena;
4714
4715         hash_key = (uint32_t *)(rss_conf->rss_key);
4716         hash_key_len = rss_conf->rss_key_len;
4717         if (hash_key != NULL && hash_key_len >=
4718                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4719                 /* Fill in RSS hash key */
4720                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4721                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4722         }
4723
4724         rss_hf = rss_conf->rss_hf;
4725         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4726         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4727         hena &= ~I40E_RSS_HENA_ALL;
4728         hena |= i40e_config_hena(rss_hf);
4729         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4730         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4731         I40E_WRITE_FLUSH(hw);
4732
4733         return 0;
4734 }
4735
4736 static int
4737 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4738                          struct rte_eth_rss_conf *rss_conf)
4739 {
4740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4742         uint64_t hena;
4743
4744         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4745         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4746         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4747                 if (rss_hf != 0) /* Enable RSS */
4748                         return -EINVAL;
4749                 return 0; /* Nothing to do */
4750         }
4751         /* RSS enabled */
4752         if (rss_hf == 0) /* Disable RSS */
4753                 return -EINVAL;
4754
4755         return i40e_hw_rss_hash_set(hw, rss_conf);
4756 }
4757
4758 static int
4759 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4760                            struct rte_eth_rss_conf *rss_conf)
4761 {
4762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4763         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4764         uint64_t hena;
4765         uint16_t i;
4766
4767         if (hash_key != NULL) {
4768                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4769                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4770                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4771         }
4772         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4773         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4774         rss_conf->rss_hf = i40e_parse_hena(hena);
4775
4776         return 0;
4777 }
4778
4779 static int
4780 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4781 {
4782         switch (filter_type) {
4783         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4784                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4785                 break;
4786         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4787                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4788                 break;
4789         case RTE_TUNNEL_FILTER_IMAC_TENID:
4790                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4791                 break;
4792         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4793                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4794                 break;
4795         case ETH_TUNNEL_FILTER_IMAC:
4796                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4797                 break;
4798         default:
4799                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4800                 return -EINVAL;
4801         }
4802
4803         return 0;
4804 }
4805
4806 static int
4807 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4808                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4809                         uint8_t add)
4810 {
4811         uint16_t ip_type;
4812         uint8_t tun_type = 0;
4813         int val, ret = 0;
4814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4815         struct i40e_vsi *vsi = pf->main_vsi;
4816         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4817         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4818
4819         cld_filter = rte_zmalloc("tunnel_filter",
4820                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4821                 0);
4822
4823         if (NULL == cld_filter) {
4824                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4825                 return -EINVAL;
4826         }
4827         pfilter = cld_filter;
4828
4829         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4830                         sizeof(struct ether_addr));
4831         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4832                         sizeof(struct ether_addr));
4833
4834         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4835         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4836                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4837                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4838                                 &tunnel_filter->ip_addr,
4839                                 sizeof(pfilter->ipaddr.v4.data));
4840         } else {
4841                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4842                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4843                                 &tunnel_filter->ip_addr,
4844                                 sizeof(pfilter->ipaddr.v6.data));
4845         }
4846
4847         /* check tunneled type */
4848         switch (tunnel_filter->tunnel_type) {
4849         case RTE_TUNNEL_TYPE_VXLAN:
4850                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4851                 break;
4852         case RTE_TUNNEL_TYPE_NVGRE:
4853                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4854                 break;
4855         default:
4856                 /* Other tunnel types is not supported. */
4857                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4858                 rte_free(cld_filter);
4859                 return -EINVAL;
4860         }
4861
4862         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4863                                                 &pfilter->flags);
4864         if (val < 0) {
4865                 rte_free(cld_filter);
4866                 return -EINVAL;
4867         }
4868
4869         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4870                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4871         pfilter->tenant_id = tunnel_filter->tenant_id;
4872         pfilter->queue_number = tunnel_filter->queue_id;
4873
4874         if (add)
4875                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4876         else
4877                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4878                                                 cld_filter, 1);
4879
4880         rte_free(cld_filter);
4881         return ret;
4882 }
4883
4884 static int
4885 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4886 {
4887         uint8_t i;
4888
4889         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4890                 if (pf->vxlan_ports[i] == port)
4891                         return i;
4892         }
4893
4894         return -1;
4895 }
4896
4897 static int
4898 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4899 {
4900         int  idx, ret;
4901         uint8_t filter_idx;
4902         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4903
4904         idx = i40e_get_vxlan_port_idx(pf, port);
4905
4906         /* Check if port already exists */
4907         if (idx >= 0) {
4908                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4909                 return -EINVAL;
4910         }
4911
4912         /* Now check if there is space to add the new port */
4913         idx = i40e_get_vxlan_port_idx(pf, 0);
4914         if (idx < 0) {
4915                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4916                         "not adding port %d", port);
4917                 return -ENOSPC;
4918         }
4919
4920         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4921                                         &filter_idx, NULL);
4922         if (ret < 0) {
4923                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4924                 return -1;
4925         }
4926
4927         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4928                          port,  filter_idx);
4929
4930         /* New port: add it and mark its index in the bitmap */
4931         pf->vxlan_ports[idx] = port;
4932         pf->vxlan_bitmap |= (1 << idx);
4933
4934         if (!(pf->flags & I40E_FLAG_VXLAN))
4935                 pf->flags |= I40E_FLAG_VXLAN;
4936
4937         return 0;
4938 }
4939
4940 static int
4941 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4942 {
4943         int idx;
4944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4945
4946         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4947                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4948                 return -EINVAL;
4949         }
4950
4951         idx = i40e_get_vxlan_port_idx(pf, port);
4952
4953         if (idx < 0) {
4954                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4955                 return -EINVAL;
4956         }
4957
4958         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4959                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4960                 return -1;
4961         }
4962
4963         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4964                         port, idx);
4965
4966         pf->vxlan_ports[idx] = 0;
4967         pf->vxlan_bitmap &= ~(1 << idx);
4968
4969         if (!pf->vxlan_bitmap)
4970                 pf->flags &= ~I40E_FLAG_VXLAN;
4971
4972         return 0;
4973 }
4974
4975 /* Add UDP tunneling port */
4976 static int
4977 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4978                         struct rte_eth_udp_tunnel *udp_tunnel)
4979 {
4980         int ret = 0;
4981         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4982
4983         if (udp_tunnel == NULL)
4984                 return -EINVAL;
4985
4986         switch (udp_tunnel->prot_type) {
4987         case RTE_TUNNEL_TYPE_VXLAN:
4988                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4989                 break;
4990
4991         case RTE_TUNNEL_TYPE_GENEVE:
4992         case RTE_TUNNEL_TYPE_TEREDO:
4993                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4994                 ret = -1;
4995                 break;
4996
4997         default:
4998                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4999                 ret = -1;
5000                 break;
5001         }
5002
5003         return ret;
5004 }
5005
5006 /* Remove UDP tunneling port */
5007 static int
5008 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5009                         struct rte_eth_udp_tunnel *udp_tunnel)
5010 {
5011         int ret = 0;
5012         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5013
5014         if (udp_tunnel == NULL)
5015                 return -EINVAL;
5016
5017         switch (udp_tunnel->prot_type) {
5018         case RTE_TUNNEL_TYPE_VXLAN:
5019                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5020                 break;
5021         case RTE_TUNNEL_TYPE_GENEVE:
5022         case RTE_TUNNEL_TYPE_TEREDO:
5023                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5024                 ret = -1;
5025                 break;
5026         default:
5027                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5028                 ret = -1;
5029                 break;
5030         }
5031
5032         return ret;
5033 }
5034
5035 /* Calculate the maximum number of contiguous PF queues that are configured */
5036 static int
5037 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5038 {
5039         struct rte_eth_dev_data *data = pf->dev_data;
5040         int i, num;
5041         struct i40e_rx_queue *rxq;
5042
5043         num = 0;
5044         for (i = 0; i < pf->lan_nb_qps; i++) {
5045                 rxq = data->rx_queues[i];
5046                 if (rxq && rxq->q_set)
5047                         num++;
5048                 else
5049                         break;
5050         }
5051
5052         return num;
5053 }
5054
5055 /* Configure RSS */
5056 static int
5057 i40e_pf_config_rss(struct i40e_pf *pf)
5058 {
5059         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5060         struct rte_eth_rss_conf rss_conf;
5061         uint32_t i, lut = 0;
5062         uint16_t j, num;
5063
5064         /*
5065          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5066          * It's necessary to calulate the actual PF queues that are configured.
5067          */
5068         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5069                 num = i40e_pf_calc_configured_queues_num(pf);
5070                 num = i40e_align_floor(num);
5071         } else
5072                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5073
5074         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5075                         num);
5076
5077         if (num == 0) {
5078                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5079                 return -ENOTSUP;
5080         }
5081
5082         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5083                 if (j == num)
5084                         j = 0;
5085                 lut = (lut << 8) | (j & ((0x1 <<
5086                         hw->func_caps.rss_table_entry_width) - 1));
5087                 if ((i & 3) == 3)
5088                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5089         }
5090
5091         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5092         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5093                 i40e_pf_disable_rss(pf);
5094                 return 0;
5095         }
5096         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5097                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5098                 /* Random default keys */
5099                 static uint32_t rss_key_default[] = {0x6b793944,
5100                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5101                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5102                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5103
5104                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5105                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5106                                                         sizeof(uint32_t);
5107         }
5108
5109         return i40e_hw_rss_hash_set(hw, &rss_conf);
5110 }
5111
5112 static int
5113 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5114                         struct rte_eth_tunnel_filter_conf *filter)
5115 {
5116         if (pf == NULL || filter == NULL) {
5117                 PMD_DRV_LOG(ERR, "Invalid parameter");
5118                 return -EINVAL;
5119         }
5120
5121         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5122                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5123                 return -EINVAL;
5124         }
5125
5126         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5127                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5128                 return -EINVAL;
5129         }
5130
5131         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5132                 (is_zero_ether_addr(filter->outer_mac))) {
5133                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5134                 return -EINVAL;
5135         }
5136
5137         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5138                 (is_zero_ether_addr(filter->inner_mac))) {
5139                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5140                 return -EINVAL;
5141         }
5142
5143         return 0;
5144 }
5145
5146 static int
5147 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5148                         void *arg)
5149 {
5150         struct rte_eth_tunnel_filter_conf *filter;
5151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5152         int ret = I40E_SUCCESS;
5153
5154         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5155
5156         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5157                 return I40E_ERR_PARAM;
5158
5159         switch (filter_op) {
5160         case RTE_ETH_FILTER_NOP:
5161                 if (!(pf->flags & I40E_FLAG_VXLAN))
5162                         ret = I40E_NOT_SUPPORTED;
5163         case RTE_ETH_FILTER_ADD:
5164                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5165                 break;
5166         case RTE_ETH_FILTER_DELETE:
5167                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5168                 break;
5169         default:
5170                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5171                 ret = I40E_ERR_PARAM;
5172                 break;
5173         }
5174
5175         return ret;
5176 }
5177
5178 static int
5179 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5180 {
5181         int ret = 0;
5182         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5183
5184         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5185                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5186                 return -ENOTSUP;
5187         }
5188
5189         /* RSS setup */
5190         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5191                 ret = i40e_pf_config_rss(pf);
5192         else
5193                 i40e_pf_disable_rss(pf);
5194
5195         return ret;
5196 }
5197
5198 /* Get the symmetric hash enable configurations per port */
5199 static void
5200 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5201 {
5202         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5203
5204         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5205 }
5206
5207 /* Set the symmetric hash enable configurations per port */
5208 static void
5209 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5210 {
5211         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5212
5213         if (enable > 0) {
5214                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5215                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5216                                                         "been enabled");
5217                         return;
5218                 }
5219                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5220         } else {
5221                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5222                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5223                                                         "been disabled");
5224                         return;
5225                 }
5226                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5227         }
5228         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5229         I40E_WRITE_FLUSH(hw);
5230 }
5231
5232 /*
5233  * Get global configurations of hash function type and symmetric hash enable
5234  * per flow type (pctype). Note that global configuration means it affects all
5235  * the ports on the same NIC.
5236  */
5237 static int
5238 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5239                                    struct rte_eth_hash_global_conf *g_cfg)
5240 {
5241         uint32_t reg, mask = I40E_FLOW_TYPES;
5242         uint16_t i;
5243         enum i40e_filter_pctype pctype;
5244
5245         memset(g_cfg, 0, sizeof(*g_cfg));
5246         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5247         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5248                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5249         else
5250                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5251         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5252                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5253
5254         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5255                 if (!(mask & (1UL << i)))
5256                         continue;
5257                 mask &= ~(1UL << i);
5258                 /* Bit set indicats the coresponding flow type is supported */
5259                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5260                 pctype = i40e_flowtype_to_pctype(i);
5261                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5262                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5263                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5264         }
5265
5266         return 0;
5267 }
5268
5269 static int
5270 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5271 {
5272         uint32_t i;
5273         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5274
5275         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5276                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5277                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5278                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5279                                                 g_cfg->hash_func);
5280                 return -EINVAL;
5281         }
5282
5283         /*
5284          * As i40e supports less than 32 flow types, only first 32 bits need to
5285          * be checked.
5286          */
5287         mask0 = g_cfg->valid_bit_mask[0];
5288         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5289                 if (i == 0) {
5290                         /* Check if any unsupported flow type configured */
5291                         if ((mask0 | i40e_mask) ^ i40e_mask)
5292                                 goto mask_err;
5293                 } else {
5294                         if (g_cfg->valid_bit_mask[i])
5295                                 goto mask_err;
5296                 }
5297         }
5298
5299         return 0;
5300
5301 mask_err:
5302         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5303
5304         return -EINVAL;
5305 }
5306
5307 /*
5308  * Set global configurations of hash function type and symmetric hash enable
5309  * per flow type (pctype). Note any modifying global configuration will affect
5310  * all the ports on the same NIC.
5311  */
5312 static int
5313 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5314                                    struct rte_eth_hash_global_conf *g_cfg)
5315 {
5316         int ret;
5317         uint16_t i;
5318         uint32_t reg;
5319         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5320         enum i40e_filter_pctype pctype;
5321
5322         /* Check the input parameters */
5323         ret = i40e_hash_global_config_check(g_cfg);
5324         if (ret < 0)
5325                 return ret;
5326
5327         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5328                 if (!(mask0 & (1UL << i)))
5329                         continue;
5330                 mask0 &= ~(1UL << i);
5331                 pctype = i40e_flowtype_to_pctype(i);
5332                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5333                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5334                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5335         }
5336
5337         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5338         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5339                 /* Toeplitz */
5340                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5341                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5342                                                                 "Toeplitz");
5343                         goto out;
5344                 }
5345                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5346         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5347                 /* Simple XOR */
5348                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5349                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5350                                                         "Simple XOR");
5351                         goto out;
5352                 }
5353                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5354         } else
5355                 /* Use the default, and keep it as it is */
5356                 goto out;
5357
5358         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5359
5360 out:
5361         I40E_WRITE_FLUSH(hw);
5362
5363         return 0;
5364 }
5365
5366 static int
5367 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5368 {
5369         int ret = 0;
5370
5371         if (!hw || !info) {
5372                 PMD_DRV_LOG(ERR, "Invalid pointer");
5373                 return -EFAULT;
5374         }
5375
5376         switch (info->info_type) {
5377         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5378                 i40e_get_symmetric_hash_enable_per_port(hw,
5379                                         &(info->info.enable));
5380                 break;
5381         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5382                 ret = i40e_get_hash_filter_global_config(hw,
5383                                 &(info->info.global_conf));
5384                 break;
5385         default:
5386                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5387                                                         info->info_type);
5388                 ret = -EINVAL;
5389                 break;
5390         }
5391
5392         return ret;
5393 }
5394
5395 static int
5396 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5397 {
5398         int ret = 0;
5399
5400         if (!hw || !info) {
5401                 PMD_DRV_LOG(ERR, "Invalid pointer");
5402                 return -EFAULT;
5403         }
5404
5405         switch (info->info_type) {
5406         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5407                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5408                 break;
5409         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5410                 ret = i40e_set_hash_filter_global_config(hw,
5411                                 &(info->info.global_conf));
5412                 break;
5413         default:
5414                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5415                                                         info->info_type);
5416                 ret = -EINVAL;
5417                 break;
5418         }
5419
5420         return ret;
5421 }
5422
5423 /* Operations for hash function */
5424 static int
5425 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5426                       enum rte_filter_op filter_op,
5427                       void *arg)
5428 {
5429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         int ret = 0;
5431
5432         switch (filter_op) {
5433         case RTE_ETH_FILTER_NOP:
5434                 break;
5435         case RTE_ETH_FILTER_GET:
5436                 ret = i40e_hash_filter_get(hw,
5437                         (struct rte_eth_hash_filter_info *)arg);
5438                 break;
5439         case RTE_ETH_FILTER_SET:
5440                 ret = i40e_hash_filter_set(hw,
5441                         (struct rte_eth_hash_filter_info *)arg);
5442                 break;
5443         default:
5444                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5445                                                                 filter_op);
5446                 ret = -ENOTSUP;
5447                 break;
5448         }
5449
5450         return ret;
5451 }
5452
5453 /*
5454  * Configure ethertype filter, which can director packet by filtering
5455  * with mac address and ether_type or only ether_type
5456  */
5457 static int
5458 i40e_ethertype_filter_set(struct i40e_pf *pf,
5459                         struct rte_eth_ethertype_filter *filter,
5460                         bool add)
5461 {
5462         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5463         struct i40e_control_filter_stats stats;
5464         uint16_t flags = 0;
5465         int ret;
5466
5467         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5468                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5469                 return -EINVAL;
5470         }
5471         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5472                 filter->ether_type == ETHER_TYPE_IPv6) {
5473                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5474                         " control packet filter.", filter->ether_type);
5475                 return -EINVAL;
5476         }
5477         if (filter->ether_type == ETHER_TYPE_VLAN)
5478                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5479                         " not supported.");
5480
5481         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5482                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5483         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5484                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5485         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5486
5487         memset(&stats, 0, sizeof(stats));
5488         ret = i40e_aq_add_rem_control_packet_filter(hw,
5489                         filter->mac_addr.addr_bytes,
5490                         filter->ether_type, flags,
5491                         pf->main_vsi->seid,
5492                         filter->queue, add, &stats, NULL);
5493
5494         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5495                          " mac_etype_used = %u, etype_used = %u,"
5496                          " mac_etype_free = %u, etype_free = %u\n",
5497                          ret, stats.mac_etype_used, stats.etype_used,
5498                          stats.mac_etype_free, stats.etype_free);
5499         if (ret < 0)
5500                 return -ENOSYS;
5501         return 0;
5502 }
5503
5504 /*
5505  * Handle operations for ethertype filter.
5506  */
5507 static int
5508 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5509                                 enum rte_filter_op filter_op,
5510                                 void *arg)
5511 {
5512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5513         int ret = 0;
5514
5515         if (filter_op == RTE_ETH_FILTER_NOP)
5516                 return ret;
5517
5518         if (arg == NULL) {
5519                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5520                             filter_op);
5521                 return -EINVAL;
5522         }
5523
5524         switch (filter_op) {
5525         case RTE_ETH_FILTER_ADD:
5526                 ret = i40e_ethertype_filter_set(pf,
5527                         (struct rte_eth_ethertype_filter *)arg,
5528                         TRUE);
5529                 break;
5530         case RTE_ETH_FILTER_DELETE:
5531                 ret = i40e_ethertype_filter_set(pf,
5532                         (struct rte_eth_ethertype_filter *)arg,
5533                         FALSE);
5534                 break;
5535         default:
5536                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5537                 ret = -ENOSYS;
5538                 break;
5539         }
5540         return ret;
5541 }
5542
5543 static int
5544 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5545                      enum rte_filter_type filter_type,
5546                      enum rte_filter_op filter_op,
5547                      void *arg)
5548 {
5549         int ret = 0;
5550
5551         if (dev == NULL)
5552                 return -EINVAL;
5553
5554         switch (filter_type) {
5555         case RTE_ETH_FILTER_HASH:
5556                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5557                 break;
5558         case RTE_ETH_FILTER_MACVLAN:
5559                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5560                 break;
5561         case RTE_ETH_FILTER_ETHERTYPE:
5562                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5563                 break;
5564         case RTE_ETH_FILTER_TUNNEL:
5565                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5566                 break;
5567         case RTE_ETH_FILTER_FDIR:
5568                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5569                 break;
5570         default:
5571                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5572                                                         filter_type);
5573                 ret = -EINVAL;
5574                 break;
5575         }
5576
5577         return ret;
5578 }
5579
5580 /*
5581  * As some registers wouldn't be reset unless a global hardware reset,
5582  * hardware initialization is needed to put those registers into an
5583  * expected initial state.
5584  */
5585 static void
5586 i40e_hw_init(struct i40e_hw *hw)
5587 {
5588         /* clear the PF Queue Filter control register */
5589         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5590
5591         /* Disable symmetric hash per port */
5592         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5593 }
5594
5595 enum i40e_filter_pctype
5596 i40e_flowtype_to_pctype(uint16_t flow_type)
5597 {
5598         static const enum i40e_filter_pctype pctype_table[] = {
5599                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5600                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5601                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5602                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5603                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5604                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5605                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5606                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5607                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5608                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5609                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5610                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5611                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5612                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5613                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5614                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5615                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5616                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5617                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5618         };
5619
5620         return pctype_table[flow_type];
5621 }
5622
5623 uint16_t
5624 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5625 {
5626         static const uint16_t flowtype_table[] = {
5627                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5628                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5629                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5630                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5631                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5632                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5633                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5634                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5635                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5636                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5637                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5638                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5639                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5640                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5641                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5642                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5643                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5644                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5645                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5646         };
5647
5648         return flowtype_table[pctype];
5649 }
5650
5651 /*
5652  * On X710, performance number is far from the expectation on recent firmware
5653  * versions; on XL710, performance number is also far from the expectation on
5654  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5655  * mode is enabled and port MAC address is equal to the packet destination MAC
5656  * address. The fix for this issue may not be integrated in the following
5657  * firmware version. So the workaround in software driver is needed. It needs
5658  * to modify the initial values of 3 internal only registers for both X710 and
5659  * XL710. Note that the values for X710 or XL710 could be different, and the
5660  * workaround can be removed when it is fixed in firmware in the future.
5661  */
5662
5663 /* For both X710 and XL710 */
5664 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5665 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5666
5667 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5668 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5669
5670 /* For X710 */
5671 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5672 /* For XL710 */
5673 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5674 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5675
5676 static void
5677 i40e_configure_registers(struct i40e_hw *hw)
5678 {
5679         static struct {
5680                 uint32_t addr;
5681                 uint64_t val;
5682         } reg_table[] = {
5683                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5684                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5685                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5686         };
5687         uint64_t reg;
5688         uint32_t i;
5689         int ret;
5690
5691         for (i = 0; i < RTE_DIM(reg_table); i++) {
5692                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5693                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5694                                 reg_table[i].val =
5695                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5696                         else /* For X710 */
5697                                 reg_table[i].val =
5698                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5699                 }
5700
5701                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5702                                                         &reg, NULL);
5703                 if (ret < 0) {
5704                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5705                                                         reg_table[i].addr);
5706                         break;
5707                 }
5708                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5709                                                 reg_table[i].addr, reg);
5710                 if (reg == reg_table[i].val)
5711                         continue;
5712
5713                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5714                                                 reg_table[i].val, NULL);
5715                 if (ret < 0) {
5716                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5717                                 "address of 0x%"PRIx32, reg_table[i].val,
5718                                                         reg_table[i].addr);
5719                         break;
5720                 }
5721                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5722                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5723         }
5724 }
5725
5726 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
5727 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
5728 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
5729 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5730 static int
5731 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5732 {
5733         uint32_t reg;
5734         int ret;
5735
5736         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5737                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5738                 return -EINVAL;
5739         }
5740
5741         /* Configure for double VLAN RX stripping */
5742         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5743         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5744                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5745                 ret = i40e_aq_debug_write_register(hw,
5746                                                    I40E_VSI_TSR(vsi->vsi_id),
5747                                                    reg, NULL);
5748                 if (ret < 0) {
5749                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5750                                     vsi->vsi_id);
5751                         return I40E_ERR_CONFIG;
5752                 }
5753         }
5754
5755         /* Configure for double VLAN TX insertion */
5756         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5757         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5758                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5759                 ret = i40e_aq_debug_write_register(hw,
5760                                                    I40E_VSI_L2TAGSTXVALID(
5761                                                    vsi->vsi_id), reg, NULL);
5762                 if (ret < 0) {
5763                         PMD_DRV_LOG(ERR, "Failed to update "
5764                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5765                         return I40E_ERR_CONFIG;
5766                 }
5767         }
5768
5769         return 0;
5770 }
5771
5772 /**
5773  * i40e_aq_add_mirror_rule
5774  * @hw: pointer to the hardware structure
5775  * @seid: VEB seid to add mirror rule to
5776  * @dst_id: destination vsi seid
5777  * @entries: Buffer which contains the entities to be mirrored
5778  * @count: number of entities contained in the buffer
5779  * @rule_id:the rule_id of the rule to be added
5780  *
5781  * Add a mirror rule for a given veb.
5782  *
5783  **/
5784 static enum i40e_status_code
5785 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5786                         uint16_t seid, uint16_t dst_id,
5787                         uint16_t rule_type, uint16_t *entries,
5788                         uint16_t count, uint16_t *rule_id)
5789 {
5790         struct i40e_aq_desc desc;
5791         struct i40e_aqc_add_delete_mirror_rule cmd;
5792         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5793                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5794                 &desc.params.raw;
5795         uint16_t buff_len;
5796         enum i40e_status_code status;
5797
5798         i40e_fill_default_direct_cmd_desc(&desc,
5799                                           i40e_aqc_opc_add_mirror_rule);
5800         memset(&cmd, 0, sizeof(cmd));
5801
5802         buff_len = sizeof(uint16_t) * count;
5803         desc.datalen = rte_cpu_to_le_16(buff_len);
5804         if (buff_len > 0)
5805                 desc.flags |= rte_cpu_to_le_16(
5806                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5807         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5808                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5809         cmd.num_entries = rte_cpu_to_le_16(count);
5810         cmd.seid = rte_cpu_to_le_16(seid);
5811         cmd.destination = rte_cpu_to_le_16(dst_id);
5812
5813         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5814         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5815         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5816                          "rule_id = %u"
5817                          " mirror_rules_used = %u, mirror_rules_free = %u,",
5818                          hw->aq.asq_last_status, resp->rule_id,
5819                          resp->mirror_rules_used, resp->mirror_rules_free);
5820         *rule_id = rte_le_to_cpu_16(resp->rule_id);
5821
5822         return status;
5823 }
5824
5825 /**
5826  * i40e_aq_del_mirror_rule
5827  * @hw: pointer to the hardware structure
5828  * @seid: VEB seid to add mirror rule to
5829  * @entries: Buffer which contains the entities to be mirrored
5830  * @count: number of entities contained in the buffer
5831  * @rule_id:the rule_id of the rule to be delete
5832  *
5833  * Delete a mirror rule for a given veb.
5834  *
5835  **/
5836 static enum i40e_status_code
5837 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5838                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5839                 uint16_t count, uint16_t rule_id)
5840 {
5841         struct i40e_aq_desc desc;
5842         struct i40e_aqc_add_delete_mirror_rule cmd;
5843         uint16_t buff_len = 0;
5844         enum i40e_status_code status;
5845         void *buff = NULL;
5846
5847         i40e_fill_default_direct_cmd_desc(&desc,
5848                                           i40e_aqc_opc_delete_mirror_rule);
5849         memset(&cmd, 0, sizeof(cmd));
5850         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5851                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5852                                                           I40E_AQ_FLAG_RD));
5853                 cmd.num_entries = count;
5854                 buff_len = sizeof(uint16_t) * count;
5855                 desc.datalen = rte_cpu_to_le_16(buff_len);
5856                 buff = (void *)entries;
5857         } else
5858                 /* rule id is filled in destination field for deleting mirror rule */
5859                 cmd.destination = rte_cpu_to_le_16(rule_id);
5860
5861         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5862                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5863         cmd.seid = rte_cpu_to_le_16(seid);
5864
5865         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5866         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5867
5868         return status;
5869 }
5870
5871 /**
5872  * i40e_mirror_rule_set
5873  * @dev: pointer to the hardware structure
5874  * @mirror_conf: mirror rule info
5875  * @sw_id: mirror rule's sw_id
5876  * @on: enable/disable
5877  *
5878  * set a mirror rule.
5879  *
5880  **/
5881 static int
5882 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5883                         struct rte_eth_mirror_conf *mirror_conf,
5884                         uint8_t sw_id, uint8_t on)
5885 {
5886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5888         struct i40e_mirror_rule *it, *mirr_rule = NULL;
5889         struct i40e_mirror_rule *parent = NULL;
5890         uint16_t seid, dst_seid, rule_id;
5891         uint16_t i, j = 0;
5892         int ret;
5893
5894         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5895
5896         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5897                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5898                         " without veb or vfs.");
5899                 return -ENOSYS;
5900         }
5901         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5902                 PMD_DRV_LOG(ERR, "mirror table is full.");
5903                 return -ENOSPC;
5904         }
5905         if (mirror_conf->dst_pool > pf->vf_num) {
5906                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5907                                  mirror_conf->dst_pool);
5908                 return -EINVAL;
5909         }
5910
5911         seid = pf->main_vsi->veb->seid;
5912
5913         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
5914                 if (sw_id <= it->index) {
5915                         mirr_rule = it;
5916                         break;
5917                 }
5918                 parent = it;
5919         }
5920         if (mirr_rule && sw_id == mirr_rule->index) {
5921                 if (on) {
5922                         PMD_DRV_LOG(ERR, "mirror rule exists.");
5923                         return -EEXIST;
5924                 } else {
5925                         ret = i40e_aq_del_mirror_rule(hw, seid,
5926                                         mirr_rule->rule_type,
5927                                         mirr_rule->entries,
5928                                         mirr_rule->num_entries, mirr_rule->id);
5929                         if (ret < 0) {
5930                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
5931                                                    " ret = %d, aq_err = %d.",
5932                                                    ret, hw->aq.asq_last_status);
5933                                 return -ENOSYS;
5934                         }
5935                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
5936                         rte_free(mirr_rule);
5937                         pf->nb_mirror_rule--;
5938                         return 0;
5939                 }
5940         } else if (!on) {
5941                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
5942                 return -ENOENT;
5943         }
5944
5945         mirr_rule = rte_zmalloc("i40e_mirror_rule",
5946                                 sizeof(struct i40e_mirror_rule) , 0);
5947         if (!mirr_rule) {
5948                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5949                 return I40E_ERR_NO_MEMORY;
5950         }
5951         switch (mirror_conf->rule_type) {
5952         case ETH_MIRROR_VLAN:
5953                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
5954                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5955                                 mirr_rule->entries[j] =
5956                                         mirror_conf->vlan.vlan_id[i];
5957                                 j++;
5958                         }
5959                 }
5960                 if (j == 0) {
5961                         PMD_DRV_LOG(ERR, "vlan is not specified.");
5962                         rte_free(mirr_rule);
5963                         return -EINVAL;
5964                 }
5965                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
5966                 break;
5967         case ETH_MIRROR_VIRTUAL_POOL_UP:
5968         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
5969                 /* check if the specified pool bit is out of range */
5970                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
5971                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
5972                         rte_free(mirr_rule);
5973                         return -EINVAL;
5974                 }
5975                 for (i = 0, j = 0; i < pf->vf_num; i++) {
5976                         if (mirror_conf->pool_mask & (1ULL << i)) {
5977                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
5978                                 j++;
5979                         }
5980                 }
5981                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
5982                         /* add pf vsi to entries */
5983                         mirr_rule->entries[j] = pf->main_vsi_seid;
5984                         j++;
5985                 }
5986                 if (j == 0) {
5987                         PMD_DRV_LOG(ERR, "pool is not specified.");
5988                         rte_free(mirr_rule);
5989                         return -EINVAL;
5990                 }
5991                 /* egress and ingress in aq commands means from switch but not port */
5992                 mirr_rule->rule_type =
5993                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
5994                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
5995                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
5996                 break;
5997         case ETH_MIRROR_UPLINK_PORT:
5998                 /* egress and ingress in aq commands means from switch but not port*/
5999                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6000                 break;
6001         case ETH_MIRROR_DOWNLINK_PORT:
6002                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6003                 break;
6004         default:
6005                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6006                         mirror_conf->rule_type);
6007                 rte_free(mirr_rule);
6008                 return -EINVAL;
6009         }
6010
6011         /* If the dst_pool is equal to vf_num, consider it as PF */
6012         if (mirror_conf->dst_pool == pf->vf_num)
6013                 dst_seid = pf->main_vsi_seid;
6014         else
6015                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6016
6017         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6018                                       mirr_rule->rule_type, mirr_rule->entries,
6019                                       j, &rule_id);
6020         if (ret < 0) {
6021                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6022                                    " ret = %d, aq_err = %d.",
6023                                    ret, hw->aq.asq_last_status);
6024                 rte_free(mirr_rule);
6025                 return -ENOSYS;
6026         }
6027
6028         mirr_rule->index = sw_id;
6029         mirr_rule->num_entries = j;
6030         mirr_rule->id = rule_id;
6031         mirr_rule->dst_vsi_seid = dst_seid;
6032
6033         if (parent)
6034                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6035         else
6036                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6037
6038         pf->nb_mirror_rule++;
6039         return 0;
6040 }
6041
6042 /**
6043  * i40e_mirror_rule_reset
6044  * @dev: pointer to the device
6045  * @sw_id: mirror rule's sw_id
6046  *
6047  * reset a mirror rule.
6048  *
6049  **/
6050 static int
6051 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6052 {
6053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6056         uint16_t seid;
6057         int ret;
6058
6059         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6060
6061         seid = pf->main_vsi->veb->seid;
6062
6063         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6064                 if (sw_id == it->index) {
6065                         mirr_rule = it;
6066                         break;
6067                 }
6068         }
6069         if (mirr_rule) {
6070                 ret = i40e_aq_del_mirror_rule(hw, seid,
6071                                 mirr_rule->rule_type,
6072                                 mirr_rule->entries,
6073                                 mirr_rule->num_entries, mirr_rule->id);
6074                 if (ret < 0) {
6075                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6076                                            " status = %d, aq_err = %d.",
6077                                            ret, hw->aq.asq_last_status);
6078                         return -ENOSYS;
6079                 }
6080                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6081                 rte_free(mirr_rule);
6082                 pf->nb_mirror_rule--;
6083         } else {
6084                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6085                 return -ENOENT;
6086         }
6087         return 0;
6088 }