drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 295                           struct ether_addr *mac_addr,
 296                           uint32_t index,
 297                           uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418
 419 int i40e_logtype_init;
 420 int i40e_logtype_driver;
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 633         struct rte_pci_device *pci_dev)
 634 {
 635         return rte_eth_dev_pci_generic_probe(pci_dev,
 636                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 637 }
 638
 639 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 640 {
 641         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 642 }
 643
 644 static struct rte_pci_driver rte_i40e_pmd = {
 645         .id_table = pci_id_i40e_map,
 646         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 647         .probe = eth_i40e_pci_probe,
 648         .remove = eth_i40e_pci_remove,
 649 };
 650
 651 static inline int
 652 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 653                                      struct rte_eth_link *link)
 654 {
 655         struct rte_eth_link *dst = link;
 656         struct rte_eth_link *src = &(dev->data->dev_link);
 657
 658         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 659                                         *(uint64_t *)src) == 0)
 660                 return -1;
 661
 662         return 0;
 663 }
 664
 665 static inline int
 666 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 667                                       struct rte_eth_link *link)
 668 {
 669         struct rte_eth_link *dst = &(dev->data->dev_link);
 670         struct rte_eth_link *src = link;
 671
 672         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 673                                         *(uint64_t *)src) == 0)
 674                 return -1;
 675
 676         return 0;
 677 }
 678
 679 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 680 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 681 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 682
 683 #ifndef I40E_GLQF_ORT
 684 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 685 #endif
 686 #ifndef I40E_GLQF_PIT
 687 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 688 #endif
 689 #ifndef I40E_GLQF_L3_MAP
 690 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 691 #endif
 692
 693 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 694 {
 695         /*
 696          * Initialize registers for flexible payload, which should be set by NVM.
 697          * This should be removed from code once it is fixed in NVM.
 698          */
 699         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 709         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 710         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 711
 712         /* Initialize registers for parsing packet type of QinQ */
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 714         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 715 }
 716
 717 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 718
 719 /*
 720  * Add a ethertype filter to drop all flow control frames transmitted
 721  * from VSIs.
 722 */
 723 static void
 724 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 725 {
 726         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 727         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 728                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 729                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 730         int ret;
 731
 732         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 733                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 734                                 pf->main_vsi_seid, 0,
 735                                 TRUE, NULL, NULL);
 736         if (ret)
 737                 PMD_INIT_LOG(ERR,
 738                         "Failed to add filter to drop flow control frames from VSIs.");
 739 }
 740
 741 static int
 742 floating_veb_list_handler(__rte_unused const char *key,
 743                           const char *floating_veb_value,
 744                           void *opaque)
 745 {
 746         int idx = 0;
 747         unsigned int count = 0;
 748         char *end = NULL;
 749         int min, max;
 750         bool *vf_floating_veb = opaque;
 751
 752         while (isblank(*floating_veb_value))
 753                 floating_veb_value++;
 754
 755         /* Reset floating VEB configuration for VFs */
 756         for (idx = 0; idx < I40E_MAX_VF; idx++)
 757                 vf_floating_veb[idx] = false;
 758
 759         min = I40E_MAX_VF;
 760         do {
 761                 while (isblank(*floating_veb_value))
 762                         floating_veb_value++;
 763                 if (*floating_veb_value == '\0')
 764                         return -1;
 765                 errno = 0;
 766                 idx = strtoul(floating_veb_value, &end, 10);
 767                 if (errno || end == NULL)
 768                         return -1;
 769                 while (isblank(*end))
 770                         end++;
 771                 if (*end == '-') {
 772                         min = idx;
 773                 } else if ((*end == ';') || (*end == '\0')) {
 774                         max = idx;
 775                         if (min == I40E_MAX_VF)
 776                                 min = idx;
 777                         if (max >= I40E_MAX_VF)
 778                                 max = I40E_MAX_VF - 1;
 779                         for (idx = min; idx <= max; idx++) {
 780                                 vf_floating_veb[idx] = true;
 781                                 count++;
 782                         }
 783                         min = I40E_MAX_VF;
 784                 } else {
 785                         return -1;
 786                 }
 787                 floating_veb_value = end + 1;
 788         } while (*end != '\0');
 789
 790         if (count == 0)
 791                 return -1;
 792
 793         return 0;
 794 }
 795
 796 static void
 797 config_vf_floating_veb(struct rte_devargs *devargs,
 798                        uint16_t floating_veb,
 799                        bool *vf_floating_veb)
 800 {
 801         struct rte_kvargs *kvlist;
 802         int i;
 803         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 804
 805         if (!floating_veb)
 806                 return;
 807         /* All the VFs attach to the floating VEB by default
 808          * when the floating VEB is enabled.
 809          */
 810         for (i = 0; i < I40E_MAX_VF; i++)
 811                 vf_floating_veb[i] = true;
 812
 813         if (devargs == NULL)
 814                 return;
 815
 816         kvlist = rte_kvargs_parse(devargs->args, NULL);
 817         if (kvlist == NULL)
 818                 return;
 819
 820         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         /* When the floating_veb_list parameter exists, all the VFs
 825          * will attach to the legacy VEB firstly, then configure VFs
 826          * to the floating VEB according to the floating_veb_list.
 827          */
 828         if (rte_kvargs_process(kvlist, floating_veb_list,
 829                                floating_veb_list_handler,
 830                                vf_floating_veb) < 0) {
 831                 rte_kvargs_free(kvlist);
 832                 return;
 833         }
 834         rte_kvargs_free(kvlist);
 835 }
 836
 837 static int
 838 i40e_check_floating_handler(__rte_unused const char *key,
 839                             const char *value,
 840                             __rte_unused void *opaque)
 841 {
 842         if (strcmp(value, "1"))
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 static int
 849 is_floating_veb_supported(struct rte_devargs *devargs)
 850 {
 851         struct rte_kvargs *kvlist;
 852         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 853
 854         if (devargs == NULL)
 855                 return 0;
 856
 857         kvlist = rte_kvargs_parse(devargs->args, NULL);
 858         if (kvlist == NULL)
 859                 return 0;
 860
 861         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 862                 rte_kvargs_free(kvlist);
 863                 return 0;
 864         }
 865         /* Floating VEB is enabled when there's key-value:
 866          * enable_floating_veb=1
 867          */
 868         if (rte_kvargs_process(kvlist, floating_veb_key,
 869                                i40e_check_floating_handler, NULL) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return 0;
 872         }
 873         rte_kvargs_free(kvlist);
 874
 875         return 1;
 876 }
 877
 878 static void
 879 config_floating_veb(struct rte_eth_dev *dev)
 880 {
 881         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884
 885         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 886
 887         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 888                 pf->floating_veb =
 889                         is_floating_veb_supported(pci_dev->device.devargs);
 890                 config_vf_floating_veb(pci_dev->device.devargs,
 891                                        pf->floating_veb,
 892                                        pf->floating_veb_list);
 893         } else {
 894                 pf->floating_veb = false;
 895         }
 896 }
 897
 898 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 899 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 900
 901 static int
 902 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 903 {
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 906         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 907         int ret;
 908
 909         struct rte_hash_parameters ethertype_hash_params = {
 910                 .name = ethertype_hash_name,
 911                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 912                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 913                 .hash_func = rte_hash_crc,
 914                 .hash_func_init_val = 0,
 915                 .socket_id = rte_socket_id(),
 916         };
 917
 918         /* Initialize ethertype filter rule list and hash */
 919         TAILQ_INIT(&ethertype_rule->ethertype_list);
 920         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 921                  "ethertype_%s", dev->data->name);
 922         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 923         if (!ethertype_rule->hash_table) {
 924                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 925                 return -EINVAL;
 926         }
 927         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 928                                        sizeof(struct i40e_ethertype_filter *) *
 929                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 930                                        0);
 931         if (!ethertype_rule->hash_map) {
 932                 PMD_INIT_LOG(ERR,
 933                              "Failed to allocate memory for ethertype hash map!");
 934                 ret = -ENOMEM;
 935                 goto err_ethertype_hash_map_alloc;
 936         }
 937
 938         return 0;
 939
 940 err_ethertype_hash_map_alloc:
 941         rte_hash_free(ethertype_rule->hash_table);
 942
 943         return ret;
 944 }
 945
 946 static int
 947 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 948 {
 949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 950         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 951         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 952         int ret;
 953
 954         struct rte_hash_parameters tunnel_hash_params = {
 955                 .name = tunnel_hash_name,
 956                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 957                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 958                 .hash_func = rte_hash_crc,
 959                 .hash_func_init_val = 0,
 960                 .socket_id = rte_socket_id(),
 961         };
 962
 963         /* Initialize tunnel filter rule list and hash */
 964         TAILQ_INIT(&tunnel_rule->tunnel_list);
 965         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 966                  "tunnel_%s", dev->data->name);
 967         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 968         if (!tunnel_rule->hash_table) {
 969                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 970                 return -EINVAL;
 971         }
 972         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 973                                     sizeof(struct i40e_tunnel_filter *) *
 974                                     I40E_MAX_TUNNEL_FILTER_NUM,
 975                                     0);
 976         if (!tunnel_rule->hash_map) {
 977                 PMD_INIT_LOG(ERR,
 978                              "Failed to allocate memory for tunnel hash map!");
 979                 ret = -ENOMEM;
 980                 goto err_tunnel_hash_map_alloc;
 981         }
 982
 983         return 0;
 984
 985 err_tunnel_hash_map_alloc:
 986         rte_hash_free(tunnel_rule->hash_table);
 987
 988         return ret;
 989 }
 990
 991 static int
 992 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 993 {
 994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 995         struct i40e_fdir_info *fdir_info = &pf->fdir;
 996         char fdir_hash_name[RTE_HASH_NAMESIZE];
 997         int ret;
 998
 999         struct rte_hash_parameters fdir_hash_params = {
1000                 .name = fdir_hash_name,
1001                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1002                 .key_len = sizeof(struct rte_eth_fdir_input),
1003                 .hash_func = rte_hash_crc,
1004                 .hash_func_init_val = 0,
1005                 .socket_id = rte_socket_id(),
1006         };
1007
1008         /* Initialize flow director filter rule list and hash */
1009         TAILQ_INIT(&fdir_info->fdir_list);
1010         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1011                  "fdir_%s", dev->data->name);
1012         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1013         if (!fdir_info->hash_table) {
1014                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1015                 return -EINVAL;
1016         }
1017         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1018                                           sizeof(struct i40e_fdir_filter *) *
1019                                           I40E_MAX_FDIR_FILTER_NUM,
1020                                           0);
1021         if (!fdir_info->hash_map) {
1022                 PMD_INIT_LOG(ERR,
1023                              "Failed to allocate memory for fdir hash map!");
1024                 ret = -ENOMEM;
1025                 goto err_fdir_hash_map_alloc;
1026         }
1027         return 0;
1028
1029 err_fdir_hash_map_alloc:
1030         rte_hash_free(fdir_info->hash_table);
1031
1032         return ret;
1033 }
1034
1035 static int
1036 eth_i40e_dev_init(struct rte_eth_dev *dev)
1037 {
1038         struct rte_pci_device *pci_dev;
1039         struct rte_intr_handle *intr_handle;
1040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042         struct i40e_vsi *vsi;
1043         int ret;
1044         uint32_t len;
1045         uint8_t aq_fail = 0;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         dev->dev_ops = &i40e_eth_dev_ops;
1050         dev->rx_pkt_burst = i40e_recv_pkts;
1051         dev->tx_pkt_burst = i40e_xmit_pkts;
1052         dev->tx_pkt_prepare = i40e_prep_pkts;
1053
1054         /* for secondary processes, we don't initialise any further as primary
1055          * has already done this work. Only check we don't need a different
1056          * RX function */
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1058                 i40e_set_rx_function(dev);
1059                 i40e_set_tx_function(dev);
1060                 return 0;
1061         }
1062         pci_dev = I40E_DEV_TO_PCI(dev);
1063         intr_handle = &pci_dev->intr_handle;
1064
1065         rte_eth_copy_pci_info(dev, pci_dev);
1066         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1067
1068         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1069         pf->adapter->eth_dev = dev;
1070         pf->dev_data = dev->data;
1071
1072         hw->back = I40E_PF_TO_ADAPTER(pf);
1073         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1074         if (!hw->hw_addr) {
1075                 PMD_INIT_LOG(ERR,
1076                         "Hardware is not available, as address is NULL");
1077                 return -ENODEV;
1078         }
1079
1080         hw->vendor_id = pci_dev->id.vendor_id;
1081         hw->device_id = pci_dev->id.device_id;
1082         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1083         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1084         hw->bus.device = pci_dev->addr.devid;
1085         hw->bus.func = pci_dev->addr.function;
1086         hw->adapter_stopped = 0;
1087
1088         /* Make sure all is clean before doing PF reset */
1089         i40e_clear_hw(hw);
1090
1091         /* Initialize the hardware */
1092         i40e_hw_init(dev);
1093
1094         /* Reset here to make sure all is clean for each PF */
1095         ret = i40e_pf_reset(hw);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1098                 return ret;
1099         }
1100
1101         /* Initialize the shared code (base driver) */
1102         ret = i40e_init_shared_code(hw);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1105                 return ret;
1106         }
1107
1108         /*
1109          * To work around the NVM issue, initialize registers
1110          * for flexible payload and packet type of QinQ by
1111          * software. It should be removed once issues are fixed
1112          * in NVM.
1113          */
1114         i40e_GLQF_reg_init(hw);
1115
1116         /* Initialize the input set for filters (hash and fd) to default value */
1117         i40e_filter_input_set_init(pf);
1118
1119         /* Initialize the parameters for adminq */
1120         i40e_init_adminq_parameter(hw);
1121         ret = i40e_init_adminq(hw);
1122         if (ret != I40E_SUCCESS) {
1123                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1124                 return -EIO;
1125         }
1126         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1127                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1128                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1129                      ((hw->nvm.version >> 12) & 0xf),
1130                      ((hw->nvm.version >> 4) & 0xff),
1131                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1132
1133         /* initialise the L3_MAP register */
1134         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1135                                    0x00000028,  NULL);
1136         if (ret)
1137                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1138
1139         /* Need the special FW version to support floating VEB */
1140         config_floating_veb(dev);
1141         /* Clear PXE mode */
1142         i40e_clear_pxe_mode(hw);
1143         ret = i40e_dev_sync_phy_type(hw);
1144         if (ret) {
1145                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1146                 goto err_sync_phy_type;
1147         }
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         ret = i40e_init_ethtype_filter_list(dev);
1300         if (ret < 0)
1301                 goto err_init_ethtype_filter_list;
1302         ret = i40e_init_tunnel_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_tunnel_filter_list;
1305         ret = i40e_init_fdir_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_fdir_filter_list;
1308
1309         return 0;
1310
1311 err_init_fdir_filter_list:
1312         rte_free(pf->tunnel.hash_table);
1313         rte_free(pf->tunnel.hash_map);
1314 err_init_tunnel_filter_list:
1315         rte_free(pf->ethertype.hash_table);
1316         rte_free(pf->ethertype.hash_map);
1317 err_init_ethtype_filter_list:
1318         rte_free(dev->data->mac_addrs);
1319 err_mac_alloc:
1320         i40e_vsi_release(pf->main_vsi);
1321 err_setup_pf_switch:
1322 err_get_mac_addr:
1323 err_configure_lan_hmc:
1324         (void)i40e_shutdown_lan_hmc(hw);
1325 err_init_lan_hmc:
1326         i40e_res_pool_destroy(&pf->msix_pool);
1327 err_msix_pool_init:
1328         i40e_res_pool_destroy(&pf->qp_pool);
1329 err_qp_pool_init:
1330 err_parameter_init:
1331 err_get_capabilities:
1332 err_sync_phy_type:
1333         (void)i40e_shutdown_adminq(hw);
1334
1335         return ret;
1336 }
1337
1338 static void
1339 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1340 {
1341         struct i40e_ethertype_filter *p_ethertype;
1342         struct i40e_ethertype_rule *ethertype_rule;
1343
1344         ethertype_rule = &pf->ethertype;
1345         /* Remove all ethertype filter rules and hash */
1346         if (ethertype_rule->hash_map)
1347                 rte_free(ethertype_rule->hash_map);
1348         if (ethertype_rule->hash_table)
1349                 rte_hash_free(ethertype_rule->hash_table);
1350
1351         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1352                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1353                              p_ethertype, rules);
1354                 rte_free(p_ethertype);
1355         }
1356 }
1357
1358 static void
1359 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1360 {
1361         struct i40e_tunnel_filter *p_tunnel;
1362         struct i40e_tunnel_rule *tunnel_rule;
1363
1364         tunnel_rule = &pf->tunnel;
1365         /* Remove all tunnel director rules and hash */
1366         if (tunnel_rule->hash_map)
1367                 rte_free(tunnel_rule->hash_map);
1368         if (tunnel_rule->hash_table)
1369                 rte_hash_free(tunnel_rule->hash_table);
1370
1371         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1372                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1373                 rte_free(p_tunnel);
1374         }
1375 }
1376
1377 static void
1378 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1379 {
1380         struct i40e_fdir_filter *p_fdir;
1381         struct i40e_fdir_info *fdir_info;
1382
1383         fdir_info = &pf->fdir;
1384         /* Remove all flow director rules and hash */
1385         if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_table)
1388                 rte_hash_free(fdir_info->hash_table);
1389
1390         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1392                 rte_free(p_fdir);
1393         }
1394 }
1395
1396 static int
1397 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1398 {
1399         struct i40e_pf *pf;
1400         struct rte_pci_device *pci_dev;
1401         struct rte_intr_handle *intr_handle;
1402         struct i40e_hw *hw;
1403         struct i40e_filter_control_settings settings;
1404         struct rte_flow *p_flow;
1405         int ret;
1406         uint8_t aq_fail = 0;
1407
1408         PMD_INIT_FUNC_TRACE();
1409
1410         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1411                 return 0;
1412
1413         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1414         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         pci_dev = I40E_DEV_TO_PCI(dev);
1416         intr_handle = &pci_dev->intr_handle;
1417
1418         if (hw->adapter_stopped == 0)
1419                 i40e_dev_close(dev);
1420
1421         dev->dev_ops = NULL;
1422         dev->rx_pkt_burst = NULL;
1423         dev->tx_pkt_burst = NULL;
1424
1425         /* Clear PXE mode */
1426         i40e_clear_pxe_mode(hw);
1427
1428         /* Unconfigure filter control */
1429         memset(&settings, 0, sizeof(settings));
1430         ret = i40e_set_filter_control(hw, &settings);
1431         if (ret)
1432                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1433                                         ret);
1434
1435         /* Disable flow control */
1436         hw->fc.requested_mode = I40E_FC_NONE;
1437         i40e_set_fc(hw, &aq_fail, TRUE);
1438
1439         /* uninitialize pf host driver */
1440         i40e_pf_host_uninit(dev);
1441
1442         rte_free(dev->data->mac_addrs);
1443         dev->data->mac_addrs = NULL;
1444
1445         /* disable uio intr before callback unregister */
1446         rte_intr_disable(intr_handle);
1447
1448         /* register callback func to eal lib */
1449         rte_intr_callback_unregister(intr_handle,
1450                                      i40e_dev_interrupt_handler, dev);
1451
1452         i40e_rm_ethtype_filter_list(pf);
1453         i40e_rm_tunnel_filter_list(pf);
1454         i40e_rm_fdir_filter_list(pf);
1455
1456         /* Remove all flows */
1457         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1458                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1459                 rte_free(p_flow);
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int
1466 i40e_dev_configure(struct rte_eth_dev *dev)
1467 {
1468         struct i40e_adapter *ad =
1469                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1471         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1472         int i, ret;
1473
1474         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1475          * bulk allocation or vector Rx preconditions we will reset it.
1476          */
1477         ad->rx_bulk_alloc_allowed = true;
1478         ad->rx_vec_allowed = true;
1479         ad->tx_simple_allowed = true;
1480         ad->tx_vec_allowed = true;
1481
1482         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1483                 ret = i40e_fdir_setup(pf);
1484                 if (ret != I40E_SUCCESS) {
1485                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1486                         return -ENOTSUP;
1487                 }
1488                 ret = i40e_fdir_configure(dev);
1489                 if (ret < 0) {
1490                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1491                         goto err;
1492                 }
1493         } else
1494                 i40e_fdir_teardown(pf);
1495
1496         ret = i40e_dev_init_vlan(dev);
1497         if (ret < 0)
1498                 goto err;
1499
1500         /* VMDQ setup.
1501          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1502          *  RSS setting have different requirements.
1503          *  General PMD driver call sequence are NIC init, configure,
1504          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1505          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1506          *  applicable. So, VMDQ setting has to be done before
1507          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1508          *  For RSS setting, it will try to calculate actual configured RX queue
1509          *  number, which will be available after rx_queue_setup(). dev_start()
1510          *  function is good to place RSS setup.
1511          */
1512         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1513                 ret = i40e_vmdq_setup(dev);
1514                 if (ret)
1515                         goto err;
1516         }
1517
1518         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1519                 ret = i40e_dcb_setup(dev);
1520                 if (ret) {
1521                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1522                         goto err_dcb;
1523                 }
1524         }
1525
1526         TAILQ_INIT(&pf->flow_list);
1527
1528         return 0;
1529
1530 err_dcb:
1531         /* need to release vmdq resource if exists */
1532         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1533                 i40e_vsi_release(pf->vmdq[i].vsi);
1534                 pf->vmdq[i].vsi = NULL;
1535         }
1536         rte_free(pf->vmdq);
1537         pf->vmdq = NULL;
1538 err:
1539         /* need to release fdir resource if exists */
1540         i40e_fdir_teardown(pf);
1541         return ret;
1542 }
1543
1544 void
1545 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1546 {
1547         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1548         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1550         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1551         uint16_t msix_vect = vsi->msix_intr;
1552         uint16_t i;
1553
1554         for (i = 0; i < vsi->nb_qps; i++) {
1555                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1556                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1557                 rte_wmb();
1558         }
1559
1560         if (vsi->type != I40E_VSI_SRIOV) {
1561                 if (!rte_intr_allow_others(intr_handle)) {
1562                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1563                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1564                         I40E_WRITE_REG(hw,
1565                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1566                                        0);
1567                 } else {
1568                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1569                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1570                         I40E_WRITE_REG(hw,
1571                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1572                                                        msix_vect - 1), 0);
1573                 }
1574         } else {
1575                 uint32_t reg;
1576                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1577                         vsi->user_param + (msix_vect - 1);
1578
1579                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1580                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1581         }
1582         I40E_WRITE_FLUSH(hw);
1583 }
1584
1585 static void
1586 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1587                        int base_queue, int nb_queue)
1588 {
1589         int i;
1590         uint32_t val;
1591         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1592
1593         /* Bind all RX queues to allocated MSIX interrupt */
1594         for (i = 0; i < nb_queue; i++) {
1595                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1596                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1597                         ((base_queue + i + 1) <<
1598                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1599                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1600                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1601
1602                 if (i == nb_queue - 1)
1603                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1604                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1605         }
1606
1607         /* Write first RX queue to Link list register as the head element */
1608         if (vsi->type != I40E_VSI_SRIOV) {
1609                 uint16_t interval =
1610                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1611
1612                 if (msix_vect == I40E_MISC_VEC_ID) {
1613                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1614                                        (base_queue <<
1615                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1616                                        (0x0 <<
1617                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1618                         I40E_WRITE_REG(hw,
1619                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1620                                        interval);
1621                 } else {
1622                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1623                                        (base_queue <<
1624                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1625                                        (0x0 <<
1626                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1627                         I40E_WRITE_REG(hw,
1628                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1629                                                        msix_vect - 1),
1630                                        interval);
1631                 }
1632         } else {
1633                 uint32_t reg;
1634
1635                 if (msix_vect == I40E_MISC_VEC_ID) {
1636                         I40E_WRITE_REG(hw,
1637                                        I40E_VPINT_LNKLST0(vsi->user_param),
1638                                        (base_queue <<
1639                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1640                                        (0x0 <<
1641                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1642                 } else {
1643                         /* num_msix_vectors_vf needs to minus irq0 */
1644                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1645                                 vsi->user_param + (msix_vect - 1);
1646
1647                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1652                 }
1653         }
1654
1655         I40E_WRITE_FLUSH(hw);
1656 }
1657
1658 void
1659 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1660 {
1661         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1662         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1663         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1664         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1665         uint16_t msix_vect = vsi->msix_intr;
1666         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1667         uint16_t queue_idx = 0;
1668         int record = 0;
1669         uint32_t val;
1670         int i;
1671
1672         for (i = 0; i < vsi->nb_qps; i++) {
1673                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1674                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1675         }
1676
1677         /* INTENA flag is not auto-cleared for interrupt */
1678         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1679         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1680                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1681                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1682         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1683
1684         /* VF bind interrupt */
1685         if (vsi->type == I40E_VSI_SRIOV) {
1686                 __vsi_queues_bind_intr(vsi, msix_vect,
1687                                        vsi->base_queue, vsi->nb_qps);
1688                 return;
1689         }
1690
1691         /* PF & VMDq bind interrupt */
1692         if (rte_intr_dp_is_en(intr_handle)) {
1693                 if (vsi->type == I40E_VSI_MAIN) {
1694                         queue_idx = 0;
1695                         record = 1;
1696                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1697                         struct i40e_vsi *main_vsi =
1698                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1699                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1700                         record = 1;
1701                 }
1702         }
1703
1704         for (i = 0; i < vsi->nb_used_qps; i++) {
1705                 if (nb_msix <= 1) {
1706                         if (!rte_intr_allow_others(intr_handle))
1707                                 /* allow to share MISC_VEC_ID */
1708                                 msix_vect = I40E_MISC_VEC_ID;
1709
1710                         /* no enough msix_vect, map all to one */
1711                         __vsi_queues_bind_intr(vsi, msix_vect,
1712                                                vsi->base_queue + i,
1713                                                vsi->nb_used_qps - i);
1714                         for (; !!record && i < vsi->nb_used_qps; i++)
1715                                 intr_handle->intr_vec[queue_idx + i] =
1716                                         msix_vect;
1717                         break;
1718                 }
1719                 /* 1:1 queue/msix_vect mapping */
1720                 __vsi_queues_bind_intr(vsi, msix_vect,
1721                                        vsi->base_queue + i, 1);
1722                 if (!!record)
1723                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1724
1725                 msix_vect++;
1726                 nb_msix--;
1727         }
1728 }
1729
1730 static void
1731 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1732 {
1733         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1734         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1735         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1737         uint16_t interval = i40e_calc_itr_interval(\
1738                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1739         uint16_t msix_intr, i;
1740
1741         if (rte_intr_allow_others(intr_handle))
1742                 for (i = 0; i < vsi->nb_msix; i++) {
1743                         msix_intr = vsi->msix_intr + i;
1744                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1745                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1746                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1747                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1748                                 (interval <<
1749                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1750                 }
1751         else
1752                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1753                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1754                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1755                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1756                                (interval <<
1757                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1758
1759         I40E_WRITE_FLUSH(hw);
1760 }
1761
1762 static void
1763 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1764 {
1765         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1766         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1767         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1768         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1769         uint16_t msix_intr, i;
1770
1771         if (rte_intr_allow_others(intr_handle))
1772                 for (i = 0; i < vsi->nb_msix; i++) {
1773                         msix_intr = vsi->msix_intr + i;
1774                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1775                                        0);
1776                 }
1777         else
1778                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1779
1780         I40E_WRITE_FLUSH(hw);
1781 }
1782
1783 static inline uint8_t
1784 i40e_parse_link_speeds(uint16_t link_speeds)
1785 {
1786         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1787
1788         if (link_speeds & ETH_LINK_SPEED_40G)
1789                 link_speed |= I40E_LINK_SPEED_40GB;
1790         if (link_speeds & ETH_LINK_SPEED_25G)
1791                 link_speed |= I40E_LINK_SPEED_25GB;
1792         if (link_speeds & ETH_LINK_SPEED_20G)
1793                 link_speed |= I40E_LINK_SPEED_20GB;
1794         if (link_speeds & ETH_LINK_SPEED_10G)
1795                 link_speed |= I40E_LINK_SPEED_10GB;
1796         if (link_speeds & ETH_LINK_SPEED_1G)
1797                 link_speed |= I40E_LINK_SPEED_1GB;
1798         if (link_speeds & ETH_LINK_SPEED_100M)
1799                 link_speed |= I40E_LINK_SPEED_100MB;
1800
1801         return link_speed;
1802 }
1803
1804 static int
1805 i40e_phy_conf_link(struct i40e_hw *hw,
1806                    uint8_t abilities,
1807                    uint8_t force_speed)
1808 {
1809         enum i40e_status_code status;
1810         struct i40e_aq_get_phy_abilities_resp phy_ab;
1811         struct i40e_aq_set_phy_config phy_conf;
1812         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1813                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1814                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1815                         I40E_AQ_PHY_FLAG_LOW_POWER;
1816         const uint8_t advt = I40E_LINK_SPEED_40GB |
1817                         I40E_LINK_SPEED_25GB |
1818                         I40E_LINK_SPEED_10GB |
1819                         I40E_LINK_SPEED_1GB |
1820                         I40E_LINK_SPEED_100MB;
1821         int ret = -ENOTSUP;
1822
1823
1824         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1825                                               NULL);
1826         if (status)
1827                 return ret;
1828
1829         memset(&phy_conf, 0, sizeof(phy_conf));
1830
1831         /* bits 0-2 use the values from get_phy_abilities_resp */
1832         abilities &= ~mask;
1833         abilities |= phy_ab.abilities & mask;
1834
1835         /* update ablities and speed */
1836         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1837                 phy_conf.link_speed = advt;
1838         else
1839                 phy_conf.link_speed = force_speed;
1840
1841         phy_conf.abilities = abilities;
1842
1843         /* use get_phy_abilities_resp value for the rest */
1844         phy_conf.phy_type = phy_ab.phy_type;
1845         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1846         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1847         phy_conf.eee_capability = phy_ab.eee_capability;
1848         phy_conf.eeer = phy_ab.eeer_val;
1849         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1850
1851         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1852                     phy_ab.abilities, phy_ab.link_speed);
1853         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1854                     phy_conf.abilities, phy_conf.link_speed);
1855
1856         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1857         if (status)
1858                 return ret;
1859
1860         return I40E_SUCCESS;
1861 }
1862
1863 static int
1864 i40e_apply_link_speed(struct rte_eth_dev *dev)
1865 {
1866         uint8_t speed;
1867         uint8_t abilities = 0;
1868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         struct rte_eth_conf *conf = &dev->data->dev_conf;
1870
1871         speed = i40e_parse_link_speeds(conf->link_speeds);
1872         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1873         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1874                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1875         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1876
1877         /* Skip changing speed on 40G interfaces, FW does not support */
1878         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1879                 speed =  I40E_LINK_SPEED_UNKNOWN;
1880                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1881         }
1882
1883         return i40e_phy_conf_link(hw, abilities, speed);
1884 }
1885
1886 static int
1887 i40e_dev_start(struct rte_eth_dev *dev)
1888 {
1889         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891         struct i40e_vsi *main_vsi = pf->main_vsi;
1892         int ret, i;
1893         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1894         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1895         uint32_t intr_vector = 0;
1896         struct i40e_vsi *vsi;
1897
1898         hw->adapter_stopped = 0;
1899
1900         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1901                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1902                              dev->data->port_id);
1903                 return -EINVAL;
1904         }
1905
1906         rte_intr_disable(intr_handle);
1907
1908         if ((rte_intr_cap_multiple(intr_handle) ||
1909              !RTE_ETH_DEV_SRIOV(dev).active) &&
1910             dev->data->dev_conf.intr_conf.rxq != 0) {
1911                 intr_vector = dev->data->nb_rx_queues;
1912                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1913                 if (ret)
1914                         return ret;
1915         }
1916
1917         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1918                 intr_handle->intr_vec =
1919                         rte_zmalloc("intr_vec",
1920                                     dev->data->nb_rx_queues * sizeof(int),
1921                                     0);
1922                 if (!intr_handle->intr_vec) {
1923                         PMD_INIT_LOG(ERR,
1924                                 "Failed to allocate %d rx_queues intr_vec",
1925                                 dev->data->nb_rx_queues);
1926                         return -ENOMEM;
1927                 }
1928         }
1929
1930         /* Initialize VSI */
1931         ret = i40e_dev_rxtx_init(pf);
1932         if (ret != I40E_SUCCESS) {
1933                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1934                 goto err_up;
1935         }
1936
1937         /* Map queues with MSIX interrupt */
1938         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1939                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1940         i40e_vsi_queues_bind_intr(main_vsi);
1941         i40e_vsi_enable_queues_intr(main_vsi);
1942
1943         /* Map VMDQ VSI queues with MSIX interrupt */
1944         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1945                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1946                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1947                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1948         }
1949
1950         /* enable FDIR MSIX interrupt */
1951         if (pf->fdir.fdir_vsi) {
1952                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1953                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1954         }
1955
1956         /* Enable all queues which have been configured */
1957         ret = i40e_dev_switch_queues(pf, TRUE);
1958         if (ret != I40E_SUCCESS) {
1959                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1960                 goto err_up;
1961         }
1962
1963         /* Enable receiving broadcast packets */
1964         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1965         if (ret != I40E_SUCCESS)
1966                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1967
1968         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1969                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1970                                                 true, NULL);
1971                 if (ret != I40E_SUCCESS)
1972                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1973         }
1974
1975         /* Enable the VLAN promiscuous mode. */
1976         if (pf->vfs) {
1977                 for (i = 0; i < pf->vf_num; i++) {
1978                         vsi = pf->vfs[i].vsi;
1979                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1980                                                      true, NULL);
1981                 }
1982         }
1983
1984         /* Apply link configure */
1985         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1986                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1987                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1988                                 ETH_LINK_SPEED_40G)) {
1989                 PMD_DRV_LOG(ERR, "Invalid link setting");
1990                 goto err_up;
1991         }
1992         ret = i40e_apply_link_speed(dev);
1993         if (I40E_SUCCESS != ret) {
1994                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1995                 goto err_up;
1996         }
1997
1998         if (!rte_intr_allow_others(intr_handle)) {
1999                 rte_intr_callback_unregister(intr_handle,
2000                                              i40e_dev_interrupt_handler,
2001                                              (void *)dev);
2002                 /* configure and enable device interrupt */
2003                 i40e_pf_config_irq0(hw, FALSE);
2004                 i40e_pf_enable_irq0(hw);
2005
2006                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2007                         PMD_INIT_LOG(INFO,
2008                                 "lsc won't enable because of no intr multiplex");
2009         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2010                 ret = i40e_aq_set_phy_int_mask(hw,
2011                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2012                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2013                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2014                 if (ret != I40E_SUCCESS)
2015                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2016
2017                 /* Call get_link_info aq commond to enable LSE */
2018                 i40e_dev_link_update(dev, 0);
2019         }
2020
2021         /* enable uio intr after callback register */
2022         rte_intr_enable(intr_handle);
2023
2024         i40e_filter_restore(pf);
2025
2026         return I40E_SUCCESS;
2027
2028 err_up:
2029         i40e_dev_switch_queues(pf, FALSE);
2030         i40e_dev_clear_queues(dev);
2031
2032         return ret;
2033 }
2034
2035 static void
2036 i40e_dev_stop(struct rte_eth_dev *dev)
2037 {
2038         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2039         struct i40e_vsi *main_vsi = pf->main_vsi;
2040         struct i40e_mirror_rule *p_mirror;
2041         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2042         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2043         int i;
2044
2045         /* Disable all queues */
2046         i40e_dev_switch_queues(pf, FALSE);
2047
2048         /* un-map queues with interrupt registers */
2049         i40e_vsi_disable_queues_intr(main_vsi);
2050         i40e_vsi_queues_unbind_intr(main_vsi);
2051
2052         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2053                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2054                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2055         }
2056
2057         if (pf->fdir.fdir_vsi) {
2058                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2059                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2060         }
2061         /* Clear all queues and release memory */
2062         i40e_dev_clear_queues(dev);
2063
2064         /* Set link down */
2065         i40e_dev_set_link_down(dev);
2066
2067         /* Remove all mirror rules */
2068         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2069                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2070                 rte_free(p_mirror);
2071         }
2072         pf->nb_mirror_rule = 0;
2073
2074         if (!rte_intr_allow_others(intr_handle))
2075                 /* resume to the default handler */
2076                 rte_intr_callback_register(intr_handle,
2077                                            i40e_dev_interrupt_handler,
2078                                            (void *)dev);
2079
2080         /* Clean datapath event and queue/vec mapping */
2081         rte_intr_efd_disable(intr_handle);
2082         if (intr_handle->intr_vec) {
2083                 rte_free(intr_handle->intr_vec);
2084                 intr_handle->intr_vec = NULL;
2085         }
2086 }
2087
2088 static void
2089 i40e_dev_close(struct rte_eth_dev *dev)
2090 {
2091         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2094         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2095         uint32_t reg;
2096         int i;
2097
2098         PMD_INIT_FUNC_TRACE();
2099
2100         i40e_dev_stop(dev);
2101         hw->adapter_stopped = 1;
2102         i40e_dev_free_queues(dev);
2103
2104         /* Disable interrupt */
2105         i40e_pf_disable_irq0(hw);
2106         rte_intr_disable(intr_handle);
2107
2108         /* shutdown and destroy the HMC */
2109         i40e_shutdown_lan_hmc(hw);
2110
2111         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2112                 i40e_vsi_release(pf->vmdq[i].vsi);
2113                 pf->vmdq[i].vsi = NULL;
2114         }
2115         rte_free(pf->vmdq);
2116         pf->vmdq = NULL;
2117
2118         /* release all the existing VSIs and VEBs */
2119         i40e_fdir_teardown(pf);
2120         i40e_vsi_release(pf->main_vsi);
2121
2122         /* shutdown the adminq */
2123         i40e_aq_queue_shutdown(hw, true);
2124         i40e_shutdown_adminq(hw);
2125
2126         i40e_res_pool_destroy(&pf->qp_pool);
2127         i40e_res_pool_destroy(&pf->msix_pool);
2128
2129         /* force a PF reset to clean anything leftover */
2130         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2131         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2132                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2133         I40E_WRITE_FLUSH(hw);
2134 }
2135
2136 static void
2137 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2138 {
2139         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         struct i40e_vsi *vsi = pf->main_vsi;
2142         int status;
2143
2144         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2145                                                      true, NULL, true);
2146         if (status != I40E_SUCCESS)
2147                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2148
2149         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2150                                                         TRUE, NULL);
2151         if (status != I40E_SUCCESS)
2152                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2153
2154 }
2155
2156 static void
2157 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2158 {
2159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         struct i40e_vsi *vsi = pf->main_vsi;
2162         int status;
2163
2164         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2165                                                      false, NULL, true);
2166         if (status != I40E_SUCCESS)
2167                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2168
2169         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2170                                                         false, NULL);
2171         if (status != I40E_SUCCESS)
2172                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2173 }
2174
2175 static void
2176 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2177 {
2178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180         struct i40e_vsi *vsi = pf->main_vsi;
2181         int ret;
2182
2183         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2184         if (ret != I40E_SUCCESS)
2185                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2186 }
2187
2188 static void
2189 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2190 {
2191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         struct i40e_vsi *vsi = pf->main_vsi;
2194         int ret;
2195
2196         if (dev->data->promiscuous == 1)
2197                 return; /* must remain in all_multicast mode */
2198
2199         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2200                                 vsi->seid, FALSE, NULL);
2201         if (ret != I40E_SUCCESS)
2202                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2203 }
2204
2205 /*
2206  * Set device link up.
2207  */
2208 static int
2209 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2210 {
2211         /* re-apply link speed setting */
2212         return i40e_apply_link_speed(dev);
2213 }
2214
2215 /*
2216  * Set device link down.
2217  */
2218 static int
2219 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2220 {
2221         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2222         uint8_t abilities = 0;
2223         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224
2225         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2226         return i40e_phy_conf_link(hw, abilities, speed);
2227 }
2228
2229 int
2230 i40e_dev_link_update(struct rte_eth_dev *dev,
2231                      int wait_to_complete)
2232 {
2233 #define CHECK_INTERVAL 100  /* 100ms */
2234 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236         struct i40e_link_status link_status;
2237         struct rte_eth_link link, old;
2238         int status;
2239         unsigned rep_cnt = MAX_REPEAT_TIME;
2240         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2241
2242         memset(&link, 0, sizeof(link));
2243         memset(&old, 0, sizeof(old));
2244         memset(&link_status, 0, sizeof(link_status));
2245         rte_i40e_dev_atomic_read_link_status(dev, &old);
2246
2247         do {
2248                 /* Get link status information from hardware */
2249                 status = i40e_aq_get_link_info(hw, enable_lse,
2250                                                 &link_status, NULL);
2251                 if (status != I40E_SUCCESS) {
2252                         link.link_speed = ETH_SPEED_NUM_100M;
2253                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2254                         PMD_DRV_LOG(ERR, "Failed to get link info");
2255                         goto out;
2256                 }
2257
2258                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2259                 if (!wait_to_complete || link.link_status)
2260                         break;
2261
2262                 rte_delay_ms(CHECK_INTERVAL);
2263         } while (--rep_cnt);
2264
2265         if (!link.link_status)
2266                 goto out;
2267
2268         /* i40e uses full duplex only */
2269         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2270
2271         /* Parse the link status */
2272         switch (link_status.link_speed) {
2273         case I40E_LINK_SPEED_100MB:
2274                 link.link_speed = ETH_SPEED_NUM_100M;
2275                 break;
2276         case I40E_LINK_SPEED_1GB:
2277                 link.link_speed = ETH_SPEED_NUM_1G;
2278                 break;
2279         case I40E_LINK_SPEED_10GB:
2280                 link.link_speed = ETH_SPEED_NUM_10G;
2281                 break;
2282         case I40E_LINK_SPEED_20GB:
2283                 link.link_speed = ETH_SPEED_NUM_20G;
2284                 break;
2285         case I40E_LINK_SPEED_25GB:
2286                 link.link_speed = ETH_SPEED_NUM_25G;
2287                 break;
2288         case I40E_LINK_SPEED_40GB:
2289                 link.link_speed = ETH_SPEED_NUM_40G;
2290                 break;
2291         default:
2292                 link.link_speed = ETH_SPEED_NUM_100M;
2293                 break;
2294         }
2295
2296         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2297                         ETH_LINK_SPEED_FIXED);
2298
2299 out:
2300         rte_i40e_dev_atomic_write_link_status(dev, &link);
2301         if (link.link_status == old.link_status)
2302                 return -1;
2303
2304         return 0;
2305 }
2306
2307 /* Get all the statistics of a VSI */
2308 void
2309 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2310 {
2311         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2312         struct i40e_eth_stats *nes = &vsi->eth_stats;
2313         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2314         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2315
2316         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2317                             vsi->offset_loaded, &oes->rx_bytes,
2318                             &nes->rx_bytes);
2319         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2320                             vsi->offset_loaded, &oes->rx_unicast,
2321                             &nes->rx_unicast);
2322         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2323                             vsi->offset_loaded, &oes->rx_multicast,
2324                             &nes->rx_multicast);
2325         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2326                             vsi->offset_loaded, &oes->rx_broadcast,
2327                             &nes->rx_broadcast);
2328         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2329                             &oes->rx_discards, &nes->rx_discards);
2330         /* GLV_REPC not supported */
2331         /* GLV_RMPC not supported */
2332         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2333                             &oes->rx_unknown_protocol,
2334                             &nes->rx_unknown_protocol);
2335         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2336                             vsi->offset_loaded, &oes->tx_bytes,
2337                             &nes->tx_bytes);
2338         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2339                             vsi->offset_loaded, &oes->tx_unicast,
2340                             &nes->tx_unicast);
2341         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2342                             vsi->offset_loaded, &oes->tx_multicast,
2343                             &nes->tx_multicast);
2344         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2345                             vsi->offset_loaded,  &oes->tx_broadcast,
2346                             &nes->tx_broadcast);
2347         /* GLV_TDPC not supported */
2348         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2349                             &oes->tx_errors, &nes->tx_errors);
2350         vsi->offset_loaded = true;
2351
2352         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2353                     vsi->vsi_id);
2354         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2355         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2356         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2357         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2358         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2359         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2360                     nes->rx_unknown_protocol);
2361         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2362         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2363         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2364         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2365         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2366         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2367         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2368                     vsi->vsi_id);
2369 }
2370
2371 static void
2372 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2373 {
2374         unsigned int i;
2375         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2376         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2377
2378         /* Get statistics of struct i40e_eth_stats */
2379         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2380                             I40E_GLPRT_GORCL(hw->port),
2381                             pf->offset_loaded, &os->eth.rx_bytes,
2382                             &ns->eth.rx_bytes);
2383         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2384                             I40E_GLPRT_UPRCL(hw->port),
2385                             pf->offset_loaded, &os->eth.rx_unicast,
2386                             &ns->eth.rx_unicast);
2387         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2388                             I40E_GLPRT_MPRCL(hw->port),
2389                             pf->offset_loaded, &os->eth.rx_multicast,
2390                             &ns->eth.rx_multicast);
2391         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2392                             I40E_GLPRT_BPRCL(hw->port),
2393                             pf->offset_loaded, &os->eth.rx_broadcast,
2394                             &ns->eth.rx_broadcast);
2395         /* Workaround: CRC size should not be included in byte statistics,
2396          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2397          */
2398         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2399                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2400
2401         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2402                             pf->offset_loaded, &os->eth.rx_discards,
2403                             &ns->eth.rx_discards);
2404         /* GLPRT_REPC not supported */
2405         /* GLPRT_RMPC not supported */
2406         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2407                             pf->offset_loaded,
2408                             &os->eth.rx_unknown_protocol,
2409                             &ns->eth.rx_unknown_protocol);
2410         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2411                             I40E_GLPRT_GOTCL(hw->port),
2412                             pf->offset_loaded, &os->eth.tx_bytes,
2413                             &ns->eth.tx_bytes);
2414         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2415                             I40E_GLPRT_UPTCL(hw->port),
2416                             pf->offset_loaded, &os->eth.tx_unicast,
2417                             &ns->eth.tx_unicast);
2418         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2419                             I40E_GLPRT_MPTCL(hw->port),
2420                             pf->offset_loaded, &os->eth.tx_multicast,
2421                             &ns->eth.tx_multicast);
2422         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2423                             I40E_GLPRT_BPTCL(hw->port),
2424                             pf->offset_loaded, &os->eth.tx_broadcast,
2425                             &ns->eth.tx_broadcast);
2426         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2427                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2428         /* GLPRT_TEPC not supported */
2429
2430         /* additional port specific stats */
2431         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2432                             pf->offset_loaded, &os->tx_dropped_link_down,
2433                             &ns->tx_dropped_link_down);
2434         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2435                             pf->offset_loaded, &os->crc_errors,
2436                             &ns->crc_errors);
2437         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2438                             pf->offset_loaded, &os->illegal_bytes,
2439                             &ns->illegal_bytes);
2440         /* GLPRT_ERRBC not supported */
2441         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2442                             pf->offset_loaded, &os->mac_local_faults,
2443                             &ns->mac_local_faults);
2444         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2445                             pf->offset_loaded, &os->mac_remote_faults,
2446                             &ns->mac_remote_faults);
2447         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2448                             pf->offset_loaded, &os->rx_length_errors,
2449                             &ns->rx_length_errors);
2450         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2451                             pf->offset_loaded, &os->link_xon_rx,
2452                             &ns->link_xon_rx);
2453         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2454                             pf->offset_loaded, &os->link_xoff_rx,
2455                             &ns->link_xoff_rx);
2456         for (i = 0; i < 8; i++) {
2457                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2458                                     pf->offset_loaded,
2459                                     &os->priority_xon_rx[i],
2460                                     &ns->priority_xon_rx[i]);
2461                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2462                                     pf->offset_loaded,
2463                                     &os->priority_xoff_rx[i],
2464                                     &ns->priority_xoff_rx[i]);
2465         }
2466         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2467                             pf->offset_loaded, &os->link_xon_tx,
2468                             &ns->link_xon_tx);
2469         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2470                             pf->offset_loaded, &os->link_xoff_tx,
2471                             &ns->link_xoff_tx);
2472         for (i = 0; i < 8; i++) {
2473                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2474                                     pf->offset_loaded,
2475                                     &os->priority_xon_tx[i],
2476                                     &ns->priority_xon_tx[i]);
2477                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2478                                     pf->offset_loaded,
2479                                     &os->priority_xoff_tx[i],
2480                                     &ns->priority_xoff_tx[i]);
2481                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2482                                     pf->offset_loaded,
2483                                     &os->priority_xon_2_xoff[i],
2484                                     &ns->priority_xon_2_xoff[i]);
2485         }
2486         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2487                             I40E_GLPRT_PRC64L(hw->port),
2488                             pf->offset_loaded, &os->rx_size_64,
2489                             &ns->rx_size_64);
2490         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2491                             I40E_GLPRT_PRC127L(hw->port),
2492                             pf->offset_loaded, &os->rx_size_127,
2493                             &ns->rx_size_127);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2495                             I40E_GLPRT_PRC255L(hw->port),
2496                             pf->offset_loaded, &os->rx_size_255,
2497                             &ns->rx_size_255);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2499                             I40E_GLPRT_PRC511L(hw->port),
2500                             pf->offset_loaded, &os->rx_size_511,
2501                             &ns->rx_size_511);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2503                             I40E_GLPRT_PRC1023L(hw->port),
2504                             pf->offset_loaded, &os->rx_size_1023,
2505                             &ns->rx_size_1023);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2507                             I40E_GLPRT_PRC1522L(hw->port),
2508                             pf->offset_loaded, &os->rx_size_1522,
2509                             &ns->rx_size_1522);
2510         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2511                             I40E_GLPRT_PRC9522L(hw->port),
2512                             pf->offset_loaded, &os->rx_size_big,
2513                             &ns->rx_size_big);
2514         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2515                             pf->offset_loaded, &os->rx_undersize,
2516                             &ns->rx_undersize);
2517         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2518                             pf->offset_loaded, &os->rx_fragments,
2519                             &ns->rx_fragments);
2520         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2521                             pf->offset_loaded, &os->rx_oversize,
2522                             &ns->rx_oversize);
2523         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2524                             pf->offset_loaded, &os->rx_jabber,
2525                             &ns->rx_jabber);
2526         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2527                             I40E_GLPRT_PTC64L(hw->port),
2528                             pf->offset_loaded, &os->tx_size_64,
2529                             &ns->tx_size_64);
2530         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2531                             I40E_GLPRT_PTC127L(hw->port),
2532                             pf->offset_loaded, &os->tx_size_127,
2533                             &ns->tx_size_127);
2534         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2535                             I40E_GLPRT_PTC255L(hw->port),
2536                             pf->offset_loaded, &os->tx_size_255,
2537                             &ns->tx_size_255);
2538         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2539                             I40E_GLPRT_PTC511L(hw->port),
2540                             pf->offset_loaded, &os->tx_size_511,
2541                             &ns->tx_size_511);
2542         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2543                             I40E_GLPRT_PTC1023L(hw->port),
2544                             pf->offset_loaded, &os->tx_size_1023,
2545                             &ns->tx_size_1023);
2546         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2547                             I40E_GLPRT_PTC1522L(hw->port),
2548                             pf->offset_loaded, &os->tx_size_1522,
2549                             &ns->tx_size_1522);
2550         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2551                             I40E_GLPRT_PTC9522L(hw->port),
2552                             pf->offset_loaded, &os->tx_size_big,
2553                             &ns->tx_size_big);
2554         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2555                            pf->offset_loaded,
2556                            &os->fd_sb_match, &ns->fd_sb_match);
2557         /* GLPRT_MSPDC not supported */
2558         /* GLPRT_XEC not supported */
2559
2560         pf->offset_loaded = true;
2561
2562         if (pf->main_vsi)
2563                 i40e_update_vsi_stats(pf->main_vsi);
2564 }
2565
2566 /* Get all statistics of a port */
2567 static void
2568 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2569 {
2570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2573         unsigned i;
2574
2575         /* call read registers - updates values, now write them to struct */
2576         i40e_read_stats_registers(pf, hw);
2577
2578         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2579                         pf->main_vsi->eth_stats.rx_multicast +
2580                         pf->main_vsi->eth_stats.rx_broadcast -
2581                         pf->main_vsi->eth_stats.rx_discards;
2582         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2583                         pf->main_vsi->eth_stats.tx_multicast +
2584                         pf->main_vsi->eth_stats.tx_broadcast;
2585         stats->ibytes   = ns->eth.rx_bytes;
2586         stats->obytes   = ns->eth.tx_bytes;
2587         stats->oerrors  = ns->eth.tx_errors +
2588                         pf->main_vsi->eth_stats.tx_errors;
2589
2590         /* Rx Errors */
2591         stats->imissed  = ns->eth.rx_discards +
2592                         pf->main_vsi->eth_stats.rx_discards;
2593         stats->ierrors  = ns->crc_errors +
2594                         ns->rx_length_errors + ns->rx_undersize +
2595                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2596
2597         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2598         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2599         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2600         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2601         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2602         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2603         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2604                     ns->eth.rx_unknown_protocol);
2605         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2606         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2607         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2608         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2609         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2610         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2611
2612         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2613                     ns->tx_dropped_link_down);
2614         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2615         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2616                     ns->illegal_bytes);
2617         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2618         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2619                     ns->mac_local_faults);
2620         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2621                     ns->mac_remote_faults);
2622         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2623                     ns->rx_length_errors);
2624         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2625         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2626         for (i = 0; i < 8; i++) {
2627                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2628                                 i, ns->priority_xon_rx[i]);
2629                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2630                                 i, ns->priority_xoff_rx[i]);
2631         }
2632         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2633         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2634         for (i = 0; i < 8; i++) {
2635                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2636                                 i, ns->priority_xon_tx[i]);
2637                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2638                                 i, ns->priority_xoff_tx[i]);
2639                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2640                                 i, ns->priority_xon_2_xoff[i]);
2641         }
2642         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2643         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2644         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2645         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2646         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2647         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2648         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2649         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2650         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2651         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2652         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2653         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2654         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2655         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2656         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2657         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2658         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2659         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2660         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2661                         ns->mac_short_packet_dropped);
2662         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2663                     ns->checksum_error);
2664         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2665         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2666 }
2667
2668 /* Reset the statistics */
2669 static void
2670 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2671 {
2672         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2673         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674
2675         /* Mark PF and VSI stats to update the offset, aka "reset" */
2676         pf->offset_loaded = false;
2677         if (pf->main_vsi)
2678                 pf->main_vsi->offset_loaded = false;
2679
2680         /* read the stats, reading current register values into offset */
2681         i40e_read_stats_registers(pf, hw);
2682 }
2683
2684 static uint32_t
2685 i40e_xstats_calc_num(void)
2686 {
2687         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2688                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2689                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2690 }
2691
2692 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2693                                      struct rte_eth_xstat_name *xstats_names,
2694                                      __rte_unused unsigned limit)
2695 {
2696         unsigned count = 0;
2697         unsigned i, prio;
2698
2699         if (xstats_names == NULL)
2700                 return i40e_xstats_calc_num();
2701
2702         /* Note: limit checked in rte_eth_xstats_names() */
2703
2704         /* Get stats from i40e_eth_stats struct */
2705         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2706                 snprintf(xstats_names[count].name,
2707                          sizeof(xstats_names[count].name),
2708                          "%s", rte_i40e_stats_strings[i].name);
2709                 count++;
2710         }
2711
2712         /* Get individiual stats from i40e_hw_port struct */
2713         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2714                 snprintf(xstats_names[count].name,
2715                         sizeof(xstats_names[count].name),
2716                          "%s", rte_i40e_hw_port_strings[i].name);
2717                 count++;
2718         }
2719
2720         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2721                 for (prio = 0; prio < 8; prio++) {
2722                         snprintf(xstats_names[count].name,
2723                                  sizeof(xstats_names[count].name),
2724                                  "rx_priority%u_%s", prio,
2725                                  rte_i40e_rxq_prio_strings[i].name);
2726                         count++;
2727                 }
2728         }
2729
2730         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2731                 for (prio = 0; prio < 8; prio++) {
2732                         snprintf(xstats_names[count].name,
2733                                  sizeof(xstats_names[count].name),
2734                                  "tx_priority%u_%s", prio,
2735                                  rte_i40e_txq_prio_strings[i].name);
2736                         count++;
2737                 }
2738         }
2739         return count;
2740 }
2741
2742 static int
2743 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2744                     unsigned n)
2745 {
2746         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2747         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2748         unsigned i, count, prio;
2749         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2750
2751         count = i40e_xstats_calc_num();
2752         if (n < count)
2753                 return count;
2754
2755         i40e_read_stats_registers(pf, hw);
2756
2757         if (xstats == NULL)
2758                 return 0;
2759
2760         count = 0;
2761
2762         /* Get stats from i40e_eth_stats struct */
2763         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2764                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2765                         rte_i40e_stats_strings[i].offset);
2766                 xstats[count].id = count;
2767                 count++;
2768         }
2769
2770         /* Get individiual stats from i40e_hw_port struct */
2771         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2772                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2773                         rte_i40e_hw_port_strings[i].offset);
2774                 xstats[count].id = count;
2775                 count++;
2776         }
2777
2778         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2779                 for (prio = 0; prio < 8; prio++) {
2780                         xstats[count].value =
2781                                 *(uint64_t *)(((char *)hw_stats) +
2782                                 rte_i40e_rxq_prio_strings[i].offset +
2783                                 (sizeof(uint64_t) * prio));
2784                         xstats[count].id = count;
2785                         count++;
2786                 }
2787         }
2788
2789         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2790                 for (prio = 0; prio < 8; prio++) {
2791                         xstats[count].value =
2792                                 *(uint64_t *)(((char *)hw_stats) +
2793                                 rte_i40e_txq_prio_strings[i].offset +
2794                                 (sizeof(uint64_t) * prio));
2795                         xstats[count].id = count;
2796                         count++;
2797                 }
2798         }
2799
2800         return count;
2801 }
2802
2803 static int
2804 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2805                                  __rte_unused uint16_t queue_id,
2806                                  __rte_unused uint8_t stat_idx,
2807                                  __rte_unused uint8_t is_rx)
2808 {
2809         PMD_INIT_FUNC_TRACE();
2810
2811         return -ENOSYS;
2812 }
2813
2814 static int
2815 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2816 {
2817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         u32 full_ver;
2819         u8 ver, patch;
2820         u16 build;
2821         int ret;
2822
2823         full_ver = hw->nvm.oem_ver;
2824         ver = (u8)(full_ver >> 24);
2825         build = (u16)((full_ver >> 8) & 0xffff);
2826         patch = (u8)(full_ver & 0xff);
2827
2828         ret = snprintf(fw_version, fw_size,
2829                  "%d.%d%d 0x%08x %d.%d.%d",
2830                  ((hw->nvm.version >> 12) & 0xf),
2831                  ((hw->nvm.version >> 4) & 0xff),
2832                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2833                  ver, build, patch);
2834
2835         ret += 1; /* add the size of '\0' */
2836         if (fw_size < (u32)ret)
2837                 return ret;
2838         else
2839                 return 0;
2840 }
2841
2842 static void
2843 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2844 {
2845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847         struct i40e_vsi *vsi = pf->main_vsi;
2848         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2849
2850         dev_info->pci_dev = pci_dev;
2851         dev_info->max_rx_queues = vsi->nb_qps;
2852         dev_info->max_tx_queues = vsi->nb_qps;
2853         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2854         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2855         dev_info->max_mac_addrs = vsi->max_macaddrs;
2856         dev_info->max_vfs = pci_dev->max_vfs;
2857         dev_info->rx_offload_capa =
2858                 DEV_RX_OFFLOAD_VLAN_STRIP |
2859                 DEV_RX_OFFLOAD_QINQ_STRIP |
2860                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2861                 DEV_RX_OFFLOAD_UDP_CKSUM |
2862                 DEV_RX_OFFLOAD_TCP_CKSUM;
2863         dev_info->tx_offload_capa =
2864                 DEV_TX_OFFLOAD_VLAN_INSERT |
2865                 DEV_TX_OFFLOAD_QINQ_INSERT |
2866                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2867                 DEV_TX_OFFLOAD_UDP_CKSUM |
2868                 DEV_TX_OFFLOAD_TCP_CKSUM |
2869                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2870                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2871                 DEV_TX_OFFLOAD_TCP_TSO |
2872                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2873                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2874                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2875                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2876         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2877                                                 sizeof(uint32_t);
2878         dev_info->reta_size = pf->hash_lut_size;
2879         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2880
2881         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2882                 .rx_thresh = {
2883                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2884                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2885                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2886                 },
2887                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2888                 .rx_drop_en = 0,
2889         };
2890
2891         dev_info->default_txconf = (struct rte_eth_txconf) {
2892                 .tx_thresh = {
2893                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2894                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2895                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2896                 },
2897                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2898                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2899                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2900                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2901         };
2902
2903         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2904                 .nb_max = I40E_MAX_RING_DESC,
2905                 .nb_min = I40E_MIN_RING_DESC,
2906                 .nb_align = I40E_ALIGN_RING_DESC,
2907         };
2908
2909         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2910                 .nb_max = I40E_MAX_RING_DESC,
2911                 .nb_min = I40E_MIN_RING_DESC,
2912                 .nb_align = I40E_ALIGN_RING_DESC,
2913                 .nb_seg_max = I40E_TX_MAX_SEG,
2914                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2915         };
2916
2917         if (pf->flags & I40E_FLAG_VMDQ) {
2918                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2919                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2920                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2921                                                 pf->max_nb_vmdq_vsi;
2922                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2923                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2924                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2925         }
2926
2927         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2928                 /* For XL710 */
2929                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2930         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2931                 /* For XXV710 */
2932                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2933         else
2934                 /* For X710 */
2935                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2936 }
2937
2938 static int
2939 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2940 {
2941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2942         struct i40e_vsi *vsi = pf->main_vsi;
2943         PMD_INIT_FUNC_TRACE();
2944
2945         if (on)
2946                 return i40e_vsi_add_vlan(vsi, vlan_id);
2947         else
2948                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2949 }
2950
2951 static int
2952 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2953                    enum rte_vlan_type vlan_type,
2954                    uint16_t tpid)
2955 {
2956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957         uint64_t reg_r = 0, reg_w = 0;
2958         uint16_t reg_id = 0;
2959         int ret = 0;
2960         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2961
2962         switch (vlan_type) {
2963         case ETH_VLAN_TYPE_OUTER:
2964                 if (qinq)
2965                         reg_id = 2;
2966                 else
2967                         reg_id = 3;
2968                 break;
2969         case ETH_VLAN_TYPE_INNER:
2970                 if (qinq)
2971                         reg_id = 3;
2972                 else {
2973                         ret = -EINVAL;
2974                         PMD_DRV_LOG(ERR,
2975                                 "Unsupported vlan type in single vlan.");
2976                         return ret;
2977                 }
2978                 break;
2979         default:
2980                 ret = -EINVAL;
2981                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2982                 return ret;
2983         }
2984         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2985                                           &reg_r, NULL);
2986         if (ret != I40E_SUCCESS) {
2987                 PMD_DRV_LOG(ERR,
2988                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2989                            reg_id);
2990                 ret = -EIO;
2991                 return ret;
2992         }
2993         PMD_DRV_LOG(DEBUG,
2994                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2995                 reg_id, reg_r);
2996
2997         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2998         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2999         if (reg_r == reg_w) {
3000                 ret = 0;
3001                 PMD_DRV_LOG(DEBUG, "No need to write");
3002                 return ret;
3003         }
3004
3005         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3006                                            reg_w, NULL);
3007         if (ret != I40E_SUCCESS) {
3008                 ret = -EIO;
3009                 PMD_DRV_LOG(ERR,
3010                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3011                         reg_id);
3012                 return ret;
3013         }
3014         PMD_DRV_LOG(DEBUG,
3015                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3016                 reg_w, reg_id);
3017
3018         return ret;
3019 }
3020
3021 static void
3022 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3023 {
3024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3025         struct i40e_vsi *vsi = pf->main_vsi;
3026
3027         if (mask & ETH_VLAN_FILTER_MASK) {
3028                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3029                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3030                 else
3031                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3032         }
3033
3034         if (mask & ETH_VLAN_STRIP_MASK) {
3035                 /* Enable or disable VLAN stripping */
3036                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3037                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3038                 else
3039                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3040         }
3041
3042         if (mask & ETH_VLAN_EXTEND_MASK) {
3043                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3044                         i40e_vsi_config_double_vlan(vsi, TRUE);
3045                         /* Set global registers with default ether type value */
3046                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3047                                            ETHER_TYPE_VLAN);
3048                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3049                                            ETHER_TYPE_VLAN);
3050                 }
3051                 else
3052                         i40e_vsi_config_double_vlan(vsi, FALSE);
3053         }
3054 }
3055
3056 static void
3057 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3058                           __rte_unused uint16_t queue,
3059                           __rte_unused int on)
3060 {
3061         PMD_INIT_FUNC_TRACE();
3062 }
3063
3064 static int
3065 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3066 {
3067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3068         struct i40e_vsi *vsi = pf->main_vsi;
3069         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3070         struct i40e_vsi_vlan_pvid_info info;
3071
3072         memset(&info, 0, sizeof(info));
3073         info.on = on;
3074         if (info.on)
3075                 info.config.pvid = pvid;
3076         else {
3077                 info.config.reject.tagged =
3078                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3079                 info.config.reject.untagged =
3080                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3081         }
3082
3083         return i40e_vsi_vlan_pvid_set(vsi, &info);
3084 }
3085
3086 static int
3087 i40e_dev_led_on(struct rte_eth_dev *dev)
3088 {
3089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090         uint32_t mode = i40e_led_get(hw);
3091
3092         if (mode == 0)
3093                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3094
3095         return 0;
3096 }
3097
3098 static int
3099 i40e_dev_led_off(struct rte_eth_dev *dev)
3100 {
3101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3102         uint32_t mode = i40e_led_get(hw);
3103
3104         if (mode != 0)
3105                 i40e_led_set(hw, 0, false);
3106
3107         return 0;
3108 }
3109
3110 static int
3111 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3112 {
3113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3115
3116         fc_conf->pause_time = pf->fc_conf.pause_time;
3117         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3118         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3119
3120          /* Return current mode according to actual setting*/
3121         switch (hw->fc.current_mode) {
3122         case I40E_FC_FULL:
3123                 fc_conf->mode = RTE_FC_FULL;
3124                 break;
3125         case I40E_FC_TX_PAUSE:
3126                 fc_conf->mode = RTE_FC_TX_PAUSE;
3127                 break;
3128         case I40E_FC_RX_PAUSE:
3129                 fc_conf->mode = RTE_FC_RX_PAUSE;
3130                 break;
3131         case I40E_FC_NONE:
3132         default:
3133                 fc_conf->mode = RTE_FC_NONE;
3134         };
3135
3136         return 0;
3137 }
3138
3139 static int
3140 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3141 {
3142         uint32_t mflcn_reg, fctrl_reg, reg;
3143         uint32_t max_high_water;
3144         uint8_t i, aq_failure;
3145         int err;
3146         struct i40e_hw *hw;
3147         struct i40e_pf *pf;
3148         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3149                 [RTE_FC_NONE] = I40E_FC_NONE,
3150                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3151                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3152                 [RTE_FC_FULL] = I40E_FC_FULL
3153         };
3154
3155         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3156
3157         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3158         if ((fc_conf->high_water > max_high_water) ||
3159                         (fc_conf->high_water < fc_conf->low_water)) {
3160                 PMD_INIT_LOG(ERR,
3161                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3162                         max_high_water);
3163                 return -EINVAL;
3164         }
3165
3166         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3169
3170         pf->fc_conf.pause_time = fc_conf->pause_time;
3171         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3172         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3173
3174         PMD_INIT_FUNC_TRACE();
3175
3176         /* All the link flow control related enable/disable register
3177          * configuration is handle by the F/W
3178          */
3179         err = i40e_set_fc(hw, &aq_failure, true);
3180         if (err < 0)
3181                 return -ENOSYS;
3182
3183         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3184                 /* Configure flow control refresh threshold,
3185                  * the value for stat_tx_pause_refresh_timer[8]
3186                  * is used for global pause operation.
3187                  */
3188
3189                 I40E_WRITE_REG(hw,
3190                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3191                                pf->fc_conf.pause_time);
3192
3193                 /* configure the timer value included in transmitted pause
3194                  * frame,
3195                  * the value for stat_tx_pause_quanta[8] is used for global
3196                  * pause operation
3197                  */
3198                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3199                                pf->fc_conf.pause_time);
3200
3201                 fctrl_reg = I40E_READ_REG(hw,
3202                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3203
3204                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3205                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3206                 else
3207                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3208
3209                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3210                                fctrl_reg);
3211         } else {
3212                 /* Configure pause time (2 TCs per register) */
3213                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3214                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3215                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3216
3217                 /* Configure flow control refresh threshold value */
3218                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3219                                pf->fc_conf.pause_time / 2);
3220
3221                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3222
3223                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3224                  *depending on configuration
3225                  */
3226                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3227                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3228                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3229                 } else {
3230                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3231                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3232                 }
3233
3234                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3235         }
3236
3237         /* config the water marker both based on the packets and bytes */
3238         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3239                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3240                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3241         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3242                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3243                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3244         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3245                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3246                        << I40E_KILOSHIFT);
3247         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3248                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3249                        << I40E_KILOSHIFT);
3250
3251         I40E_WRITE_FLUSH(hw);
3252
3253         return 0;
3254 }
3255
3256 static int
3257 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3258                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3259 {
3260         PMD_INIT_FUNC_TRACE();
3261
3262         return -ENOSYS;
3263 }
3264
3265 /* Add a MAC address, and update filters */
3266 static void
3267 i40e_macaddr_add(struct rte_eth_dev *dev,
3268                  struct ether_addr *mac_addr,
3269                  __rte_unused uint32_t index,
3270                  uint32_t pool)
3271 {
3272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273         struct i40e_mac_filter_info mac_filter;
3274         struct i40e_vsi *vsi;
3275         int ret;
3276
3277         /* If VMDQ not enabled or configured, return */
3278         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3279                           !pf->nb_cfg_vmdq_vsi)) {
3280                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3281                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3282                         pool);
3283                 return;
3284         }
3285
3286         if (pool > pf->nb_cfg_vmdq_vsi) {
3287                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3288                                 pool, pf->nb_cfg_vmdq_vsi);
3289                 return;
3290         }
3291
3292         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3293         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3294                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3295         else
3296                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3297
3298         if (pool == 0)
3299                 vsi = pf->main_vsi;
3300         else
3301                 vsi = pf->vmdq[pool - 1].vsi;
3302
3303         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3304         if (ret != I40E_SUCCESS) {
3305                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3306                 return;
3307         }
3308 }
3309
3310 /* Remove a MAC address, and update filters */
3311 static void
3312 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3313 {
3314         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3315         struct i40e_vsi *vsi;
3316         struct rte_eth_dev_data *data = dev->data;
3317         struct ether_addr *macaddr;
3318         int ret;
3319         uint32_t i;
3320         uint64_t pool_sel;
3321
3322         macaddr = &(data->mac_addrs[index]);
3323
3324         pool_sel = dev->data->mac_pool_sel[index];
3325
3326         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3327                 if (pool_sel & (1ULL << i)) {
3328                         if (i == 0)
3329                                 vsi = pf->main_vsi;
3330                         else {
3331                                 /* No VMDQ pool enabled or configured */
3332                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3333                                         (i > pf->nb_cfg_vmdq_vsi)) {
3334                                         PMD_DRV_LOG(ERR,
3335                                                 "No VMDQ pool enabled/configured");
3336                                         return;
3337                                 }
3338                                 vsi = pf->vmdq[i - 1].vsi;
3339                         }
3340                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3341
3342                         if (ret) {
3343                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3344                                 return;
3345                         }
3346                 }
3347         }
3348 }
3349
3350 /* Set perfect match or hash match of MAC and VLAN for a VF */
3351 static int
3352 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3353                  struct rte_eth_mac_filter *filter,
3354                  bool add)
3355 {
3356         struct i40e_hw *hw;
3357         struct i40e_mac_filter_info mac_filter;
3358         struct ether_addr old_mac;
3359         struct ether_addr *new_mac;
3360         struct i40e_pf_vf *vf = NULL;
3361         uint16_t vf_id;
3362         int ret;
3363
3364         if (pf == NULL) {
3365                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3366                 return -EINVAL;
3367         }
3368         hw = I40E_PF_TO_HW(pf);
3369
3370         if (filter == NULL) {
3371                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3372                 return -EINVAL;
3373         }
3374
3375         new_mac = &filter->mac_addr;
3376
3377         if (is_zero_ether_addr(new_mac)) {
3378                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3379                 return -EINVAL;
3380         }
3381
3382         vf_id = filter->dst_id;
3383
3384         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3385                 PMD_DRV_LOG(ERR, "Invalid argument.");
3386                 return -EINVAL;
3387         }
3388         vf = &pf->vfs[vf_id];
3389
3390         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3391                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3392                 return -EINVAL;
3393         }
3394
3395         if (add) {
3396                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3397                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3398                                 ETHER_ADDR_LEN);
3399                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3400                                  ETHER_ADDR_LEN);
3401
3402                 mac_filter.filter_type = filter->filter_type;
3403                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3404                 if (ret != I40E_SUCCESS) {
3405                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3406                         return -1;
3407                 }
3408                 ether_addr_copy(new_mac, &pf->dev_addr);
3409         } else {
3410                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3411                                 ETHER_ADDR_LEN);
3412                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3413                 if (ret != I40E_SUCCESS) {
3414                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3415                         return -1;
3416                 }
3417
3418                 /* Clear device address as it has been removed */
3419                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3420                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3421         }
3422
3423         return 0;
3424 }
3425
3426 /* MAC filter handle */
3427 static int
3428 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3429                 void *arg)
3430 {
3431         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3432         struct rte_eth_mac_filter *filter;
3433         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3434         int ret = I40E_NOT_SUPPORTED;
3435
3436         filter = (struct rte_eth_mac_filter *)(arg);
3437
3438         switch (filter_op) {
3439         case RTE_ETH_FILTER_NOP:
3440                 ret = I40E_SUCCESS;
3441                 break;
3442         case RTE_ETH_FILTER_ADD:
3443                 i40e_pf_disable_irq0(hw);
3444                 if (filter->is_vf)
3445                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3446                 i40e_pf_enable_irq0(hw);
3447                 break;
3448         case RTE_ETH_FILTER_DELETE:
3449                 i40e_pf_disable_irq0(hw);
3450                 if (filter->is_vf)
3451                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3452                 i40e_pf_enable_irq0(hw);
3453                 break;
3454         default:
3455                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3456                 ret = I40E_ERR_PARAM;
3457                 break;
3458         }
3459
3460         return ret;
3461 }
3462
3463 static int
3464 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3465 {
3466         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3467         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3468         int ret;
3469
3470         if (!lut)
3471                 return -EINVAL;
3472
3473         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3474                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3475                                           lut, lut_size);
3476                 if (ret) {
3477                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3478                         return ret;
3479                 }
3480         } else {
3481                 uint32_t *lut_dw = (uint32_t *)lut;
3482                 uint16_t i, lut_size_dw = lut_size / 4;
3483
3484                 for (i = 0; i < lut_size_dw; i++)
3485                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3486         }
3487
3488         return 0;
3489 }
3490
3491 static int
3492 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3493 {
3494         struct i40e_pf *pf;
3495         struct i40e_hw *hw;
3496         int ret;
3497
3498         if (!vsi || !lut)
3499                 return -EINVAL;
3500
3501         pf = I40E_VSI_TO_PF(vsi);
3502         hw = I40E_VSI_TO_HW(vsi);
3503
3504         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3505                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3506                                           lut, lut_size);
3507                 if (ret) {
3508                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3509                         return ret;
3510                 }
3511         } else {
3512                 uint32_t *lut_dw = (uint32_t *)lut;
3513                 uint16_t i, lut_size_dw = lut_size / 4;
3514
3515                 for (i = 0; i < lut_size_dw; i++)
3516                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3517                 I40E_WRITE_FLUSH(hw);
3518         }
3519
3520         return 0;
3521 }
3522
3523 static int
3524 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3525                          struct rte_eth_rss_reta_entry64 *reta_conf,
3526                          uint16_t reta_size)
3527 {
3528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3529         uint16_t i, lut_size = pf->hash_lut_size;
3530         uint16_t idx, shift;
3531         uint8_t *lut;
3532         int ret;
3533
3534         if (reta_size != lut_size ||
3535                 reta_size > ETH_RSS_RETA_SIZE_512) {
3536                 PMD_DRV_LOG(ERR,
3537                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3538                         reta_size, lut_size);
3539                 return -EINVAL;
3540         }
3541
3542         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3543         if (!lut) {
3544                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3545                 return -ENOMEM;
3546         }
3547         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3548         if (ret)
3549                 goto out;
3550         for (i = 0; i < reta_size; i++) {
3551                 idx = i / RTE_RETA_GROUP_SIZE;
3552                 shift = i % RTE_RETA_GROUP_SIZE;
3553                 if (reta_conf[idx].mask & (1ULL << shift))
3554                         lut[i] = reta_conf[idx].reta[shift];
3555         }
3556         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3557
3558 out:
3559         rte_free(lut);
3560
3561         return ret;
3562 }
3563
3564 static int
3565 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3566                         struct rte_eth_rss_reta_entry64 *reta_conf,
3567                         uint16_t reta_size)
3568 {
3569         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3570         uint16_t i, lut_size = pf->hash_lut_size;
3571         uint16_t idx, shift;
3572         uint8_t *lut;
3573         int ret;
3574
3575         if (reta_size != lut_size ||
3576                 reta_size > ETH_RSS_RETA_SIZE_512) {
3577                 PMD_DRV_LOG(ERR,
3578                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3579                         reta_size, lut_size);
3580                 return -EINVAL;
3581         }
3582
3583         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3584         if (!lut) {
3585                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3586                 return -ENOMEM;
3587         }
3588
3589         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3590         if (ret)
3591                 goto out;
3592         for (i = 0; i < reta_size; i++) {
3593                 idx = i / RTE_RETA_GROUP_SIZE;
3594                 shift = i % RTE_RETA_GROUP_SIZE;
3595                 if (reta_conf[idx].mask & (1ULL << shift))
3596                         reta_conf[idx].reta[shift] = lut[i];
3597         }
3598
3599 out:
3600         rte_free(lut);
3601
3602         return ret;
3603 }
3604
3605 /**
3606  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3607  * @hw:   pointer to the HW structure
3608  * @mem:  pointer to mem struct to fill out
3609  * @size: size of memory requested
3610  * @alignment: what to align the allocation to
3611  **/
3612 enum i40e_status_code
3613 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3614                         struct i40e_dma_mem *mem,
3615                         u64 size,
3616                         u32 alignment)
3617 {
3618         const struct rte_memzone *mz = NULL;
3619         char z_name[RTE_MEMZONE_NAMESIZE];
3620
3621         if (!mem)
3622                 return I40E_ERR_PARAM;
3623
3624         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3625         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3626                                          alignment, RTE_PGSIZE_2M);
3627         if (!mz)
3628                 return I40E_ERR_NO_MEMORY;
3629
3630         mem->size = size;
3631         mem->va = mz->addr;
3632         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3633         mem->zone = (const void *)mz;
3634         PMD_DRV_LOG(DEBUG,
3635                 "memzone %s allocated with physical address: %"PRIu64,
3636                 mz->name, mem->pa);
3637
3638         return I40E_SUCCESS;
3639 }
3640
3641 /**
3642  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3643  * @hw:   pointer to the HW structure
3644  * @mem:  ptr to mem struct to free
3645  **/
3646 enum i40e_status_code
3647 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3648                     struct i40e_dma_mem *mem)
3649 {
3650         if (!mem)
3651                 return I40E_ERR_PARAM;
3652
3653         PMD_DRV_LOG(DEBUG,
3654                 "memzone %s to be freed with physical address: %"PRIu64,
3655                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3656         rte_memzone_free((const struct rte_memzone *)mem->zone);
3657         mem->zone = NULL;
3658         mem->va = NULL;
3659         mem->pa = (u64)0;
3660
3661         return I40E_SUCCESS;
3662 }
3663
3664 /**
3665  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3666  * @hw:   pointer to the HW structure
3667  * @mem:  pointer to mem struct to fill out
3668  * @size: size of memory requested
3669  **/
3670 enum i40e_status_code
3671 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3672                          struct i40e_virt_mem *mem,
3673                          u32 size)
3674 {
3675         if (!mem)
3676                 return I40E_ERR_PARAM;
3677
3678         mem->size = size;
3679         mem->va = rte_zmalloc("i40e", size, 0);
3680
3681         if (mem->va)
3682                 return I40E_SUCCESS;
3683         else
3684                 return I40E_ERR_NO_MEMORY;
3685 }
3686
3687 /**
3688  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3689  * @hw:   pointer to the HW structure
3690  * @mem:  pointer to mem struct to free
3691  **/
3692 enum i40e_status_code
3693 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3694                      struct i40e_virt_mem *mem)
3695 {
3696         if (!mem)
3697                 return I40E_ERR_PARAM;
3698
3699         rte_free(mem->va);
3700         mem->va = NULL;
3701
3702         return I40E_SUCCESS;
3703 }
3704
3705 void
3706 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3707 {
3708         rte_spinlock_init(&sp->spinlock);
3709 }
3710
3711 void
3712 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3713 {
3714         rte_spinlock_lock(&sp->spinlock);
3715 }
3716
3717 void
3718 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3719 {
3720         rte_spinlock_unlock(&sp->spinlock);
3721 }
3722
3723 void
3724 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3725 {
3726         return;
3727 }
3728
3729 /**
3730  * Get the hardware capabilities, which will be parsed
3731  * and saved into struct i40e_hw.
3732  */
3733 static int
3734 i40e_get_cap(struct i40e_hw *hw)
3735 {
3736         struct i40e_aqc_list_capabilities_element_resp *buf;
3737         uint16_t len, size = 0;
3738         int ret;
3739
3740         /* Calculate a huge enough buff for saving response data temporarily */
3741         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3742                                                 I40E_MAX_CAP_ELE_NUM;
3743         buf = rte_zmalloc("i40e", len, 0);
3744         if (!buf) {
3745                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3746                 return I40E_ERR_NO_MEMORY;
3747         }
3748
3749         /* Get, parse the capabilities and save it to hw */
3750         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3751                         i40e_aqc_opc_list_func_capabilities, NULL);
3752         if (ret != I40E_SUCCESS)
3753                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3754
3755         /* Free the temporary buffer after being used */
3756         rte_free(buf);
3757
3758         return ret;
3759 }
3760
3761 static int
3762 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3763 {
3764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3766         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3767         uint16_t qp_count = 0, vsi_count = 0;
3768
3769         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3770                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3771                 return -EINVAL;
3772         }
3773         /* Add the parameter init for LFC */
3774         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3775         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3776         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3777
3778         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3779         pf->max_num_vsi = hw->func_caps.num_vsis;
3780         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3781         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3782         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3783
3784         /* FDir queue/VSI allocation */
3785         pf->fdir_qp_offset = 0;
3786         if (hw->func_caps.fd) {
3787                 pf->flags |= I40E_FLAG_FDIR;
3788                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3789         } else {
3790                 pf->fdir_nb_qps = 0;
3791         }
3792         qp_count += pf->fdir_nb_qps;
3793         vsi_count += 1;
3794
3795         /* LAN queue/VSI allocation */
3796         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3797         if (!hw->func_caps.rss) {
3798                 pf->lan_nb_qps = 1;
3799         } else {
3800                 pf->flags |= I40E_FLAG_RSS;
3801                 if (hw->mac.type == I40E_MAC_X722)
3802                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3803                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3804         }
3805         qp_count += pf->lan_nb_qps;
3806         vsi_count += 1;
3807
3808         /* VF queue/VSI allocation */
3809         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3810         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3811                 pf->flags |= I40E_FLAG_SRIOV;
3812                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3813                 pf->vf_num = pci_dev->max_vfs;
3814                 PMD_DRV_LOG(DEBUG,
3815                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3816                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3817         } else {
3818                 pf->vf_nb_qps = 0;
3819                 pf->vf_num = 0;
3820         }
3821         qp_count += pf->vf_nb_qps * pf->vf_num;
3822         vsi_count += pf->vf_num;
3823
3824         /* VMDq queue/VSI allocation */
3825         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3826         pf->vmdq_nb_qps = 0;
3827         pf->max_nb_vmdq_vsi = 0;
3828         if (hw->func_caps.vmdq) {
3829                 if (qp_count < hw->func_caps.num_tx_qp &&
3830                         vsi_count < hw->func_caps.num_vsis) {
3831                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3832                                 qp_count) / pf->vmdq_nb_qp_max;
3833
3834                         /* Limit the maximum number of VMDq vsi to the maximum
3835                          * ethdev can support
3836                          */
3837                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3838                                 hw->func_caps.num_vsis - vsi_count);
3839                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3840                                 ETH_64_POOLS);
3841                         if (pf->max_nb_vmdq_vsi) {
3842                                 pf->flags |= I40E_FLAG_VMDQ;
3843                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3844                                 PMD_DRV_LOG(DEBUG,
3845                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3846                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3847                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3848                         } else {
3849                                 PMD_DRV_LOG(INFO,
3850                                         "No enough queues left for VMDq");
3851                         }
3852                 } else {
3853                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3854                 }
3855         }
3856         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3857         vsi_count += pf->max_nb_vmdq_vsi;
3858
3859         if (hw->func_caps.dcb)
3860                 pf->flags |= I40E_FLAG_DCB;
3861
3862         if (qp_count > hw->func_caps.num_tx_qp) {
3863                 PMD_DRV_LOG(ERR,
3864                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3865                         qp_count, hw->func_caps.num_tx_qp);
3866                 return -EINVAL;
3867         }
3868         if (vsi_count > hw->func_caps.num_vsis) {
3869                 PMD_DRV_LOG(ERR,
3870                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3871                         vsi_count, hw->func_caps.num_vsis);
3872                 return -EINVAL;
3873         }
3874
3875         return 0;
3876 }
3877
3878 static int
3879 i40e_pf_get_switch_config(struct i40e_pf *pf)
3880 {
3881         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3882         struct i40e_aqc_get_switch_config_resp *switch_config;
3883         struct i40e_aqc_switch_config_element_resp *element;
3884         uint16_t start_seid = 0, num_reported;
3885         int ret;
3886
3887         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3888                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3889         if (!switch_config) {
3890                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3891                 return -ENOMEM;
3892         }
3893
3894         /* Get the switch configurations */
3895         ret = i40e_aq_get_switch_config(hw, switch_config,
3896                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3897         if (ret != I40E_SUCCESS) {
3898                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3899                 goto fail;
3900         }
3901         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3902         if (num_reported != 1) { /* The number should be 1 */
3903                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3904                 goto fail;
3905         }
3906
3907         /* Parse the switch configuration elements */
3908         element = &(switch_config->element[0]);
3909         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3910                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3911                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3912         } else
3913                 PMD_DRV_LOG(INFO, "Unknown element type");
3914
3915 fail:
3916         rte_free(switch_config);
3917
3918         return ret;
3919 }
3920
3921 static int
3922 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3923                         uint32_t num)
3924 {
3925         struct pool_entry *entry;
3926
3927         if (pool == NULL || num == 0)
3928                 return -EINVAL;
3929
3930         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3931         if (entry == NULL) {
3932                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3933                 return -ENOMEM;
3934         }
3935
3936         /* queue heap initialize */
3937         pool->num_free = num;
3938         pool->num_alloc = 0;
3939         pool->base = base;
3940         LIST_INIT(&pool->alloc_list);
3941         LIST_INIT(&pool->free_list);
3942
3943         /* Initialize element  */
3944         entry->base = 0;
3945         entry->len = num;
3946
3947         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3948         return 0;
3949 }
3950
3951 static void
3952 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3953 {
3954         struct pool_entry *entry, *next_entry;
3955
3956         if (pool == NULL)
3957                 return;
3958
3959         for (entry = LIST_FIRST(&pool->alloc_list);
3960                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3961                         entry = next_entry) {
3962                 LIST_REMOVE(entry, next);
3963                 rte_free(entry);
3964         }
3965
3966         for (entry = LIST_FIRST(&pool->free_list);
3967                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3968                         entry = next_entry) {
3969                 LIST_REMOVE(entry, next);
3970                 rte_free(entry);
3971         }
3972
3973         pool->num_free = 0;
3974         pool->num_alloc = 0;
3975         pool->base = 0;
3976         LIST_INIT(&pool->alloc_list);
3977         LIST_INIT(&pool->free_list);
3978 }
3979
3980 static int
3981 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3982                        uint32_t base)
3983 {
3984         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3985         uint32_t pool_offset;
3986         int insert;
3987
3988         if (pool == NULL) {
3989                 PMD_DRV_LOG(ERR, "Invalid parameter");
3990                 return -EINVAL;
3991         }
3992
3993         pool_offset = base - pool->base;
3994         /* Lookup in alloc list */
3995         LIST_FOREACH(entry, &pool->alloc_list, next) {
3996                 if (entry->base == pool_offset) {
3997                         valid_entry = entry;
3998                         LIST_REMOVE(entry, next);
3999                         break;
4000                 }
4001         }
4002
4003         /* Not find, return */
4004         if (valid_entry == NULL) {
4005                 PMD_DRV_LOG(ERR, "Failed to find entry");
4006                 return -EINVAL;
4007         }
4008
4009         /**
4010          * Found it, move it to free list  and try to merge.
4011          * In order to make merge easier, always sort it by qbase.
4012          * Find adjacent prev and last entries.
4013          */
4014         prev = next = NULL;
4015         LIST_FOREACH(entry, &pool->free_list, next) {
4016                 if (entry->base > valid_entry->base) {
4017                         next = entry;
4018                         break;
4019                 }
4020                 prev = entry;
4021         }
4022
4023         insert = 0;
4024         /* Try to merge with next one*/
4025         if (next != NULL) {
4026                 /* Merge with next one */
4027                 if (valid_entry->base + valid_entry->len == next->base) {
4028                         next->base = valid_entry->base;
4029                         next->len += valid_entry->len;
4030                         rte_free(valid_entry);
4031                         valid_entry = next;
4032                         insert = 1;
4033                 }
4034         }
4035
4036         if (prev != NULL) {
4037                 /* Merge with previous one */
4038                 if (prev->base + prev->len == valid_entry->base) {
4039                         prev->len += valid_entry->len;
4040                         /* If it merge with next one, remove next node */
4041                         if (insert == 1) {
4042                                 LIST_REMOVE(valid_entry, next);
4043                                 rte_free(valid_entry);
4044                         } else {
4045                                 rte_free(valid_entry);
4046                                 insert = 1;
4047                         }
4048                 }
4049         }
4050
4051         /* Not find any entry to merge, insert */
4052         if (insert == 0) {
4053                 if (prev != NULL)
4054                         LIST_INSERT_AFTER(prev, valid_entry, next);
4055                 else if (next != NULL)
4056                         LIST_INSERT_BEFORE(next, valid_entry, next);
4057                 else /* It's empty list, insert to head */
4058                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4059         }
4060
4061         pool->num_free += valid_entry->len;
4062         pool->num_alloc -= valid_entry->len;
4063
4064         return 0;
4065 }
4066
4067 static int
4068 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4069                        uint16_t num)
4070 {
4071         struct pool_entry *entry, *valid_entry;
4072
4073         if (pool == NULL || num == 0) {
4074                 PMD_DRV_LOG(ERR, "Invalid parameter");
4075                 return -EINVAL;
4076         }
4077
4078         if (pool->num_free < num) {
4079                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4080                             num, pool->num_free);
4081                 return -ENOMEM;
4082         }
4083
4084         valid_entry = NULL;
4085         /* Lookup  in free list and find most fit one */
4086         LIST_FOREACH(entry, &pool->free_list, next) {
4087                 if (entry->len >= num) {
4088                         /* Find best one */
4089                         if (entry->len == num) {
4090                                 valid_entry = entry;
4091                                 break;
4092                         }
4093                         if (valid_entry == NULL || valid_entry->len > entry->len)
4094                                 valid_entry = entry;
4095                 }
4096         }
4097
4098         /* Not find one to satisfy the request, return */
4099         if (valid_entry == NULL) {
4100                 PMD_DRV_LOG(ERR, "No valid entry found");
4101                 return -ENOMEM;
4102         }
4103         /**
4104          * The entry have equal queue number as requested,
4105          * remove it from alloc_list.
4106          */
4107         if (valid_entry->len == num) {
4108                 LIST_REMOVE(valid_entry, next);
4109         } else {
4110                 /**
4111                  * The entry have more numbers than requested,
4112                  * create a new entry for alloc_list and minus its
4113                  * queue base and number in free_list.
4114                  */
4115                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4116                 if (entry == NULL) {
4117                         PMD_DRV_LOG(ERR,
4118                                 "Failed to allocate memory for resource pool");
4119                         return -ENOMEM;
4120                 }
4121                 entry->base = valid_entry->base;
4122                 entry->len = num;
4123                 valid_entry->base += num;
4124                 valid_entry->len -= num;
4125                 valid_entry = entry;
4126         }
4127
4128         /* Insert it into alloc list, not sorted */
4129         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4130
4131         pool->num_free -= valid_entry->len;
4132         pool->num_alloc += valid_entry->len;
4133
4134         return valid_entry->base + pool->base;
4135 }
4136
4137 /**
4138  * bitmap_is_subset - Check whether src2 is subset of src1
4139  **/
4140 static inline int
4141 bitmap_is_subset(uint8_t src1, uint8_t src2)
4142 {
4143         return !((src1 ^ src2) & src2);
4144 }
4145
4146 static enum i40e_status_code
4147 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4148 {
4149         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4150
4151         /* If DCB is not supported, only default TC is supported */
4152         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4153                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4154                 return I40E_NOT_SUPPORTED;
4155         }
4156
4157         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4158                 PMD_DRV_LOG(ERR,
4159                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4160                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4161                 return I40E_NOT_SUPPORTED;
4162         }
4163         return I40E_SUCCESS;
4164 }
4165
4166 int
4167 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4168                                 struct i40e_vsi_vlan_pvid_info *info)
4169 {
4170         struct i40e_hw *hw;
4171         struct i40e_vsi_context ctxt;
4172         uint8_t vlan_flags = 0;
4173         int ret;
4174
4175         if (vsi == NULL || info == NULL) {
4176                 PMD_DRV_LOG(ERR, "invalid parameters");
4177                 return I40E_ERR_PARAM;
4178         }
4179
4180         if (info->on) {
4181                 vsi->info.pvid = info->config.pvid;
4182                 /**
4183                  * If insert pvid is enabled, only tagged pkts are
4184                  * allowed to be sent out.
4185                  */
4186                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4187                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4188         } else {
4189                 vsi->info.pvid = 0;
4190                 if (info->config.reject.tagged == 0)
4191                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4192
4193                 if (info->config.reject.untagged == 0)
4194                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4195         }
4196         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4197                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4198         vsi->info.port_vlan_flags |= vlan_flags;
4199         vsi->info.valid_sections =
4200                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4201         memset(&ctxt, 0, sizeof(ctxt));
4202         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4203         ctxt.seid = vsi->seid;
4204
4205         hw = I40E_VSI_TO_HW(vsi);
4206         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4207         if (ret != I40E_SUCCESS)
4208                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4209
4210         return ret;
4211 }
4212
4213 static int
4214 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4215 {
4216         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4217         int i, ret;
4218         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4219
4220         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4221         if (ret != I40E_SUCCESS)
4222                 return ret;
4223
4224         if (!vsi->seid) {
4225                 PMD_DRV_LOG(ERR, "seid not valid");
4226                 return -EINVAL;
4227         }
4228
4229         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4230         tc_bw_data.tc_valid_bits = enabled_tcmap;
4231         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4232                 tc_bw_data.tc_bw_credits[i] =
4233                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4234
4235         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4236         if (ret != I40E_SUCCESS) {
4237                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4238                 return ret;
4239         }
4240
4241         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4242                                         sizeof(vsi->info.qs_handle));
4243         return I40E_SUCCESS;
4244 }
4245
4246 static enum i40e_status_code
4247 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4248                                  struct i40e_aqc_vsi_properties_data *info,
4249                                  uint8_t enabled_tcmap)
4250 {
4251         enum i40e_status_code ret;
4252         int i, total_tc = 0;
4253         uint16_t qpnum_per_tc, bsf, qp_idx;
4254
4255         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4256         if (ret != I40E_SUCCESS)
4257                 return ret;
4258
4259         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4260                 if (enabled_tcmap & (1 << i))
4261                         total_tc++;
4262         vsi->enabled_tc = enabled_tcmap;
4263
4264         /* Number of queues per enabled TC */
4265         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4266         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4267         bsf = rte_bsf32(qpnum_per_tc);
4268
4269         /* Adjust the queue number to actual queues that can be applied */
4270         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4271                 vsi->nb_qps = qpnum_per_tc * total_tc;
4272
4273         /**
4274          * Configure TC and queue mapping parameters, for enabled TC,
4275          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4276          * default queue will serve it.
4277          */
4278         qp_idx = 0;
4279         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4280                 if (vsi->enabled_tc & (1 << i)) {
4281                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4282                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4283                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4284                         qp_idx += qpnum_per_tc;
4285                 } else
4286                         info->tc_mapping[i] = 0;
4287         }
4288
4289         /* Associate queue number with VSI */
4290         if (vsi->type == I40E_VSI_SRIOV) {
4291                 info->mapping_flags |=
4292                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4293                 for (i = 0; i < vsi->nb_qps; i++)
4294                         info->queue_mapping[i] =
4295                                 rte_cpu_to_le_16(vsi->base_queue + i);
4296         } else {
4297                 info->mapping_flags |=
4298                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4299                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4300         }
4301         info->valid_sections |=
4302                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4303
4304         return I40E_SUCCESS;
4305 }
4306
4307 static int
4308 i40e_veb_release(struct i40e_veb *veb)
4309 {
4310         struct i40e_vsi *vsi;
4311         struct i40e_hw *hw;
4312
4313         if (veb == NULL)
4314                 return -EINVAL;
4315
4316         if (!TAILQ_EMPTY(&veb->head)) {
4317                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4318                 return -EACCES;
4319         }
4320         /* associate_vsi field is NULL for floating VEB */
4321         if (veb->associate_vsi != NULL) {
4322                 vsi = veb->associate_vsi;
4323                 hw = I40E_VSI_TO_HW(vsi);
4324
4325                 vsi->uplink_seid = veb->uplink_seid;
4326                 vsi->veb = NULL;
4327         } else {
4328                 veb->associate_pf->main_vsi->floating_veb = NULL;
4329                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4330         }
4331
4332         i40e_aq_delete_element(hw, veb->seid, NULL);
4333         rte_free(veb);
4334         return I40E_SUCCESS;
4335 }
4336
4337 /* Setup a veb */
4338 static struct i40e_veb *
4339 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4340 {
4341         struct i40e_veb *veb;
4342         int ret;
4343         struct i40e_hw *hw;
4344
4345         if (pf == NULL) {
4346                 PMD_DRV_LOG(ERR,
4347                             "veb setup failed, associated PF shouldn't null");
4348                 return NULL;
4349         }
4350         hw = I40E_PF_TO_HW(pf);
4351
4352         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4353         if (!veb) {
4354                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4355                 goto fail;
4356         }
4357
4358         veb->associate_vsi = vsi;
4359         veb->associate_pf = pf;
4360         TAILQ_INIT(&veb->head);
4361         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4362
4363         /* create floating veb if vsi is NULL */
4364         if (vsi != NULL) {
4365                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4366                                       I40E_DEFAULT_TCMAP, false,
4367                                       &veb->seid, false, NULL);
4368         } else {
4369                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4370                                       true, &veb->seid, false, NULL);
4371         }
4372
4373         if (ret != I40E_SUCCESS) {
4374                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4375                             hw->aq.asq_last_status);
4376                 goto fail;
4377         }
4378         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4379
4380         /* get statistics index */
4381         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4382                                 &veb->stats_idx, NULL, NULL, NULL);
4383         if (ret != I40E_SUCCESS) {
4384                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4385                             hw->aq.asq_last_status);
4386                 goto fail;
4387         }
4388         /* Get VEB bandwidth, to be implemented */
4389         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4390         if (vsi)
4391                 vsi->uplink_seid = veb->seid;
4392
4393         return veb;
4394 fail:
4395         rte_free(veb);
4396         return NULL;
4397 }
4398
4399 int
4400 i40e_vsi_release(struct i40e_vsi *vsi)
4401 {
4402         struct i40e_pf *pf;
4403         struct i40e_hw *hw;
4404         struct i40e_vsi_list *vsi_list;
4405         void *temp;
4406         int ret;
4407         struct i40e_mac_filter *f;
4408         uint16_t user_param;
4409
4410         if (!vsi)
4411                 return I40E_SUCCESS;
4412
4413         if (!vsi->adapter)
4414                 return -EFAULT;
4415
4416         user_param = vsi->user_param;
4417
4418         pf = I40E_VSI_TO_PF(vsi);
4419         hw = I40E_VSI_TO_HW(vsi);
4420
4421         /* VSI has child to attach, release child first */
4422         if (vsi->veb) {
4423                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4424                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4425                                 return -1;
4426                 }
4427                 i40e_veb_release(vsi->veb);
4428         }
4429
4430         if (vsi->floating_veb) {
4431                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4432                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4433                                 return -1;
4434                 }
4435         }
4436
4437         /* Remove all macvlan filters of the VSI */
4438         i40e_vsi_remove_all_macvlan_filter(vsi);
4439         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4440                 rte_free(f);
4441
4442         if (vsi->type != I40E_VSI_MAIN &&
4443             ((vsi->type != I40E_VSI_SRIOV) ||
4444             !pf->floating_veb_list[user_param])) {
4445                 /* Remove vsi from parent's sibling list */
4446                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4447                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4448                         return I40E_ERR_PARAM;
4449                 }
4450                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4451                                 &vsi->sib_vsi_list, list);
4452
4453                 /* Remove all switch element of the VSI */
4454                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4455                 if (ret != I40E_SUCCESS)
4456                         PMD_DRV_LOG(ERR, "Failed to delete element");
4457         }
4458
4459         if ((vsi->type == I40E_VSI_SRIOV) &&
4460             pf->floating_veb_list[user_param]) {
4461                 /* Remove vsi from parent's sibling list */
4462                 if (vsi->parent_vsi == NULL ||
4463                     vsi->parent_vsi->floating_veb == NULL) {
4464                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4465                         return I40E_ERR_PARAM;
4466                 }
4467                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4468                              &vsi->sib_vsi_list, list);
4469
4470                 /* Remove all switch element of the VSI */
4471                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4472                 if (ret != I40E_SUCCESS)
4473                         PMD_DRV_LOG(ERR, "Failed to delete element");
4474         }
4475
4476         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4477
4478         if (vsi->type != I40E_VSI_SRIOV)
4479                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4480         rte_free(vsi);
4481
4482         return I40E_SUCCESS;
4483 }
4484
4485 static int
4486 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4487 {
4488         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4489         struct i40e_aqc_remove_macvlan_element_data def_filter;
4490         struct i40e_mac_filter_info filter;
4491         int ret;
4492
4493         if (vsi->type != I40E_VSI_MAIN)
4494                 return I40E_ERR_CONFIG;
4495         memset(&def_filter, 0, sizeof(def_filter));
4496         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4497                                         ETH_ADDR_LEN);
4498         def_filter.vlan_tag = 0;
4499         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4500                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4501         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4502         if (ret != I40E_SUCCESS) {
4503                 struct i40e_mac_filter *f;
4504                 struct ether_addr *mac;
4505
4506                 PMD_DRV_LOG(WARNING,
4507                         "Cannot remove the default macvlan filter");
4508                 /* It needs to add the permanent mac into mac list */
4509                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4510                 if (f == NULL) {
4511                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4512                         return I40E_ERR_NO_MEMORY;
4513                 }
4514                 mac = &f->mac_info.mac_addr;
4515                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4516                                 ETH_ADDR_LEN);
4517                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4518                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4519                 vsi->mac_num++;
4520
4521                 return ret;
4522         }
4523         (void)rte_memcpy(&filter.mac_addr,
4524                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4525         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4526         return i40e_vsi_add_mac(vsi, &filter);
4527 }
4528
4529 /*
4530  * i40e_vsi_get_bw_config - Query VSI BW Information
4531  * @vsi: the VSI to be queried
4532  *
4533  * Returns 0 on success, negative value on failure
4534  */
4535 static enum i40e_status_code
4536 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4537 {
4538         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4539         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4540         struct i40e_hw *hw = &vsi->adapter->hw;
4541         i40e_status ret;
4542         int i;
4543         uint32_t bw_max;
4544
4545         memset(&bw_config, 0, sizeof(bw_config));
4546         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4547         if (ret != I40E_SUCCESS) {
4548                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4549                             hw->aq.asq_last_status);
4550                 return ret;
4551         }
4552
4553         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4554         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4555                                         &ets_sla_config, NULL);
4556         if (ret != I40E_SUCCESS) {
4557                 PMD_DRV_LOG(ERR,
4558                         "VSI failed to get TC bandwdith configuration %u",
4559                         hw->aq.asq_last_status);
4560                 return ret;
4561         }
4562
4563         /* store and print out BW info */
4564         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4565         vsi->bw_info.bw_max = bw_config.max_bw;
4566         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4567         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4568         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4569                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4570                      I40E_16_BIT_WIDTH);
4571         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4572                 vsi->bw_info.bw_ets_share_credits[i] =
4573                                 ets_sla_config.share_credits[i];
4574                 vsi->bw_info.bw_ets_credits[i] =
4575                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4576                 /* 4 bits per TC, 4th bit is reserved */
4577                 vsi->bw_info.bw_ets_max[i] =
4578                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4579                                   RTE_LEN2MASK(3, uint8_t));
4580                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4581                             vsi->bw_info.bw_ets_share_credits[i]);
4582                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4583                             vsi->bw_info.bw_ets_credits[i]);
4584                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4585                             vsi->bw_info.bw_ets_max[i]);
4586         }
4587
4588         return I40E_SUCCESS;
4589 }
4590
4591 /* i40e_enable_pf_lb
4592  * @pf: pointer to the pf structure
4593  *
4594  * allow loopback on pf
4595  */
4596 static inline void
4597 i40e_enable_pf_lb(struct i40e_pf *pf)
4598 {
4599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4600         struct i40e_vsi_context ctxt;
4601         int ret;
4602
4603         /* Use the FW API if FW >= v5.0 */
4604         if (hw->aq.fw_maj_ver < 5) {
4605                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4606                 return;
4607         }
4608
4609         memset(&ctxt, 0, sizeof(ctxt));
4610         ctxt.seid = pf->main_vsi_seid;
4611         ctxt.pf_num = hw->pf_id;
4612         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4613         if (ret) {
4614                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4615                             ret, hw->aq.asq_last_status);
4616                 return;
4617         }
4618         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4619         ctxt.info.valid_sections =
4620                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4621         ctxt.info.switch_id |=
4622                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4623
4624         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4625         if (ret)
4626                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4627                             hw->aq.asq_last_status);
4628 }
4629
4630 /* Setup a VSI */
4631 struct i40e_vsi *
4632 i40e_vsi_setup(struct i40e_pf *pf,
4633                enum i40e_vsi_type type,
4634                struct i40e_vsi *uplink_vsi,
4635                uint16_t user_param)
4636 {
4637         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4638         struct i40e_vsi *vsi;
4639         struct i40e_mac_filter_info filter;
4640         int ret;
4641         struct i40e_vsi_context ctxt;
4642         struct ether_addr broadcast =
4643                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4644
4645         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4646             uplink_vsi == NULL) {
4647                 PMD_DRV_LOG(ERR,
4648                         "VSI setup failed, VSI link shouldn't be NULL");
4649                 return NULL;
4650         }
4651
4652         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4653                 PMD_DRV_LOG(ERR,
4654                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4655                 return NULL;
4656         }
4657
4658         /* two situations
4659          * 1.type is not MAIN and uplink vsi is not NULL
4660          * If uplink vsi didn't setup VEB, create one first under veb field
4661          * 2.type is SRIOV and the uplink is NULL
4662          * If floating VEB is NULL, create one veb under floating veb field
4663          */
4664
4665         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4666             uplink_vsi->veb == NULL) {
4667                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4668
4669                 if (uplink_vsi->veb == NULL) {
4670                         PMD_DRV_LOG(ERR, "VEB setup failed");
4671                         return NULL;
4672                 }
4673                 /* set ALLOWLOOPBACk on pf, when veb is created */
4674                 i40e_enable_pf_lb(pf);
4675         }
4676
4677         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4678             pf->main_vsi->floating_veb == NULL) {
4679                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4680
4681                 if (pf->main_vsi->floating_veb == NULL) {
4682                         PMD_DRV_LOG(ERR, "VEB setup failed");
4683                         return NULL;
4684                 }
4685         }
4686
4687         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4688         if (!vsi) {
4689                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4690                 return NULL;
4691         }
4692         TAILQ_INIT(&vsi->mac_list);
4693         vsi->type = type;
4694         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4695         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4696         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4697         vsi->user_param = user_param;
4698         vsi->vlan_anti_spoof_on = 0;
4699         vsi->vlan_filter_on = 0;
4700         /* Allocate queues */
4701         switch (vsi->type) {
4702         case I40E_VSI_MAIN  :
4703                 vsi->nb_qps = pf->lan_nb_qps;
4704                 break;
4705         case I40E_VSI_SRIOV :
4706                 vsi->nb_qps = pf->vf_nb_qps;
4707                 break;
4708         case I40E_VSI_VMDQ2:
4709                 vsi->nb_qps = pf->vmdq_nb_qps;
4710                 break;
4711         case I40E_VSI_FDIR:
4712                 vsi->nb_qps = pf->fdir_nb_qps;
4713                 break;
4714         default:
4715                 goto fail_mem;
4716         }
4717         /*
4718          * The filter status descriptor is reported in rx queue 0,
4719          * while the tx queue for fdir filter programming has no
4720          * such constraints, can be non-zero queues.
4721          * To simplify it, choose FDIR vsi use queue 0 pair.
4722          * To make sure it will use queue 0 pair, queue allocation
4723          * need be done before this function is called
4724          */
4725         if (type != I40E_VSI_FDIR) {
4726                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4727                         if (ret < 0) {
4728                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4729                                                 vsi->seid, ret);
4730                                 goto fail_mem;
4731                         }
4732                         vsi->base_queue = ret;
4733         } else
4734                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4735
4736         /* VF has MSIX interrupt in VF range, don't allocate here */
4737         if (type == I40E_VSI_MAIN) {
4738                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4739                                           RTE_MIN(vsi->nb_qps,
4740                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4741                 if (ret < 0) {
4742                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4743                                     vsi->seid, ret);
4744                         goto fail_queue_alloc;
4745                 }
4746                 vsi->msix_intr = ret;
4747                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4748         } else if (type != I40E_VSI_SRIOV) {
4749                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4750                 if (ret < 0) {
4751                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4752                         goto fail_queue_alloc;
4753                 }
4754                 vsi->msix_intr = ret;
4755                 vsi->nb_msix = 1;
4756         } else {
4757                 vsi->msix_intr = 0;
4758                 vsi->nb_msix = 0;
4759         }
4760
4761         /* Add VSI */
4762         if (type == I40E_VSI_MAIN) {
4763                 /* For main VSI, no need to add since it's default one */
4764                 vsi->uplink_seid = pf->mac_seid;
4765                 vsi->seid = pf->main_vsi_seid;
4766                 /* Bind queues with specific MSIX interrupt */
4767                 /**
4768                  * Needs 2 interrupt at least, one for misc cause which will
4769                  * enabled from OS side, Another for queues binding the
4770                  * interrupt from device side only.
4771                  */
4772
4773                 /* Get default VSI parameters from hardware */
4774                 memset(&ctxt, 0, sizeof(ctxt));
4775                 ctxt.seid = vsi->seid;
4776                 ctxt.pf_num = hw->pf_id;
4777                 ctxt.uplink_seid = vsi->uplink_seid;
4778                 ctxt.vf_num = 0;
4779                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4780                 if (ret != I40E_SUCCESS) {
4781                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4782                         goto fail_msix_alloc;
4783                 }
4784                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4785                         sizeof(struct i40e_aqc_vsi_properties_data));
4786                 vsi->vsi_id = ctxt.vsi_number;
4787                 vsi->info.valid_sections = 0;
4788
4789                 /* Configure tc, enabled TC0 only */
4790                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4791                         I40E_SUCCESS) {
4792                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4793                         goto fail_msix_alloc;
4794                 }
4795
4796                 /* TC, queue mapping */
4797                 memset(&ctxt, 0, sizeof(ctxt));
4798                 vsi->info.valid_sections |=
4799                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4800                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4801                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4802                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4803                         sizeof(struct i40e_aqc_vsi_properties_data));
4804                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4805                                                 I40E_DEFAULT_TCMAP);
4806                 if (ret != I40E_SUCCESS) {
4807                         PMD_DRV_LOG(ERR,
4808                                 "Failed to configure TC queue mapping");
4809                         goto fail_msix_alloc;
4810                 }
4811                 ctxt.seid = vsi->seid;
4812                 ctxt.pf_num = hw->pf_id;
4813                 ctxt.uplink_seid = vsi->uplink_seid;
4814                 ctxt.vf_num = 0;
4815
4816                 /* Update VSI parameters */
4817                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4818                 if (ret != I40E_SUCCESS) {
4819                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4820                         goto fail_msix_alloc;
4821                 }
4822
4823                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4824                                                 sizeof(vsi->info.tc_mapping));
4825                 (void)rte_memcpy(&vsi->info.queue_mapping,
4826                                 &ctxt.info.queue_mapping,
4827                         sizeof(vsi->info.queue_mapping));
4828                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4829                 vsi->info.valid_sections = 0;
4830
4831                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4832                                 ETH_ADDR_LEN);
4833
4834                 /**
4835                  * Updating default filter settings are necessary to prevent
4836                  * reception of tagged packets.
4837                  * Some old firmware configurations load a default macvlan
4838                  * filter which accepts both tagged and untagged packets.
4839                  * The updating is to use a normal filter instead if needed.
4840                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4841                  * The firmware with correct configurations load the default
4842                  * macvlan filter which is expected and cannot be removed.
4843                  */
4844                 i40e_update_default_filter_setting(vsi);
4845                 i40e_config_qinq(hw, vsi);
4846         } else if (type == I40E_VSI_SRIOV) {
4847                 memset(&ctxt, 0, sizeof(ctxt));
4848                 /**
4849                  * For other VSI, the uplink_seid equals to uplink VSI's
4850                  * uplink_seid since they share same VEB
4851                  */
4852                 if (uplink_vsi == NULL)
4853                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4854                 else
4855                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4856                 ctxt.pf_num = hw->pf_id;
4857                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4858                 ctxt.uplink_seid = vsi->uplink_seid;
4859                 ctxt.connection_type = 0x1;
4860                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4861
4862                 /* Use the VEB configuration if FW >= v5.0 */
4863                 if (hw->aq.fw_maj_ver >= 5) {
4864                         /* Configure switch ID */
4865                         ctxt.info.valid_sections |=
4866                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4867                         ctxt.info.switch_id =
4868                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4869                 }
4870
4871                 /* Configure port/vlan */
4872                 ctxt.info.valid_sections |=
4873                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4874                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4875                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4876                                                 hw->func_caps.enabled_tcmap);
4877                 if (ret != I40E_SUCCESS) {
4878                         PMD_DRV_LOG(ERR,
4879                                 "Failed to configure TC queue mapping");
4880                         goto fail_msix_alloc;
4881                 }
4882
4883                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4884                 ctxt.info.valid_sections |=
4885                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4886                 /**
4887                  * Since VSI is not created yet, only configure parameter,
4888                  * will add vsi below.
4889                  */
4890
4891                 i40e_config_qinq(hw, vsi);
4892         } else if (type == I40E_VSI_VMDQ2) {
4893                 memset(&ctxt, 0, sizeof(ctxt));
4894                 /*
4895                  * For other VSI, the uplink_seid equals to uplink VSI's
4896                  * uplink_seid since they share same VEB
4897                  */
4898                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4899                 ctxt.pf_num = hw->pf_id;
4900                 ctxt.vf_num = 0;
4901                 ctxt.uplink_seid = vsi->uplink_seid;
4902                 ctxt.connection_type = 0x1;
4903                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4904
4905                 ctxt.info.valid_sections |=
4906                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4907                 /* user_param carries flag to enable loop back */
4908                 if (user_param) {
4909                         ctxt.info.switch_id =
4910                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4911                         ctxt.info.switch_id |=
4912                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4913                 }
4914
4915                 /* Configure port/vlan */
4916                 ctxt.info.valid_sections |=
4917                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4918                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4919                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4920                                                 I40E_DEFAULT_TCMAP);
4921                 if (ret != I40E_SUCCESS) {
4922                         PMD_DRV_LOG(ERR,
4923                                 "Failed to configure TC queue mapping");
4924                         goto fail_msix_alloc;
4925                 }
4926                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4927                 ctxt.info.valid_sections |=
4928                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4929         } else if (type == I40E_VSI_FDIR) {
4930                 memset(&ctxt, 0, sizeof(ctxt));
4931                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4932                 ctxt.pf_num = hw->pf_id;
4933                 ctxt.vf_num = 0;
4934                 ctxt.uplink_seid = vsi->uplink_seid;
4935                 ctxt.connection_type = 0x1;     /* regular data port */
4936                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4937                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4938                                                 I40E_DEFAULT_TCMAP);
4939                 if (ret != I40E_SUCCESS) {
4940                         PMD_DRV_LOG(ERR,
4941                                 "Failed to configure TC queue mapping.");
4942                         goto fail_msix_alloc;
4943                 }
4944                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4945                 ctxt.info.valid_sections |=
4946                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4947         } else {
4948                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4949                 goto fail_msix_alloc;
4950         }
4951
4952         if (vsi->type != I40E_VSI_MAIN) {
4953                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4954                 if (ret != I40E_SUCCESS) {
4955                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4956                                     hw->aq.asq_last_status);
4957                         goto fail_msix_alloc;
4958                 }
4959                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4960                 vsi->info.valid_sections = 0;
4961                 vsi->seid = ctxt.seid;
4962                 vsi->vsi_id = ctxt.vsi_number;
4963                 vsi->sib_vsi_list.vsi = vsi;
4964                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4965                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4966                                           &vsi->sib_vsi_list, list);
4967                 } else {
4968                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4969                                           &vsi->sib_vsi_list, list);
4970                 }
4971         }
4972
4973         /* MAC/VLAN configuration */
4974         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4975         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4976
4977         ret = i40e_vsi_add_mac(vsi, &filter);
4978         if (ret != I40E_SUCCESS) {
4979                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4980                 goto fail_msix_alloc;
4981         }
4982
4983         /* Get VSI BW information */
4984         i40e_vsi_get_bw_config(vsi);
4985         return vsi;
4986 fail_msix_alloc:
4987         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4988 fail_queue_alloc:
4989         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4990 fail_mem:
4991         rte_free(vsi);
4992         return NULL;
4993 }
4994
4995 /* Configure vlan filter on or off */
4996 int
4997 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4998 {
4999         int i, num;
5000         struct i40e_mac_filter *f;
5001         void *temp;
5002         struct i40e_mac_filter_info *mac_filter;
5003         enum rte_mac_filter_type desired_filter;
5004         int ret = I40E_SUCCESS;
5005
5006         if (on) {
5007                 /* Filter to match MAC and VLAN */
5008                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5009         } else {
5010                 /* Filter to match only MAC */
5011                 desired_filter = RTE_MAC_PERFECT_MATCH;
5012         }
5013
5014         num = vsi->mac_num;
5015
5016         mac_filter = rte_zmalloc("mac_filter_info_data",
5017                                  num * sizeof(*mac_filter), 0);
5018         if (mac_filter == NULL) {
5019                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5020                 return I40E_ERR_NO_MEMORY;
5021         }
5022
5023         i = 0;
5024
5025         /* Remove all existing mac */
5026         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5027                 mac_filter[i] = f->mac_info;
5028                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5029                 if (ret) {
5030                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5031                                     on ? "enable" : "disable");
5032                         goto DONE;
5033                 }
5034                 i++;
5035         }
5036
5037         /* Override with new filter */
5038         for (i = 0; i < num; i++) {
5039                 mac_filter[i].filter_type = desired_filter;
5040                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5041                 if (ret) {
5042                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5043                                     on ? "enable" : "disable");
5044                         goto DONE;
5045                 }
5046         }
5047
5048 DONE:
5049         rte_free(mac_filter);
5050         return ret;
5051 }
5052
5053 /* Configure vlan stripping on or off */
5054 int
5055 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5056 {
5057         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5058         struct i40e_vsi_context ctxt;
5059         uint8_t vlan_flags;
5060         int ret = I40E_SUCCESS;
5061
5062         /* Check if it has been already on or off */
5063         if (vsi->info.valid_sections &
5064                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5065                 if (on) {
5066                         if ((vsi->info.port_vlan_flags &
5067                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5068                                 return 0; /* already on */
5069                 } else {
5070                         if ((vsi->info.port_vlan_flags &
5071                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5072                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5073                                 return 0; /* already off */
5074                 }
5075         }
5076
5077         if (on)
5078                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5079         else
5080                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5081         vsi->info.valid_sections =
5082                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5083         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5084         vsi->info.port_vlan_flags |= vlan_flags;
5085         ctxt.seid = vsi->seid;
5086         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5087         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5088         if (ret)
5089                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5090                             on ? "enable" : "disable");
5091
5092         return ret;
5093 }
5094
5095 static int
5096 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5097 {
5098         struct rte_eth_dev_data *data = dev->data;
5099         int ret;
5100         int mask = 0;
5101
5102         /* Apply vlan offload setting */
5103         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5104         i40e_vlan_offload_set(dev, mask);
5105
5106         /* Apply double-vlan setting, not implemented yet */
5107
5108         /* Apply pvid setting */
5109         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5110                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5111         if (ret)
5112                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5113
5114         return ret;
5115 }
5116
5117 static int
5118 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5119 {
5120         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5121
5122         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5123 }
5124
5125 static int
5126 i40e_update_flow_control(struct i40e_hw *hw)
5127 {
5128 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5129         struct i40e_link_status link_status;
5130         uint32_t rxfc = 0, txfc = 0, reg;
5131         uint8_t an_info;
5132         int ret;
5133
5134         memset(&link_status, 0, sizeof(link_status));
5135         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5136         if (ret != I40E_SUCCESS) {
5137                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5138                 goto write_reg; /* Disable flow control */
5139         }
5140
5141         an_info = hw->phy.link_info.an_info;
5142         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5143                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5144                 ret = I40E_ERR_NOT_READY;
5145                 goto write_reg; /* Disable flow control */
5146         }
5147         /**
5148          * If link auto negotiation is enabled, flow control needs to
5149          * be configured according to it
5150          */
5151         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5152         case I40E_LINK_PAUSE_RXTX:
5153                 rxfc = 1;
5154                 txfc = 1;
5155                 hw->fc.current_mode = I40E_FC_FULL;
5156                 break;
5157         case I40E_AQ_LINK_PAUSE_RX:
5158                 rxfc = 1;
5159                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5160                 break;
5161         case I40E_AQ_LINK_PAUSE_TX:
5162                 txfc = 1;
5163                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5164                 break;
5165         default:
5166                 hw->fc.current_mode = I40E_FC_NONE;
5167                 break;
5168         }
5169
5170 write_reg:
5171         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5172                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5173         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5174         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5175         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5176         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5177
5178         return ret;
5179 }
5180
5181 /* PF setup */
5182 static int
5183 i40e_pf_setup(struct i40e_pf *pf)
5184 {
5185         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5186         struct i40e_filter_control_settings settings;
5187         struct i40e_vsi *vsi;
5188         int ret;
5189
5190         /* Clear all stats counters */
5191         pf->offset_loaded = FALSE;
5192         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5193         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5194
5195         ret = i40e_pf_get_switch_config(pf);
5196         if (ret != I40E_SUCCESS) {
5197                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5198                 return ret;
5199         }
5200         if (pf->flags & I40E_FLAG_FDIR) {
5201                 /* make queue allocated first, let FDIR use queue pair 0*/
5202                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5203                 if (ret != I40E_FDIR_QUEUE_ID) {
5204                         PMD_DRV_LOG(ERR,
5205                                 "queue allocation fails for FDIR: ret =%d",
5206                                 ret);
5207                         pf->flags &= ~I40E_FLAG_FDIR;
5208                 }
5209         }
5210         /*  main VSI setup */
5211         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5212         if (!vsi) {
5213                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5214                 return I40E_ERR_NOT_READY;
5215         }
5216         pf->main_vsi = vsi;
5217
5218         /* Configure filter control */
5219         memset(&settings, 0, sizeof(settings));
5220         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5221                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5222         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5223                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5224         else {
5225                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5226                         hw->func_caps.rss_table_size);
5227                 return I40E_ERR_PARAM;
5228         }
5229         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5230                 hw->func_caps.rss_table_size);
5231         pf->hash_lut_size = hw->func_caps.rss_table_size;
5232
5233         /* Enable ethtype and macvlan filters */
5234         settings.enable_ethtype = TRUE;
5235         settings.enable_macvlan = TRUE;
5236         ret = i40e_set_filter_control(hw, &settings);
5237         if (ret)
5238                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5239                                                                 ret);
5240
5241         /* Update flow control according to the auto negotiation */
5242         i40e_update_flow_control(hw);
5243
5244         return I40E_SUCCESS;
5245 }
5246
5247 int
5248 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5249 {
5250         uint32_t reg;
5251         uint16_t j;
5252
5253         /**
5254          * Set or clear TX Queue Disable flags,
5255          * which is required by hardware.
5256          */
5257         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5258         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5259
5260         /* Wait until the request is finished */
5261         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5262                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5263                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5264                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5265                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5266                                                         & 0x1))) {
5267                         break;
5268                 }
5269         }
5270         if (on) {
5271                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5272                         return I40E_SUCCESS; /* already on, skip next steps */
5273
5274                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5275                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5276         } else {
5277                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5278                         return I40E_SUCCESS; /* already off, skip next steps */
5279                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5280         }
5281         /* Write the register */
5282         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5283         /* Check the result */
5284         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5285                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5286                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5287                 if (on) {
5288                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5289                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5290                                 break;
5291                 } else {
5292                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5293                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5294                                 break;
5295                 }
5296         }
5297         /* Check if it is timeout */
5298         if (j >= I40E_CHK_Q_ENA_COUNT) {
5299                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5300                             (on ? "enable" : "disable"), q_idx);
5301                 return I40E_ERR_TIMEOUT;
5302         }
5303
5304         return I40E_SUCCESS;
5305 }
5306
5307 /* Swith on or off the tx queues */
5308 static int
5309 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5310 {
5311         struct rte_eth_dev_data *dev_data = pf->dev_data;
5312         struct i40e_tx_queue *txq;
5313         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5314         uint16_t i;
5315         int ret;
5316
5317         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5318                 txq = dev_data->tx_queues[i];
5319                 /* Don't operate the queue if not configured or
5320                  * if starting only per queue */
5321                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5322                         continue;
5323                 if (on)
5324                         ret = i40e_dev_tx_queue_start(dev, i);
5325                 else
5326                         ret = i40e_dev_tx_queue_stop(dev, i);
5327                 if ( ret != I40E_SUCCESS)
5328                         return ret;
5329         }
5330
5331         return I40E_SUCCESS;
5332 }
5333
5334 int
5335 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5336 {
5337         uint32_t reg;
5338         uint16_t j;
5339
5340         /* Wait until the request is finished */
5341         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5342                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5343                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5344                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5345                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5346                         break;
5347         }
5348
5349         if (on) {
5350                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5351                         return I40E_SUCCESS; /* Already on, skip next steps */
5352                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5353         } else {
5354                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5355                         return I40E_SUCCESS; /* Already off, skip next steps */
5356                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5357         }
5358
5359         /* Write the register */
5360         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5361         /* Check the result */
5362         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5363                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5364                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5365                 if (on) {
5366                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5367                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5368                                 break;
5369                 } else {
5370                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5371                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5372                                 break;
5373                 }
5374         }
5375
5376         /* Check if it is timeout */
5377         if (j >= I40E_CHK_Q_ENA_COUNT) {
5378                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5379                             (on ? "enable" : "disable"), q_idx);
5380                 return I40E_ERR_TIMEOUT;
5381         }
5382
5383         return I40E_SUCCESS;
5384 }
5385 /* Switch on or off the rx queues */
5386 static int
5387 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5388 {
5389         struct rte_eth_dev_data *dev_data = pf->dev_data;
5390         struct i40e_rx_queue *rxq;
5391         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5392         uint16_t i;
5393         int ret;
5394
5395         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5396                 rxq = dev_data->rx_queues[i];
5397                 /* Don't operate the queue if not configured or
5398                  * if starting only per queue */
5399                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5400                         continue;
5401                 if (on)
5402                         ret = i40e_dev_rx_queue_start(dev, i);
5403                 else
5404                         ret = i40e_dev_rx_queue_stop(dev, i);
5405                 if (ret != I40E_SUCCESS)
5406                         return ret;
5407         }
5408
5409         return I40E_SUCCESS;
5410 }
5411
5412 /* Switch on or off all the rx/tx queues */
5413 int
5414 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5415 {
5416         int ret;
5417
5418         if (on) {
5419                 /* enable rx queues before enabling tx queues */
5420                 ret = i40e_dev_switch_rx_queues(pf, on);
5421                 if (ret) {
5422                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5423                         return ret;
5424                 }
5425                 ret = i40e_dev_switch_tx_queues(pf, on);
5426         } else {
5427                 /* Stop tx queues before stopping rx queues */
5428                 ret = i40e_dev_switch_tx_queues(pf, on);
5429                 if (ret) {
5430                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5431                         return ret;
5432                 }
5433                 ret = i40e_dev_switch_rx_queues(pf, on);
5434         }
5435
5436         return ret;
5437 }
5438
5439 /* Initialize VSI for TX */
5440 static int
5441 i40e_dev_tx_init(struct i40e_pf *pf)
5442 {
5443         struct rte_eth_dev_data *data = pf->dev_data;
5444         uint16_t i;
5445         uint32_t ret = I40E_SUCCESS;
5446         struct i40e_tx_queue *txq;
5447
5448         for (i = 0; i < data->nb_tx_queues; i++) {
5449                 txq = data->tx_queues[i];
5450                 if (!txq || !txq->q_set)
5451                         continue;
5452                 ret = i40e_tx_queue_init(txq);
5453                 if (ret != I40E_SUCCESS)
5454                         break;
5455         }
5456         if (ret == I40E_SUCCESS)
5457                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5458                                      ->eth_dev);
5459
5460         return ret;
5461 }
5462
5463 /* Initialize VSI for RX */
5464 static int
5465 i40e_dev_rx_init(struct i40e_pf *pf)
5466 {
5467         struct rte_eth_dev_data *data = pf->dev_data;
5468         int ret = I40E_SUCCESS;
5469         uint16_t i;
5470         struct i40e_rx_queue *rxq;
5471
5472         i40e_pf_config_mq_rx(pf);
5473         for (i = 0; i < data->nb_rx_queues; i++) {
5474                 rxq = data->rx_queues[i];
5475                 if (!rxq || !rxq->q_set)
5476                         continue;
5477
5478                 ret = i40e_rx_queue_init(rxq);
5479                 if (ret != I40E_SUCCESS) {
5480                         PMD_DRV_LOG(ERR,
5481                                 "Failed to do RX queue initialization");
5482                         break;
5483                 }
5484         }
5485         if (ret == I40E_SUCCESS)
5486                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5487                                      ->eth_dev);
5488
5489         return ret;
5490 }
5491
5492 static int
5493 i40e_dev_rxtx_init(struct i40e_pf *pf)
5494 {
5495         int err;
5496
5497         err = i40e_dev_tx_init(pf);
5498         if (err) {
5499                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5500                 return err;
5501         }
5502         err = i40e_dev_rx_init(pf);
5503         if (err) {
5504                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5505                 return err;
5506         }
5507
5508         return err;
5509 }
5510
5511 static int
5512 i40e_vmdq_setup(struct rte_eth_dev *dev)
5513 {
5514         struct rte_eth_conf *conf = &dev->data->dev_conf;
5515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5516         int i, err, conf_vsis, j, loop;
5517         struct i40e_vsi *vsi;
5518         struct i40e_vmdq_info *vmdq_info;
5519         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5520         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5521
5522         /*
5523          * Disable interrupt to avoid message from VF. Furthermore, it will
5524          * avoid race condition in VSI creation/destroy.
5525          */
5526         i40e_pf_disable_irq0(hw);
5527
5528         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5529                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5530                 return -ENOTSUP;
5531         }
5532
5533         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5534         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5535                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5536                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5537                         pf->max_nb_vmdq_vsi);
5538                 return -ENOTSUP;
5539         }
5540
5541         if (pf->vmdq != NULL) {
5542                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5543                 return 0;
5544         }
5545
5546         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5547                                 sizeof(*vmdq_info) * conf_vsis, 0);
5548
5549         if (pf->vmdq == NULL) {
5550                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5551                 return -ENOMEM;
5552         }
5553
5554         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5555
5556         /* Create VMDQ VSI */
5557         for (i = 0; i < conf_vsis; i++) {
5558                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5559                                 vmdq_conf->enable_loop_back);
5560                 if (vsi == NULL) {
5561                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5562                         err = -1;
5563                         goto err_vsi_setup;
5564                 }
5565                 vmdq_info = &pf->vmdq[i];
5566                 vmdq_info->pf = pf;
5567                 vmdq_info->vsi = vsi;
5568         }
5569         pf->nb_cfg_vmdq_vsi = conf_vsis;
5570
5571         /* Configure Vlan */
5572         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5573         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5574                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5575                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5576                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5577                                         vmdq_conf->pool_map[i].vlan_id, j);
5578
5579                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5580                                                 vmdq_conf->pool_map[i].vlan_id);
5581                                 if (err) {
5582                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5583                                         err = -1;
5584                                         goto err_vsi_setup;
5585                                 }
5586                         }
5587                 }
5588         }
5589
5590         i40e_pf_enable_irq0(hw);
5591
5592         return 0;
5593
5594 err_vsi_setup:
5595         for (i = 0; i < conf_vsis; i++)
5596                 if (pf->vmdq[i].vsi == NULL)
5597                         break;
5598                 else
5599                         i40e_vsi_release(pf->vmdq[i].vsi);
5600
5601         rte_free(pf->vmdq);
5602         pf->vmdq = NULL;
5603         i40e_pf_enable_irq0(hw);
5604         return err;
5605 }
5606
5607 static void
5608 i40e_stat_update_32(struct i40e_hw *hw,
5609                    uint32_t reg,
5610                    bool offset_loaded,
5611                    uint64_t *offset,
5612                    uint64_t *stat)
5613 {
5614         uint64_t new_data;
5615
5616         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5617         if (!offset_loaded)
5618                 *offset = new_data;
5619
5620         if (new_data >= *offset)
5621                 *stat = (uint64_t)(new_data - *offset);
5622         else
5623                 *stat = (uint64_t)((new_data +
5624                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5625 }
5626
5627 static void
5628 i40e_stat_update_48(struct i40e_hw *hw,
5629                    uint32_t hireg,
5630                    uint32_t loreg,
5631                    bool offset_loaded,
5632                    uint64_t *offset,
5633                    uint64_t *stat)
5634 {
5635         uint64_t new_data;
5636
5637         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5638         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5639                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5640
5641         if (!offset_loaded)
5642                 *offset = new_data;
5643
5644         if (new_data >= *offset)
5645                 *stat = new_data - *offset;
5646         else
5647                 *stat = (uint64_t)((new_data +
5648                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5649
5650         *stat &= I40E_48_BIT_MASK;
5651 }
5652
5653 /* Disable IRQ0 */
5654 void
5655 i40e_pf_disable_irq0(struct i40e_hw *hw)
5656 {
5657         /* Disable all interrupt types */
5658         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5659         I40E_WRITE_FLUSH(hw);
5660 }
5661
5662 /* Enable IRQ0 */
5663 void
5664 i40e_pf_enable_irq0(struct i40e_hw *hw)
5665 {
5666         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5667                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5668                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5669                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5670         I40E_WRITE_FLUSH(hw);
5671 }
5672
5673 static void
5674 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5675 {
5676         /* read pending request and disable first */
5677         i40e_pf_disable_irq0(hw);
5678         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5679         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5680                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5681
5682         if (no_queue)
5683                 /* Link no queues with irq0 */
5684                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5685                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5686 }
5687
5688 static void
5689 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5690 {
5691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5693         int i;
5694         uint16_t abs_vf_id;
5695         uint32_t index, offset, val;
5696
5697         if (!pf->vfs)
5698                 return;
5699         /**
5700          * Try to find which VF trigger a reset, use absolute VF id to access
5701          * since the reg is global register.
5702          */
5703         for (i = 0; i < pf->vf_num; i++) {
5704                 abs_vf_id = hw->func_caps.vf_base_id + i;
5705                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5706                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5707                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5708                 /* VFR event occured */
5709                 if (val & (0x1 << offset)) {
5710                         int ret;
5711
5712                         /* Clear the event first */
5713                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5714                                                         (0x1 << offset));
5715                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5716                         /**
5717                          * Only notify a VF reset event occured,
5718                          * don't trigger another SW reset
5719                          */
5720                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5721                         if (ret != I40E_SUCCESS)
5722                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5723                 }
5724         }
5725 }
5726
5727 static void
5728 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5729 {
5730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5731         int i;
5732
5733         for (i = 0; i < pf->vf_num; i++)
5734                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5735 }
5736
5737 static void
5738 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5739 {
5740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741         struct i40e_arq_event_info info;
5742         uint16_t pending, opcode;
5743         int ret;
5744
5745         info.buf_len = I40E_AQ_BUF_SZ;
5746         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5747         if (!info.msg_buf) {
5748                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5749                 return;
5750         }
5751
5752         pending = 1;
5753         while (pending) {
5754                 ret = i40e_clean_arq_element(hw, &info, &pending);
5755
5756                 if (ret != I40E_SUCCESS) {
5757                         PMD_DRV_LOG(INFO,
5758                                 "Failed to read msg from AdminQ, aq_err: %u",
5759                                 hw->aq.asq_last_status);
5760                         break;
5761                 }
5762                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5763
5764                 switch (opcode) {
5765                 case i40e_aqc_opc_send_msg_to_pf:
5766                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5767                         i40e_pf_host_handle_vf_msg(dev,
5768                                         rte_le_to_cpu_16(info.desc.retval),
5769                                         rte_le_to_cpu_32(info.desc.cookie_high),
5770                                         rte_le_to_cpu_32(info.desc.cookie_low),
5771                                         info.msg_buf,
5772                                         info.msg_len);
5773                         break;
5774                 case i40e_aqc_opc_get_link_status:
5775                         ret = i40e_dev_link_update(dev, 0);
5776                         if (!ret) {
5777                                 i40e_notify_all_vfs_link_status(dev);
5778                                 _rte_eth_dev_callback_process(dev,
5779                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5780                         }
5781                         break;
5782                 default:
5783                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5784                                     opcode);
5785                         break;
5786                 }
5787         }
5788         rte_free(info.msg_buf);
5789 }
5790
5791 /**
5792  * Interrupt handler triggered by NIC  for handling
5793  * specific interrupt.
5794  *
5795  * @param handle
5796  *  Pointer to interrupt handle.
5797  * @param param
5798  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5799  *
5800  * @return
5801  *  void
5802  */
5803 static void
5804 i40e_dev_interrupt_handler(void *param)
5805 {
5806         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808         uint32_t icr0;
5809
5810         /* Disable interrupt */
5811         i40e_pf_disable_irq0(hw);
5812
5813         /* read out interrupt causes */
5814         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5815
5816         /* No interrupt event indicated */
5817         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5818                 PMD_DRV_LOG(INFO, "No interrupt event");
5819                 goto done;
5820         }
5821         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5822                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5823         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5824                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5825         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5826                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5827         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5828                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5829         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5830                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5831         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5832                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5833         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5834                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5835
5836         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5837                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5838                 i40e_dev_handle_vfr_event(dev);
5839         }
5840         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5841                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5842                 i40e_dev_handle_aq_msg(dev);
5843         }
5844
5845 done:
5846         /* Enable interrupt */
5847         i40e_pf_enable_irq0(hw);
5848         rte_intr_enable(dev->intr_handle);
5849 }
5850
5851 int
5852 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5853                          struct i40e_macvlan_filter *filter,
5854                          int total)
5855 {
5856         int ele_num, ele_buff_size;
5857         int num, actual_num, i;
5858         uint16_t flags;
5859         int ret = I40E_SUCCESS;
5860         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5861         struct i40e_aqc_add_macvlan_element_data *req_list;
5862
5863         if (filter == NULL  || total == 0)
5864                 return I40E_ERR_PARAM;
5865         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5866         ele_buff_size = hw->aq.asq_buf_size;
5867
5868         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5869         if (req_list == NULL) {
5870                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5871                 return I40E_ERR_NO_MEMORY;
5872         }
5873
5874         num = 0;
5875         do {
5876                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5877                 memset(req_list, 0, ele_buff_size);
5878
5879                 for (i = 0; i < actual_num; i++) {
5880                         (void)rte_memcpy(req_list[i].mac_addr,
5881                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5882                         req_list[i].vlan_tag =
5883                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5884
5885                         switch (filter[num + i].filter_type) {
5886                         case RTE_MAC_PERFECT_MATCH:
5887                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5888                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5889                                 break;
5890                         case RTE_MACVLAN_PERFECT_MATCH:
5891                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5892                                 break;
5893                         case RTE_MAC_HASH_MATCH:
5894                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5895                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5896                                 break;
5897                         case RTE_MACVLAN_HASH_MATCH:
5898                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5899                                 break;
5900                         default:
5901                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5902                                 ret = I40E_ERR_PARAM;
5903                                 goto DONE;
5904                         }
5905
5906                         req_list[i].queue_number = 0;
5907
5908                         req_list[i].flags = rte_cpu_to_le_16(flags);
5909                 }
5910
5911                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5912                                                 actual_num, NULL);
5913                 if (ret != I40E_SUCCESS) {
5914                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5915                         goto DONE;
5916                 }
5917                 num += actual_num;
5918         } while (num < total);
5919
5920 DONE:
5921         rte_free(req_list);
5922         return ret;
5923 }
5924
5925 int
5926 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5927                             struct i40e_macvlan_filter *filter,
5928                             int total)
5929 {
5930         int ele_num, ele_buff_size;
5931         int num, actual_num, i;
5932         uint16_t flags;
5933         int ret = I40E_SUCCESS;
5934         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5935         struct i40e_aqc_remove_macvlan_element_data *req_list;
5936
5937         if (filter == NULL  || total == 0)
5938                 return I40E_ERR_PARAM;
5939
5940         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5941         ele_buff_size = hw->aq.asq_buf_size;
5942
5943         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5944         if (req_list == NULL) {
5945                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5946                 return I40E_ERR_NO_MEMORY;
5947         }
5948
5949         num = 0;
5950         do {
5951                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5952                 memset(req_list, 0, ele_buff_size);
5953
5954                 for (i = 0; i < actual_num; i++) {
5955                         (void)rte_memcpy(req_list[i].mac_addr,
5956                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5957                         req_list[i].vlan_tag =
5958                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5959
5960                         switch (filter[num + i].filter_type) {
5961                         case RTE_MAC_PERFECT_MATCH:
5962                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5963                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5964                                 break;
5965                         case RTE_MACVLAN_PERFECT_MATCH:
5966                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5967                                 break;
5968                         case RTE_MAC_HASH_MATCH:
5969                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5970                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5971                                 break;
5972                         case RTE_MACVLAN_HASH_MATCH:
5973                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5974                                 break;
5975                         default:
5976                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5977                                 ret = I40E_ERR_PARAM;
5978                                 goto DONE;
5979                         }
5980                         req_list[i].flags = rte_cpu_to_le_16(flags);
5981                 }
5982
5983                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5984                                                 actual_num, NULL);
5985                 if (ret != I40E_SUCCESS) {
5986                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5987                         goto DONE;
5988                 }
5989                 num += actual_num;
5990         } while (num < total);
5991
5992 DONE:
5993         rte_free(req_list);
5994         return ret;
5995 }
5996
5997 /* Find out specific MAC filter */
5998 static struct i40e_mac_filter *
5999 i40e_find_mac_filter(struct i40e_vsi *vsi,
6000                          struct ether_addr *macaddr)
6001 {
6002         struct i40e_mac_filter *f;
6003
6004         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6005                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6006                         return f;
6007         }
6008
6009         return NULL;
6010 }
6011
6012 static bool
6013 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6014                          uint16_t vlan_id)
6015 {
6016         uint32_t vid_idx, vid_bit;
6017
6018         if (vlan_id > ETH_VLAN_ID_MAX)
6019                 return 0;
6020
6021         vid_idx = I40E_VFTA_IDX(vlan_id);
6022         vid_bit = I40E_VFTA_BIT(vlan_id);
6023
6024         if (vsi->vfta[vid_idx] & vid_bit)
6025                 return 1;
6026         else
6027                 return 0;
6028 }
6029
6030 static void
6031 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6032                        uint16_t vlan_id, bool on)
6033 {
6034         uint32_t vid_idx, vid_bit;
6035
6036         vid_idx = I40E_VFTA_IDX(vlan_id);
6037         vid_bit = I40E_VFTA_BIT(vlan_id);
6038
6039         if (on)
6040                 vsi->vfta[vid_idx] |= vid_bit;
6041         else
6042                 vsi->vfta[vid_idx] &= ~vid_bit;
6043 }
6044
6045 void
6046 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6047                      uint16_t vlan_id, bool on)
6048 {
6049         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6050         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6051         int ret;
6052
6053         if (vlan_id > ETH_VLAN_ID_MAX)
6054                 return;
6055
6056         i40e_store_vlan_filter(vsi, vlan_id, on);
6057
6058         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6059                 return;
6060
6061         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6062
6063         if (on) {
6064                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6065                                        &vlan_data, 1, NULL);
6066                 if (ret != I40E_SUCCESS)
6067                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6068         } else {
6069                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6070                                           &vlan_data, 1, NULL);
6071                 if (ret != I40E_SUCCESS)
6072                         PMD_DRV_LOG(ERR,
6073                                     "Failed to remove vlan filter");
6074         }
6075 }
6076
6077 /**
6078  * Find all vlan options for specific mac addr,
6079  * return with actual vlan found.
6080  */
6081 int
6082 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6083                            struct i40e_macvlan_filter *mv_f,
6084                            int num, struct ether_addr *addr)
6085 {
6086         int i;
6087         uint32_t j, k;
6088
6089         /**
6090          * Not to use i40e_find_vlan_filter to decrease the loop time,
6091          * although the code looks complex.
6092           */
6093         if (num < vsi->vlan_num)
6094                 return I40E_ERR_PARAM;
6095
6096         i = 0;
6097         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6098                 if (vsi->vfta[j]) {
6099                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6100                                 if (vsi->vfta[j] & (1 << k)) {
6101                                         if (i > num - 1) {
6102                                                 PMD_DRV_LOG(ERR,
6103                                                         "vlan number doesn't match");
6104                                                 return I40E_ERR_PARAM;
6105                                         }
6106                                         (void)rte_memcpy(&mv_f[i].macaddr,
6107                                                         addr, ETH_ADDR_LEN);
6108                                         mv_f[i].vlan_id =
6109                                                 j * I40E_UINT32_BIT_SIZE + k;
6110                                         i++;
6111                                 }
6112                         }
6113                 }
6114         }
6115         return I40E_SUCCESS;
6116 }
6117
6118 static inline int
6119 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6120                            struct i40e_macvlan_filter *mv_f,
6121                            int num,
6122                            uint16_t vlan)
6123 {
6124         int i = 0;
6125         struct i40e_mac_filter *f;
6126
6127         if (num < vsi->mac_num)
6128                 return I40E_ERR_PARAM;
6129
6130         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6131                 if (i > num - 1) {
6132                         PMD_DRV_LOG(ERR, "buffer number not match");
6133                         return I40E_ERR_PARAM;
6134                 }
6135                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6136                                 ETH_ADDR_LEN);
6137                 mv_f[i].vlan_id = vlan;
6138                 mv_f[i].filter_type = f->mac_info.filter_type;
6139                 i++;
6140         }
6141
6142         return I40E_SUCCESS;
6143 }
6144
6145 static int
6146 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6147 {
6148         int i, j, num;
6149         struct i40e_mac_filter *f;
6150         struct i40e_macvlan_filter *mv_f;
6151         int ret = I40E_SUCCESS;
6152
6153         if (vsi == NULL || vsi->mac_num == 0)
6154                 return I40E_ERR_PARAM;
6155
6156         /* Case that no vlan is set */
6157         if (vsi->vlan_num == 0)
6158                 num = vsi->mac_num;
6159         else
6160                 num = vsi->mac_num * vsi->vlan_num;
6161
6162         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6163         if (mv_f == NULL) {
6164                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6165                 return I40E_ERR_NO_MEMORY;
6166         }
6167
6168         i = 0;
6169         if (vsi->vlan_num == 0) {
6170                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6171                         (void)rte_memcpy(&mv_f[i].macaddr,
6172                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6173                         mv_f[i].filter_type = f->mac_info.filter_type;
6174                         mv_f[i].vlan_id = 0;
6175                         i++;
6176                 }
6177         } else {
6178                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6179                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6180                                         vsi->vlan_num, &f->mac_info.mac_addr);
6181                         if (ret != I40E_SUCCESS)
6182                                 goto DONE;
6183                         for (j = i; j < i + vsi->vlan_num; j++)
6184                                 mv_f[j].filter_type = f->mac_info.filter_type;
6185                         i += vsi->vlan_num;
6186                 }
6187         }
6188
6189         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6190 DONE:
6191         rte_free(mv_f);
6192
6193         return ret;
6194 }
6195
6196 int
6197 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6198 {
6199         struct i40e_macvlan_filter *mv_f;
6200         int mac_num;
6201         int ret = I40E_SUCCESS;
6202
6203         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6204                 return I40E_ERR_PARAM;
6205
6206         /* If it's already set, just return */
6207         if (i40e_find_vlan_filter(vsi,vlan))
6208                 return I40E_SUCCESS;
6209
6210         mac_num = vsi->mac_num;
6211
6212         if (mac_num == 0) {
6213                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6214                 return I40E_ERR_PARAM;
6215         }
6216
6217         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6218
6219         if (mv_f == NULL) {
6220                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6221                 return I40E_ERR_NO_MEMORY;
6222         }
6223
6224         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6225
6226         if (ret != I40E_SUCCESS)
6227                 goto DONE;
6228
6229         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6230
6231         if (ret != I40E_SUCCESS)
6232                 goto DONE;
6233
6234         i40e_set_vlan_filter(vsi, vlan, 1);
6235
6236         vsi->vlan_num++;
6237         ret = I40E_SUCCESS;
6238 DONE:
6239         rte_free(mv_f);
6240         return ret;
6241 }
6242
6243 int
6244 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6245 {
6246         struct i40e_macvlan_filter *mv_f;
6247         int mac_num;
6248         int ret = I40E_SUCCESS;
6249
6250         /**
6251          * Vlan 0 is the generic filter for untagged packets
6252          * and can't be removed.
6253          */
6254         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6255                 return I40E_ERR_PARAM;
6256
6257         /* If can't find it, just return */
6258         if (!i40e_find_vlan_filter(vsi, vlan))
6259                 return I40E_ERR_PARAM;
6260
6261         mac_num = vsi->mac_num;
6262
6263         if (mac_num == 0) {
6264                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6265                 return I40E_ERR_PARAM;
6266         }
6267
6268         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6269
6270         if (mv_f == NULL) {
6271                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6272                 return I40E_ERR_NO_MEMORY;
6273         }
6274
6275         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6276
6277         if (ret != I40E_SUCCESS)
6278                 goto DONE;
6279
6280         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6281
6282         if (ret != I40E_SUCCESS)
6283                 goto DONE;
6284
6285         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6286         if (vsi->vlan_num == 1) {
6287                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6288                 if (ret != I40E_SUCCESS)
6289                         goto DONE;
6290
6291                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6292                 if (ret != I40E_SUCCESS)
6293                         goto DONE;
6294         }
6295
6296         i40e_set_vlan_filter(vsi, vlan, 0);
6297
6298         vsi->vlan_num--;
6299         ret = I40E_SUCCESS;
6300 DONE:
6301         rte_free(mv_f);
6302         return ret;
6303 }
6304
6305 int
6306 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6307 {
6308         struct i40e_mac_filter *f;
6309         struct i40e_macvlan_filter *mv_f;
6310         int i, vlan_num = 0;
6311         int ret = I40E_SUCCESS;
6312
6313         /* If it's add and we've config it, return */
6314         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6315         if (f != NULL)
6316                 return I40E_SUCCESS;
6317         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6318                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6319
6320                 /**
6321                  * If vlan_num is 0, that's the first time to add mac,
6322                  * set mask for vlan_id 0.
6323                  */
6324                 if (vsi->vlan_num == 0) {
6325                         i40e_set_vlan_filter(vsi, 0, 1);
6326                         vsi->vlan_num = 1;
6327                 }
6328                 vlan_num = vsi->vlan_num;
6329         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6330                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6331                 vlan_num = 1;
6332
6333         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6334         if (mv_f == NULL) {
6335                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6336                 return I40E_ERR_NO_MEMORY;
6337         }
6338
6339         for (i = 0; i < vlan_num; i++) {
6340                 mv_f[i].filter_type = mac_filter->filter_type;
6341                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6342                                 ETH_ADDR_LEN);
6343         }
6344
6345         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6346                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6347                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6348                                         &mac_filter->mac_addr);
6349                 if (ret != I40E_SUCCESS)
6350                         goto DONE;
6351         }
6352
6353         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6354         if (ret != I40E_SUCCESS)
6355                 goto DONE;
6356
6357         /* Add the mac addr into mac list */
6358         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6359         if (f == NULL) {
6360                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6361                 ret = I40E_ERR_NO_MEMORY;
6362                 goto DONE;
6363         }
6364         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6365                         ETH_ADDR_LEN);
6366         f->mac_info.filter_type = mac_filter->filter_type;
6367         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6368         vsi->mac_num++;
6369
6370         ret = I40E_SUCCESS;
6371 DONE:
6372         rte_free(mv_f);
6373
6374         return ret;
6375 }
6376
6377 int
6378 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6379 {
6380         struct i40e_mac_filter *f;
6381         struct i40e_macvlan_filter *mv_f;
6382         int i, vlan_num;
6383         enum rte_mac_filter_type filter_type;
6384         int ret = I40E_SUCCESS;
6385
6386         /* Can't find it, return an error */
6387         f = i40e_find_mac_filter(vsi, addr);
6388         if (f == NULL)
6389                 return I40E_ERR_PARAM;
6390
6391         vlan_num = vsi->vlan_num;
6392         filter_type = f->mac_info.filter_type;
6393         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6394                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6395                 if (vlan_num == 0) {
6396                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6397                         return I40E_ERR_PARAM;
6398                 }
6399         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6400                         filter_type == RTE_MAC_HASH_MATCH)
6401                 vlan_num = 1;
6402
6403         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6404         if (mv_f == NULL) {
6405                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6406                 return I40E_ERR_NO_MEMORY;
6407         }
6408
6409         for (i = 0; i < vlan_num; i++) {
6410                 mv_f[i].filter_type = filter_type;
6411                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6412                                 ETH_ADDR_LEN);
6413         }
6414         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6415                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6416                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6417                 if (ret != I40E_SUCCESS)
6418                         goto DONE;
6419         }
6420
6421         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6422         if (ret != I40E_SUCCESS)
6423                 goto DONE;
6424
6425         /* Remove the mac addr into mac list */
6426         TAILQ_REMOVE(&vsi->mac_list, f, next);
6427         rte_free(f);
6428         vsi->mac_num--;
6429
6430         ret = I40E_SUCCESS;
6431 DONE:
6432         rte_free(mv_f);
6433         return ret;
6434 }
6435
6436 /* Configure hash enable flags for RSS */
6437 uint64_t
6438 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6439 {
6440         uint64_t hena = 0;
6441
6442         if (!flags)
6443                 return hena;
6444
6445         if (flags & ETH_RSS_FRAG_IPV4)
6446                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6447         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6448                 if (type == I40E_MAC_X722) {
6449                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6450                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6451                 } else
6452                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6453         }
6454         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6455                 if (type == I40E_MAC_X722) {
6456                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6457                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6458                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6459                 } else
6460                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6461         }
6462         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6463                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6464         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6465                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6466         if (flags & ETH_RSS_FRAG_IPV6)
6467                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6468         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6469                 if (type == I40E_MAC_X722) {
6470                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6471                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6472                 } else
6473                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6474         }
6475         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6476                 if (type == I40E_MAC_X722) {
6477                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6478                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6479                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6480                 } else
6481                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6482         }
6483         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6484                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6485         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6486                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6487         if (flags & ETH_RSS_L2_PAYLOAD)
6488                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6489
6490         return hena;
6491 }
6492
6493 /* Parse the hash enable flags */
6494 uint64_t
6495 i40e_parse_hena(uint64_t flags)
6496 {
6497         uint64_t rss_hf = 0;
6498
6499         if (!flags)
6500                 return rss_hf;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6502                 rss_hf |= ETH_RSS_FRAG_IPV4;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6508                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6511         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6512                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6513         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6514                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6515         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6516                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6518                 rss_hf |= ETH_RSS_FRAG_IPV6;
6519         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6520                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6522                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6524                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6534                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6535
6536         return rss_hf;
6537 }
6538
6539 /* Disable RSS */
6540 static void
6541 i40e_pf_disable_rss(struct i40e_pf *pf)
6542 {
6543         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6544         uint64_t hena;
6545
6546         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6547         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6548         if (hw->mac.type == I40E_MAC_X722)
6549                 hena &= ~I40E_RSS_HENA_ALL_X722;
6550         else
6551                 hena &= ~I40E_RSS_HENA_ALL;
6552         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6553         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6554         I40E_WRITE_FLUSH(hw);
6555 }
6556
6557 static int
6558 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6559 {
6560         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6561         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6562         int ret = 0;
6563
6564         if (!key || key_len == 0) {
6565                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6566                 return 0;
6567         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6568                 sizeof(uint32_t)) {
6569                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6570                 return -EINVAL;
6571         }
6572
6573         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6574                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6575                         (struct i40e_aqc_get_set_rss_key_data *)key;
6576
6577                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6578                 if (ret)
6579                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6580         } else {
6581                 uint32_t *hash_key = (uint32_t *)key;
6582                 uint16_t i;
6583
6584                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6585                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6586                 I40E_WRITE_FLUSH(hw);
6587         }
6588
6589         return ret;
6590 }
6591
6592 static int
6593 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6594 {
6595         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6596         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6597         int ret;
6598
6599         if (!key || !key_len)
6600                 return -EINVAL;
6601
6602         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6603                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6604                         (struct i40e_aqc_get_set_rss_key_data *)key);
6605                 if (ret) {
6606                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6607                         return ret;
6608                 }
6609         } else {
6610                 uint32_t *key_dw = (uint32_t *)key;
6611                 uint16_t i;
6612
6613                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6614                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6615         }
6616         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6617
6618         return 0;
6619 }
6620
6621 static int
6622 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6623 {
6624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6625         uint64_t rss_hf;
6626         uint64_t hena;
6627         int ret;
6628
6629         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6630                                rss_conf->rss_key_len);
6631         if (ret)
6632                 return ret;
6633
6634         rss_hf = rss_conf->rss_hf;
6635         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6636         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6637         if (hw->mac.type == I40E_MAC_X722)
6638                 hena &= ~I40E_RSS_HENA_ALL_X722;
6639         else
6640                 hena &= ~I40E_RSS_HENA_ALL;
6641         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6642         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6643         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6644         I40E_WRITE_FLUSH(hw);
6645
6646         return 0;
6647 }
6648
6649 static int
6650 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6651                          struct rte_eth_rss_conf *rss_conf)
6652 {
6653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6656         uint64_t hena;
6657
6658         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6659         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6660         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6661                  ? I40E_RSS_HENA_ALL_X722
6662                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6663                 if (rss_hf != 0) /* Enable RSS */
6664                         return -EINVAL;
6665                 return 0; /* Nothing to do */
6666         }
6667         /* RSS enabled */
6668         if (rss_hf == 0) /* Disable RSS */
6669                 return -EINVAL;
6670
6671         return i40e_hw_rss_hash_set(pf, rss_conf);
6672 }
6673
6674 static int
6675 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6676                            struct rte_eth_rss_conf *rss_conf)
6677 {
6678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680         uint64_t hena;
6681
6682         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6683                          &rss_conf->rss_key_len);
6684
6685         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6686         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6687         rss_conf->rss_hf = i40e_parse_hena(hena);
6688
6689         return 0;
6690 }
6691
6692 static int
6693 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6694 {
6695         switch (filter_type) {
6696         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6697                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6698                 break;
6699         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6700                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6701                 break;
6702         case RTE_TUNNEL_FILTER_IMAC_TENID:
6703                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6704                 break;
6705         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6706                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6707                 break;
6708         case ETH_TUNNEL_FILTER_IMAC:
6709                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6710                 break;
6711         case ETH_TUNNEL_FILTER_OIP:
6712                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6713                 break;
6714         case ETH_TUNNEL_FILTER_IIP:
6715                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6716                 break;
6717         default:
6718                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6719                 return -EINVAL;
6720         }
6721
6722         return 0;
6723 }
6724
6725 /* Convert tunnel filter structure */
6726 static int
6727 i40e_tunnel_filter_convert(
6728         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6729         struct i40e_tunnel_filter *tunnel_filter)
6730 {
6731         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6732                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6733         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6734                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6735         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6736         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6737              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6738             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6739                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6740         else
6741                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6742         tunnel_filter->input.flags = cld_filter->element.flags;
6743         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6744         tunnel_filter->queue = cld_filter->element.queue_number;
6745         rte_memcpy(tunnel_filter->input.general_fields,
6746                    cld_filter->general_fields,
6747                    sizeof(cld_filter->general_fields));
6748
6749         return 0;
6750 }
6751
6752 /* Check if there exists the tunnel filter */
6753 struct i40e_tunnel_filter *
6754 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6755                              const struct i40e_tunnel_filter_input *input)
6756 {
6757         int ret;
6758
6759         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6760         if (ret < 0)
6761                 return NULL;
6762
6763         return tunnel_rule->hash_map[ret];
6764 }
6765
6766 /* Add a tunnel filter into the SW list */
6767 static int
6768 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6769                              struct i40e_tunnel_filter *tunnel_filter)
6770 {
6771         struct i40e_tunnel_rule *rule = &pf->tunnel;
6772         int ret;
6773
6774         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6775         if (ret < 0) {
6776                 PMD_DRV_LOG(ERR,
6777                             "Failed to insert tunnel filter to hash table %d!",
6778                             ret);
6779                 return ret;
6780         }
6781         rule->hash_map[ret] = tunnel_filter;
6782
6783         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6784
6785         return 0;
6786 }
6787
6788 /* Delete a tunnel filter from the SW list */
6789 int
6790 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6791                           struct i40e_tunnel_filter_input *input)
6792 {
6793         struct i40e_tunnel_rule *rule = &pf->tunnel;
6794         struct i40e_tunnel_filter *tunnel_filter;
6795         int ret;
6796
6797         ret = rte_hash_del_key(rule->hash_table, input);
6798         if (ret < 0) {
6799                 PMD_DRV_LOG(ERR,
6800                             "Failed to delete tunnel filter to hash table %d!",
6801                             ret);
6802                 return ret;
6803         }
6804         tunnel_filter = rule->hash_map[ret];
6805         rule->hash_map[ret] = NULL;
6806
6807         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6808         rte_free(tunnel_filter);
6809
6810         return 0;
6811 }
6812
6813 int
6814 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6815                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6816                         uint8_t add)
6817 {
6818         uint16_t ip_type;
6819         uint32_t ipv4_addr;
6820         uint8_t i, tun_type = 0;
6821         /* internal varialbe to convert ipv6 byte order */
6822         uint32_t convert_ipv6[4];
6823         int val, ret = 0;
6824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6825         struct i40e_vsi *vsi = pf->main_vsi;
6826         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6827         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6828         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6829         struct i40e_tunnel_filter *tunnel, *node;
6830         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6831
6832         cld_filter = rte_zmalloc("tunnel_filter",
6833                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6834         0);
6835
6836         if (NULL == cld_filter) {
6837                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6838                 return -ENOMEM;
6839         }
6840         pfilter = cld_filter;
6841
6842         ether_addr_copy(&tunnel_filter->outer_mac,
6843                         (struct ether_addr *)&pfilter->element.outer_mac);
6844         ether_addr_copy(&tunnel_filter->inner_mac,
6845                         (struct ether_addr *)&pfilter->element.inner_mac);
6846
6847         pfilter->element.inner_vlan =
6848                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6849         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6850                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6851                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6852                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6853                                 &rte_cpu_to_le_32(ipv4_addr),
6854                                 sizeof(pfilter->element.ipaddr.v4.data));
6855         } else {
6856                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6857                 for (i = 0; i < 4; i++) {
6858                         convert_ipv6[i] =
6859                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6860                 }
6861                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6862                            &convert_ipv6,
6863                            sizeof(pfilter->element.ipaddr.v6.data));
6864         }
6865
6866         /* check tunneled type */
6867         switch (tunnel_filter->tunnel_type) {
6868         case RTE_TUNNEL_TYPE_VXLAN:
6869                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6870                 break;
6871         case RTE_TUNNEL_TYPE_NVGRE:
6872                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6873                 break;
6874         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6875                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6876                 break;
6877         default:
6878                 /* Other tunnel types is not supported. */
6879                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6880                 rte_free(cld_filter);
6881                 return -EINVAL;
6882         }
6883
6884         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6885                                        &pfilter->element.flags);
6886         if (val < 0) {
6887                 rte_free(cld_filter);
6888                 return -EINVAL;
6889         }
6890
6891         pfilter->element.flags |= rte_cpu_to_le_16(
6892                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6893                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6894         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6895         pfilter->element.queue_number =
6896                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6897
6898         /* Check if there is the filter in SW list */
6899         memset(&check_filter, 0, sizeof(check_filter));
6900         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6901         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6902         if (add && node) {
6903                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6904                 return -EINVAL;
6905         }
6906
6907         if (!add && !node) {
6908                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6909                 return -EINVAL;
6910         }
6911
6912         if (add) {
6913                 ret = i40e_aq_add_cloud_filters(hw,
6914                                         vsi->seid, &cld_filter->element, 1);
6915                 if (ret < 0) {
6916                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6917                         return -ENOTSUP;
6918                 }
6919                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6920                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6921                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6922         } else {
6923                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6924                                                    &cld_filter->element, 1);
6925                 if (ret < 0) {
6926                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6927                         return -ENOTSUP;
6928                 }
6929                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6930         }
6931
6932         rte_free(cld_filter);
6933         return ret;
6934 }
6935
6936 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6937 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6938 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6939 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6940 #define I40E_TR_GRE_KEY_MASK                    0x400
6941 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6942 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6943
6944 static enum
6945 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6946 {
6947         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6948         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6949         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6950         enum i40e_status_code status = I40E_SUCCESS;
6951
6952         memset(&filter_replace, 0,
6953                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6954         memset(&filter_replace_buf, 0,
6955                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6956
6957         /* create L1 filter */
6958         filter_replace.old_filter_type =
6959                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6960         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6961         filter_replace.tr_bit = 0;
6962
6963         /* Prepare the buffer, 3 entries */
6964         filter_replace_buf.data[0] =
6965                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6966         filter_replace_buf.data[0] |=
6967                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6968         filter_replace_buf.data[2] = 0xFF;
6969         filter_replace_buf.data[3] = 0xFF;
6970         filter_replace_buf.data[4] =
6971                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6972         filter_replace_buf.data[4] |=
6973                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6974         filter_replace_buf.data[7] = 0xF0;
6975         filter_replace_buf.data[8]
6976                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6977         filter_replace_buf.data[8] |=
6978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6979         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6980                 I40E_TR_GENEVE_KEY_MASK |
6981                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6982         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6983                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6984                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6985
6986         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6987                                                &filter_replace_buf);
6988         return status;
6989 }
6990
6991 static enum
6992 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6993 {
6994         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6995         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6997         enum i40e_status_code status = I40E_SUCCESS;
6998
6999         /* For MPLSoUDP */
7000         memset(&filter_replace, 0,
7001                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7002         memset(&filter_replace_buf, 0,
7003                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7004         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7005                 I40E_AQC_MIRROR_CLOUD_FILTER;
7006         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7007         filter_replace.new_filter_type =
7008                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7009         /* Prepare the buffer, 2 entries */
7010         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7011         filter_replace_buf.data[0] |=
7012                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7013         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7014         filter_replace_buf.data[4] |=
7015                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7016         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7017                                                &filter_replace_buf);
7018         if (status < 0)
7019                 return status;
7020
7021         /* For MPLSoGRE */
7022         memset(&filter_replace, 0,
7023                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7024         memset(&filter_replace_buf, 0,
7025                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7026
7027         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7028                 I40E_AQC_MIRROR_CLOUD_FILTER;
7029         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7030         filter_replace.new_filter_type =
7031                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7032         /* Prepare the buffer, 2 entries */
7033         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7034         filter_replace_buf.data[0] |=
7035                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7036         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7037         filter_replace_buf.data[4] |=
7038                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7039
7040         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7041                                                &filter_replace_buf);
7042         return status;
7043 }
7044
7045 int
7046 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7047                       struct i40e_tunnel_filter_conf *tunnel_filter,
7048                       uint8_t add)
7049 {
7050         uint16_t ip_type;
7051         uint32_t ipv4_addr;
7052         uint8_t i, tun_type = 0;
7053         /* internal variable to convert ipv6 byte order */
7054         uint32_t convert_ipv6[4];
7055         int val, ret = 0;
7056         struct i40e_pf_vf *vf = NULL;
7057         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7058         struct i40e_vsi *vsi;
7059         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7060         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7061         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7062         struct i40e_tunnel_filter *tunnel, *node;
7063         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7064         uint32_t teid_le;
7065         bool big_buffer = 0;
7066
7067         cld_filter = rte_zmalloc("tunnel_filter",
7068                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7069                          0);
7070
7071         if (cld_filter == NULL) {
7072                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7073                 return -ENOMEM;
7074         }
7075         pfilter = cld_filter;
7076
7077         ether_addr_copy(&tunnel_filter->outer_mac,
7078                         (struct ether_addr *)&pfilter->element.outer_mac);
7079         ether_addr_copy(&tunnel_filter->inner_mac,
7080                         (struct ether_addr *)&pfilter->element.inner_mac);
7081
7082         pfilter->element.inner_vlan =
7083                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7084         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7085                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7086                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7087                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7088                                 &rte_cpu_to_le_32(ipv4_addr),
7089                                 sizeof(pfilter->element.ipaddr.v4.data));
7090         } else {
7091                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7092                 for (i = 0; i < 4; i++) {
7093                         convert_ipv6[i] =
7094                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7095                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7096                 }
7097                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7098                            &convert_ipv6,
7099                            sizeof(pfilter->element.ipaddr.v6.data));
7100         }
7101
7102         /* check tunneled type */
7103         switch (tunnel_filter->tunnel_type) {
7104         case I40E_TUNNEL_TYPE_VXLAN:
7105                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7106                 break;
7107         case I40E_TUNNEL_TYPE_NVGRE:
7108                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7109                 break;
7110         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7111                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7112                 break;
7113         case I40E_TUNNEL_TYPE_MPLSoUDP:
7114                 if (!pf->mpls_replace_flag) {
7115                         i40e_replace_mpls_l1_filter(pf);
7116                         i40e_replace_mpls_cloud_filter(pf);
7117                         pf->mpls_replace_flag = 1;
7118                 }
7119                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7120                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7121                         teid_le >> 4;
7122                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7123                         (teid_le & 0xF) << 12;
7124                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7125                         0x40;
7126                 big_buffer = 1;
7127                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7128                 break;
7129         case I40E_TUNNEL_TYPE_MPLSoGRE:
7130                 if (!pf->mpls_replace_flag) {
7131                         i40e_replace_mpls_l1_filter(pf);
7132                         i40e_replace_mpls_cloud_filter(pf);
7133                         pf->mpls_replace_flag = 1;
7134                 }
7135                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7136                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7137                         teid_le >> 4;
7138                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7139                         (teid_le & 0xF) << 12;
7140                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7141                         0x0;
7142                 big_buffer = 1;
7143                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7144                 break;
7145         case I40E_TUNNEL_TYPE_QINQ:
7146                 if (!pf->qinq_replace_flag) {
7147                         ret = i40e_cloud_filter_qinq_create(pf);
7148                         if (ret < 0)
7149                                 PMD_DRV_LOG(ERR,
7150                                         "Failed to create a qinq tunnel filter.");
7151                         pf->qinq_replace_flag = 1;
7152                 }
7153                 /*      Add in the General fields the values of
7154                  *      the Outer and Inner VLAN
7155                  *      Big Buffer should be set, see changes in
7156                  *      i40e_aq_add_cloud_filters
7157                  */
7158                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7159                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7160                 big_buffer = 1;
7161                 break;
7162         default:
7163                 /* Other tunnel types is not supported. */
7164                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7165                 rte_free(cld_filter);
7166                 return -EINVAL;
7167         }
7168
7169         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7170                 pfilter->element.flags =
7171                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7172         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7173                 pfilter->element.flags =
7174                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7175         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7176                 pfilter->element.flags |=
7177                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7178         else {
7179                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7180                                                 &pfilter->element.flags);
7181                 if (val < 0) {
7182                         rte_free(cld_filter);
7183                         return -EINVAL;
7184                 }
7185         }
7186
7187         pfilter->element.flags |= rte_cpu_to_le_16(
7188                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7189                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7190         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7191         pfilter->element.queue_number =
7192                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7193
7194         if (!tunnel_filter->is_to_vf)
7195                 vsi = pf->main_vsi;
7196         else {
7197                 if (tunnel_filter->vf_id >= pf->vf_num) {
7198                         PMD_DRV_LOG(ERR, "Invalid argument.");
7199                         return -EINVAL;
7200                 }
7201                 vf = &pf->vfs[tunnel_filter->vf_id];
7202                 vsi = vf->vsi;
7203         }
7204
7205         /* Check if there is the filter in SW list */
7206         memset(&check_filter, 0, sizeof(check_filter));
7207         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7208         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7209         check_filter.vf_id = tunnel_filter->vf_id;
7210         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7211         if (add && node) {
7212                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7213                 return -EINVAL;
7214         }
7215
7216         if (!add && !node) {
7217                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7218                 return -EINVAL;
7219         }
7220
7221         if (add) {
7222                 if (big_buffer)
7223                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7224                                                    vsi->seid, cld_filter, 1);
7225                 else
7226                         ret = i40e_aq_add_cloud_filters(hw,
7227                                         vsi->seid, &cld_filter->element, 1);
7228                 if (ret < 0) {
7229                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7230                         return -ENOTSUP;
7231                 }
7232                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7233                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7234                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7235         } else {
7236                 if (big_buffer)
7237                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7238                                 hw, vsi->seid, cld_filter, 1);
7239                 else
7240                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7241                                                    &cld_filter->element, 1);
7242                 if (ret < 0) {
7243                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7244                         return -ENOTSUP;
7245                 }
7246                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7247         }
7248
7249         rte_free(cld_filter);
7250         return ret;
7251 }
7252
7253 static int
7254 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7255 {
7256         uint8_t i;
7257
7258         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7259                 if (pf->vxlan_ports[i] == port)
7260                         return i;
7261         }
7262
7263         return -1;
7264 }
7265
7266 static int
7267 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7268 {
7269         int  idx, ret;
7270         uint8_t filter_idx;
7271         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7272
7273         idx = i40e_get_vxlan_port_idx(pf, port);
7274
7275         /* Check if port already exists */
7276         if (idx >= 0) {
7277                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7278                 return -EINVAL;
7279         }
7280
7281         /* Now check if there is space to add the new port */
7282         idx = i40e_get_vxlan_port_idx(pf, 0);
7283         if (idx < 0) {
7284                 PMD_DRV_LOG(ERR,
7285                         "Maximum number of UDP ports reached, not adding port %d",
7286                         port);
7287                 return -ENOSPC;
7288         }
7289
7290         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7291                                         &filter_idx, NULL);
7292         if (ret < 0) {
7293                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7294                 return -1;
7295         }
7296
7297         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7298                          port,  filter_idx);
7299
7300         /* New port: add it and mark its index in the bitmap */
7301         pf->vxlan_ports[idx] = port;
7302         pf->vxlan_bitmap |= (1 << idx);
7303
7304         if (!(pf->flags & I40E_FLAG_VXLAN))
7305                 pf->flags |= I40E_FLAG_VXLAN;
7306
7307         return 0;
7308 }
7309
7310 static int
7311 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7312 {
7313         int idx;
7314         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7315
7316         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7317                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7318                 return -EINVAL;
7319         }
7320
7321         idx = i40e_get_vxlan_port_idx(pf, port);
7322
7323         if (idx < 0) {
7324                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7325                 return -EINVAL;
7326         }
7327
7328         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7329                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7330                 return -1;
7331         }
7332
7333         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7334                         port, idx);
7335
7336         pf->vxlan_ports[idx] = 0;
7337         pf->vxlan_bitmap &= ~(1 << idx);
7338
7339         if (!pf->vxlan_bitmap)
7340                 pf->flags &= ~I40E_FLAG_VXLAN;
7341
7342         return 0;
7343 }
7344
7345 /* Add UDP tunneling port */
7346 static int
7347 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7348                              struct rte_eth_udp_tunnel *udp_tunnel)
7349 {
7350         int ret = 0;
7351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7352
7353         if (udp_tunnel == NULL)
7354                 return -EINVAL;
7355
7356         switch (udp_tunnel->prot_type) {
7357         case RTE_TUNNEL_TYPE_VXLAN:
7358                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7359                 break;
7360
7361         case RTE_TUNNEL_TYPE_GENEVE:
7362         case RTE_TUNNEL_TYPE_TEREDO:
7363                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7364                 ret = -1;
7365                 break;
7366
7367         default:
7368                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7369                 ret = -1;
7370                 break;
7371         }
7372
7373         return ret;
7374 }
7375
7376 /* Remove UDP tunneling port */
7377 static int
7378 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7379                              struct rte_eth_udp_tunnel *udp_tunnel)
7380 {
7381         int ret = 0;
7382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7383
7384         if (udp_tunnel == NULL)
7385                 return -EINVAL;
7386
7387         switch (udp_tunnel->prot_type) {
7388         case RTE_TUNNEL_TYPE_VXLAN:
7389                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7390                 break;
7391         case RTE_TUNNEL_TYPE_GENEVE:
7392         case RTE_TUNNEL_TYPE_TEREDO:
7393                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7394                 ret = -1;
7395                 break;
7396         default:
7397                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7398                 ret = -1;
7399                 break;
7400         }
7401
7402         return ret;
7403 }
7404
7405 /* Calculate the maximum number of contiguous PF queues that are configured */
7406 static int
7407 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7408 {
7409         struct rte_eth_dev_data *data = pf->dev_data;
7410         int i, num;
7411         struct i40e_rx_queue *rxq;
7412
7413         num = 0;
7414         for (i = 0; i < pf->lan_nb_qps; i++) {
7415                 rxq = data->rx_queues[i];
7416                 if (rxq && rxq->q_set)
7417                         num++;
7418                 else
7419                         break;
7420         }
7421
7422         return num;
7423 }
7424
7425 /* Configure RSS */
7426 static int
7427 i40e_pf_config_rss(struct i40e_pf *pf)
7428 {
7429         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7430         struct rte_eth_rss_conf rss_conf;
7431         uint32_t i, lut = 0;
7432         uint16_t j, num;
7433
7434         /*
7435          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7436          * It's necessary to calulate the actual PF queues that are configured.
7437          */
7438         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7439                 num = i40e_pf_calc_configured_queues_num(pf);
7440         else
7441                 num = pf->dev_data->nb_rx_queues;
7442
7443         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7444         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7445                         num);
7446
7447         if (num == 0) {
7448                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7449                 return -ENOTSUP;
7450         }
7451
7452         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7453                 if (j == num)
7454                         j = 0;
7455                 lut = (lut << 8) | (j & ((0x1 <<
7456                         hw->func_caps.rss_table_entry_width) - 1));
7457                 if ((i & 3) == 3)
7458                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7459         }
7460
7461         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7462         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7463                 i40e_pf_disable_rss(pf);
7464                 return 0;
7465         }
7466         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7467                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7468                 /* Random default keys */
7469                 static uint32_t rss_key_default[] = {0x6b793944,
7470                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7471                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7472                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7473
7474                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7475                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7476                                                         sizeof(uint32_t);
7477         }
7478
7479         return i40e_hw_rss_hash_set(pf, &rss_conf);
7480 }
7481
7482 static int
7483 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7484                                struct rte_eth_tunnel_filter_conf *filter)
7485 {
7486         if (pf == NULL || filter == NULL) {
7487                 PMD_DRV_LOG(ERR, "Invalid parameter");
7488                 return -EINVAL;
7489         }
7490
7491         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7492                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7493                 return -EINVAL;
7494         }
7495
7496         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7497                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7498                 return -EINVAL;
7499         }
7500
7501         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7502                 (is_zero_ether_addr(&filter->outer_mac))) {
7503                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7504                 return -EINVAL;
7505         }
7506
7507         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7508                 (is_zero_ether_addr(&filter->inner_mac))) {
7509                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7510                 return -EINVAL;
7511         }
7512
7513         return 0;
7514 }
7515
7516 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7517 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7518 static int
7519 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7520 {
7521         uint32_t val, reg;
7522         int ret = -EINVAL;
7523
7524         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7525         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7526
7527         if (len == 3) {
7528                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7529         } else if (len == 4) {
7530                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7531         } else {
7532                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7533                 return ret;
7534         }
7535
7536         if (reg != val) {
7537                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7538                                                    reg, NULL);
7539                 if (ret != 0)
7540                         return ret;
7541         } else {
7542                 ret = 0;
7543         }
7544         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7545                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7546
7547         return ret;
7548 }
7549
7550 static int
7551 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7552 {
7553         int ret = -EINVAL;
7554
7555         if (!hw || !cfg)
7556                 return -EINVAL;
7557
7558         switch (cfg->cfg_type) {
7559         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7560                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7561                 break;
7562         default:
7563                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7564                 break;
7565         }
7566
7567         return ret;
7568 }
7569
7570 static int
7571 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7572                                enum rte_filter_op filter_op,
7573                                void *arg)
7574 {
7575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7576         int ret = I40E_ERR_PARAM;
7577
7578         switch (filter_op) {
7579         case RTE_ETH_FILTER_SET:
7580                 ret = i40e_dev_global_config_set(hw,
7581                         (struct rte_eth_global_cfg *)arg);
7582                 break;
7583         default:
7584                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7585                 break;
7586         }
7587
7588         return ret;
7589 }
7590
7591 static int
7592 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7593                           enum rte_filter_op filter_op,
7594                           void *arg)
7595 {
7596         struct rte_eth_tunnel_filter_conf *filter;
7597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7598         int ret = I40E_SUCCESS;
7599
7600         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7601
7602         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7603                 return I40E_ERR_PARAM;
7604
7605         switch (filter_op) {
7606         case RTE_ETH_FILTER_NOP:
7607                 if (!(pf->flags & I40E_FLAG_VXLAN))
7608                         ret = I40E_NOT_SUPPORTED;
7609                 break;
7610         case RTE_ETH_FILTER_ADD:
7611                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7612                 break;
7613         case RTE_ETH_FILTER_DELETE:
7614                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7615                 break;
7616         default:
7617                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7618                 ret = I40E_ERR_PARAM;
7619                 break;
7620         }
7621
7622         return ret;
7623 }
7624
7625 static int
7626 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7627 {
7628         int ret = 0;
7629         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7630
7631         /* RSS setup */
7632         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7633                 ret = i40e_pf_config_rss(pf);
7634         else
7635                 i40e_pf_disable_rss(pf);
7636
7637         return ret;
7638 }
7639
7640 /* Get the symmetric hash enable configurations per port */
7641 static void
7642 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7643 {
7644         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7645
7646         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7647 }
7648
7649 /* Set the symmetric hash enable configurations per port */
7650 static void
7651 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7652 {
7653         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7654
7655         if (enable > 0) {
7656                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7657                         PMD_DRV_LOG(INFO,
7658                                 "Symmetric hash has already been enabled");
7659                         return;
7660                 }
7661                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7662         } else {
7663                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7664                         PMD_DRV_LOG(INFO,
7665                                 "Symmetric hash has already been disabled");
7666                         return;
7667                 }
7668                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7669         }
7670         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7671         I40E_WRITE_FLUSH(hw);
7672 }
7673
7674 /*
7675  * Get global configurations of hash function type and symmetric hash enable
7676  * per flow type (pctype). Note that global configuration means it affects all
7677  * the ports on the same NIC.
7678  */
7679 static int
7680 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7681                                    struct rte_eth_hash_global_conf *g_cfg)
7682 {
7683         uint32_t reg, mask = I40E_FLOW_TYPES;
7684         uint16_t i;
7685         enum i40e_filter_pctype pctype;
7686
7687         memset(g_cfg, 0, sizeof(*g_cfg));
7688         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7689         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7690                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7691         else
7692                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7693         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7694                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7695
7696         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7697                 if (!(mask & (1UL << i)))
7698                         continue;
7699                 mask &= ~(1UL << i);
7700                 /* Bit set indicats the coresponding flow type is supported */
7701                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7702                 /* if flowtype is invalid, continue */
7703                 if (!I40E_VALID_FLOW(i))
7704                         continue;
7705                 pctype = i40e_flowtype_to_pctype(i);
7706                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7707                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7708                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7709         }
7710
7711         return 0;
7712 }
7713
7714 static int
7715 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7716 {
7717         uint32_t i;
7718         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7719
7720         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7721                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7722                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7723                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7724                                                 g_cfg->hash_func);
7725                 return -EINVAL;
7726         }
7727
7728         /*
7729          * As i40e supports less than 32 flow types, only first 32 bits need to
7730          * be checked.
7731          */
7732         mask0 = g_cfg->valid_bit_mask[0];
7733         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7734                 if (i == 0) {
7735                         /* Check if any unsupported flow type configured */
7736                         if ((mask0 | i40e_mask) ^ i40e_mask)
7737                                 goto mask_err;
7738                 } else {
7739                         if (g_cfg->valid_bit_mask[i])
7740                                 goto mask_err;
7741                 }
7742         }
7743
7744         return 0;
7745
7746 mask_err:
7747         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7748
7749         return -EINVAL;
7750 }
7751
7752 /*
7753  * Set global configurations of hash function type and symmetric hash enable
7754  * per flow type (pctype). Note any modifying global configuration will affect
7755  * all the ports on the same NIC.
7756  */
7757 static int
7758 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7759                                    struct rte_eth_hash_global_conf *g_cfg)
7760 {
7761         int ret;
7762         uint16_t i;
7763         uint32_t reg;
7764         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7765         enum i40e_filter_pctype pctype;
7766
7767         /* Check the input parameters */
7768         ret = i40e_hash_global_config_check(g_cfg);
7769         if (ret < 0)
7770                 return ret;
7771
7772         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7773                 if (!(mask0 & (1UL << i)))
7774                         continue;
7775                 mask0 &= ~(1UL << i);
7776                 /* if flowtype is invalid, continue */
7777                 if (!I40E_VALID_FLOW(i))
7778                         continue;
7779                 pctype = i40e_flowtype_to_pctype(i);
7780                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7781                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7782                 if (hw->mac.type == I40E_MAC_X722) {
7783                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7784                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7785                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7786                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7787                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7788                                   reg);
7789                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7790                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7791                                   reg);
7792                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7793                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7794                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7795                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7796                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7797                                   reg);
7798                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7799                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7800                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7801                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7802                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7803                                   reg);
7804                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7805                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7806                                   reg);
7807                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7808                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7809                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7810                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7811                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7812                                   reg);
7813                         } else {
7814                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7815                                   reg);
7816                         }
7817                 } else {
7818                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7819                 }
7820         }
7821
7822         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7823         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7824                 /* Toeplitz */
7825                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7826                         PMD_DRV_LOG(DEBUG,
7827                                 "Hash function already set to Toeplitz");
7828                         goto out;
7829                 }
7830                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7831         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7832                 /* Simple XOR */
7833                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7834                         PMD_DRV_LOG(DEBUG,
7835                                 "Hash function already set to Simple XOR");
7836                         goto out;
7837                 }
7838                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7839         } else
7840                 /* Use the default, and keep it as it is */
7841                 goto out;
7842
7843         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7844
7845 out:
7846         I40E_WRITE_FLUSH(hw);
7847
7848         return 0;
7849 }
7850
7851 /**
7852  * Valid input sets for hash and flow director filters per PCTYPE
7853  */
7854 static uint64_t
7855 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7856                 enum rte_filter_type filter)
7857 {
7858         uint64_t valid;
7859
7860         static const uint64_t valid_hash_inset_table[] = {
7861                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7862                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7863                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7864                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7865                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7866                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7867                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7868                         I40E_INSET_FLEX_PAYLOAD,
7869                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7870                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7871                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7872                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7873                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7874                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7875                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7876                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7877                         I40E_INSET_FLEX_PAYLOAD,
7878                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7879                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7880                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7881                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7882                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7883                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7884                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7885                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7886                         I40E_INSET_FLEX_PAYLOAD,
7887                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7888                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7889                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7890                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7891                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7892                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7893                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7894                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7895                         I40E_INSET_FLEX_PAYLOAD,
7896                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7897                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7898                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7899                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7900                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7901                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7902                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7903                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7904                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7905                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7906                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7907                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7908                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7909                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7910                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7911                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7912                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7913                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7914                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7915                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7916                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7917                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7918                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7919                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7920                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7921                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7922                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7923                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7924                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7925                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7926                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7927                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7928                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7929                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7930                         I40E_INSET_FLEX_PAYLOAD,
7931                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7932                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7933                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7934                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7935                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7936                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7937                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7938                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7939                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7940                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7941                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7942                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7943                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7944                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7945                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7946                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7947                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7948                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7949                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7950                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7951                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7952                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7953                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7954                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7955                         I40E_INSET_FLEX_PAYLOAD,
7956                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7957                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7958                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7959                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7960                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7961                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7962                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7963                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7964                         I40E_INSET_FLEX_PAYLOAD,
7965                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7966                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7967                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7968                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7969                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7970                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7971                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7972                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7973                         I40E_INSET_FLEX_PAYLOAD,
7974                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7975                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7976                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7977                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7978                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7979                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7980                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7981                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7982                         I40E_INSET_FLEX_PAYLOAD,
7983                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7984                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7985                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7986                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7987                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7988                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7989                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7990                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7991                         I40E_INSET_FLEX_PAYLOAD,
7992                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7993                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7994                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7995                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7996                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7997                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7998                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7999                         I40E_INSET_FLEX_PAYLOAD,
8000                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8001                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8002                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8003                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8004                         I40E_INSET_FLEX_PAYLOAD,
8005         };
8006
8007         /**
8008          * Flow director supports only fields defined in
8009          * union rte_eth_fdir_flow.
8010          */
8011         static const uint64_t valid_fdir_inset_table[] = {
8012                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8013                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8015                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8016                 I40E_INSET_IPV4_TTL,
8017                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8018                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8020                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8021                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8022                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8023                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8024                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8026                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8027                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8028                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8030                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8031                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8032                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8033                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8034                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8035                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8036                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8038                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8040                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8041                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8042                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8043                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8044                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8045                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8046                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8047                 I40E_INSET_SCTP_VT,
8048                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8049                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8051                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8052                 I40E_INSET_IPV4_TTL,
8053                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8054                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8055                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8056                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8057                 I40E_INSET_IPV6_HOP_LIMIT,
8058                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8059                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8060                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8061                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8062                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8063                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8064                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8065                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8066                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8067                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8068                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8069                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8070                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8071                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8072                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8073                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8074                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8076                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8077                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8078                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8079                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8080                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8081                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8082                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8083                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8084                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8085                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8086                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8087                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8088                 I40E_INSET_SCTP_VT,
8089                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8090                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8092                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8093                 I40E_INSET_IPV6_HOP_LIMIT,
8094                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8095                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8096                 I40E_INSET_LAST_ETHER_TYPE,
8097         };
8098
8099         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8100                 return 0;
8101         if (filter == RTE_ETH_FILTER_HASH)
8102                 valid = valid_hash_inset_table[pctype];
8103         else
8104                 valid = valid_fdir_inset_table[pctype];
8105
8106         return valid;
8107 }
8108
8109 /**
8110  * Validate if the input set is allowed for a specific PCTYPE
8111  */
8112 static int
8113 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8114                 enum rte_filter_type filter, uint64_t inset)
8115 {
8116         uint64_t valid;
8117
8118         valid = i40e_get_valid_input_set(pctype, filter);
8119         if (inset & (~valid))
8120                 return -EINVAL;
8121
8122         return 0;
8123 }
8124
8125 /* default input set fields combination per pctype */
8126 uint64_t
8127 i40e_get_default_input_set(uint16_t pctype)
8128 {
8129         static const uint64_t default_inset_table[] = {
8130                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8131                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8133                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8138                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8142                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8144                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8145                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8148                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8150                         I40E_INSET_SCTP_VT,
8151                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8152                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8153                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8154                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8155                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8156                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8158                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8159                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8162                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8163                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8164                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8165                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8168                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8170                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8171                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8172                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8173                         I40E_INSET_SCTP_VT,
8174                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8175                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8176                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8177                         I40E_INSET_LAST_ETHER_TYPE,
8178         };
8179
8180         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8181                 return 0;
8182
8183         return default_inset_table[pctype];
8184 }
8185
8186 /**
8187  * Parse the input set from index to logical bit masks
8188  */
8189 static int
8190 i40e_parse_input_set(uint64_t *inset,
8191                      enum i40e_filter_pctype pctype,
8192                      enum rte_eth_input_set_field *field,
8193                      uint16_t size)
8194 {
8195         uint16_t i, j;
8196         int ret = -EINVAL;
8197
8198         static const struct {
8199                 enum rte_eth_input_set_field field;
8200                 uint64_t inset;
8201         } inset_convert_table[] = {
8202                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8203                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8204                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8205                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8206                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8207                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8208                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8209                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8210                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8211                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8212                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8213                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8214                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8215                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8216                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8217                         I40E_INSET_IPV6_NEXT_HDR},
8218                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8219                         I40E_INSET_IPV6_HOP_LIMIT},
8220                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8221                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8222                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8223                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8224                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8225                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8226                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8227                         I40E_INSET_SCTP_VT},
8228                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8229                         I40E_INSET_TUNNEL_DMAC},
8230                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8231                         I40E_INSET_VLAN_TUNNEL},
8232                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8233                         I40E_INSET_TUNNEL_ID},
8234                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8235                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8236                         I40E_INSET_FLEX_PAYLOAD_W1},
8237                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8238                         I40E_INSET_FLEX_PAYLOAD_W2},
8239                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8240                         I40E_INSET_FLEX_PAYLOAD_W3},
8241                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8242                         I40E_INSET_FLEX_PAYLOAD_W4},
8243                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8244                         I40E_INSET_FLEX_PAYLOAD_W5},
8245                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8246                         I40E_INSET_FLEX_PAYLOAD_W6},
8247                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8248                         I40E_INSET_FLEX_PAYLOAD_W7},
8249                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8250                         I40E_INSET_FLEX_PAYLOAD_W8},
8251         };
8252
8253         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8254                 return ret;
8255
8256         /* Only one item allowed for default or all */
8257         if (size == 1) {
8258                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8259                         *inset = i40e_get_default_input_set(pctype);
8260                         return 0;
8261                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8262                         *inset = I40E_INSET_NONE;
8263                         return 0;
8264                 }
8265         }
8266
8267         for (i = 0, *inset = 0; i < size; i++) {
8268                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8269                         if (field[i] == inset_convert_table[j].field) {
8270                                 *inset |= inset_convert_table[j].inset;
8271                                 break;
8272                         }
8273                 }
8274
8275                 /* It contains unsupported input set, return immediately */
8276                 if (j == RTE_DIM(inset_convert_table))
8277                         return ret;
8278         }
8279
8280         return 0;
8281 }
8282
8283 /**
8284  * Translate the input set from bit masks to register aware bit masks
8285  * and vice versa
8286  */
8287 static uint64_t
8288 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8289 {
8290         uint64_t val = 0;
8291         uint16_t i;
8292
8293         struct inset_map {
8294                 uint64_t inset;
8295                 uint64_t inset_reg;
8296         };
8297
8298         static const struct inset_map inset_map_common[] = {
8299                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8300                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8301                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8302                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8303                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8304                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8305                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8306                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8307                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8308                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8309                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8310                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8311                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8312                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8313                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8314                 {I40E_INSET_TUNNEL_DMAC,
8315                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8316                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8317                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8318                 {I40E_INSET_TUNNEL_SRC_PORT,
8319                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8320                 {I40E_INSET_TUNNEL_DST_PORT,
8321                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8322                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8323                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8324                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8325                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8326                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8327                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8328                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8329                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8330                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8331         };
8332
8333     /* some different registers map in x722*/
8334         static const struct inset_map inset_map_diff_x722[] = {
8335                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8336                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8337                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8338                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8339         };
8340
8341         static const struct inset_map inset_map_diff_not_x722[] = {
8342                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8343                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8344                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8345                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8346         };
8347
8348         if (input == 0)
8349                 return val;
8350
8351         /* Translate input set to register aware inset */
8352         if (type == I40E_MAC_X722) {
8353                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8354                         if (input & inset_map_diff_x722[i].inset)
8355                                 val |= inset_map_diff_x722[i].inset_reg;
8356                 }
8357         } else {
8358                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8359                         if (input & inset_map_diff_not_x722[i].inset)
8360                                 val |= inset_map_diff_not_x722[i].inset_reg;
8361                 }
8362         }
8363
8364         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8365                 if (input & inset_map_common[i].inset)
8366                         val |= inset_map_common[i].inset_reg;
8367         }
8368
8369         return val;
8370 }
8371
8372 static int
8373 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8374 {
8375         uint8_t i, idx = 0;
8376         uint64_t inset_need_mask = inset;
8377
8378         static const struct {
8379                 uint64_t inset;
8380                 uint32_t mask;
8381         } inset_mask_map[] = {
8382                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8383                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8384                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8385                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8386                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8387                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8388                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8389                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8390         };
8391
8392         if (!inset || !mask || !nb_elem)
8393                 return 0;
8394
8395         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8396                 /* Clear the inset bit, if no MASK is required,
8397                  * for example proto + ttl
8398                  */
8399                 if ((inset & inset_mask_map[i].inset) ==
8400                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8401                         inset_need_mask &= ~inset_mask_map[i].inset;
8402                 if (!inset_need_mask)
8403                         return 0;
8404         }
8405         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8406                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8407                     inset_mask_map[i].inset) {
8408                         if (idx >= nb_elem) {
8409                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8410                                 return -EINVAL;
8411                         }
8412                         mask[idx] = inset_mask_map[i].mask;
8413                         idx++;
8414                 }
8415         }
8416
8417         return idx;
8418 }
8419
8420 static void
8421 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8422 {
8423         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8424
8425         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8426         if (reg != val)
8427                 i40e_write_rx_ctl(hw, addr, val);
8428         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8429                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8430 }
8431
8432 static void
8433 i40e_filter_input_set_init(struct i40e_pf *pf)
8434 {
8435         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8436         enum i40e_filter_pctype pctype;
8437         uint64_t input_set, inset_reg;
8438         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8439         int num, i;
8440
8441         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8442              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8443                 if (hw->mac.type == I40E_MAC_X722) {
8444                         if (!I40E_VALID_PCTYPE_X722(pctype))
8445                                 continue;
8446                 } else {
8447                         if (!I40E_VALID_PCTYPE(pctype))
8448                                 continue;
8449                 }
8450
8451                 input_set = i40e_get_default_input_set(pctype);
8452
8453                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8454                                                    I40E_INSET_MASK_NUM_REG);
8455                 if (num < 0)
8456                         return;
8457                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8458                                         input_set);
8459
8460                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8461                                       (uint32_t)(inset_reg & UINT32_MAX));
8462                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8463                                      (uint32_t)((inset_reg >>
8464                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8465                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8466                                       (uint32_t)(inset_reg & UINT32_MAX));
8467                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8468                                      (uint32_t)((inset_reg >>
8469                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8470
8471                 for (i = 0; i < num; i++) {
8472                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8473                                              mask_reg[i]);
8474                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8475                                              mask_reg[i]);
8476                 }
8477                 /*clear unused mask registers of the pctype */
8478                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8479                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8480                                              0);
8481                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8482                                              0);
8483                 }
8484                 I40E_WRITE_FLUSH(hw);
8485
8486                 /* store the default input set */
8487                 pf->hash_input_set[pctype] = input_set;
8488                 pf->fdir.input_set[pctype] = input_set;
8489         }
8490 }
8491
8492 int
8493 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8494                          struct rte_eth_input_set_conf *conf)
8495 {
8496         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8497         enum i40e_filter_pctype pctype;
8498         uint64_t input_set, inset_reg = 0;
8499         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8500         int ret, i, num;
8501
8502         if (!conf) {
8503                 PMD_DRV_LOG(ERR, "Invalid pointer");
8504                 return -EFAULT;
8505         }
8506         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8507             conf->op != RTE_ETH_INPUT_SET_ADD) {
8508                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8509                 return -EINVAL;
8510         }
8511
8512         if (!I40E_VALID_FLOW(conf->flow_type)) {
8513                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8514                 return -EINVAL;
8515         }
8516
8517         if (hw->mac.type == I40E_MAC_X722) {
8518                 /* get translated pctype value in fd pctype register */
8519                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8520                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8521                         conf->flow_type)));
8522         } else
8523                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8524
8525         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8526                                    conf->inset_size);
8527         if (ret) {
8528                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8529                 return -EINVAL;
8530         }
8531         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8532                                     input_set) != 0) {
8533                 PMD_DRV_LOG(ERR, "Invalid input set");
8534                 return -EINVAL;
8535         }
8536         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8537                 /* get inset value in register */
8538                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8539                 inset_reg <<= I40E_32_BIT_WIDTH;
8540                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8541                 input_set |= pf->hash_input_set[pctype];
8542         }
8543         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8544                                            I40E_INSET_MASK_NUM_REG);
8545         if (num < 0)
8546                 return -EINVAL;
8547
8548         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8549
8550         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8551                               (uint32_t)(inset_reg & UINT32_MAX));
8552         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8553                              (uint32_t)((inset_reg >>
8554                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8555
8556         for (i = 0; i < num; i++)
8557                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8558                                      mask_reg[i]);
8559         /*clear unused mask registers of the pctype */
8560         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8561                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8562                                      0);
8563         I40E_WRITE_FLUSH(hw);
8564
8565         pf->hash_input_set[pctype] = input_set;
8566         return 0;
8567 }
8568
8569 int
8570 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8571                          struct rte_eth_input_set_conf *conf)
8572 {
8573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8574         enum i40e_filter_pctype pctype;
8575         uint64_t input_set, inset_reg = 0;
8576         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8577         int ret, i, num;
8578
8579         if (!hw || !conf) {
8580                 PMD_DRV_LOG(ERR, "Invalid pointer");
8581                 return -EFAULT;
8582         }
8583         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8584             conf->op != RTE_ETH_INPUT_SET_ADD) {
8585                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8586                 return -EINVAL;
8587         }
8588
8589         if (!I40E_VALID_FLOW(conf->flow_type)) {
8590                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8591                 return -EINVAL;
8592         }
8593
8594         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8595
8596         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8597                                    conf->inset_size);
8598         if (ret) {
8599                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8600                 return -EINVAL;
8601         }
8602         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8603                                     input_set) != 0) {
8604                 PMD_DRV_LOG(ERR, "Invalid input set");
8605                 return -EINVAL;
8606         }
8607
8608         /* get inset value in register */
8609         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8610         inset_reg <<= I40E_32_BIT_WIDTH;
8611         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8612
8613         /* Can not change the inset reg for flex payload for fdir,
8614          * it is done by writing I40E_PRTQF_FD_FLXINSET
8615          * in i40e_set_flex_mask_on_pctype.
8616          */
8617         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8618                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8619         else
8620                 input_set |= pf->fdir.input_set[pctype];
8621         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8622                                            I40E_INSET_MASK_NUM_REG);
8623         if (num < 0)
8624                 return -EINVAL;
8625
8626         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8627
8628         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8629                               (uint32_t)(inset_reg & UINT32_MAX));
8630         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8631                              (uint32_t)((inset_reg >>
8632                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8633
8634         for (i = 0; i < num; i++)
8635                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8636                                      mask_reg[i]);
8637         /*clear unused mask registers of the pctype */
8638         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8639                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8640                                      0);
8641         I40E_WRITE_FLUSH(hw);
8642
8643         pf->fdir.input_set[pctype] = input_set;
8644         return 0;
8645 }
8646
8647 static int
8648 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8649 {
8650         int ret = 0;
8651
8652         if (!hw || !info) {
8653                 PMD_DRV_LOG(ERR, "Invalid pointer");
8654                 return -EFAULT;
8655         }
8656
8657         switch (info->info_type) {
8658         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8659                 i40e_get_symmetric_hash_enable_per_port(hw,
8660                                         &(info->info.enable));
8661                 break;
8662         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8663                 ret = i40e_get_hash_filter_global_config(hw,
8664                                 &(info->info.global_conf));
8665                 break;
8666         default:
8667                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8668                                                         info->info_type);
8669                 ret = -EINVAL;
8670                 break;
8671         }
8672
8673         return ret;
8674 }
8675
8676 static int
8677 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8678 {
8679         int ret = 0;
8680
8681         if (!hw || !info) {
8682                 PMD_DRV_LOG(ERR, "Invalid pointer");
8683                 return -EFAULT;
8684         }
8685
8686         switch (info->info_type) {
8687         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8688                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8689                 break;
8690         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8691                 ret = i40e_set_hash_filter_global_config(hw,
8692                                 &(info->info.global_conf));
8693                 break;
8694         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8695                 ret = i40e_hash_filter_inset_select(hw,
8696                                                &(info->info.input_set_conf));
8697                 break;
8698
8699         default:
8700                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8701                                                         info->info_type);
8702                 ret = -EINVAL;
8703                 break;
8704         }
8705
8706         return ret;
8707 }
8708
8709 /* Operations for hash function */
8710 static int
8711 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8712                       enum rte_filter_op filter_op,
8713                       void *arg)
8714 {
8715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8716         int ret = 0;
8717
8718         switch (filter_op) {
8719         case RTE_ETH_FILTER_NOP:
8720                 break;
8721         case RTE_ETH_FILTER_GET:
8722                 ret = i40e_hash_filter_get(hw,
8723                         (struct rte_eth_hash_filter_info *)arg);
8724                 break;
8725         case RTE_ETH_FILTER_SET:
8726                 ret = i40e_hash_filter_set(hw,
8727                         (struct rte_eth_hash_filter_info *)arg);
8728                 break;
8729         default:
8730                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8731                                                                 filter_op);
8732                 ret = -ENOTSUP;
8733                 break;
8734         }
8735
8736         return ret;
8737 }
8738
8739 /* Convert ethertype filter structure */
8740 static int
8741 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8742                               struct i40e_ethertype_filter *filter)
8743 {
8744         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8745         filter->input.ether_type = input->ether_type;
8746         filter->flags = input->flags;
8747         filter->queue = input->queue;
8748
8749         return 0;
8750 }
8751
8752 /* Check if there exists the ehtertype filter */
8753 struct i40e_ethertype_filter *
8754 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8755                                 const struct i40e_ethertype_filter_input *input)
8756 {
8757         int ret;
8758
8759         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8760         if (ret < 0)
8761                 return NULL;
8762
8763         return ethertype_rule->hash_map[ret];
8764 }
8765
8766 /* Add ethertype filter in SW list */
8767 static int
8768 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8769                                 struct i40e_ethertype_filter *filter)
8770 {
8771         struct i40e_ethertype_rule *rule = &pf->ethertype;
8772         int ret;
8773
8774         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8775         if (ret < 0) {
8776                 PMD_DRV_LOG(ERR,
8777                             "Failed to insert ethertype filter"
8778                             " to hash table %d!",
8779                             ret);
8780                 return ret;
8781         }
8782         rule->hash_map[ret] = filter;
8783
8784         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8785
8786         return 0;
8787 }
8788
8789 /* Delete ethertype filter in SW list */
8790 int
8791 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8792                              struct i40e_ethertype_filter_input *input)
8793 {
8794         struct i40e_ethertype_rule *rule = &pf->ethertype;
8795         struct i40e_ethertype_filter *filter;
8796         int ret;
8797
8798         ret = rte_hash_del_key(rule->hash_table, input);
8799         if (ret < 0) {
8800                 PMD_DRV_LOG(ERR,
8801                             "Failed to delete ethertype filter"
8802                             " to hash table %d!",
8803                             ret);
8804                 return ret;
8805         }
8806         filter = rule->hash_map[ret];
8807         rule->hash_map[ret] = NULL;
8808
8809         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8810         rte_free(filter);
8811
8812         return 0;
8813 }
8814
8815 /*
8816  * Configure ethertype filter, which can director packet by filtering
8817  * with mac address and ether_type or only ether_type
8818  */
8819 int
8820 i40e_ethertype_filter_set(struct i40e_pf *pf,
8821                         struct rte_eth_ethertype_filter *filter,
8822                         bool add)
8823 {
8824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8825         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8826         struct i40e_ethertype_filter *ethertype_filter, *node;
8827         struct i40e_ethertype_filter check_filter;
8828         struct i40e_control_filter_stats stats;
8829         uint16_t flags = 0;
8830         int ret;
8831
8832         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8833                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8834                 return -EINVAL;
8835         }
8836         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8837                 filter->ether_type == ETHER_TYPE_IPv6) {
8838                 PMD_DRV_LOG(ERR,
8839                         "unsupported ether_type(0x%04x) in control packet filter.",
8840                         filter->ether_type);
8841                 return -EINVAL;
8842         }
8843         if (filter->ether_type == ETHER_TYPE_VLAN)
8844                 PMD_DRV_LOG(WARNING,
8845                         "filter vlan ether_type in first tag is not supported.");
8846
8847         /* Check if there is the filter in SW list */
8848         memset(&check_filter, 0, sizeof(check_filter));
8849         i40e_ethertype_filter_convert(filter, &check_filter);
8850         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8851                                                &check_filter.input);
8852         if (add && node) {
8853                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8854                 return -EINVAL;
8855         }
8856
8857         if (!add && !node) {
8858                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8859                 return -EINVAL;
8860         }
8861
8862         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8863                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8864         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8865                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8866         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8867
8868         memset(&stats, 0, sizeof(stats));
8869         ret = i40e_aq_add_rem_control_packet_filter(hw,
8870                         filter->mac_addr.addr_bytes,
8871                         filter->ether_type, flags,
8872                         pf->main_vsi->seid,
8873                         filter->queue, add, &stats, NULL);
8874
8875         PMD_DRV_LOG(INFO,
8876                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8877                 ret, stats.mac_etype_used, stats.etype_used,
8878                 stats.mac_etype_free, stats.etype_free);
8879         if (ret < 0)
8880                 return -ENOSYS;
8881
8882         /* Add or delete a filter in SW list */
8883         if (add) {
8884                 ethertype_filter = rte_zmalloc("ethertype_filter",
8885                                        sizeof(*ethertype_filter), 0);
8886                 rte_memcpy(ethertype_filter, &check_filter,
8887                            sizeof(check_filter));
8888                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8889         } else {
8890                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8891         }
8892
8893         return ret;
8894 }
8895
8896 /*
8897  * Handle operations for ethertype filter.
8898  */
8899 static int
8900 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8901                                 enum rte_filter_op filter_op,
8902                                 void *arg)
8903 {
8904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8905         int ret = 0;
8906
8907         if (filter_op == RTE_ETH_FILTER_NOP)
8908                 return ret;
8909
8910         if (arg == NULL) {
8911                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8912                             filter_op);
8913                 return -EINVAL;
8914         }
8915
8916         switch (filter_op) {
8917         case RTE_ETH_FILTER_ADD:
8918                 ret = i40e_ethertype_filter_set(pf,
8919                         (struct rte_eth_ethertype_filter *)arg,
8920                         TRUE);
8921                 break;
8922         case RTE_ETH_FILTER_DELETE:
8923                 ret = i40e_ethertype_filter_set(pf,
8924                         (struct rte_eth_ethertype_filter *)arg,
8925                         FALSE);
8926                 break;
8927         default:
8928                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8929                 ret = -ENOSYS;
8930                 break;
8931         }
8932         return ret;
8933 }
8934
8935 static int
8936 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8937                      enum rte_filter_type filter_type,
8938                      enum rte_filter_op filter_op,
8939                      void *arg)
8940 {
8941         int ret = 0;
8942
8943         if (dev == NULL)
8944                 return -EINVAL;
8945
8946         switch (filter_type) {
8947         case RTE_ETH_FILTER_NONE:
8948                 /* For global configuration */
8949                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8950                 break;
8951         case RTE_ETH_FILTER_HASH:
8952                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8953                 break;
8954         case RTE_ETH_FILTER_MACVLAN:
8955                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8956                 break;
8957         case RTE_ETH_FILTER_ETHERTYPE:
8958                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8959                 break;
8960         case RTE_ETH_FILTER_TUNNEL:
8961                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8962                 break;
8963         case RTE_ETH_FILTER_FDIR:
8964                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8965                 break;
8966         case RTE_ETH_FILTER_GENERIC:
8967                 if (filter_op != RTE_ETH_FILTER_GET)
8968                         return -EINVAL;
8969                 *(const void **)arg = &i40e_flow_ops;
8970                 break;
8971         default:
8972                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8973                                                         filter_type);
8974                 ret = -EINVAL;
8975                 break;
8976         }
8977
8978         return ret;
8979 }
8980
8981 /*
8982  * Check and enable Extended Tag.
8983  * Enabling Extended Tag is important for 40G performance.
8984  */
8985 static void
8986 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8987 {
8988         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8989         uint32_t buf = 0;
8990         int ret;
8991
8992         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8993                                       PCI_DEV_CAP_REG);
8994         if (ret < 0) {
8995                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8996                             PCI_DEV_CAP_REG);
8997                 return;
8998         }
8999         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9000                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9001                 return;
9002         }
9003
9004         buf = 0;
9005         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
9006                                       PCI_DEV_CTRL_REG);
9007         if (ret < 0) {
9008                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9009                             PCI_DEV_CTRL_REG);
9010                 return;
9011         }
9012         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9013                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9014                 return;
9015         }
9016         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9017         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
9018                                        PCI_DEV_CTRL_REG);
9019         if (ret < 0) {
9020                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9021                             PCI_DEV_CTRL_REG);
9022                 return;
9023         }
9024 }
9025
9026 /*
9027  * As some registers wouldn't be reset unless a global hardware reset,
9028  * hardware initialization is needed to put those registers into an
9029  * expected initial state.
9030  */
9031 static void
9032 i40e_hw_init(struct rte_eth_dev *dev)
9033 {
9034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9035
9036         i40e_enable_extended_tag(dev);
9037
9038         /* clear the PF Queue Filter control register */
9039         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9040
9041         /* Disable symmetric hash per port */
9042         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9043 }
9044
9045 enum i40e_filter_pctype
9046 i40e_flowtype_to_pctype(uint16_t flow_type)
9047 {
9048         static const enum i40e_filter_pctype pctype_table[] = {
9049                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9050                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9051                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9052                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9053                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9054                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9055                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9056                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9057                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9058                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9059                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9060                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9061                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9062                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9063                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9064                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9065                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9066                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9067                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9068         };
9069
9070         return pctype_table[flow_type];
9071 }
9072
9073 uint16_t
9074 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9075 {
9076         static const uint16_t flowtype_table[] = {
9077                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9078                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9079                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9080                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9081                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9082                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9083                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9084                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9085                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9086                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9087                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9088                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9089                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9090                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9091                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9092                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9093                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9094                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9095                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9096                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9097                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9098                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9099                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9100                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9101                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9102                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9103                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9104                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9105                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9106                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9107                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9108         };
9109
9110         return flowtype_table[pctype];
9111 }
9112
9113 /*
9114  * On X710, performance number is far from the expectation on recent firmware
9115  * versions; on XL710, performance number is also far from the expectation on
9116  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9117  * mode is enabled and port MAC address is equal to the packet destination MAC
9118  * address. The fix for this issue may not be integrated in the following
9119  * firmware version. So the workaround in software driver is needed. It needs
9120  * to modify the initial values of 3 internal only registers for both X710 and
9121  * XL710. Note that the values for X710 or XL710 could be different, and the
9122  * workaround can be removed when it is fixed in firmware in the future.
9123  */
9124
9125 /* For both X710 and XL710 */
9126 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9127 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9128
9129 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9130 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9131
9132 /* For X722 */
9133 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9134 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9135
9136 /* For X710 */
9137 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9138 /* For XL710 */
9139 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9140 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9141
9142 static int
9143 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9144 {
9145         enum i40e_status_code status;
9146         struct i40e_aq_get_phy_abilities_resp phy_ab;
9147         int ret = -ENOTSUP;
9148
9149         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9150                                               NULL);
9151
9152         if (status)
9153                 return ret;
9154
9155         return 0;
9156 }
9157
9158 static void
9159 i40e_configure_registers(struct i40e_hw *hw)
9160 {
9161         static struct {
9162                 uint32_t addr;
9163                 uint64_t val;
9164         } reg_table[] = {
9165                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9166                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9167                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9168         };
9169         uint64_t reg;
9170         uint32_t i;
9171         int ret;
9172
9173         for (i = 0; i < RTE_DIM(reg_table); i++) {
9174                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9175                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9176                                 reg_table[i].val =
9177                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9178                         else /* For X710/XL710/XXV710 */
9179                                 reg_table[i].val =
9180                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9181                 }
9182
9183                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9184                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9185                                 reg_table[i].val =
9186                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9187                         else /* For X710/XL710/XXV710 */
9188                                 reg_table[i].val =
9189                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9190                 }
9191
9192                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9193                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9194                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9195                                 reg_table[i].val =
9196                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9197                         else /* For X710 */
9198                                 reg_table[i].val =
9199                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9200                 }
9201
9202                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9203                                                         &reg, NULL);
9204                 if (ret < 0) {
9205                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9206                                                         reg_table[i].addr);
9207                         break;
9208                 }
9209                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9210                                                 reg_table[i].addr, reg);
9211                 if (reg == reg_table[i].val)
9212                         continue;
9213
9214                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9215                                                 reg_table[i].val, NULL);
9216                 if (ret < 0) {
9217                         PMD_DRV_LOG(ERR,
9218                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9219                                 reg_table[i].val, reg_table[i].addr);
9220                         break;
9221                 }
9222                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9223                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9224         }
9225 }
9226
9227 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9228 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9229 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9230 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9231 static int
9232 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9233 {
9234         uint32_t reg;
9235         int ret;
9236
9237         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9238                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9239                 return -EINVAL;
9240         }
9241
9242         /* Configure for double VLAN RX stripping */
9243         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9244         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9245                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9246                 ret = i40e_aq_debug_write_register(hw,
9247                                                    I40E_VSI_TSR(vsi->vsi_id),
9248                                                    reg, NULL);
9249                 if (ret < 0) {
9250                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9251                                     vsi->vsi_id);
9252                         return I40E_ERR_CONFIG;
9253                 }
9254         }
9255
9256         /* Configure for double VLAN TX insertion */
9257         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9258         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9259                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9260                 ret = i40e_aq_debug_write_register(hw,
9261                                                    I40E_VSI_L2TAGSTXVALID(
9262                                                    vsi->vsi_id), reg, NULL);
9263                 if (ret < 0) {
9264                         PMD_DRV_LOG(ERR,
9265                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9266                                 vsi->vsi_id);
9267                         return I40E_ERR_CONFIG;
9268                 }
9269         }
9270
9271         return 0;
9272 }
9273
9274 /**
9275  * i40e_aq_add_mirror_rule
9276  * @hw: pointer to the hardware structure
9277  * @seid: VEB seid to add mirror rule to
9278  * @dst_id: destination vsi seid
9279  * @entries: Buffer which contains the entities to be mirrored
9280  * @count: number of entities contained in the buffer
9281  * @rule_id:the rule_id of the rule to be added
9282  *
9283  * Add a mirror rule for a given veb.
9284  *
9285  **/
9286 static enum i40e_status_code
9287 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9288                         uint16_t seid, uint16_t dst_id,
9289                         uint16_t rule_type, uint16_t *entries,
9290                         uint16_t count, uint16_t *rule_id)
9291 {
9292         struct i40e_aq_desc desc;
9293         struct i40e_aqc_add_delete_mirror_rule cmd;
9294         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9295                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9296                 &desc.params.raw;
9297         uint16_t buff_len;
9298         enum i40e_status_code status;
9299
9300         i40e_fill_default_direct_cmd_desc(&desc,
9301                                           i40e_aqc_opc_add_mirror_rule);
9302         memset(&cmd, 0, sizeof(cmd));
9303
9304         buff_len = sizeof(uint16_t) * count;
9305         desc.datalen = rte_cpu_to_le_16(buff_len);
9306         if (buff_len > 0)
9307                 desc.flags |= rte_cpu_to_le_16(
9308                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9309         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9310                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9311         cmd.num_entries = rte_cpu_to_le_16(count);
9312         cmd.seid = rte_cpu_to_le_16(seid);
9313         cmd.destination = rte_cpu_to_le_16(dst_id);
9314
9315         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9316         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9317         PMD_DRV_LOG(INFO,
9318                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9319                 hw->aq.asq_last_status, resp->rule_id,
9320                 resp->mirror_rules_used, resp->mirror_rules_free);
9321         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9322
9323         return status;
9324 }
9325
9326 /**
9327  * i40e_aq_del_mirror_rule
9328  * @hw: pointer to the hardware structure
9329  * @seid: VEB seid to add mirror rule to
9330  * @entries: Buffer which contains the entities to be mirrored
9331  * @count: number of entities contained in the buffer
9332  * @rule_id:the rule_id of the rule to be delete
9333  *
9334  * Delete a mirror rule for a given veb.
9335  *
9336  **/
9337 static enum i40e_status_code
9338 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9339                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9340                 uint16_t count, uint16_t rule_id)
9341 {
9342         struct i40e_aq_desc desc;
9343         struct i40e_aqc_add_delete_mirror_rule cmd;
9344         uint16_t buff_len = 0;
9345         enum i40e_status_code status;
9346         void *buff = NULL;
9347
9348         i40e_fill_default_direct_cmd_desc(&desc,
9349                                           i40e_aqc_opc_delete_mirror_rule);
9350         memset(&cmd, 0, sizeof(cmd));
9351         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9352                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9353                                                           I40E_AQ_FLAG_RD));
9354                 cmd.num_entries = count;
9355                 buff_len = sizeof(uint16_t) * count;
9356                 desc.datalen = rte_cpu_to_le_16(buff_len);
9357                 buff = (void *)entries;
9358         } else
9359                 /* rule id is filled in destination field for deleting mirror rule */
9360                 cmd.destination = rte_cpu_to_le_16(rule_id);
9361
9362         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9363                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9364         cmd.seid = rte_cpu_to_le_16(seid);
9365
9366         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9367         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9368
9369         return status;
9370 }
9371
9372 /**
9373  * i40e_mirror_rule_set
9374  * @dev: pointer to the hardware structure
9375  * @mirror_conf: mirror rule info
9376  * @sw_id: mirror rule's sw_id
9377  * @on: enable/disable
9378  *
9379  * set a mirror rule.
9380  *
9381  **/
9382 static int
9383 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9384                         struct rte_eth_mirror_conf *mirror_conf,
9385                         uint8_t sw_id, uint8_t on)
9386 {
9387         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9389         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9390         struct i40e_mirror_rule *parent = NULL;
9391         uint16_t seid, dst_seid, rule_id;
9392         uint16_t i, j = 0;
9393         int ret;
9394
9395         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9396
9397         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9398                 PMD_DRV_LOG(ERR,
9399                         "mirror rule can not be configured without veb or vfs.");
9400                 return -ENOSYS;
9401         }
9402         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9403                 PMD_DRV_LOG(ERR, "mirror table is full.");
9404                 return -ENOSPC;
9405         }
9406         if (mirror_conf->dst_pool > pf->vf_num) {
9407                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9408                                  mirror_conf->dst_pool);
9409                 return -EINVAL;
9410         }
9411
9412         seid = pf->main_vsi->veb->seid;
9413
9414         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9415                 if (sw_id <= it->index) {
9416                         mirr_rule = it;
9417                         break;
9418                 }
9419                 parent = it;
9420         }
9421         if (mirr_rule && sw_id == mirr_rule->index) {
9422                 if (on) {
9423                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9424                         return -EEXIST;
9425                 } else {
9426                         ret = i40e_aq_del_mirror_rule(hw, seid,
9427                                         mirr_rule->rule_type,
9428                                         mirr_rule->entries,
9429                                         mirr_rule->num_entries, mirr_rule->id);
9430                         if (ret < 0) {
9431                                 PMD_DRV_LOG(ERR,
9432                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9433                                         ret, hw->aq.asq_last_status);
9434                                 return -ENOSYS;
9435                         }
9436                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9437                         rte_free(mirr_rule);
9438                         pf->nb_mirror_rule--;
9439                         return 0;
9440                 }
9441         } else if (!on) {
9442                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9443                 return -ENOENT;
9444         }
9445
9446         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9447                                 sizeof(struct i40e_mirror_rule) , 0);
9448         if (!mirr_rule) {
9449                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9450                 return I40E_ERR_NO_MEMORY;
9451         }
9452         switch (mirror_conf->rule_type) {
9453         case ETH_MIRROR_VLAN:
9454                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9455                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9456                                 mirr_rule->entries[j] =
9457                                         mirror_conf->vlan.vlan_id[i];
9458                                 j++;
9459                         }
9460                 }
9461                 if (j == 0) {
9462                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9463                         rte_free(mirr_rule);
9464                         return -EINVAL;
9465                 }
9466                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9467                 break;
9468         case ETH_MIRROR_VIRTUAL_POOL_UP:
9469         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9470                 /* check if the specified pool bit is out of range */
9471                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9472                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9473                         rte_free(mirr_rule);
9474                         return -EINVAL;
9475                 }
9476                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9477                         if (mirror_conf->pool_mask & (1ULL << i)) {
9478                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9479                                 j++;
9480                         }
9481                 }
9482                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9483                         /* add pf vsi to entries */
9484                         mirr_rule->entries[j] = pf->main_vsi_seid;
9485                         j++;
9486                 }
9487                 if (j == 0) {
9488                         PMD_DRV_LOG(ERR, "pool is not specified.");
9489                         rte_free(mirr_rule);
9490                         return -EINVAL;
9491                 }
9492                 /* egress and ingress in aq commands means from switch but not port */
9493                 mirr_rule->rule_type =
9494                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9495                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9496                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9497                 break;
9498         case ETH_MIRROR_UPLINK_PORT:
9499                 /* egress and ingress in aq commands means from switch but not port*/
9500                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9501                 break;
9502         case ETH_MIRROR_DOWNLINK_PORT:
9503                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9504                 break;
9505         default:
9506                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9507                         mirror_conf->rule_type);
9508                 rte_free(mirr_rule);
9509                 return -EINVAL;
9510         }
9511
9512         /* If the dst_pool is equal to vf_num, consider it as PF */
9513         if (mirror_conf->dst_pool == pf->vf_num)
9514                 dst_seid = pf->main_vsi_seid;
9515         else
9516                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9517
9518         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9519                                       mirr_rule->rule_type, mirr_rule->entries,
9520                                       j, &rule_id);
9521         if (ret < 0) {
9522                 PMD_DRV_LOG(ERR,
9523                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9524                         ret, hw->aq.asq_last_status);
9525                 rte_free(mirr_rule);
9526                 return -ENOSYS;
9527         }
9528
9529         mirr_rule->index = sw_id;
9530         mirr_rule->num_entries = j;
9531         mirr_rule->id = rule_id;
9532         mirr_rule->dst_vsi_seid = dst_seid;
9533
9534         if (parent)
9535                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9536         else
9537                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9538
9539         pf->nb_mirror_rule++;
9540         return 0;
9541 }
9542
9543 /**
9544  * i40e_mirror_rule_reset
9545  * @dev: pointer to the device
9546  * @sw_id: mirror rule's sw_id
9547  *
9548  * reset a mirror rule.
9549  *
9550  **/
9551 static int
9552 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9553 {
9554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9556         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9557         uint16_t seid;
9558         int ret;
9559
9560         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9561
9562         seid = pf->main_vsi->veb->seid;
9563
9564         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9565                 if (sw_id == it->index) {
9566                         mirr_rule = it;
9567                         break;
9568                 }
9569         }
9570         if (mirr_rule) {
9571                 ret = i40e_aq_del_mirror_rule(hw, seid,
9572                                 mirr_rule->rule_type,
9573                                 mirr_rule->entries,
9574                                 mirr_rule->num_entries, mirr_rule->id);
9575                 if (ret < 0) {
9576                         PMD_DRV_LOG(ERR,
9577                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9578                                 ret, hw->aq.asq_last_status);
9579                         return -ENOSYS;
9580                 }
9581                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9582                 rte_free(mirr_rule);
9583                 pf->nb_mirror_rule--;
9584         } else {
9585                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9586                 return -ENOENT;
9587         }
9588         return 0;
9589 }
9590
9591 static uint64_t
9592 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9593 {
9594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9595         uint64_t systim_cycles;
9596
9597         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9598         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9599                         << 32;
9600
9601         return systim_cycles;
9602 }
9603
9604 static uint64_t
9605 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9606 {
9607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9608         uint64_t rx_tstamp;
9609
9610         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9611         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9612                         << 32;
9613
9614         return rx_tstamp;
9615 }
9616
9617 static uint64_t
9618 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9619 {
9620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9621         uint64_t tx_tstamp;
9622
9623         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9624         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9625                         << 32;
9626
9627         return tx_tstamp;
9628 }
9629
9630 static void
9631 i40e_start_timecounters(struct rte_eth_dev *dev)
9632 {
9633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9634         struct i40e_adapter *adapter =
9635                         (struct i40e_adapter *)dev->data->dev_private;
9636         struct rte_eth_link link;
9637         uint32_t tsync_inc_l;
9638         uint32_t tsync_inc_h;
9639
9640         /* Get current link speed. */
9641         memset(&link, 0, sizeof(link));
9642         i40e_dev_link_update(dev, 1);
9643         rte_i40e_dev_atomic_read_link_status(dev, &link);
9644
9645         switch (link.link_speed) {
9646         case ETH_SPEED_NUM_40G:
9647                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9648                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9649                 break;
9650         case ETH_SPEED_NUM_10G:
9651                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9652                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9653                 break;
9654         case ETH_SPEED_NUM_1G:
9655                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9656                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9657                 break;
9658         default:
9659                 tsync_inc_l = 0x0;
9660                 tsync_inc_h = 0x0;
9661         }
9662
9663         /* Set the timesync increment value. */
9664         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9665         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9666
9667         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9668         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9669         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9670
9671         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9672         adapter->systime_tc.cc_shift = 0;
9673         adapter->systime_tc.nsec_mask = 0;
9674
9675         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9676         adapter->rx_tstamp_tc.cc_shift = 0;
9677         adapter->rx_tstamp_tc.nsec_mask = 0;
9678
9679         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9680         adapter->tx_tstamp_tc.cc_shift = 0;
9681         adapter->tx_tstamp_tc.nsec_mask = 0;
9682 }
9683
9684 static int
9685 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9686 {
9687         struct i40e_adapter *adapter =
9688                         (struct i40e_adapter *)dev->data->dev_private;
9689
9690         adapter->systime_tc.nsec += delta;
9691         adapter->rx_tstamp_tc.nsec += delta;
9692         adapter->tx_tstamp_tc.nsec += delta;
9693
9694         return 0;
9695 }
9696
9697 static int
9698 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9699 {
9700         uint64_t ns;
9701         struct i40e_adapter *adapter =
9702                         (struct i40e_adapter *)dev->data->dev_private;
9703
9704         ns = rte_timespec_to_ns(ts);
9705
9706         /* Set the timecounters to a new value. */
9707         adapter->systime_tc.nsec = ns;
9708         adapter->rx_tstamp_tc.nsec = ns;
9709         adapter->tx_tstamp_tc.nsec = ns;
9710
9711         return 0;
9712 }
9713
9714 static int
9715 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9716 {
9717         uint64_t ns, systime_cycles;
9718         struct i40e_adapter *adapter =
9719                         (struct i40e_adapter *)dev->data->dev_private;
9720
9721         systime_cycles = i40e_read_systime_cyclecounter(dev);
9722         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9723         *ts = rte_ns_to_timespec(ns);
9724
9725         return 0;
9726 }
9727
9728 static int
9729 i40e_timesync_enable(struct rte_eth_dev *dev)
9730 {
9731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9732         uint32_t tsync_ctl_l;
9733         uint32_t tsync_ctl_h;
9734
9735         /* Stop the timesync system time. */
9736         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9737         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9738         /* Reset the timesync system time value. */
9739         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9740         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9741
9742         i40e_start_timecounters(dev);
9743
9744         /* Clear timesync registers. */
9745         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9746         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9747         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9748         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9749         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9750         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9751
9752         /* Enable timestamping of PTP packets. */
9753         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9754         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9755
9756         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9757         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9758         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9759
9760         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9761         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9762
9763         return 0;
9764 }
9765
9766 static int
9767 i40e_timesync_disable(struct rte_eth_dev *dev)
9768 {
9769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9770         uint32_t tsync_ctl_l;
9771         uint32_t tsync_ctl_h;
9772
9773         /* Disable timestamping of transmitted PTP packets. */
9774         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9775         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9776
9777         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9778         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9779
9780         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9781         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9782
9783         /* Reset the timesync increment value. */
9784         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9785         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9786
9787         return 0;
9788 }
9789
9790 static int
9791 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9792                                 struct timespec *timestamp, uint32_t flags)
9793 {
9794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9795         struct i40e_adapter *adapter =
9796                 (struct i40e_adapter *)dev->data->dev_private;
9797
9798         uint32_t sync_status;
9799         uint32_t index = flags & 0x03;
9800         uint64_t rx_tstamp_cycles;
9801         uint64_t ns;
9802
9803         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9804         if ((sync_status & (1 << index)) == 0)
9805                 return -EINVAL;
9806
9807         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9808         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9809         *timestamp = rte_ns_to_timespec(ns);
9810
9811         return 0;
9812 }
9813
9814 static int
9815 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9816                                 struct timespec *timestamp)
9817 {
9818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9819         struct i40e_adapter *adapter =
9820                 (struct i40e_adapter *)dev->data->dev_private;
9821
9822         uint32_t sync_status;
9823         uint64_t tx_tstamp_cycles;
9824         uint64_t ns;
9825
9826         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9827         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9828                 return -EINVAL;
9829
9830         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9831         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9832         *timestamp = rte_ns_to_timespec(ns);
9833
9834         return 0;
9835 }
9836
9837 /*
9838  * i40e_parse_dcb_configure - parse dcb configure from user
9839  * @dev: the device being configured
9840  * @dcb_cfg: pointer of the result of parse
9841  * @*tc_map: bit map of enabled traffic classes
9842  *
9843  * Returns 0 on success, negative value on failure
9844  */
9845 static int
9846 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9847                          struct i40e_dcbx_config *dcb_cfg,
9848                          uint8_t *tc_map)
9849 {
9850         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9851         uint8_t i, tc_bw, bw_lf;
9852
9853         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9854
9855         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9856         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9857                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9858                 return -EINVAL;
9859         }
9860
9861         /* assume each tc has the same bw */
9862         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9863         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9864                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9865         /* to ensure the sum of tcbw is equal to 100 */
9866         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9867         for (i = 0; i < bw_lf; i++)
9868                 dcb_cfg->etscfg.tcbwtable[i]++;
9869
9870         /* assume each tc has the same Transmission Selection Algorithm */
9871         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9872                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9873
9874         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9875                 dcb_cfg->etscfg.prioritytable[i] =
9876                                 dcb_rx_conf->dcb_tc[i];
9877
9878         /* FW needs one App to configure HW */
9879         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9880         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9881         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9882         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9883
9884         if (dcb_rx_conf->nb_tcs == 0)
9885                 *tc_map = 1; /* tc0 only */
9886         else
9887                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9888
9889         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9890                 dcb_cfg->pfc.willing = 0;
9891                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9892                 dcb_cfg->pfc.pfcenable = *tc_map;
9893         }
9894         return 0;
9895 }
9896
9897
9898 static enum i40e_status_code
9899 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9900                               struct i40e_aqc_vsi_properties_data *info,
9901                               uint8_t enabled_tcmap)
9902 {
9903         enum i40e_status_code ret;
9904         int i, total_tc = 0;
9905         uint16_t qpnum_per_tc, bsf, qp_idx;
9906         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9907         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9908         uint16_t used_queues;
9909
9910         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9911         if (ret != I40E_SUCCESS)
9912                 return ret;
9913
9914         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9915                 if (enabled_tcmap & (1 << i))
9916                         total_tc++;
9917         }
9918         if (total_tc == 0)
9919                 total_tc = 1;
9920         vsi->enabled_tc = enabled_tcmap;
9921
9922         /* different VSI has different queues assigned */
9923         if (vsi->type == I40E_VSI_MAIN)
9924                 used_queues = dev_data->nb_rx_queues -
9925                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9926         else if (vsi->type == I40E_VSI_VMDQ2)
9927                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9928         else {
9929                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9930                 return I40E_ERR_NO_AVAILABLE_VSI;
9931         }
9932
9933         qpnum_per_tc = used_queues / total_tc;
9934         /* Number of queues per enabled TC */
9935         if (qpnum_per_tc == 0) {
9936                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9937                 return I40E_ERR_INVALID_QP_ID;
9938         }
9939         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9940                                 I40E_MAX_Q_PER_TC);
9941         bsf = rte_bsf32(qpnum_per_tc);
9942
9943         /**
9944          * Configure TC and queue mapping parameters, for enabled TC,
9945          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9946          * default queue will serve it.
9947          */
9948         qp_idx = 0;
9949         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9950                 if (vsi->enabled_tc & (1 << i)) {
9951                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9952                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9953                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9954                         qp_idx += qpnum_per_tc;
9955                 } else
9956                         info->tc_mapping[i] = 0;
9957         }
9958
9959         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9960         if (vsi->type == I40E_VSI_SRIOV) {
9961                 info->mapping_flags |=
9962                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9963                 for (i = 0; i < vsi->nb_qps; i++)
9964                         info->queue_mapping[i] =
9965                                 rte_cpu_to_le_16(vsi->base_queue + i);
9966         } else {
9967                 info->mapping_flags |=
9968                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9969                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9970         }
9971         info->valid_sections |=
9972                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9973
9974         return I40E_SUCCESS;
9975 }
9976
9977 /*
9978  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9979  * @veb: VEB to be configured
9980  * @tc_map: enabled TC bitmap
9981  *
9982  * Returns 0 on success, negative value on failure
9983  */
9984 static enum i40e_status_code
9985 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9986 {
9987         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9988         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9989         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9990         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9991         enum i40e_status_code ret = I40E_SUCCESS;
9992         int i;
9993         uint32_t bw_max;
9994
9995         /* Check if enabled_tc is same as existing or new TCs */
9996         if (veb->enabled_tc == tc_map)
9997                 return ret;
9998
9999         /* configure tc bandwidth */
10000         memset(&veb_bw, 0, sizeof(veb_bw));
10001         veb_bw.tc_valid_bits = tc_map;
10002         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10003         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10004                 if (tc_map & BIT_ULL(i))
10005                         veb_bw.tc_bw_share_credits[i] = 1;
10006         }
10007         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10008                                                    &veb_bw, NULL);
10009         if (ret) {
10010                 PMD_INIT_LOG(ERR,
10011                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10012                         hw->aq.asq_last_status);
10013                 return ret;
10014         }
10015
10016         memset(&ets_query, 0, sizeof(ets_query));
10017         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10018                                                    &ets_query, NULL);
10019         if (ret != I40E_SUCCESS) {
10020                 PMD_DRV_LOG(ERR,
10021                         "Failed to get switch_comp ETS configuration %u",
10022                         hw->aq.asq_last_status);
10023                 return ret;
10024         }
10025         memset(&bw_query, 0, sizeof(bw_query));
10026         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10027                                                   &bw_query, NULL);
10028         if (ret != I40E_SUCCESS) {
10029                 PMD_DRV_LOG(ERR,
10030                         "Failed to get switch_comp bandwidth configuration %u",
10031                         hw->aq.asq_last_status);
10032                 return ret;
10033         }
10034
10035         /* store and print out BW info */
10036         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10037         veb->bw_info.bw_max = ets_query.tc_bw_max;
10038         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10039         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10040         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10041                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10042                      I40E_16_BIT_WIDTH);
10043         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10044                 veb->bw_info.bw_ets_share_credits[i] =
10045                                 bw_query.tc_bw_share_credits[i];
10046                 veb->bw_info.bw_ets_credits[i] =
10047                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10048                 /* 4 bits per TC, 4th bit is reserved */
10049                 veb->bw_info.bw_ets_max[i] =
10050                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10051                                   RTE_LEN2MASK(3, uint8_t));
10052                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10053                             veb->bw_info.bw_ets_share_credits[i]);
10054                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10055                             veb->bw_info.bw_ets_credits[i]);
10056                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10057                             veb->bw_info.bw_ets_max[i]);
10058         }
10059
10060         veb->enabled_tc = tc_map;
10061
10062         return ret;
10063 }
10064
10065
10066 /*
10067  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10068  * @vsi: VSI to be configured
10069  * @tc_map: enabled TC bitmap
10070  *
10071  * Returns 0 on success, negative value on failure
10072  */
10073 static enum i40e_status_code
10074 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10075 {
10076         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10077         struct i40e_vsi_context ctxt;
10078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10079         enum i40e_status_code ret = I40E_SUCCESS;
10080         int i;
10081
10082         /* Check if enabled_tc is same as existing or new TCs */
10083         if (vsi->enabled_tc == tc_map)
10084                 return ret;
10085
10086         /* configure tc bandwidth */
10087         memset(&bw_data, 0, sizeof(bw_data));
10088         bw_data.tc_valid_bits = tc_map;
10089         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10090         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10091                 if (tc_map & BIT_ULL(i))
10092                         bw_data.tc_bw_credits[i] = 1;
10093         }
10094         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10095         if (ret) {
10096                 PMD_INIT_LOG(ERR,
10097                         "AQ command Config VSI BW allocation per TC failed = %d",
10098                         hw->aq.asq_last_status);
10099                 goto out;
10100         }
10101         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10102                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10103
10104         /* Update Queue Pairs Mapping for currently enabled UPs */
10105         ctxt.seid = vsi->seid;
10106         ctxt.pf_num = hw->pf_id;
10107         ctxt.vf_num = 0;
10108         ctxt.uplink_seid = vsi->uplink_seid;
10109         ctxt.info = vsi->info;
10110         i40e_get_cap(hw);
10111         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10112         if (ret)
10113                 goto out;
10114
10115         /* Update the VSI after updating the VSI queue-mapping information */
10116         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10117         if (ret) {
10118                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10119                         hw->aq.asq_last_status);
10120                 goto out;
10121         }
10122         /* update the local VSI info with updated queue map */
10123         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10124                                         sizeof(vsi->info.tc_mapping));
10125         (void)rte_memcpy(&vsi->info.queue_mapping,
10126                         &ctxt.info.queue_mapping,
10127                 sizeof(vsi->info.queue_mapping));
10128         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10129         vsi->info.valid_sections = 0;
10130
10131         /* query and update current VSI BW information */
10132         ret = i40e_vsi_get_bw_config(vsi);
10133         if (ret) {
10134                 PMD_INIT_LOG(ERR,
10135                          "Failed updating vsi bw info, err %s aq_err %s",
10136                          i40e_stat_str(hw, ret),
10137                          i40e_aq_str(hw, hw->aq.asq_last_status));
10138                 goto out;
10139         }
10140
10141         vsi->enabled_tc = tc_map;
10142
10143 out:
10144         return ret;
10145 }
10146
10147 /*
10148  * i40e_dcb_hw_configure - program the dcb setting to hw
10149  * @pf: pf the configuration is taken on
10150  * @new_cfg: new configuration
10151  * @tc_map: enabled TC bitmap
10152  *
10153  * Returns 0 on success, negative value on failure
10154  */
10155 static enum i40e_status_code
10156 i40e_dcb_hw_configure(struct i40e_pf *pf,
10157                       struct i40e_dcbx_config *new_cfg,
10158                       uint8_t tc_map)
10159 {
10160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10161         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10162         struct i40e_vsi *main_vsi = pf->main_vsi;
10163         struct i40e_vsi_list *vsi_list;
10164         enum i40e_status_code ret;
10165         int i;
10166         uint32_t val;
10167
10168         /* Use the FW API if FW > v4.4*/
10169         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10170               (hw->aq.fw_maj_ver >= 5))) {
10171                 PMD_INIT_LOG(ERR,
10172                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10173                 return I40E_ERR_FIRMWARE_API_VERSION;
10174         }
10175
10176         /* Check if need reconfiguration */
10177         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10178                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10179                 return I40E_SUCCESS;
10180         }
10181
10182         /* Copy the new config to the current config */
10183         *old_cfg = *new_cfg;
10184         old_cfg->etsrec = old_cfg->etscfg;
10185         ret = i40e_set_dcb_config(hw);
10186         if (ret) {
10187                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10188                          i40e_stat_str(hw, ret),
10189                          i40e_aq_str(hw, hw->aq.asq_last_status));
10190                 return ret;
10191         }
10192         /* set receive Arbiter to RR mode and ETS scheme by default */
10193         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10194                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10195                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10196                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10197                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10198                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10199                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10200                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10201                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10202                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10203                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10204                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10205                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10206         }
10207         /* get local mib to check whether it is configured correctly */
10208         /* IEEE mode */
10209         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10210         /* Get Local DCB Config */
10211         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10212                                      &hw->local_dcbx_config);
10213
10214         /* if Veb is created, need to update TC of it at first */
10215         if (main_vsi->veb) {
10216                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10217                 if (ret)
10218                         PMD_INIT_LOG(WARNING,
10219                                  "Failed configuring TC for VEB seid=%d",
10220                                  main_vsi->veb->seid);
10221         }
10222         /* Update each VSI */
10223         i40e_vsi_config_tc(main_vsi, tc_map);
10224         if (main_vsi->veb) {
10225                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10226                         /* Beside main VSI and VMDQ VSIs, only enable default
10227                          * TC for other VSIs
10228                          */
10229                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10230                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10231                                                          tc_map);
10232                         else
10233                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10234                                                          I40E_DEFAULT_TCMAP);
10235                         if (ret)
10236                                 PMD_INIT_LOG(WARNING,
10237                                         "Failed configuring TC for VSI seid=%d",
10238                                         vsi_list->vsi->seid);
10239                         /* continue */
10240                 }
10241         }
10242         return I40E_SUCCESS;
10243 }
10244
10245 /*
10246  * i40e_dcb_init_configure - initial dcb config
10247  * @dev: device being configured
10248  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10249  *
10250  * Returns 0 on success, negative value on failure
10251  */
10252 static int
10253 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10254 {
10255         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10256         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10257         int i, ret = 0;
10258
10259         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10260                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10261                 return -ENOTSUP;
10262         }
10263
10264         /* DCB initialization:
10265          * Update DCB configuration from the Firmware and configure
10266          * LLDP MIB change event.
10267          */
10268         if (sw_dcb == TRUE) {
10269                 ret = i40e_init_dcb(hw);
10270                 /* If lldp agent is stopped, the return value from
10271                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10272                  * adminq status. Otherwise, it should return success.
10273                  */
10274                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10275                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10276                         memset(&hw->local_dcbx_config, 0,
10277                                 sizeof(struct i40e_dcbx_config));
10278                         /* set dcb default configuration */
10279                         hw->local_dcbx_config.etscfg.willing = 0;
10280                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10281                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10282                         hw->local_dcbx_config.etscfg.tsatable[0] =
10283                                                 I40E_IEEE_TSA_ETS;
10284                         /* all UPs mapping to TC0 */
10285                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10286                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10287                         hw->local_dcbx_config.etsrec =
10288                                 hw->local_dcbx_config.etscfg;
10289                         hw->local_dcbx_config.pfc.willing = 0;
10290                         hw->local_dcbx_config.pfc.pfccap =
10291                                                 I40E_MAX_TRAFFIC_CLASS;
10292                         /* FW needs one App to configure HW */
10293                         hw->local_dcbx_config.numapps = 1;
10294                         hw->local_dcbx_config.app[0].selector =
10295                                                 I40E_APP_SEL_ETHTYPE;
10296                         hw->local_dcbx_config.app[0].priority = 3;
10297                         hw->local_dcbx_config.app[0].protocolid =
10298                                                 I40E_APP_PROTOID_FCOE;
10299                         ret = i40e_set_dcb_config(hw);
10300                         if (ret) {
10301                                 PMD_INIT_LOG(ERR,
10302                                         "default dcb config fails. err = %d, aq_err = %d.",
10303                                         ret, hw->aq.asq_last_status);
10304                                 return -ENOSYS;
10305                         }
10306                 } else {
10307                         PMD_INIT_LOG(ERR,
10308                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10309                                 ret, hw->aq.asq_last_status);
10310                         return -ENOTSUP;
10311                 }
10312         } else {
10313                 ret = i40e_aq_start_lldp(hw, NULL);
10314                 if (ret != I40E_SUCCESS)
10315                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10316
10317                 ret = i40e_init_dcb(hw);
10318                 if (!ret) {
10319                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10320                                 PMD_INIT_LOG(ERR,
10321                                         "HW doesn't support DCBX offload.");
10322                                 return -ENOTSUP;
10323                         }
10324                 } else {
10325                         PMD_INIT_LOG(ERR,
10326                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10327                                 ret, hw->aq.asq_last_status);
10328                         return -ENOTSUP;
10329                 }
10330         }
10331         return 0;
10332 }
10333
10334 /*
10335  * i40e_dcb_setup - setup dcb related config
10336  * @dev: device being configured
10337  *
10338  * Returns 0 on success, negative value on failure
10339  */
10340 static int
10341 i40e_dcb_setup(struct rte_eth_dev *dev)
10342 {
10343         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10344         struct i40e_dcbx_config dcb_cfg;
10345         uint8_t tc_map = 0;
10346         int ret = 0;
10347
10348         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10349                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10350                 return -ENOTSUP;
10351         }
10352
10353         if (pf->vf_num != 0)
10354                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10355
10356         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10357         if (ret) {
10358                 PMD_INIT_LOG(ERR, "invalid dcb config");
10359                 return -EINVAL;
10360         }
10361         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10362         if (ret) {
10363                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10364                 return -ENOSYS;
10365         }
10366
10367         return 0;
10368 }
10369
10370 static int
10371 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10372                       struct rte_eth_dcb_info *dcb_info)
10373 {
10374         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10376         struct i40e_vsi *vsi = pf->main_vsi;
10377         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10378         uint16_t bsf, tc_mapping;
10379         int i, j = 0;
10380
10381         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10382                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10383         else
10384                 dcb_info->nb_tcs = 1;
10385         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10386                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10387         for (i = 0; i < dcb_info->nb_tcs; i++)
10388                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10389
10390         /* get queue mapping if vmdq is disabled */
10391         if (!pf->nb_cfg_vmdq_vsi) {
10392                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10393                         if (!(vsi->enabled_tc & (1 << i)))
10394                                 continue;
10395                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10396                         dcb_info->tc_queue.tc_rxq[j][i].base =
10397                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10398                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10399                         dcb_info->tc_queue.tc_txq[j][i].base =
10400                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10401                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10402                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10403                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10404                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10405                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10406                 }
10407                 return 0;
10408         }
10409
10410         /* get queue mapping if vmdq is enabled */
10411         do {
10412                 vsi = pf->vmdq[j].vsi;
10413                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10414                         if (!(vsi->enabled_tc & (1 << i)))
10415                                 continue;
10416                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10417                         dcb_info->tc_queue.tc_rxq[j][i].base =
10418                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10419                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10420                         dcb_info->tc_queue.tc_txq[j][i].base =
10421                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10422                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10423                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10424                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10425                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10426                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10427                 }
10428                 j++;
10429         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10430         return 0;
10431 }
10432
10433 static int
10434 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10435 {
10436         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10439         uint16_t interval =
10440                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10441         uint16_t msix_intr;
10442
10443         msix_intr = intr_handle->intr_vec[queue_id];
10444         if (msix_intr == I40E_MISC_VEC_ID)
10445                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10446                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10447                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10448                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10449                                (interval <<
10450                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10451         else
10452                 I40E_WRITE_REG(hw,
10453                                I40E_PFINT_DYN_CTLN(msix_intr -
10454                                                    I40E_RX_VEC_START),
10455                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10456                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10457                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10458                                (interval <<
10459                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10460
10461         I40E_WRITE_FLUSH(hw);
10462         rte_intr_enable(&pci_dev->intr_handle);
10463
10464         return 0;
10465 }
10466
10467 static int
10468 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10469 {
10470         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10471         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10473         uint16_t msix_intr;
10474
10475         msix_intr = intr_handle->intr_vec[queue_id];
10476         if (msix_intr == I40E_MISC_VEC_ID)
10477                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10478         else
10479                 I40E_WRITE_REG(hw,
10480                                I40E_PFINT_DYN_CTLN(msix_intr -
10481                                                    I40E_RX_VEC_START),
10482                                0);
10483         I40E_WRITE_FLUSH(hw);
10484
10485         return 0;
10486 }
10487
10488 static int i40e_get_regs(struct rte_eth_dev *dev,
10489                          struct rte_dev_reg_info *regs)
10490 {
10491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10492         uint32_t *ptr_data = regs->data;
10493         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10494         const struct i40e_reg_info *reg_info;
10495
10496         if (ptr_data == NULL) {
10497                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10498                 regs->width = sizeof(uint32_t);
10499                 return 0;
10500         }
10501
10502         /* The first few registers have to be read using AQ operations */
10503         reg_idx = 0;
10504         while (i40e_regs_adminq[reg_idx].name) {
10505                 reg_info = &i40e_regs_adminq[reg_idx++];
10506                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10507                         for (arr_idx2 = 0;
10508                                         arr_idx2 <= reg_info->count2;
10509                                         arr_idx2++) {
10510                                 reg_offset = arr_idx * reg_info->stride1 +
10511                                         arr_idx2 * reg_info->stride2;
10512                                 reg_offset += reg_info->base_addr;
10513                                 ptr_data[reg_offset >> 2] =
10514                                         i40e_read_rx_ctl(hw, reg_offset);
10515                         }
10516         }
10517
10518         /* The remaining registers can be read using primitives */
10519         reg_idx = 0;
10520         while (i40e_regs_others[reg_idx].name) {
10521                 reg_info = &i40e_regs_others[reg_idx++];
10522                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10523                         for (arr_idx2 = 0;
10524                                         arr_idx2 <= reg_info->count2;
10525                                         arr_idx2++) {
10526                                 reg_offset = arr_idx * reg_info->stride1 +
10527                                         arr_idx2 * reg_info->stride2;
10528                                 reg_offset += reg_info->base_addr;
10529                                 ptr_data[reg_offset >> 2] =
10530                                         I40E_READ_REG(hw, reg_offset);
10531                         }
10532         }
10533
10534         return 0;
10535 }
10536
10537 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10538 {
10539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10540
10541         /* Convert word count to byte count */
10542         return hw->nvm.sr_size << 1;
10543 }
10544
10545 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10546                            struct rte_dev_eeprom_info *eeprom)
10547 {
10548         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10549         uint16_t *data = eeprom->data;
10550         uint16_t offset, length, cnt_words;
10551         int ret_code;
10552
10553         offset = eeprom->offset >> 1;
10554         length = eeprom->length >> 1;
10555         cnt_words = length;
10556
10557         if (offset > hw->nvm.sr_size ||
10558                 offset + length > hw->nvm.sr_size) {
10559                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10560                 return -EINVAL;
10561         }
10562
10563         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10564
10565         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10566         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10567                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10568                 return -EIO;
10569         }
10570
10571         return 0;
10572 }
10573
10574 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10575                                       struct ether_addr *mac_addr)
10576 {
10577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10578
10579         if (!is_valid_assigned_ether_addr(mac_addr)) {
10580                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10581                 return;
10582         }
10583
10584         /* Flags: 0x3 updates port address */
10585         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10586 }
10587
10588 static int
10589 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10590 {
10591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10592         struct rte_eth_dev_data *dev_data = pf->dev_data;
10593         uint32_t frame_size = mtu + ETHER_HDR_LEN
10594                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10595         int ret = 0;
10596
10597         /* check if mtu is within the allowed range */
10598         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10599                 return -EINVAL;
10600
10601         /* mtu setting is forbidden if port is start */
10602         if (dev_data->dev_started) {
10603                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10604                             dev_data->port_id);
10605                 return -EBUSY;
10606         }
10607
10608         if (frame_size > ETHER_MAX_LEN)
10609                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10610         else
10611                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10612
10613         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10614
10615         return ret;
10616 }
10617
10618 /* Restore ethertype filter */
10619 static void
10620 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10621 {
10622         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10623         struct i40e_ethertype_filter_list
10624                 *ethertype_list = &pf->ethertype.ethertype_list;
10625         struct i40e_ethertype_filter *f;
10626         struct i40e_control_filter_stats stats;
10627         uint16_t flags;
10628
10629         TAILQ_FOREACH(f, ethertype_list, rules) {
10630                 flags = 0;
10631                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10632                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10633                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10634                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10635                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10636
10637                 memset(&stats, 0, sizeof(stats));
10638                 i40e_aq_add_rem_control_packet_filter(hw,
10639                                             f->input.mac_addr.addr_bytes,
10640                                             f->input.ether_type,
10641                                             flags, pf->main_vsi->seid,
10642                                             f->queue, 1, &stats, NULL);
10643         }
10644         PMD_DRV_LOG(INFO, "Ethertype filter:"
10645                     " mac_etype_used = %u, etype_used = %u,"
10646                     " mac_etype_free = %u, etype_free = %u",
10647                     stats.mac_etype_used, stats.etype_used,
10648                     stats.mac_etype_free, stats.etype_free);
10649 }
10650
10651 /* Restore tunnel filter */
10652 static void
10653 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10654 {
10655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10656         struct i40e_vsi *vsi;
10657         struct i40e_pf_vf *vf;
10658         struct i40e_tunnel_filter_list
10659                 *tunnel_list = &pf->tunnel.tunnel_list;
10660         struct i40e_tunnel_filter *f;
10661         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10662         bool big_buffer = 0;
10663
10664         TAILQ_FOREACH(f, tunnel_list, rules) {
10665                 if (!f->is_to_vf)
10666                         vsi = pf->main_vsi;
10667                 else {
10668                         vf = &pf->vfs[f->vf_id];
10669                         vsi = vf->vsi;
10670                 }
10671                 memset(&cld_filter, 0, sizeof(cld_filter));
10672                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10673                         (struct ether_addr *)&cld_filter.element.outer_mac);
10674                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10675                         (struct ether_addr *)&cld_filter.element.inner_mac);
10676                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10677                 cld_filter.element.flags = f->input.flags;
10678                 cld_filter.element.tenant_id = f->input.tenant_id;
10679                 cld_filter.element.queue_number = f->queue;
10680                 rte_memcpy(cld_filter.general_fields,
10681                            f->input.general_fields,
10682                            sizeof(f->input.general_fields));
10683
10684                 if (((f->input.flags &
10685                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10686                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10687                     ((f->input.flags &
10688                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10689                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10690                     ((f->input.flags &
10691                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10692                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10693                         big_buffer = 1;
10694
10695                 if (big_buffer)
10696                         i40e_aq_add_cloud_filters_big_buffer(hw,
10697                                              vsi->seid, &cld_filter, 1);
10698                 else
10699                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10700                                                   &cld_filter.element, 1);
10701         }
10702 }
10703
10704 static void
10705 i40e_filter_restore(struct i40e_pf *pf)
10706 {
10707         i40e_ethertype_filter_restore(pf);
10708         i40e_tunnel_filter_restore(pf);
10709         i40e_fdir_filter_restore(pf);
10710 }
10711
10712 static bool
10713 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10714 {
10715         if (strcmp(dev->data->drv_name,
10716                    drv->driver.name))
10717                 return false;
10718
10719         return true;
10720 }
10721
10722 bool
10723 is_i40e_supported(struct rte_eth_dev *dev)
10724 {
10725         return is_device_supported(dev, &rte_i40e_pmd);
10726 }
10727
10728 /* Create a QinQ cloud filter
10729  *
10730  * The Fortville NIC has limited resources for tunnel filters,
10731  * so we can only reuse existing filters.
10732  *
10733  * In step 1 we define which Field Vector fields can be used for
10734  * filter types.
10735  * As we do not have the inner tag defined as a field,
10736  * we have to define it first, by reusing one of L1 entries.
10737  *
10738  * In step 2 we are replacing one of existing filter types with
10739  * a new one for QinQ.
10740  * As we reusing L1 and replacing L2, some of the default filter
10741  * types will disappear,which depends on L1 and L2 entries we reuse.
10742  *
10743  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10744  *
10745  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10746  *              later when we define the cloud filter.
10747  *      a.      Valid_flags.replace_cloud = 0
10748  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10749  *      c.      New_filter = 0x10
10750  *      d.      TR bit = 0xff (optional, not used here)
10751  *      e.      Buffer – 2 entries:
10752  *              i.      Byte 0 = 8 (outer vlan FV index).
10753  *                      Byte 1 = 0 (rsv)
10754  *                      Byte 2-3 = 0x0fff
10755  *              ii.     Byte 0 = 37 (inner vlan FV index).
10756  *                      Byte 1 =0 (rsv)
10757  *                      Byte 2-3 = 0x0fff
10758  *
10759  * Step 2:
10760  * 2.   Create cloud filter using two L1 filters entries: stag and
10761  *              new filter(outer vlan+ inner vlan)
10762  *      a.      Valid_flags.replace_cloud = 1
10763  *      b.      Old_filter = 1 (instead of outer IP)
10764  *      c.      New_filter = 0x10
10765  *      d.      Buffer – 2 entries:
10766  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10767  *                      Byte 1-3 = 0 (rsv)
10768  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10769  *                      Byte 9-11 = 0 (rsv)
10770  */
10771 static int
10772 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10773 {
10774         int ret = -ENOTSUP;
10775         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10776         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10778
10779         /* Init */
10780         memset(&filter_replace, 0,
10781                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10782         memset(&filter_replace_buf, 0,
10783                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10784
10785         /* create L1 filter */
10786         filter_replace.old_filter_type =
10787                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10788         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10789         filter_replace.tr_bit = 0;
10790
10791         /* Prepare the buffer, 2 entries */
10792         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10793         filter_replace_buf.data[0] |=
10794                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10795         /* Field Vector 12b mask */
10796         filter_replace_buf.data[2] = 0xff;
10797         filter_replace_buf.data[3] = 0x0f;
10798         filter_replace_buf.data[4] =
10799                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10800         filter_replace_buf.data[4] |=
10801                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10802         /* Field Vector 12b mask */
10803         filter_replace_buf.data[6] = 0xff;
10804         filter_replace_buf.data[7] = 0x0f;
10805         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10806                         &filter_replace_buf);
10807         if (ret != I40E_SUCCESS)
10808                 return ret;
10809
10810         /* Apply the second L2 cloud filter */
10811         memset(&filter_replace, 0,
10812                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10813         memset(&filter_replace_buf, 0,
10814                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10815
10816         /* create L2 filter, input for L2 filter will be L1 filter  */
10817         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10818         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10819         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10820
10821         /* Prepare the buffer, 2 entries */
10822         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10823         filter_replace_buf.data[0] |=
10824                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10825         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10826         filter_replace_buf.data[4] |=
10827                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10828         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10829                         &filter_replace_buf);
10830         return ret;
10831 }
10832
10833 RTE_INIT(i40e_init_log);
10834 static void
10835 i40e_init_log(void)
10836 {
10837         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10838         if (i40e_logtype_init >= 0)
10839                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10840         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10841         if (i40e_logtype_driver >= 0)
10842                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10843 }