drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 /* The max bandwidth of i40e is 40Gbps. */
 247 #define I40E_QOS_BW_MAX 40000
 248 /* The bandwidth should be the multiple of 50Mbps. */
 249 #define I40E_QOS_BW_GRANULARITY 50
 250 /* The min bandwidth weight is 1. */
 251 #define I40E_QOS_BW_WEIGHT_MIN 1
 252 /* The max bandwidth weight is 127. */
 253 #define I40E_QOS_BW_WEIGHT_MAX 127
 254
 255 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 256 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 257 static int i40e_dev_configure(struct rte_eth_dev *dev);
 258 static int i40e_dev_start(struct rte_eth_dev *dev);
 259 static void i40e_dev_stop(struct rte_eth_dev *dev);
 260 static void i40e_dev_close(struct rte_eth_dev *dev);
 261 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 262 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 263 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 264 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 265 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 266 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 267 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 268                                struct rte_eth_stats *stats);
 269 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 270                                struct rte_eth_xstat *xstats, unsigned n);
 271 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 272                                      struct rte_eth_xstat_name *xstats_names,
 273                                      unsigned limit);
 274 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 275 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 276                                             uint16_t queue_id,
 277                                             uint8_t stat_idx,
 278                                             uint8_t is_rx);
 279 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 280                                 char *fw_version, size_t fw_size);
 281 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 282                               struct rte_eth_dev_info *dev_info);
 283 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 284                                 uint16_t vlan_id,
 285                                 int on);
 286 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 287                               enum rte_vlan_type vlan_type,
 288                               uint16_t tpid);
 289 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 290 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 291                                       uint16_t queue,
 292                                       int on);
 293 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 294 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 295 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 296 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 297                               struct rte_eth_fc_conf *fc_conf);
 298 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 299                               struct rte_eth_fc_conf *fc_conf);
 300 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 301                                        struct rte_eth_pfc_conf *pfc_conf);
 302 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 303                           struct ether_addr *mac_addr,
 304                           uint32_t index,
 305                           uint32_t pool);
 306 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 307 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 308                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 309                                     uint16_t reta_size);
 310 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 311                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 312                                    uint16_t reta_size);
 313
 314 static int i40e_get_cap(struct i40e_hw *hw);
 315 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 316 static int i40e_pf_setup(struct i40e_pf *pf);
 317 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 318 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 319 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 320 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 321 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 322                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 323 static void i40e_stat_update_48(struct i40e_hw *hw,
 324                                uint32_t hireg,
 325                                uint32_t loreg,
 326                                bool offset_loaded,
 327                                uint64_t *offset,
 328                                uint64_t *stat);
 329 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 330 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 331                                        void *param);
 332 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 333                                 uint32_t base, uint32_t num);
 334 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 335 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 336                         uint32_t base);
 337 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 338                         uint16_t num);
 339 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 340 static int i40e_veb_release(struct i40e_veb *veb);
 341 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 342                                                 struct i40e_vsi *vsi);
 343 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 344 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 345 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 346                                              struct i40e_macvlan_filter *mv_f,
 347                                              int num,
 348                                              struct ether_addr *addr);
 349 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 350                                              struct i40e_macvlan_filter *mv_f,
 351                                              int num,
 352                                              uint16_t vlan);
 353 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 354 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 355                                     struct rte_eth_rss_conf *rss_conf);
 356 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 357                                       struct rte_eth_rss_conf *rss_conf);
 358 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 359                                         struct rte_eth_udp_tunnel *udp_tunnel);
 360 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 361                                         struct rte_eth_udp_tunnel *udp_tunnel);
 362 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 363 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 364                                 enum rte_filter_op filter_op,
 365                                 void *arg);
 366 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 367                                 enum rte_filter_type filter_type,
 368                                 enum rte_filter_op filter_op,
 369                                 void *arg);
 370 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 371                                   struct rte_eth_dcb_info *dcb_info);
 372 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 373 static void i40e_configure_registers(struct i40e_hw *hw);
 374 static void i40e_hw_init(struct rte_eth_dev *dev);
 375 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 376 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 377                         struct rte_eth_mirror_conf *mirror_conf,
 378                         uint8_t sw_id, uint8_t on);
 379 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 380
 381 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 382 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 383 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 384                                            struct timespec *timestamp,
 385                                            uint32_t flags);
 386 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 387                                            struct timespec *timestamp);
 388 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 389
 390 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 391
 392 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 393                                    struct timespec *timestamp);
 394 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 395                                     const struct timespec *timestamp);
 396
 397 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 398                                          uint16_t queue_id);
 399 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 400                                           uint16_t queue_id);
 401
 402 static int i40e_get_regs(struct rte_eth_dev *dev,
 403                          struct rte_dev_reg_info *regs);
 404
 405 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 406
 407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 408                            struct rte_dev_eeprom_info *eeprom);
 409
 410 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 411                                       struct ether_addr *mac_addr);
 412
 413 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 414
 415 static int i40e_ethertype_filter_convert(
 416         const struct rte_eth_ethertype_filter *input,
 417         struct i40e_ethertype_filter *filter);
 418 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 419                                    struct i40e_ethertype_filter *filter);
 420
 421 static int i40e_tunnel_filter_convert(
 422         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 423         struct i40e_tunnel_filter *tunnel_filter);
 424 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 425                                 struct i40e_tunnel_filter *tunnel_filter);
 426
 427 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 428 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 429 static void i40e_filter_restore(struct i40e_pf *pf);
 430
 431 static const struct rte_pci_id pci_id_i40e_map[] = {
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 452         { .vendor_id = 0, /* sentinel */ },
 453 };
 454
 455 static const struct eth_dev_ops i40e_eth_dev_ops = {
 456         .dev_configure                = i40e_dev_configure,
 457         .dev_start                    = i40e_dev_start,
 458         .dev_stop                     = i40e_dev_stop,
 459         .dev_close                    = i40e_dev_close,
 460         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 461         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 462         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 463         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 464         .dev_set_link_up              = i40e_dev_set_link_up,
 465         .dev_set_link_down            = i40e_dev_set_link_down,
 466         .link_update                  = i40e_dev_link_update,
 467         .stats_get                    = i40e_dev_stats_get,
 468         .xstats_get                   = i40e_dev_xstats_get,
 469         .xstats_get_names             = i40e_dev_xstats_get_names,
 470         .stats_reset                  = i40e_dev_stats_reset,
 471         .xstats_reset                 = i40e_dev_stats_reset,
 472         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 473         .fw_version_get               = i40e_fw_version_get,
 474         .dev_infos_get                = i40e_dev_info_get,
 475         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 476         .vlan_filter_set              = i40e_vlan_filter_set,
 477         .vlan_tpid_set                = i40e_vlan_tpid_set,
 478         .vlan_offload_set             = i40e_vlan_offload_set,
 479         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 480         .vlan_pvid_set                = i40e_vlan_pvid_set,
 481         .rx_queue_start               = i40e_dev_rx_queue_start,
 482         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 483         .tx_queue_start               = i40e_dev_tx_queue_start,
 484         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 485         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 486         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 487         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 488         .rx_queue_release             = i40e_dev_rx_queue_release,
 489         .rx_queue_count               = i40e_dev_rx_queue_count,
 490         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 491         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 492         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 493         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 494         .tx_queue_release             = i40e_dev_tx_queue_release,
 495         .dev_led_on                   = i40e_dev_led_on,
 496         .dev_led_off                  = i40e_dev_led_off,
 497         .flow_ctrl_get                = i40e_flow_ctrl_get,
 498         .flow_ctrl_set                = i40e_flow_ctrl_set,
 499         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 500         .mac_addr_add                 = i40e_macaddr_add,
 501         .mac_addr_remove              = i40e_macaddr_remove,
 502         .reta_update                  = i40e_dev_rss_reta_update,
 503         .reta_query                   = i40e_dev_rss_reta_query,
 504         .rss_hash_update              = i40e_dev_rss_hash_update,
 505         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 506         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 507         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 508         .filter_ctrl                  = i40e_dev_filter_ctrl,
 509         .rxq_info_get                 = i40e_rxq_info_get,
 510         .txq_info_get                 = i40e_txq_info_get,
 511         .mirror_rule_set              = i40e_mirror_rule_set,
 512         .mirror_rule_reset            = i40e_mirror_rule_reset,
 513         .timesync_enable              = i40e_timesync_enable,
 514         .timesync_disable             = i40e_timesync_disable,
 515         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 516         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 517         .get_dcb_info                 = i40e_dev_get_dcb_info,
 518         .timesync_adjust_time         = i40e_timesync_adjust_time,
 519         .timesync_read_time           = i40e_timesync_read_time,
 520         .timesync_write_time          = i40e_timesync_write_time,
 521         .get_reg                      = i40e_get_regs,
 522         .get_eeprom_length            = i40e_get_eeprom_length,
 523         .get_eeprom                   = i40e_get_eeprom,
 524         .mac_addr_set                 = i40e_set_default_mac_addr,
 525         .mtu_set                      = i40e_dev_mtu_set,
 526 };
 527
 528 /* store statistics names and its offset in stats structure */
 529 struct rte_i40e_xstats_name_off {
 530         char name[RTE_ETH_XSTATS_NAME_SIZE];
 531         unsigned offset;
 532 };
 533
 534 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 535         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 536         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 537         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 538         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 539         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 540                 rx_unknown_protocol)},
 541         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 542         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 543         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 544         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 545 };
 546
 547 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 548                 sizeof(rte_i40e_stats_strings[0]))
 549
 550 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 551         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 552                 tx_dropped_link_down)},
 553         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 554         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 555                 illegal_bytes)},
 556         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 557         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 558                 mac_local_faults)},
 559         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 560                 mac_remote_faults)},
 561         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 562                 rx_length_errors)},
 563         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 564         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 565         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 566         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 567         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 568         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_127)},
 570         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_255)},
 572         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_511)},
 574         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_1023)},
 576         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_1522)},
 578         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_big)},
 580         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 581                 rx_undersize)},
 582         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_oversize)},
 584         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 585                 mac_short_packet_dropped)},
 586         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_fragments)},
 588         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 589         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 590         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_127)},
 592         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_255)},
 594         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_511)},
 596         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_1023)},
 598         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_1522)},
 600         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_big)},
 602         {"rx_flow_director_atr_match_packets",
 603                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 604         {"rx_flow_director_sb_match_packets",
 605                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 606         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 607                 tx_lpi_status)},
 608         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 609                 rx_lpi_status)},
 610         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_count)},
 612         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_count)},
 614 };
 615
 616 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 617                 sizeof(rte_i40e_hw_port_strings[0]))
 618
 619 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 620         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_rx)},
 622         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xoff_rx)},
 624 };
 625
 626 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 627                 sizeof(rte_i40e_rxq_prio_strings[0]))
 628
 629 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 630         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 631                 priority_xon_tx)},
 632         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xoff_tx)},
 634         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_2_xoff)},
 636 };
 637
 638 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 639                 sizeof(rte_i40e_txq_prio_strings[0]))
 640
 641 static struct eth_driver rte_i40e_pmd = {
 642         .pci_drv = {
 643                 .id_table = pci_id_i40e_map,
 644                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 645                 .probe = rte_eth_dev_pci_probe,
 646                 .remove = rte_eth_dev_pci_remove,
 647         },
 648         .eth_dev_init = eth_i40e_dev_init,
 649         .eth_dev_uninit = eth_i40e_dev_uninit,
 650         .dev_private_size = sizeof(struct i40e_adapter),
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691
 692 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 693 {
 694         /*
 695          * Initialize registers for flexible payload, which should be set by NVM.
 696          * This should be removed from code once it is fixed in NVM.
 697          */
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 699         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 708         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 709         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 710
 711         /* Initialize registers for parsing packet type of QinQ */
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 713         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 714 }
 715
 716 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 717
 718 /*
 719  * Add a ethertype filter to drop all flow control frames transmitted
 720  * from VSIs.
 721 */
 722 static void
 723 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 724 {
 725         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 726         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 727                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 728                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 729         int ret;
 730
 731         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 732                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 733                                 pf->main_vsi_seid, 0,
 734                                 TRUE, NULL, NULL);
 735         if (ret)
 736                 PMD_INIT_LOG(ERR,
 737                         "Failed to add filter to drop flow control frames from VSIs.");
 738 }
 739
 740 static int
 741 floating_veb_list_handler(__rte_unused const char *key,
 742                           const char *floating_veb_value,
 743                           void *opaque)
 744 {
 745         int idx = 0;
 746         unsigned int count = 0;
 747         char *end = NULL;
 748         int min, max;
 749         bool *vf_floating_veb = opaque;
 750
 751         while (isblank(*floating_veb_value))
 752                 floating_veb_value++;
 753
 754         /* Reset floating VEB configuration for VFs */
 755         for (idx = 0; idx < I40E_MAX_VF; idx++)
 756                 vf_floating_veb[idx] = false;
 757
 758         min = I40E_MAX_VF;
 759         do {
 760                 while (isblank(*floating_veb_value))
 761                         floating_veb_value++;
 762                 if (*floating_veb_value == '\0')
 763                         return -1;
 764                 errno = 0;
 765                 idx = strtoul(floating_veb_value, &end, 10);
 766                 if (errno || end == NULL)
 767                         return -1;
 768                 while (isblank(*end))
 769                         end++;
 770                 if (*end == '-') {
 771                         min = idx;
 772                 } else if ((*end == ';') || (*end == '\0')) {
 773                         max = idx;
 774                         if (min == I40E_MAX_VF)
 775                                 min = idx;
 776                         if (max >= I40E_MAX_VF)
 777                                 max = I40E_MAX_VF - 1;
 778                         for (idx = min; idx <= max; idx++) {
 779                                 vf_floating_veb[idx] = true;
 780                                 count++;
 781                         }
 782                         min = I40E_MAX_VF;
 783                 } else {
 784                         return -1;
 785                 }
 786                 floating_veb_value = end + 1;
 787         } while (*end != '\0');
 788
 789         if (count == 0)
 790                 return -1;
 791
 792         return 0;
 793 }
 794
 795 static void
 796 config_vf_floating_veb(struct rte_devargs *devargs,
 797                        uint16_t floating_veb,
 798                        bool *vf_floating_veb)
 799 {
 800         struct rte_kvargs *kvlist;
 801         int i;
 802         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 803
 804         if (!floating_veb)
 805                 return;
 806         /* All the VFs attach to the floating VEB by default
 807          * when the floating VEB is enabled.
 808          */
 809         for (i = 0; i < I40E_MAX_VF; i++)
 810                 vf_floating_veb[i] = true;
 811
 812         if (devargs == NULL)
 813                 return;
 814
 815         kvlist = rte_kvargs_parse(devargs->args, NULL);
 816         if (kvlist == NULL)
 817                 return;
 818
 819         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 820                 rte_kvargs_free(kvlist);
 821                 return;
 822         }
 823         /* When the floating_veb_list parameter exists, all the VFs
 824          * will attach to the legacy VEB firstly, then configure VFs
 825          * to the floating VEB according to the floating_veb_list.
 826          */
 827         if (rte_kvargs_process(kvlist, floating_veb_list,
 828                                floating_veb_list_handler,
 829                                vf_floating_veb) < 0) {
 830                 rte_kvargs_free(kvlist);
 831                 return;
 832         }
 833         rte_kvargs_free(kvlist);
 834 }
 835
 836 static int
 837 i40e_check_floating_handler(__rte_unused const char *key,
 838                             const char *value,
 839                             __rte_unused void *opaque)
 840 {
 841         if (strcmp(value, "1"))
 842                 return -1;
 843
 844         return 0;
 845 }
 846
 847 static int
 848 is_floating_veb_supported(struct rte_devargs *devargs)
 849 {
 850         struct rte_kvargs *kvlist;
 851         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 852
 853         if (devargs == NULL)
 854                 return 0;
 855
 856         kvlist = rte_kvargs_parse(devargs->args, NULL);
 857         if (kvlist == NULL)
 858                 return 0;
 859
 860         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 861                 rte_kvargs_free(kvlist);
 862                 return 0;
 863         }
 864         /* Floating VEB is enabled when there's key-value:
 865          * enable_floating_veb=1
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_key,
 868                                i40e_check_floating_handler, NULL) < 0) {
 869                 rte_kvargs_free(kvlist);
 870                 return 0;
 871         }
 872         rte_kvargs_free(kvlist);
 873
 874         return 1;
 875 }
 876
 877 static void
 878 config_floating_veb(struct rte_eth_dev *dev)
 879 {
 880         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 883
 884         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 885
 886         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 887                 pf->floating_veb =
 888                         is_floating_veb_supported(pci_dev->device.devargs);
 889                 config_vf_floating_veb(pci_dev->device.devargs,
 890                                        pf->floating_veb,
 891                                        pf->floating_veb_list);
 892         } else {
 893                 pf->floating_veb = false;
 894         }
 895 }
 896
 897 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 898 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 899
 900 static int
 901 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 902 {
 903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 904         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 905         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 906         int ret;
 907
 908         struct rte_hash_parameters ethertype_hash_params = {
 909                 .name = ethertype_hash_name,
 910                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 911                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 912                 .hash_func = rte_hash_crc,
 913                 .hash_func_init_val = 0,
 914                 .socket_id = rte_socket_id(),
 915         };
 916
 917         /* Initialize ethertype filter rule list and hash */
 918         TAILQ_INIT(&ethertype_rule->ethertype_list);
 919         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 920                  "ethertype_%s", dev->data->name);
 921         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 922         if (!ethertype_rule->hash_table) {
 923                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 924                 return -EINVAL;
 925         }
 926         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 927                                        sizeof(struct i40e_ethertype_filter *) *
 928                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 929                                        0);
 930         if (!ethertype_rule->hash_map) {
 931                 PMD_INIT_LOG(ERR,
 932                              "Failed to allocate memory for ethertype hash map!");
 933                 ret = -ENOMEM;
 934                 goto err_ethertype_hash_map_alloc;
 935         }
 936
 937         return 0;
 938
 939 err_ethertype_hash_map_alloc:
 940         rte_hash_free(ethertype_rule->hash_table);
 941
 942         return ret;
 943 }
 944
 945 static int
 946 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 947 {
 948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 949         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 950         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 951         int ret;
 952
 953         struct rte_hash_parameters tunnel_hash_params = {
 954                 .name = tunnel_hash_name,
 955                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 956                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 957                 .hash_func = rte_hash_crc,
 958                 .hash_func_init_val = 0,
 959                 .socket_id = rte_socket_id(),
 960         };
 961
 962         /* Initialize tunnel filter rule list and hash */
 963         TAILQ_INIT(&tunnel_rule->tunnel_list);
 964         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 965                  "tunnel_%s", dev->data->name);
 966         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 967         if (!tunnel_rule->hash_table) {
 968                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 969                 return -EINVAL;
 970         }
 971         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 972                                     sizeof(struct i40e_tunnel_filter *) *
 973                                     I40E_MAX_TUNNEL_FILTER_NUM,
 974                                     0);
 975         if (!tunnel_rule->hash_map) {
 976                 PMD_INIT_LOG(ERR,
 977                              "Failed to allocate memory for tunnel hash map!");
 978                 ret = -ENOMEM;
 979                 goto err_tunnel_hash_map_alloc;
 980         }
 981
 982         return 0;
 983
 984 err_tunnel_hash_map_alloc:
 985         rte_hash_free(tunnel_rule->hash_table);
 986
 987         return ret;
 988 }
 989
 990 static int
 991 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 992 {
 993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 994         struct i40e_fdir_info *fdir_info = &pf->fdir;
 995         char fdir_hash_name[RTE_HASH_NAMESIZE];
 996         int ret;
 997
 998         struct rte_hash_parameters fdir_hash_params = {
 999                 .name = fdir_hash_name,
1000                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1001                 .key_len = sizeof(struct rte_eth_fdir_input),
1002                 .hash_func = rte_hash_crc,
1003                 .hash_func_init_val = 0,
1004                 .socket_id = rte_socket_id(),
1005         };
1006
1007         /* Initialize flow director filter rule list and hash */
1008         TAILQ_INIT(&fdir_info->fdir_list);
1009         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1010                  "fdir_%s", dev->data->name);
1011         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1012         if (!fdir_info->hash_table) {
1013                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1014                 return -EINVAL;
1015         }
1016         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1017                                           sizeof(struct i40e_fdir_filter *) *
1018                                           I40E_MAX_FDIR_FILTER_NUM,
1019                                           0);
1020         if (!fdir_info->hash_map) {
1021                 PMD_INIT_LOG(ERR,
1022                              "Failed to allocate memory for fdir hash map!");
1023                 ret = -ENOMEM;
1024                 goto err_fdir_hash_map_alloc;
1025         }
1026         return 0;
1027
1028 err_fdir_hash_map_alloc:
1029         rte_hash_free(fdir_info->hash_table);
1030
1031         return ret;
1032 }
1033
1034 static int
1035 eth_i40e_dev_init(struct rte_eth_dev *dev)
1036 {
1037         struct rte_pci_device *pci_dev;
1038         struct rte_intr_handle *intr_handle;
1039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041         struct i40e_vsi *vsi;
1042         int ret;
1043         uint32_t len;
1044         uint8_t aq_fail = 0;
1045
1046         PMD_INIT_FUNC_TRACE();
1047
1048         dev->dev_ops = &i40e_eth_dev_ops;
1049         dev->rx_pkt_burst = i40e_recv_pkts;
1050         dev->tx_pkt_burst = i40e_xmit_pkts;
1051         dev->tx_pkt_prepare = i40e_prep_pkts;
1052
1053         /* for secondary processes, we don't initialise any further as primary
1054          * has already done this work. Only check we don't need a different
1055          * RX function */
1056         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1057                 i40e_set_rx_function(dev);
1058                 i40e_set_tx_function(dev);
1059                 return 0;
1060         }
1061         pci_dev = I40E_DEV_TO_PCI(dev);
1062         intr_handle = &pci_dev->intr_handle;
1063
1064         rte_eth_copy_pci_info(dev, pci_dev);
1065         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1066
1067         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068         pf->adapter->eth_dev = dev;
1069         pf->dev_data = dev->data;
1070
1071         hw->back = I40E_PF_TO_ADAPTER(pf);
1072         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1073         if (!hw->hw_addr) {
1074                 PMD_INIT_LOG(ERR,
1075                         "Hardware is not available, as address is NULL");
1076                 return -ENODEV;
1077         }
1078
1079         hw->vendor_id = pci_dev->id.vendor_id;
1080         hw->device_id = pci_dev->id.device_id;
1081         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1082         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1083         hw->bus.device = pci_dev->addr.devid;
1084         hw->bus.func = pci_dev->addr.function;
1085         hw->adapter_stopped = 0;
1086
1087         /* Make sure all is clean before doing PF reset */
1088         i40e_clear_hw(hw);
1089
1090         /* Initialize the hardware */
1091         i40e_hw_init(dev);
1092
1093         /* Reset here to make sure all is clean for each PF */
1094         ret = i40e_pf_reset(hw);
1095         if (ret) {
1096                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1097                 return ret;
1098         }
1099
1100         /* Initialize the shared code (base driver) */
1101         ret = i40e_init_shared_code(hw);
1102         if (ret) {
1103                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1104                 return ret;
1105         }
1106
1107         /*
1108          * To work around the NVM issue, initialize registers
1109          * for flexible payload and packet type of QinQ by
1110          * software. It should be removed once issues are fixed
1111          * in NVM.
1112          */
1113         i40e_GLQF_reg_init(hw);
1114
1115         /* Initialize the input set for filters (hash and fd) to default value */
1116         i40e_filter_input_set_init(pf);
1117
1118         /* Initialize the parameters for adminq */
1119         i40e_init_adminq_parameter(hw);
1120         ret = i40e_init_adminq(hw);
1121         if (ret != I40E_SUCCESS) {
1122                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1123                 return -EIO;
1124         }
1125         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1126                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1127                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1128                      ((hw->nvm.version >> 12) & 0xf),
1129                      ((hw->nvm.version >> 4) & 0xff),
1130                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1131
1132         /* Need the special FW version to support floating VEB */
1133         config_floating_veb(dev);
1134         /* Clear PXE mode */
1135         i40e_clear_pxe_mode(hw);
1136         ret = i40e_dev_sync_phy_type(hw);
1137         if (ret) {
1138                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1139                 goto err_sync_phy_type;
1140         }
1141         /*
1142          * On X710, performance number is far from the expectation on recent
1143          * firmware versions. The fix for this issue may not be integrated in
1144          * the following firmware version. So the workaround in software driver
1145          * is needed. It needs to modify the initial values of 3 internal only
1146          * registers. Note that the workaround can be removed when it is fixed
1147          * in firmware in the future.
1148          */
1149         i40e_configure_registers(hw);
1150
1151         /* Get hw capabilities */
1152         ret = i40e_get_cap(hw);
1153         if (ret != I40E_SUCCESS) {
1154                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1155                 goto err_get_capabilities;
1156         }
1157
1158         /* Initialize parameters for PF */
1159         ret = i40e_pf_parameter_init(dev);
1160         if (ret != 0) {
1161                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1162                 goto err_parameter_init;
1163         }
1164
1165         /* Initialize the queue management */
1166         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1167         if (ret < 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1169                 goto err_qp_pool_init;
1170         }
1171         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1172                                 hw->func_caps.num_msix_vectors - 1);
1173         if (ret < 0) {
1174                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1175                 goto err_msix_pool_init;
1176         }
1177
1178         /* Initialize lan hmc */
1179         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1180                                 hw->func_caps.num_rx_qp, 0, 0);
1181         if (ret != I40E_SUCCESS) {
1182                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1183                 goto err_init_lan_hmc;
1184         }
1185
1186         /* Configure lan hmc */
1187         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1190                 goto err_configure_lan_hmc;
1191         }
1192
1193         /* Get and check the mac address */
1194         i40e_get_mac_addr(hw, hw->mac.addr);
1195         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "mac address is not valid");
1197                 ret = -EIO;
1198                 goto err_get_mac_addr;
1199         }
1200         /* Copy the permanent MAC address */
1201         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1202                         (struct ether_addr *) hw->mac.perm_addr);
1203
1204         /* Disable flow control */
1205         hw->fc.requested_mode = I40E_FC_NONE;
1206         i40e_set_fc(hw, &aq_fail, TRUE);
1207
1208         /* Set the global registers with default ether type value */
1209         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1210         if (ret != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR,
1212                         "Failed to set the default outer VLAN ether type");
1213                 goto err_setup_pf_switch;
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR,
1249                         "Failed to allocated memory for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* Init dcb to sw mode by default */
1256         ret = i40e_dcb_init_configure(dev, TRUE);
1257         if (ret != I40E_SUCCESS) {
1258                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1259                 pf->flags &= ~I40E_FLAG_DCB;
1260         }
1261         /* Update HW struct after DCB configuration */
1262         i40e_get_cap(hw);
1263
1264         /* initialize pf host driver to setup SRIOV resource if applicable */
1265         i40e_pf_host_init(dev);
1266
1267         /* register callback func to eal lib */
1268         rte_intr_callback_register(intr_handle,
1269                                    i40e_dev_interrupt_handler, dev);
1270
1271         /* configure and enable device interrupt */
1272         i40e_pf_config_irq0(hw, TRUE);
1273         i40e_pf_enable_irq0(hw);
1274
1275         /* enable uio intr after callback register */
1276         rte_intr_enable(intr_handle);
1277         /*
1278          * Add an ethertype filter to drop all flow control frames transmitted
1279          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1280          * frames to wire.
1281          */
1282         i40e_add_tx_flow_control_drop_filter(pf);
1283
1284         /* Set the max frame size to 0x2600 by default,
1285          * in case other drivers changed the default value.
1286          */
1287         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1288
1289         /* initialize mirror rule list */
1290         TAILQ_INIT(&pf->mirror_list);
1291
1292         ret = i40e_init_ethtype_filter_list(dev);
1293         if (ret < 0)
1294                 goto err_init_ethtype_filter_list;
1295         ret = i40e_init_tunnel_filter_list(dev);
1296         if (ret < 0)
1297                 goto err_init_tunnel_filter_list;
1298         ret = i40e_init_fdir_filter_list(dev);
1299         if (ret < 0)
1300                 goto err_init_fdir_filter_list;
1301
1302         return 0;
1303
1304 err_init_fdir_filter_list:
1305         rte_free(pf->tunnel.hash_table);
1306         rte_free(pf->tunnel.hash_map);
1307 err_init_tunnel_filter_list:
1308         rte_free(pf->ethertype.hash_table);
1309         rte_free(pf->ethertype.hash_map);
1310 err_init_ethtype_filter_list:
1311         rte_free(dev->data->mac_addrs);
1312 err_mac_alloc:
1313         i40e_vsi_release(pf->main_vsi);
1314 err_setup_pf_switch:
1315 err_get_mac_addr:
1316 err_configure_lan_hmc:
1317         (void)i40e_shutdown_lan_hmc(hw);
1318 err_init_lan_hmc:
1319         i40e_res_pool_destroy(&pf->msix_pool);
1320 err_msix_pool_init:
1321         i40e_res_pool_destroy(&pf->qp_pool);
1322 err_qp_pool_init:
1323 err_parameter_init:
1324 err_get_capabilities:
1325 err_sync_phy_type:
1326         (void)i40e_shutdown_adminq(hw);
1327
1328         return ret;
1329 }
1330
1331 static void
1332 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1333 {
1334         struct i40e_ethertype_filter *p_ethertype;
1335         struct i40e_ethertype_rule *ethertype_rule;
1336
1337         ethertype_rule = &pf->ethertype;
1338         /* Remove all ethertype filter rules and hash */
1339         if (ethertype_rule->hash_map)
1340                 rte_free(ethertype_rule->hash_map);
1341         if (ethertype_rule->hash_table)
1342                 rte_hash_free(ethertype_rule->hash_table);
1343
1344         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1345                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1346                              p_ethertype, rules);
1347                 rte_free(p_ethertype);
1348         }
1349 }
1350
1351 static void
1352 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1353 {
1354         struct i40e_tunnel_filter *p_tunnel;
1355         struct i40e_tunnel_rule *tunnel_rule;
1356
1357         tunnel_rule = &pf->tunnel;
1358         /* Remove all tunnel director rules and hash */
1359         if (tunnel_rule->hash_map)
1360                 rte_free(tunnel_rule->hash_map);
1361         if (tunnel_rule->hash_table)
1362                 rte_hash_free(tunnel_rule->hash_table);
1363
1364         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1365                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1366                 rte_free(p_tunnel);
1367         }
1368 }
1369
1370 static void
1371 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1372 {
1373         struct i40e_fdir_filter *p_fdir;
1374         struct i40e_fdir_info *fdir_info;
1375
1376         fdir_info = &pf->fdir;
1377         /* Remove all flow director rules and hash */
1378         if (fdir_info->hash_map)
1379                 rte_free(fdir_info->hash_map);
1380         if (fdir_info->hash_table)
1381                 rte_hash_free(fdir_info->hash_table);
1382
1383         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1384                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1385                 rte_free(p_fdir);
1386         }
1387 }
1388
1389 static int
1390 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1391 {
1392         struct i40e_pf *pf;
1393         struct rte_pci_device *pci_dev;
1394         struct rte_intr_handle *intr_handle;
1395         struct i40e_hw *hw;
1396         struct i40e_filter_control_settings settings;
1397         struct rte_flow *p_flow;
1398         int ret;
1399         uint8_t aq_fail = 0;
1400
1401         PMD_INIT_FUNC_TRACE();
1402
1403         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1404                 return 0;
1405
1406         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1407         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         pci_dev = I40E_DEV_TO_PCI(dev);
1409         intr_handle = &pci_dev->intr_handle;
1410
1411         if (hw->adapter_stopped == 0)
1412                 i40e_dev_close(dev);
1413
1414         dev->dev_ops = NULL;
1415         dev->rx_pkt_burst = NULL;
1416         dev->tx_pkt_burst = NULL;
1417
1418         /* Clear PXE mode */
1419         i40e_clear_pxe_mode(hw);
1420
1421         /* Unconfigure filter control */
1422         memset(&settings, 0, sizeof(settings));
1423         ret = i40e_set_filter_control(hw, &settings);
1424         if (ret)
1425                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1426                                         ret);
1427
1428         /* Disable flow control */
1429         hw->fc.requested_mode = I40E_FC_NONE;
1430         i40e_set_fc(hw, &aq_fail, TRUE);
1431
1432         /* uninitialize pf host driver */
1433         i40e_pf_host_uninit(dev);
1434
1435         rte_free(dev->data->mac_addrs);
1436         dev->data->mac_addrs = NULL;
1437
1438         /* disable uio intr before callback unregister */
1439         rte_intr_disable(intr_handle);
1440
1441         /* register callback func to eal lib */
1442         rte_intr_callback_unregister(intr_handle,
1443                                      i40e_dev_interrupt_handler, dev);
1444
1445         i40e_rm_ethtype_filter_list(pf);
1446         i40e_rm_tunnel_filter_list(pf);
1447         i40e_rm_fdir_filter_list(pf);
1448
1449         /* Remove all flows */
1450         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1451                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1452                 rte_free(p_flow);
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int
1459 i40e_dev_configure(struct rte_eth_dev *dev)
1460 {
1461         struct i40e_adapter *ad =
1462                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1464         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1465         int i, ret;
1466
1467         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1468          * bulk allocation or vector Rx preconditions we will reset it.
1469          */
1470         ad->rx_bulk_alloc_allowed = true;
1471         ad->rx_vec_allowed = true;
1472         ad->tx_simple_allowed = true;
1473         ad->tx_vec_allowed = true;
1474
1475         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1476                 ret = i40e_fdir_setup(pf);
1477                 if (ret != I40E_SUCCESS) {
1478                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1479                         return -ENOTSUP;
1480                 }
1481                 ret = i40e_fdir_configure(dev);
1482                 if (ret < 0) {
1483                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1484                         goto err;
1485                 }
1486         } else
1487                 i40e_fdir_teardown(pf);
1488
1489         ret = i40e_dev_init_vlan(dev);
1490         if (ret < 0)
1491                 goto err;
1492
1493         /* VMDQ setup.
1494          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1495          *  RSS setting have different requirements.
1496          *  General PMD driver call sequence are NIC init, configure,
1497          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1498          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1499          *  applicable. So, VMDQ setting has to be done before
1500          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1501          *  For RSS setting, it will try to calculate actual configured RX queue
1502          *  number, which will be available after rx_queue_setup(). dev_start()
1503          *  function is good to place RSS setup.
1504          */
1505         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1506                 ret = i40e_vmdq_setup(dev);
1507                 if (ret)
1508                         goto err;
1509         }
1510
1511         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1512                 ret = i40e_dcb_setup(dev);
1513                 if (ret) {
1514                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1515                         goto err_dcb;
1516                 }
1517         }
1518
1519         TAILQ_INIT(&pf->flow_list);
1520
1521         return 0;
1522
1523 err_dcb:
1524         /* need to release vmdq resource if exists */
1525         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1526                 i40e_vsi_release(pf->vmdq[i].vsi);
1527                 pf->vmdq[i].vsi = NULL;
1528         }
1529         rte_free(pf->vmdq);
1530         pf->vmdq = NULL;
1531 err:
1532         /* need to release fdir resource if exists */
1533         i40e_fdir_teardown(pf);
1534         return ret;
1535 }
1536
1537 void
1538 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1539 {
1540         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1541         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1544         uint16_t msix_vect = vsi->msix_intr;
1545         uint16_t i;
1546
1547         for (i = 0; i < vsi->nb_qps; i++) {
1548                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1549                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1550                 rte_wmb();
1551         }
1552
1553         if (vsi->type != I40E_VSI_SRIOV) {
1554                 if (!rte_intr_allow_others(intr_handle)) {
1555                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1556                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1557                         I40E_WRITE_REG(hw,
1558                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1559                                        0);
1560                 } else {
1561                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1562                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1563                         I40E_WRITE_REG(hw,
1564                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1565                                                        msix_vect - 1), 0);
1566                 }
1567         } else {
1568                 uint32_t reg;
1569                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1570                         vsi->user_param + (msix_vect - 1);
1571
1572                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1573                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1574         }
1575         I40E_WRITE_FLUSH(hw);
1576 }
1577
1578 static void
1579 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1580                        int base_queue, int nb_queue)
1581 {
1582         int i;
1583         uint32_t val;
1584         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1585
1586         /* Bind all RX queues to allocated MSIX interrupt */
1587         for (i = 0; i < nb_queue; i++) {
1588                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1589                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1590                         ((base_queue + i + 1) <<
1591                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1592                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1593                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1594
1595                 if (i == nb_queue - 1)
1596                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1597                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1598         }
1599
1600         /* Write first RX queue to Link list register as the head element */
1601         if (vsi->type != I40E_VSI_SRIOV) {
1602                 uint16_t interval =
1603                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1604
1605                 if (msix_vect == I40E_MISC_VEC_ID) {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1607                                        (base_queue <<
1608                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1609                                        (0x0 <<
1610                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1611                         I40E_WRITE_REG(hw,
1612                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1613                                        interval);
1614                 } else {
1615                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1616                                        (base_queue <<
1617                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1618                                        (0x0 <<
1619                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1622                                                        msix_vect - 1),
1623                                        interval);
1624                 }
1625         } else {
1626                 uint32_t reg;
1627
1628                 if (msix_vect == I40E_MISC_VEC_ID) {
1629                         I40E_WRITE_REG(hw,
1630                                        I40E_VPINT_LNKLST0(vsi->user_param),
1631                                        (base_queue <<
1632                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1633                                        (0x0 <<
1634                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1635                 } else {
1636                         /* num_msix_vectors_vf needs to minus irq0 */
1637                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1638                                 vsi->user_param + (msix_vect - 1);
1639
1640                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1641                                        (base_queue <<
1642                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1643                                        (0x0 <<
1644                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1645                 }
1646         }
1647
1648         I40E_WRITE_FLUSH(hw);
1649 }
1650
1651 void
1652 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1653 {
1654         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1655         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1656         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1657         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1658         uint16_t msix_vect = vsi->msix_intr;
1659         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1660         uint16_t queue_idx = 0;
1661         int record = 0;
1662         uint32_t val;
1663         int i;
1664
1665         for (i = 0; i < vsi->nb_qps; i++) {
1666                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1667                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1668         }
1669
1670         /* INTENA flag is not auto-cleared for interrupt */
1671         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1672         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1673                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1674                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1675         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1676
1677         /* VF bind interrupt */
1678         if (vsi->type == I40E_VSI_SRIOV) {
1679                 __vsi_queues_bind_intr(vsi, msix_vect,
1680                                        vsi->base_queue, vsi->nb_qps);
1681                 return;
1682         }
1683
1684         /* PF & VMDq bind interrupt */
1685         if (rte_intr_dp_is_en(intr_handle)) {
1686                 if (vsi->type == I40E_VSI_MAIN) {
1687                         queue_idx = 0;
1688                         record = 1;
1689                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1690                         struct i40e_vsi *main_vsi =
1691                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1692                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1693                         record = 1;
1694                 }
1695         }
1696
1697         for (i = 0; i < vsi->nb_used_qps; i++) {
1698                 if (nb_msix <= 1) {
1699                         if (!rte_intr_allow_others(intr_handle))
1700                                 /* allow to share MISC_VEC_ID */
1701                                 msix_vect = I40E_MISC_VEC_ID;
1702
1703                         /* no enough msix_vect, map all to one */
1704                         __vsi_queues_bind_intr(vsi, msix_vect,
1705                                                vsi->base_queue + i,
1706                                                vsi->nb_used_qps - i);
1707                         for (; !!record && i < vsi->nb_used_qps; i++)
1708                                 intr_handle->intr_vec[queue_idx + i] =
1709                                         msix_vect;
1710                         break;
1711                 }
1712                 /* 1:1 queue/msix_vect mapping */
1713                 __vsi_queues_bind_intr(vsi, msix_vect,
1714                                        vsi->base_queue + i, 1);
1715                 if (!!record)
1716                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1717
1718                 msix_vect++;
1719                 nb_msix--;
1720         }
1721 }
1722
1723 static void
1724 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1725 {
1726         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1727         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1728         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1730         uint16_t interval = i40e_calc_itr_interval(\
1731                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1732         uint16_t msix_intr, i;
1733
1734         if (rte_intr_allow_others(intr_handle))
1735                 for (i = 0; i < vsi->nb_msix; i++) {
1736                         msix_intr = vsi->msix_intr + i;
1737                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1738                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1739                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1740                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1741                                 (interval <<
1742                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1743                 }
1744         else
1745                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1746                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1747                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1748                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1749                                (interval <<
1750                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1751
1752         I40E_WRITE_FLUSH(hw);
1753 }
1754
1755 static void
1756 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1757 {
1758         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1760         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762         uint16_t msix_intr, i;
1763
1764         if (rte_intr_allow_others(intr_handle))
1765                 for (i = 0; i < vsi->nb_msix; i++) {
1766                         msix_intr = vsi->msix_intr + i;
1767                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1768                                        0);
1769                 }
1770         else
1771                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1772
1773         I40E_WRITE_FLUSH(hw);
1774 }
1775
1776 static inline uint8_t
1777 i40e_parse_link_speeds(uint16_t link_speeds)
1778 {
1779         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1780
1781         if (link_speeds & ETH_LINK_SPEED_40G)
1782                 link_speed |= I40E_LINK_SPEED_40GB;
1783         if (link_speeds & ETH_LINK_SPEED_25G)
1784                 link_speed |= I40E_LINK_SPEED_25GB;
1785         if (link_speeds & ETH_LINK_SPEED_20G)
1786                 link_speed |= I40E_LINK_SPEED_20GB;
1787         if (link_speeds & ETH_LINK_SPEED_10G)
1788                 link_speed |= I40E_LINK_SPEED_10GB;
1789         if (link_speeds & ETH_LINK_SPEED_1G)
1790                 link_speed |= I40E_LINK_SPEED_1GB;
1791         if (link_speeds & ETH_LINK_SPEED_100M)
1792                 link_speed |= I40E_LINK_SPEED_100MB;
1793
1794         return link_speed;
1795 }
1796
1797 static int
1798 i40e_phy_conf_link(struct i40e_hw *hw,
1799                    uint8_t abilities,
1800                    uint8_t force_speed)
1801 {
1802         enum i40e_status_code status;
1803         struct i40e_aq_get_phy_abilities_resp phy_ab;
1804         struct i40e_aq_set_phy_config phy_conf;
1805         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1806                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1807                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1808                         I40E_AQ_PHY_FLAG_LOW_POWER;
1809         const uint8_t advt = I40E_LINK_SPEED_40GB |
1810                         I40E_LINK_SPEED_25GB |
1811                         I40E_LINK_SPEED_10GB |
1812                         I40E_LINK_SPEED_1GB |
1813                         I40E_LINK_SPEED_100MB;
1814         int ret = -ENOTSUP;
1815
1816
1817         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1818                                               NULL);
1819         if (status)
1820                 return ret;
1821
1822         memset(&phy_conf, 0, sizeof(phy_conf));
1823
1824         /* bits 0-2 use the values from get_phy_abilities_resp */
1825         abilities &= ~mask;
1826         abilities |= phy_ab.abilities & mask;
1827
1828         /* update ablities and speed */
1829         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1830                 phy_conf.link_speed = advt;
1831         else
1832                 phy_conf.link_speed = force_speed;
1833
1834         phy_conf.abilities = abilities;
1835
1836         /* use get_phy_abilities_resp value for the rest */
1837         phy_conf.phy_type = phy_ab.phy_type;
1838         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1839         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1840         phy_conf.eee_capability = phy_ab.eee_capability;
1841         phy_conf.eeer = phy_ab.eeer_val;
1842         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1843
1844         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1845                     phy_ab.abilities, phy_ab.link_speed);
1846         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1847                     phy_conf.abilities, phy_conf.link_speed);
1848
1849         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1850         if (status)
1851                 return ret;
1852
1853         return I40E_SUCCESS;
1854 }
1855
1856 static int
1857 i40e_apply_link_speed(struct rte_eth_dev *dev)
1858 {
1859         uint8_t speed;
1860         uint8_t abilities = 0;
1861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         struct rte_eth_conf *conf = &dev->data->dev_conf;
1863
1864         speed = i40e_parse_link_speeds(conf->link_speeds);
1865         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1866         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1867                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1868         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1869
1870         /* Skip changing speed on 40G interfaces, FW does not support */
1871         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1872                 speed =  I40E_LINK_SPEED_UNKNOWN;
1873                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1874         }
1875
1876         return i40e_phy_conf_link(hw, abilities, speed);
1877 }
1878
1879 static int
1880 i40e_dev_start(struct rte_eth_dev *dev)
1881 {
1882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         struct i40e_vsi *main_vsi = pf->main_vsi;
1885         int ret, i;
1886         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1887         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1888         uint32_t intr_vector = 0;
1889         struct i40e_vsi *vsi;
1890
1891         hw->adapter_stopped = 0;
1892
1893         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1894                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1895                              dev->data->port_id);
1896                 return -EINVAL;
1897         }
1898
1899         rte_intr_disable(intr_handle);
1900
1901         if ((rte_intr_cap_multiple(intr_handle) ||
1902              !RTE_ETH_DEV_SRIOV(dev).active) &&
1903             dev->data->dev_conf.intr_conf.rxq != 0) {
1904                 intr_vector = dev->data->nb_rx_queues;
1905                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1906                 if (ret)
1907                         return ret;
1908         }
1909
1910         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1911                 intr_handle->intr_vec =
1912                         rte_zmalloc("intr_vec",
1913                                     dev->data->nb_rx_queues * sizeof(int),
1914                                     0);
1915                 if (!intr_handle->intr_vec) {
1916                         PMD_INIT_LOG(ERR,
1917                                 "Failed to allocate %d rx_queues intr_vec",
1918                                 dev->data->nb_rx_queues);
1919                         return -ENOMEM;
1920                 }
1921         }
1922
1923         /* Initialize VSI */
1924         ret = i40e_dev_rxtx_init(pf);
1925         if (ret != I40E_SUCCESS) {
1926                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1927                 goto err_up;
1928         }
1929
1930         /* Map queues with MSIX interrupt */
1931         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1932                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1933         i40e_vsi_queues_bind_intr(main_vsi);
1934         i40e_vsi_enable_queues_intr(main_vsi);
1935
1936         /* Map VMDQ VSI queues with MSIX interrupt */
1937         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1938                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1939                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1940                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1941         }
1942
1943         /* enable FDIR MSIX interrupt */
1944         if (pf->fdir.fdir_vsi) {
1945                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1946                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1947         }
1948
1949         /* Enable all queues which have been configured */
1950         ret = i40e_dev_switch_queues(pf, TRUE);
1951         if (ret != I40E_SUCCESS) {
1952                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1953                 goto err_up;
1954         }
1955
1956         /* Enable receiving broadcast packets */
1957         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1958         if (ret != I40E_SUCCESS)
1959                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1960
1961         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1962                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1963                                                 true, NULL);
1964                 if (ret != I40E_SUCCESS)
1965                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1966         }
1967
1968         /* Enable the VLAN promiscuous mode. */
1969         if (pf->vfs) {
1970                 for (i = 0; i < pf->vf_num; i++) {
1971                         vsi = pf->vfs[i].vsi;
1972                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1973                                                      true, NULL);
1974                 }
1975         }
1976
1977         /* Apply link configure */
1978         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1979                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1980                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1981                                 ETH_LINK_SPEED_40G)) {
1982                 PMD_DRV_LOG(ERR, "Invalid link setting");
1983                 goto err_up;
1984         }
1985         ret = i40e_apply_link_speed(dev);
1986         if (I40E_SUCCESS != ret) {
1987                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1988                 goto err_up;
1989         }
1990
1991         if (!rte_intr_allow_others(intr_handle)) {
1992                 rte_intr_callback_unregister(intr_handle,
1993                                              i40e_dev_interrupt_handler,
1994                                              (void *)dev);
1995                 /* configure and enable device interrupt */
1996                 i40e_pf_config_irq0(hw, FALSE);
1997                 i40e_pf_enable_irq0(hw);
1998
1999                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2000                         PMD_INIT_LOG(INFO,
2001                                 "lsc won't enable because of no intr multiplex");
2002         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2003                 ret = i40e_aq_set_phy_int_mask(hw,
2004                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2005                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2006                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2007                 if (ret != I40E_SUCCESS)
2008                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2009
2010                 /* Call get_link_info aq commond to enable LSE */
2011                 i40e_dev_link_update(dev, 0);
2012         }
2013
2014         /* enable uio intr after callback register */
2015         rte_intr_enable(intr_handle);
2016
2017         i40e_filter_restore(pf);
2018
2019         return I40E_SUCCESS;
2020
2021 err_up:
2022         i40e_dev_switch_queues(pf, FALSE);
2023         i40e_dev_clear_queues(dev);
2024
2025         return ret;
2026 }
2027
2028 static void
2029 i40e_dev_stop(struct rte_eth_dev *dev)
2030 {
2031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032         struct i40e_vsi *main_vsi = pf->main_vsi;
2033         struct i40e_mirror_rule *p_mirror;
2034         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2035         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2036         int i;
2037
2038         /* Disable all queues */
2039         i40e_dev_switch_queues(pf, FALSE);
2040
2041         /* un-map queues with interrupt registers */
2042         i40e_vsi_disable_queues_intr(main_vsi);
2043         i40e_vsi_queues_unbind_intr(main_vsi);
2044
2045         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2046                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2047                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2048         }
2049
2050         if (pf->fdir.fdir_vsi) {
2051                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2052                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2053         }
2054         /* Clear all queues and release memory */
2055         i40e_dev_clear_queues(dev);
2056
2057         /* Set link down */
2058         i40e_dev_set_link_down(dev);
2059
2060         /* Remove all mirror rules */
2061         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2062                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2063                 rte_free(p_mirror);
2064         }
2065         pf->nb_mirror_rule = 0;
2066
2067         if (!rte_intr_allow_others(intr_handle))
2068                 /* resume to the default handler */
2069                 rte_intr_callback_register(intr_handle,
2070                                            i40e_dev_interrupt_handler,
2071                                            (void *)dev);
2072
2073         /* Clean datapath event and queue/vec mapping */
2074         rte_intr_efd_disable(intr_handle);
2075         if (intr_handle->intr_vec) {
2076                 rte_free(intr_handle->intr_vec);
2077                 intr_handle->intr_vec = NULL;
2078         }
2079 }
2080
2081 static void
2082 i40e_dev_close(struct rte_eth_dev *dev)
2083 {
2084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2087         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2088         uint32_t reg;
2089         int i;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         i40e_dev_stop(dev);
2094         hw->adapter_stopped = 1;
2095         i40e_dev_free_queues(dev);
2096
2097         /* Disable interrupt */
2098         i40e_pf_disable_irq0(hw);
2099         rte_intr_disable(intr_handle);
2100
2101         /* shutdown and destroy the HMC */
2102         i40e_shutdown_lan_hmc(hw);
2103
2104         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2105                 i40e_vsi_release(pf->vmdq[i].vsi);
2106                 pf->vmdq[i].vsi = NULL;
2107         }
2108         rte_free(pf->vmdq);
2109         pf->vmdq = NULL;
2110
2111         /* release all the existing VSIs and VEBs */
2112         i40e_fdir_teardown(pf);
2113         i40e_vsi_release(pf->main_vsi);
2114
2115         /* shutdown the adminq */
2116         i40e_aq_queue_shutdown(hw, true);
2117         i40e_shutdown_adminq(hw);
2118
2119         i40e_res_pool_destroy(&pf->qp_pool);
2120         i40e_res_pool_destroy(&pf->msix_pool);
2121
2122         /* force a PF reset to clean anything leftover */
2123         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2124         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2125                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2126         I40E_WRITE_FLUSH(hw);
2127 }
2128
2129 static void
2130 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2131 {
2132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct i40e_vsi *vsi = pf->main_vsi;
2135         int status;
2136
2137         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2138                                                      true, NULL, true);
2139         if (status != I40E_SUCCESS)
2140                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2141
2142         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2143                                                         TRUE, NULL);
2144         if (status != I40E_SUCCESS)
2145                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2146
2147 }
2148
2149 static void
2150 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2151 {
2152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         struct i40e_vsi *vsi = pf->main_vsi;
2155         int status;
2156
2157         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2158                                                      false, NULL, true);
2159         if (status != I40E_SUCCESS)
2160                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2161
2162         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2163                                                         false, NULL);
2164         if (status != I40E_SUCCESS)
2165                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2166 }
2167
2168 static void
2169 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2170 {
2171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct i40e_vsi *vsi = pf->main_vsi;
2174         int ret;
2175
2176         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2177         if (ret != I40E_SUCCESS)
2178                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2179 }
2180
2181 static void
2182 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2183 {
2184         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         struct i40e_vsi *vsi = pf->main_vsi;
2187         int ret;
2188
2189         if (dev->data->promiscuous == 1)
2190                 return; /* must remain in all_multicast mode */
2191
2192         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2193                                 vsi->seid, FALSE, NULL);
2194         if (ret != I40E_SUCCESS)
2195                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2196 }
2197
2198 /*
2199  * Set device link up.
2200  */
2201 static int
2202 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2203 {
2204         /* re-apply link speed setting */
2205         return i40e_apply_link_speed(dev);
2206 }
2207
2208 /*
2209  * Set device link down.
2210  */
2211 static int
2212 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2213 {
2214         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2215         uint8_t abilities = 0;
2216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217
2218         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2219         return i40e_phy_conf_link(hw, abilities, speed);
2220 }
2221
2222 int
2223 i40e_dev_link_update(struct rte_eth_dev *dev,
2224                      int wait_to_complete)
2225 {
2226 #define CHECK_INTERVAL 100  /* 100ms */
2227 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229         struct i40e_link_status link_status;
2230         struct rte_eth_link link, old;
2231         int status;
2232         unsigned rep_cnt = MAX_REPEAT_TIME;
2233         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2234
2235         memset(&link, 0, sizeof(link));
2236         memset(&old, 0, sizeof(old));
2237         memset(&link_status, 0, sizeof(link_status));
2238         rte_i40e_dev_atomic_read_link_status(dev, &old);
2239
2240         do {
2241                 /* Get link status information from hardware */
2242                 status = i40e_aq_get_link_info(hw, enable_lse,
2243                                                 &link_status, NULL);
2244                 if (status != I40E_SUCCESS) {
2245                         link.link_speed = ETH_SPEED_NUM_100M;
2246                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2247                         PMD_DRV_LOG(ERR, "Failed to get link info");
2248                         goto out;
2249                 }
2250
2251                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2252                 if (!wait_to_complete || link.link_status)
2253                         break;
2254
2255                 rte_delay_ms(CHECK_INTERVAL);
2256         } while (--rep_cnt);
2257
2258         if (!link.link_status)
2259                 goto out;
2260
2261         /* i40e uses full duplex only */
2262         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2263
2264         /* Parse the link status */
2265         switch (link_status.link_speed) {
2266         case I40E_LINK_SPEED_100MB:
2267                 link.link_speed = ETH_SPEED_NUM_100M;
2268                 break;
2269         case I40E_LINK_SPEED_1GB:
2270                 link.link_speed = ETH_SPEED_NUM_1G;
2271                 break;
2272         case I40E_LINK_SPEED_10GB:
2273                 link.link_speed = ETH_SPEED_NUM_10G;
2274                 break;
2275         case I40E_LINK_SPEED_20GB:
2276                 link.link_speed = ETH_SPEED_NUM_20G;
2277                 break;
2278         case I40E_LINK_SPEED_25GB:
2279                 link.link_speed = ETH_SPEED_NUM_25G;
2280                 break;
2281         case I40E_LINK_SPEED_40GB:
2282                 link.link_speed = ETH_SPEED_NUM_40G;
2283                 break;
2284         default:
2285                 link.link_speed = ETH_SPEED_NUM_100M;
2286                 break;
2287         }
2288
2289         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2290                         ETH_LINK_SPEED_FIXED);
2291
2292 out:
2293         rte_i40e_dev_atomic_write_link_status(dev, &link);
2294         if (link.link_status == old.link_status)
2295                 return -1;
2296
2297         return 0;
2298 }
2299
2300 /* Get all the statistics of a VSI */
2301 void
2302 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2303 {
2304         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2305         struct i40e_eth_stats *nes = &vsi->eth_stats;
2306         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2307         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2308
2309         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2310                             vsi->offset_loaded, &oes->rx_bytes,
2311                             &nes->rx_bytes);
2312         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2313                             vsi->offset_loaded, &oes->rx_unicast,
2314                             &nes->rx_unicast);
2315         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2316                             vsi->offset_loaded, &oes->rx_multicast,
2317                             &nes->rx_multicast);
2318         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2319                             vsi->offset_loaded, &oes->rx_broadcast,
2320                             &nes->rx_broadcast);
2321         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2322                             &oes->rx_discards, &nes->rx_discards);
2323         /* GLV_REPC not supported */
2324         /* GLV_RMPC not supported */
2325         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2326                             &oes->rx_unknown_protocol,
2327                             &nes->rx_unknown_protocol);
2328         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2329                             vsi->offset_loaded, &oes->tx_bytes,
2330                             &nes->tx_bytes);
2331         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2332                             vsi->offset_loaded, &oes->tx_unicast,
2333                             &nes->tx_unicast);
2334         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2335                             vsi->offset_loaded, &oes->tx_multicast,
2336                             &nes->tx_multicast);
2337         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2338                             vsi->offset_loaded,  &oes->tx_broadcast,
2339                             &nes->tx_broadcast);
2340         /* GLV_TDPC not supported */
2341         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2342                             &oes->tx_errors, &nes->tx_errors);
2343         vsi->offset_loaded = true;
2344
2345         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2346                     vsi->vsi_id);
2347         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2348         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2349         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2350         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2351         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2352         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2353                     nes->rx_unknown_protocol);
2354         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2355         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2356         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2357         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2358         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2359         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2360         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2361                     vsi->vsi_id);
2362 }
2363
2364 static void
2365 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2366 {
2367         unsigned int i;
2368         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2369         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2370
2371         /* Get statistics of struct i40e_eth_stats */
2372         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2373                             I40E_GLPRT_GORCL(hw->port),
2374                             pf->offset_loaded, &os->eth.rx_bytes,
2375                             &ns->eth.rx_bytes);
2376         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2377                             I40E_GLPRT_UPRCL(hw->port),
2378                             pf->offset_loaded, &os->eth.rx_unicast,
2379                             &ns->eth.rx_unicast);
2380         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2381                             I40E_GLPRT_MPRCL(hw->port),
2382                             pf->offset_loaded, &os->eth.rx_multicast,
2383                             &ns->eth.rx_multicast);
2384         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2385                             I40E_GLPRT_BPRCL(hw->port),
2386                             pf->offset_loaded, &os->eth.rx_broadcast,
2387                             &ns->eth.rx_broadcast);
2388         /* Workaround: CRC size should not be included in byte statistics,
2389          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2390          */
2391         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2392                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2393
2394         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2395                             pf->offset_loaded, &os->eth.rx_discards,
2396                             &ns->eth.rx_discards);
2397         /* GLPRT_REPC not supported */
2398         /* GLPRT_RMPC not supported */
2399         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2400                             pf->offset_loaded,
2401                             &os->eth.rx_unknown_protocol,
2402                             &ns->eth.rx_unknown_protocol);
2403         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2404                             I40E_GLPRT_GOTCL(hw->port),
2405                             pf->offset_loaded, &os->eth.tx_bytes,
2406                             &ns->eth.tx_bytes);
2407         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2408                             I40E_GLPRT_UPTCL(hw->port),
2409                             pf->offset_loaded, &os->eth.tx_unicast,
2410                             &ns->eth.tx_unicast);
2411         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2412                             I40E_GLPRT_MPTCL(hw->port),
2413                             pf->offset_loaded, &os->eth.tx_multicast,
2414                             &ns->eth.tx_multicast);
2415         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2416                             I40E_GLPRT_BPTCL(hw->port),
2417                             pf->offset_loaded, &os->eth.tx_broadcast,
2418                             &ns->eth.tx_broadcast);
2419         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2420                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2421         /* GLPRT_TEPC not supported */
2422
2423         /* additional port specific stats */
2424         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2425                             pf->offset_loaded, &os->tx_dropped_link_down,
2426                             &ns->tx_dropped_link_down);
2427         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2428                             pf->offset_loaded, &os->crc_errors,
2429                             &ns->crc_errors);
2430         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2431                             pf->offset_loaded, &os->illegal_bytes,
2432                             &ns->illegal_bytes);
2433         /* GLPRT_ERRBC not supported */
2434         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2435                             pf->offset_loaded, &os->mac_local_faults,
2436                             &ns->mac_local_faults);
2437         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2438                             pf->offset_loaded, &os->mac_remote_faults,
2439                             &ns->mac_remote_faults);
2440         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2441                             pf->offset_loaded, &os->rx_length_errors,
2442                             &ns->rx_length_errors);
2443         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2444                             pf->offset_loaded, &os->link_xon_rx,
2445                             &ns->link_xon_rx);
2446         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2447                             pf->offset_loaded, &os->link_xoff_rx,
2448                             &ns->link_xoff_rx);
2449         for (i = 0; i < 8; i++) {
2450                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2451                                     pf->offset_loaded,
2452                                     &os->priority_xon_rx[i],
2453                                     &ns->priority_xon_rx[i]);
2454                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2455                                     pf->offset_loaded,
2456                                     &os->priority_xoff_rx[i],
2457                                     &ns->priority_xoff_rx[i]);
2458         }
2459         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2460                             pf->offset_loaded, &os->link_xon_tx,
2461                             &ns->link_xon_tx);
2462         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2463                             pf->offset_loaded, &os->link_xoff_tx,
2464                             &ns->link_xoff_tx);
2465         for (i = 0; i < 8; i++) {
2466                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2467                                     pf->offset_loaded,
2468                                     &os->priority_xon_tx[i],
2469                                     &ns->priority_xon_tx[i]);
2470                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2471                                     pf->offset_loaded,
2472                                     &os->priority_xoff_tx[i],
2473                                     &ns->priority_xoff_tx[i]);
2474                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2475                                     pf->offset_loaded,
2476                                     &os->priority_xon_2_xoff[i],
2477                                     &ns->priority_xon_2_xoff[i]);
2478         }
2479         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2480                             I40E_GLPRT_PRC64L(hw->port),
2481                             pf->offset_loaded, &os->rx_size_64,
2482                             &ns->rx_size_64);
2483         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2484                             I40E_GLPRT_PRC127L(hw->port),
2485                             pf->offset_loaded, &os->rx_size_127,
2486                             &ns->rx_size_127);
2487         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2488                             I40E_GLPRT_PRC255L(hw->port),
2489                             pf->offset_loaded, &os->rx_size_255,
2490                             &ns->rx_size_255);
2491         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2492                             I40E_GLPRT_PRC511L(hw->port),
2493                             pf->offset_loaded, &os->rx_size_511,
2494                             &ns->rx_size_511);
2495         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2496                             I40E_GLPRT_PRC1023L(hw->port),
2497                             pf->offset_loaded, &os->rx_size_1023,
2498                             &ns->rx_size_1023);
2499         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2500                             I40E_GLPRT_PRC1522L(hw->port),
2501                             pf->offset_loaded, &os->rx_size_1522,
2502                             &ns->rx_size_1522);
2503         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2504                             I40E_GLPRT_PRC9522L(hw->port),
2505                             pf->offset_loaded, &os->rx_size_big,
2506                             &ns->rx_size_big);
2507         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2508                             pf->offset_loaded, &os->rx_undersize,
2509                             &ns->rx_undersize);
2510         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2511                             pf->offset_loaded, &os->rx_fragments,
2512                             &ns->rx_fragments);
2513         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2514                             pf->offset_loaded, &os->rx_oversize,
2515                             &ns->rx_oversize);
2516         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2517                             pf->offset_loaded, &os->rx_jabber,
2518                             &ns->rx_jabber);
2519         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2520                             I40E_GLPRT_PTC64L(hw->port),
2521                             pf->offset_loaded, &os->tx_size_64,
2522                             &ns->tx_size_64);
2523         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2524                             I40E_GLPRT_PTC127L(hw->port),
2525                             pf->offset_loaded, &os->tx_size_127,
2526                             &ns->tx_size_127);
2527         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2528                             I40E_GLPRT_PTC255L(hw->port),
2529                             pf->offset_loaded, &os->tx_size_255,
2530                             &ns->tx_size_255);
2531         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2532                             I40E_GLPRT_PTC511L(hw->port),
2533                             pf->offset_loaded, &os->tx_size_511,
2534                             &ns->tx_size_511);
2535         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2536                             I40E_GLPRT_PTC1023L(hw->port),
2537                             pf->offset_loaded, &os->tx_size_1023,
2538                             &ns->tx_size_1023);
2539         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2540                             I40E_GLPRT_PTC1522L(hw->port),
2541                             pf->offset_loaded, &os->tx_size_1522,
2542                             &ns->tx_size_1522);
2543         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2544                             I40E_GLPRT_PTC9522L(hw->port),
2545                             pf->offset_loaded, &os->tx_size_big,
2546                             &ns->tx_size_big);
2547         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2548                            pf->offset_loaded,
2549                            &os->fd_sb_match, &ns->fd_sb_match);
2550         /* GLPRT_MSPDC not supported */
2551         /* GLPRT_XEC not supported */
2552
2553         pf->offset_loaded = true;
2554
2555         if (pf->main_vsi)
2556                 i40e_update_vsi_stats(pf->main_vsi);
2557 }
2558
2559 /* Get all statistics of a port */
2560 static void
2561 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2562 {
2563         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2566         unsigned i;
2567
2568         /* call read registers - updates values, now write them to struct */
2569         i40e_read_stats_registers(pf, hw);
2570
2571         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2572                         pf->main_vsi->eth_stats.rx_multicast +
2573                         pf->main_vsi->eth_stats.rx_broadcast -
2574                         pf->main_vsi->eth_stats.rx_discards;
2575         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2576                         pf->main_vsi->eth_stats.tx_multicast +
2577                         pf->main_vsi->eth_stats.tx_broadcast;
2578         stats->ibytes   = ns->eth.rx_bytes;
2579         stats->obytes   = ns->eth.tx_bytes;
2580         stats->oerrors  = ns->eth.tx_errors +
2581                         pf->main_vsi->eth_stats.tx_errors;
2582
2583         /* Rx Errors */
2584         stats->imissed  = ns->eth.rx_discards +
2585                         pf->main_vsi->eth_stats.rx_discards;
2586         stats->ierrors  = ns->crc_errors +
2587                         ns->rx_length_errors + ns->rx_undersize +
2588                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2589
2590         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2591         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2592         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2593         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2594         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2595         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2596         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2597                     ns->eth.rx_unknown_protocol);
2598         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2599         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2600         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2601         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2602         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2603         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2604
2605         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2606                     ns->tx_dropped_link_down);
2607         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2608         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2609                     ns->illegal_bytes);
2610         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2611         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2612                     ns->mac_local_faults);
2613         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2614                     ns->mac_remote_faults);
2615         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2616                     ns->rx_length_errors);
2617         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2618         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2619         for (i = 0; i < 8; i++) {
2620                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2621                                 i, ns->priority_xon_rx[i]);
2622                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2623                                 i, ns->priority_xoff_rx[i]);
2624         }
2625         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2626         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2627         for (i = 0; i < 8; i++) {
2628                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2629                                 i, ns->priority_xon_tx[i]);
2630                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2631                                 i, ns->priority_xoff_tx[i]);
2632                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2633                                 i, ns->priority_xon_2_xoff[i]);
2634         }
2635         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2636         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2637         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2638         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2639         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2640         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2641         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2642         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2643         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2644         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2645         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2646         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2647         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2648         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2649         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2650         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2651         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2652         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2653         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2654                         ns->mac_short_packet_dropped);
2655         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2656                     ns->checksum_error);
2657         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2658         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2659 }
2660
2661 /* Reset the statistics */
2662 static void
2663 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2664 {
2665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667
2668         /* Mark PF and VSI stats to update the offset, aka "reset" */
2669         pf->offset_loaded = false;
2670         if (pf->main_vsi)
2671                 pf->main_vsi->offset_loaded = false;
2672
2673         /* read the stats, reading current register values into offset */
2674         i40e_read_stats_registers(pf, hw);
2675 }
2676
2677 static uint32_t
2678 i40e_xstats_calc_num(void)
2679 {
2680         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2681                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2682                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2683 }
2684
2685 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2686                                      struct rte_eth_xstat_name *xstats_names,
2687                                      __rte_unused unsigned limit)
2688 {
2689         unsigned count = 0;
2690         unsigned i, prio;
2691
2692         if (xstats_names == NULL)
2693                 return i40e_xstats_calc_num();
2694
2695         /* Note: limit checked in rte_eth_xstats_names() */
2696
2697         /* Get stats from i40e_eth_stats struct */
2698         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2699                 snprintf(xstats_names[count].name,
2700                          sizeof(xstats_names[count].name),
2701                          "%s", rte_i40e_stats_strings[i].name);
2702                 count++;
2703         }
2704
2705         /* Get individiual stats from i40e_hw_port struct */
2706         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2707                 snprintf(xstats_names[count].name,
2708                         sizeof(xstats_names[count].name),
2709                          "%s", rte_i40e_hw_port_strings[i].name);
2710                 count++;
2711         }
2712
2713         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2714                 for (prio = 0; prio < 8; prio++) {
2715                         snprintf(xstats_names[count].name,
2716                                  sizeof(xstats_names[count].name),
2717                                  "rx_priority%u_%s", prio,
2718                                  rte_i40e_rxq_prio_strings[i].name);
2719                         count++;
2720                 }
2721         }
2722
2723         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2724                 for (prio = 0; prio < 8; prio++) {
2725                         snprintf(xstats_names[count].name,
2726                                  sizeof(xstats_names[count].name),
2727                                  "tx_priority%u_%s", prio,
2728                                  rte_i40e_txq_prio_strings[i].name);
2729                         count++;
2730                 }
2731         }
2732         return count;
2733 }
2734
2735 static int
2736 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2737                     unsigned n)
2738 {
2739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741         unsigned i, count, prio;
2742         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2743
2744         count = i40e_xstats_calc_num();
2745         if (n < count)
2746                 return count;
2747
2748         i40e_read_stats_registers(pf, hw);
2749
2750         if (xstats == NULL)
2751                 return 0;
2752
2753         count = 0;
2754
2755         /* Get stats from i40e_eth_stats struct */
2756         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2757                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2758                         rte_i40e_stats_strings[i].offset);
2759                 xstats[count].id = count;
2760                 count++;
2761         }
2762
2763         /* Get individiual stats from i40e_hw_port struct */
2764         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2765                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2766                         rte_i40e_hw_port_strings[i].offset);
2767                 xstats[count].id = count;
2768                 count++;
2769         }
2770
2771         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2772                 for (prio = 0; prio < 8; prio++) {
2773                         xstats[count].value =
2774                                 *(uint64_t *)(((char *)hw_stats) +
2775                                 rte_i40e_rxq_prio_strings[i].offset +
2776                                 (sizeof(uint64_t) * prio));
2777                         xstats[count].id = count;
2778                         count++;
2779                 }
2780         }
2781
2782         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2783                 for (prio = 0; prio < 8; prio++) {
2784                         xstats[count].value =
2785                                 *(uint64_t *)(((char *)hw_stats) +
2786                                 rte_i40e_txq_prio_strings[i].offset +
2787                                 (sizeof(uint64_t) * prio));
2788                         xstats[count].id = count;
2789                         count++;
2790                 }
2791         }
2792
2793         return count;
2794 }
2795
2796 static int
2797 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2798                                  __rte_unused uint16_t queue_id,
2799                                  __rte_unused uint8_t stat_idx,
2800                                  __rte_unused uint8_t is_rx)
2801 {
2802         PMD_INIT_FUNC_TRACE();
2803
2804         return -ENOSYS;
2805 }
2806
2807 static int
2808 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2809 {
2810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         u32 full_ver;
2812         u8 ver, patch;
2813         u16 build;
2814         int ret;
2815
2816         full_ver = hw->nvm.oem_ver;
2817         ver = (u8)(full_ver >> 24);
2818         build = (u16)((full_ver >> 8) & 0xffff);
2819         patch = (u8)(full_ver & 0xff);
2820
2821         ret = snprintf(fw_version, fw_size,
2822                  "%d.%d%d 0x%08x %d.%d.%d",
2823                  ((hw->nvm.version >> 12) & 0xf),
2824                  ((hw->nvm.version >> 4) & 0xff),
2825                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2826                  ver, build, patch);
2827
2828         ret += 1; /* add the size of '\0' */
2829         if (fw_size < (u32)ret)
2830                 return ret;
2831         else
2832                 return 0;
2833 }
2834
2835 static void
2836 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2837 {
2838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         struct i40e_vsi *vsi = pf->main_vsi;
2841         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2842
2843         dev_info->pci_dev = pci_dev;
2844         dev_info->max_rx_queues = vsi->nb_qps;
2845         dev_info->max_tx_queues = vsi->nb_qps;
2846         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2847         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2848         dev_info->max_mac_addrs = vsi->max_macaddrs;
2849         dev_info->max_vfs = pci_dev->max_vfs;
2850         dev_info->rx_offload_capa =
2851                 DEV_RX_OFFLOAD_VLAN_STRIP |
2852                 DEV_RX_OFFLOAD_QINQ_STRIP |
2853                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2854                 DEV_RX_OFFLOAD_UDP_CKSUM |
2855                 DEV_RX_OFFLOAD_TCP_CKSUM;
2856         dev_info->tx_offload_capa =
2857                 DEV_TX_OFFLOAD_VLAN_INSERT |
2858                 DEV_TX_OFFLOAD_QINQ_INSERT |
2859                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2860                 DEV_TX_OFFLOAD_UDP_CKSUM |
2861                 DEV_TX_OFFLOAD_TCP_CKSUM |
2862                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2863                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2864                 DEV_TX_OFFLOAD_TCP_TSO |
2865                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2866                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2867                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2868                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2869         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2870                                                 sizeof(uint32_t);
2871         dev_info->reta_size = pf->hash_lut_size;
2872         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2873
2874         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2875                 .rx_thresh = {
2876                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2877                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2878                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2879                 },
2880                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2881                 .rx_drop_en = 0,
2882         };
2883
2884         dev_info->default_txconf = (struct rte_eth_txconf) {
2885                 .tx_thresh = {
2886                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2887                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2888                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2889                 },
2890                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2891                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2892                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2893                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2894         };
2895
2896         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2897                 .nb_max = I40E_MAX_RING_DESC,
2898                 .nb_min = I40E_MIN_RING_DESC,
2899                 .nb_align = I40E_ALIGN_RING_DESC,
2900         };
2901
2902         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2903                 .nb_max = I40E_MAX_RING_DESC,
2904                 .nb_min = I40E_MIN_RING_DESC,
2905                 .nb_align = I40E_ALIGN_RING_DESC,
2906                 .nb_seg_max = I40E_TX_MAX_SEG,
2907                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2908         };
2909
2910         if (pf->flags & I40E_FLAG_VMDQ) {
2911                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2912                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2913                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2914                                                 pf->max_nb_vmdq_vsi;
2915                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2916                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2917                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2918         }
2919
2920         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2921                 /* For XL710 */
2922                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2923         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2924                 /* For XXV710 */
2925                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2926         else
2927                 /* For X710 */
2928                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2929 }
2930
2931 static int
2932 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2933 {
2934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935         struct i40e_vsi *vsi = pf->main_vsi;
2936         PMD_INIT_FUNC_TRACE();
2937
2938         if (on)
2939                 return i40e_vsi_add_vlan(vsi, vlan_id);
2940         else
2941                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2942 }
2943
2944 static int
2945 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2946                    enum rte_vlan_type vlan_type,
2947                    uint16_t tpid)
2948 {
2949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950         uint64_t reg_r = 0, reg_w = 0;
2951         uint16_t reg_id = 0;
2952         int ret = 0;
2953         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2954
2955         switch (vlan_type) {
2956         case ETH_VLAN_TYPE_OUTER:
2957                 if (qinq)
2958                         reg_id = 2;
2959                 else
2960                         reg_id = 3;
2961                 break;
2962         case ETH_VLAN_TYPE_INNER:
2963                 if (qinq)
2964                         reg_id = 3;
2965                 else {
2966                         ret = -EINVAL;
2967                         PMD_DRV_LOG(ERR,
2968                                 "Unsupported vlan type in single vlan.");
2969                         return ret;
2970                 }
2971                 break;
2972         default:
2973                 ret = -EINVAL;
2974                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2975                 return ret;
2976         }
2977         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2978                                           &reg_r, NULL);
2979         if (ret != I40E_SUCCESS) {
2980                 PMD_DRV_LOG(ERR,
2981                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2982                            reg_id);
2983                 ret = -EIO;
2984                 return ret;
2985         }
2986         PMD_DRV_LOG(DEBUG,
2987                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2988                 reg_id, reg_r);
2989
2990         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2991         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2992         if (reg_r == reg_w) {
2993                 ret = 0;
2994                 PMD_DRV_LOG(DEBUG, "No need to write");
2995                 return ret;
2996         }
2997
2998         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2999                                            reg_w, NULL);
3000         if (ret != I40E_SUCCESS) {
3001                 ret = -EIO;
3002                 PMD_DRV_LOG(ERR,
3003                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3004                         reg_id);
3005                 return ret;
3006         }
3007         PMD_DRV_LOG(DEBUG,
3008                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3009                 reg_w, reg_id);
3010
3011         return ret;
3012 }
3013
3014 static void
3015 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3016 {
3017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3018         struct i40e_vsi *vsi = pf->main_vsi;
3019
3020         if (mask & ETH_VLAN_FILTER_MASK) {
3021                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3022                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3023                 else
3024                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3025         }
3026
3027         if (mask & ETH_VLAN_STRIP_MASK) {
3028                 /* Enable or disable VLAN stripping */
3029                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3030                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3031                 else
3032                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3033         }
3034
3035         if (mask & ETH_VLAN_EXTEND_MASK) {
3036                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3037                         i40e_vsi_config_double_vlan(vsi, TRUE);
3038                         /* Set global registers with default ether type value */
3039                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3040                                            ETHER_TYPE_VLAN);
3041                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3042                                            ETHER_TYPE_VLAN);
3043                 }
3044                 else
3045                         i40e_vsi_config_double_vlan(vsi, FALSE);
3046         }
3047 }
3048
3049 static void
3050 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3051                           __rte_unused uint16_t queue,
3052                           __rte_unused int on)
3053 {
3054         PMD_INIT_FUNC_TRACE();
3055 }
3056
3057 static int
3058 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3059 {
3060         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3061         struct i40e_vsi *vsi = pf->main_vsi;
3062         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3063         struct i40e_vsi_vlan_pvid_info info;
3064
3065         memset(&info, 0, sizeof(info));
3066         info.on = on;
3067         if (info.on)
3068                 info.config.pvid = pvid;
3069         else {
3070                 info.config.reject.tagged =
3071                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3072                 info.config.reject.untagged =
3073                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3074         }
3075
3076         return i40e_vsi_vlan_pvid_set(vsi, &info);
3077 }
3078
3079 static int
3080 i40e_dev_led_on(struct rte_eth_dev *dev)
3081 {
3082         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083         uint32_t mode = i40e_led_get(hw);
3084
3085         if (mode == 0)
3086                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3087
3088         return 0;
3089 }
3090
3091 static int
3092 i40e_dev_led_off(struct rte_eth_dev *dev)
3093 {
3094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095         uint32_t mode = i40e_led_get(hw);
3096
3097         if (mode != 0)
3098                 i40e_led_set(hw, 0, false);
3099
3100         return 0;
3101 }
3102
3103 static int
3104 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3105 {
3106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3108
3109         fc_conf->pause_time = pf->fc_conf.pause_time;
3110         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3111         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3112
3113          /* Return current mode according to actual setting*/
3114         switch (hw->fc.current_mode) {
3115         case I40E_FC_FULL:
3116                 fc_conf->mode = RTE_FC_FULL;
3117                 break;
3118         case I40E_FC_TX_PAUSE:
3119                 fc_conf->mode = RTE_FC_TX_PAUSE;
3120                 break;
3121         case I40E_FC_RX_PAUSE:
3122                 fc_conf->mode = RTE_FC_RX_PAUSE;
3123                 break;
3124         case I40E_FC_NONE:
3125         default:
3126                 fc_conf->mode = RTE_FC_NONE;
3127         };
3128
3129         return 0;
3130 }
3131
3132 static int
3133 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3134 {
3135         uint32_t mflcn_reg, fctrl_reg, reg;
3136         uint32_t max_high_water;
3137         uint8_t i, aq_failure;
3138         int err;
3139         struct i40e_hw *hw;
3140         struct i40e_pf *pf;
3141         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3142                 [RTE_FC_NONE] = I40E_FC_NONE,
3143                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3144                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3145                 [RTE_FC_FULL] = I40E_FC_FULL
3146         };
3147
3148         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3149
3150         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3151         if ((fc_conf->high_water > max_high_water) ||
3152                         (fc_conf->high_water < fc_conf->low_water)) {
3153                 PMD_INIT_LOG(ERR,
3154                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3155                         max_high_water);
3156                 return -EINVAL;
3157         }
3158
3159         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3162
3163         pf->fc_conf.pause_time = fc_conf->pause_time;
3164         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3165         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3166
3167         PMD_INIT_FUNC_TRACE();
3168
3169         /* All the link flow control related enable/disable register
3170          * configuration is handle by the F/W
3171          */
3172         err = i40e_set_fc(hw, &aq_failure, true);
3173         if (err < 0)
3174                 return -ENOSYS;
3175
3176         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3177                 /* Configure flow control refresh threshold,
3178                  * the value for stat_tx_pause_refresh_timer[8]
3179                  * is used for global pause operation.
3180                  */
3181
3182                 I40E_WRITE_REG(hw,
3183                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3184                                pf->fc_conf.pause_time);
3185
3186                 /* configure the timer value included in transmitted pause
3187                  * frame,
3188                  * the value for stat_tx_pause_quanta[8] is used for global
3189                  * pause operation
3190                  */
3191                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3192                                pf->fc_conf.pause_time);
3193
3194                 fctrl_reg = I40E_READ_REG(hw,
3195                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3196
3197                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3198                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3199                 else
3200                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3201
3202                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3203                                fctrl_reg);
3204         } else {
3205                 /* Configure pause time (2 TCs per register) */
3206                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3207                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3208                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3209
3210                 /* Configure flow control refresh threshold value */
3211                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3212                                pf->fc_conf.pause_time / 2);
3213
3214                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3215
3216                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3217                  *depending on configuration
3218                  */
3219                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3220                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3221                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3222                 } else {
3223                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3224                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3225                 }
3226
3227                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3228         }
3229
3230         /* config the water marker both based on the packets and bytes */
3231         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3232                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3233                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3234         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3235                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3236                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3237         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3238                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3239                        << I40E_KILOSHIFT);
3240         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3241                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3242                        << I40E_KILOSHIFT);
3243
3244         I40E_WRITE_FLUSH(hw);
3245
3246         return 0;
3247 }
3248
3249 static int
3250 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3251                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3252 {
3253         PMD_INIT_FUNC_TRACE();
3254
3255         return -ENOSYS;
3256 }
3257
3258 /* Add a MAC address, and update filters */
3259 static void
3260 i40e_macaddr_add(struct rte_eth_dev *dev,
3261                  struct ether_addr *mac_addr,
3262                  __rte_unused uint32_t index,
3263                  uint32_t pool)
3264 {
3265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3266         struct i40e_mac_filter_info mac_filter;
3267         struct i40e_vsi *vsi;
3268         int ret;
3269
3270         /* If VMDQ not enabled or configured, return */
3271         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3272                           !pf->nb_cfg_vmdq_vsi)) {
3273                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3274                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3275                         pool);
3276                 return;
3277         }
3278
3279         if (pool > pf->nb_cfg_vmdq_vsi) {
3280                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3281                                 pool, pf->nb_cfg_vmdq_vsi);
3282                 return;
3283         }
3284
3285         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3286         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3287                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3288         else
3289                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3290
3291         if (pool == 0)
3292                 vsi = pf->main_vsi;
3293         else
3294                 vsi = pf->vmdq[pool - 1].vsi;
3295
3296         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3297         if (ret != I40E_SUCCESS) {
3298                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3299                 return;
3300         }
3301 }
3302
3303 /* Remove a MAC address, and update filters */
3304 static void
3305 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3306 {
3307         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308         struct i40e_vsi *vsi;
3309         struct rte_eth_dev_data *data = dev->data;
3310         struct ether_addr *macaddr;
3311         int ret;
3312         uint32_t i;
3313         uint64_t pool_sel;
3314
3315         macaddr = &(data->mac_addrs[index]);
3316
3317         pool_sel = dev->data->mac_pool_sel[index];
3318
3319         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3320                 if (pool_sel & (1ULL << i)) {
3321                         if (i == 0)
3322                                 vsi = pf->main_vsi;
3323                         else {
3324                                 /* No VMDQ pool enabled or configured */
3325                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3326                                         (i > pf->nb_cfg_vmdq_vsi)) {
3327                                         PMD_DRV_LOG(ERR,
3328                                                 "No VMDQ pool enabled/configured");
3329                                         return;
3330                                 }
3331                                 vsi = pf->vmdq[i - 1].vsi;
3332                         }
3333                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3334
3335                         if (ret) {
3336                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3337                                 return;
3338                         }
3339                 }
3340         }
3341 }
3342
3343 /* Set perfect match or hash match of MAC and VLAN for a VF */
3344 static int
3345 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3346                  struct rte_eth_mac_filter *filter,
3347                  bool add)
3348 {
3349         struct i40e_hw *hw;
3350         struct i40e_mac_filter_info mac_filter;
3351         struct ether_addr old_mac;
3352         struct ether_addr *new_mac;
3353         struct i40e_pf_vf *vf = NULL;
3354         uint16_t vf_id;
3355         int ret;
3356
3357         if (pf == NULL) {
3358                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3359                 return -EINVAL;
3360         }
3361         hw = I40E_PF_TO_HW(pf);
3362
3363         if (filter == NULL) {
3364                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3365                 return -EINVAL;
3366         }
3367
3368         new_mac = &filter->mac_addr;
3369
3370         if (is_zero_ether_addr(new_mac)) {
3371                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3372                 return -EINVAL;
3373         }
3374
3375         vf_id = filter->dst_id;
3376
3377         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3378                 PMD_DRV_LOG(ERR, "Invalid argument.");
3379                 return -EINVAL;
3380         }
3381         vf = &pf->vfs[vf_id];
3382
3383         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3384                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3385                 return -EINVAL;
3386         }
3387
3388         if (add) {
3389                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3390                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3391                                 ETHER_ADDR_LEN);
3392                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3393                                  ETHER_ADDR_LEN);
3394
3395                 mac_filter.filter_type = filter->filter_type;
3396                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3397                 if (ret != I40E_SUCCESS) {
3398                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3399                         return -1;
3400                 }
3401                 ether_addr_copy(new_mac, &pf->dev_addr);
3402         } else {
3403                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3404                                 ETHER_ADDR_LEN);
3405                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3406                 if (ret != I40E_SUCCESS) {
3407                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3408                         return -1;
3409                 }
3410
3411                 /* Clear device address as it has been removed */
3412                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3413                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3414         }
3415
3416         return 0;
3417 }
3418
3419 /* MAC filter handle */
3420 static int
3421 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3422                 void *arg)
3423 {
3424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3425         struct rte_eth_mac_filter *filter;
3426         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3427         int ret = I40E_NOT_SUPPORTED;
3428
3429         filter = (struct rte_eth_mac_filter *)(arg);
3430
3431         switch (filter_op) {
3432         case RTE_ETH_FILTER_NOP:
3433                 ret = I40E_SUCCESS;
3434                 break;
3435         case RTE_ETH_FILTER_ADD:
3436                 i40e_pf_disable_irq0(hw);
3437                 if (filter->is_vf)
3438                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3439                 i40e_pf_enable_irq0(hw);
3440                 break;
3441         case RTE_ETH_FILTER_DELETE:
3442                 i40e_pf_disable_irq0(hw);
3443                 if (filter->is_vf)
3444                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3445                 i40e_pf_enable_irq0(hw);
3446                 break;
3447         default:
3448                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3449                 ret = I40E_ERR_PARAM;
3450                 break;
3451         }
3452
3453         return ret;
3454 }
3455
3456 static int
3457 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3458 {
3459         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3460         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3461         int ret;
3462
3463         if (!lut)
3464                 return -EINVAL;
3465
3466         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3467                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3468                                           lut, lut_size);
3469                 if (ret) {
3470                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3471                         return ret;
3472                 }
3473         } else {
3474                 uint32_t *lut_dw = (uint32_t *)lut;
3475                 uint16_t i, lut_size_dw = lut_size / 4;
3476
3477                 for (i = 0; i < lut_size_dw; i++)
3478                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3479         }
3480
3481         return 0;
3482 }
3483
3484 static int
3485 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3486 {
3487         struct i40e_pf *pf;
3488         struct i40e_hw *hw;
3489         int ret;
3490
3491         if (!vsi || !lut)
3492                 return -EINVAL;
3493
3494         pf = I40E_VSI_TO_PF(vsi);
3495         hw = I40E_VSI_TO_HW(vsi);
3496
3497         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3498                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3499                                           lut, lut_size);
3500                 if (ret) {
3501                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3502                         return ret;
3503                 }
3504         } else {
3505                 uint32_t *lut_dw = (uint32_t *)lut;
3506                 uint16_t i, lut_size_dw = lut_size / 4;
3507
3508                 for (i = 0; i < lut_size_dw; i++)
3509                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3510                 I40E_WRITE_FLUSH(hw);
3511         }
3512
3513         return 0;
3514 }
3515
3516 static int
3517 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3518                          struct rte_eth_rss_reta_entry64 *reta_conf,
3519                          uint16_t reta_size)
3520 {
3521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3522         uint16_t i, lut_size = pf->hash_lut_size;
3523         uint16_t idx, shift;
3524         uint8_t *lut;
3525         int ret;
3526
3527         if (reta_size != lut_size ||
3528                 reta_size > ETH_RSS_RETA_SIZE_512) {
3529                 PMD_DRV_LOG(ERR,
3530                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3531                         reta_size, lut_size);
3532                 return -EINVAL;
3533         }
3534
3535         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3536         if (!lut) {
3537                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3538                 return -ENOMEM;
3539         }
3540         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3541         if (ret)
3542                 goto out;
3543         for (i = 0; i < reta_size; i++) {
3544                 idx = i / RTE_RETA_GROUP_SIZE;
3545                 shift = i % RTE_RETA_GROUP_SIZE;
3546                 if (reta_conf[idx].mask & (1ULL << shift))
3547                         lut[i] = reta_conf[idx].reta[shift];
3548         }
3549         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3550
3551 out:
3552         rte_free(lut);
3553
3554         return ret;
3555 }
3556
3557 static int
3558 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3559                         struct rte_eth_rss_reta_entry64 *reta_conf,
3560                         uint16_t reta_size)
3561 {
3562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3563         uint16_t i, lut_size = pf->hash_lut_size;
3564         uint16_t idx, shift;
3565         uint8_t *lut;
3566         int ret;
3567
3568         if (reta_size != lut_size ||
3569                 reta_size > ETH_RSS_RETA_SIZE_512) {
3570                 PMD_DRV_LOG(ERR,
3571                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3572                         reta_size, lut_size);
3573                 return -EINVAL;
3574         }
3575
3576         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3577         if (!lut) {
3578                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3579                 return -ENOMEM;
3580         }
3581
3582         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3583         if (ret)
3584                 goto out;
3585         for (i = 0; i < reta_size; i++) {
3586                 idx = i / RTE_RETA_GROUP_SIZE;
3587                 shift = i % RTE_RETA_GROUP_SIZE;
3588                 if (reta_conf[idx].mask & (1ULL << shift))
3589                         reta_conf[idx].reta[shift] = lut[i];
3590         }
3591
3592 out:
3593         rte_free(lut);
3594
3595         return ret;
3596 }
3597
3598 /**
3599  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3600  * @hw:   pointer to the HW structure
3601  * @mem:  pointer to mem struct to fill out
3602  * @size: size of memory requested
3603  * @alignment: what to align the allocation to
3604  **/
3605 enum i40e_status_code
3606 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3607                         struct i40e_dma_mem *mem,
3608                         u64 size,
3609                         u32 alignment)
3610 {
3611         const struct rte_memzone *mz = NULL;
3612         char z_name[RTE_MEMZONE_NAMESIZE];
3613
3614         if (!mem)
3615                 return I40E_ERR_PARAM;
3616
3617         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3618         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3619                                          alignment, RTE_PGSIZE_2M);
3620         if (!mz)
3621                 return I40E_ERR_NO_MEMORY;
3622
3623         mem->size = size;
3624         mem->va = mz->addr;
3625         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3626         mem->zone = (const void *)mz;
3627         PMD_DRV_LOG(DEBUG,
3628                 "memzone %s allocated with physical address: %"PRIu64,
3629                 mz->name, mem->pa);
3630
3631         return I40E_SUCCESS;
3632 }
3633
3634 /**
3635  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3636  * @hw:   pointer to the HW structure
3637  * @mem:  ptr to mem struct to free
3638  **/
3639 enum i40e_status_code
3640 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3641                     struct i40e_dma_mem *mem)
3642 {
3643         if (!mem)
3644                 return I40E_ERR_PARAM;
3645
3646         PMD_DRV_LOG(DEBUG,
3647                 "memzone %s to be freed with physical address: %"PRIu64,
3648                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3649         rte_memzone_free((const struct rte_memzone *)mem->zone);
3650         mem->zone = NULL;
3651         mem->va = NULL;
3652         mem->pa = (u64)0;
3653
3654         return I40E_SUCCESS;
3655 }
3656
3657 /**
3658  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3659  * @hw:   pointer to the HW structure
3660  * @mem:  pointer to mem struct to fill out
3661  * @size: size of memory requested
3662  **/
3663 enum i40e_status_code
3664 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3665                          struct i40e_virt_mem *mem,
3666                          u32 size)
3667 {
3668         if (!mem)
3669                 return I40E_ERR_PARAM;
3670
3671         mem->size = size;
3672         mem->va = rte_zmalloc("i40e", size, 0);
3673
3674         if (mem->va)
3675                 return I40E_SUCCESS;
3676         else
3677                 return I40E_ERR_NO_MEMORY;
3678 }
3679
3680 /**
3681  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3682  * @hw:   pointer to the HW structure
3683  * @mem:  pointer to mem struct to free
3684  **/
3685 enum i40e_status_code
3686 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3687                      struct i40e_virt_mem *mem)
3688 {
3689         if (!mem)
3690                 return I40E_ERR_PARAM;
3691
3692         rte_free(mem->va);
3693         mem->va = NULL;
3694
3695         return I40E_SUCCESS;
3696 }
3697
3698 void
3699 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3700 {
3701         rte_spinlock_init(&sp->spinlock);
3702 }
3703
3704 void
3705 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3706 {
3707         rte_spinlock_lock(&sp->spinlock);
3708 }
3709
3710 void
3711 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3712 {
3713         rte_spinlock_unlock(&sp->spinlock);
3714 }
3715
3716 void
3717 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3718 {
3719         return;
3720 }
3721
3722 /**
3723  * Get the hardware capabilities, which will be parsed
3724  * and saved into struct i40e_hw.
3725  */
3726 static int
3727 i40e_get_cap(struct i40e_hw *hw)
3728 {
3729         struct i40e_aqc_list_capabilities_element_resp *buf;
3730         uint16_t len, size = 0;
3731         int ret;
3732
3733         /* Calculate a huge enough buff for saving response data temporarily */
3734         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3735                                                 I40E_MAX_CAP_ELE_NUM;
3736         buf = rte_zmalloc("i40e", len, 0);
3737         if (!buf) {
3738                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3739                 return I40E_ERR_NO_MEMORY;
3740         }
3741
3742         /* Get, parse the capabilities and save it to hw */
3743         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3744                         i40e_aqc_opc_list_func_capabilities, NULL);
3745         if (ret != I40E_SUCCESS)
3746                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3747
3748         /* Free the temporary buffer after being used */
3749         rte_free(buf);
3750
3751         return ret;
3752 }
3753
3754 static int
3755 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3756 {
3757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3758         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3759         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3760         uint16_t qp_count = 0, vsi_count = 0;
3761
3762         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3763                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3764                 return -EINVAL;
3765         }
3766         /* Add the parameter init for LFC */
3767         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3768         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3769         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3770
3771         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3772         pf->max_num_vsi = hw->func_caps.num_vsis;
3773         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3774         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3775         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3776
3777         /* FDir queue/VSI allocation */
3778         pf->fdir_qp_offset = 0;
3779         if (hw->func_caps.fd) {
3780                 pf->flags |= I40E_FLAG_FDIR;
3781                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3782         } else {
3783                 pf->fdir_nb_qps = 0;
3784         }
3785         qp_count += pf->fdir_nb_qps;
3786         vsi_count += 1;
3787
3788         /* LAN queue/VSI allocation */
3789         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3790         if (!hw->func_caps.rss) {
3791                 pf->lan_nb_qps = 1;
3792         } else {
3793                 pf->flags |= I40E_FLAG_RSS;
3794                 if (hw->mac.type == I40E_MAC_X722)
3795                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3796                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3797         }
3798         qp_count += pf->lan_nb_qps;
3799         vsi_count += 1;
3800
3801         /* VF queue/VSI allocation */
3802         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3803         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3804                 pf->flags |= I40E_FLAG_SRIOV;
3805                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3806                 pf->vf_num = pci_dev->max_vfs;
3807                 PMD_DRV_LOG(DEBUG,
3808                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3809                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3810         } else {
3811                 pf->vf_nb_qps = 0;
3812                 pf->vf_num = 0;
3813         }
3814         qp_count += pf->vf_nb_qps * pf->vf_num;
3815         vsi_count += pf->vf_num;
3816
3817         /* VMDq queue/VSI allocation */
3818         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3819         pf->vmdq_nb_qps = 0;
3820         pf->max_nb_vmdq_vsi = 0;
3821         if (hw->func_caps.vmdq) {
3822                 if (qp_count < hw->func_caps.num_tx_qp &&
3823                         vsi_count < hw->func_caps.num_vsis) {
3824                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3825                                 qp_count) / pf->vmdq_nb_qp_max;
3826
3827                         /* Limit the maximum number of VMDq vsi to the maximum
3828                          * ethdev can support
3829                          */
3830                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3831                                 hw->func_caps.num_vsis - vsi_count);
3832                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3833                                 ETH_64_POOLS);
3834                         if (pf->max_nb_vmdq_vsi) {
3835                                 pf->flags |= I40E_FLAG_VMDQ;
3836                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3837                                 PMD_DRV_LOG(DEBUG,
3838                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3839                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3840                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3841                         } else {
3842                                 PMD_DRV_LOG(INFO,
3843                                         "No enough queues left for VMDq");
3844                         }
3845                 } else {
3846                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3847                 }
3848         }
3849         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3850         vsi_count += pf->max_nb_vmdq_vsi;
3851
3852         if (hw->func_caps.dcb)
3853                 pf->flags |= I40E_FLAG_DCB;
3854
3855         if (qp_count > hw->func_caps.num_tx_qp) {
3856                 PMD_DRV_LOG(ERR,
3857                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3858                         qp_count, hw->func_caps.num_tx_qp);
3859                 return -EINVAL;
3860         }
3861         if (vsi_count > hw->func_caps.num_vsis) {
3862                 PMD_DRV_LOG(ERR,
3863                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3864                         vsi_count, hw->func_caps.num_vsis);
3865                 return -EINVAL;
3866         }
3867
3868         return 0;
3869 }
3870
3871 static int
3872 i40e_pf_get_switch_config(struct i40e_pf *pf)
3873 {
3874         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3875         struct i40e_aqc_get_switch_config_resp *switch_config;
3876         struct i40e_aqc_switch_config_element_resp *element;
3877         uint16_t start_seid = 0, num_reported;
3878         int ret;
3879
3880         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3881                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3882         if (!switch_config) {
3883                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3884                 return -ENOMEM;
3885         }
3886
3887         /* Get the switch configurations */
3888         ret = i40e_aq_get_switch_config(hw, switch_config,
3889                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3890         if (ret != I40E_SUCCESS) {
3891                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3892                 goto fail;
3893         }
3894         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3895         if (num_reported != 1) { /* The number should be 1 */
3896                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3897                 goto fail;
3898         }
3899
3900         /* Parse the switch configuration elements */
3901         element = &(switch_config->element[0]);
3902         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3903                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3904                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3905         } else
3906                 PMD_DRV_LOG(INFO, "Unknown element type");
3907
3908 fail:
3909         rte_free(switch_config);
3910
3911         return ret;
3912 }
3913
3914 static int
3915 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3916                         uint32_t num)
3917 {
3918         struct pool_entry *entry;
3919
3920         if (pool == NULL || num == 0)
3921                 return -EINVAL;
3922
3923         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3924         if (entry == NULL) {
3925                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3926                 return -ENOMEM;
3927         }
3928
3929         /* queue heap initialize */
3930         pool->num_free = num;
3931         pool->num_alloc = 0;
3932         pool->base = base;
3933         LIST_INIT(&pool->alloc_list);
3934         LIST_INIT(&pool->free_list);
3935
3936         /* Initialize element  */
3937         entry->base = 0;
3938         entry->len = num;
3939
3940         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3941         return 0;
3942 }
3943
3944 static void
3945 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3946 {
3947         struct pool_entry *entry, *next_entry;
3948
3949         if (pool == NULL)
3950                 return;
3951
3952         for (entry = LIST_FIRST(&pool->alloc_list);
3953                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3954                         entry = next_entry) {
3955                 LIST_REMOVE(entry, next);
3956                 rte_free(entry);
3957         }
3958
3959         for (entry = LIST_FIRST(&pool->free_list);
3960                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3961                         entry = next_entry) {
3962                 LIST_REMOVE(entry, next);
3963                 rte_free(entry);
3964         }
3965
3966         pool->num_free = 0;
3967         pool->num_alloc = 0;
3968         pool->base = 0;
3969         LIST_INIT(&pool->alloc_list);
3970         LIST_INIT(&pool->free_list);
3971 }
3972
3973 static int
3974 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3975                        uint32_t base)
3976 {
3977         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3978         uint32_t pool_offset;
3979         int insert;
3980
3981         if (pool == NULL) {
3982                 PMD_DRV_LOG(ERR, "Invalid parameter");
3983                 return -EINVAL;
3984         }
3985
3986         pool_offset = base - pool->base;
3987         /* Lookup in alloc list */
3988         LIST_FOREACH(entry, &pool->alloc_list, next) {
3989                 if (entry->base == pool_offset) {
3990                         valid_entry = entry;
3991                         LIST_REMOVE(entry, next);
3992                         break;
3993                 }
3994         }
3995
3996         /* Not find, return */
3997         if (valid_entry == NULL) {
3998                 PMD_DRV_LOG(ERR, "Failed to find entry");
3999                 return -EINVAL;
4000         }
4001
4002         /**
4003          * Found it, move it to free list  and try to merge.
4004          * In order to make merge easier, always sort it by qbase.
4005          * Find adjacent prev and last entries.
4006          */
4007         prev = next = NULL;
4008         LIST_FOREACH(entry, &pool->free_list, next) {
4009                 if (entry->base > valid_entry->base) {
4010                         next = entry;
4011                         break;
4012                 }
4013                 prev = entry;
4014         }
4015
4016         insert = 0;
4017         /* Try to merge with next one*/
4018         if (next != NULL) {
4019                 /* Merge with next one */
4020                 if (valid_entry->base + valid_entry->len == next->base) {
4021                         next->base = valid_entry->base;
4022                         next->len += valid_entry->len;
4023                         rte_free(valid_entry);
4024                         valid_entry = next;
4025                         insert = 1;
4026                 }
4027         }
4028
4029         if (prev != NULL) {
4030                 /* Merge with previous one */
4031                 if (prev->base + prev->len == valid_entry->base) {
4032                         prev->len += valid_entry->len;
4033                         /* If it merge with next one, remove next node */
4034                         if (insert == 1) {
4035                                 LIST_REMOVE(valid_entry, next);
4036                                 rte_free(valid_entry);
4037                         } else {
4038                                 rte_free(valid_entry);
4039                                 insert = 1;
4040                         }
4041                 }
4042         }
4043
4044         /* Not find any entry to merge, insert */
4045         if (insert == 0) {
4046                 if (prev != NULL)
4047                         LIST_INSERT_AFTER(prev, valid_entry, next);
4048                 else if (next != NULL)
4049                         LIST_INSERT_BEFORE(next, valid_entry, next);
4050                 else /* It's empty list, insert to head */
4051                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4052         }
4053
4054         pool->num_free += valid_entry->len;
4055         pool->num_alloc -= valid_entry->len;
4056
4057         return 0;
4058 }
4059
4060 static int
4061 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4062                        uint16_t num)
4063 {
4064         struct pool_entry *entry, *valid_entry;
4065
4066         if (pool == NULL || num == 0) {
4067                 PMD_DRV_LOG(ERR, "Invalid parameter");
4068                 return -EINVAL;
4069         }
4070
4071         if (pool->num_free < num) {
4072                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4073                             num, pool->num_free);
4074                 return -ENOMEM;
4075         }
4076
4077         valid_entry = NULL;
4078         /* Lookup  in free list and find most fit one */
4079         LIST_FOREACH(entry, &pool->free_list, next) {
4080                 if (entry->len >= num) {
4081                         /* Find best one */
4082                         if (entry->len == num) {
4083                                 valid_entry = entry;
4084                                 break;
4085                         }
4086                         if (valid_entry == NULL || valid_entry->len > entry->len)
4087                                 valid_entry = entry;
4088                 }
4089         }
4090
4091         /* Not find one to satisfy the request, return */
4092         if (valid_entry == NULL) {
4093                 PMD_DRV_LOG(ERR, "No valid entry found");
4094                 return -ENOMEM;
4095         }
4096         /**
4097          * The entry have equal queue number as requested,
4098          * remove it from alloc_list.
4099          */
4100         if (valid_entry->len == num) {
4101                 LIST_REMOVE(valid_entry, next);
4102         } else {
4103                 /**
4104                  * The entry have more numbers than requested,
4105                  * create a new entry for alloc_list and minus its
4106                  * queue base and number in free_list.
4107                  */
4108                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4109                 if (entry == NULL) {
4110                         PMD_DRV_LOG(ERR,
4111                                 "Failed to allocate memory for resource pool");
4112                         return -ENOMEM;
4113                 }
4114                 entry->base = valid_entry->base;
4115                 entry->len = num;
4116                 valid_entry->base += num;
4117                 valid_entry->len -= num;
4118                 valid_entry = entry;
4119         }
4120
4121         /* Insert it into alloc list, not sorted */
4122         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4123
4124         pool->num_free -= valid_entry->len;
4125         pool->num_alloc += valid_entry->len;
4126
4127         return valid_entry->base + pool->base;
4128 }
4129
4130 /**
4131  * bitmap_is_subset - Check whether src2 is subset of src1
4132  **/
4133 static inline int
4134 bitmap_is_subset(uint8_t src1, uint8_t src2)
4135 {
4136         return !((src1 ^ src2) & src2);
4137 }
4138
4139 static enum i40e_status_code
4140 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4141 {
4142         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4143
4144         /* If DCB is not supported, only default TC is supported */
4145         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4146                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4147                 return I40E_NOT_SUPPORTED;
4148         }
4149
4150         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4151                 PMD_DRV_LOG(ERR,
4152                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4153                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4154                 return I40E_NOT_SUPPORTED;
4155         }
4156         return I40E_SUCCESS;
4157 }
4158
4159 int
4160 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4161                                 struct i40e_vsi_vlan_pvid_info *info)
4162 {
4163         struct i40e_hw *hw;
4164         struct i40e_vsi_context ctxt;
4165         uint8_t vlan_flags = 0;
4166         int ret;
4167
4168         if (vsi == NULL || info == NULL) {
4169                 PMD_DRV_LOG(ERR, "invalid parameters");
4170                 return I40E_ERR_PARAM;
4171         }
4172
4173         if (info->on) {
4174                 vsi->info.pvid = info->config.pvid;
4175                 /**
4176                  * If insert pvid is enabled, only tagged pkts are
4177                  * allowed to be sent out.
4178                  */
4179                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4180                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4181         } else {
4182                 vsi->info.pvid = 0;
4183                 if (info->config.reject.tagged == 0)
4184                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4185
4186                 if (info->config.reject.untagged == 0)
4187                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4188         }
4189         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4190                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4191         vsi->info.port_vlan_flags |= vlan_flags;
4192         vsi->info.valid_sections =
4193                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4194         memset(&ctxt, 0, sizeof(ctxt));
4195         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4196         ctxt.seid = vsi->seid;
4197
4198         hw = I40E_VSI_TO_HW(vsi);
4199         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4200         if (ret != I40E_SUCCESS)
4201                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4202
4203         return ret;
4204 }
4205
4206 static int
4207 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4208 {
4209         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4210         int i, ret;
4211         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4212
4213         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4214         if (ret != I40E_SUCCESS)
4215                 return ret;
4216
4217         if (!vsi->seid) {
4218                 PMD_DRV_LOG(ERR, "seid not valid");
4219                 return -EINVAL;
4220         }
4221
4222         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4223         tc_bw_data.tc_valid_bits = enabled_tcmap;
4224         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4225                 tc_bw_data.tc_bw_credits[i] =
4226                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4227
4228         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4229         if (ret != I40E_SUCCESS) {
4230                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4231                 return ret;
4232         }
4233
4234         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4235                                         sizeof(vsi->info.qs_handle));
4236         return I40E_SUCCESS;
4237 }
4238
4239 static enum i40e_status_code
4240 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4241                                  struct i40e_aqc_vsi_properties_data *info,
4242                                  uint8_t enabled_tcmap)
4243 {
4244         enum i40e_status_code ret;
4245         int i, total_tc = 0;
4246         uint16_t qpnum_per_tc, bsf, qp_idx;
4247
4248         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4249         if (ret != I40E_SUCCESS)
4250                 return ret;
4251
4252         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4253                 if (enabled_tcmap & (1 << i))
4254                         total_tc++;
4255         vsi->enabled_tc = enabled_tcmap;
4256
4257         /* Number of queues per enabled TC */
4258         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4259         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4260         bsf = rte_bsf32(qpnum_per_tc);
4261
4262         /* Adjust the queue number to actual queues that can be applied */
4263         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4264                 vsi->nb_qps = qpnum_per_tc * total_tc;
4265
4266         /**
4267          * Configure TC and queue mapping parameters, for enabled TC,
4268          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4269          * default queue will serve it.
4270          */
4271         qp_idx = 0;
4272         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4273                 if (vsi->enabled_tc & (1 << i)) {
4274                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4275                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4276                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4277                         qp_idx += qpnum_per_tc;
4278                 } else
4279                         info->tc_mapping[i] = 0;
4280         }
4281
4282         /* Associate queue number with VSI */
4283         if (vsi->type == I40E_VSI_SRIOV) {
4284                 info->mapping_flags |=
4285                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4286                 for (i = 0; i < vsi->nb_qps; i++)
4287                         info->queue_mapping[i] =
4288                                 rte_cpu_to_le_16(vsi->base_queue + i);
4289         } else {
4290                 info->mapping_flags |=
4291                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4292                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4293         }
4294         info->valid_sections |=
4295                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4296
4297         return I40E_SUCCESS;
4298 }
4299
4300 static int
4301 i40e_veb_release(struct i40e_veb *veb)
4302 {
4303         struct i40e_vsi *vsi;
4304         struct i40e_hw *hw;
4305
4306         if (veb == NULL)
4307                 return -EINVAL;
4308
4309         if (!TAILQ_EMPTY(&veb->head)) {
4310                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4311                 return -EACCES;
4312         }
4313         /* associate_vsi field is NULL for floating VEB */
4314         if (veb->associate_vsi != NULL) {
4315                 vsi = veb->associate_vsi;
4316                 hw = I40E_VSI_TO_HW(vsi);
4317
4318                 vsi->uplink_seid = veb->uplink_seid;
4319                 vsi->veb = NULL;
4320         } else {
4321                 veb->associate_pf->main_vsi->floating_veb = NULL;
4322                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4323         }
4324
4325         i40e_aq_delete_element(hw, veb->seid, NULL);
4326         rte_free(veb);
4327         return I40E_SUCCESS;
4328 }
4329
4330 /* Setup a veb */
4331 static struct i40e_veb *
4332 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4333 {
4334         struct i40e_veb *veb;
4335         int ret;
4336         struct i40e_hw *hw;
4337
4338         if (pf == NULL) {
4339                 PMD_DRV_LOG(ERR,
4340                             "veb setup failed, associated PF shouldn't null");
4341                 return NULL;
4342         }
4343         hw = I40E_PF_TO_HW(pf);
4344
4345         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4346         if (!veb) {
4347                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4348                 goto fail;
4349         }
4350
4351         veb->associate_vsi = vsi;
4352         veb->associate_pf = pf;
4353         TAILQ_INIT(&veb->head);
4354         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4355
4356         /* create floating veb if vsi is NULL */
4357         if (vsi != NULL) {
4358                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4359                                       I40E_DEFAULT_TCMAP, false,
4360                                       &veb->seid, false, NULL);
4361         } else {
4362                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4363                                       true, &veb->seid, false, NULL);
4364         }
4365
4366         if (ret != I40E_SUCCESS) {
4367                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4368                             hw->aq.asq_last_status);
4369                 goto fail;
4370         }
4371         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4372
4373         /* get statistics index */
4374         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4375                                 &veb->stats_idx, NULL, NULL, NULL);
4376         if (ret != I40E_SUCCESS) {
4377                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4378                             hw->aq.asq_last_status);
4379                 goto fail;
4380         }
4381         /* Get VEB bandwidth, to be implemented */
4382         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4383         if (vsi)
4384                 vsi->uplink_seid = veb->seid;
4385
4386         return veb;
4387 fail:
4388         rte_free(veb);
4389         return NULL;
4390 }
4391
4392 int
4393 i40e_vsi_release(struct i40e_vsi *vsi)
4394 {
4395         struct i40e_pf *pf;
4396         struct i40e_hw *hw;
4397         struct i40e_vsi_list *vsi_list;
4398         void *temp;
4399         int ret;
4400         struct i40e_mac_filter *f;
4401         uint16_t user_param;
4402
4403         if (!vsi)
4404                 return I40E_SUCCESS;
4405
4406         if (!vsi->adapter)
4407                 return -EFAULT;
4408
4409         user_param = vsi->user_param;
4410
4411         pf = I40E_VSI_TO_PF(vsi);
4412         hw = I40E_VSI_TO_HW(vsi);
4413
4414         /* VSI has child to attach, release child first */
4415         if (vsi->veb) {
4416                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4417                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4418                                 return -1;
4419                 }
4420                 i40e_veb_release(vsi->veb);
4421         }
4422
4423         if (vsi->floating_veb) {
4424                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4425                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4426                                 return -1;
4427                 }
4428         }
4429
4430         /* Remove all macvlan filters of the VSI */
4431         i40e_vsi_remove_all_macvlan_filter(vsi);
4432         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4433                 rte_free(f);
4434
4435         if (vsi->type != I40E_VSI_MAIN &&
4436             ((vsi->type != I40E_VSI_SRIOV) ||
4437             !pf->floating_veb_list[user_param])) {
4438                 /* Remove vsi from parent's sibling list */
4439                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4440                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4441                         return I40E_ERR_PARAM;
4442                 }
4443                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4444                                 &vsi->sib_vsi_list, list);
4445
4446                 /* Remove all switch element of the VSI */
4447                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4448                 if (ret != I40E_SUCCESS)
4449                         PMD_DRV_LOG(ERR, "Failed to delete element");
4450         }
4451
4452         if ((vsi->type == I40E_VSI_SRIOV) &&
4453             pf->floating_veb_list[user_param]) {
4454                 /* Remove vsi from parent's sibling list */
4455                 if (vsi->parent_vsi == NULL ||
4456                     vsi->parent_vsi->floating_veb == NULL) {
4457                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4458                         return I40E_ERR_PARAM;
4459                 }
4460                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4461                              &vsi->sib_vsi_list, list);
4462
4463                 /* Remove all switch element of the VSI */
4464                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4465                 if (ret != I40E_SUCCESS)
4466                         PMD_DRV_LOG(ERR, "Failed to delete element");
4467         }
4468
4469         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4470
4471         if (vsi->type != I40E_VSI_SRIOV)
4472                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4473         rte_free(vsi);
4474
4475         return I40E_SUCCESS;
4476 }
4477
4478 static int
4479 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4480 {
4481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4482         struct i40e_aqc_remove_macvlan_element_data def_filter;
4483         struct i40e_mac_filter_info filter;
4484         int ret;
4485
4486         if (vsi->type != I40E_VSI_MAIN)
4487                 return I40E_ERR_CONFIG;
4488         memset(&def_filter, 0, sizeof(def_filter));
4489         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4490                                         ETH_ADDR_LEN);
4491         def_filter.vlan_tag = 0;
4492         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4493                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4494         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4495         if (ret != I40E_SUCCESS) {
4496                 struct i40e_mac_filter *f;
4497                 struct ether_addr *mac;
4498
4499                 PMD_DRV_LOG(WARNING,
4500                         "Cannot remove the default macvlan filter");
4501                 /* It needs to add the permanent mac into mac list */
4502                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4503                 if (f == NULL) {
4504                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4505                         return I40E_ERR_NO_MEMORY;
4506                 }
4507                 mac = &f->mac_info.mac_addr;
4508                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4509                                 ETH_ADDR_LEN);
4510                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4511                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4512                 vsi->mac_num++;
4513
4514                 return ret;
4515         }
4516         (void)rte_memcpy(&filter.mac_addr,
4517                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4518         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4519         return i40e_vsi_add_mac(vsi, &filter);
4520 }
4521
4522 /*
4523  * i40e_vsi_get_bw_config - Query VSI BW Information
4524  * @vsi: the VSI to be queried
4525  *
4526  * Returns 0 on success, negative value on failure
4527  */
4528 static enum i40e_status_code
4529 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4530 {
4531         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4532         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4533         struct i40e_hw *hw = &vsi->adapter->hw;
4534         i40e_status ret;
4535         int i;
4536         uint32_t bw_max;
4537
4538         memset(&bw_config, 0, sizeof(bw_config));
4539         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4540         if (ret != I40E_SUCCESS) {
4541                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4542                             hw->aq.asq_last_status);
4543                 return ret;
4544         }
4545
4546         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4547         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4548                                         &ets_sla_config, NULL);
4549         if (ret != I40E_SUCCESS) {
4550                 PMD_DRV_LOG(ERR,
4551                         "VSI failed to get TC bandwdith configuration %u",
4552                         hw->aq.asq_last_status);
4553                 return ret;
4554         }
4555
4556         /* store and print out BW info */
4557         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4558         vsi->bw_info.bw_max = bw_config.max_bw;
4559         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4560         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4561         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4562                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4563                      I40E_16_BIT_WIDTH);
4564         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4565                 vsi->bw_info.bw_ets_share_credits[i] =
4566                                 ets_sla_config.share_credits[i];
4567                 vsi->bw_info.bw_ets_credits[i] =
4568                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4569                 /* 4 bits per TC, 4th bit is reserved */
4570                 vsi->bw_info.bw_ets_max[i] =
4571                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4572                                   RTE_LEN2MASK(3, uint8_t));
4573                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4574                             vsi->bw_info.bw_ets_share_credits[i]);
4575                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4576                             vsi->bw_info.bw_ets_credits[i]);
4577                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4578                             vsi->bw_info.bw_ets_max[i]);
4579         }
4580
4581         return I40E_SUCCESS;
4582 }
4583
4584 /* i40e_enable_pf_lb
4585  * @pf: pointer to the pf structure
4586  *
4587  * allow loopback on pf
4588  */
4589 static inline void
4590 i40e_enable_pf_lb(struct i40e_pf *pf)
4591 {
4592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4593         struct i40e_vsi_context ctxt;
4594         int ret;
4595
4596         /* Use the FW API if FW >= v5.0 */
4597         if (hw->aq.fw_maj_ver < 5) {
4598                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4599                 return;
4600         }
4601
4602         memset(&ctxt, 0, sizeof(ctxt));
4603         ctxt.seid = pf->main_vsi_seid;
4604         ctxt.pf_num = hw->pf_id;
4605         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4606         if (ret) {
4607                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4608                             ret, hw->aq.asq_last_status);
4609                 return;
4610         }
4611         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4612         ctxt.info.valid_sections =
4613                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4614         ctxt.info.switch_id |=
4615                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4616
4617         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4618         if (ret)
4619                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4620                             hw->aq.asq_last_status);
4621 }
4622
4623 /* Setup a VSI */
4624 struct i40e_vsi *
4625 i40e_vsi_setup(struct i40e_pf *pf,
4626                enum i40e_vsi_type type,
4627                struct i40e_vsi *uplink_vsi,
4628                uint16_t user_param)
4629 {
4630         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4631         struct i40e_vsi *vsi;
4632         struct i40e_mac_filter_info filter;
4633         int ret;
4634         struct i40e_vsi_context ctxt;
4635         struct ether_addr broadcast =
4636                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4637
4638         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4639             uplink_vsi == NULL) {
4640                 PMD_DRV_LOG(ERR,
4641                         "VSI setup failed, VSI link shouldn't be NULL");
4642                 return NULL;
4643         }
4644
4645         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4646                 PMD_DRV_LOG(ERR,
4647                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4648                 return NULL;
4649         }
4650
4651         /* two situations
4652          * 1.type is not MAIN and uplink vsi is not NULL
4653          * If uplink vsi didn't setup VEB, create one first under veb field
4654          * 2.type is SRIOV and the uplink is NULL
4655          * If floating VEB is NULL, create one veb under floating veb field
4656          */
4657
4658         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4659             uplink_vsi->veb == NULL) {
4660                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4661
4662                 if (uplink_vsi->veb == NULL) {
4663                         PMD_DRV_LOG(ERR, "VEB setup failed");
4664                         return NULL;
4665                 }
4666                 /* set ALLOWLOOPBACk on pf, when veb is created */
4667                 i40e_enable_pf_lb(pf);
4668         }
4669
4670         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4671             pf->main_vsi->floating_veb == NULL) {
4672                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4673
4674                 if (pf->main_vsi->floating_veb == NULL) {
4675                         PMD_DRV_LOG(ERR, "VEB setup failed");
4676                         return NULL;
4677                 }
4678         }
4679
4680         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4681         if (!vsi) {
4682                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4683                 return NULL;
4684         }
4685         TAILQ_INIT(&vsi->mac_list);
4686         vsi->type = type;
4687         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4688         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4689         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4690         vsi->user_param = user_param;
4691         vsi->vlan_anti_spoof_on = 0;
4692         vsi->vlan_filter_on = 0;
4693         /* Allocate queues */
4694         switch (vsi->type) {
4695         case I40E_VSI_MAIN  :
4696                 vsi->nb_qps = pf->lan_nb_qps;
4697                 break;
4698         case I40E_VSI_SRIOV :
4699                 vsi->nb_qps = pf->vf_nb_qps;
4700                 break;
4701         case I40E_VSI_VMDQ2:
4702                 vsi->nb_qps = pf->vmdq_nb_qps;
4703                 break;
4704         case I40E_VSI_FDIR:
4705                 vsi->nb_qps = pf->fdir_nb_qps;
4706                 break;
4707         default:
4708                 goto fail_mem;
4709         }
4710         /*
4711          * The filter status descriptor is reported in rx queue 0,
4712          * while the tx queue for fdir filter programming has no
4713          * such constraints, can be non-zero queues.
4714          * To simplify it, choose FDIR vsi use queue 0 pair.
4715          * To make sure it will use queue 0 pair, queue allocation
4716          * need be done before this function is called
4717          */
4718         if (type != I40E_VSI_FDIR) {
4719                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4720                         if (ret < 0) {
4721                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4722                                                 vsi->seid, ret);
4723                                 goto fail_mem;
4724                         }
4725                         vsi->base_queue = ret;
4726         } else
4727                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4728
4729         /* VF has MSIX interrupt in VF range, don't allocate here */
4730         if (type == I40E_VSI_MAIN) {
4731                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4732                                           RTE_MIN(vsi->nb_qps,
4733                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4734                 if (ret < 0) {
4735                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4736                                     vsi->seid, ret);
4737                         goto fail_queue_alloc;
4738                 }
4739                 vsi->msix_intr = ret;
4740                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4741         } else if (type != I40E_VSI_SRIOV) {
4742                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4743                 if (ret < 0) {
4744                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4745                         goto fail_queue_alloc;
4746                 }
4747                 vsi->msix_intr = ret;
4748                 vsi->nb_msix = 1;
4749         } else {
4750                 vsi->msix_intr = 0;
4751                 vsi->nb_msix = 0;
4752         }
4753
4754         /* Add VSI */
4755         if (type == I40E_VSI_MAIN) {
4756                 /* For main VSI, no need to add since it's default one */
4757                 vsi->uplink_seid = pf->mac_seid;
4758                 vsi->seid = pf->main_vsi_seid;
4759                 /* Bind queues with specific MSIX interrupt */
4760                 /**
4761                  * Needs 2 interrupt at least, one for misc cause which will
4762                  * enabled from OS side, Another for queues binding the
4763                  * interrupt from device side only.
4764                  */
4765
4766                 /* Get default VSI parameters from hardware */
4767                 memset(&ctxt, 0, sizeof(ctxt));
4768                 ctxt.seid = vsi->seid;
4769                 ctxt.pf_num = hw->pf_id;
4770                 ctxt.uplink_seid = vsi->uplink_seid;
4771                 ctxt.vf_num = 0;
4772                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4773                 if (ret != I40E_SUCCESS) {
4774                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4775                         goto fail_msix_alloc;
4776                 }
4777                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4778                         sizeof(struct i40e_aqc_vsi_properties_data));
4779                 vsi->vsi_id = ctxt.vsi_number;
4780                 vsi->info.valid_sections = 0;
4781
4782                 /* Configure tc, enabled TC0 only */
4783                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4784                         I40E_SUCCESS) {
4785                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4786                         goto fail_msix_alloc;
4787                 }
4788
4789                 /* TC, queue mapping */
4790                 memset(&ctxt, 0, sizeof(ctxt));
4791                 vsi->info.valid_sections |=
4792                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4793                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4794                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4795                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4796                         sizeof(struct i40e_aqc_vsi_properties_data));
4797                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4798                                                 I40E_DEFAULT_TCMAP);
4799                 if (ret != I40E_SUCCESS) {
4800                         PMD_DRV_LOG(ERR,
4801                                 "Failed to configure TC queue mapping");
4802                         goto fail_msix_alloc;
4803                 }
4804                 ctxt.seid = vsi->seid;
4805                 ctxt.pf_num = hw->pf_id;
4806                 ctxt.uplink_seid = vsi->uplink_seid;
4807                 ctxt.vf_num = 0;
4808
4809                 /* Update VSI parameters */
4810                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4811                 if (ret != I40E_SUCCESS) {
4812                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4813                         goto fail_msix_alloc;
4814                 }
4815
4816                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4817                                                 sizeof(vsi->info.tc_mapping));
4818                 (void)rte_memcpy(&vsi->info.queue_mapping,
4819                                 &ctxt.info.queue_mapping,
4820                         sizeof(vsi->info.queue_mapping));
4821                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4822                 vsi->info.valid_sections = 0;
4823
4824                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4825                                 ETH_ADDR_LEN);
4826
4827                 /**
4828                  * Updating default filter settings are necessary to prevent
4829                  * reception of tagged packets.
4830                  * Some old firmware configurations load a default macvlan
4831                  * filter which accepts both tagged and untagged packets.
4832                  * The updating is to use a normal filter instead if needed.
4833                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4834                  * The firmware with correct configurations load the default
4835                  * macvlan filter which is expected and cannot be removed.
4836                  */
4837                 i40e_update_default_filter_setting(vsi);
4838                 i40e_config_qinq(hw, vsi);
4839         } else if (type == I40E_VSI_SRIOV) {
4840                 memset(&ctxt, 0, sizeof(ctxt));
4841                 /**
4842                  * For other VSI, the uplink_seid equals to uplink VSI's
4843                  * uplink_seid since they share same VEB
4844                  */
4845                 if (uplink_vsi == NULL)
4846                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4847                 else
4848                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4849                 ctxt.pf_num = hw->pf_id;
4850                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4851                 ctxt.uplink_seid = vsi->uplink_seid;
4852                 ctxt.connection_type = 0x1;
4853                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4854
4855                 /* Use the VEB configuration if FW >= v5.0 */
4856                 if (hw->aq.fw_maj_ver >= 5) {
4857                         /* Configure switch ID */
4858                         ctxt.info.valid_sections |=
4859                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4860                         ctxt.info.switch_id =
4861                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4862                 }
4863
4864                 /* Configure port/vlan */
4865                 ctxt.info.valid_sections |=
4866                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4867                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4868                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4869                                                 hw->func_caps.enabled_tcmap);
4870                 if (ret != I40E_SUCCESS) {
4871                         PMD_DRV_LOG(ERR,
4872                                 "Failed to configure TC queue mapping");
4873                         goto fail_msix_alloc;
4874                 }
4875
4876                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4877                 ctxt.info.valid_sections |=
4878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4879                 /**
4880                  * Since VSI is not created yet, only configure parameter,
4881                  * will add vsi below.
4882                  */
4883
4884                 i40e_config_qinq(hw, vsi);
4885         } else if (type == I40E_VSI_VMDQ2) {
4886                 memset(&ctxt, 0, sizeof(ctxt));
4887                 /*
4888                  * For other VSI, the uplink_seid equals to uplink VSI's
4889                  * uplink_seid since they share same VEB
4890                  */
4891                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4892                 ctxt.pf_num = hw->pf_id;
4893                 ctxt.vf_num = 0;
4894                 ctxt.uplink_seid = vsi->uplink_seid;
4895                 ctxt.connection_type = 0x1;
4896                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4897
4898                 ctxt.info.valid_sections |=
4899                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4900                 /* user_param carries flag to enable loop back */
4901                 if (user_param) {
4902                         ctxt.info.switch_id =
4903                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4904                         ctxt.info.switch_id |=
4905                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4906                 }
4907
4908                 /* Configure port/vlan */
4909                 ctxt.info.valid_sections |=
4910                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4911                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4912                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4913                                                 I40E_DEFAULT_TCMAP);
4914                 if (ret != I40E_SUCCESS) {
4915                         PMD_DRV_LOG(ERR,
4916                                 "Failed to configure TC queue mapping");
4917                         goto fail_msix_alloc;
4918                 }
4919                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4920                 ctxt.info.valid_sections |=
4921                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4922         } else if (type == I40E_VSI_FDIR) {
4923                 memset(&ctxt, 0, sizeof(ctxt));
4924                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4925                 ctxt.pf_num = hw->pf_id;
4926                 ctxt.vf_num = 0;
4927                 ctxt.uplink_seid = vsi->uplink_seid;
4928                 ctxt.connection_type = 0x1;     /* regular data port */
4929                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4930                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4931                                                 I40E_DEFAULT_TCMAP);
4932                 if (ret != I40E_SUCCESS) {
4933                         PMD_DRV_LOG(ERR,
4934                                 "Failed to configure TC queue mapping.");
4935                         goto fail_msix_alloc;
4936                 }
4937                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4938                 ctxt.info.valid_sections |=
4939                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4940         } else {
4941                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4942                 goto fail_msix_alloc;
4943         }
4944
4945         if (vsi->type != I40E_VSI_MAIN) {
4946                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4947                 if (ret != I40E_SUCCESS) {
4948                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4949                                     hw->aq.asq_last_status);
4950                         goto fail_msix_alloc;
4951                 }
4952                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4953                 vsi->info.valid_sections = 0;
4954                 vsi->seid = ctxt.seid;
4955                 vsi->vsi_id = ctxt.vsi_number;
4956                 vsi->sib_vsi_list.vsi = vsi;
4957                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4958                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4959                                           &vsi->sib_vsi_list, list);
4960                 } else {
4961                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4962                                           &vsi->sib_vsi_list, list);
4963                 }
4964         }
4965
4966         /* MAC/VLAN configuration */
4967         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4968         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4969
4970         ret = i40e_vsi_add_mac(vsi, &filter);
4971         if (ret != I40E_SUCCESS) {
4972                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4973                 goto fail_msix_alloc;
4974         }
4975
4976         /* Get VSI BW information */
4977         i40e_vsi_get_bw_config(vsi);
4978         return vsi;
4979 fail_msix_alloc:
4980         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4981 fail_queue_alloc:
4982         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4983 fail_mem:
4984         rte_free(vsi);
4985         return NULL;
4986 }
4987
4988 /* Configure vlan filter on or off */
4989 int
4990 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4991 {
4992         int i, num;
4993         struct i40e_mac_filter *f;
4994         void *temp;
4995         struct i40e_mac_filter_info *mac_filter;
4996         enum rte_mac_filter_type desired_filter;
4997         int ret = I40E_SUCCESS;
4998
4999         if (on) {
5000                 /* Filter to match MAC and VLAN */
5001                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5002         } else {
5003                 /* Filter to match only MAC */
5004                 desired_filter = RTE_MAC_PERFECT_MATCH;
5005         }
5006
5007         num = vsi->mac_num;
5008
5009         mac_filter = rte_zmalloc("mac_filter_info_data",
5010                                  num * sizeof(*mac_filter), 0);
5011         if (mac_filter == NULL) {
5012                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5013                 return I40E_ERR_NO_MEMORY;
5014         }
5015
5016         i = 0;
5017
5018         /* Remove all existing mac */
5019         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5020                 mac_filter[i] = f->mac_info;
5021                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5022                 if (ret) {
5023                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5024                                     on ? "enable" : "disable");
5025                         goto DONE;
5026                 }
5027                 i++;
5028         }
5029
5030         /* Override with new filter */
5031         for (i = 0; i < num; i++) {
5032                 mac_filter[i].filter_type = desired_filter;
5033                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5034                 if (ret) {
5035                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5036                                     on ? "enable" : "disable");
5037                         goto DONE;
5038                 }
5039         }
5040
5041 DONE:
5042         rte_free(mac_filter);
5043         return ret;
5044 }
5045
5046 /* Configure vlan stripping on or off */
5047 int
5048 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5049 {
5050         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5051         struct i40e_vsi_context ctxt;
5052         uint8_t vlan_flags;
5053         int ret = I40E_SUCCESS;
5054
5055         /* Check if it has been already on or off */
5056         if (vsi->info.valid_sections &
5057                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5058                 if (on) {
5059                         if ((vsi->info.port_vlan_flags &
5060                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5061                                 return 0; /* already on */
5062                 } else {
5063                         if ((vsi->info.port_vlan_flags &
5064                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5065                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5066                                 return 0; /* already off */
5067                 }
5068         }
5069
5070         if (on)
5071                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5072         else
5073                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5074         vsi->info.valid_sections =
5075                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5076         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5077         vsi->info.port_vlan_flags |= vlan_flags;
5078         ctxt.seid = vsi->seid;
5079         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5080         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5081         if (ret)
5082                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5083                             on ? "enable" : "disable");
5084
5085         return ret;
5086 }
5087
5088 static int
5089 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5090 {
5091         struct rte_eth_dev_data *data = dev->data;
5092         int ret;
5093         int mask = 0;
5094
5095         /* Apply vlan offload setting */
5096         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5097         i40e_vlan_offload_set(dev, mask);
5098
5099         /* Apply double-vlan setting, not implemented yet */
5100
5101         /* Apply pvid setting */
5102         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5103                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5104         if (ret)
5105                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5106
5107         return ret;
5108 }
5109
5110 static int
5111 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5112 {
5113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5114
5115         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5116 }
5117
5118 static int
5119 i40e_update_flow_control(struct i40e_hw *hw)
5120 {
5121 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5122         struct i40e_link_status link_status;
5123         uint32_t rxfc = 0, txfc = 0, reg;
5124         uint8_t an_info;
5125         int ret;
5126
5127         memset(&link_status, 0, sizeof(link_status));
5128         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5129         if (ret != I40E_SUCCESS) {
5130                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5131                 goto write_reg; /* Disable flow control */
5132         }
5133
5134         an_info = hw->phy.link_info.an_info;
5135         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5136                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5137                 ret = I40E_ERR_NOT_READY;
5138                 goto write_reg; /* Disable flow control */
5139         }
5140         /**
5141          * If link auto negotiation is enabled, flow control needs to
5142          * be configured according to it
5143          */
5144         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5145         case I40E_LINK_PAUSE_RXTX:
5146                 rxfc = 1;
5147                 txfc = 1;
5148                 hw->fc.current_mode = I40E_FC_FULL;
5149                 break;
5150         case I40E_AQ_LINK_PAUSE_RX:
5151                 rxfc = 1;
5152                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5153                 break;
5154         case I40E_AQ_LINK_PAUSE_TX:
5155                 txfc = 1;
5156                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5157                 break;
5158         default:
5159                 hw->fc.current_mode = I40E_FC_NONE;
5160                 break;
5161         }
5162
5163 write_reg:
5164         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5165                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5166         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5167         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5168         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5169         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5170
5171         return ret;
5172 }
5173
5174 /* PF setup */
5175 static int
5176 i40e_pf_setup(struct i40e_pf *pf)
5177 {
5178         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5179         struct i40e_filter_control_settings settings;
5180         struct i40e_vsi *vsi;
5181         int ret;
5182
5183         /* Clear all stats counters */
5184         pf->offset_loaded = FALSE;
5185         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5186         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5187
5188         ret = i40e_pf_get_switch_config(pf);
5189         if (ret != I40E_SUCCESS) {
5190                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5191                 return ret;
5192         }
5193         if (pf->flags & I40E_FLAG_FDIR) {
5194                 /* make queue allocated first, let FDIR use queue pair 0*/
5195                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5196                 if (ret != I40E_FDIR_QUEUE_ID) {
5197                         PMD_DRV_LOG(ERR,
5198                                 "queue allocation fails for FDIR: ret =%d",
5199                                 ret);
5200                         pf->flags &= ~I40E_FLAG_FDIR;
5201                 }
5202         }
5203         /*  main VSI setup */
5204         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5205         if (!vsi) {
5206                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5207                 return I40E_ERR_NOT_READY;
5208         }
5209         pf->main_vsi = vsi;
5210
5211         /* Configure filter control */
5212         memset(&settings, 0, sizeof(settings));
5213         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5214                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5215         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5216                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5217         else {
5218                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5219                         hw->func_caps.rss_table_size);
5220                 return I40E_ERR_PARAM;
5221         }
5222         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5223                 hw->func_caps.rss_table_size);
5224         pf->hash_lut_size = hw->func_caps.rss_table_size;
5225
5226         /* Enable ethtype and macvlan filters */
5227         settings.enable_ethtype = TRUE;
5228         settings.enable_macvlan = TRUE;
5229         ret = i40e_set_filter_control(hw, &settings);
5230         if (ret)
5231                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5232                                                                 ret);
5233
5234         /* Update flow control according to the auto negotiation */
5235         i40e_update_flow_control(hw);
5236
5237         return I40E_SUCCESS;
5238 }
5239
5240 int
5241 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5242 {
5243         uint32_t reg;
5244         uint16_t j;
5245
5246         /**
5247          * Set or clear TX Queue Disable flags,
5248          * which is required by hardware.
5249          */
5250         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5251         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5252
5253         /* Wait until the request is finished */
5254         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5255                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5256                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5257                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5258                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5259                                                         & 0x1))) {
5260                         break;
5261                 }
5262         }
5263         if (on) {
5264                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5265                         return I40E_SUCCESS; /* already on, skip next steps */
5266
5267                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5268                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5269         } else {
5270                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5271                         return I40E_SUCCESS; /* already off, skip next steps */
5272                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5273         }
5274         /* Write the register */
5275         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5276         /* Check the result */
5277         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5278                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5279                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5280                 if (on) {
5281                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5282                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5283                                 break;
5284                 } else {
5285                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5286                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5287                                 break;
5288                 }
5289         }
5290         /* Check if it is timeout */
5291         if (j >= I40E_CHK_Q_ENA_COUNT) {
5292                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5293                             (on ? "enable" : "disable"), q_idx);
5294                 return I40E_ERR_TIMEOUT;
5295         }
5296
5297         return I40E_SUCCESS;
5298 }
5299
5300 /* Swith on or off the tx queues */
5301 static int
5302 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5303 {
5304         struct rte_eth_dev_data *dev_data = pf->dev_data;
5305         struct i40e_tx_queue *txq;
5306         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5307         uint16_t i;
5308         int ret;
5309
5310         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5311                 txq = dev_data->tx_queues[i];
5312                 /* Don't operate the queue if not configured or
5313                  * if starting only per queue */
5314                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5315                         continue;
5316                 if (on)
5317                         ret = i40e_dev_tx_queue_start(dev, i);
5318                 else
5319                         ret = i40e_dev_tx_queue_stop(dev, i);
5320                 if ( ret != I40E_SUCCESS)
5321                         return ret;
5322         }
5323
5324         return I40E_SUCCESS;
5325 }
5326
5327 int
5328 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5329 {
5330         uint32_t reg;
5331         uint16_t j;
5332
5333         /* Wait until the request is finished */
5334         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5335                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5336                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5337                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5338                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5339                         break;
5340         }
5341
5342         if (on) {
5343                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5344                         return I40E_SUCCESS; /* Already on, skip next steps */
5345                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5346         } else {
5347                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5348                         return I40E_SUCCESS; /* Already off, skip next steps */
5349                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5350         }
5351
5352         /* Write the register */
5353         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5354         /* Check the result */
5355         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5356                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5357                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5358                 if (on) {
5359                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5360                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5361                                 break;
5362                 } else {
5363                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5364                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5365                                 break;
5366                 }
5367         }
5368
5369         /* Check if it is timeout */
5370         if (j >= I40E_CHK_Q_ENA_COUNT) {
5371                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5372                             (on ? "enable" : "disable"), q_idx);
5373                 return I40E_ERR_TIMEOUT;
5374         }
5375
5376         return I40E_SUCCESS;
5377 }
5378 /* Switch on or off the rx queues */
5379 static int
5380 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5381 {
5382         struct rte_eth_dev_data *dev_data = pf->dev_data;
5383         struct i40e_rx_queue *rxq;
5384         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5385         uint16_t i;
5386         int ret;
5387
5388         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5389                 rxq = dev_data->rx_queues[i];
5390                 /* Don't operate the queue if not configured or
5391                  * if starting only per queue */
5392                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5393                         continue;
5394                 if (on)
5395                         ret = i40e_dev_rx_queue_start(dev, i);
5396                 else
5397                         ret = i40e_dev_rx_queue_stop(dev, i);
5398                 if (ret != I40E_SUCCESS)
5399                         return ret;
5400         }
5401
5402         return I40E_SUCCESS;
5403 }
5404
5405 /* Switch on or off all the rx/tx queues */
5406 int
5407 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5408 {
5409         int ret;
5410
5411         if (on) {
5412                 /* enable rx queues before enabling tx queues */
5413                 ret = i40e_dev_switch_rx_queues(pf, on);
5414                 if (ret) {
5415                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5416                         return ret;
5417                 }
5418                 ret = i40e_dev_switch_tx_queues(pf, on);
5419         } else {
5420                 /* Stop tx queues before stopping rx queues */
5421                 ret = i40e_dev_switch_tx_queues(pf, on);
5422                 if (ret) {
5423                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5424                         return ret;
5425                 }
5426                 ret = i40e_dev_switch_rx_queues(pf, on);
5427         }
5428
5429         return ret;
5430 }
5431
5432 /* Initialize VSI for TX */
5433 static int
5434 i40e_dev_tx_init(struct i40e_pf *pf)
5435 {
5436         struct rte_eth_dev_data *data = pf->dev_data;
5437         uint16_t i;
5438         uint32_t ret = I40E_SUCCESS;
5439         struct i40e_tx_queue *txq;
5440
5441         for (i = 0; i < data->nb_tx_queues; i++) {
5442                 txq = data->tx_queues[i];
5443                 if (!txq || !txq->q_set)
5444                         continue;
5445                 ret = i40e_tx_queue_init(txq);
5446                 if (ret != I40E_SUCCESS)
5447                         break;
5448         }
5449         if (ret == I40E_SUCCESS)
5450                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5451                                      ->eth_dev);
5452
5453         return ret;
5454 }
5455
5456 /* Initialize VSI for RX */
5457 static int
5458 i40e_dev_rx_init(struct i40e_pf *pf)
5459 {
5460         struct rte_eth_dev_data *data = pf->dev_data;
5461         int ret = I40E_SUCCESS;
5462         uint16_t i;
5463         struct i40e_rx_queue *rxq;
5464
5465         i40e_pf_config_mq_rx(pf);
5466         for (i = 0; i < data->nb_rx_queues; i++) {
5467                 rxq = data->rx_queues[i];
5468                 if (!rxq || !rxq->q_set)
5469                         continue;
5470
5471                 ret = i40e_rx_queue_init(rxq);
5472                 if (ret != I40E_SUCCESS) {
5473                         PMD_DRV_LOG(ERR,
5474                                 "Failed to do RX queue initialization");
5475                         break;
5476                 }
5477         }
5478         if (ret == I40E_SUCCESS)
5479                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5480                                      ->eth_dev);
5481
5482         return ret;
5483 }
5484
5485 static int
5486 i40e_dev_rxtx_init(struct i40e_pf *pf)
5487 {
5488         int err;
5489
5490         err = i40e_dev_tx_init(pf);
5491         if (err) {
5492                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5493                 return err;
5494         }
5495         err = i40e_dev_rx_init(pf);
5496         if (err) {
5497                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5498                 return err;
5499         }
5500
5501         return err;
5502 }
5503
5504 static int
5505 i40e_vmdq_setup(struct rte_eth_dev *dev)
5506 {
5507         struct rte_eth_conf *conf = &dev->data->dev_conf;
5508         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5509         int i, err, conf_vsis, j, loop;
5510         struct i40e_vsi *vsi;
5511         struct i40e_vmdq_info *vmdq_info;
5512         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5513         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5514
5515         /*
5516          * Disable interrupt to avoid message from VF. Furthermore, it will
5517          * avoid race condition in VSI creation/destroy.
5518          */
5519         i40e_pf_disable_irq0(hw);
5520
5521         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5522                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5523                 return -ENOTSUP;
5524         }
5525
5526         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5527         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5528                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5529                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5530                         pf->max_nb_vmdq_vsi);
5531                 return -ENOTSUP;
5532         }
5533
5534         if (pf->vmdq != NULL) {
5535                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5536                 return 0;
5537         }
5538
5539         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5540                                 sizeof(*vmdq_info) * conf_vsis, 0);
5541
5542         if (pf->vmdq == NULL) {
5543                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5544                 return -ENOMEM;
5545         }
5546
5547         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5548
5549         /* Create VMDQ VSI */
5550         for (i = 0; i < conf_vsis; i++) {
5551                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5552                                 vmdq_conf->enable_loop_back);
5553                 if (vsi == NULL) {
5554                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5555                         err = -1;
5556                         goto err_vsi_setup;
5557                 }
5558                 vmdq_info = &pf->vmdq[i];
5559                 vmdq_info->pf = pf;
5560                 vmdq_info->vsi = vsi;
5561         }
5562         pf->nb_cfg_vmdq_vsi = conf_vsis;
5563
5564         /* Configure Vlan */
5565         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5566         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5567                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5568                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5569                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5570                                         vmdq_conf->pool_map[i].vlan_id, j);
5571
5572                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5573                                                 vmdq_conf->pool_map[i].vlan_id);
5574                                 if (err) {
5575                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5576                                         err = -1;
5577                                         goto err_vsi_setup;
5578                                 }
5579                         }
5580                 }
5581         }
5582
5583         i40e_pf_enable_irq0(hw);
5584
5585         return 0;
5586
5587 err_vsi_setup:
5588         for (i = 0; i < conf_vsis; i++)
5589                 if (pf->vmdq[i].vsi == NULL)
5590                         break;
5591                 else
5592                         i40e_vsi_release(pf->vmdq[i].vsi);
5593
5594         rte_free(pf->vmdq);
5595         pf->vmdq = NULL;
5596         i40e_pf_enable_irq0(hw);
5597         return err;
5598 }
5599
5600 static void
5601 i40e_stat_update_32(struct i40e_hw *hw,
5602                    uint32_t reg,
5603                    bool offset_loaded,
5604                    uint64_t *offset,
5605                    uint64_t *stat)
5606 {
5607         uint64_t new_data;
5608
5609         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5610         if (!offset_loaded)
5611                 *offset = new_data;
5612
5613         if (new_data >= *offset)
5614                 *stat = (uint64_t)(new_data - *offset);
5615         else
5616                 *stat = (uint64_t)((new_data +
5617                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5618 }
5619
5620 static void
5621 i40e_stat_update_48(struct i40e_hw *hw,
5622                    uint32_t hireg,
5623                    uint32_t loreg,
5624                    bool offset_loaded,
5625                    uint64_t *offset,
5626                    uint64_t *stat)
5627 {
5628         uint64_t new_data;
5629
5630         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5631         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5632                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5633
5634         if (!offset_loaded)
5635                 *offset = new_data;
5636
5637         if (new_data >= *offset)
5638                 *stat = new_data - *offset;
5639         else
5640                 *stat = (uint64_t)((new_data +
5641                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5642
5643         *stat &= I40E_48_BIT_MASK;
5644 }
5645
5646 /* Disable IRQ0 */
5647 void
5648 i40e_pf_disable_irq0(struct i40e_hw *hw)
5649 {
5650         /* Disable all interrupt types */
5651         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5652         I40E_WRITE_FLUSH(hw);
5653 }
5654
5655 /* Enable IRQ0 */
5656 void
5657 i40e_pf_enable_irq0(struct i40e_hw *hw)
5658 {
5659         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5660                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5661                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5662                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5663         I40E_WRITE_FLUSH(hw);
5664 }
5665
5666 static void
5667 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5668 {
5669         /* read pending request and disable first */
5670         i40e_pf_disable_irq0(hw);
5671         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5672         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5673                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5674
5675         if (no_queue)
5676                 /* Link no queues with irq0 */
5677                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5678                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5679 }
5680
5681 static void
5682 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5683 {
5684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5686         int i;
5687         uint16_t abs_vf_id;
5688         uint32_t index, offset, val;
5689
5690         if (!pf->vfs)
5691                 return;
5692         /**
5693          * Try to find which VF trigger a reset, use absolute VF id to access
5694          * since the reg is global register.
5695          */
5696         for (i = 0; i < pf->vf_num; i++) {
5697                 abs_vf_id = hw->func_caps.vf_base_id + i;
5698                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5699                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5700                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5701                 /* VFR event occured */
5702                 if (val & (0x1 << offset)) {
5703                         int ret;
5704
5705                         /* Clear the event first */
5706                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5707                                                         (0x1 << offset));
5708                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5709                         /**
5710                          * Only notify a VF reset event occured,
5711                          * don't trigger another SW reset
5712                          */
5713                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5714                         if (ret != I40E_SUCCESS)
5715                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5716                 }
5717         }
5718 }
5719
5720 static void
5721 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5722 {
5723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5724         struct i40e_virtchnl_pf_event event;
5725         int i;
5726
5727         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5728         event.event_data.link_event.link_status =
5729                 dev->data->dev_link.link_status;
5730         event.event_data.link_event.link_speed =
5731                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5732
5733         for (i = 0; i < pf->vf_num; i++)
5734                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5735                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5736 }
5737
5738 static void
5739 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5740 {
5741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742         struct i40e_arq_event_info info;
5743         uint16_t pending, opcode;
5744         int ret;
5745
5746         info.buf_len = I40E_AQ_BUF_SZ;
5747         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5748         if (!info.msg_buf) {
5749                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5750                 return;
5751         }
5752
5753         pending = 1;
5754         while (pending) {
5755                 ret = i40e_clean_arq_element(hw, &info, &pending);
5756
5757                 if (ret != I40E_SUCCESS) {
5758                         PMD_DRV_LOG(INFO,
5759                                 "Failed to read msg from AdminQ, aq_err: %u",
5760                                 hw->aq.asq_last_status);
5761                         break;
5762                 }
5763                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5764
5765                 switch (opcode) {
5766                 case i40e_aqc_opc_send_msg_to_pf:
5767                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5768                         i40e_pf_host_handle_vf_msg(dev,
5769                                         rte_le_to_cpu_16(info.desc.retval),
5770                                         rte_le_to_cpu_32(info.desc.cookie_high),
5771                                         rte_le_to_cpu_32(info.desc.cookie_low),
5772                                         info.msg_buf,
5773                                         info.msg_len);
5774                         break;
5775                 case i40e_aqc_opc_get_link_status:
5776                         ret = i40e_dev_link_update(dev, 0);
5777                         if (!ret) {
5778                                 i40e_notify_all_vfs_link_status(dev);
5779                                 _rte_eth_dev_callback_process(dev,
5780                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5781                         }
5782                         break;
5783                 default:
5784                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5785                                     opcode);
5786                         break;
5787                 }
5788         }
5789         rte_free(info.msg_buf);
5790 }
5791
5792 /**
5793  * Interrupt handler triggered by NIC  for handling
5794  * specific interrupt.
5795  *
5796  * @param handle
5797  *  Pointer to interrupt handle.
5798  * @param param
5799  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5800  *
5801  * @return
5802  *  void
5803  */
5804 static void
5805 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5806                            void *param)
5807 {
5808         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5810         uint32_t icr0;
5811
5812         /* Disable interrupt */
5813         i40e_pf_disable_irq0(hw);
5814
5815         /* read out interrupt causes */
5816         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5817
5818         /* No interrupt event indicated */
5819         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5820                 PMD_DRV_LOG(INFO, "No interrupt event");
5821                 goto done;
5822         }
5823 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5824         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5825                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5826         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5827                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5828         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5829                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5830         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5831                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5832         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5833                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5834         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5835                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5836         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5837                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5838 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5839
5840         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5841                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5842                 i40e_dev_handle_vfr_event(dev);
5843         }
5844         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5845                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5846                 i40e_dev_handle_aq_msg(dev);
5847         }
5848
5849 done:
5850         /* Enable interrupt */
5851         i40e_pf_enable_irq0(hw);
5852         rte_intr_enable(intr_handle);
5853 }
5854
5855 static int
5856 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5857                          struct i40e_macvlan_filter *filter,
5858                          int total)
5859 {
5860         int ele_num, ele_buff_size;
5861         int num, actual_num, i;
5862         uint16_t flags;
5863         int ret = I40E_SUCCESS;
5864         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5865         struct i40e_aqc_add_macvlan_element_data *req_list;
5866
5867         if (filter == NULL  || total == 0)
5868                 return I40E_ERR_PARAM;
5869         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5870         ele_buff_size = hw->aq.asq_buf_size;
5871
5872         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5873         if (req_list == NULL) {
5874                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5875                 return I40E_ERR_NO_MEMORY;
5876         }
5877
5878         num = 0;
5879         do {
5880                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5881                 memset(req_list, 0, ele_buff_size);
5882
5883                 for (i = 0; i < actual_num; i++) {
5884                         (void)rte_memcpy(req_list[i].mac_addr,
5885                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5886                         req_list[i].vlan_tag =
5887                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5888
5889                         switch (filter[num + i].filter_type) {
5890                         case RTE_MAC_PERFECT_MATCH:
5891                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5892                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5893                                 break;
5894                         case RTE_MACVLAN_PERFECT_MATCH:
5895                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5896                                 break;
5897                         case RTE_MAC_HASH_MATCH:
5898                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5899                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5900                                 break;
5901                         case RTE_MACVLAN_HASH_MATCH:
5902                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5903                                 break;
5904                         default:
5905                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5906                                 ret = I40E_ERR_PARAM;
5907                                 goto DONE;
5908                         }
5909
5910                         req_list[i].queue_number = 0;
5911
5912                         req_list[i].flags = rte_cpu_to_le_16(flags);
5913                 }
5914
5915                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5916                                                 actual_num, NULL);
5917                 if (ret != I40E_SUCCESS) {
5918                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5919                         goto DONE;
5920                 }
5921                 num += actual_num;
5922         } while (num < total);
5923
5924 DONE:
5925         rte_free(req_list);
5926         return ret;
5927 }
5928
5929 static int
5930 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5931                             struct i40e_macvlan_filter *filter,
5932                             int total)
5933 {
5934         int ele_num, ele_buff_size;
5935         int num, actual_num, i;
5936         uint16_t flags;
5937         int ret = I40E_SUCCESS;
5938         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5939         struct i40e_aqc_remove_macvlan_element_data *req_list;
5940
5941         if (filter == NULL  || total == 0)
5942                 return I40E_ERR_PARAM;
5943
5944         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5945         ele_buff_size = hw->aq.asq_buf_size;
5946
5947         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5948         if (req_list == NULL) {
5949                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5950                 return I40E_ERR_NO_MEMORY;
5951         }
5952
5953         num = 0;
5954         do {
5955                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5956                 memset(req_list, 0, ele_buff_size);
5957
5958                 for (i = 0; i < actual_num; i++) {
5959                         (void)rte_memcpy(req_list[i].mac_addr,
5960                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5961                         req_list[i].vlan_tag =
5962                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5963
5964                         switch (filter[num + i].filter_type) {
5965                         case RTE_MAC_PERFECT_MATCH:
5966                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5967                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5968                                 break;
5969                         case RTE_MACVLAN_PERFECT_MATCH:
5970                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5971                                 break;
5972                         case RTE_MAC_HASH_MATCH:
5973                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5974                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5975                                 break;
5976                         case RTE_MACVLAN_HASH_MATCH:
5977                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5978                                 break;
5979                         default:
5980                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5981                                 ret = I40E_ERR_PARAM;
5982                                 goto DONE;
5983                         }
5984                         req_list[i].flags = rte_cpu_to_le_16(flags);
5985                 }
5986
5987                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5988                                                 actual_num, NULL);
5989                 if (ret != I40E_SUCCESS) {
5990                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5991                         goto DONE;
5992                 }
5993                 num += actual_num;
5994         } while (num < total);
5995
5996 DONE:
5997         rte_free(req_list);
5998         return ret;
5999 }
6000
6001 /* Find out specific MAC filter */
6002 static struct i40e_mac_filter *
6003 i40e_find_mac_filter(struct i40e_vsi *vsi,
6004                          struct ether_addr *macaddr)
6005 {
6006         struct i40e_mac_filter *f;
6007
6008         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6009                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6010                         return f;
6011         }
6012
6013         return NULL;
6014 }
6015
6016 static bool
6017 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6018                          uint16_t vlan_id)
6019 {
6020         uint32_t vid_idx, vid_bit;
6021
6022         if (vlan_id > ETH_VLAN_ID_MAX)
6023                 return 0;
6024
6025         vid_idx = I40E_VFTA_IDX(vlan_id);
6026         vid_bit = I40E_VFTA_BIT(vlan_id);
6027
6028         if (vsi->vfta[vid_idx] & vid_bit)
6029                 return 1;
6030         else
6031                 return 0;
6032 }
6033
6034 static void
6035 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6036                        uint16_t vlan_id, bool on)
6037 {
6038         uint32_t vid_idx, vid_bit;
6039
6040         vid_idx = I40E_VFTA_IDX(vlan_id);
6041         vid_bit = I40E_VFTA_BIT(vlan_id);
6042
6043         if (on)
6044                 vsi->vfta[vid_idx] |= vid_bit;
6045         else
6046                 vsi->vfta[vid_idx] &= ~vid_bit;
6047 }
6048
6049 static void
6050 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6051                      uint16_t vlan_id, bool on)
6052 {
6053         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6054         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6055         int ret;
6056
6057         if (vlan_id > ETH_VLAN_ID_MAX)
6058                 return;
6059
6060         i40e_store_vlan_filter(vsi, vlan_id, on);
6061
6062         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6063                 return;
6064
6065         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6066
6067         if (on) {
6068                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6069                                        &vlan_data, 1, NULL);
6070                 if (ret != I40E_SUCCESS)
6071                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6072         } else {
6073                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6074                                           &vlan_data, 1, NULL);
6075                 if (ret != I40E_SUCCESS)
6076                         PMD_DRV_LOG(ERR,
6077                                     "Failed to remove vlan filter");
6078         }
6079 }
6080
6081 /**
6082  * Find all vlan options for specific mac addr,
6083  * return with actual vlan found.
6084  */
6085 static inline int
6086 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6087                            struct i40e_macvlan_filter *mv_f,
6088                            int num, struct ether_addr *addr)
6089 {
6090         int i;
6091         uint32_t j, k;
6092
6093         /**
6094          * Not to use i40e_find_vlan_filter to decrease the loop time,
6095          * although the code looks complex.
6096           */
6097         if (num < vsi->vlan_num)
6098                 return I40E_ERR_PARAM;
6099
6100         i = 0;
6101         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6102                 if (vsi->vfta[j]) {
6103                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6104                                 if (vsi->vfta[j] & (1 << k)) {
6105                                         if (i > num - 1) {
6106                                                 PMD_DRV_LOG(ERR,
6107                                                         "vlan number doesn't match");
6108                                                 return I40E_ERR_PARAM;
6109                                         }
6110                                         (void)rte_memcpy(&mv_f[i].macaddr,
6111                                                         addr, ETH_ADDR_LEN);
6112                                         mv_f[i].vlan_id =
6113                                                 j * I40E_UINT32_BIT_SIZE + k;
6114                                         i++;
6115                                 }
6116                         }
6117                 }
6118         }
6119         return I40E_SUCCESS;
6120 }
6121
6122 static inline int
6123 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6124                            struct i40e_macvlan_filter *mv_f,
6125                            int num,
6126                            uint16_t vlan)
6127 {
6128         int i = 0;
6129         struct i40e_mac_filter *f;
6130
6131         if (num < vsi->mac_num)
6132                 return I40E_ERR_PARAM;
6133
6134         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6135                 if (i > num - 1) {
6136                         PMD_DRV_LOG(ERR, "buffer number not match");
6137                         return I40E_ERR_PARAM;
6138                 }
6139                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6140                                 ETH_ADDR_LEN);
6141                 mv_f[i].vlan_id = vlan;
6142                 mv_f[i].filter_type = f->mac_info.filter_type;
6143                 i++;
6144         }
6145
6146         return I40E_SUCCESS;
6147 }
6148
6149 static int
6150 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6151 {
6152         int i, j, num;
6153         struct i40e_mac_filter *f;
6154         struct i40e_macvlan_filter *mv_f;
6155         int ret = I40E_SUCCESS;
6156
6157         if (vsi == NULL || vsi->mac_num == 0)
6158                 return I40E_ERR_PARAM;
6159
6160         /* Case that no vlan is set */
6161         if (vsi->vlan_num == 0)
6162                 num = vsi->mac_num;
6163         else
6164                 num = vsi->mac_num * vsi->vlan_num;
6165
6166         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6167         if (mv_f == NULL) {
6168                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6169                 return I40E_ERR_NO_MEMORY;
6170         }
6171
6172         i = 0;
6173         if (vsi->vlan_num == 0) {
6174                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6175                         (void)rte_memcpy(&mv_f[i].macaddr,
6176                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6177                         mv_f[i].filter_type = f->mac_info.filter_type;
6178                         mv_f[i].vlan_id = 0;
6179                         i++;
6180                 }
6181         } else {
6182                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6183                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6184                                         vsi->vlan_num, &f->mac_info.mac_addr);
6185                         if (ret != I40E_SUCCESS)
6186                                 goto DONE;
6187                         for (j = i; j < i + vsi->vlan_num; j++)
6188                                 mv_f[j].filter_type = f->mac_info.filter_type;
6189                         i += vsi->vlan_num;
6190                 }
6191         }
6192
6193         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6194 DONE:
6195         rte_free(mv_f);
6196
6197         return ret;
6198 }
6199
6200 int
6201 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6202 {
6203         struct i40e_macvlan_filter *mv_f;
6204         int mac_num;
6205         int ret = I40E_SUCCESS;
6206
6207         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6208                 return I40E_ERR_PARAM;
6209
6210         /* If it's already set, just return */
6211         if (i40e_find_vlan_filter(vsi,vlan))
6212                 return I40E_SUCCESS;
6213
6214         mac_num = vsi->mac_num;
6215
6216         if (mac_num == 0) {
6217                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6218                 return I40E_ERR_PARAM;
6219         }
6220
6221         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6222
6223         if (mv_f == NULL) {
6224                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6225                 return I40E_ERR_NO_MEMORY;
6226         }
6227
6228         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6229
6230         if (ret != I40E_SUCCESS)
6231                 goto DONE;
6232
6233         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6234
6235         if (ret != I40E_SUCCESS)
6236                 goto DONE;
6237
6238         i40e_set_vlan_filter(vsi, vlan, 1);
6239
6240         vsi->vlan_num++;
6241         ret = I40E_SUCCESS;
6242 DONE:
6243         rte_free(mv_f);
6244         return ret;
6245 }
6246
6247 int
6248 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6249 {
6250         struct i40e_macvlan_filter *mv_f;
6251         int mac_num;
6252         int ret = I40E_SUCCESS;
6253
6254         /**
6255          * Vlan 0 is the generic filter for untagged packets
6256          * and can't be removed.
6257          */
6258         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6259                 return I40E_ERR_PARAM;
6260
6261         /* If can't find it, just return */
6262         if (!i40e_find_vlan_filter(vsi, vlan))
6263                 return I40E_ERR_PARAM;
6264
6265         mac_num = vsi->mac_num;
6266
6267         if (mac_num == 0) {
6268                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6269                 return I40E_ERR_PARAM;
6270         }
6271
6272         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6273
6274         if (mv_f == NULL) {
6275                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6276                 return I40E_ERR_NO_MEMORY;
6277         }
6278
6279         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6280
6281         if (ret != I40E_SUCCESS)
6282                 goto DONE;
6283
6284         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6285
6286         if (ret != I40E_SUCCESS)
6287                 goto DONE;
6288
6289         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6290         if (vsi->vlan_num == 1) {
6291                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6292                 if (ret != I40E_SUCCESS)
6293                         goto DONE;
6294
6295                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6296                 if (ret != I40E_SUCCESS)
6297                         goto DONE;
6298         }
6299
6300         i40e_set_vlan_filter(vsi, vlan, 0);
6301
6302         vsi->vlan_num--;
6303         ret = I40E_SUCCESS;
6304 DONE:
6305         rte_free(mv_f);
6306         return ret;
6307 }
6308
6309 int
6310 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6311 {
6312         struct i40e_mac_filter *f;
6313         struct i40e_macvlan_filter *mv_f;
6314         int i, vlan_num = 0;
6315         int ret = I40E_SUCCESS;
6316
6317         /* If it's add and we've config it, return */
6318         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6319         if (f != NULL)
6320                 return I40E_SUCCESS;
6321         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6322                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6323
6324                 /**
6325                  * If vlan_num is 0, that's the first time to add mac,
6326                  * set mask for vlan_id 0.
6327                  */
6328                 if (vsi->vlan_num == 0) {
6329                         i40e_set_vlan_filter(vsi, 0, 1);
6330                         vsi->vlan_num = 1;
6331                 }
6332                 vlan_num = vsi->vlan_num;
6333         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6334                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6335                 vlan_num = 1;
6336
6337         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6338         if (mv_f == NULL) {
6339                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6340                 return I40E_ERR_NO_MEMORY;
6341         }
6342
6343         for (i = 0; i < vlan_num; i++) {
6344                 mv_f[i].filter_type = mac_filter->filter_type;
6345                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6346                                 ETH_ADDR_LEN);
6347         }
6348
6349         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6350                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6351                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6352                                         &mac_filter->mac_addr);
6353                 if (ret != I40E_SUCCESS)
6354                         goto DONE;
6355         }
6356
6357         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6358         if (ret != I40E_SUCCESS)
6359                 goto DONE;
6360
6361         /* Add the mac addr into mac list */
6362         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6363         if (f == NULL) {
6364                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6365                 ret = I40E_ERR_NO_MEMORY;
6366                 goto DONE;
6367         }
6368         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6369                         ETH_ADDR_LEN);
6370         f->mac_info.filter_type = mac_filter->filter_type;
6371         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6372         vsi->mac_num++;
6373
6374         ret = I40E_SUCCESS;
6375 DONE:
6376         rte_free(mv_f);
6377
6378         return ret;
6379 }
6380
6381 int
6382 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6383 {
6384         struct i40e_mac_filter *f;
6385         struct i40e_macvlan_filter *mv_f;
6386         int i, vlan_num;
6387         enum rte_mac_filter_type filter_type;
6388         int ret = I40E_SUCCESS;
6389
6390         /* Can't find it, return an error */
6391         f = i40e_find_mac_filter(vsi, addr);
6392         if (f == NULL)
6393                 return I40E_ERR_PARAM;
6394
6395         vlan_num = vsi->vlan_num;
6396         filter_type = f->mac_info.filter_type;
6397         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6398                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6399                 if (vlan_num == 0) {
6400                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6401                         return I40E_ERR_PARAM;
6402                 }
6403         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6404                         filter_type == RTE_MAC_HASH_MATCH)
6405                 vlan_num = 1;
6406
6407         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6408         if (mv_f == NULL) {
6409                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6410                 return I40E_ERR_NO_MEMORY;
6411         }
6412
6413         for (i = 0; i < vlan_num; i++) {
6414                 mv_f[i].filter_type = filter_type;
6415                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6416                                 ETH_ADDR_LEN);
6417         }
6418         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6419                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6420                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6421                 if (ret != I40E_SUCCESS)
6422                         goto DONE;
6423         }
6424
6425         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6426         if (ret != I40E_SUCCESS)
6427                 goto DONE;
6428
6429         /* Remove the mac addr into mac list */
6430         TAILQ_REMOVE(&vsi->mac_list, f, next);
6431         rte_free(f);
6432         vsi->mac_num--;
6433
6434         ret = I40E_SUCCESS;
6435 DONE:
6436         rte_free(mv_f);
6437         return ret;
6438 }
6439
6440 /* Configure hash enable flags for RSS */
6441 uint64_t
6442 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6443 {
6444         uint64_t hena = 0;
6445
6446         if (!flags)
6447                 return hena;
6448
6449         if (flags & ETH_RSS_FRAG_IPV4)
6450                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6451         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6452                 if (type == I40E_MAC_X722) {
6453                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6454                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6455                 } else
6456                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6457         }
6458         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6459                 if (type == I40E_MAC_X722) {
6460                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6461                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6462                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6463                 } else
6464                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6465         }
6466         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6467                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6468         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6469                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6470         if (flags & ETH_RSS_FRAG_IPV6)
6471                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6472         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6473                 if (type == I40E_MAC_X722) {
6474                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6475                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6476                 } else
6477                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6478         }
6479         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6480                 if (type == I40E_MAC_X722) {
6481                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6482                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6483                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6484                 } else
6485                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6486         }
6487         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6488                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6489         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6490                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6491         if (flags & ETH_RSS_L2_PAYLOAD)
6492                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6493
6494         return hena;
6495 }
6496
6497 /* Parse the hash enable flags */
6498 uint64_t
6499 i40e_parse_hena(uint64_t flags)
6500 {
6501         uint64_t rss_hf = 0;
6502
6503         if (!flags)
6504                 return rss_hf;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6506                 rss_hf |= ETH_RSS_FRAG_IPV4;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6508                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6511         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6512                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6513         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6514                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6515         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6516                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6518                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6519         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6520                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6522                 rss_hf |= ETH_RSS_FRAG_IPV6;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6524                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6534                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6535         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6536                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6537         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6538                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6539
6540         return rss_hf;
6541 }
6542
6543 /* Disable RSS */
6544 static void
6545 i40e_pf_disable_rss(struct i40e_pf *pf)
6546 {
6547         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6548         uint64_t hena;
6549
6550         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6551         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6552         if (hw->mac.type == I40E_MAC_X722)
6553                 hena &= ~I40E_RSS_HENA_ALL_X722;
6554         else
6555                 hena &= ~I40E_RSS_HENA_ALL;
6556         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6557         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6558         I40E_WRITE_FLUSH(hw);
6559 }
6560
6561 static int
6562 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6563 {
6564         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6566         int ret = 0;
6567
6568         if (!key || key_len == 0) {
6569                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6570                 return 0;
6571         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6572                 sizeof(uint32_t)) {
6573                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6574                 return -EINVAL;
6575         }
6576
6577         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6578                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6579                         (struct i40e_aqc_get_set_rss_key_data *)key;
6580
6581                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6582                 if (ret)
6583                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6584         } else {
6585                 uint32_t *hash_key = (uint32_t *)key;
6586                 uint16_t i;
6587
6588                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6589                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6590                 I40E_WRITE_FLUSH(hw);
6591         }
6592
6593         return ret;
6594 }
6595
6596 static int
6597 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6598 {
6599         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6600         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6601         int ret;
6602
6603         if (!key || !key_len)
6604                 return -EINVAL;
6605
6606         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6607                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6608                         (struct i40e_aqc_get_set_rss_key_data *)key);
6609                 if (ret) {
6610                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6611                         return ret;
6612                 }
6613         } else {
6614                 uint32_t *key_dw = (uint32_t *)key;
6615                 uint16_t i;
6616
6617                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6618                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6619         }
6620         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6621
6622         return 0;
6623 }
6624
6625 static int
6626 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6627 {
6628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6629         uint64_t rss_hf;
6630         uint64_t hena;
6631         int ret;
6632
6633         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6634                                rss_conf->rss_key_len);
6635         if (ret)
6636                 return ret;
6637
6638         rss_hf = rss_conf->rss_hf;
6639         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6640         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6641         if (hw->mac.type == I40E_MAC_X722)
6642                 hena &= ~I40E_RSS_HENA_ALL_X722;
6643         else
6644                 hena &= ~I40E_RSS_HENA_ALL;
6645         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6646         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6647         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6648         I40E_WRITE_FLUSH(hw);
6649
6650         return 0;
6651 }
6652
6653 static int
6654 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6655                          struct rte_eth_rss_conf *rss_conf)
6656 {
6657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6659         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6660         uint64_t hena;
6661
6662         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6663         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6664         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6665                  ? I40E_RSS_HENA_ALL_X722
6666                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6667                 if (rss_hf != 0) /* Enable RSS */
6668                         return -EINVAL;
6669                 return 0; /* Nothing to do */
6670         }
6671         /* RSS enabled */
6672         if (rss_hf == 0) /* Disable RSS */
6673                 return -EINVAL;
6674
6675         return i40e_hw_rss_hash_set(pf, rss_conf);
6676 }
6677
6678 static int
6679 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6680                            struct rte_eth_rss_conf *rss_conf)
6681 {
6682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684         uint64_t hena;
6685
6686         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6687                          &rss_conf->rss_key_len);
6688
6689         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6690         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6691         rss_conf->rss_hf = i40e_parse_hena(hena);
6692
6693         return 0;
6694 }
6695
6696 static int
6697 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6698 {
6699         switch (filter_type) {
6700         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6701                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6702                 break;
6703         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6704                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6705                 break;
6706         case RTE_TUNNEL_FILTER_IMAC_TENID:
6707                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6708                 break;
6709         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6710                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6711                 break;
6712         case ETH_TUNNEL_FILTER_IMAC:
6713                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6714                 break;
6715         case ETH_TUNNEL_FILTER_OIP:
6716                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6717                 break;
6718         case ETH_TUNNEL_FILTER_IIP:
6719                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6720                 break;
6721         default:
6722                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6723                 return -EINVAL;
6724         }
6725
6726         return 0;
6727 }
6728
6729 /* Convert tunnel filter structure */
6730 static int
6731 i40e_tunnel_filter_convert(
6732         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6733         struct i40e_tunnel_filter *tunnel_filter)
6734 {
6735         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6736                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6737         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6738                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6739         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6740         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6741              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6742             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6743                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6744         else
6745                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6746         tunnel_filter->input.flags = cld_filter->element.flags;
6747         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6748         tunnel_filter->queue = cld_filter->element.queue_number;
6749         rte_memcpy(tunnel_filter->input.general_fields,
6750                    cld_filter->general_fields,
6751                    sizeof(cld_filter->general_fields));
6752
6753         return 0;
6754 }
6755
6756 /* Check if there exists the tunnel filter */
6757 struct i40e_tunnel_filter *
6758 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6759                              const struct i40e_tunnel_filter_input *input)
6760 {
6761         int ret;
6762
6763         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6764         if (ret < 0)
6765                 return NULL;
6766
6767         return tunnel_rule->hash_map[ret];
6768 }
6769
6770 /* Add a tunnel filter into the SW list */
6771 static int
6772 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6773                              struct i40e_tunnel_filter *tunnel_filter)
6774 {
6775         struct i40e_tunnel_rule *rule = &pf->tunnel;
6776         int ret;
6777
6778         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6779         if (ret < 0) {
6780                 PMD_DRV_LOG(ERR,
6781                             "Failed to insert tunnel filter to hash table %d!",
6782                             ret);
6783                 return ret;
6784         }
6785         rule->hash_map[ret] = tunnel_filter;
6786
6787         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6788
6789         return 0;
6790 }
6791
6792 /* Delete a tunnel filter from the SW list */
6793 int
6794 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6795                           struct i40e_tunnel_filter_input *input)
6796 {
6797         struct i40e_tunnel_rule *rule = &pf->tunnel;
6798         struct i40e_tunnel_filter *tunnel_filter;
6799         int ret;
6800
6801         ret = rte_hash_del_key(rule->hash_table, input);
6802         if (ret < 0) {
6803                 PMD_DRV_LOG(ERR,
6804                             "Failed to delete tunnel filter to hash table %d!",
6805                             ret);
6806                 return ret;
6807         }
6808         tunnel_filter = rule->hash_map[ret];
6809         rule->hash_map[ret] = NULL;
6810
6811         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6812         rte_free(tunnel_filter);
6813
6814         return 0;
6815 }
6816
6817 int
6818 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6819                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6820                         uint8_t add)
6821 {
6822         uint16_t ip_type;
6823         uint32_t ipv4_addr;
6824         uint8_t i, tun_type = 0;
6825         /* internal varialbe to convert ipv6 byte order */
6826         uint32_t convert_ipv6[4];
6827         int val, ret = 0;
6828         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6829         struct i40e_vsi *vsi = pf->main_vsi;
6830         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6831         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6832         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6833         struct i40e_tunnel_filter *tunnel, *node;
6834         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6835
6836         cld_filter = rte_zmalloc("tunnel_filter",
6837                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6838         0);
6839
6840         if (NULL == cld_filter) {
6841                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6842                 return -ENOMEM;
6843         }
6844         pfilter = cld_filter;
6845
6846         ether_addr_copy(&tunnel_filter->outer_mac,
6847                         (struct ether_addr *)&pfilter->element.outer_mac);
6848         ether_addr_copy(&tunnel_filter->inner_mac,
6849                         (struct ether_addr *)&pfilter->element.inner_mac);
6850
6851         pfilter->element.inner_vlan =
6852                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6853         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6854                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6855                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6856                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6857                                 &rte_cpu_to_le_32(ipv4_addr),
6858                                 sizeof(pfilter->element.ipaddr.v4.data));
6859         } else {
6860                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6861                 for (i = 0; i < 4; i++) {
6862                         convert_ipv6[i] =
6863                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6864                 }
6865                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6866                            &convert_ipv6,
6867                            sizeof(pfilter->element.ipaddr.v6.data));
6868         }
6869
6870         /* check tunneled type */
6871         switch (tunnel_filter->tunnel_type) {
6872         case RTE_TUNNEL_TYPE_VXLAN:
6873                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6874                 break;
6875         case RTE_TUNNEL_TYPE_NVGRE:
6876                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6877                 break;
6878         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6879                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6880                 break;
6881         default:
6882                 /* Other tunnel types is not supported. */
6883                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6884                 rte_free(cld_filter);
6885                 return -EINVAL;
6886         }
6887
6888         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6889                                        &pfilter->element.flags);
6890         if (val < 0) {
6891                 rte_free(cld_filter);
6892                 return -EINVAL;
6893         }
6894
6895         pfilter->element.flags |= rte_cpu_to_le_16(
6896                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6897                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6898         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6899         pfilter->element.queue_number =
6900                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6901
6902         /* Check if there is the filter in SW list */
6903         memset(&check_filter, 0, sizeof(check_filter));
6904         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6905         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6906         if (add && node) {
6907                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6908                 return -EINVAL;
6909         }
6910
6911         if (!add && !node) {
6912                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6913                 return -EINVAL;
6914         }
6915
6916         if (add) {
6917                 ret = i40e_aq_add_cloud_filters(hw,
6918                                         vsi->seid, &cld_filter->element, 1);
6919                 if (ret < 0) {
6920                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6921                         return -ENOTSUP;
6922                 }
6923                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6924                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6925                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6926         } else {
6927                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6928                                                    &cld_filter->element, 1);
6929                 if (ret < 0) {
6930                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6931                         return -ENOTSUP;
6932                 }
6933                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6934         }
6935
6936         rte_free(cld_filter);
6937         return ret;
6938 }
6939
6940 int
6941 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
6942                       struct i40e_tunnel_filter_conf *tunnel_filter,
6943                       uint8_t add)
6944 {
6945         uint16_t ip_type;
6946         uint32_t ipv4_addr;
6947         uint8_t i, tun_type = 0;
6948         /* internal variable to convert ipv6 byte order */
6949         uint32_t convert_ipv6[4];
6950         int val, ret = 0;
6951         struct i40e_pf_vf *vf = NULL;
6952         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6953         struct i40e_vsi *vsi;
6954         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6955         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6956         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6957         struct i40e_tunnel_filter *tunnel, *node;
6958         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6959
6960         cld_filter = rte_zmalloc("tunnel_filter",
6961                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6962                          0);
6963
6964         if (cld_filter == NULL) {
6965                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6966                 return -ENOMEM;
6967         }
6968         pfilter = cld_filter;
6969
6970         ether_addr_copy(&tunnel_filter->outer_mac,
6971                         (struct ether_addr *)&pfilter->element.outer_mac);
6972         ether_addr_copy(&tunnel_filter->inner_mac,
6973                         (struct ether_addr *)&pfilter->element.inner_mac);
6974
6975         pfilter->element.inner_vlan =
6976                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6977         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6978                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6979                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6980                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6981                                 &rte_cpu_to_le_32(ipv4_addr),
6982                                 sizeof(pfilter->element.ipaddr.v4.data));
6983         } else {
6984                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6985                 for (i = 0; i < 4; i++) {
6986                         convert_ipv6[i] =
6987                         rte_cpu_to_le_32(rte_be_to_cpu_32(
6988                                          tunnel_filter->ip_addr.ipv6_addr[i]));
6989                 }
6990                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6991                            &convert_ipv6,
6992                            sizeof(pfilter->element.ipaddr.v6.data));
6993         }
6994
6995         /* check tunneled type */
6996         switch (tunnel_filter->tunnel_type) {
6997         case RTE_TUNNEL_TYPE_VXLAN:
6998                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6999                 break;
7000         case RTE_TUNNEL_TYPE_NVGRE:
7001                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7002                 break;
7003         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7004                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7005                 break;
7006         default:
7007                 /* Other tunnel types is not supported. */
7008                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7009                 rte_free(cld_filter);
7010                 return -EINVAL;
7011         }
7012
7013         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7014                                        &pfilter->element.flags);
7015         if (val < 0) {
7016                 rte_free(cld_filter);
7017                 return -EINVAL;
7018         }
7019
7020         pfilter->element.flags |= rte_cpu_to_le_16(
7021                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7022                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7023         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7024         pfilter->element.queue_number =
7025                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7026
7027         if (!tunnel_filter->is_to_vf)
7028                 vsi = pf->main_vsi;
7029         else {
7030                 if (tunnel_filter->vf_id >= pf->vf_num) {
7031                         PMD_DRV_LOG(ERR, "Invalid argument.");
7032                         return -EINVAL;
7033                 }
7034                 vf = &pf->vfs[tunnel_filter->vf_id];
7035                 vsi = vf->vsi;
7036         }
7037
7038         /* Check if there is the filter in SW list */
7039         memset(&check_filter, 0, sizeof(check_filter));
7040         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7041         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7042         if (add && node) {
7043                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7044                 return -EINVAL;
7045         }
7046
7047         if (!add && !node) {
7048                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7049                 return -EINVAL;
7050         }
7051
7052         if (add) {
7053                 ret = i40e_aq_add_cloud_filters(hw,
7054                                         vsi->seid, &cld_filter->element, 1);
7055                 if (ret < 0) {
7056                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7057                         return -ENOTSUP;
7058                 }
7059                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7060                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7061                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7062         } else {
7063                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7064                                                    &cld_filter->element, 1);
7065                 if (ret < 0) {
7066                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7067                         return -ENOTSUP;
7068                 }
7069                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7070         }
7071
7072         rte_free(cld_filter);
7073         return ret;
7074 }
7075
7076 static int
7077 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7078 {
7079         uint8_t i;
7080
7081         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7082                 if (pf->vxlan_ports[i] == port)
7083                         return i;
7084         }
7085
7086         return -1;
7087 }
7088
7089 static int
7090 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7091 {
7092         int  idx, ret;
7093         uint8_t filter_idx;
7094         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7095
7096         idx = i40e_get_vxlan_port_idx(pf, port);
7097
7098         /* Check if port already exists */
7099         if (idx >= 0) {
7100                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7101                 return -EINVAL;
7102         }
7103
7104         /* Now check if there is space to add the new port */
7105         idx = i40e_get_vxlan_port_idx(pf, 0);
7106         if (idx < 0) {
7107                 PMD_DRV_LOG(ERR,
7108                         "Maximum number of UDP ports reached, not adding port %d",
7109                         port);
7110                 return -ENOSPC;
7111         }
7112
7113         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7114                                         &filter_idx, NULL);
7115         if (ret < 0) {
7116                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7117                 return -1;
7118         }
7119
7120         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7121                          port,  filter_idx);
7122
7123         /* New port: add it and mark its index in the bitmap */
7124         pf->vxlan_ports[idx] = port;
7125         pf->vxlan_bitmap |= (1 << idx);
7126
7127         if (!(pf->flags & I40E_FLAG_VXLAN))
7128                 pf->flags |= I40E_FLAG_VXLAN;
7129
7130         return 0;
7131 }
7132
7133 static int
7134 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7135 {
7136         int idx;
7137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7138
7139         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7140                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7141                 return -EINVAL;
7142         }
7143
7144         idx = i40e_get_vxlan_port_idx(pf, port);
7145
7146         if (idx < 0) {
7147                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7148                 return -EINVAL;
7149         }
7150
7151         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7152                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7153                 return -1;
7154         }
7155
7156         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7157                         port, idx);
7158
7159         pf->vxlan_ports[idx] = 0;
7160         pf->vxlan_bitmap &= ~(1 << idx);
7161
7162         if (!pf->vxlan_bitmap)
7163                 pf->flags &= ~I40E_FLAG_VXLAN;
7164
7165         return 0;
7166 }
7167
7168 /* Add UDP tunneling port */
7169 static int
7170 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7171                              struct rte_eth_udp_tunnel *udp_tunnel)
7172 {
7173         int ret = 0;
7174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7175
7176         if (udp_tunnel == NULL)
7177                 return -EINVAL;
7178
7179         switch (udp_tunnel->prot_type) {
7180         case RTE_TUNNEL_TYPE_VXLAN:
7181                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7182                 break;
7183
7184         case RTE_TUNNEL_TYPE_GENEVE:
7185         case RTE_TUNNEL_TYPE_TEREDO:
7186                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7187                 ret = -1;
7188                 break;
7189
7190         default:
7191                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7192                 ret = -1;
7193                 break;
7194         }
7195
7196         return ret;
7197 }
7198
7199 /* Remove UDP tunneling port */
7200 static int
7201 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7202                              struct rte_eth_udp_tunnel *udp_tunnel)
7203 {
7204         int ret = 0;
7205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7206
7207         if (udp_tunnel == NULL)
7208                 return -EINVAL;
7209
7210         switch (udp_tunnel->prot_type) {
7211         case RTE_TUNNEL_TYPE_VXLAN:
7212                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7213                 break;
7214         case RTE_TUNNEL_TYPE_GENEVE:
7215         case RTE_TUNNEL_TYPE_TEREDO:
7216                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7217                 ret = -1;
7218                 break;
7219         default:
7220                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7221                 ret = -1;
7222                 break;
7223         }
7224
7225         return ret;
7226 }
7227
7228 /* Calculate the maximum number of contiguous PF queues that are configured */
7229 static int
7230 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7231 {
7232         struct rte_eth_dev_data *data = pf->dev_data;
7233         int i, num;
7234         struct i40e_rx_queue *rxq;
7235
7236         num = 0;
7237         for (i = 0; i < pf->lan_nb_qps; i++) {
7238                 rxq = data->rx_queues[i];
7239                 if (rxq && rxq->q_set)
7240                         num++;
7241                 else
7242                         break;
7243         }
7244
7245         return num;
7246 }
7247
7248 /* Configure RSS */
7249 static int
7250 i40e_pf_config_rss(struct i40e_pf *pf)
7251 {
7252         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7253         struct rte_eth_rss_conf rss_conf;
7254         uint32_t i, lut = 0;
7255         uint16_t j, num;
7256
7257         /*
7258          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7259          * It's necessary to calulate the actual PF queues that are configured.
7260          */
7261         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7262                 num = i40e_pf_calc_configured_queues_num(pf);
7263         else
7264                 num = pf->dev_data->nb_rx_queues;
7265
7266         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7267         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7268                         num);
7269
7270         if (num == 0) {
7271                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7272                 return -ENOTSUP;
7273         }
7274
7275         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7276                 if (j == num)
7277                         j = 0;
7278                 lut = (lut << 8) | (j & ((0x1 <<
7279                         hw->func_caps.rss_table_entry_width) - 1));
7280                 if ((i & 3) == 3)
7281                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7282         }
7283
7284         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7285         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7286                 i40e_pf_disable_rss(pf);
7287                 return 0;
7288         }
7289         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7290                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7291                 /* Random default keys */
7292                 static uint32_t rss_key_default[] = {0x6b793944,
7293                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7294                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7295                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7296
7297                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7298                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7299                                                         sizeof(uint32_t);
7300         }
7301
7302         return i40e_hw_rss_hash_set(pf, &rss_conf);
7303 }
7304
7305 static int
7306 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7307                                struct rte_eth_tunnel_filter_conf *filter)
7308 {
7309         if (pf == NULL || filter == NULL) {
7310                 PMD_DRV_LOG(ERR, "Invalid parameter");
7311                 return -EINVAL;
7312         }
7313
7314         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7315                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7316                 return -EINVAL;
7317         }
7318
7319         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7320                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7321                 return -EINVAL;
7322         }
7323
7324         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7325                 (is_zero_ether_addr(&filter->outer_mac))) {
7326                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7327                 return -EINVAL;
7328         }
7329
7330         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7331                 (is_zero_ether_addr(&filter->inner_mac))) {
7332                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7333                 return -EINVAL;
7334         }
7335
7336         return 0;
7337 }
7338
7339 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7340 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7341 static int
7342 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7343 {
7344         uint32_t val, reg;
7345         int ret = -EINVAL;
7346
7347         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7348         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7349
7350         if (len == 3) {
7351                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7352         } else if (len == 4) {
7353                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7354         } else {
7355                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7356                 return ret;
7357         }
7358
7359         if (reg != val) {
7360                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7361                                                    reg, NULL);
7362                 if (ret != 0)
7363                         return ret;
7364         } else {
7365                 ret = 0;
7366         }
7367         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7368                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7369
7370         return ret;
7371 }
7372
7373 static int
7374 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7375 {
7376         int ret = -EINVAL;
7377
7378         if (!hw || !cfg)
7379                 return -EINVAL;
7380
7381         switch (cfg->cfg_type) {
7382         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7383                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7384                 break;
7385         default:
7386                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7387                 break;
7388         }
7389
7390         return ret;
7391 }
7392
7393 static int
7394 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7395                                enum rte_filter_op filter_op,
7396                                void *arg)
7397 {
7398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7399         int ret = I40E_ERR_PARAM;
7400
7401         switch (filter_op) {
7402         case RTE_ETH_FILTER_SET:
7403                 ret = i40e_dev_global_config_set(hw,
7404                         (struct rte_eth_global_cfg *)arg);
7405                 break;
7406         default:
7407                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7408                 break;
7409         }
7410
7411         return ret;
7412 }
7413
7414 static int
7415 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7416                           enum rte_filter_op filter_op,
7417                           void *arg)
7418 {
7419         struct rte_eth_tunnel_filter_conf *filter;
7420         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7421         int ret = I40E_SUCCESS;
7422
7423         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7424
7425         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7426                 return I40E_ERR_PARAM;
7427
7428         switch (filter_op) {
7429         case RTE_ETH_FILTER_NOP:
7430                 if (!(pf->flags & I40E_FLAG_VXLAN))
7431                         ret = I40E_NOT_SUPPORTED;
7432                 break;
7433         case RTE_ETH_FILTER_ADD:
7434                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7435                 break;
7436         case RTE_ETH_FILTER_DELETE:
7437                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7438                 break;
7439         default:
7440                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7441                 ret = I40E_ERR_PARAM;
7442                 break;
7443         }
7444
7445         return ret;
7446 }
7447
7448 static int
7449 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7450 {
7451         int ret = 0;
7452         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7453
7454         /* RSS setup */
7455         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7456                 ret = i40e_pf_config_rss(pf);
7457         else
7458                 i40e_pf_disable_rss(pf);
7459
7460         return ret;
7461 }
7462
7463 /* Get the symmetric hash enable configurations per port */
7464 static void
7465 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7466 {
7467         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7468
7469         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7470 }
7471
7472 /* Set the symmetric hash enable configurations per port */
7473 static void
7474 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7475 {
7476         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7477
7478         if (enable > 0) {
7479                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7480                         PMD_DRV_LOG(INFO,
7481                                 "Symmetric hash has already been enabled");
7482                         return;
7483                 }
7484                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7485         } else {
7486                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7487                         PMD_DRV_LOG(INFO,
7488                                 "Symmetric hash has already been disabled");
7489                         return;
7490                 }
7491                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7492         }
7493         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7494         I40E_WRITE_FLUSH(hw);
7495 }
7496
7497 /*
7498  * Get global configurations of hash function type and symmetric hash enable
7499  * per flow type (pctype). Note that global configuration means it affects all
7500  * the ports on the same NIC.
7501  */
7502 static int
7503 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7504                                    struct rte_eth_hash_global_conf *g_cfg)
7505 {
7506         uint32_t reg, mask = I40E_FLOW_TYPES;
7507         uint16_t i;
7508         enum i40e_filter_pctype pctype;
7509
7510         memset(g_cfg, 0, sizeof(*g_cfg));
7511         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7512         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7513                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7514         else
7515                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7516         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7517                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7518
7519         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7520                 if (!(mask & (1UL << i)))
7521                         continue;
7522                 mask &= ~(1UL << i);
7523                 /* Bit set indicats the coresponding flow type is supported */
7524                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7525                 /* if flowtype is invalid, continue */
7526                 if (!I40E_VALID_FLOW(i))
7527                         continue;
7528                 pctype = i40e_flowtype_to_pctype(i);
7529                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7530                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7531                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7532         }
7533
7534         return 0;
7535 }
7536
7537 static int
7538 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7539 {
7540         uint32_t i;
7541         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7542
7543         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7544                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7545                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7546                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7547                                                 g_cfg->hash_func);
7548                 return -EINVAL;
7549         }
7550
7551         /*
7552          * As i40e supports less than 32 flow types, only first 32 bits need to
7553          * be checked.
7554          */
7555         mask0 = g_cfg->valid_bit_mask[0];
7556         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7557                 if (i == 0) {
7558                         /* Check if any unsupported flow type configured */
7559                         if ((mask0 | i40e_mask) ^ i40e_mask)
7560                                 goto mask_err;
7561                 } else {
7562                         if (g_cfg->valid_bit_mask[i])
7563                                 goto mask_err;
7564                 }
7565         }
7566
7567         return 0;
7568
7569 mask_err:
7570         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7571
7572         return -EINVAL;
7573 }
7574
7575 /*
7576  * Set global configurations of hash function type and symmetric hash enable
7577  * per flow type (pctype). Note any modifying global configuration will affect
7578  * all the ports on the same NIC.
7579  */
7580 static int
7581 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7582                                    struct rte_eth_hash_global_conf *g_cfg)
7583 {
7584         int ret;
7585         uint16_t i;
7586         uint32_t reg;
7587         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7588         enum i40e_filter_pctype pctype;
7589
7590         /* Check the input parameters */
7591         ret = i40e_hash_global_config_check(g_cfg);
7592         if (ret < 0)
7593                 return ret;
7594
7595         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7596                 if (!(mask0 & (1UL << i)))
7597                         continue;
7598                 mask0 &= ~(1UL << i);
7599                 /* if flowtype is invalid, continue */
7600                 if (!I40E_VALID_FLOW(i))
7601                         continue;
7602                 pctype = i40e_flowtype_to_pctype(i);
7603                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7604                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7605                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7606         }
7607
7608         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7609         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7610                 /* Toeplitz */
7611                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7612                         PMD_DRV_LOG(DEBUG,
7613                                 "Hash function already set to Toeplitz");
7614                         goto out;
7615                 }
7616                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7617         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7618                 /* Simple XOR */
7619                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7620                         PMD_DRV_LOG(DEBUG,
7621                                 "Hash function already set to Simple XOR");
7622                         goto out;
7623                 }
7624                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7625         } else
7626                 /* Use the default, and keep it as it is */
7627                 goto out;
7628
7629         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7630
7631 out:
7632         I40E_WRITE_FLUSH(hw);
7633
7634         return 0;
7635 }
7636
7637 /**
7638  * Valid input sets for hash and flow director filters per PCTYPE
7639  */
7640 static uint64_t
7641 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7642                 enum rte_filter_type filter)
7643 {
7644         uint64_t valid;
7645
7646         static const uint64_t valid_hash_inset_table[] = {
7647                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7648                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7649                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7650                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7651                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7652                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7653                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7654                         I40E_INSET_FLEX_PAYLOAD,
7655                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7656                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7657                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7658                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7659                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7660                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7661                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7662                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7663                         I40E_INSET_FLEX_PAYLOAD,
7664                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7665                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7666                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7667                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7668                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7669                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7670                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7671                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7672                         I40E_INSET_FLEX_PAYLOAD,
7673                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7674                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7675                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7677                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7678                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7679                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7680                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7681                         I40E_INSET_FLEX_PAYLOAD,
7682                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7683                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7684                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7685                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7686                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7687                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7688                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7689                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7690                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7691                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7692                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7693                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7694                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7695                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7696                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7697                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7698                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7699                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7700                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7701                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7702                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7703                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7704                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7705                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7706                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7707                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7708                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7709                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7710                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7711                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7712                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7713                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7714                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7715                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7716                         I40E_INSET_FLEX_PAYLOAD,
7717                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7718                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7719                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7720                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7721                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7722                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7723                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7724                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7725                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7726                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7727                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7728                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7729                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7730                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7731                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7732                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7733                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7734                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7735                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7736                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7737                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7738                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7739                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7740                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7741                         I40E_INSET_FLEX_PAYLOAD,
7742                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7743                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7744                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7745                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7746                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7747                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7748                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7749                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7750                         I40E_INSET_FLEX_PAYLOAD,
7751                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7752                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7753                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7754                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7755                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7756                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7757                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7758                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7759                         I40E_INSET_FLEX_PAYLOAD,
7760                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7761                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7762                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7763                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7764                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7765                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7766                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7767                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7768                         I40E_INSET_FLEX_PAYLOAD,
7769                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7770                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7771                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7772                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7773                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7774                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7775                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7776                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7777                         I40E_INSET_FLEX_PAYLOAD,
7778                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7779                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7780                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7781                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7782                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7783                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7784                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7785                         I40E_INSET_FLEX_PAYLOAD,
7786                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7787                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7788                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7789                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7790                         I40E_INSET_FLEX_PAYLOAD,
7791         };
7792
7793         /**
7794          * Flow director supports only fields defined in
7795          * union rte_eth_fdir_flow.
7796          */
7797         static const uint64_t valid_fdir_inset_table[] = {
7798                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7799                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7800                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7801                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7802                 I40E_INSET_IPV4_TTL,
7803                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7804                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7805                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7806                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7807                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7808                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7809                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7810                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7811                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7812                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7813                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7814                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7815                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7816                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7817                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7818                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7819                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7820                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7821                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7822                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7823                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7824                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7825                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7826                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7827                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7828                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7829                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7830                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7831                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7832                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7833                 I40E_INSET_SCTP_VT,
7834                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7835                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7836                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7837                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7838                 I40E_INSET_IPV4_TTL,
7839                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7840                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7841                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7842                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7843                 I40E_INSET_IPV6_HOP_LIMIT,
7844                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7845                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7846                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7847                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7848                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7849                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7850                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7851                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7852                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7853                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7854                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7855                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7856                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7857                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7858                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7859                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7860                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7861                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7862                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7863                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7864                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7865                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7866                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7867                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7868                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7869                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7870                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7871                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7872                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7873                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7874                 I40E_INSET_SCTP_VT,
7875                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7876                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7877                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7878                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7879                 I40E_INSET_IPV6_HOP_LIMIT,
7880                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7881                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7882                 I40E_INSET_LAST_ETHER_TYPE,
7883         };
7884
7885         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7886                 return 0;
7887         if (filter == RTE_ETH_FILTER_HASH)
7888                 valid = valid_hash_inset_table[pctype];
7889         else
7890                 valid = valid_fdir_inset_table[pctype];
7891
7892         return valid;
7893 }
7894
7895 /**
7896  * Validate if the input set is allowed for a specific PCTYPE
7897  */
7898 static int
7899 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7900                 enum rte_filter_type filter, uint64_t inset)
7901 {
7902         uint64_t valid;
7903
7904         valid = i40e_get_valid_input_set(pctype, filter);
7905         if (inset & (~valid))
7906                 return -EINVAL;
7907
7908         return 0;
7909 }
7910
7911 /* default input set fields combination per pctype */
7912 uint64_t
7913 i40e_get_default_input_set(uint16_t pctype)
7914 {
7915         static const uint64_t default_inset_table[] = {
7916                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7917                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7918                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7919                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7920                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7921                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7922                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7923                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7924                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7925                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7926                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7927                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7928                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7929                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7930                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7931                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7932                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7933                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7934                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7935                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7936                         I40E_INSET_SCTP_VT,
7937                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7938                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7939                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7940                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7941                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7942                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7943                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7944                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7945                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7946                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7947                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7948                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7949                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7950                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7951                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7952                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7953                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7954                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7955                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7956                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7957                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7958                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7959                         I40E_INSET_SCTP_VT,
7960                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7961                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7962                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7963                         I40E_INSET_LAST_ETHER_TYPE,
7964         };
7965
7966         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7967                 return 0;
7968
7969         return default_inset_table[pctype];
7970 }
7971
7972 /**
7973  * Parse the input set from index to logical bit masks
7974  */
7975 static int
7976 i40e_parse_input_set(uint64_t *inset,
7977                      enum i40e_filter_pctype pctype,
7978                      enum rte_eth_input_set_field *field,
7979                      uint16_t size)
7980 {
7981         uint16_t i, j;
7982         int ret = -EINVAL;
7983
7984         static const struct {
7985                 enum rte_eth_input_set_field field;
7986                 uint64_t inset;
7987         } inset_convert_table[] = {
7988                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7989                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7990                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7991                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7992                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7993                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7994                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7995                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7996                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7997                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7998                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7999                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8000                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8001                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8002                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8003                         I40E_INSET_IPV6_NEXT_HDR},
8004                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8005                         I40E_INSET_IPV6_HOP_LIMIT},
8006                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8007                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8008                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8009                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8010                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8011                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8012                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8013                         I40E_INSET_SCTP_VT},
8014                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8015                         I40E_INSET_TUNNEL_DMAC},
8016                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8017                         I40E_INSET_VLAN_TUNNEL},
8018                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8019                         I40E_INSET_TUNNEL_ID},
8020                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8021                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8022                         I40E_INSET_FLEX_PAYLOAD_W1},
8023                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8024                         I40E_INSET_FLEX_PAYLOAD_W2},
8025                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8026                         I40E_INSET_FLEX_PAYLOAD_W3},
8027                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8028                         I40E_INSET_FLEX_PAYLOAD_W4},
8029                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8030                         I40E_INSET_FLEX_PAYLOAD_W5},
8031                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8032                         I40E_INSET_FLEX_PAYLOAD_W6},
8033                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8034                         I40E_INSET_FLEX_PAYLOAD_W7},
8035                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8036                         I40E_INSET_FLEX_PAYLOAD_W8},
8037         };
8038
8039         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8040                 return ret;
8041
8042         /* Only one item allowed for default or all */
8043         if (size == 1) {
8044                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8045                         *inset = i40e_get_default_input_set(pctype);
8046                         return 0;
8047                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8048                         *inset = I40E_INSET_NONE;
8049                         return 0;
8050                 }
8051         }
8052
8053         for (i = 0, *inset = 0; i < size; i++) {
8054                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8055                         if (field[i] == inset_convert_table[j].field) {
8056                                 *inset |= inset_convert_table[j].inset;
8057                                 break;
8058                         }
8059                 }
8060
8061                 /* It contains unsupported input set, return immediately */
8062                 if (j == RTE_DIM(inset_convert_table))
8063                         return ret;
8064         }
8065
8066         return 0;
8067 }
8068
8069 /**
8070  * Translate the input set from bit masks to register aware bit masks
8071  * and vice versa
8072  */
8073 static uint64_t
8074 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8075 {
8076         uint64_t val = 0;
8077         uint16_t i;
8078
8079         struct inset_map {
8080                 uint64_t inset;
8081                 uint64_t inset_reg;
8082         };
8083
8084         static const struct inset_map inset_map_common[] = {
8085                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8086                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8087                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8088                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8089                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8090                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8091                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8092                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8093                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8094                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8095                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8096                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8097                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8098                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8099                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8100                 {I40E_INSET_TUNNEL_DMAC,
8101                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8102                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8103                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8104                 {I40E_INSET_TUNNEL_SRC_PORT,
8105                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8106                 {I40E_INSET_TUNNEL_DST_PORT,
8107                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8108                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8109                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8110                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8111                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8112                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8113                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8114                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8115                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8116                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8117         };
8118
8119     /* some different registers map in x722*/
8120         static const struct inset_map inset_map_diff_x722[] = {
8121                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8122                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8123                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8124                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8125         };
8126
8127         static const struct inset_map inset_map_diff_not_x722[] = {
8128                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8129                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8130                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8131                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8132         };
8133
8134         if (input == 0)
8135                 return val;
8136
8137         /* Translate input set to register aware inset */
8138         if (type == I40E_MAC_X722) {
8139                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8140                         if (input & inset_map_diff_x722[i].inset)
8141                                 val |= inset_map_diff_x722[i].inset_reg;
8142                 }
8143         } else {
8144                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8145                         if (input & inset_map_diff_not_x722[i].inset)
8146                                 val |= inset_map_diff_not_x722[i].inset_reg;
8147                 }
8148         }
8149
8150         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8151                 if (input & inset_map_common[i].inset)
8152                         val |= inset_map_common[i].inset_reg;
8153         }
8154
8155         return val;
8156 }
8157
8158 static int
8159 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8160 {
8161         uint8_t i, idx = 0;
8162         uint64_t inset_need_mask = inset;
8163
8164         static const struct {
8165                 uint64_t inset;
8166                 uint32_t mask;
8167         } inset_mask_map[] = {
8168                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8169                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8170                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8171                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8172                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8173                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8174                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8175                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8176         };
8177
8178         if (!inset || !mask || !nb_elem)
8179                 return 0;
8180
8181         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8182                 /* Clear the inset bit, if no MASK is required,
8183                  * for example proto + ttl
8184                  */
8185                 if ((inset & inset_mask_map[i].inset) ==
8186                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8187                         inset_need_mask &= ~inset_mask_map[i].inset;
8188                 if (!inset_need_mask)
8189                         return 0;
8190         }
8191         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8192                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8193                     inset_mask_map[i].inset) {
8194                         if (idx >= nb_elem) {
8195                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8196                                 return -EINVAL;
8197                         }
8198                         mask[idx] = inset_mask_map[i].mask;
8199                         idx++;
8200                 }
8201         }
8202
8203         return idx;
8204 }
8205
8206 static void
8207 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8208 {
8209         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8210
8211         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8212         if (reg != val)
8213                 i40e_write_rx_ctl(hw, addr, val);
8214         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8215                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8216 }
8217
8218 static void
8219 i40e_filter_input_set_init(struct i40e_pf *pf)
8220 {
8221         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8222         enum i40e_filter_pctype pctype;
8223         uint64_t input_set, inset_reg;
8224         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8225         int num, i;
8226
8227         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8228              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8229                 if (hw->mac.type == I40E_MAC_X722) {
8230                         if (!I40E_VALID_PCTYPE_X722(pctype))
8231                                 continue;
8232                 } else {
8233                         if (!I40E_VALID_PCTYPE(pctype))
8234                                 continue;
8235                 }
8236
8237                 input_set = i40e_get_default_input_set(pctype);
8238
8239                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8240                                                    I40E_INSET_MASK_NUM_REG);
8241                 if (num < 0)
8242                         return;
8243                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8244                                         input_set);
8245
8246                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8247                                       (uint32_t)(inset_reg & UINT32_MAX));
8248                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8249                                      (uint32_t)((inset_reg >>
8250                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8251                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8252                                       (uint32_t)(inset_reg & UINT32_MAX));
8253                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8254                                      (uint32_t)((inset_reg >>
8255                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8256
8257                 for (i = 0; i < num; i++) {
8258                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8259                                              mask_reg[i]);
8260                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8261                                              mask_reg[i]);
8262                 }
8263                 /*clear unused mask registers of the pctype */
8264                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8265                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8266                                              0);
8267                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8268                                              0);
8269                 }
8270                 I40E_WRITE_FLUSH(hw);
8271
8272                 /* store the default input set */
8273                 pf->hash_input_set[pctype] = input_set;
8274                 pf->fdir.input_set[pctype] = input_set;
8275         }
8276 }
8277
8278 int
8279 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8280                          struct rte_eth_input_set_conf *conf)
8281 {
8282         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8283         enum i40e_filter_pctype pctype;
8284         uint64_t input_set, inset_reg = 0;
8285         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8286         int ret, i, num;
8287
8288         if (!conf) {
8289                 PMD_DRV_LOG(ERR, "Invalid pointer");
8290                 return -EFAULT;
8291         }
8292         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8293             conf->op != RTE_ETH_INPUT_SET_ADD) {
8294                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8295                 return -EINVAL;
8296         }
8297
8298         if (!I40E_VALID_FLOW(conf->flow_type)) {
8299                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8300                 return -EINVAL;
8301         }
8302
8303         if (hw->mac.type == I40E_MAC_X722) {
8304                 /* get translated pctype value in fd pctype register */
8305                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8306                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8307                         conf->flow_type)));
8308         } else
8309                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8310
8311         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8312                                    conf->inset_size);
8313         if (ret) {
8314                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8315                 return -EINVAL;
8316         }
8317         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8318                                     input_set) != 0) {
8319                 PMD_DRV_LOG(ERR, "Invalid input set");
8320                 return -EINVAL;
8321         }
8322         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8323                 /* get inset value in register */
8324                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8325                 inset_reg <<= I40E_32_BIT_WIDTH;
8326                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8327                 input_set |= pf->hash_input_set[pctype];
8328         }
8329         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8330                                            I40E_INSET_MASK_NUM_REG);
8331         if (num < 0)
8332                 return -EINVAL;
8333
8334         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8335
8336         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8337                               (uint32_t)(inset_reg & UINT32_MAX));
8338         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8339                              (uint32_t)((inset_reg >>
8340                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8341
8342         for (i = 0; i < num; i++)
8343                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8344                                      mask_reg[i]);
8345         /*clear unused mask registers of the pctype */
8346         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8347                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8348                                      0);
8349         I40E_WRITE_FLUSH(hw);
8350
8351         pf->hash_input_set[pctype] = input_set;
8352         return 0;
8353 }
8354
8355 int
8356 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8357                          struct rte_eth_input_set_conf *conf)
8358 {
8359         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8360         enum i40e_filter_pctype pctype;
8361         uint64_t input_set, inset_reg = 0;
8362         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8363         int ret, i, num;
8364
8365         if (!hw || !conf) {
8366                 PMD_DRV_LOG(ERR, "Invalid pointer");
8367                 return -EFAULT;
8368         }
8369         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8370             conf->op != RTE_ETH_INPUT_SET_ADD) {
8371                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8372                 return -EINVAL;
8373         }
8374
8375         if (!I40E_VALID_FLOW(conf->flow_type)) {
8376                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8377                 return -EINVAL;
8378         }
8379
8380         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8381
8382         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8383                                    conf->inset_size);
8384         if (ret) {
8385                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8386                 return -EINVAL;
8387         }
8388         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8389                                     input_set) != 0) {
8390                 PMD_DRV_LOG(ERR, "Invalid input set");
8391                 return -EINVAL;
8392         }
8393
8394         /* get inset value in register */
8395         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8396         inset_reg <<= I40E_32_BIT_WIDTH;
8397         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8398
8399         /* Can not change the inset reg for flex payload for fdir,
8400          * it is done by writing I40E_PRTQF_FD_FLXINSET
8401          * in i40e_set_flex_mask_on_pctype.
8402          */
8403         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8404                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8405         else
8406                 input_set |= pf->fdir.input_set[pctype];
8407         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8408                                            I40E_INSET_MASK_NUM_REG);
8409         if (num < 0)
8410                 return -EINVAL;
8411
8412         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8413
8414         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8415                               (uint32_t)(inset_reg & UINT32_MAX));
8416         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8417                              (uint32_t)((inset_reg >>
8418                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8419
8420         for (i = 0; i < num; i++)
8421                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8422                                      mask_reg[i]);
8423         /*clear unused mask registers of the pctype */
8424         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8425                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8426                                      0);
8427         I40E_WRITE_FLUSH(hw);
8428
8429         pf->fdir.input_set[pctype] = input_set;
8430         return 0;
8431 }
8432
8433 static int
8434 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8435 {
8436         int ret = 0;
8437
8438         if (!hw || !info) {
8439                 PMD_DRV_LOG(ERR, "Invalid pointer");
8440                 return -EFAULT;
8441         }
8442
8443         switch (info->info_type) {
8444         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8445                 i40e_get_symmetric_hash_enable_per_port(hw,
8446                                         &(info->info.enable));
8447                 break;
8448         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8449                 ret = i40e_get_hash_filter_global_config(hw,
8450                                 &(info->info.global_conf));
8451                 break;
8452         default:
8453                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8454                                                         info->info_type);
8455                 ret = -EINVAL;
8456                 break;
8457         }
8458
8459         return ret;
8460 }
8461
8462 static int
8463 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8464 {
8465         int ret = 0;
8466
8467         if (!hw || !info) {
8468                 PMD_DRV_LOG(ERR, "Invalid pointer");
8469                 return -EFAULT;
8470         }
8471
8472         switch (info->info_type) {
8473         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8474                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8475                 break;
8476         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8477                 ret = i40e_set_hash_filter_global_config(hw,
8478                                 &(info->info.global_conf));
8479                 break;
8480         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8481                 ret = i40e_hash_filter_inset_select(hw,
8482                                                &(info->info.input_set_conf));
8483                 break;
8484
8485         default:
8486                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8487                                                         info->info_type);
8488                 ret = -EINVAL;
8489                 break;
8490         }
8491
8492         return ret;
8493 }
8494
8495 /* Operations for hash function */
8496 static int
8497 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8498                       enum rte_filter_op filter_op,
8499                       void *arg)
8500 {
8501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8502         int ret = 0;
8503
8504         switch (filter_op) {
8505         case RTE_ETH_FILTER_NOP:
8506                 break;
8507         case RTE_ETH_FILTER_GET:
8508                 ret = i40e_hash_filter_get(hw,
8509                         (struct rte_eth_hash_filter_info *)arg);
8510                 break;
8511         case RTE_ETH_FILTER_SET:
8512                 ret = i40e_hash_filter_set(hw,
8513                         (struct rte_eth_hash_filter_info *)arg);
8514                 break;
8515         default:
8516                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8517                                                                 filter_op);
8518                 ret = -ENOTSUP;
8519                 break;
8520         }
8521
8522         return ret;
8523 }
8524
8525 /* Convert ethertype filter structure */
8526 static int
8527 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8528                               struct i40e_ethertype_filter *filter)
8529 {
8530         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8531         filter->input.ether_type = input->ether_type;
8532         filter->flags = input->flags;
8533         filter->queue = input->queue;
8534
8535         return 0;
8536 }
8537
8538 /* Check if there exists the ehtertype filter */
8539 struct i40e_ethertype_filter *
8540 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8541                                 const struct i40e_ethertype_filter_input *input)
8542 {
8543         int ret;
8544
8545         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8546         if (ret < 0)
8547                 return NULL;
8548
8549         return ethertype_rule->hash_map[ret];
8550 }
8551
8552 /* Add ethertype filter in SW list */
8553 static int
8554 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8555                                 struct i40e_ethertype_filter *filter)
8556 {
8557         struct i40e_ethertype_rule *rule = &pf->ethertype;
8558         int ret;
8559
8560         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8561         if (ret < 0) {
8562                 PMD_DRV_LOG(ERR,
8563                             "Failed to insert ethertype filter"
8564                             " to hash table %d!",
8565                             ret);
8566                 return ret;
8567         }
8568         rule->hash_map[ret] = filter;
8569
8570         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8571
8572         return 0;
8573 }
8574
8575 /* Delete ethertype filter in SW list */
8576 int
8577 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8578                              struct i40e_ethertype_filter_input *input)
8579 {
8580         struct i40e_ethertype_rule *rule = &pf->ethertype;
8581         struct i40e_ethertype_filter *filter;
8582         int ret;
8583
8584         ret = rte_hash_del_key(rule->hash_table, input);
8585         if (ret < 0) {
8586                 PMD_DRV_LOG(ERR,
8587                             "Failed to delete ethertype filter"
8588                             " to hash table %d!",
8589                             ret);
8590                 return ret;
8591         }
8592         filter = rule->hash_map[ret];
8593         rule->hash_map[ret] = NULL;
8594
8595         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8596         rte_free(filter);
8597
8598         return 0;
8599 }
8600
8601 /*
8602  * Configure ethertype filter, which can director packet by filtering
8603  * with mac address and ether_type or only ether_type
8604  */
8605 int
8606 i40e_ethertype_filter_set(struct i40e_pf *pf,
8607                         struct rte_eth_ethertype_filter *filter,
8608                         bool add)
8609 {
8610         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8611         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8612         struct i40e_ethertype_filter *ethertype_filter, *node;
8613         struct i40e_ethertype_filter check_filter;
8614         struct i40e_control_filter_stats stats;
8615         uint16_t flags = 0;
8616         int ret;
8617
8618         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8619                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8620                 return -EINVAL;
8621         }
8622         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8623                 filter->ether_type == ETHER_TYPE_IPv6) {
8624                 PMD_DRV_LOG(ERR,
8625                         "unsupported ether_type(0x%04x) in control packet filter.",
8626                         filter->ether_type);
8627                 return -EINVAL;
8628         }
8629         if (filter->ether_type == ETHER_TYPE_VLAN)
8630                 PMD_DRV_LOG(WARNING,
8631                         "filter vlan ether_type in first tag is not supported.");
8632
8633         /* Check if there is the filter in SW list */
8634         memset(&check_filter, 0, sizeof(check_filter));
8635         i40e_ethertype_filter_convert(filter, &check_filter);
8636         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8637                                                &check_filter.input);
8638         if (add && node) {
8639                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8640                 return -EINVAL;
8641         }
8642
8643         if (!add && !node) {
8644                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8645                 return -EINVAL;
8646         }
8647
8648         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8649                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8650         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8651                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8652         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8653
8654         memset(&stats, 0, sizeof(stats));
8655         ret = i40e_aq_add_rem_control_packet_filter(hw,
8656                         filter->mac_addr.addr_bytes,
8657                         filter->ether_type, flags,
8658                         pf->main_vsi->seid,
8659                         filter->queue, add, &stats, NULL);
8660
8661         PMD_DRV_LOG(INFO,
8662                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8663                 ret, stats.mac_etype_used, stats.etype_used,
8664                 stats.mac_etype_free, stats.etype_free);
8665         if (ret < 0)
8666                 return -ENOSYS;
8667
8668         /* Add or delete a filter in SW list */
8669         if (add) {
8670                 ethertype_filter = rte_zmalloc("ethertype_filter",
8671                                        sizeof(*ethertype_filter), 0);
8672                 rte_memcpy(ethertype_filter, &check_filter,
8673                            sizeof(check_filter));
8674                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8675         } else {
8676                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8677         }
8678
8679         return ret;
8680 }
8681
8682 /*
8683  * Handle operations for ethertype filter.
8684  */
8685 static int
8686 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8687                                 enum rte_filter_op filter_op,
8688                                 void *arg)
8689 {
8690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8691         int ret = 0;
8692
8693         if (filter_op == RTE_ETH_FILTER_NOP)
8694                 return ret;
8695
8696         if (arg == NULL) {
8697                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8698                             filter_op);
8699                 return -EINVAL;
8700         }
8701
8702         switch (filter_op) {
8703         case RTE_ETH_FILTER_ADD:
8704                 ret = i40e_ethertype_filter_set(pf,
8705                         (struct rte_eth_ethertype_filter *)arg,
8706                         TRUE);
8707                 break;
8708         case RTE_ETH_FILTER_DELETE:
8709                 ret = i40e_ethertype_filter_set(pf,
8710                         (struct rte_eth_ethertype_filter *)arg,
8711                         FALSE);
8712                 break;
8713         default:
8714                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8715                 ret = -ENOSYS;
8716                 break;
8717         }
8718         return ret;
8719 }
8720
8721 static int
8722 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8723                      enum rte_filter_type filter_type,
8724                      enum rte_filter_op filter_op,
8725                      void *arg)
8726 {
8727         int ret = 0;
8728
8729         if (dev == NULL)
8730                 return -EINVAL;
8731
8732         switch (filter_type) {
8733         case RTE_ETH_FILTER_NONE:
8734                 /* For global configuration */
8735                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8736                 break;
8737         case RTE_ETH_FILTER_HASH:
8738                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8739                 break;
8740         case RTE_ETH_FILTER_MACVLAN:
8741                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8742                 break;
8743         case RTE_ETH_FILTER_ETHERTYPE:
8744                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8745                 break;
8746         case RTE_ETH_FILTER_TUNNEL:
8747                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8748                 break;
8749         case RTE_ETH_FILTER_FDIR:
8750                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8751                 break;
8752         case RTE_ETH_FILTER_GENERIC:
8753                 if (filter_op != RTE_ETH_FILTER_GET)
8754                         return -EINVAL;
8755                 *(const void **)arg = &i40e_flow_ops;
8756                 break;
8757         default:
8758                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8759                                                         filter_type);
8760                 ret = -EINVAL;
8761                 break;
8762         }
8763
8764         return ret;
8765 }
8766
8767 /*
8768  * Check and enable Extended Tag.
8769  * Enabling Extended Tag is important for 40G performance.
8770  */
8771 static void
8772 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8773 {
8774         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8775         uint32_t buf = 0;
8776         int ret;
8777
8778         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8779                                       PCI_DEV_CAP_REG);
8780         if (ret < 0) {
8781                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8782                             PCI_DEV_CAP_REG);
8783                 return;
8784         }
8785         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8786                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8787                 return;
8788         }
8789
8790         buf = 0;
8791         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8792                                       PCI_DEV_CTRL_REG);
8793         if (ret < 0) {
8794                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8795                             PCI_DEV_CTRL_REG);
8796                 return;
8797         }
8798         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8799                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8800                 return;
8801         }
8802         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8803         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8804                                        PCI_DEV_CTRL_REG);
8805         if (ret < 0) {
8806                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8807                             PCI_DEV_CTRL_REG);
8808                 return;
8809         }
8810 }
8811
8812 /*
8813  * As some registers wouldn't be reset unless a global hardware reset,
8814  * hardware initialization is needed to put those registers into an
8815  * expected initial state.
8816  */
8817 static void
8818 i40e_hw_init(struct rte_eth_dev *dev)
8819 {
8820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8821
8822         i40e_enable_extended_tag(dev);
8823
8824         /* clear the PF Queue Filter control register */
8825         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8826
8827         /* Disable symmetric hash per port */
8828         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8829 }
8830
8831 enum i40e_filter_pctype
8832 i40e_flowtype_to_pctype(uint16_t flow_type)
8833 {
8834         static const enum i40e_filter_pctype pctype_table[] = {
8835                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8836                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8837                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8838                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8839                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8840                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8841                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8842                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8843                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8844                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8845                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8846                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8847                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8848                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8849                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8850                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8851                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8852                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8853                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8854         };
8855
8856         return pctype_table[flow_type];
8857 }
8858
8859 uint16_t
8860 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8861 {
8862         static const uint16_t flowtype_table[] = {
8863                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8864                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8865                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8866                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8867                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8868                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8869                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8870                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8871                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8872                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8873                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8874                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8875                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8876                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8877                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8878                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8879                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8880                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8881                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8882                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8883                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8884                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8885                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8886                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8887                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8888                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8889                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8890                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8891                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8892                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8893                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8894         };
8895
8896         return flowtype_table[pctype];
8897 }
8898
8899 /*
8900  * On X710, performance number is far from the expectation on recent firmware
8901  * versions; on XL710, performance number is also far from the expectation on
8902  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8903  * mode is enabled and port MAC address is equal to the packet destination MAC
8904  * address. The fix for this issue may not be integrated in the following
8905  * firmware version. So the workaround in software driver is needed. It needs
8906  * to modify the initial values of 3 internal only registers for both X710 and
8907  * XL710. Note that the values for X710 or XL710 could be different, and the
8908  * workaround can be removed when it is fixed in firmware in the future.
8909  */
8910
8911 /* For both X710 and XL710 */
8912 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8913 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8914
8915 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8916 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8917
8918 /* For X722 */
8919 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8920 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8921
8922 /* For X710 */
8923 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8924 /* For XL710 */
8925 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8926 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8927
8928 static int
8929 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8930 {
8931         enum i40e_status_code status;
8932         struct i40e_aq_get_phy_abilities_resp phy_ab;
8933         int ret = -ENOTSUP;
8934
8935         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8936                                               NULL);
8937
8938         if (status)
8939                 return ret;
8940
8941         return 0;
8942 }
8943
8944 static void
8945 i40e_configure_registers(struct i40e_hw *hw)
8946 {
8947         static struct {
8948                 uint32_t addr;
8949                 uint64_t val;
8950         } reg_table[] = {
8951                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8952                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8953                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8954         };
8955         uint64_t reg;
8956         uint32_t i;
8957         int ret;
8958
8959         for (i = 0; i < RTE_DIM(reg_table); i++) {
8960                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8961                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8962                                 reg_table[i].val =
8963                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8964                         else /* For X710/XL710/XXV710 */
8965                                 reg_table[i].val =
8966                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8967                 }
8968
8969                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8970                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8971                                 reg_table[i].val =
8972                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8973                         else /* For X710/XL710/XXV710 */
8974                                 reg_table[i].val =
8975                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8976                 }
8977
8978                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8979                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8980                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8981                                 reg_table[i].val =
8982                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8983                         else /* For X710 */
8984                                 reg_table[i].val =
8985                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8986                 }
8987
8988                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8989                                                         &reg, NULL);
8990                 if (ret < 0) {
8991                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8992                                                         reg_table[i].addr);
8993                         break;
8994                 }
8995                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8996                                                 reg_table[i].addr, reg);
8997                 if (reg == reg_table[i].val)
8998                         continue;
8999
9000                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9001                                                 reg_table[i].val, NULL);
9002                 if (ret < 0) {
9003                         PMD_DRV_LOG(ERR,
9004                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9005                                 reg_table[i].val, reg_table[i].addr);
9006                         break;
9007                 }
9008                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9009                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9010         }
9011 }
9012
9013 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9014 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9015 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9016 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9017 static int
9018 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9019 {
9020         uint32_t reg;
9021         int ret;
9022
9023         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9024                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9025                 return -EINVAL;
9026         }
9027
9028         /* Configure for double VLAN RX stripping */
9029         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9030         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9031                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9032                 ret = i40e_aq_debug_write_register(hw,
9033                                                    I40E_VSI_TSR(vsi->vsi_id),
9034                                                    reg, NULL);
9035                 if (ret < 0) {
9036                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9037                                     vsi->vsi_id);
9038                         return I40E_ERR_CONFIG;
9039                 }
9040         }
9041
9042         /* Configure for double VLAN TX insertion */
9043         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9044         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9045                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9046                 ret = i40e_aq_debug_write_register(hw,
9047                                                    I40E_VSI_L2TAGSTXVALID(
9048                                                    vsi->vsi_id), reg, NULL);
9049                 if (ret < 0) {
9050                         PMD_DRV_LOG(ERR,
9051                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9052                                 vsi->vsi_id);
9053                         return I40E_ERR_CONFIG;
9054                 }
9055         }
9056
9057         return 0;
9058 }
9059
9060 /**
9061  * i40e_aq_add_mirror_rule
9062  * @hw: pointer to the hardware structure
9063  * @seid: VEB seid to add mirror rule to
9064  * @dst_id: destination vsi seid
9065  * @entries: Buffer which contains the entities to be mirrored
9066  * @count: number of entities contained in the buffer
9067  * @rule_id:the rule_id of the rule to be added
9068  *
9069  * Add a mirror rule for a given veb.
9070  *
9071  **/
9072 static enum i40e_status_code
9073 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9074                         uint16_t seid, uint16_t dst_id,
9075                         uint16_t rule_type, uint16_t *entries,
9076                         uint16_t count, uint16_t *rule_id)
9077 {
9078         struct i40e_aq_desc desc;
9079         struct i40e_aqc_add_delete_mirror_rule cmd;
9080         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9081                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9082                 &desc.params.raw;
9083         uint16_t buff_len;
9084         enum i40e_status_code status;
9085
9086         i40e_fill_default_direct_cmd_desc(&desc,
9087                                           i40e_aqc_opc_add_mirror_rule);
9088         memset(&cmd, 0, sizeof(cmd));
9089
9090         buff_len = sizeof(uint16_t) * count;
9091         desc.datalen = rte_cpu_to_le_16(buff_len);
9092         if (buff_len > 0)
9093                 desc.flags |= rte_cpu_to_le_16(
9094                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9095         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9096                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9097         cmd.num_entries = rte_cpu_to_le_16(count);
9098         cmd.seid = rte_cpu_to_le_16(seid);
9099         cmd.destination = rte_cpu_to_le_16(dst_id);
9100
9101         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9102         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9103         PMD_DRV_LOG(INFO,
9104                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9105                 hw->aq.asq_last_status, resp->rule_id,
9106                 resp->mirror_rules_used, resp->mirror_rules_free);
9107         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9108
9109         return status;
9110 }
9111
9112 /**
9113  * i40e_aq_del_mirror_rule
9114  * @hw: pointer to the hardware structure
9115  * @seid: VEB seid to add mirror rule to
9116  * @entries: Buffer which contains the entities to be mirrored
9117  * @count: number of entities contained in the buffer
9118  * @rule_id:the rule_id of the rule to be delete
9119  *
9120  * Delete a mirror rule for a given veb.
9121  *
9122  **/
9123 static enum i40e_status_code
9124 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9125                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9126                 uint16_t count, uint16_t rule_id)
9127 {
9128         struct i40e_aq_desc desc;
9129         struct i40e_aqc_add_delete_mirror_rule cmd;
9130         uint16_t buff_len = 0;
9131         enum i40e_status_code status;
9132         void *buff = NULL;
9133
9134         i40e_fill_default_direct_cmd_desc(&desc,
9135                                           i40e_aqc_opc_delete_mirror_rule);
9136         memset(&cmd, 0, sizeof(cmd));
9137         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9138                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9139                                                           I40E_AQ_FLAG_RD));
9140                 cmd.num_entries = count;
9141                 buff_len = sizeof(uint16_t) * count;
9142                 desc.datalen = rte_cpu_to_le_16(buff_len);
9143                 buff = (void *)entries;
9144         } else
9145                 /* rule id is filled in destination field for deleting mirror rule */
9146                 cmd.destination = rte_cpu_to_le_16(rule_id);
9147
9148         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9149                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9150         cmd.seid = rte_cpu_to_le_16(seid);
9151
9152         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9153         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9154
9155         return status;
9156 }
9157
9158 /**
9159  * i40e_mirror_rule_set
9160  * @dev: pointer to the hardware structure
9161  * @mirror_conf: mirror rule info
9162  * @sw_id: mirror rule's sw_id
9163  * @on: enable/disable
9164  *
9165  * set a mirror rule.
9166  *
9167  **/
9168 static int
9169 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9170                         struct rte_eth_mirror_conf *mirror_conf,
9171                         uint8_t sw_id, uint8_t on)
9172 {
9173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9175         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9176         struct i40e_mirror_rule *parent = NULL;
9177         uint16_t seid, dst_seid, rule_id;
9178         uint16_t i, j = 0;
9179         int ret;
9180
9181         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9182
9183         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9184                 PMD_DRV_LOG(ERR,
9185                         "mirror rule can not be configured without veb or vfs.");
9186                 return -ENOSYS;
9187         }
9188         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9189                 PMD_DRV_LOG(ERR, "mirror table is full.");
9190                 return -ENOSPC;
9191         }
9192         if (mirror_conf->dst_pool > pf->vf_num) {
9193                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9194                                  mirror_conf->dst_pool);
9195                 return -EINVAL;
9196         }
9197
9198         seid = pf->main_vsi->veb->seid;
9199
9200         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9201                 if (sw_id <= it->index) {
9202                         mirr_rule = it;
9203                         break;
9204                 }
9205                 parent = it;
9206         }
9207         if (mirr_rule && sw_id == mirr_rule->index) {
9208                 if (on) {
9209                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9210                         return -EEXIST;
9211                 } else {
9212                         ret = i40e_aq_del_mirror_rule(hw, seid,
9213                                         mirr_rule->rule_type,
9214                                         mirr_rule->entries,
9215                                         mirr_rule->num_entries, mirr_rule->id);
9216                         if (ret < 0) {
9217                                 PMD_DRV_LOG(ERR,
9218                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9219                                         ret, hw->aq.asq_last_status);
9220                                 return -ENOSYS;
9221                         }
9222                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9223                         rte_free(mirr_rule);
9224                         pf->nb_mirror_rule--;
9225                         return 0;
9226                 }
9227         } else if (!on) {
9228                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9229                 return -ENOENT;
9230         }
9231
9232         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9233                                 sizeof(struct i40e_mirror_rule) , 0);
9234         if (!mirr_rule) {
9235                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9236                 return I40E_ERR_NO_MEMORY;
9237         }
9238         switch (mirror_conf->rule_type) {
9239         case ETH_MIRROR_VLAN:
9240                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9241                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9242                                 mirr_rule->entries[j] =
9243                                         mirror_conf->vlan.vlan_id[i];
9244                                 j++;
9245                         }
9246                 }
9247                 if (j == 0) {
9248                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9249                         rte_free(mirr_rule);
9250                         return -EINVAL;
9251                 }
9252                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9253                 break;
9254         case ETH_MIRROR_VIRTUAL_POOL_UP:
9255         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9256                 /* check if the specified pool bit is out of range */
9257                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9258                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9259                         rte_free(mirr_rule);
9260                         return -EINVAL;
9261                 }
9262                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9263                         if (mirror_conf->pool_mask & (1ULL << i)) {
9264                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9265                                 j++;
9266                         }
9267                 }
9268                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9269                         /* add pf vsi to entries */
9270                         mirr_rule->entries[j] = pf->main_vsi_seid;
9271                         j++;
9272                 }
9273                 if (j == 0) {
9274                         PMD_DRV_LOG(ERR, "pool is not specified.");
9275                         rte_free(mirr_rule);
9276                         return -EINVAL;
9277                 }
9278                 /* egress and ingress in aq commands means from switch but not port */
9279                 mirr_rule->rule_type =
9280                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9281                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9282                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9283                 break;
9284         case ETH_MIRROR_UPLINK_PORT:
9285                 /* egress and ingress in aq commands means from switch but not port*/
9286                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9287                 break;
9288         case ETH_MIRROR_DOWNLINK_PORT:
9289                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9290                 break;
9291         default:
9292                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9293                         mirror_conf->rule_type);
9294                 rte_free(mirr_rule);
9295                 return -EINVAL;
9296         }
9297
9298         /* If the dst_pool is equal to vf_num, consider it as PF */
9299         if (mirror_conf->dst_pool == pf->vf_num)
9300                 dst_seid = pf->main_vsi_seid;
9301         else
9302                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9303
9304         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9305                                       mirr_rule->rule_type, mirr_rule->entries,
9306                                       j, &rule_id);
9307         if (ret < 0) {
9308                 PMD_DRV_LOG(ERR,
9309                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9310                         ret, hw->aq.asq_last_status);
9311                 rte_free(mirr_rule);
9312                 return -ENOSYS;
9313         }
9314
9315         mirr_rule->index = sw_id;
9316         mirr_rule->num_entries = j;
9317         mirr_rule->id = rule_id;
9318         mirr_rule->dst_vsi_seid = dst_seid;
9319
9320         if (parent)
9321                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9322         else
9323                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9324
9325         pf->nb_mirror_rule++;
9326         return 0;
9327 }
9328
9329 /**
9330  * i40e_mirror_rule_reset
9331  * @dev: pointer to the device
9332  * @sw_id: mirror rule's sw_id
9333  *
9334  * reset a mirror rule.
9335  *
9336  **/
9337 static int
9338 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9339 {
9340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9342         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9343         uint16_t seid;
9344         int ret;
9345
9346         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9347
9348         seid = pf->main_vsi->veb->seid;
9349
9350         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9351                 if (sw_id == it->index) {
9352                         mirr_rule = it;
9353                         break;
9354                 }
9355         }
9356         if (mirr_rule) {
9357                 ret = i40e_aq_del_mirror_rule(hw, seid,
9358                                 mirr_rule->rule_type,
9359                                 mirr_rule->entries,
9360                                 mirr_rule->num_entries, mirr_rule->id);
9361                 if (ret < 0) {
9362                         PMD_DRV_LOG(ERR,
9363                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9364                                 ret, hw->aq.asq_last_status);
9365                         return -ENOSYS;
9366                 }
9367                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9368                 rte_free(mirr_rule);
9369                 pf->nb_mirror_rule--;
9370         } else {
9371                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9372                 return -ENOENT;
9373         }
9374         return 0;
9375 }
9376
9377 static uint64_t
9378 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9379 {
9380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9381         uint64_t systim_cycles;
9382
9383         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9384         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9385                         << 32;
9386
9387         return systim_cycles;
9388 }
9389
9390 static uint64_t
9391 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9392 {
9393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9394         uint64_t rx_tstamp;
9395
9396         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9397         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9398                         << 32;
9399
9400         return rx_tstamp;
9401 }
9402
9403 static uint64_t
9404 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9405 {
9406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9407         uint64_t tx_tstamp;
9408
9409         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9410         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9411                         << 32;
9412
9413         return tx_tstamp;
9414 }
9415
9416 static void
9417 i40e_start_timecounters(struct rte_eth_dev *dev)
9418 {
9419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9420         struct i40e_adapter *adapter =
9421                         (struct i40e_adapter *)dev->data->dev_private;
9422         struct rte_eth_link link;
9423         uint32_t tsync_inc_l;
9424         uint32_t tsync_inc_h;
9425
9426         /* Get current link speed. */
9427         memset(&link, 0, sizeof(link));
9428         i40e_dev_link_update(dev, 1);
9429         rte_i40e_dev_atomic_read_link_status(dev, &link);
9430
9431         switch (link.link_speed) {
9432         case ETH_SPEED_NUM_40G:
9433                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9434                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9435                 break;
9436         case ETH_SPEED_NUM_10G:
9437                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9438                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9439                 break;
9440         case ETH_SPEED_NUM_1G:
9441                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9442                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9443                 break;
9444         default:
9445                 tsync_inc_l = 0x0;
9446                 tsync_inc_h = 0x0;
9447         }
9448
9449         /* Set the timesync increment value. */
9450         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9451         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9452
9453         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9454         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9455         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9456
9457         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9458         adapter->systime_tc.cc_shift = 0;
9459         adapter->systime_tc.nsec_mask = 0;
9460
9461         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9462         adapter->rx_tstamp_tc.cc_shift = 0;
9463         adapter->rx_tstamp_tc.nsec_mask = 0;
9464
9465         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9466         adapter->tx_tstamp_tc.cc_shift = 0;
9467         adapter->tx_tstamp_tc.nsec_mask = 0;
9468 }
9469
9470 static int
9471 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9472 {
9473         struct i40e_adapter *adapter =
9474                         (struct i40e_adapter *)dev->data->dev_private;
9475
9476         adapter->systime_tc.nsec += delta;
9477         adapter->rx_tstamp_tc.nsec += delta;
9478         adapter->tx_tstamp_tc.nsec += delta;
9479
9480         return 0;
9481 }
9482
9483 static int
9484 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9485 {
9486         uint64_t ns;
9487         struct i40e_adapter *adapter =
9488                         (struct i40e_adapter *)dev->data->dev_private;
9489
9490         ns = rte_timespec_to_ns(ts);
9491
9492         /* Set the timecounters to a new value. */
9493         adapter->systime_tc.nsec = ns;
9494         adapter->rx_tstamp_tc.nsec = ns;
9495         adapter->tx_tstamp_tc.nsec = ns;
9496
9497         return 0;
9498 }
9499
9500 static int
9501 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9502 {
9503         uint64_t ns, systime_cycles;
9504         struct i40e_adapter *adapter =
9505                         (struct i40e_adapter *)dev->data->dev_private;
9506
9507         systime_cycles = i40e_read_systime_cyclecounter(dev);
9508         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9509         *ts = rte_ns_to_timespec(ns);
9510
9511         return 0;
9512 }
9513
9514 static int
9515 i40e_timesync_enable(struct rte_eth_dev *dev)
9516 {
9517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9518         uint32_t tsync_ctl_l;
9519         uint32_t tsync_ctl_h;
9520
9521         /* Stop the timesync system time. */
9522         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9523         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9524         /* Reset the timesync system time value. */
9525         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9526         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9527
9528         i40e_start_timecounters(dev);
9529
9530         /* Clear timesync registers. */
9531         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9532         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9533         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9534         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9535         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9536         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9537
9538         /* Enable timestamping of PTP packets. */
9539         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9540         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9541
9542         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9543         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9544         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9545
9546         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9547         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9548
9549         return 0;
9550 }
9551
9552 static int
9553 i40e_timesync_disable(struct rte_eth_dev *dev)
9554 {
9555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9556         uint32_t tsync_ctl_l;
9557         uint32_t tsync_ctl_h;
9558
9559         /* Disable timestamping of transmitted PTP packets. */
9560         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9561         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9562
9563         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9564         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9565
9566         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9567         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9568
9569         /* Reset the timesync increment value. */
9570         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9571         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9572
9573         return 0;
9574 }
9575
9576 static int
9577 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9578                                 struct timespec *timestamp, uint32_t flags)
9579 {
9580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9581         struct i40e_adapter *adapter =
9582                 (struct i40e_adapter *)dev->data->dev_private;
9583
9584         uint32_t sync_status;
9585         uint32_t index = flags & 0x03;
9586         uint64_t rx_tstamp_cycles;
9587         uint64_t ns;
9588
9589         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9590         if ((sync_status & (1 << index)) == 0)
9591                 return -EINVAL;
9592
9593         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9594         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9595         *timestamp = rte_ns_to_timespec(ns);
9596
9597         return 0;
9598 }
9599
9600 static int
9601 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9602                                 struct timespec *timestamp)
9603 {
9604         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9605         struct i40e_adapter *adapter =
9606                 (struct i40e_adapter *)dev->data->dev_private;
9607
9608         uint32_t sync_status;
9609         uint64_t tx_tstamp_cycles;
9610         uint64_t ns;
9611
9612         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9613         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9614                 return -EINVAL;
9615
9616         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9617         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9618         *timestamp = rte_ns_to_timespec(ns);
9619
9620         return 0;
9621 }
9622
9623 /*
9624  * i40e_parse_dcb_configure - parse dcb configure from user
9625  * @dev: the device being configured
9626  * @dcb_cfg: pointer of the result of parse
9627  * @*tc_map: bit map of enabled traffic classes
9628  *
9629  * Returns 0 on success, negative value on failure
9630  */
9631 static int
9632 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9633                          struct i40e_dcbx_config *dcb_cfg,
9634                          uint8_t *tc_map)
9635 {
9636         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9637         uint8_t i, tc_bw, bw_lf;
9638
9639         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9640
9641         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9642         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9643                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9644                 return -EINVAL;
9645         }
9646
9647         /* assume each tc has the same bw */
9648         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9649         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9650                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9651         /* to ensure the sum of tcbw is equal to 100 */
9652         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9653         for (i = 0; i < bw_lf; i++)
9654                 dcb_cfg->etscfg.tcbwtable[i]++;
9655
9656         /* assume each tc has the same Transmission Selection Algorithm */
9657         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9658                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9659
9660         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9661                 dcb_cfg->etscfg.prioritytable[i] =
9662                                 dcb_rx_conf->dcb_tc[i];
9663
9664         /* FW needs one App to configure HW */
9665         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9666         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9667         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9668         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9669
9670         if (dcb_rx_conf->nb_tcs == 0)
9671                 *tc_map = 1; /* tc0 only */
9672         else
9673                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9674
9675         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9676                 dcb_cfg->pfc.willing = 0;
9677                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9678                 dcb_cfg->pfc.pfcenable = *tc_map;
9679         }
9680         return 0;
9681 }
9682
9683
9684 static enum i40e_status_code
9685 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9686                               struct i40e_aqc_vsi_properties_data *info,
9687                               uint8_t enabled_tcmap)
9688 {
9689         enum i40e_status_code ret;
9690         int i, total_tc = 0;
9691         uint16_t qpnum_per_tc, bsf, qp_idx;
9692         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9693         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9694         uint16_t used_queues;
9695
9696         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9697         if (ret != I40E_SUCCESS)
9698                 return ret;
9699
9700         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9701                 if (enabled_tcmap & (1 << i))
9702                         total_tc++;
9703         }
9704         if (total_tc == 0)
9705                 total_tc = 1;
9706         vsi->enabled_tc = enabled_tcmap;
9707
9708         /* different VSI has different queues assigned */
9709         if (vsi->type == I40E_VSI_MAIN)
9710                 used_queues = dev_data->nb_rx_queues -
9711                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9712         else if (vsi->type == I40E_VSI_VMDQ2)
9713                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9714         else {
9715                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9716                 return I40E_ERR_NO_AVAILABLE_VSI;
9717         }
9718
9719         qpnum_per_tc = used_queues / total_tc;
9720         /* Number of queues per enabled TC */
9721         if (qpnum_per_tc == 0) {
9722                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9723                 return I40E_ERR_INVALID_QP_ID;
9724         }
9725         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9726                                 I40E_MAX_Q_PER_TC);
9727         bsf = rte_bsf32(qpnum_per_tc);
9728
9729         /**
9730          * Configure TC and queue mapping parameters, for enabled TC,
9731          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9732          * default queue will serve it.
9733          */
9734         qp_idx = 0;
9735         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9736                 if (vsi->enabled_tc & (1 << i)) {
9737                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9738                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9739                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9740                         qp_idx += qpnum_per_tc;
9741                 } else
9742                         info->tc_mapping[i] = 0;
9743         }
9744
9745         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9746         if (vsi->type == I40E_VSI_SRIOV) {
9747                 info->mapping_flags |=
9748                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9749                 for (i = 0; i < vsi->nb_qps; i++)
9750                         info->queue_mapping[i] =
9751                                 rte_cpu_to_le_16(vsi->base_queue + i);
9752         } else {
9753                 info->mapping_flags |=
9754                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9755                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9756         }
9757         info->valid_sections |=
9758                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9759
9760         return I40E_SUCCESS;
9761 }
9762
9763 /*
9764  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9765  * @veb: VEB to be configured
9766  * @tc_map: enabled TC bitmap
9767  *
9768  * Returns 0 on success, negative value on failure
9769  */
9770 static enum i40e_status_code
9771 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9772 {
9773         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9774         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9775         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9776         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9777         enum i40e_status_code ret = I40E_SUCCESS;
9778         int i;
9779         uint32_t bw_max;
9780
9781         /* Check if enabled_tc is same as existing or new TCs */
9782         if (veb->enabled_tc == tc_map)
9783                 return ret;
9784
9785         /* configure tc bandwidth */
9786         memset(&veb_bw, 0, sizeof(veb_bw));
9787         veb_bw.tc_valid_bits = tc_map;
9788         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9789         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9790                 if (tc_map & BIT_ULL(i))
9791                         veb_bw.tc_bw_share_credits[i] = 1;
9792         }
9793         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9794                                                    &veb_bw, NULL);
9795         if (ret) {
9796                 PMD_INIT_LOG(ERR,
9797                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9798                         hw->aq.asq_last_status);
9799                 return ret;
9800         }
9801
9802         memset(&ets_query, 0, sizeof(ets_query));
9803         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9804                                                    &ets_query, NULL);
9805         if (ret != I40E_SUCCESS) {
9806                 PMD_DRV_LOG(ERR,
9807                         "Failed to get switch_comp ETS configuration %u",
9808                         hw->aq.asq_last_status);
9809                 return ret;
9810         }
9811         memset(&bw_query, 0, sizeof(bw_query));
9812         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9813                                                   &bw_query, NULL);
9814         if (ret != I40E_SUCCESS) {
9815                 PMD_DRV_LOG(ERR,
9816                         "Failed to get switch_comp bandwidth configuration %u",
9817                         hw->aq.asq_last_status);
9818                 return ret;
9819         }
9820
9821         /* store and print out BW info */
9822         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9823         veb->bw_info.bw_max = ets_query.tc_bw_max;
9824         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9825         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9826         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9827                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9828                      I40E_16_BIT_WIDTH);
9829         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9830                 veb->bw_info.bw_ets_share_credits[i] =
9831                                 bw_query.tc_bw_share_credits[i];
9832                 veb->bw_info.bw_ets_credits[i] =
9833                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9834                 /* 4 bits per TC, 4th bit is reserved */
9835                 veb->bw_info.bw_ets_max[i] =
9836                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9837                                   RTE_LEN2MASK(3, uint8_t));
9838                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9839                             veb->bw_info.bw_ets_share_credits[i]);
9840                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9841                             veb->bw_info.bw_ets_credits[i]);
9842                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9843                             veb->bw_info.bw_ets_max[i]);
9844         }
9845
9846         veb->enabled_tc = tc_map;
9847
9848         return ret;
9849 }
9850
9851
9852 /*
9853  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9854  * @vsi: VSI to be configured
9855  * @tc_map: enabled TC bitmap
9856  *
9857  * Returns 0 on success, negative value on failure
9858  */
9859 static enum i40e_status_code
9860 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9861 {
9862         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9863         struct i40e_vsi_context ctxt;
9864         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9865         enum i40e_status_code ret = I40E_SUCCESS;
9866         int i;
9867
9868         /* Check if enabled_tc is same as existing or new TCs */
9869         if (vsi->enabled_tc == tc_map)
9870                 return ret;
9871
9872         /* configure tc bandwidth */
9873         memset(&bw_data, 0, sizeof(bw_data));
9874         bw_data.tc_valid_bits = tc_map;
9875         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9876         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9877                 if (tc_map & BIT_ULL(i))
9878                         bw_data.tc_bw_credits[i] = 1;
9879         }
9880         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9881         if (ret) {
9882                 PMD_INIT_LOG(ERR,
9883                         "AQ command Config VSI BW allocation per TC failed = %d",
9884                         hw->aq.asq_last_status);
9885                 goto out;
9886         }
9887         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9888                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9889
9890         /* Update Queue Pairs Mapping for currently enabled UPs */
9891         ctxt.seid = vsi->seid;
9892         ctxt.pf_num = hw->pf_id;
9893         ctxt.vf_num = 0;
9894         ctxt.uplink_seid = vsi->uplink_seid;
9895         ctxt.info = vsi->info;
9896         i40e_get_cap(hw);
9897         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9898         if (ret)
9899                 goto out;
9900
9901         /* Update the VSI after updating the VSI queue-mapping information */
9902         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9903         if (ret) {
9904                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9905                         hw->aq.asq_last_status);
9906                 goto out;
9907         }
9908         /* update the local VSI info with updated queue map */
9909         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9910                                         sizeof(vsi->info.tc_mapping));
9911         (void)rte_memcpy(&vsi->info.queue_mapping,
9912                         &ctxt.info.queue_mapping,
9913                 sizeof(vsi->info.queue_mapping));
9914         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9915         vsi->info.valid_sections = 0;
9916
9917         /* query and update current VSI BW information */
9918         ret = i40e_vsi_get_bw_config(vsi);
9919         if (ret) {
9920                 PMD_INIT_LOG(ERR,
9921                          "Failed updating vsi bw info, err %s aq_err %s",
9922                          i40e_stat_str(hw, ret),
9923                          i40e_aq_str(hw, hw->aq.asq_last_status));
9924                 goto out;
9925         }
9926
9927         vsi->enabled_tc = tc_map;
9928
9929 out:
9930         return ret;
9931 }
9932
9933 /*
9934  * i40e_dcb_hw_configure - program the dcb setting to hw
9935  * @pf: pf the configuration is taken on
9936  * @new_cfg: new configuration
9937  * @tc_map: enabled TC bitmap
9938  *
9939  * Returns 0 on success, negative value on failure
9940  */
9941 static enum i40e_status_code
9942 i40e_dcb_hw_configure(struct i40e_pf *pf,
9943                       struct i40e_dcbx_config *new_cfg,
9944                       uint8_t tc_map)
9945 {
9946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9947         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9948         struct i40e_vsi *main_vsi = pf->main_vsi;
9949         struct i40e_vsi_list *vsi_list;
9950         enum i40e_status_code ret;
9951         int i;
9952         uint32_t val;
9953
9954         /* Use the FW API if FW > v4.4*/
9955         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9956               (hw->aq.fw_maj_ver >= 5))) {
9957                 PMD_INIT_LOG(ERR,
9958                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9959                 return I40E_ERR_FIRMWARE_API_VERSION;
9960         }
9961
9962         /* Check if need reconfiguration */
9963         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9964                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9965                 return I40E_SUCCESS;
9966         }
9967
9968         /* Copy the new config to the current config */
9969         *old_cfg = *new_cfg;
9970         old_cfg->etsrec = old_cfg->etscfg;
9971         ret = i40e_set_dcb_config(hw);
9972         if (ret) {
9973                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9974                          i40e_stat_str(hw, ret),
9975                          i40e_aq_str(hw, hw->aq.asq_last_status));
9976                 return ret;
9977         }
9978         /* set receive Arbiter to RR mode and ETS scheme by default */
9979         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9980                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9981                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9982                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9983                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9984                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9985                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9986                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9987                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9988                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9989                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9990                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9991                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9992         }
9993         /* get local mib to check whether it is configured correctly */
9994         /* IEEE mode */
9995         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9996         /* Get Local DCB Config */
9997         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9998                                      &hw->local_dcbx_config);
9999
10000         /* if Veb is created, need to update TC of it at first */
10001         if (main_vsi->veb) {
10002                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10003                 if (ret)
10004                         PMD_INIT_LOG(WARNING,
10005                                  "Failed configuring TC for VEB seid=%d",
10006                                  main_vsi->veb->seid);
10007         }
10008         /* Update each VSI */
10009         i40e_vsi_config_tc(main_vsi, tc_map);
10010         if (main_vsi->veb) {
10011                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10012                         /* Beside main VSI and VMDQ VSIs, only enable default
10013                          * TC for other VSIs
10014                          */
10015                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10016                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10017                                                          tc_map);
10018                         else
10019                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10020                                                          I40E_DEFAULT_TCMAP);
10021                         if (ret)
10022                                 PMD_INIT_LOG(WARNING,
10023                                         "Failed configuring TC for VSI seid=%d",
10024                                         vsi_list->vsi->seid);
10025                         /* continue */
10026                 }
10027         }
10028         return I40E_SUCCESS;
10029 }
10030
10031 /*
10032  * i40e_dcb_init_configure - initial dcb config
10033  * @dev: device being configured
10034  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10035  *
10036  * Returns 0 on success, negative value on failure
10037  */
10038 static int
10039 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10040 {
10041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10043         int i, ret = 0;
10044
10045         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10046                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10047                 return -ENOTSUP;
10048         }
10049
10050         /* DCB initialization:
10051          * Update DCB configuration from the Firmware and configure
10052          * LLDP MIB change event.
10053          */
10054         if (sw_dcb == TRUE) {
10055                 ret = i40e_init_dcb(hw);
10056                 /* If lldp agent is stopped, the return value from
10057                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10058                  * adminq status. Otherwise, it should return success.
10059                  */
10060                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10061                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10062                         memset(&hw->local_dcbx_config, 0,
10063                                 sizeof(struct i40e_dcbx_config));
10064                         /* set dcb default configuration */
10065                         hw->local_dcbx_config.etscfg.willing = 0;
10066                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10067                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10068                         hw->local_dcbx_config.etscfg.tsatable[0] =
10069                                                 I40E_IEEE_TSA_ETS;
10070                         /* all UPs mapping to TC0 */
10071                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10072                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10073                         hw->local_dcbx_config.etsrec =
10074                                 hw->local_dcbx_config.etscfg;
10075                         hw->local_dcbx_config.pfc.willing = 0;
10076                         hw->local_dcbx_config.pfc.pfccap =
10077                                                 I40E_MAX_TRAFFIC_CLASS;
10078                         hw->local_dcbx_config.pfc.pfcenable =
10079                                                 I40E_DEFAULT_TCMAP;
10080                         /* FW needs one App to configure HW */
10081                         hw->local_dcbx_config.numapps = 1;
10082                         hw->local_dcbx_config.app[0].selector =
10083                                                 I40E_APP_SEL_ETHTYPE;
10084                         hw->local_dcbx_config.app[0].priority = 3;
10085                         hw->local_dcbx_config.app[0].protocolid =
10086                                                 I40E_APP_PROTOID_FCOE;
10087                         ret = i40e_set_dcb_config(hw);
10088                         if (ret) {
10089                                 PMD_INIT_LOG(ERR,
10090                                         "default dcb config fails. err = %d, aq_err = %d.",
10091                                         ret, hw->aq.asq_last_status);
10092                                 return -ENOSYS;
10093                         }
10094                 } else {
10095                         PMD_INIT_LOG(ERR,
10096                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10097                                 ret, hw->aq.asq_last_status);
10098                         return -ENOTSUP;
10099                 }
10100         } else {
10101                 ret = i40e_aq_start_lldp(hw, NULL);
10102                 if (ret != I40E_SUCCESS)
10103                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10104
10105                 ret = i40e_init_dcb(hw);
10106                 if (!ret) {
10107                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10108                                 PMD_INIT_LOG(ERR,
10109                                         "HW doesn't support DCBX offload.");
10110                                 return -ENOTSUP;
10111                         }
10112                 } else {
10113                         PMD_INIT_LOG(ERR,
10114                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10115                                 ret, hw->aq.asq_last_status);
10116                         return -ENOTSUP;
10117                 }
10118         }
10119         return 0;
10120 }
10121
10122 /*
10123  * i40e_dcb_setup - setup dcb related config
10124  * @dev: device being configured
10125  *
10126  * Returns 0 on success, negative value on failure
10127  */
10128 static int
10129 i40e_dcb_setup(struct rte_eth_dev *dev)
10130 {
10131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10132         struct i40e_dcbx_config dcb_cfg;
10133         uint8_t tc_map = 0;
10134         int ret = 0;
10135
10136         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10137                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10138                 return -ENOTSUP;
10139         }
10140
10141         if (pf->vf_num != 0)
10142                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10143
10144         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10145         if (ret) {
10146                 PMD_INIT_LOG(ERR, "invalid dcb config");
10147                 return -EINVAL;
10148         }
10149         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10150         if (ret) {
10151                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10152                 return -ENOSYS;
10153         }
10154
10155         return 0;
10156 }
10157
10158 static int
10159 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10160                       struct rte_eth_dcb_info *dcb_info)
10161 {
10162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10164         struct i40e_vsi *vsi = pf->main_vsi;
10165         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10166         uint16_t bsf, tc_mapping;
10167         int i, j = 0;
10168
10169         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10170                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10171         else
10172                 dcb_info->nb_tcs = 1;
10173         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10174                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10175         for (i = 0; i < dcb_info->nb_tcs; i++)
10176                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10177
10178         /* get queue mapping if vmdq is disabled */
10179         if (!pf->nb_cfg_vmdq_vsi) {
10180                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10181                         if (!(vsi->enabled_tc & (1 << i)))
10182                                 continue;
10183                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10184                         dcb_info->tc_queue.tc_rxq[j][i].base =
10185                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10186                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10187                         dcb_info->tc_queue.tc_txq[j][i].base =
10188                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10189                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10190                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10191                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10192                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10193                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10194                 }
10195                 return 0;
10196         }
10197
10198         /* get queue mapping if vmdq is enabled */
10199         do {
10200                 vsi = pf->vmdq[j].vsi;
10201                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10202                         if (!(vsi->enabled_tc & (1 << i)))
10203                                 continue;
10204                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10205                         dcb_info->tc_queue.tc_rxq[j][i].base =
10206                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10207                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10208                         dcb_info->tc_queue.tc_txq[j][i].base =
10209                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10210                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10211                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10212                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10213                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10214                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10215                 }
10216                 j++;
10217         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10218         return 0;
10219 }
10220
10221 static int
10222 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10223 {
10224         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10225         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10227         uint16_t interval =
10228                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10229         uint16_t msix_intr;
10230
10231         msix_intr = intr_handle->intr_vec[queue_id];
10232         if (msix_intr == I40E_MISC_VEC_ID)
10233                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10234                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10235                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10236                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10237                                (interval <<
10238                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10239         else
10240                 I40E_WRITE_REG(hw,
10241                                I40E_PFINT_DYN_CTLN(msix_intr -
10242                                                    I40E_RX_VEC_START),
10243                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10244                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10245                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10246                                (interval <<
10247                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10248
10249         I40E_WRITE_FLUSH(hw);
10250         rte_intr_enable(&pci_dev->intr_handle);
10251
10252         return 0;
10253 }
10254
10255 static int
10256 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10257 {
10258         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10259         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10261         uint16_t msix_intr;
10262
10263         msix_intr = intr_handle->intr_vec[queue_id];
10264         if (msix_intr == I40E_MISC_VEC_ID)
10265                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10266         else
10267                 I40E_WRITE_REG(hw,
10268                                I40E_PFINT_DYN_CTLN(msix_intr -
10269                                                    I40E_RX_VEC_START),
10270                                0);
10271         I40E_WRITE_FLUSH(hw);
10272
10273         return 0;
10274 }
10275
10276 static int i40e_get_regs(struct rte_eth_dev *dev,
10277                          struct rte_dev_reg_info *regs)
10278 {
10279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10280         uint32_t *ptr_data = regs->data;
10281         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10282         const struct i40e_reg_info *reg_info;
10283
10284         if (ptr_data == NULL) {
10285                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10286                 regs->width = sizeof(uint32_t);
10287                 return 0;
10288         }
10289
10290         /* The first few registers have to be read using AQ operations */
10291         reg_idx = 0;
10292         while (i40e_regs_adminq[reg_idx].name) {
10293                 reg_info = &i40e_regs_adminq[reg_idx++];
10294                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10295                         for (arr_idx2 = 0;
10296                                         arr_idx2 <= reg_info->count2;
10297                                         arr_idx2++) {
10298                                 reg_offset = arr_idx * reg_info->stride1 +
10299                                         arr_idx2 * reg_info->stride2;
10300                                 reg_offset += reg_info->base_addr;
10301                                 ptr_data[reg_offset >> 2] =
10302                                         i40e_read_rx_ctl(hw, reg_offset);
10303                         }
10304         }
10305
10306         /* The remaining registers can be read using primitives */
10307         reg_idx = 0;
10308         while (i40e_regs_others[reg_idx].name) {
10309                 reg_info = &i40e_regs_others[reg_idx++];
10310                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10311                         for (arr_idx2 = 0;
10312                                         arr_idx2 <= reg_info->count2;
10313                                         arr_idx2++) {
10314                                 reg_offset = arr_idx * reg_info->stride1 +
10315                                         arr_idx2 * reg_info->stride2;
10316                                 reg_offset += reg_info->base_addr;
10317                                 ptr_data[reg_offset >> 2] =
10318                                         I40E_READ_REG(hw, reg_offset);
10319                         }
10320         }
10321
10322         return 0;
10323 }
10324
10325 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10326 {
10327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10328
10329         /* Convert word count to byte count */
10330         return hw->nvm.sr_size << 1;
10331 }
10332
10333 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10334                            struct rte_dev_eeprom_info *eeprom)
10335 {
10336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10337         uint16_t *data = eeprom->data;
10338         uint16_t offset, length, cnt_words;
10339         int ret_code;
10340
10341         offset = eeprom->offset >> 1;
10342         length = eeprom->length >> 1;
10343         cnt_words = length;
10344
10345         if (offset > hw->nvm.sr_size ||
10346                 offset + length > hw->nvm.sr_size) {
10347                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10348                 return -EINVAL;
10349         }
10350
10351         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10352
10353         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10354         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10355                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10356                 return -EIO;
10357         }
10358
10359         return 0;
10360 }
10361
10362 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10363                                       struct ether_addr *mac_addr)
10364 {
10365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10366
10367         if (!is_valid_assigned_ether_addr(mac_addr)) {
10368                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10369                 return;
10370         }
10371
10372         /* Flags: 0x3 updates port address */
10373         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10374 }
10375
10376 static int
10377 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10378 {
10379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10380         struct rte_eth_dev_data *dev_data = pf->dev_data;
10381         uint32_t frame_size = mtu + ETHER_HDR_LEN
10382                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10383         int ret = 0;
10384
10385         /* check if mtu is within the allowed range */
10386         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10387                 return -EINVAL;
10388
10389         /* mtu setting is forbidden if port is start */
10390         if (dev_data->dev_started) {
10391                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10392                             dev_data->port_id);
10393                 return -EBUSY;
10394         }
10395
10396         if (frame_size > ETHER_MAX_LEN)
10397                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10398         else
10399                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10400
10401         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10402
10403         return ret;
10404 }
10405
10406 /* Restore ethertype filter */
10407 static void
10408 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10409 {
10410         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10411         struct i40e_ethertype_filter_list
10412                 *ethertype_list = &pf->ethertype.ethertype_list;
10413         struct i40e_ethertype_filter *f;
10414         struct i40e_control_filter_stats stats;
10415         uint16_t flags;
10416
10417         TAILQ_FOREACH(f, ethertype_list, rules) {
10418                 flags = 0;
10419                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10420                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10421                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10422                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10423                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10424
10425                 memset(&stats, 0, sizeof(stats));
10426                 i40e_aq_add_rem_control_packet_filter(hw,
10427                                             f->input.mac_addr.addr_bytes,
10428                                             f->input.ether_type,
10429                                             flags, pf->main_vsi->seid,
10430                                             f->queue, 1, &stats, NULL);
10431         }
10432         PMD_DRV_LOG(INFO, "Ethertype filter:"
10433                     " mac_etype_used = %u, etype_used = %u,"
10434                     " mac_etype_free = %u, etype_free = %u",
10435                     stats.mac_etype_used, stats.etype_used,
10436                     stats.mac_etype_free, stats.etype_free);
10437 }
10438
10439 /* Restore tunnel filter */
10440 static void
10441 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10442 {
10443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10444         struct i40e_vsi *vsi = pf->main_vsi;
10445         struct i40e_tunnel_filter_list
10446                 *tunnel_list = &pf->tunnel.tunnel_list;
10447         struct i40e_tunnel_filter *f;
10448         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10449
10450         TAILQ_FOREACH(f, tunnel_list, rules) {
10451                 memset(&cld_filter, 0, sizeof(cld_filter));
10452                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10453                         (struct ether_addr *)&cld_filter.element.outer_mac);
10454                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10455                         (struct ether_addr *)&cld_filter.element.inner_mac);
10456                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10457                 cld_filter.element.flags = f->input.flags;
10458                 cld_filter.element.tenant_id = f->input.tenant_id;
10459                 cld_filter.element.queue_number = f->queue;
10460                 rte_memcpy(cld_filter.general_fields,
10461                            f->input.general_fields,
10462                            sizeof(f->input.general_fields));
10463
10464                 i40e_aq_add_cloud_filters(hw, vsi->seid,
10465                                           &cld_filter.element, 1);
10466         }
10467 }
10468
10469 static void
10470 i40e_filter_restore(struct i40e_pf *pf)
10471 {
10472         i40e_ethertype_filter_restore(pf);
10473         i40e_tunnel_filter_restore(pf);
10474         i40e_fdir_filter_restore(pf);
10475 }
10476
10477 static bool
10478 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10479 {
10480         if (strcmp(dev->driver->pci_drv.driver.name,
10481                    drv->pci_drv.driver.name))
10482                 return false;
10483
10484         return true;
10485 }
10486
10487 int
10488 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10489 {
10490         struct rte_eth_dev *dev;
10491         struct i40e_pf *pf;
10492
10493         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10494
10495         dev = &rte_eth_devices[port];
10496
10497         if (!is_device_supported(dev, &rte_i40e_pmd))
10498                 return -ENOTSUP;
10499
10500         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10501
10502         if (vf >= pf->vf_num || !pf->vfs) {
10503                 PMD_DRV_LOG(ERR, "Invalid argument.");
10504                 return -EINVAL;
10505         }
10506
10507         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10508
10509         return 0;
10510 }
10511
10512 int
10513 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10514 {
10515         struct rte_eth_dev *dev;
10516         struct i40e_pf *pf;
10517         struct i40e_vsi *vsi;
10518         struct i40e_hw *hw;
10519         struct i40e_vsi_context ctxt;
10520         int ret;
10521
10522         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10523
10524         dev = &rte_eth_devices[port];
10525
10526         if (!is_device_supported(dev, &rte_i40e_pmd))
10527                 return -ENOTSUP;
10528
10529         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10530
10531         if (vf_id >= pf->vf_num || !pf->vfs) {
10532                 PMD_DRV_LOG(ERR, "Invalid argument.");
10533                 return -EINVAL;
10534         }
10535
10536         vsi = pf->vfs[vf_id].vsi;
10537         if (!vsi) {
10538                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10539                 return -EINVAL;
10540         }
10541
10542         /* Check if it has been already on or off */
10543         if (vsi->info.valid_sections &
10544                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10545                 if (on) {
10546                         if ((vsi->info.sec_flags &
10547                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10548                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10549                                 return 0; /* already on */
10550                 } else {
10551                         if ((vsi->info.sec_flags &
10552                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10553                                 return 0; /* already off */
10554                 }
10555         }
10556
10557         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10558         if (on)
10559                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10560         else
10561                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10562
10563         memset(&ctxt, 0, sizeof(ctxt));
10564         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10565         ctxt.seid = vsi->seid;
10566
10567         hw = I40E_VSI_TO_HW(vsi);
10568         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10569         if (ret != I40E_SUCCESS) {
10570                 ret = -ENOTSUP;
10571                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10572         }
10573
10574         return ret;
10575 }
10576
10577 static int
10578 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10579 {
10580         uint32_t j, k;
10581         uint16_t vlan_id;
10582         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10583         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10584         int ret;
10585
10586         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10587                 if (!vsi->vfta[j])
10588                         continue;
10589
10590                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10591                         if (!(vsi->vfta[j] & (1 << k)))
10592                                 continue;
10593
10594                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10595                         if (!vlan_id)
10596                                 continue;
10597
10598                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10599                         if (add)
10600                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10601                                                        &vlan_data, 1, NULL);
10602                         else
10603                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10604                                                           &vlan_data, 1, NULL);
10605                         if (ret != I40E_SUCCESS) {
10606                                 PMD_DRV_LOG(ERR,
10607                                             "Failed to add/rm vlan filter");
10608                                 return ret;
10609                         }
10610                 }
10611         }
10612
10613         return I40E_SUCCESS;
10614 }
10615
10616 int
10617 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10618 {
10619         struct rte_eth_dev *dev;
10620         struct i40e_pf *pf;
10621         struct i40e_vsi *vsi;
10622         struct i40e_hw *hw;
10623         struct i40e_vsi_context ctxt;
10624         int ret;
10625
10626         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10627
10628         dev = &rte_eth_devices[port];
10629
10630         if (!is_device_supported(dev, &rte_i40e_pmd))
10631                 return -ENOTSUP;
10632
10633         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10634
10635         if (vf_id >= pf->vf_num || !pf->vfs) {
10636                 PMD_DRV_LOG(ERR, "Invalid argument.");
10637                 return -EINVAL;
10638         }
10639
10640         vsi = pf->vfs[vf_id].vsi;
10641         if (!vsi) {
10642                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10643                 return -EINVAL;
10644         }
10645
10646         /* Check if it has been already on or off */
10647         if (vsi->vlan_anti_spoof_on == on)
10648                 return 0; /* already on or off */
10649
10650         vsi->vlan_anti_spoof_on = on;
10651         if (!vsi->vlan_filter_on) {
10652                 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10653                 if (ret) {
10654                         PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10655                         return -ENOTSUP;
10656                 }
10657         }
10658
10659         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10660         if (on)
10661                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10662         else
10663                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10664
10665         memset(&ctxt, 0, sizeof(ctxt));
10666         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10667         ctxt.seid = vsi->seid;
10668
10669         hw = I40E_VSI_TO_HW(vsi);
10670         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10671         if (ret != I40E_SUCCESS) {
10672                 ret = -ENOTSUP;
10673                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10674         }
10675
10676         return ret;
10677 }
10678
10679 static int
10680 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10681 {
10682         struct i40e_mac_filter *f;
10683         struct i40e_macvlan_filter *mv_f;
10684         int i, vlan_num;
10685         enum rte_mac_filter_type filter_type;
10686         int ret = I40E_SUCCESS;
10687         void *temp;
10688
10689         /* remove all the MACs */
10690         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10691                 vlan_num = vsi->vlan_num;
10692                 filter_type = f->mac_info.filter_type;
10693                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10694                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10695                         if (vlan_num == 0) {
10696                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10697                                 return I40E_ERR_PARAM;
10698                         }
10699                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10700                            filter_type == RTE_MAC_HASH_MATCH)
10701                         vlan_num = 1;
10702
10703                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10704                 if (!mv_f) {
10705                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10706                         return I40E_ERR_NO_MEMORY;
10707                 }
10708
10709                 for (i = 0; i < vlan_num; i++) {
10710                         mv_f[i].filter_type = filter_type;
10711                         (void)rte_memcpy(&mv_f[i].macaddr,
10712                                          &f->mac_info.mac_addr,
10713                                          ETH_ADDR_LEN);
10714                 }
10715                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10716                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10717                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10718                                                          &f->mac_info.mac_addr);
10719                         if (ret != I40E_SUCCESS) {
10720                                 rte_free(mv_f);
10721                                 return ret;
10722                         }
10723                 }
10724
10725                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10726                 if (ret != I40E_SUCCESS) {
10727                         rte_free(mv_f);
10728                         return ret;
10729                 }
10730
10731                 rte_free(mv_f);
10732                 ret = I40E_SUCCESS;
10733         }
10734
10735         return ret;
10736 }
10737
10738 static int
10739 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10740 {
10741         struct i40e_mac_filter *f;
10742         struct i40e_macvlan_filter *mv_f;
10743         int i, vlan_num = 0;
10744         int ret = I40E_SUCCESS;
10745         void *temp;
10746
10747         /* restore all the MACs */
10748         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10749                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10750                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10751                         /**
10752                          * If vlan_num is 0, that's the first time to add mac,
10753                          * set mask for vlan_id 0.
10754                          */
10755                         if (vsi->vlan_num == 0) {
10756                                 i40e_set_vlan_filter(vsi, 0, 1);
10757                                 vsi->vlan_num = 1;
10758                         }
10759                         vlan_num = vsi->vlan_num;
10760                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10761                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10762                         vlan_num = 1;
10763
10764                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10765                 if (!mv_f) {
10766                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10767                         return I40E_ERR_NO_MEMORY;
10768                 }
10769
10770                 for (i = 0; i < vlan_num; i++) {
10771                         mv_f[i].filter_type = f->mac_info.filter_type;
10772                         (void)rte_memcpy(&mv_f[i].macaddr,
10773                                          &f->mac_info.mac_addr,
10774                                          ETH_ADDR_LEN);
10775                 }
10776
10777                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10778                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10779                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10780                                                          &f->mac_info.mac_addr);
10781                         if (ret != I40E_SUCCESS) {
10782                                 rte_free(mv_f);
10783                                 return ret;
10784                         }
10785                 }
10786
10787                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10788                 if (ret != I40E_SUCCESS) {
10789                         rte_free(mv_f);
10790                         return ret;
10791                 }
10792
10793                 rte_free(mv_f);
10794                 ret = I40E_SUCCESS;
10795         }
10796
10797         return ret;
10798 }
10799
10800 static int
10801 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10802 {
10803         struct i40e_vsi_context ctxt;
10804         struct i40e_hw *hw;
10805         int ret;
10806
10807         if (!vsi)
10808                 return -EINVAL;
10809
10810         hw = I40E_VSI_TO_HW(vsi);
10811
10812         /* Use the FW API if FW >= v5.0 */
10813         if (hw->aq.fw_maj_ver < 5) {
10814                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10815                 return -ENOTSUP;
10816         }
10817
10818         /* Check if it has been already on or off */
10819         if (vsi->info.valid_sections &
10820                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10821                 if (on) {
10822                         if ((vsi->info.switch_id &
10823                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10824                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10825                                 return 0; /* already on */
10826                 } else {
10827                         if ((vsi->info.switch_id &
10828                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10829                                 return 0; /* already off */
10830                 }
10831         }
10832
10833         /* remove all the MAC and VLAN first */
10834         ret = i40e_vsi_rm_mac_filter(vsi);
10835         if (ret) {
10836                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10837                 return ret;
10838         }
10839         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10840                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10841                 if (ret) {
10842                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10843                         return ret;
10844                 }
10845         }
10846
10847         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10848         if (on)
10849                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10850         else
10851                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10852
10853         memset(&ctxt, 0, sizeof(ctxt));
10854         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10855         ctxt.seid = vsi->seid;
10856
10857         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10858         if (ret != I40E_SUCCESS) {
10859                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10860                 return ret;
10861         }
10862
10863         /* add all the MAC and VLAN back */
10864         ret = i40e_vsi_restore_mac_filter(vsi);
10865         if (ret)
10866                 return ret;
10867         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10868                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10869                 if (ret)
10870                         return ret;
10871         }
10872
10873         return ret;
10874 }
10875
10876 int
10877 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10878 {
10879         struct rte_eth_dev *dev;
10880         struct i40e_pf *pf;
10881         struct i40e_pf_vf *vf;
10882         struct i40e_vsi *vsi;
10883         uint16_t vf_id;
10884         int ret;
10885
10886         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10887
10888         dev = &rte_eth_devices[port];
10889
10890         if (!is_device_supported(dev, &rte_i40e_pmd))
10891                 return -ENOTSUP;
10892
10893         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10894
10895         /* setup PF TX loopback */
10896         vsi = pf->main_vsi;
10897         ret = i40e_vsi_set_tx_loopback(vsi, on);
10898         if (ret)
10899                 return -ENOTSUP;
10900
10901         /* setup TX loopback for all the VFs */
10902         if (!pf->vfs) {
10903                 /* if no VF, do nothing. */
10904                 return 0;
10905         }
10906
10907         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10908                 vf = &pf->vfs[vf_id];
10909                 vsi = vf->vsi;
10910
10911                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10912                 if (ret)
10913                         return -ENOTSUP;
10914         }
10915
10916         return ret;
10917 }
10918
10919 int
10920 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10921 {
10922         struct rte_eth_dev *dev;
10923         struct i40e_pf *pf;
10924         struct i40e_vsi *vsi;
10925         struct i40e_hw *hw;
10926         int ret;
10927
10928         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10929
10930         dev = &rte_eth_devices[port];
10931
10932         if (!is_device_supported(dev, &rte_i40e_pmd))
10933                 return -ENOTSUP;
10934
10935         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10936
10937         if (vf_id >= pf->vf_num || !pf->vfs) {
10938                 PMD_DRV_LOG(ERR, "Invalid argument.");
10939                 return -EINVAL;
10940         }
10941
10942         vsi = pf->vfs[vf_id].vsi;
10943         if (!vsi) {
10944                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10945                 return -EINVAL;
10946         }
10947
10948         hw = I40E_VSI_TO_HW(vsi);
10949
10950         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10951                                                   on, NULL, true);
10952         if (ret != I40E_SUCCESS) {
10953                 ret = -ENOTSUP;
10954                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10955         }
10956
10957         return ret;
10958 }
10959
10960 int
10961 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10962 {
10963         struct rte_eth_dev *dev;
10964         struct i40e_pf *pf;
10965         struct i40e_vsi *vsi;
10966         struct i40e_hw *hw;
10967         int ret;
10968
10969         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10970
10971         dev = &rte_eth_devices[port];
10972
10973         if (!is_device_supported(dev, &rte_i40e_pmd))
10974                 return -ENOTSUP;
10975
10976         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10977
10978         if (vf_id >= pf->vf_num || !pf->vfs) {
10979                 PMD_DRV_LOG(ERR, "Invalid argument.");
10980                 return -EINVAL;
10981         }
10982
10983         vsi = pf->vfs[vf_id].vsi;
10984         if (!vsi) {
10985                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10986                 return -EINVAL;
10987         }
10988
10989         hw = I40E_VSI_TO_HW(vsi);
10990
10991         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10992                                                     on, NULL);
10993         if (ret != I40E_SUCCESS) {
10994                 ret = -ENOTSUP;
10995                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10996         }
10997
10998         return ret;
10999 }
11000
11001 int
11002 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11003                              struct ether_addr *mac_addr)
11004 {
11005         struct i40e_mac_filter *f;
11006         struct rte_eth_dev *dev;
11007         struct i40e_pf_vf *vf;
11008         struct i40e_vsi *vsi;
11009         struct i40e_pf *pf;
11010         void *temp;
11011
11012         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11013                 return -EINVAL;
11014
11015         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11016
11017         dev = &rte_eth_devices[port];
11018
11019         if (!is_device_supported(dev, &rte_i40e_pmd))
11020                 return -ENOTSUP;
11021
11022         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11023
11024         if (vf_id >= pf->vf_num || !pf->vfs)
11025                 return -EINVAL;
11026
11027         vf = &pf->vfs[vf_id];
11028         vsi = vf->vsi;
11029         if (!vsi) {
11030                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11031                 return -EINVAL;
11032         }
11033
11034         ether_addr_copy(mac_addr, &vf->mac_addr);
11035
11036         /* Remove all existing mac */
11037         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11038                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11039
11040         return 0;
11041 }
11042
11043 /* Set vlan strip on/off for specific VF from host */
11044 int
11045 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11046 {
11047         struct rte_eth_dev *dev;
11048         struct i40e_pf *pf;
11049         struct i40e_vsi *vsi;
11050         int ret;
11051
11052         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11053
11054         dev = &rte_eth_devices[port];
11055
11056         if (!is_device_supported(dev, &rte_i40e_pmd))
11057                 return -ENOTSUP;
11058
11059         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11060
11061         if (vf_id >= pf->vf_num || !pf->vfs) {
11062                 PMD_DRV_LOG(ERR, "Invalid argument.");
11063                 return -EINVAL;
11064         }
11065
11066         vsi = pf->vfs[vf_id].vsi;
11067
11068         if (!vsi)
11069                 return -EINVAL;
11070
11071         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11072         if (ret != I40E_SUCCESS) {
11073                 ret = -ENOTSUP;
11074                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11075         }
11076
11077         return ret;
11078 }
11079
11080 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11081                                     uint16_t vlan_id)
11082 {
11083         struct rte_eth_dev *dev;
11084         struct i40e_pf *pf;
11085         struct i40e_hw *hw;
11086         struct i40e_vsi *vsi;
11087         struct i40e_vsi_context ctxt;
11088         int ret;
11089
11090         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11091
11092         if (vlan_id > ETHER_MAX_VLAN_ID) {
11093                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11094                 return -EINVAL;
11095         }
11096
11097         dev = &rte_eth_devices[port];
11098
11099         if (!is_device_supported(dev, &rte_i40e_pmd))
11100                 return -ENOTSUP;
11101
11102         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11103         hw = I40E_PF_TO_HW(pf);
11104
11105         /**
11106          * return -ENODEV if SRIOV not enabled, VF number not configured
11107          * or no queue assigned.
11108          */
11109         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11110             pf->vf_nb_qps == 0)
11111                 return -ENODEV;
11112
11113         if (vf_id >= pf->vf_num || !pf->vfs) {
11114                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11115                 return -EINVAL;
11116         }
11117
11118         vsi = pf->vfs[vf_id].vsi;
11119         if (!vsi) {
11120                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11121                 return -EINVAL;
11122         }
11123
11124         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11125         vsi->info.pvid = vlan_id;
11126         if (vlan_id > 0)
11127                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11128         else
11129                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11130
11131         memset(&ctxt, 0, sizeof(ctxt));
11132         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11133         ctxt.seid = vsi->seid;
11134
11135         hw = I40E_VSI_TO_HW(vsi);
11136         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11137         if (ret != I40E_SUCCESS) {
11138                 ret = -ENOTSUP;
11139                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11140         }
11141
11142         return ret;
11143 }
11144
11145 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11146                                   uint8_t on)
11147 {
11148         struct rte_eth_dev *dev;
11149         struct i40e_pf *pf;
11150         struct i40e_vsi *vsi;
11151         struct i40e_hw *hw;
11152         struct i40e_mac_filter_info filter;
11153         struct ether_addr broadcast = {
11154                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11155         int ret;
11156
11157         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11158
11159         if (on > 1) {
11160                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11161                 return -EINVAL;
11162         }
11163
11164         dev = &rte_eth_devices[port];
11165
11166         if (!is_device_supported(dev, &rte_i40e_pmd))
11167                 return -ENOTSUP;
11168
11169         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11170         hw = I40E_PF_TO_HW(pf);
11171
11172         if (vf_id >= pf->vf_num || !pf->vfs) {
11173                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11174                 return -EINVAL;
11175         }
11176
11177         /**
11178          * return -ENODEV if SRIOV not enabled, VF number not configured
11179          * or no queue assigned.
11180          */
11181         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11182             pf->vf_nb_qps == 0) {
11183                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11184                 return -ENODEV;
11185         }
11186
11187         vsi = pf->vfs[vf_id].vsi;
11188         if (!vsi) {
11189                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11190                 return -EINVAL;
11191         }
11192
11193         if (on) {
11194                 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11195                 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11196                 ret = i40e_vsi_add_mac(vsi, &filter);
11197         } else {
11198                 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11199         }
11200
11201         if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11202                 ret = -ENOTSUP;
11203                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11204         } else {
11205                 ret = 0;
11206         }
11207
11208         return ret;
11209 }
11210
11211 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11212 {
11213         struct rte_eth_dev *dev;
11214         struct i40e_pf *pf;
11215         struct i40e_hw *hw;
11216         struct i40e_vsi *vsi;
11217         struct i40e_vsi_context ctxt;
11218         int ret;
11219
11220         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11221
11222         if (on > 1) {
11223                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11224                 return -EINVAL;
11225         }
11226
11227         dev = &rte_eth_devices[port];
11228
11229         if (!is_device_supported(dev, &rte_i40e_pmd))
11230                 return -ENOTSUP;
11231
11232         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11233         hw = I40E_PF_TO_HW(pf);
11234
11235         /**
11236          * return -ENODEV if SRIOV not enabled, VF number not configured
11237          * or no queue assigned.
11238          */
11239         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11240             pf->vf_nb_qps == 0) {
11241                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11242                 return -ENODEV;
11243         }
11244
11245         if (vf_id >= pf->vf_num || !pf->vfs) {
11246                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11247                 return -EINVAL;
11248         }
11249
11250         vsi = pf->vfs[vf_id].vsi;
11251         if (!vsi) {
11252                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11253                 return -EINVAL;
11254         }
11255
11256         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11257         if (on) {
11258                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11259                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11260         } else {
11261                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11262                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11263         }
11264
11265         memset(&ctxt, 0, sizeof(ctxt));
11266         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11267         ctxt.seid = vsi->seid;
11268
11269         hw = I40E_VSI_TO_HW(vsi);
11270         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11271         if (ret != I40E_SUCCESS) {
11272                 ret = -ENOTSUP;
11273                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11274         }
11275
11276         return ret;
11277 }
11278
11279 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11280                                     uint64_t vf_mask, uint8_t on)
11281 {
11282         struct rte_eth_dev *dev;
11283         struct i40e_pf *pf;
11284         struct i40e_hw *hw;
11285         struct i40e_vsi *vsi;
11286         uint16_t vf_idx;
11287         int ret = I40E_SUCCESS;
11288
11289         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11290
11291         dev = &rte_eth_devices[port];
11292
11293         if (!is_device_supported(dev, &rte_i40e_pmd))
11294                 return -ENOTSUP;
11295
11296         if (vlan_id > ETHER_MAX_VLAN_ID) {
11297                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11298                 return -EINVAL;
11299         }
11300
11301         if (vf_mask == 0) {
11302                 PMD_DRV_LOG(ERR, "No VF.");
11303                 return -EINVAL;
11304         }
11305
11306         if (on > 1) {
11307                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11308                 return -EINVAL;
11309         }
11310
11311         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11312         hw = I40E_PF_TO_HW(pf);
11313
11314         /**
11315          * return -ENODEV if SRIOV not enabled, VF number not configured
11316          * or no queue assigned.
11317          */
11318         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11319             pf->vf_nb_qps == 0) {
11320                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11321                 return -ENODEV;
11322         }
11323
11324         for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11325                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11326                         vsi = pf->vfs[vf_idx].vsi;
11327                         if (on) {
11328                                 if (!vsi->vlan_filter_on) {
11329                                         vsi->vlan_filter_on = true;
11330                                         if (!vsi->vlan_anti_spoof_on)
11331                                                 i40e_add_rm_all_vlan_filter(
11332                                                         vsi, true);
11333                                 }
11334                                 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11335                                                              false, NULL);
11336                                 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11337                         } else {
11338                                 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11339                         }
11340                 }
11341         }
11342
11343         if (ret != I40E_SUCCESS) {
11344                 ret = -ENOTSUP;
11345                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11346         }
11347
11348         return ret;
11349 }
11350
11351 int
11352 rte_pmd_i40e_get_vf_stats(uint8_t port,
11353                           uint16_t vf_id,
11354                           struct rte_eth_stats *stats)
11355 {
11356         struct rte_eth_dev *dev;
11357         struct i40e_pf *pf;
11358         struct i40e_vsi *vsi;
11359
11360         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11361
11362         dev = &rte_eth_devices[port];
11363
11364         if (!is_device_supported(dev, &rte_i40e_pmd))
11365                 return -ENOTSUP;
11366
11367         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11368
11369         if (vf_id >= pf->vf_num || !pf->vfs) {
11370                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11371                 return -EINVAL;
11372         }
11373
11374         vsi = pf->vfs[vf_id].vsi;
11375         if (!vsi) {
11376                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11377                 return -EINVAL;
11378         }
11379
11380         i40e_update_vsi_stats(vsi);
11381
11382         stats->ipackets = vsi->eth_stats.rx_unicast +
11383                         vsi->eth_stats.rx_multicast +
11384                         vsi->eth_stats.rx_broadcast;
11385         stats->opackets = vsi->eth_stats.tx_unicast +
11386                         vsi->eth_stats.tx_multicast +
11387                         vsi->eth_stats.tx_broadcast;
11388         stats->ibytes   = vsi->eth_stats.rx_bytes;
11389         stats->obytes   = vsi->eth_stats.tx_bytes;
11390         stats->ierrors  = vsi->eth_stats.rx_discards;
11391         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11392
11393         return 0;
11394 }
11395
11396 int
11397 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11398                             uint16_t vf_id)
11399 {
11400         struct rte_eth_dev *dev;
11401         struct i40e_pf *pf;
11402         struct i40e_vsi *vsi;
11403
11404         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11405
11406         dev = &rte_eth_devices[port];
11407
11408         if (!is_device_supported(dev, &rte_i40e_pmd))
11409                 return -ENOTSUP;
11410
11411         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11412
11413         if (vf_id >= pf->vf_num || !pf->vfs) {
11414                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11415                 return -EINVAL;
11416         }
11417
11418         vsi = pf->vfs[vf_id].vsi;
11419         if (!vsi) {
11420                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11421                 return -EINVAL;
11422         }
11423
11424         vsi->offset_loaded = false;
11425         i40e_update_vsi_stats(vsi);
11426
11427         return 0;
11428 }
11429
11430 int
11431 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11432 {
11433         struct rte_eth_dev *dev;
11434         struct i40e_pf *pf;
11435         struct i40e_vsi *vsi;
11436         struct i40e_hw *hw;
11437         int ret = 0;
11438         int i;
11439
11440         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11441
11442         dev = &rte_eth_devices[port];
11443
11444         if (!is_device_supported(dev, &rte_i40e_pmd))
11445                 return -ENOTSUP;
11446
11447         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11448
11449         if (vf_id >= pf->vf_num || !pf->vfs) {
11450                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11451                 return -EINVAL;
11452         }
11453
11454         vsi = pf->vfs[vf_id].vsi;
11455         if (!vsi) {
11456                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11457                 return -EINVAL;
11458         }
11459
11460         if (bw > I40E_QOS_BW_MAX) {
11461                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11462                             I40E_QOS_BW_MAX);
11463                 return -EINVAL;
11464         }
11465
11466         if (bw % I40E_QOS_BW_GRANULARITY) {
11467                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11468                             I40E_QOS_BW_GRANULARITY);
11469                 return -EINVAL;
11470         }
11471
11472         bw /= I40E_QOS_BW_GRANULARITY;
11473
11474         hw = I40E_VSI_TO_HW(vsi);
11475
11476         /* No change. */
11477         if (bw == vsi->bw_info.bw_limit) {
11478                 PMD_DRV_LOG(INFO,
11479                             "No change for VF max bandwidth. Nothing to do.");
11480                 return 0;
11481         }
11482
11483         /**
11484          * VF bandwidth limitation and TC bandwidth limitation cannot be
11485          * enabled in parallel, quit if TC bandwidth limitation is enabled.
11486          *
11487          * If bw is 0, means disable bandwidth limitation. Then no need to
11488          * check TC bandwidth limitation.
11489          */
11490         if (bw) {
11491                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11492                         if ((vsi->enabled_tc & BIT_ULL(i)) &&
11493                             vsi->bw_info.bw_ets_credits[i])
11494                                 break;
11495                 }
11496                 if (i != I40E_MAX_TRAFFIC_CLASS) {
11497                         PMD_DRV_LOG(ERR,
11498                                     "TC max bandwidth has been set on this VF,"
11499                                     " please disable it first.");
11500                         return -EINVAL;
11501                 }
11502         }
11503
11504         ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11505         if (ret) {
11506                 PMD_DRV_LOG(ERR,
11507                             "Failed to set VF %d bandwidth, err(%d).",
11508                             vf_id, ret);
11509                 return -EINVAL;
11510         }
11511
11512         /* Store the configuration. */
11513         vsi->bw_info.bw_limit = (uint16_t)bw;
11514         vsi->bw_info.bw_max = 0;
11515
11516         return 0;
11517 }
11518
11519 int
11520 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11521                                 uint8_t tc_num, uint8_t *bw_weight)
11522 {
11523         struct rte_eth_dev *dev;
11524         struct i40e_pf *pf;
11525         struct i40e_vsi *vsi;
11526         struct i40e_hw *hw;
11527         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11528         int ret = 0;
11529         int i, j;
11530         uint16_t sum;
11531         bool b_change = false;
11532
11533         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11534
11535         dev = &rte_eth_devices[port];
11536
11537         if (!is_device_supported(dev, &rte_i40e_pmd))
11538                 return -ENOTSUP;
11539
11540         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11541
11542         if (vf_id >= pf->vf_num || !pf->vfs) {
11543                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11544                 return -EINVAL;
11545         }
11546
11547         vsi = pf->vfs[vf_id].vsi;
11548         if (!vsi) {
11549                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11550                 return -EINVAL;
11551         }
11552
11553         if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11554                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11555                             I40E_MAX_TRAFFIC_CLASS);
11556                 return -EINVAL;
11557         }
11558
11559         sum = 0;
11560         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11561                 if (vsi->enabled_tc & BIT_ULL(i))
11562                         sum++;
11563         }
11564         if (sum != tc_num) {
11565                 PMD_DRV_LOG(ERR,
11566                             "Weight should be set for all %d enabled TCs.",
11567                             sum);
11568                 return -EINVAL;
11569         }
11570
11571         sum = 0;
11572         for (i = 0; i < tc_num; i++) {
11573                 if (!bw_weight[i]) {
11574                         PMD_DRV_LOG(ERR,
11575                                     "The weight should be 1 at least.");
11576                         return -EINVAL;
11577                 }
11578                 sum += bw_weight[i];
11579         }
11580         if (sum != 100) {
11581                 PMD_DRV_LOG(ERR,
11582                             "The summary of the TC weight should be 100.");
11583                 return -EINVAL;
11584         }
11585
11586         /**
11587          * Create the configuration for all the TCs.
11588          */
11589         memset(&tc_bw, 0, sizeof(tc_bw));
11590         tc_bw.tc_valid_bits = vsi->enabled_tc;
11591         j = 0;
11592         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11593                 if (vsi->enabled_tc & BIT_ULL(i)) {
11594                         if (bw_weight[j] !=
11595                                 vsi->bw_info.bw_ets_share_credits[i])
11596                                 b_change = true;
11597
11598                         tc_bw.tc_bw_credits[i] = bw_weight[j];
11599                         j++;
11600                 }
11601         }
11602
11603         /* No change. */
11604         if (!b_change) {
11605                 PMD_DRV_LOG(INFO,
11606                             "No change for TC allocated bandwidth."
11607                             " Nothing to do.");
11608                 return 0;
11609         }
11610
11611         hw = I40E_VSI_TO_HW(vsi);
11612
11613         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11614         if (ret) {
11615                 PMD_DRV_LOG(ERR,
11616                             "Failed to set VF %d TC bandwidth weight, err(%d).",
11617                             vf_id, ret);
11618                 return -EINVAL;
11619         }
11620
11621         /* Store the configuration. */
11622         j = 0;
11623         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11624                 if (vsi->enabled_tc & BIT_ULL(i)) {
11625                         vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11626                         j++;
11627                 }
11628         }
11629
11630         return 0;
11631 }
11632
11633 int
11634 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11635                               uint8_t tc_no, uint32_t bw)
11636 {
11637         struct rte_eth_dev *dev;
11638         struct i40e_pf *pf;
11639         struct i40e_vsi *vsi;
11640         struct i40e_hw *hw;
11641         struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11642         int ret = 0;
11643         int i;
11644
11645         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11646
11647         dev = &rte_eth_devices[port];
11648
11649         if (!is_device_supported(dev, &rte_i40e_pmd))
11650                 return -ENOTSUP;
11651
11652         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11653
11654         if (vf_id >= pf->vf_num || !pf->vfs) {
11655                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11656                 return -EINVAL;
11657         }
11658
11659         vsi = pf->vfs[vf_id].vsi;
11660         if (!vsi) {
11661                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11662                 return -EINVAL;
11663         }
11664
11665         if (bw > I40E_QOS_BW_MAX) {
11666                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11667                             I40E_QOS_BW_MAX);
11668                 return -EINVAL;
11669         }
11670
11671         if (bw % I40E_QOS_BW_GRANULARITY) {
11672                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11673                             I40E_QOS_BW_GRANULARITY);
11674                 return -EINVAL;
11675         }
11676
11677         bw /= I40E_QOS_BW_GRANULARITY;
11678
11679         if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11680                 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11681                             I40E_MAX_TRAFFIC_CLASS);
11682                 return -EINVAL;
11683         }
11684
11685         hw = I40E_VSI_TO_HW(vsi);
11686
11687         if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11688                 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11689                             vf_id, tc_no);
11690                 return -EINVAL;
11691         }
11692
11693         /* No change. */
11694         if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11695                 PMD_DRV_LOG(INFO,
11696                             "No change for TC max bandwidth. Nothing to do.");
11697                 return 0;
11698         }
11699
11700         /**
11701          * VF bandwidth limitation and TC bandwidth limitation cannot be
11702          * enabled in parallel, disable VF bandwidth limitation if it's
11703          * enabled.
11704          * If bw is 0, means disable bandwidth limitation. Then no need to
11705          * care about VF bandwidth limitation configuration.
11706          */
11707         if (bw && vsi->bw_info.bw_limit) {
11708                 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11709                 if (ret) {
11710                         PMD_DRV_LOG(ERR,
11711                                     "Failed to disable VF(%d)"
11712                                     " bandwidth limitation, err(%d).",
11713                                     vf_id, ret);
11714                         return -EINVAL;
11715                 }
11716
11717                 PMD_DRV_LOG(INFO,
11718                             "VF max bandwidth is disabled according"
11719                             " to TC max bandwidth setting.");
11720         }
11721
11722         /**
11723          * Get all the TCs' info to create a whole picture.
11724          * Because the incremental change isn't permitted.
11725          */
11726         memset(&tc_bw, 0, sizeof(tc_bw));
11727         tc_bw.tc_valid_bits = vsi->enabled_tc;
11728         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11729                 if (vsi->enabled_tc & BIT_ULL(i)) {
11730                         tc_bw.tc_bw_credits[i] =
11731                                 rte_cpu_to_le_16(
11732                                         vsi->bw_info.bw_ets_credits[i]);
11733                 }
11734         }
11735         tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11736
11737         ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11738         if (ret) {
11739                 PMD_DRV_LOG(ERR,
11740                             "Failed to set VF %d TC %d max bandwidth, err(%d).",
11741                             vf_id, tc_no, ret);
11742                 return -EINVAL;
11743         }
11744
11745         /* Store the configuration. */
11746         vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
11747
11748         return 0;
11749 }
11750
11751 int
11752 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
11753 {
11754         struct rte_eth_dev *dev;
11755         struct i40e_pf *pf;
11756         struct i40e_vsi *vsi;
11757         struct i40e_veb *veb;
11758         struct i40e_hw *hw;
11759         struct i40e_aqc_configure_switching_comp_ets_data ets_data;
11760         int i;
11761         int ret;
11762
11763         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11764
11765         dev = &rte_eth_devices[port];
11766
11767         if (!is_device_supported(dev, &rte_i40e_pmd))
11768                 return -ENOTSUP;
11769
11770         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11771
11772         vsi = pf->main_vsi;
11773         if (!vsi) {
11774                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11775                 return -EINVAL;
11776         }
11777
11778         veb = vsi->veb;
11779         if (!veb) {
11780                 PMD_DRV_LOG(ERR, "Invalid VEB.");
11781                 return -EINVAL;
11782         }
11783
11784         if ((tc_map & veb->enabled_tc) != tc_map) {
11785                 PMD_DRV_LOG(ERR,
11786                             "TC bitmap isn't the subset of enabled TCs 0x%x.",
11787                             veb->enabled_tc);
11788                 return -EINVAL;
11789         }
11790
11791         if (tc_map == veb->strict_prio_tc) {
11792                 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
11793                 return 0;
11794         }
11795
11796         hw = I40E_VSI_TO_HW(vsi);
11797
11798         /* Disable DCBx if it's the first time to set strict priority. */
11799         if (!veb->strict_prio_tc) {
11800                 ret = i40e_aq_stop_lldp(hw, true, NULL);
11801                 if (ret)
11802                         PMD_DRV_LOG(INFO,
11803                                     "Failed to disable DCBx as it's already"
11804                                     " disabled.");
11805                 else
11806                         PMD_DRV_LOG(INFO,
11807                                     "DCBx is disabled according to strict"
11808                                     " priority setting.");
11809         }
11810
11811         memset(&ets_data, 0, sizeof(ets_data));
11812         ets_data.tc_valid_bits = veb->enabled_tc;
11813         ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
11814         ets_data.tc_strict_priority_flags = tc_map;
11815         /* Get all TCs' bandwidth. */
11816         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11817                 if (veb->enabled_tc & BIT_ULL(i)) {
11818                         /* For rubust, if bandwidth is 0, use 1 instead. */
11819                         if (veb->bw_info.bw_ets_share_credits[i])
11820                                 ets_data.tc_bw_share_credits[i] =
11821                                         veb->bw_info.bw_ets_share_credits[i];
11822                         else
11823                                 ets_data.tc_bw_share_credits[i] =
11824                                         I40E_QOS_BW_WEIGHT_MIN;
11825                 }
11826         }
11827
11828         if (!veb->strict_prio_tc)
11829                 ret = i40e_aq_config_switch_comp_ets(
11830                         hw, veb->uplink_seid,
11831                         &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
11832                         NULL);
11833         else if (tc_map)
11834                 ret = i40e_aq_config_switch_comp_ets(
11835                         hw, veb->uplink_seid,
11836                         &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
11837                         NULL);
11838         else
11839                 ret = i40e_aq_config_switch_comp_ets(
11840                         hw, veb->uplink_seid,
11841                         &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
11842                         NULL);
11843
11844         if (ret) {
11845                 PMD_DRV_LOG(ERR,
11846                             "Failed to set TCs' strict priority mode."
11847                             " err (%d)", ret);
11848                 return -EINVAL;
11849         }
11850
11851         veb->strict_prio_tc = tc_map;
11852
11853         /* Enable DCBx again, if all the TCs' strict priority disabled. */
11854         if (!tc_map) {
11855                 ret = i40e_aq_start_lldp(hw, NULL);
11856                 if (ret) {
11857                         PMD_DRV_LOG(ERR,
11858                                     "Failed to enable DCBx, err(%d).", ret);
11859                         return -EINVAL;
11860                 }
11861
11862                 PMD_DRV_LOG(INFO,
11863                             "DCBx is enabled again according to strict"
11864                             " priority setting.");
11865         }
11866
11867         return ret;
11868 }