1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define I40E_CLEAR_PXE_WAIT_MS 200
50 /* Maximun number of capability elements */
51 #define I40E_MAX_CAP_ELE_NUM 128
53 /* Wait count and interval */
54 #define I40E_CHK_Q_ENA_COUNT 1000
55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
57 /* Maximun number of VSI */
58 #define I40E_MAX_NUM_VSIS (384UL)
60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
62 /* Flow control default timer */
63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
65 /* Flow control enable fwd bit */
66 #define I40E_PRTMAC_FWD_CTRL 0x00000001
68 /* Receive Packet Buffer size */
69 #define I40E_RXPBSIZE (968 * 1024)
72 #define I40E_KILOSHIFT 10
74 /* Flow control default high water */
75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Flow control default low water */
78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
80 /* Receive Average Packet Size in Byte*/
81 #define I40E_PACKET_AVERAGE_SIZE 128
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
95 #define I40E_FLOW_TYPES ( \
96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
108 /* Additional timesync values. */
109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
112 #define I40E_PRTTSYN_TSYNENA 0x80000000
113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
117 * Below are values for writing un-exposed registers suggested
120 /* Destination MAC address */
121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
122 /* Source MAC address */
123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
128 /* Single VLAN tag in the inner L2 header */
129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
130 /* Source IPv4 address */
131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
132 /* Destination IPv4 address */
133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
134 /* Source IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
136 /* Destination IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
138 /* IPv4 Protocol for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
140 /* IPv4 Time to Live for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
142 /* IPv4 Type of Service (TOS) */
143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
146 /* IPv4 Time to Live */
147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
148 /* Source IPv6 address */
149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
150 /* Destination IPv6 address */
151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
152 /* IPv6 Traffic Class (TC) */
153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
154 /* IPv6 Next Header */
155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
160 /* Destination L4 port */
161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
162 /* SCTP verification tag */
163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
166 /* Source port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
168 /* Destination port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
170 /* UDP Tunneling ID, NVGRE/GRE key */
171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
172 /* Last ether type */
173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
174 /* Tunneling outer destination IPv4 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
176 /* Tunneling outer destination IPv6 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
178 /* 1st word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
180 /* 2nd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
182 /* 3rd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
184 /* 4th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
186 /* 5th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
188 /* 6th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
190 /* 7th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
192 /* 8th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
194 /* all 8 words flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
198 #define I40E_TRANSLATE_INSET 0
199 #define I40E_TRANSLATE_REG 1
201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
208 /* PCI offset for querying capability */
209 #define PCI_DEV_CAP_REG 0xA4
210 /* PCI offset for enabling/disabling Extended Tag */
211 #define PCI_DEV_CTRL_REG 0xA8
212 /* Bit mask of Extended Tag capability */
213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
214 /* Bit shift of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
216 /* Bit mask of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
221 static int i40e_dev_configure(struct rte_eth_dev *dev);
222 static int i40e_dev_start(struct rte_eth_dev *dev);
223 static void i40e_dev_stop(struct rte_eth_dev *dev);
224 static void i40e_dev_close(struct rte_eth_dev *dev);
225 static int i40e_dev_reset(struct rte_eth_dev *dev);
226 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
233 struct rte_eth_stats *stats);
234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
235 struct rte_eth_xstat *xstats, unsigned n);
236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
237 struct rte_eth_xstat_name *xstats_names,
239 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
240 static int i40e_fw_version_get(struct rte_eth_dev *dev,
241 char *fw_version, size_t fw_size);
242 static int i40e_dev_info_get(struct rte_eth_dev *dev,
243 struct rte_eth_dev_info *dev_info);
244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
248 enum rte_vlan_type vlan_type,
250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
255 static int i40e_dev_led_on(struct rte_eth_dev *dev);
256 static int i40e_dev_led_off(struct rte_eth_dev *dev);
257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
258 struct rte_eth_fc_conf *fc_conf);
259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_pfc_conf *pfc_conf);
263 static int i40e_macaddr_add(struct rte_eth_dev *dev,
264 struct rte_ether_addr *mac_addr,
267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
269 struct rte_eth_rss_reta_entry64 *reta_conf,
271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
272 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_get_cap(struct i40e_hw *hw);
276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
277 static int i40e_pf_setup(struct i40e_pf *pf);
278 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
279 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
280 static int i40e_dcb_setup(struct rte_eth_dev *dev);
281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
282 bool offset_loaded, uint64_t *offset, uint64_t *stat);
283 static void i40e_stat_update_48(struct i40e_hw *hw,
289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
290 static void i40e_dev_interrupt_handler(void *param);
291 static void i40e_dev_alarm_handler(void *param);
292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
293 uint32_t base, uint32_t num);
294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
300 static int i40e_veb_release(struct i40e_veb *veb);
301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
302 struct i40e_vsi *vsi);
303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
306 struct i40e_macvlan_filter *mv_f,
309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
311 struct rte_eth_rss_conf *rss_conf);
312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
315 struct rte_eth_udp_tunnel *udp_tunnel);
316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
327 struct rte_eth_dcb_info *dcb_info);
328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
329 static void i40e_configure_registers(struct i40e_hw *hw);
330 static void i40e_hw_init(struct rte_eth_dev *dev);
331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
339 struct rte_eth_mirror_conf *mirror_conf,
340 uint8_t sw_id, uint8_t on);
341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
355 struct timespec *timestamp);
356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
357 const struct timespec *timestamp);
359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
364 static int i40e_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
370 struct rte_dev_eeprom_info *eeprom);
372 static int i40e_get_module_info(struct rte_eth_dev *dev,
373 struct rte_eth_dev_module_info *modinfo);
374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *info);
377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
378 struct rte_ether_addr *mac_addr);
380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
382 static int i40e_ethertype_filter_convert(
383 const struct rte_eth_ethertype_filter *input,
384 struct i40e_ethertype_filter *filter);
385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
386 struct i40e_ethertype_filter *filter);
388 static int i40e_tunnel_filter_convert(
389 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
390 struct i40e_tunnel_filter *tunnel_filter);
391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
392 struct i40e_tunnel_filter *tunnel_filter);
393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
397 static void i40e_filter_restore(struct i40e_pf *pf);
398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
400 int i40e_logtype_init;
401 int i40e_logtype_driver;
403 static const char *const valid_keys[] = {
404 ETH_I40E_FLOATING_VEB_ARG,
405 ETH_I40E_FLOATING_VEB_LIST_ARG,
406 ETH_I40E_SUPPORT_MULTI_DRIVER,
407 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
408 ETH_I40E_USE_LATEST_VEC,
411 static const struct rte_pci_id pci_id_i40e_map[] = {
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
435 { .vendor_id = 0, /* sentinel */ },
438 static const struct eth_dev_ops i40e_eth_dev_ops = {
439 .dev_configure = i40e_dev_configure,
440 .dev_start = i40e_dev_start,
441 .dev_stop = i40e_dev_stop,
442 .dev_close = i40e_dev_close,
443 .dev_reset = i40e_dev_reset,
444 .promiscuous_enable = i40e_dev_promiscuous_enable,
445 .promiscuous_disable = i40e_dev_promiscuous_disable,
446 .allmulticast_enable = i40e_dev_allmulticast_enable,
447 .allmulticast_disable = i40e_dev_allmulticast_disable,
448 .dev_set_link_up = i40e_dev_set_link_up,
449 .dev_set_link_down = i40e_dev_set_link_down,
450 .link_update = i40e_dev_link_update,
451 .stats_get = i40e_dev_stats_get,
452 .xstats_get = i40e_dev_xstats_get,
453 .xstats_get_names = i40e_dev_xstats_get_names,
454 .stats_reset = i40e_dev_stats_reset,
455 .xstats_reset = i40e_dev_stats_reset,
456 .fw_version_get = i40e_fw_version_get,
457 .dev_infos_get = i40e_dev_info_get,
458 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
459 .vlan_filter_set = i40e_vlan_filter_set,
460 .vlan_tpid_set = i40e_vlan_tpid_set,
461 .vlan_offload_set = i40e_vlan_offload_set,
462 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
463 .vlan_pvid_set = i40e_vlan_pvid_set,
464 .rx_queue_start = i40e_dev_rx_queue_start,
465 .rx_queue_stop = i40e_dev_rx_queue_stop,
466 .tx_queue_start = i40e_dev_tx_queue_start,
467 .tx_queue_stop = i40e_dev_tx_queue_stop,
468 .rx_queue_setup = i40e_dev_rx_queue_setup,
469 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
470 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
471 .rx_queue_release = i40e_dev_rx_queue_release,
472 .rx_queue_count = i40e_dev_rx_queue_count,
473 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
474 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
475 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
476 .tx_queue_setup = i40e_dev_tx_queue_setup,
477 .tx_queue_release = i40e_dev_tx_queue_release,
478 .dev_led_on = i40e_dev_led_on,
479 .dev_led_off = i40e_dev_led_off,
480 .flow_ctrl_get = i40e_flow_ctrl_get,
481 .flow_ctrl_set = i40e_flow_ctrl_set,
482 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
483 .mac_addr_add = i40e_macaddr_add,
484 .mac_addr_remove = i40e_macaddr_remove,
485 .reta_update = i40e_dev_rss_reta_update,
486 .reta_query = i40e_dev_rss_reta_query,
487 .rss_hash_update = i40e_dev_rss_hash_update,
488 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
489 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
490 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
491 .filter_ctrl = i40e_dev_filter_ctrl,
492 .rxq_info_get = i40e_rxq_info_get,
493 .txq_info_get = i40e_txq_info_get,
494 .mirror_rule_set = i40e_mirror_rule_set,
495 .mirror_rule_reset = i40e_mirror_rule_reset,
496 .timesync_enable = i40e_timesync_enable,
497 .timesync_disable = i40e_timesync_disable,
498 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
499 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
500 .get_dcb_info = i40e_dev_get_dcb_info,
501 .timesync_adjust_time = i40e_timesync_adjust_time,
502 .timesync_read_time = i40e_timesync_read_time,
503 .timesync_write_time = i40e_timesync_write_time,
504 .get_reg = i40e_get_regs,
505 .get_eeprom_length = i40e_get_eeprom_length,
506 .get_eeprom = i40e_get_eeprom,
507 .get_module_info = i40e_get_module_info,
508 .get_module_eeprom = i40e_get_module_eeprom,
509 .mac_addr_set = i40e_set_default_mac_addr,
510 .mtu_set = i40e_dev_mtu_set,
511 .tm_ops_get = i40e_tm_ops_get,
514 /* store statistics names and its offset in stats structure */
515 struct rte_i40e_xstats_name_off {
516 char name[RTE_ETH_XSTATS_NAME_SIZE];
520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
521 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
522 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
523 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
524 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
525 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
526 rx_unknown_protocol)},
527 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
528 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
529 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
530 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
534 sizeof(rte_i40e_stats_strings[0]))
536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
537 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
538 tx_dropped_link_down)},
539 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
540 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
542 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
543 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
545 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
549 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
550 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
551 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
552 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
553 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
554 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
556 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
568 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
571 mac_short_packet_dropped)},
572 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
575 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
576 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
578 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
588 {"rx_flow_director_atr_match_packets",
589 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
590 {"rx_flow_director_sb_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
592 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
594 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
603 sizeof(rte_i40e_hw_port_strings[0]))
605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
606 {"xon_packets", offsetof(struct i40e_hw_port_stats,
608 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
613 sizeof(rte_i40e_rxq_prio_strings[0]))
615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
616 {"xon_packets", offsetof(struct i40e_hw_port_stats,
618 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
621 priority_xon_2_xoff)},
624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
625 sizeof(rte_i40e_txq_prio_strings[0]))
628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
629 struct rte_pci_device *pci_dev)
631 char name[RTE_ETH_NAME_MAX_LEN];
632 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
635 if (pci_dev->device.devargs) {
636 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
642 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
643 sizeof(struct i40e_adapter),
644 eth_dev_pci_specific_init, pci_dev,
645 eth_i40e_dev_init, NULL);
647 if (retval || eth_da.nb_representor_ports < 1)
650 /* probe VF representor ports */
651 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
652 pci_dev->device.name);
654 if (pf_ethdev == NULL)
657 for (i = 0; i < eth_da.nb_representor_ports; i++) {
658 struct i40e_vf_representor representor = {
659 .vf_id = eth_da.representor_ports[i],
660 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
661 pf_ethdev->data->dev_private)->switch_domain_id,
662 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
663 pf_ethdev->data->dev_private)
666 /* representor port net_bdf_port */
667 snprintf(name, sizeof(name), "net_%s_representor_%d",
668 pci_dev->device.name, eth_da.representor_ports[i]);
670 retval = rte_eth_dev_create(&pci_dev->device, name,
671 sizeof(struct i40e_vf_representor), NULL, NULL,
672 i40e_vf_representor_init, &representor);
675 PMD_DRV_LOG(ERR, "failed to create i40e vf "
676 "representor %s.", name);
682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
684 struct rte_eth_dev *ethdev;
686 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
691 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
692 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
694 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
697 static struct rte_pci_driver rte_i40e_pmd = {
698 .id_table = pci_id_i40e_map,
699 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
700 .probe = eth_i40e_pci_probe,
701 .remove = eth_i40e_pci_remove,
705 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
708 uint32_t ori_reg_val;
709 struct rte_eth_dev *dev;
711 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
712 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
713 i40e_write_rx_ctl(hw, reg_addr, reg_val);
714 if (ori_reg_val != reg_val)
716 "i40e device %s changed global register [0x%08x]."
717 " original: 0x%08x, new: 0x%08x",
718 dev->device->name, reg_addr, ori_reg_val, reg_val);
721 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
722 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
723 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
725 #ifndef I40E_GLQF_ORT
726 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
728 #ifndef I40E_GLQF_PIT
729 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
731 #ifndef I40E_GLQF_L3_MAP
732 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
735 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
738 * Initialize registers for parsing packet type of QinQ
739 * This should be removed from code once proper
740 * configuration API is added to avoid configuration conflicts
741 * between ports of the same device.
743 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
744 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
747 static inline void i40e_config_automask(struct i40e_pf *pf)
749 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
752 /* INTENA flag is not auto-cleared for interrupt */
753 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
754 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
755 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
757 /* If support multi-driver, PF will use INT0. */
758 if (!pf->support_multi_driver)
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
761 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
764 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
767 * Add a ethertype filter to drop all flow control frames transmitted
771 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
774 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
775 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
776 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
779 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
780 I40E_FLOW_CONTROL_ETHERTYPE, flags,
781 pf->main_vsi_seid, 0,
785 "Failed to add filter to drop flow control frames from VSIs.");
789 floating_veb_list_handler(__rte_unused const char *key,
790 const char *floating_veb_value,
794 unsigned int count = 0;
797 bool *vf_floating_veb = opaque;
799 while (isblank(*floating_veb_value))
800 floating_veb_value++;
802 /* Reset floating VEB configuration for VFs */
803 for (idx = 0; idx < I40E_MAX_VF; idx++)
804 vf_floating_veb[idx] = false;
808 while (isblank(*floating_veb_value))
809 floating_veb_value++;
810 if (*floating_veb_value == '\0')
813 idx = strtoul(floating_veb_value, &end, 10);
814 if (errno || end == NULL)
816 while (isblank(*end))
820 } else if ((*end == ';') || (*end == '\0')) {
822 if (min == I40E_MAX_VF)
824 if (max >= I40E_MAX_VF)
825 max = I40E_MAX_VF - 1;
826 for (idx = min; idx <= max; idx++) {
827 vf_floating_veb[idx] = true;
834 floating_veb_value = end + 1;
835 } while (*end != '\0');
844 config_vf_floating_veb(struct rte_devargs *devargs,
845 uint16_t floating_veb,
846 bool *vf_floating_veb)
848 struct rte_kvargs *kvlist;
850 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
854 /* All the VFs attach to the floating VEB by default
855 * when the floating VEB is enabled.
857 for (i = 0; i < I40E_MAX_VF; i++)
858 vf_floating_veb[i] = true;
863 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
867 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
868 rte_kvargs_free(kvlist);
871 /* When the floating_veb_list parameter exists, all the VFs
872 * will attach to the legacy VEB firstly, then configure VFs
873 * to the floating VEB according to the floating_veb_list.
875 if (rte_kvargs_process(kvlist, floating_veb_list,
876 floating_veb_list_handler,
877 vf_floating_veb) < 0) {
878 rte_kvargs_free(kvlist);
881 rte_kvargs_free(kvlist);
885 i40e_check_floating_handler(__rte_unused const char *key,
887 __rte_unused void *opaque)
889 if (strcmp(value, "1"))
896 is_floating_veb_supported(struct rte_devargs *devargs)
898 struct rte_kvargs *kvlist;
899 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
904 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
908 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
909 rte_kvargs_free(kvlist);
912 /* Floating VEB is enabled when there's key-value:
913 * enable_floating_veb=1
915 if (rte_kvargs_process(kvlist, floating_veb_key,
916 i40e_check_floating_handler, NULL) < 0) {
917 rte_kvargs_free(kvlist);
920 rte_kvargs_free(kvlist);
926 config_floating_veb(struct rte_eth_dev *dev)
928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
932 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
934 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
936 is_floating_veb_supported(pci_dev->device.devargs);
937 config_vf_floating_veb(pci_dev->device.devargs,
939 pf->floating_veb_list);
941 pf->floating_veb = false;
945 #define I40E_L2_TAGS_S_TAG_SHIFT 1
946 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
949 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
953 char ethertype_hash_name[RTE_HASH_NAMESIZE];
956 struct rte_hash_parameters ethertype_hash_params = {
957 .name = ethertype_hash_name,
958 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
959 .key_len = sizeof(struct i40e_ethertype_filter_input),
960 .hash_func = rte_hash_crc,
961 .hash_func_init_val = 0,
962 .socket_id = rte_socket_id(),
965 /* Initialize ethertype filter rule list and hash */
966 TAILQ_INIT(ðertype_rule->ethertype_list);
967 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
968 "ethertype_%s", dev->device->name);
969 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
970 if (!ethertype_rule->hash_table) {
971 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
974 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
975 sizeof(struct i40e_ethertype_filter *) *
976 I40E_MAX_ETHERTYPE_FILTER_NUM,
978 if (!ethertype_rule->hash_map) {
980 "Failed to allocate memory for ethertype hash map!");
982 goto err_ethertype_hash_map_alloc;
987 err_ethertype_hash_map_alloc:
988 rte_hash_free(ethertype_rule->hash_table);
994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
998 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001 struct rte_hash_parameters tunnel_hash_params = {
1002 .name = tunnel_hash_name,
1003 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1004 .key_len = sizeof(struct i40e_tunnel_filter_input),
1005 .hash_func = rte_hash_crc,
1006 .hash_func_init_val = 0,
1007 .socket_id = rte_socket_id(),
1010 /* Initialize tunnel filter rule list and hash */
1011 TAILQ_INIT(&tunnel_rule->tunnel_list);
1012 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1013 "tunnel_%s", dev->device->name);
1014 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1015 if (!tunnel_rule->hash_table) {
1016 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1020 sizeof(struct i40e_tunnel_filter *) *
1021 I40E_MAX_TUNNEL_FILTER_NUM,
1023 if (!tunnel_rule->hash_map) {
1025 "Failed to allocate memory for tunnel hash map!");
1027 goto err_tunnel_hash_map_alloc;
1032 err_tunnel_hash_map_alloc:
1033 rte_hash_free(tunnel_rule->hash_table);
1039 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_fdir_info *fdir_info = &pf->fdir;
1043 char fdir_hash_name[RTE_HASH_NAMESIZE];
1046 struct rte_hash_parameters fdir_hash_params = {
1047 .name = fdir_hash_name,
1048 .entries = I40E_MAX_FDIR_FILTER_NUM,
1049 .key_len = sizeof(struct i40e_fdir_input),
1050 .hash_func = rte_hash_crc,
1051 .hash_func_init_val = 0,
1052 .socket_id = rte_socket_id(),
1055 /* Initialize flow director filter rule list and hash */
1056 TAILQ_INIT(&fdir_info->fdir_list);
1057 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1058 "fdir_%s", dev->device->name);
1059 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1060 if (!fdir_info->hash_table) {
1061 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1065 sizeof(struct i40e_fdir_filter *) *
1066 I40E_MAX_FDIR_FILTER_NUM,
1068 if (!fdir_info->hash_map) {
1070 "Failed to allocate memory for fdir hash map!");
1072 goto err_fdir_hash_map_alloc;
1076 err_fdir_hash_map_alloc:
1077 rte_hash_free(fdir_info->hash_table);
1083 i40e_init_customized_info(struct i40e_pf *pf)
1087 /* Initialize customized pctype */
1088 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1089 pf->customized_pctype[i].index = i;
1090 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1091 pf->customized_pctype[i].valid = false;
1094 pf->gtp_support = false;
1098 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1102 struct i40e_queue_regions *info = &pf->queue_region;
1105 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1106 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1108 memset(info, 0, sizeof(struct i40e_queue_regions));
1112 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117 unsigned long support_multi_driver;
1120 pf = (struct i40e_pf *)opaque;
1123 support_multi_driver = strtoul(value, &end, 10);
1124 if (errno != 0 || end == value || *end != 0) {
1125 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1129 if (support_multi_driver == 1 || support_multi_driver == 0)
1130 pf->support_multi_driver = (bool)support_multi_driver;
1132 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1133 "enable global configuration by default."
1134 ETH_I40E_SUPPORT_MULTI_DRIVER);
1139 i40e_support_multi_driver(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct rte_kvargs *kvlist;
1145 /* Enable global configuration by default */
1146 pf->support_multi_driver = false;
1148 if (!dev->device->devargs)
1151 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1155 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1156 if (!kvargs_count) {
1157 rte_kvargs_free(kvlist);
1161 if (kvargs_count > 1)
1162 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1163 "the first invalid or last valid one is used !",
1164 ETH_I40E_SUPPORT_MULTI_DRIVER);
1166 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1167 i40e_parse_multi_drv_handler, pf) < 0) {
1168 rte_kvargs_free(kvlist);
1172 rte_kvargs_free(kvlist);
1177 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1178 uint32_t reg_addr, uint64_t reg_val,
1179 struct i40e_asq_cmd_details *cmd_details)
1181 uint64_t ori_reg_val;
1182 struct rte_eth_dev *dev;
1185 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1186 if (ret != I40E_SUCCESS) {
1188 "Fail to debug read from 0x%08x",
1192 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1194 if (ori_reg_val != reg_val)
1195 PMD_DRV_LOG(WARNING,
1196 "i40e device %s changed global register [0x%08x]."
1197 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1198 dev->device->name, reg_addr, ori_reg_val, reg_val);
1200 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1204 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1208 struct i40e_adapter *ad = opaque;
1211 use_latest_vec = atoi(value);
1213 if (use_latest_vec != 0 && use_latest_vec != 1)
1214 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1216 ad->use_latest_vec = (uint8_t)use_latest_vec;
1222 i40e_use_latest_vec(struct rte_eth_dev *dev)
1224 struct i40e_adapter *ad =
1225 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226 struct rte_kvargs *kvlist;
1229 ad->use_latest_vec = false;
1231 if (!dev->device->devargs)
1234 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1238 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1239 if (!kvargs_count) {
1240 rte_kvargs_free(kvlist);
1244 if (kvargs_count > 1)
1245 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1246 "the first invalid or last valid one is used !",
1247 ETH_I40E_USE_LATEST_VEC);
1249 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1250 i40e_parse_latest_vec_handler, ad) < 0) {
1251 rte_kvargs_free(kvlist);
1255 rte_kvargs_free(kvlist);
1259 #define I40E_ALARM_INTERVAL 50000 /* us */
1262 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1264 struct rte_pci_device *pci_dev;
1265 struct rte_intr_handle *intr_handle;
1266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct i40e_vsi *vsi;
1271 uint8_t aq_fail = 0;
1273 PMD_INIT_FUNC_TRACE();
1275 dev->dev_ops = &i40e_eth_dev_ops;
1276 dev->rx_pkt_burst = i40e_recv_pkts;
1277 dev->tx_pkt_burst = i40e_xmit_pkts;
1278 dev->tx_pkt_prepare = i40e_prep_pkts;
1280 /* for secondary processes, we don't initialise any further as primary
1281 * has already done this work. Only check we don't need a different
1283 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1284 i40e_set_rx_function(dev);
1285 i40e_set_tx_function(dev);
1288 i40e_set_default_ptype_table(dev);
1289 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290 intr_handle = &pci_dev->intr_handle;
1292 rte_eth_copy_pci_info(dev, pci_dev);
1294 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1295 pf->adapter->eth_dev = dev;
1296 pf->dev_data = dev->data;
1298 hw->back = I40E_PF_TO_ADAPTER(pf);
1299 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1302 "Hardware is not available, as address is NULL");
1306 hw->vendor_id = pci_dev->id.vendor_id;
1307 hw->device_id = pci_dev->id.device_id;
1308 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1309 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1310 hw->bus.device = pci_dev->addr.devid;
1311 hw->bus.func = pci_dev->addr.function;
1312 hw->adapter_stopped = 0;
1313 hw->adapter_closed = 0;
1316 * Switch Tag value should not be identical to either the First Tag
1317 * or Second Tag values. So set something other than common Ethertype
1318 * for internal switching.
1320 hw->switch_tag = 0xffff;
1322 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1323 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1324 PMD_INIT_LOG(ERR, "\nERROR: "
1325 "Firmware recovery mode detected. Limiting functionality.\n"
1326 "Refer to the Intel(R) Ethernet Adapters and Devices "
1327 "User Guide for details on firmware recovery mode.");
1331 /* Check if need to support multi-driver */
1332 i40e_support_multi_driver(dev);
1333 /* Check if users want the latest supported vec path */
1334 i40e_use_latest_vec(dev);
1336 /* Make sure all is clean before doing PF reset */
1339 /* Reset here to make sure all is clean for each PF */
1340 ret = i40e_pf_reset(hw);
1342 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1346 /* Initialize the shared code (base driver) */
1347 ret = i40e_init_shared_code(hw);
1349 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1353 /* Initialize the parameters for adminq */
1354 i40e_init_adminq_parameter(hw);
1355 ret = i40e_init_adminq(hw);
1356 if (ret != I40E_SUCCESS) {
1357 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1360 /* Firmware of SFP x722 does not support adminq option */
1361 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1362 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1364 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1365 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1366 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1367 ((hw->nvm.version >> 12) & 0xf),
1368 ((hw->nvm.version >> 4) & 0xff),
1369 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1371 /* Initialize the hardware */
1374 i40e_config_automask(pf);
1376 i40e_set_default_pctype_table(dev);
1379 * To work around the NVM issue, initialize registers
1380 * for packet type of QinQ by software.
1381 * It should be removed once issues are fixed in NVM.
1383 if (!pf->support_multi_driver)
1384 i40e_GLQF_reg_init(hw);
1386 /* Initialize the input set for filters (hash and fd) to default value */
1387 i40e_filter_input_set_init(pf);
1389 /* initialise the L3_MAP register */
1390 if (!pf->support_multi_driver) {
1391 ret = i40e_aq_debug_write_global_register(hw,
1392 I40E_GLQF_L3_MAP(40),
1395 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398 "Global register 0x%08x is changed with 0x28",
1399 I40E_GLQF_L3_MAP(40));
1402 /* Need the special FW version to support floating VEB */
1403 config_floating_veb(dev);
1404 /* Clear PXE mode */
1405 i40e_clear_pxe_mode(hw);
1406 i40e_dev_sync_phy_type(hw);
1409 * On X710, performance number is far from the expectation on recent
1410 * firmware versions. The fix for this issue may not be integrated in
1411 * the following firmware version. So the workaround in software driver
1412 * is needed. It needs to modify the initial values of 3 internal only
1413 * registers. Note that the workaround can be removed when it is fixed
1414 * in firmware in the future.
1416 i40e_configure_registers(hw);
1418 /* Get hw capabilities */
1419 ret = i40e_get_cap(hw);
1420 if (ret != I40E_SUCCESS) {
1421 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1422 goto err_get_capabilities;
1425 /* Initialize parameters for PF */
1426 ret = i40e_pf_parameter_init(dev);
1428 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1429 goto err_parameter_init;
1432 /* Initialize the queue management */
1433 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1435 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1436 goto err_qp_pool_init;
1438 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1439 hw->func_caps.num_msix_vectors - 1);
1441 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1442 goto err_msix_pool_init;
1445 /* Initialize lan hmc */
1446 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1447 hw->func_caps.num_rx_qp, 0, 0);
1448 if (ret != I40E_SUCCESS) {
1449 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1450 goto err_init_lan_hmc;
1453 /* Configure lan hmc */
1454 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1455 if (ret != I40E_SUCCESS) {
1456 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1457 goto err_configure_lan_hmc;
1460 /* Get and check the mac address */
1461 i40e_get_mac_addr(hw, hw->mac.addr);
1462 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1463 PMD_INIT_LOG(ERR, "mac address is not valid");
1465 goto err_get_mac_addr;
1467 /* Copy the permanent MAC address */
1468 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1469 (struct rte_ether_addr *)hw->mac.perm_addr);
1471 /* Disable flow control */
1472 hw->fc.requested_mode = I40E_FC_NONE;
1473 i40e_set_fc(hw, &aq_fail, TRUE);
1475 /* Set the global registers with default ether type value */
1476 if (!pf->support_multi_driver) {
1477 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1478 RTE_ETHER_TYPE_VLAN);
1479 if (ret != I40E_SUCCESS) {
1481 "Failed to set the default outer "
1483 goto err_setup_pf_switch;
1487 /* PF setup, which includes VSI setup */
1488 ret = i40e_pf_setup(pf);
1490 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1491 goto err_setup_pf_switch;
1496 /* Disable double vlan by default */
1497 i40e_vsi_config_double_vlan(vsi, FALSE);
1499 /* Disable S-TAG identification when floating_veb is disabled */
1500 if (!pf->floating_veb) {
1501 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1502 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1503 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1504 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1508 if (!vsi->max_macaddrs)
1509 len = RTE_ETHER_ADDR_LEN;
1511 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1513 /* Should be after VSI initialized */
1514 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1515 if (!dev->data->mac_addrs) {
1517 "Failed to allocated memory for storing mac address");
1520 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1521 &dev->data->mac_addrs[0]);
1523 /* Init dcb to sw mode by default */
1524 ret = i40e_dcb_init_configure(dev, TRUE);
1525 if (ret != I40E_SUCCESS) {
1526 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1527 pf->flags &= ~I40E_FLAG_DCB;
1529 /* Update HW struct after DCB configuration */
1532 /* initialize pf host driver to setup SRIOV resource if applicable */
1533 i40e_pf_host_init(dev);
1535 /* register callback func to eal lib */
1536 rte_intr_callback_register(intr_handle,
1537 i40e_dev_interrupt_handler, dev);
1539 /* configure and enable device interrupt */
1540 i40e_pf_config_irq0(hw, TRUE);
1541 i40e_pf_enable_irq0(hw);
1543 /* enable uio intr after callback register */
1544 rte_intr_enable(intr_handle);
1546 /* By default disable flexible payload in global configuration */
1547 if (!pf->support_multi_driver)
1548 i40e_flex_payload_reg_set_default(hw);
1551 * Add an ethertype filter to drop all flow control frames transmitted
1552 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1555 i40e_add_tx_flow_control_drop_filter(pf);
1557 /* Set the max frame size to 0x2600 by default,
1558 * in case other drivers changed the default value.
1560 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1562 /* initialize mirror rule list */
1563 TAILQ_INIT(&pf->mirror_list);
1565 /* initialize Traffic Manager configuration */
1566 i40e_tm_conf_init(dev);
1568 /* Initialize customized information */
1569 i40e_init_customized_info(pf);
1571 ret = i40e_init_ethtype_filter_list(dev);
1573 goto err_init_ethtype_filter_list;
1574 ret = i40e_init_tunnel_filter_list(dev);
1576 goto err_init_tunnel_filter_list;
1577 ret = i40e_init_fdir_filter_list(dev);
1579 goto err_init_fdir_filter_list;
1581 /* initialize queue region configuration */
1582 i40e_init_queue_region_conf(dev);
1584 /* initialize rss configuration from rte_flow */
1585 memset(&pf->rss_info, 0,
1586 sizeof(struct i40e_rte_flow_rss_conf));
1588 /* reset all stats of the device, including pf and main vsi */
1589 i40e_dev_stats_reset(dev);
1593 err_init_fdir_filter_list:
1594 rte_free(pf->tunnel.hash_table);
1595 rte_free(pf->tunnel.hash_map);
1596 err_init_tunnel_filter_list:
1597 rte_free(pf->ethertype.hash_table);
1598 rte_free(pf->ethertype.hash_map);
1599 err_init_ethtype_filter_list:
1600 rte_free(dev->data->mac_addrs);
1601 dev->data->mac_addrs = NULL;
1603 i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1606 err_configure_lan_hmc:
1607 (void)i40e_shutdown_lan_hmc(hw);
1609 i40e_res_pool_destroy(&pf->msix_pool);
1611 i40e_res_pool_destroy(&pf->qp_pool);
1614 err_get_capabilities:
1615 (void)i40e_shutdown_adminq(hw);
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 struct i40e_ethertype_filter *p_ethertype;
1624 struct i40e_ethertype_rule *ethertype_rule;
1626 ethertype_rule = &pf->ethertype;
1627 /* Remove all ethertype filter rules and hash */
1628 if (ethertype_rule->hash_map)
1629 rte_free(ethertype_rule->hash_map);
1630 if (ethertype_rule->hash_table)
1631 rte_hash_free(ethertype_rule->hash_table);
1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1634 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1635 p_ethertype, rules);
1636 rte_free(p_ethertype);
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 struct i40e_tunnel_filter *p_tunnel;
1644 struct i40e_tunnel_rule *tunnel_rule;
1646 tunnel_rule = &pf->tunnel;
1647 /* Remove all tunnel director rules and hash */
1648 if (tunnel_rule->hash_map)
1649 rte_free(tunnel_rule->hash_map);
1650 if (tunnel_rule->hash_table)
1651 rte_hash_free(tunnel_rule->hash_table);
1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 struct i40e_fdir_filter *p_fdir;
1663 struct i40e_fdir_info *fdir_info;
1665 fdir_info = &pf->fdir;
1666 /* Remove all flow director rules and hash */
1667 if (fdir_info->hash_map)
1668 rte_free(fdir_info->hash_map);
1669 if (fdir_info->hash_table)
1670 rte_hash_free(fdir_info->hash_table);
1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1681 * Disable by default flexible payload
1682 * for corresponding L2/L3/L4 layers.
1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1693 struct rte_pci_device *pci_dev;
1694 struct rte_intr_handle *intr_handle;
1696 struct i40e_filter_control_settings settings;
1697 struct rte_flow *p_flow;
1699 uint8_t aq_fail = 0;
1702 PMD_INIT_FUNC_TRACE();
1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710 intr_handle = &pci_dev->intr_handle;
1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716 if (hw->adapter_closed == 0)
1717 i40e_dev_close(dev);
1719 dev->dev_ops = NULL;
1720 dev->rx_pkt_burst = NULL;
1721 dev->tx_pkt_burst = NULL;
1723 /* Clear PXE mode */
1724 i40e_clear_pxe_mode(hw);
1726 /* Unconfigure filter control */
1727 memset(&settings, 0, sizeof(settings));
1728 ret = i40e_set_filter_control(hw, &settings);
1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1733 /* Disable flow control */
1734 hw->fc.requested_mode = I40E_FC_NONE;
1735 i40e_set_fc(hw, &aq_fail, TRUE);
1737 /* uninitialize pf host driver */
1738 i40e_pf_host_uninit(dev);
1740 /* disable uio intr before callback unregister */
1741 rte_intr_disable(intr_handle);
1743 /* unregister callback func to eal lib */
1745 ret = rte_intr_callback_unregister(intr_handle,
1746 i40e_dev_interrupt_handler, dev);
1749 } else if (ret != -EAGAIN) {
1751 "intr callback unregister failed: %d",
1755 i40e_msec_delay(500);
1756 } while (retries++ < 5);
1758 i40e_rm_ethtype_filter_list(pf);
1759 i40e_rm_tunnel_filter_list(pf);
1760 i40e_rm_fdir_filter_list(pf);
1762 /* Remove all flows */
1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768 /* Remove all Traffic Manager configuration */
1769 i40e_tm_conf_uninit(dev);
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1777 struct i40e_adapter *ad =
1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1784 ret = i40e_dev_sync_phy_type(hw);
1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789 * bulk allocation or vector Rx preconditions we will reset it.
1791 ad->rx_bulk_alloc_allowed = true;
1792 ad->rx_vec_allowed = true;
1793 ad->tx_simple_allowed = true;
1794 ad->tx_vec_allowed = true;
1796 /* Only legacy filter API needs the following fdir config. So when the
1797 * legacy filter API is deprecated, the following codes should also be
1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801 ret = i40e_fdir_setup(pf);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1806 ret = i40e_fdir_configure(dev);
1808 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812 i40e_fdir_teardown(pf);
1814 ret = i40e_dev_init_vlan(dev);
1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820 * RSS setting have different requirements.
1821 * General PMD driver call sequence are NIC init, configure,
1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823 * will try to lookup the VSI that specific queue belongs to if VMDQ
1824 * applicable. So, VMDQ setting has to be done before
1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1826 * For RSS setting, it will try to calculate actual configured RX queue
1827 * number, which will be available after rx_queue_setup(). dev_start()
1828 * function is good to place RSS setup.
1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831 ret = i40e_vmdq_setup(dev);
1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837 ret = i40e_dcb_setup(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1844 TAILQ_INIT(&pf->flow_list);
1849 /* need to release vmdq resource if exists */
1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851 i40e_vsi_release(pf->vmdq[i].vsi);
1852 pf->vmdq[i].vsi = NULL;
1857 /* Need to release fdir resource if exists.
1858 * Only legacy filter API needs the following fdir config. So when the
1859 * legacy filter API is deprecated, the following code should also be
1862 i40e_fdir_teardown(pf);
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873 uint16_t msix_vect = vsi->msix_intr;
1876 for (i = 0; i < vsi->nb_qps; i++) {
1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882 if (vsi->type != I40E_VSI_SRIOV) {
1883 if (!rte_intr_allow_others(intr_handle)) {
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899 vsi->user_param + (msix_vect - 1);
1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909 int base_queue, int nb_queue,
1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917 /* Bind all RX queues to allocated MSIX interrupt */
1918 for (i = 0; i < nb_queue; i++) {
1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921 ((base_queue + i + 1) <<
1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926 if (i == nb_queue - 1)
1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1931 /* Write first RX queue to Link list register as the head element */
1932 if (vsi->type != I40E_VSI_SRIOV) {
1934 i40e_calc_itr_interval(1, pf->support_multi_driver);
1936 if (msix_vect == I40E_MISC_VEC_ID) {
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1959 if (msix_vect == I40E_MISC_VEC_ID) {
1961 I40E_VPINT_LNKLST0(vsi->user_param),
1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967 /* num_msix_vectors_vf needs to minus irq0 */
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 uint16_t msix_vect = vsi->msix_intr;
1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991 uint16_t queue_idx = 0;
1995 for (i = 0; i < vsi->nb_qps; i++) {
1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2000 /* VF bind interrupt */
2001 if (vsi->type == I40E_VSI_SRIOV) {
2002 __vsi_queues_bind_intr(vsi, msix_vect,
2003 vsi->base_queue, vsi->nb_qps,
2008 /* PF & VMDq bind interrupt */
2009 if (rte_intr_dp_is_en(intr_handle)) {
2010 if (vsi->type == I40E_VSI_MAIN) {
2013 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014 struct i40e_vsi *main_vsi =
2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2021 for (i = 0; i < vsi->nb_used_qps; i++) {
2023 if (!rte_intr_allow_others(intr_handle))
2024 /* allow to share MISC_VEC_ID */
2025 msix_vect = I40E_MISC_VEC_ID;
2027 /* no enough msix_vect, map all to one */
2028 __vsi_queues_bind_intr(vsi, msix_vect,
2029 vsi->base_queue + i,
2030 vsi->nb_used_qps - i,
2032 for (; !!record && i < vsi->nb_used_qps; i++)
2033 intr_handle->intr_vec[queue_idx + i] =
2037 /* 1:1 queue/msix_vect mapping */
2038 __vsi_queues_bind_intr(vsi, msix_vect,
2039 vsi->base_queue + i, 1,
2042 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057 uint16_t msix_intr, i;
2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060 for (i = 0; i < vsi->nb_msix; i++) {
2061 msix_intr = vsi->msix_intr + i;
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073 I40E_WRITE_FLUSH(hw);
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084 uint16_t msix_intr, i;
2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087 for (i = 0; i < vsi->nb_msix; i++) {
2088 msix_intr = vsi->msix_intr + i;
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096 I40E_WRITE_FLUSH(hw);
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104 if (link_speeds & ETH_LINK_SPEED_40G)
2105 link_speed |= I40E_LINK_SPEED_40GB;
2106 if (link_speeds & ETH_LINK_SPEED_25G)
2107 link_speed |= I40E_LINK_SPEED_25GB;
2108 if (link_speeds & ETH_LINK_SPEED_20G)
2109 link_speed |= I40E_LINK_SPEED_20GB;
2110 if (link_speeds & ETH_LINK_SPEED_10G)
2111 link_speed |= I40E_LINK_SPEED_10GB;
2112 if (link_speeds & ETH_LINK_SPEED_1G)
2113 link_speed |= I40E_LINK_SPEED_1GB;
2114 if (link_speeds & ETH_LINK_SPEED_100M)
2115 link_speed |= I40E_LINK_SPEED_100MB;
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2123 uint8_t force_speed,
2126 enum i40e_status_code status;
2127 struct i40e_aq_get_phy_abilities_resp phy_ab;
2128 struct i40e_aq_set_phy_config phy_conf;
2129 enum i40e_aq_phy_type cnt;
2130 uint8_t avail_speed;
2131 uint32_t phy_type_mask = 0;
2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134 I40E_AQ_PHY_FLAG_PAUSE_RX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_LOW_POWER;
2139 /* To get phy capabilities of available speeds. */
2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147 avail_speed = phy_ab.link_speed;
2149 /* To get the current phy config. */
2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2158 /* If link needs to go up and it is in autoneg mode the speed is OK,
2159 * no need to set up again.
2161 if (is_up && phy_ab.phy_type != 0 &&
2162 abilities & I40E_AQ_PHY_AN_ENABLED &&
2163 phy_ab.link_speed != 0)
2164 return I40E_SUCCESS;
2166 memset(&phy_conf, 0, sizeof(phy_conf));
2168 /* bits 0-2 use the values from get_phy_abilities_resp */
2170 abilities |= phy_ab.abilities & mask;
2172 phy_conf.abilities = abilities;
2174 /* If link needs to go up, but the force speed is not supported,
2175 * Warn users and config the default available speeds.
2177 if (is_up && !(force_speed & avail_speed)) {
2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179 phy_conf.link_speed = avail_speed;
2181 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2184 /* PHY type mask needs to include each type except PHY type extension */
2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186 phy_type_mask |= 1 << cnt;
2188 /* use get_phy_abilities_resp value for the rest */
2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194 phy_conf.eee_capability = phy_ab.eee_capability;
2195 phy_conf.eeer = phy_ab.eeer_val;
2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199 phy_ab.abilities, phy_ab.link_speed);
2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2201 phy_conf.abilities, phy_conf.link_speed);
2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207 return I40E_SUCCESS;
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2214 uint8_t abilities = 0;
2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct rte_eth_conf *conf = &dev->data->dev_conf;
2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219 conf->link_speeds = ETH_LINK_SPEED_40G |
2220 ETH_LINK_SPEED_25G |
2221 ETH_LINK_SPEED_20G |
2222 ETH_LINK_SPEED_10G |
2224 ETH_LINK_SPEED_100M;
2226 speed = i40e_parse_link_speeds(conf->link_speeds);
2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228 I40E_AQ_PHY_AN_ENABLED |
2229 I40E_AQ_PHY_LINK_ENABLED;
2231 return i40e_phy_conf_link(hw, abilities, speed, true);
2235 i40e_dev_start(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_vsi *main_vsi = pf->main_vsi;
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 uint32_t intr_vector = 0;
2244 struct i40e_vsi *vsi;
2246 hw->adapter_stopped = 0;
2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250 "Invalid link_speeds for port %u, autonegotiation disabled",
2251 dev->data->port_id);
2255 rte_intr_disable(intr_handle);
2257 if ((rte_intr_cap_multiple(intr_handle) ||
2258 !RTE_ETH_DEV_SRIOV(dev).active) &&
2259 dev->data->dev_conf.intr_conf.rxq != 0) {
2260 intr_vector = dev->data->nb_rx_queues;
2261 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267 intr_handle->intr_vec =
2268 rte_zmalloc("intr_vec",
2269 dev->data->nb_rx_queues * sizeof(int),
2271 if (!intr_handle->intr_vec) {
2273 "Failed to allocate %d rx_queues intr_vec",
2274 dev->data->nb_rx_queues);
2279 /* Initialize VSI */
2280 ret = i40e_dev_rxtx_init(pf);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286 /* Map queues with MSIX interrupt */
2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290 i40e_vsi_enable_queues_intr(main_vsi);
2292 /* Map VMDQ VSI queues with MSIX interrupt */
2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296 I40E_ITR_INDEX_DEFAULT);
2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2300 /* enable FDIR MSIX interrupt */
2301 if (pf->fdir.fdir_vsi) {
2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303 I40E_ITR_INDEX_NONE);
2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2307 /* Enable all queues which have been configured */
2308 ret = i40e_dev_switch_queues(pf, TRUE);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314 /* Enable receiving broadcast packets */
2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322 if (ret != I40E_SUCCESS)
2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326 /* Enable the VLAN promiscuous mode. */
2328 for (i = 0; i < pf->vf_num; i++) {
2329 vsi = pf->vfs[i].vsi;
2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2335 /* Enable mac loopback mode */
2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339 if (ret != I40E_SUCCESS) {
2340 PMD_DRV_LOG(ERR, "fail to set loopback link");
2345 /* Apply link configure */
2346 ret = i40e_apply_link_speed(dev);
2347 if (I40E_SUCCESS != ret) {
2348 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352 if (!rte_intr_allow_others(intr_handle)) {
2353 rte_intr_callback_unregister(intr_handle,
2354 i40e_dev_interrupt_handler,
2356 /* configure and enable device interrupt */
2357 i40e_pf_config_irq0(hw, FALSE);
2358 i40e_pf_enable_irq0(hw);
2360 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362 "lsc won't enable because of no intr multiplex");
2364 ret = i40e_aq_set_phy_int_mask(hw,
2365 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367 I40E_AQ_EVENT_MEDIA_NA), NULL);
2368 if (ret != I40E_SUCCESS)
2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371 /* Call get_link_info aq commond to enable/disable LSE */
2372 i40e_dev_link_update(dev, 0);
2375 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377 i40e_dev_alarm_handler, dev);
2379 /* enable uio intr after callback register */
2380 rte_intr_enable(intr_handle);
2383 i40e_filter_restore(pf);
2385 if (pf->tm_conf.root && !pf->tm_conf.committed)
2386 PMD_DRV_LOG(WARNING,
2387 "please call hierarchy_commit() "
2388 "before starting the port");
2390 return I40E_SUCCESS;
2393 i40e_dev_switch_queues(pf, FALSE);
2394 i40e_dev_clear_queues(dev);
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct i40e_vsi *main_vsi = pf->main_vsi;
2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2409 if (hw->adapter_stopped == 1)
2412 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414 rte_intr_enable(intr_handle);
2417 /* Disable all queues */
2418 i40e_dev_switch_queues(pf, FALSE);
2420 /* un-map queues with interrupt registers */
2421 i40e_vsi_disable_queues_intr(main_vsi);
2422 i40e_vsi_queues_unbind_intr(main_vsi);
2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2429 if (pf->fdir.fdir_vsi) {
2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433 /* Clear all queues and release memory */
2434 i40e_dev_clear_queues(dev);
2437 i40e_dev_set_link_down(dev);
2439 if (!rte_intr_allow_others(intr_handle))
2440 /* resume to the default handler */
2441 rte_intr_callback_register(intr_handle,
2442 i40e_dev_interrupt_handler,
2445 /* Clean datapath event and queue/vec mapping */
2446 rte_intr_efd_disable(intr_handle);
2447 if (intr_handle->intr_vec) {
2448 rte_free(intr_handle->intr_vec);
2449 intr_handle->intr_vec = NULL;
2452 /* reset hierarchy commit */
2453 pf->tm_conf.committed = false;
2455 hw->adapter_stopped = 1;
2457 pf->adapter->rss_reta_updated = 0;
2461 i40e_dev_close(struct rte_eth_dev *dev)
2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467 struct i40e_mirror_rule *p_mirror;
2472 PMD_INIT_FUNC_TRACE();
2476 /* Remove all mirror rules */
2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478 ret = i40e_aq_del_mirror_rule(hw,
2479 pf->main_vsi->veb->seid,
2480 p_mirror->rule_type,
2482 p_mirror->num_entries,
2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486 "status = %d, aq_err = %d.", ret,
2487 hw->aq.asq_last_status);
2489 /* remove mirror software resource anyway */
2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492 pf->nb_mirror_rule--;
2495 i40e_dev_free_queues(dev);
2497 /* Disable interrupt */
2498 i40e_pf_disable_irq0(hw);
2499 rte_intr_disable(intr_handle);
2502 * Only legacy filter API needs the following fdir config. So when the
2503 * legacy filter API is deprecated, the following code should also be
2506 i40e_fdir_teardown(pf);
2508 /* shutdown and destroy the HMC */
2509 i40e_shutdown_lan_hmc(hw);
2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512 i40e_vsi_release(pf->vmdq[i].vsi);
2513 pf->vmdq[i].vsi = NULL;
2518 /* release all the existing VSIs and VEBs */
2519 i40e_vsi_release(pf->main_vsi);
2521 /* shutdown the adminq */
2522 i40e_aq_queue_shutdown(hw, true);
2523 i40e_shutdown_adminq(hw);
2525 i40e_res_pool_destroy(&pf->qp_pool);
2526 i40e_res_pool_destroy(&pf->msix_pool);
2528 /* Disable flexible payload in global configuration */
2529 if (!pf->support_multi_driver)
2530 i40e_flex_payload_reg_set_default(hw);
2532 /* force a PF reset to clean anything leftover */
2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536 I40E_WRITE_FLUSH(hw);
2538 hw->adapter_closed = 1;
2542 * Reset PF device only to re-initialize resources in PMD layer
2545 i40e_dev_reset(struct rte_eth_dev *dev)
2549 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2550 * its VF to make them align with it. The detailed notification
2551 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2552 * To avoid unexpected behavior in VF, currently reset of PF with
2553 * SR-IOV activation is not supported. It might be supported later.
2555 if (dev->data->sriov.active)
2558 ret = eth_i40e_dev_uninit(dev);
2562 ret = eth_i40e_dev_init(dev, NULL);
2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572 struct i40e_vsi *vsi = pf->main_vsi;
2575 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577 if (status != I40E_SUCCESS) {
2578 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2582 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2584 if (status != I40E_SUCCESS) {
2585 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2586 /* Rollback unicast promiscuous mode */
2587 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2596 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2598 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2599 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600 struct i40e_vsi *vsi = pf->main_vsi;
2603 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2605 if (status != I40E_SUCCESS) {
2606 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2610 /* must remain in all_multicast mode */
2611 if (dev->data->all_multicast == 1)
2614 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2616 if (status != I40E_SUCCESS) {
2617 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2618 /* Rollback unicast promiscuous mode */
2619 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2628 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 struct i40e_vsi *vsi = pf->main_vsi;
2635 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2636 if (ret != I40E_SUCCESS) {
2637 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2645 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 struct i40e_vsi *vsi = pf->main_vsi;
2652 if (dev->data->promiscuous == 1)
2653 return 0; /* must remain in all_multicast mode */
2655 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2656 vsi->seid, FALSE, NULL);
2657 if (ret != I40E_SUCCESS) {
2658 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2666 * Set device link up.
2669 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2671 /* re-apply link speed setting */
2672 return i40e_apply_link_speed(dev);
2676 * Set device link down.
2679 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2681 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2682 uint8_t abilities = 0;
2683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2686 return i40e_phy_conf_link(hw, abilities, speed, false);
2689 static __rte_always_inline void
2690 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2692 /* Link status registers and values*/
2693 #define I40E_PRTMAC_LINKSTA 0x001E2420
2694 #define I40E_REG_LINK_UP 0x40000080
2695 #define I40E_PRTMAC_MACC 0x001E24E0
2696 #define I40E_REG_MACC_25GB 0x00020000
2697 #define I40E_REG_SPEED_MASK 0x38000000
2698 #define I40E_REG_SPEED_0 0x00000000
2699 #define I40E_REG_SPEED_1 0x08000000
2700 #define I40E_REG_SPEED_2 0x10000000
2701 #define I40E_REG_SPEED_3 0x18000000
2702 #define I40E_REG_SPEED_4 0x20000000
2703 uint32_t link_speed;
2706 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2707 link_speed = reg_val & I40E_REG_SPEED_MASK;
2708 reg_val &= I40E_REG_LINK_UP;
2709 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2711 if (unlikely(link->link_status == 0))
2714 /* Parse the link status */
2715 switch (link_speed) {
2716 case I40E_REG_SPEED_0:
2717 link->link_speed = ETH_SPEED_NUM_100M;
2719 case I40E_REG_SPEED_1:
2720 link->link_speed = ETH_SPEED_NUM_1G;
2722 case I40E_REG_SPEED_2:
2723 if (hw->mac.type == I40E_MAC_X722)
2724 link->link_speed = ETH_SPEED_NUM_2_5G;
2726 link->link_speed = ETH_SPEED_NUM_10G;
2728 case I40E_REG_SPEED_3:
2729 if (hw->mac.type == I40E_MAC_X722) {
2730 link->link_speed = ETH_SPEED_NUM_5G;
2732 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2734 if (reg_val & I40E_REG_MACC_25GB)
2735 link->link_speed = ETH_SPEED_NUM_25G;
2737 link->link_speed = ETH_SPEED_NUM_40G;
2740 case I40E_REG_SPEED_4:
2741 if (hw->mac.type == I40E_MAC_X722)
2742 link->link_speed = ETH_SPEED_NUM_10G;
2744 link->link_speed = ETH_SPEED_NUM_20G;
2747 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2752 static __rte_always_inline void
2753 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2754 bool enable_lse, int wait_to_complete)
2756 #define CHECK_INTERVAL 100 /* 100ms */
2757 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2758 uint32_t rep_cnt = MAX_REPEAT_TIME;
2759 struct i40e_link_status link_status;
2762 memset(&link_status, 0, sizeof(link_status));
2765 memset(&link_status, 0, sizeof(link_status));
2767 /* Get link status information from hardware */
2768 status = i40e_aq_get_link_info(hw, enable_lse,
2769 &link_status, NULL);
2770 if (unlikely(status != I40E_SUCCESS)) {
2771 link->link_speed = ETH_SPEED_NUM_100M;
2772 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2773 PMD_DRV_LOG(ERR, "Failed to get link info");
2777 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2778 if (!wait_to_complete || link->link_status)
2781 rte_delay_ms(CHECK_INTERVAL);
2782 } while (--rep_cnt);
2784 /* Parse the link status */
2785 switch (link_status.link_speed) {
2786 case I40E_LINK_SPEED_100MB:
2787 link->link_speed = ETH_SPEED_NUM_100M;
2789 case I40E_LINK_SPEED_1GB:
2790 link->link_speed = ETH_SPEED_NUM_1G;
2792 case I40E_LINK_SPEED_10GB:
2793 link->link_speed = ETH_SPEED_NUM_10G;
2795 case I40E_LINK_SPEED_20GB:
2796 link->link_speed = ETH_SPEED_NUM_20G;
2798 case I40E_LINK_SPEED_25GB:
2799 link->link_speed = ETH_SPEED_NUM_25G;
2801 case I40E_LINK_SPEED_40GB:
2802 link->link_speed = ETH_SPEED_NUM_40G;
2805 link->link_speed = ETH_SPEED_NUM_100M;
2811 i40e_dev_link_update(struct rte_eth_dev *dev,
2812 int wait_to_complete)
2814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 struct rte_eth_link link;
2816 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2819 memset(&link, 0, sizeof(link));
2821 /* i40e uses full duplex only */
2822 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2823 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2824 ETH_LINK_SPEED_FIXED);
2826 if (!wait_to_complete && !enable_lse)
2827 update_link_reg(hw, &link);
2829 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2831 ret = rte_eth_linkstatus_set(dev, &link);
2832 i40e_notify_all_vfs_link_status(dev);
2837 /* Get all the statistics of a VSI */
2839 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2841 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2842 struct i40e_eth_stats *nes = &vsi->eth_stats;
2843 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2844 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2846 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2847 vsi->offset_loaded, &oes->rx_bytes,
2849 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2850 vsi->offset_loaded, &oes->rx_unicast,
2852 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2853 vsi->offset_loaded, &oes->rx_multicast,
2854 &nes->rx_multicast);
2855 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2856 vsi->offset_loaded, &oes->rx_broadcast,
2857 &nes->rx_broadcast);
2858 /* exclude CRC bytes */
2859 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2860 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2862 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2863 &oes->rx_discards, &nes->rx_discards);
2864 /* GLV_REPC not supported */
2865 /* GLV_RMPC not supported */
2866 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2867 &oes->rx_unknown_protocol,
2868 &nes->rx_unknown_protocol);
2869 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2870 vsi->offset_loaded, &oes->tx_bytes,
2872 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2873 vsi->offset_loaded, &oes->tx_unicast,
2875 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2876 vsi->offset_loaded, &oes->tx_multicast,
2877 &nes->tx_multicast);
2878 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2879 vsi->offset_loaded, &oes->tx_broadcast,
2880 &nes->tx_broadcast);
2881 /* GLV_TDPC not supported */
2882 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2883 &oes->tx_errors, &nes->tx_errors);
2884 vsi->offset_loaded = true;
2886 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2888 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2889 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2890 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2891 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2892 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2893 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2894 nes->rx_unknown_protocol);
2895 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2896 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2897 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2898 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2899 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2900 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2901 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2906 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2909 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2910 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2912 /* Get rx/tx bytes of internal transfer packets */
2913 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2914 I40E_GLV_GORCL(hw->port),
2916 &pf->internal_stats_offset.rx_bytes,
2917 &pf->internal_stats.rx_bytes);
2919 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2920 I40E_GLV_GOTCL(hw->port),
2922 &pf->internal_stats_offset.tx_bytes,
2923 &pf->internal_stats.tx_bytes);
2924 /* Get total internal rx packet count */
2925 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2926 I40E_GLV_UPRCL(hw->port),
2928 &pf->internal_stats_offset.rx_unicast,
2929 &pf->internal_stats.rx_unicast);
2930 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2931 I40E_GLV_MPRCL(hw->port),
2933 &pf->internal_stats_offset.rx_multicast,
2934 &pf->internal_stats.rx_multicast);
2935 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2936 I40E_GLV_BPRCL(hw->port),
2938 &pf->internal_stats_offset.rx_broadcast,
2939 &pf->internal_stats.rx_broadcast);
2940 /* Get total internal tx packet count */
2941 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2942 I40E_GLV_UPTCL(hw->port),
2944 &pf->internal_stats_offset.tx_unicast,
2945 &pf->internal_stats.tx_unicast);
2946 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2947 I40E_GLV_MPTCL(hw->port),
2949 &pf->internal_stats_offset.tx_multicast,
2950 &pf->internal_stats.tx_multicast);
2951 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2952 I40E_GLV_BPTCL(hw->port),
2954 &pf->internal_stats_offset.tx_broadcast,
2955 &pf->internal_stats.tx_broadcast);
2957 /* exclude CRC size */
2958 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2959 pf->internal_stats.rx_multicast +
2960 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2962 /* Get statistics of struct i40e_eth_stats */
2963 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2964 I40E_GLPRT_GORCL(hw->port),
2965 pf->offset_loaded, &os->eth.rx_bytes,
2967 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2968 I40E_GLPRT_UPRCL(hw->port),
2969 pf->offset_loaded, &os->eth.rx_unicast,
2970 &ns->eth.rx_unicast);
2971 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2972 I40E_GLPRT_MPRCL(hw->port),
2973 pf->offset_loaded, &os->eth.rx_multicast,
2974 &ns->eth.rx_multicast);
2975 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2976 I40E_GLPRT_BPRCL(hw->port),
2977 pf->offset_loaded, &os->eth.rx_broadcast,
2978 &ns->eth.rx_broadcast);
2979 /* Workaround: CRC size should not be included in byte statistics,
2980 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2983 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2984 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2986 /* exclude internal rx bytes
2987 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2988 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2990 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2992 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2993 ns->eth.rx_bytes = 0;
2995 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2997 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2998 ns->eth.rx_unicast = 0;
3000 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3002 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3003 ns->eth.rx_multicast = 0;
3005 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3007 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3008 ns->eth.rx_broadcast = 0;
3010 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3012 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3013 pf->offset_loaded, &os->eth.rx_discards,
3014 &ns->eth.rx_discards);
3015 /* GLPRT_REPC not supported */
3016 /* GLPRT_RMPC not supported */
3017 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3019 &os->eth.rx_unknown_protocol,
3020 &ns->eth.rx_unknown_protocol);
3021 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3022 I40E_GLPRT_GOTCL(hw->port),
3023 pf->offset_loaded, &os->eth.tx_bytes,
3025 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3026 I40E_GLPRT_UPTCL(hw->port),
3027 pf->offset_loaded, &os->eth.tx_unicast,
3028 &ns->eth.tx_unicast);
3029 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3030 I40E_GLPRT_MPTCL(hw->port),
3031 pf->offset_loaded, &os->eth.tx_multicast,
3032 &ns->eth.tx_multicast);
3033 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3034 I40E_GLPRT_BPTCL(hw->port),
3035 pf->offset_loaded, &os->eth.tx_broadcast,
3036 &ns->eth.tx_broadcast);
3037 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3038 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3040 /* exclude internal tx bytes
3041 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3042 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3044 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3046 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3047 ns->eth.tx_bytes = 0;
3049 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3051 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3052 ns->eth.tx_unicast = 0;
3054 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3056 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3057 ns->eth.tx_multicast = 0;
3059 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3061 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3062 ns->eth.tx_broadcast = 0;
3064 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3066 /* GLPRT_TEPC not supported */
3068 /* additional port specific stats */
3069 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3070 pf->offset_loaded, &os->tx_dropped_link_down,
3071 &ns->tx_dropped_link_down);
3072 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3073 pf->offset_loaded, &os->crc_errors,
3075 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3076 pf->offset_loaded, &os->illegal_bytes,
3077 &ns->illegal_bytes);
3078 /* GLPRT_ERRBC not supported */
3079 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3080 pf->offset_loaded, &os->mac_local_faults,
3081 &ns->mac_local_faults);
3082 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3083 pf->offset_loaded, &os->mac_remote_faults,
3084 &ns->mac_remote_faults);
3085 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3086 pf->offset_loaded, &os->rx_length_errors,
3087 &ns->rx_length_errors);
3088 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3089 pf->offset_loaded, &os->link_xon_rx,
3091 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3092 pf->offset_loaded, &os->link_xoff_rx,
3094 for (i = 0; i < 8; i++) {
3095 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3097 &os->priority_xon_rx[i],
3098 &ns->priority_xon_rx[i]);
3099 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3101 &os->priority_xoff_rx[i],
3102 &ns->priority_xoff_rx[i]);
3104 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3105 pf->offset_loaded, &os->link_xon_tx,
3107 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3108 pf->offset_loaded, &os->link_xoff_tx,
3110 for (i = 0; i < 8; i++) {
3111 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3113 &os->priority_xon_tx[i],
3114 &ns->priority_xon_tx[i]);
3115 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3117 &os->priority_xoff_tx[i],
3118 &ns->priority_xoff_tx[i]);
3119 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3121 &os->priority_xon_2_xoff[i],
3122 &ns->priority_xon_2_xoff[i]);
3124 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3125 I40E_GLPRT_PRC64L(hw->port),
3126 pf->offset_loaded, &os->rx_size_64,
3128 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3129 I40E_GLPRT_PRC127L(hw->port),
3130 pf->offset_loaded, &os->rx_size_127,
3132 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3133 I40E_GLPRT_PRC255L(hw->port),
3134 pf->offset_loaded, &os->rx_size_255,
3136 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3137 I40E_GLPRT_PRC511L(hw->port),
3138 pf->offset_loaded, &os->rx_size_511,
3140 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3141 I40E_GLPRT_PRC1023L(hw->port),
3142 pf->offset_loaded, &os->rx_size_1023,
3144 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3145 I40E_GLPRT_PRC1522L(hw->port),
3146 pf->offset_loaded, &os->rx_size_1522,
3148 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3149 I40E_GLPRT_PRC9522L(hw->port),
3150 pf->offset_loaded, &os->rx_size_big,
3152 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3153 pf->offset_loaded, &os->rx_undersize,
3155 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3156 pf->offset_loaded, &os->rx_fragments,
3158 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3159 pf->offset_loaded, &os->rx_oversize,
3161 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3162 pf->offset_loaded, &os->rx_jabber,
3164 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3165 I40E_GLPRT_PTC64L(hw->port),
3166 pf->offset_loaded, &os->tx_size_64,
3168 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3169 I40E_GLPRT_PTC127L(hw->port),
3170 pf->offset_loaded, &os->tx_size_127,
3172 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3173 I40E_GLPRT_PTC255L(hw->port),
3174 pf->offset_loaded, &os->tx_size_255,
3176 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3177 I40E_GLPRT_PTC511L(hw->port),
3178 pf->offset_loaded, &os->tx_size_511,
3180 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3181 I40E_GLPRT_PTC1023L(hw->port),
3182 pf->offset_loaded, &os->tx_size_1023,
3184 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3185 I40E_GLPRT_PTC1522L(hw->port),
3186 pf->offset_loaded, &os->tx_size_1522,
3188 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3189 I40E_GLPRT_PTC9522L(hw->port),
3190 pf->offset_loaded, &os->tx_size_big,
3192 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3194 &os->fd_sb_match, &ns->fd_sb_match);
3195 /* GLPRT_MSPDC not supported */
3196 /* GLPRT_XEC not supported */
3198 pf->offset_loaded = true;
3201 i40e_update_vsi_stats(pf->main_vsi);
3204 /* Get all statistics of a port */
3206 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3208 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3210 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3211 struct i40e_vsi *vsi;
3214 /* call read registers - updates values, now write them to struct */
3215 i40e_read_stats_registers(pf, hw);
3217 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3218 pf->main_vsi->eth_stats.rx_multicast +
3219 pf->main_vsi->eth_stats.rx_broadcast -
3220 pf->main_vsi->eth_stats.rx_discards;
3221 stats->opackets = ns->eth.tx_unicast +
3222 ns->eth.tx_multicast +
3223 ns->eth.tx_broadcast;
3224 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3225 stats->obytes = ns->eth.tx_bytes;
3226 stats->oerrors = ns->eth.tx_errors +
3227 pf->main_vsi->eth_stats.tx_errors;
3230 stats->imissed = ns->eth.rx_discards +
3231 pf->main_vsi->eth_stats.rx_discards;
3232 stats->ierrors = ns->crc_errors +
3233 ns->rx_length_errors + ns->rx_undersize +
3234 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3237 for (i = 0; i < pf->vf_num; i++) {
3238 vsi = pf->vfs[i].vsi;
3239 i40e_update_vsi_stats(vsi);
3241 stats->ipackets += (vsi->eth_stats.rx_unicast +
3242 vsi->eth_stats.rx_multicast +
3243 vsi->eth_stats.rx_broadcast -
3244 vsi->eth_stats.rx_discards);
3245 stats->ibytes += vsi->eth_stats.rx_bytes;
3246 stats->oerrors += vsi->eth_stats.tx_errors;
3247 stats->imissed += vsi->eth_stats.rx_discards;
3251 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3252 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3253 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3254 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3255 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3256 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3257 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3258 ns->eth.rx_unknown_protocol);
3259 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3260 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3261 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3262 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3263 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3264 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3266 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3267 ns->tx_dropped_link_down);
3268 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3269 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3271 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3272 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3273 ns->mac_local_faults);
3274 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3275 ns->mac_remote_faults);
3276 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3277 ns->rx_length_errors);
3278 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3279 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3280 for (i = 0; i < 8; i++) {
3281 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3282 i, ns->priority_xon_rx[i]);
3283 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3284 i, ns->priority_xoff_rx[i]);
3286 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3287 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3288 for (i = 0; i < 8; i++) {
3289 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3290 i, ns->priority_xon_tx[i]);
3291 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3292 i, ns->priority_xoff_tx[i]);
3293 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3294 i, ns->priority_xon_2_xoff[i]);
3296 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3297 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3298 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3299 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3300 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3301 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3302 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3303 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3304 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3305 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3306 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3307 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3308 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3309 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3310 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3311 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3312 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3313 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3314 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3315 ns->mac_short_packet_dropped);
3316 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3317 ns->checksum_error);
3318 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3319 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3323 /* Reset the statistics */
3325 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3327 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3328 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330 /* Mark PF and VSI stats to update the offset, aka "reset" */
3331 pf->offset_loaded = false;
3333 pf->main_vsi->offset_loaded = false;
3335 /* read the stats, reading current register values into offset */
3336 i40e_read_stats_registers(pf, hw);
3342 i40e_xstats_calc_num(void)
3344 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3345 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3346 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3349 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3350 struct rte_eth_xstat_name *xstats_names,
3351 __rte_unused unsigned limit)
3356 if (xstats_names == NULL)
3357 return i40e_xstats_calc_num();
3359 /* Note: limit checked in rte_eth_xstats_names() */
3361 /* Get stats from i40e_eth_stats struct */
3362 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3363 strlcpy(xstats_names[count].name,
3364 rte_i40e_stats_strings[i].name,
3365 sizeof(xstats_names[count].name));
3369 /* Get individiual stats from i40e_hw_port struct */
3370 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3371 strlcpy(xstats_names[count].name,
3372 rte_i40e_hw_port_strings[i].name,
3373 sizeof(xstats_names[count].name));
3377 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3378 for (prio = 0; prio < 8; prio++) {
3379 snprintf(xstats_names[count].name,
3380 sizeof(xstats_names[count].name),
3381 "rx_priority%u_%s", prio,
3382 rte_i40e_rxq_prio_strings[i].name);
3387 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3388 for (prio = 0; prio < 8; prio++) {
3389 snprintf(xstats_names[count].name,
3390 sizeof(xstats_names[count].name),
3391 "tx_priority%u_%s", prio,
3392 rte_i40e_txq_prio_strings[i].name);
3400 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405 unsigned i, count, prio;
3406 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3408 count = i40e_xstats_calc_num();
3412 i40e_read_stats_registers(pf, hw);
3419 /* Get stats from i40e_eth_stats struct */
3420 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3421 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3422 rte_i40e_stats_strings[i].offset);
3423 xstats[count].id = count;
3427 /* Get individiual stats from i40e_hw_port struct */
3428 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3429 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3430 rte_i40e_hw_port_strings[i].offset);
3431 xstats[count].id = count;
3435 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3436 for (prio = 0; prio < 8; prio++) {
3437 xstats[count].value =
3438 *(uint64_t *)(((char *)hw_stats) +
3439 rte_i40e_rxq_prio_strings[i].offset +
3440 (sizeof(uint64_t) * prio));
3441 xstats[count].id = count;
3446 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3447 for (prio = 0; prio < 8; prio++) {
3448 xstats[count].value =
3449 *(uint64_t *)(((char *)hw_stats) +
3450 rte_i40e_txq_prio_strings[i].offset +
3451 (sizeof(uint64_t) * prio));
3452 xstats[count].id = count;
3461 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3463 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469 full_ver = hw->nvm.oem_ver;
3470 ver = (u8)(full_ver >> 24);
3471 build = (u16)((full_ver >> 8) & 0xffff);
3472 patch = (u8)(full_ver & 0xff);
3474 ret = snprintf(fw_version, fw_size,
3475 "%d.%d%d 0x%08x %d.%d.%d",
3476 ((hw->nvm.version >> 12) & 0xf),
3477 ((hw->nvm.version >> 4) & 0xff),
3478 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3481 ret += 1; /* add the size of '\0' */
3482 if (fw_size < (u32)ret)
3489 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3490 * the Rx data path does not hang if the FW LLDP is stopped.
3491 * return true if lldp need to stop
3492 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3495 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3498 char ver_str[64] = {0};
3499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501 i40e_fw_version_get(dev, ver_str, 64);
3502 nvm_ver = atof(ver_str);
3503 if ((hw->mac.type == I40E_MAC_X722 ||
3504 hw->mac.type == I40E_MAC_X722_VF) &&
3505 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3507 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3514 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3516 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 struct i40e_vsi *vsi = pf->main_vsi;
3519 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3521 dev_info->max_rx_queues = vsi->nb_qps;
3522 dev_info->max_tx_queues = vsi->nb_qps;
3523 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3524 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3525 dev_info->max_mac_addrs = vsi->max_macaddrs;
3526 dev_info->max_vfs = pci_dev->max_vfs;
3527 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3528 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3529 dev_info->rx_queue_offload_capa = 0;
3530 dev_info->rx_offload_capa =
3531 DEV_RX_OFFLOAD_VLAN_STRIP |
3532 DEV_RX_OFFLOAD_QINQ_STRIP |
3533 DEV_RX_OFFLOAD_IPV4_CKSUM |
3534 DEV_RX_OFFLOAD_UDP_CKSUM |
3535 DEV_RX_OFFLOAD_TCP_CKSUM |
3536 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3537 DEV_RX_OFFLOAD_KEEP_CRC |
3538 DEV_RX_OFFLOAD_SCATTER |
3539 DEV_RX_OFFLOAD_VLAN_EXTEND |
3540 DEV_RX_OFFLOAD_VLAN_FILTER |
3541 DEV_RX_OFFLOAD_JUMBO_FRAME;
3543 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3544 dev_info->tx_offload_capa =
3545 DEV_TX_OFFLOAD_VLAN_INSERT |
3546 DEV_TX_OFFLOAD_QINQ_INSERT |
3547 DEV_TX_OFFLOAD_IPV4_CKSUM |
3548 DEV_TX_OFFLOAD_UDP_CKSUM |
3549 DEV_TX_OFFLOAD_TCP_CKSUM |
3550 DEV_TX_OFFLOAD_SCTP_CKSUM |
3551 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3552 DEV_TX_OFFLOAD_TCP_TSO |
3553 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3554 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3555 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3556 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3557 DEV_TX_OFFLOAD_MULTI_SEGS |
3558 dev_info->tx_queue_offload_capa;
3559 dev_info->dev_capa =
3560 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3561 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3563 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3565 dev_info->reta_size = pf->hash_lut_size;
3566 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3568 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3570 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3571 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3572 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3574 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3579 dev_info->default_txconf = (struct rte_eth_txconf) {
3581 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3582 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3583 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3585 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3586 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3590 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3591 .nb_max = I40E_MAX_RING_DESC,
3592 .nb_min = I40E_MIN_RING_DESC,
3593 .nb_align = I40E_ALIGN_RING_DESC,
3596 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3597 .nb_max = I40E_MAX_RING_DESC,
3598 .nb_min = I40E_MIN_RING_DESC,
3599 .nb_align = I40E_ALIGN_RING_DESC,
3600 .nb_seg_max = I40E_TX_MAX_SEG,
3601 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3604 if (pf->flags & I40E_FLAG_VMDQ) {
3605 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3606 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3607 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3608 pf->max_nb_vmdq_vsi;
3609 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3610 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3611 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3614 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3616 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3617 dev_info->default_rxportconf.nb_queues = 2;
3618 dev_info->default_txportconf.nb_queues = 2;
3619 if (dev->data->nb_rx_queues == 1)
3620 dev_info->default_rxportconf.ring_size = 2048;
3622 dev_info->default_rxportconf.ring_size = 1024;
3623 if (dev->data->nb_tx_queues == 1)
3624 dev_info->default_txportconf.ring_size = 1024;
3626 dev_info->default_txportconf.ring_size = 512;
3628 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3630 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3631 dev_info->default_rxportconf.nb_queues = 1;
3632 dev_info->default_txportconf.nb_queues = 1;
3633 dev_info->default_rxportconf.ring_size = 256;
3634 dev_info->default_txportconf.ring_size = 256;
3637 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3638 dev_info->default_rxportconf.nb_queues = 1;
3639 dev_info->default_txportconf.nb_queues = 1;
3640 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3641 dev_info->default_rxportconf.ring_size = 512;
3642 dev_info->default_txportconf.ring_size = 256;
3644 dev_info->default_rxportconf.ring_size = 256;
3645 dev_info->default_txportconf.ring_size = 256;
3648 dev_info->default_rxportconf.burst_size = 32;
3649 dev_info->default_txportconf.burst_size = 32;
3655 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3657 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3658 struct i40e_vsi *vsi = pf->main_vsi;
3659 PMD_INIT_FUNC_TRACE();
3662 return i40e_vsi_add_vlan(vsi, vlan_id);
3664 return i40e_vsi_delete_vlan(vsi, vlan_id);
3668 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3669 enum rte_vlan_type vlan_type,
3670 uint16_t tpid, int qinq)
3672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3675 uint16_t reg_id = 3;
3679 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3683 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3685 if (ret != I40E_SUCCESS) {
3687 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3692 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3695 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3696 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3697 if (reg_r == reg_w) {
3698 PMD_DRV_LOG(DEBUG, "No need to write");
3702 ret = i40e_aq_debug_write_global_register(hw,
3703 I40E_GL_SWT_L2TAGCTRL(reg_id),
3705 if (ret != I40E_SUCCESS) {
3707 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3712 "Global register 0x%08x is changed with value 0x%08x",
3713 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3719 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3720 enum rte_vlan_type vlan_type,
3723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3725 int qinq = dev->data->dev_conf.rxmode.offloads &
3726 DEV_RX_OFFLOAD_VLAN_EXTEND;
3729 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3730 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3731 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3733 "Unsupported vlan type.");
3737 if (pf->support_multi_driver) {
3738 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3742 /* 802.1ad frames ability is added in NVM API 1.7*/
3743 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3745 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3746 hw->first_tag = rte_cpu_to_le_16(tpid);
3747 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3748 hw->second_tag = rte_cpu_to_le_16(tpid);
3750 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3751 hw->second_tag = rte_cpu_to_le_16(tpid);
3753 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3754 if (ret != I40E_SUCCESS) {
3756 "Set switch config failed aq_err: %d",
3757 hw->aq.asq_last_status);
3761 /* If NVM API < 1.7, keep the register setting */
3762 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3769 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3772 struct i40e_vsi *vsi = pf->main_vsi;
3773 struct rte_eth_rxmode *rxmode;
3775 rxmode = &dev->data->dev_conf.rxmode;
3776 if (mask & ETH_VLAN_FILTER_MASK) {
3777 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3778 i40e_vsi_config_vlan_filter(vsi, TRUE);
3780 i40e_vsi_config_vlan_filter(vsi, FALSE);
3783 if (mask & ETH_VLAN_STRIP_MASK) {
3784 /* Enable or disable VLAN stripping */
3785 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3786 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3788 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3791 if (mask & ETH_VLAN_EXTEND_MASK) {
3792 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3793 i40e_vsi_config_double_vlan(vsi, TRUE);
3794 /* Set global registers with default ethertype. */
3795 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3796 RTE_ETHER_TYPE_VLAN);
3797 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3798 RTE_ETHER_TYPE_VLAN);
3801 i40e_vsi_config_double_vlan(vsi, FALSE);
3808 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3809 __rte_unused uint16_t queue,
3810 __rte_unused int on)
3812 PMD_INIT_FUNC_TRACE();
3816 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3818 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3819 struct i40e_vsi *vsi = pf->main_vsi;
3820 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3821 struct i40e_vsi_vlan_pvid_info info;
3823 memset(&info, 0, sizeof(info));
3826 info.config.pvid = pvid;
3828 info.config.reject.tagged =
3829 data->dev_conf.txmode.hw_vlan_reject_tagged;
3830 info.config.reject.untagged =
3831 data->dev_conf.txmode.hw_vlan_reject_untagged;
3834 return i40e_vsi_vlan_pvid_set(vsi, &info);
3838 i40e_dev_led_on(struct rte_eth_dev *dev)
3840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3841 uint32_t mode = i40e_led_get(hw);
3844 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3850 i40e_dev_led_off(struct rte_eth_dev *dev)
3852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853 uint32_t mode = i40e_led_get(hw);
3856 i40e_led_set(hw, 0, false);
3862 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3865 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3867 fc_conf->pause_time = pf->fc_conf.pause_time;
3869 /* read out from register, in case they are modified by other port */
3870 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3871 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3872 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3873 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3875 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3876 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3878 /* Return current mode according to actual setting*/
3879 switch (hw->fc.current_mode) {
3881 fc_conf->mode = RTE_FC_FULL;
3883 case I40E_FC_TX_PAUSE:
3884 fc_conf->mode = RTE_FC_TX_PAUSE;
3886 case I40E_FC_RX_PAUSE:
3887 fc_conf->mode = RTE_FC_RX_PAUSE;
3891 fc_conf->mode = RTE_FC_NONE;
3898 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3900 uint32_t mflcn_reg, fctrl_reg, reg;
3901 uint32_t max_high_water;
3902 uint8_t i, aq_failure;
3906 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3907 [RTE_FC_NONE] = I40E_FC_NONE,
3908 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3909 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3910 [RTE_FC_FULL] = I40E_FC_FULL
3913 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3915 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3916 if ((fc_conf->high_water > max_high_water) ||
3917 (fc_conf->high_water < fc_conf->low_water)) {
3919 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3924 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3926 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3928 pf->fc_conf.pause_time = fc_conf->pause_time;
3929 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3930 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3932 PMD_INIT_FUNC_TRACE();
3934 /* All the link flow control related enable/disable register
3935 * configuration is handle by the F/W
3937 err = i40e_set_fc(hw, &aq_failure, true);
3941 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3942 /* Configure flow control refresh threshold,
3943 * the value for stat_tx_pause_refresh_timer[8]
3944 * is used for global pause operation.
3948 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3949 pf->fc_conf.pause_time);
3951 /* configure the timer value included in transmitted pause
3953 * the value for stat_tx_pause_quanta[8] is used for global
3956 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3957 pf->fc_conf.pause_time);
3959 fctrl_reg = I40E_READ_REG(hw,
3960 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3962 if (fc_conf->mac_ctrl_frame_fwd != 0)
3963 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3965 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3967 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3970 /* Configure pause time (2 TCs per register) */
3971 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3972 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3973 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3975 /* Configure flow control refresh threshold value */
3976 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3977 pf->fc_conf.pause_time / 2);
3979 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3981 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3982 *depending on configuration
3984 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3985 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3986 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3988 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3989 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3992 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3995 if (!pf->support_multi_driver) {
3996 /* config water marker both based on the packets and bytes */
3997 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3998 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3999 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4000 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4001 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4002 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4003 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4004 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4006 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4007 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4011 "Water marker configuration is not supported.");
4014 I40E_WRITE_FLUSH(hw);
4020 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4021 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4023 PMD_INIT_FUNC_TRACE();
4028 /* Add a MAC address, and update filters */
4030 i40e_macaddr_add(struct rte_eth_dev *dev,
4031 struct rte_ether_addr *mac_addr,
4032 __rte_unused uint32_t index,
4035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4036 struct i40e_mac_filter_info mac_filter;
4037 struct i40e_vsi *vsi;
4038 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4041 /* If VMDQ not enabled or configured, return */
4042 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4043 !pf->nb_cfg_vmdq_vsi)) {
4044 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4045 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4050 if (pool > pf->nb_cfg_vmdq_vsi) {
4051 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4052 pool, pf->nb_cfg_vmdq_vsi);
4056 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4057 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4058 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4060 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4065 vsi = pf->vmdq[pool - 1].vsi;
4067 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4068 if (ret != I40E_SUCCESS) {
4069 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4075 /* Remove a MAC address, and update filters */
4077 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080 struct i40e_vsi *vsi;
4081 struct rte_eth_dev_data *data = dev->data;
4082 struct rte_ether_addr *macaddr;
4087 macaddr = &(data->mac_addrs[index]);
4089 pool_sel = dev->data->mac_pool_sel[index];
4091 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4092 if (pool_sel & (1ULL << i)) {
4096 /* No VMDQ pool enabled or configured */
4097 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4098 (i > pf->nb_cfg_vmdq_vsi)) {
4100 "No VMDQ pool enabled/configured");
4103 vsi = pf->vmdq[i - 1].vsi;
4105 ret = i40e_vsi_delete_mac(vsi, macaddr);
4108 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4115 /* Set perfect match or hash match of MAC and VLAN for a VF */
4117 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4118 struct rte_eth_mac_filter *filter,
4122 struct i40e_mac_filter_info mac_filter;
4123 struct rte_ether_addr old_mac;
4124 struct rte_ether_addr *new_mac;
4125 struct i40e_pf_vf *vf = NULL;
4130 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4133 hw = I40E_PF_TO_HW(pf);
4135 if (filter == NULL) {
4136 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4140 new_mac = &filter->mac_addr;
4142 if (rte_is_zero_ether_addr(new_mac)) {
4143 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4147 vf_id = filter->dst_id;
4149 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4150 PMD_DRV_LOG(ERR, "Invalid argument.");
4153 vf = &pf->vfs[vf_id];
4155 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4156 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4161 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4162 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4163 RTE_ETHER_ADDR_LEN);
4164 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4165 RTE_ETHER_ADDR_LEN);
4167 mac_filter.filter_type = filter->filter_type;
4168 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4169 if (ret != I40E_SUCCESS) {
4170 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4173 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4175 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4176 RTE_ETHER_ADDR_LEN);
4177 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4178 if (ret != I40E_SUCCESS) {
4179 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4183 /* Clear device address as it has been removed */
4184 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4185 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4191 /* MAC filter handle */
4193 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4197 struct rte_eth_mac_filter *filter;
4198 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4199 int ret = I40E_NOT_SUPPORTED;
4201 filter = (struct rte_eth_mac_filter *)(arg);
4203 switch (filter_op) {
4204 case RTE_ETH_FILTER_NOP:
4207 case RTE_ETH_FILTER_ADD:
4208 i40e_pf_disable_irq0(hw);
4210 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4211 i40e_pf_enable_irq0(hw);
4213 case RTE_ETH_FILTER_DELETE:
4214 i40e_pf_disable_irq0(hw);
4216 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4217 i40e_pf_enable_irq0(hw);
4220 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4221 ret = I40E_ERR_PARAM;
4229 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4231 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4232 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4239 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4240 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4241 vsi->type != I40E_VSI_SRIOV,
4244 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4248 uint32_t *lut_dw = (uint32_t *)lut;
4249 uint16_t i, lut_size_dw = lut_size / 4;
4251 if (vsi->type == I40E_VSI_SRIOV) {
4252 for (i = 0; i <= lut_size_dw; i++) {
4253 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4254 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4257 for (i = 0; i < lut_size_dw; i++)
4258 lut_dw[i] = I40E_READ_REG(hw,
4267 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4276 pf = I40E_VSI_TO_PF(vsi);
4277 hw = I40E_VSI_TO_HW(vsi);
4279 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4280 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4281 vsi->type != I40E_VSI_SRIOV,
4284 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4288 uint32_t *lut_dw = (uint32_t *)lut;
4289 uint16_t i, lut_size_dw = lut_size / 4;
4291 if (vsi->type == I40E_VSI_SRIOV) {
4292 for (i = 0; i < lut_size_dw; i++)
4295 I40E_VFQF_HLUT1(i, vsi->user_param),
4298 for (i = 0; i < lut_size_dw; i++)
4299 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4302 I40E_WRITE_FLUSH(hw);
4309 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4310 struct rte_eth_rss_reta_entry64 *reta_conf,
4313 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4314 uint16_t i, lut_size = pf->hash_lut_size;
4315 uint16_t idx, shift;
4319 if (reta_size != lut_size ||
4320 reta_size > ETH_RSS_RETA_SIZE_512) {
4322 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4323 reta_size, lut_size);
4327 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4329 PMD_DRV_LOG(ERR, "No memory can be allocated");
4332 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4335 for (i = 0; i < reta_size; i++) {
4336 idx = i / RTE_RETA_GROUP_SIZE;
4337 shift = i % RTE_RETA_GROUP_SIZE;
4338 if (reta_conf[idx].mask & (1ULL << shift))
4339 lut[i] = reta_conf[idx].reta[shift];
4341 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4343 pf->adapter->rss_reta_updated = 1;
4352 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4353 struct rte_eth_rss_reta_entry64 *reta_conf,
4356 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4357 uint16_t i, lut_size = pf->hash_lut_size;
4358 uint16_t idx, shift;
4362 if (reta_size != lut_size ||
4363 reta_size > ETH_RSS_RETA_SIZE_512) {
4365 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4366 reta_size, lut_size);
4370 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4372 PMD_DRV_LOG(ERR, "No memory can be allocated");
4376 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4379 for (i = 0; i < reta_size; i++) {
4380 idx = i / RTE_RETA_GROUP_SIZE;
4381 shift = i % RTE_RETA_GROUP_SIZE;
4382 if (reta_conf[idx].mask & (1ULL << shift))
4383 reta_conf[idx].reta[shift] = lut[i];
4393 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4394 * @hw: pointer to the HW structure
4395 * @mem: pointer to mem struct to fill out
4396 * @size: size of memory requested
4397 * @alignment: what to align the allocation to
4399 enum i40e_status_code
4400 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4401 struct i40e_dma_mem *mem,
4405 const struct rte_memzone *mz = NULL;
4406 char z_name[RTE_MEMZONE_NAMESIZE];
4409 return I40E_ERR_PARAM;
4411 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4412 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4413 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4415 return I40E_ERR_NO_MEMORY;
4420 mem->zone = (const void *)mz;
4422 "memzone %s allocated with physical address: %"PRIu64,
4425 return I40E_SUCCESS;
4429 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4430 * @hw: pointer to the HW structure
4431 * @mem: ptr to mem struct to free
4433 enum i40e_status_code
4434 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4435 struct i40e_dma_mem *mem)
4438 return I40E_ERR_PARAM;
4441 "memzone %s to be freed with physical address: %"PRIu64,
4442 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4443 rte_memzone_free((const struct rte_memzone *)mem->zone);
4448 return I40E_SUCCESS;
4452 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4453 * @hw: pointer to the HW structure
4454 * @mem: pointer to mem struct to fill out
4455 * @size: size of memory requested
4457 enum i40e_status_code
4458 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4459 struct i40e_virt_mem *mem,
4463 return I40E_ERR_PARAM;
4466 mem->va = rte_zmalloc("i40e", size, 0);
4469 return I40E_SUCCESS;
4471 return I40E_ERR_NO_MEMORY;
4475 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4476 * @hw: pointer to the HW structure
4477 * @mem: pointer to mem struct to free
4479 enum i40e_status_code
4480 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4481 struct i40e_virt_mem *mem)
4484 return I40E_ERR_PARAM;
4489 return I40E_SUCCESS;
4493 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4495 rte_spinlock_init(&sp->spinlock);
4499 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4501 rte_spinlock_lock(&sp->spinlock);
4505 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4507 rte_spinlock_unlock(&sp->spinlock);
4511 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4517 * Get the hardware capabilities, which will be parsed
4518 * and saved into struct i40e_hw.
4521 i40e_get_cap(struct i40e_hw *hw)
4523 struct i40e_aqc_list_capabilities_element_resp *buf;
4524 uint16_t len, size = 0;
4527 /* Calculate a huge enough buff for saving response data temporarily */
4528 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4529 I40E_MAX_CAP_ELE_NUM;
4530 buf = rte_zmalloc("i40e", len, 0);
4532 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4533 return I40E_ERR_NO_MEMORY;
4536 /* Get, parse the capabilities and save it to hw */
4537 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4538 i40e_aqc_opc_list_func_capabilities, NULL);
4539 if (ret != I40E_SUCCESS)
4540 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4542 /* Free the temporary buffer after being used */
4548 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4550 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4558 pf = (struct i40e_pf *)opaque;
4562 num = strtoul(value, &end, 0);
4563 if (errno != 0 || end == value || *end != 0) {
4564 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4565 "kept the value = %hu", value, pf->vf_nb_qp_max);
4569 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4570 pf->vf_nb_qp_max = (uint16_t)num;
4572 /* here return 0 to make next valid same argument work */
4573 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4574 "power of 2 and equal or less than 16 !, Now it is "
4575 "kept the value = %hu", num, pf->vf_nb_qp_max);
4580 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4582 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4583 struct rte_kvargs *kvlist;
4586 /* set default queue number per VF as 4 */
4587 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4589 if (dev->device->devargs == NULL)
4592 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4596 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4597 if (!kvargs_count) {
4598 rte_kvargs_free(kvlist);
4602 if (kvargs_count > 1)
4603 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4604 "the first invalid or last valid one is used !",
4605 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4607 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4608 i40e_pf_parse_vf_queue_number_handler, pf);
4610 rte_kvargs_free(kvlist);
4616 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4619 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4620 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4621 uint16_t qp_count = 0, vsi_count = 0;
4623 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4624 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4628 i40e_pf_config_vf_rxq_number(dev);
4630 /* Add the parameter init for LFC */
4631 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4632 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4633 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4635 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4636 pf->max_num_vsi = hw->func_caps.num_vsis;
4637 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4638 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4640 /* FDir queue/VSI allocation */
4641 pf->fdir_qp_offset = 0;
4642 if (hw->func_caps.fd) {
4643 pf->flags |= I40E_FLAG_FDIR;
4644 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4646 pf->fdir_nb_qps = 0;
4648 qp_count += pf->fdir_nb_qps;
4651 /* LAN queue/VSI allocation */
4652 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4653 if (!hw->func_caps.rss) {
4656 pf->flags |= I40E_FLAG_RSS;
4657 if (hw->mac.type == I40E_MAC_X722)
4658 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4659 pf->lan_nb_qps = pf->lan_nb_qp_max;
4661 qp_count += pf->lan_nb_qps;
4664 /* VF queue/VSI allocation */
4665 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4666 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4667 pf->flags |= I40E_FLAG_SRIOV;
4668 pf->vf_nb_qps = pf->vf_nb_qp_max;
4669 pf->vf_num = pci_dev->max_vfs;
4671 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4672 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4677 qp_count += pf->vf_nb_qps * pf->vf_num;
4678 vsi_count += pf->vf_num;
4680 /* VMDq queue/VSI allocation */
4681 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4682 pf->vmdq_nb_qps = 0;
4683 pf->max_nb_vmdq_vsi = 0;
4684 if (hw->func_caps.vmdq) {
4685 if (qp_count < hw->func_caps.num_tx_qp &&
4686 vsi_count < hw->func_caps.num_vsis) {
4687 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4688 qp_count) / pf->vmdq_nb_qp_max;
4690 /* Limit the maximum number of VMDq vsi to the maximum
4691 * ethdev can support
4693 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4694 hw->func_caps.num_vsis - vsi_count);
4695 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4697 if (pf->max_nb_vmdq_vsi) {
4698 pf->flags |= I40E_FLAG_VMDQ;
4699 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4701 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4702 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4703 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4706 "No enough queues left for VMDq");
4709 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4712 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4713 vsi_count += pf->max_nb_vmdq_vsi;
4715 if (hw->func_caps.dcb)
4716 pf->flags |= I40E_FLAG_DCB;
4718 if (qp_count > hw->func_caps.num_tx_qp) {
4720 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4721 qp_count, hw->func_caps.num_tx_qp);
4724 if (vsi_count > hw->func_caps.num_vsis) {
4726 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4727 vsi_count, hw->func_caps.num_vsis);
4735 i40e_pf_get_switch_config(struct i40e_pf *pf)
4737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4738 struct i40e_aqc_get_switch_config_resp *switch_config;
4739 struct i40e_aqc_switch_config_element_resp *element;
4740 uint16_t start_seid = 0, num_reported;
4743 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4744 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4745 if (!switch_config) {
4746 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4750 /* Get the switch configurations */
4751 ret = i40e_aq_get_switch_config(hw, switch_config,
4752 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4753 if (ret != I40E_SUCCESS) {
4754 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4757 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4758 if (num_reported != 1) { /* The number should be 1 */
4759 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4763 /* Parse the switch configuration elements */
4764 element = &(switch_config->element[0]);
4765 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4766 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4767 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4769 PMD_DRV_LOG(INFO, "Unknown element type");
4772 rte_free(switch_config);
4778 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4781 struct pool_entry *entry;
4783 if (pool == NULL || num == 0)
4786 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4787 if (entry == NULL) {
4788 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4792 /* queue heap initialize */
4793 pool->num_free = num;
4794 pool->num_alloc = 0;
4796 LIST_INIT(&pool->alloc_list);
4797 LIST_INIT(&pool->free_list);
4799 /* Initialize element */
4803 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4808 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4810 struct pool_entry *entry, *next_entry;
4815 for (entry = LIST_FIRST(&pool->alloc_list);
4816 entry && (next_entry = LIST_NEXT(entry, next), 1);
4817 entry = next_entry) {
4818 LIST_REMOVE(entry, next);
4822 for (entry = LIST_FIRST(&pool->free_list);
4823 entry && (next_entry = LIST_NEXT(entry, next), 1);
4824 entry = next_entry) {
4825 LIST_REMOVE(entry, next);
4830 pool->num_alloc = 0;
4832 LIST_INIT(&pool->alloc_list);
4833 LIST_INIT(&pool->free_list);
4837 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4840 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4841 uint32_t pool_offset;
4845 PMD_DRV_LOG(ERR, "Invalid parameter");
4849 pool_offset = base - pool->base;
4850 /* Lookup in alloc list */
4851 LIST_FOREACH(entry, &pool->alloc_list, next) {
4852 if (entry->base == pool_offset) {
4853 valid_entry = entry;
4854 LIST_REMOVE(entry, next);
4859 /* Not find, return */
4860 if (valid_entry == NULL) {
4861 PMD_DRV_LOG(ERR, "Failed to find entry");
4866 * Found it, move it to free list and try to merge.
4867 * In order to make merge easier, always sort it by qbase.
4868 * Find adjacent prev and last entries.
4871 LIST_FOREACH(entry, &pool->free_list, next) {
4872 if (entry->base > valid_entry->base) {
4880 /* Try to merge with next one*/
4882 /* Merge with next one */
4883 if (valid_entry->base + valid_entry->len == next->base) {
4884 next->base = valid_entry->base;
4885 next->len += valid_entry->len;
4886 rte_free(valid_entry);
4893 /* Merge with previous one */
4894 if (prev->base + prev->len == valid_entry->base) {
4895 prev->len += valid_entry->len;
4896 /* If it merge with next one, remove next node */
4898 LIST_REMOVE(valid_entry, next);
4899 rte_free(valid_entry);
4901 rte_free(valid_entry);
4907 /* Not find any entry to merge, insert */
4910 LIST_INSERT_AFTER(prev, valid_entry, next);
4911 else if (next != NULL)
4912 LIST_INSERT_BEFORE(next, valid_entry, next);
4913 else /* It's empty list, insert to head */
4914 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4917 pool->num_free += valid_entry->len;
4918 pool->num_alloc -= valid_entry->len;
4924 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4927 struct pool_entry *entry, *valid_entry;
4929 if (pool == NULL || num == 0) {
4930 PMD_DRV_LOG(ERR, "Invalid parameter");
4934 if (pool->num_free < num) {
4935 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4936 num, pool->num_free);
4941 /* Lookup in free list and find most fit one */
4942 LIST_FOREACH(entry, &pool->free_list, next) {
4943 if (entry->len >= num) {
4945 if (entry->len == num) {
4946 valid_entry = entry;
4949 if (valid_entry == NULL || valid_entry->len > entry->len)
4950 valid_entry = entry;
4954 /* Not find one to satisfy the request, return */
4955 if (valid_entry == NULL) {
4956 PMD_DRV_LOG(ERR, "No valid entry found");
4960 * The entry have equal queue number as requested,
4961 * remove it from alloc_list.
4963 if (valid_entry->len == num) {
4964 LIST_REMOVE(valid_entry, next);
4967 * The entry have more numbers than requested,
4968 * create a new entry for alloc_list and minus its
4969 * queue base and number in free_list.
4971 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4972 if (entry == NULL) {
4974 "Failed to allocate memory for resource pool");
4977 entry->base = valid_entry->base;
4979 valid_entry->base += num;
4980 valid_entry->len -= num;
4981 valid_entry = entry;
4984 /* Insert it into alloc list, not sorted */
4985 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4987 pool->num_free -= valid_entry->len;
4988 pool->num_alloc += valid_entry->len;
4990 return valid_entry->base + pool->base;
4994 * bitmap_is_subset - Check whether src2 is subset of src1
4997 bitmap_is_subset(uint8_t src1, uint8_t src2)
4999 return !((src1 ^ src2) & src2);
5002 static enum i40e_status_code
5003 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5005 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5007 /* If DCB is not supported, only default TC is supported */
5008 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5009 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5010 return I40E_NOT_SUPPORTED;
5013 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5015 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5016 hw->func_caps.enabled_tcmap, enabled_tcmap);
5017 return I40E_NOT_SUPPORTED;
5019 return I40E_SUCCESS;
5023 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5024 struct i40e_vsi_vlan_pvid_info *info)
5027 struct i40e_vsi_context ctxt;
5028 uint8_t vlan_flags = 0;
5031 if (vsi == NULL || info == NULL) {
5032 PMD_DRV_LOG(ERR, "invalid parameters");
5033 return I40E_ERR_PARAM;
5037 vsi->info.pvid = info->config.pvid;
5039 * If insert pvid is enabled, only tagged pkts are
5040 * allowed to be sent out.
5042 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5043 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5046 if (info->config.reject.tagged == 0)
5047 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5049 if (info->config.reject.untagged == 0)
5050 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5052 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5053 I40E_AQ_VSI_PVLAN_MODE_MASK);
5054 vsi->info.port_vlan_flags |= vlan_flags;
5055 vsi->info.valid_sections =
5056 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5057 memset(&ctxt, 0, sizeof(ctxt));
5058 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5059 ctxt.seid = vsi->seid;
5061 hw = I40E_VSI_TO_HW(vsi);
5062 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5063 if (ret != I40E_SUCCESS)
5064 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5070 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5072 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5074 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5076 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5077 if (ret != I40E_SUCCESS)
5081 PMD_DRV_LOG(ERR, "seid not valid");
5085 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5086 tc_bw_data.tc_valid_bits = enabled_tcmap;
5087 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5088 tc_bw_data.tc_bw_credits[i] =
5089 (enabled_tcmap & (1 << i)) ? 1 : 0;
5091 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5092 if (ret != I40E_SUCCESS) {
5093 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5097 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5098 sizeof(vsi->info.qs_handle));
5099 return I40E_SUCCESS;
5102 static enum i40e_status_code
5103 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5104 struct i40e_aqc_vsi_properties_data *info,
5105 uint8_t enabled_tcmap)
5107 enum i40e_status_code ret;
5108 int i, total_tc = 0;
5109 uint16_t qpnum_per_tc, bsf, qp_idx;
5111 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5112 if (ret != I40E_SUCCESS)
5115 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5116 if (enabled_tcmap & (1 << i))
5120 vsi->enabled_tc = enabled_tcmap;
5122 /* Number of queues per enabled TC */
5123 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5124 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5125 bsf = rte_bsf32(qpnum_per_tc);
5127 /* Adjust the queue number to actual queues that can be applied */
5128 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5129 vsi->nb_qps = qpnum_per_tc * total_tc;
5132 * Configure TC and queue mapping parameters, for enabled TC,
5133 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5134 * default queue will serve it.
5137 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5138 if (vsi->enabled_tc & (1 << i)) {
5139 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5140 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5141 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5142 qp_idx += qpnum_per_tc;
5144 info->tc_mapping[i] = 0;
5147 /* Associate queue number with VSI */
5148 if (vsi->type == I40E_VSI_SRIOV) {
5149 info->mapping_flags |=
5150 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5151 for (i = 0; i < vsi->nb_qps; i++)
5152 info->queue_mapping[i] =
5153 rte_cpu_to_le_16(vsi->base_queue + i);
5155 info->mapping_flags |=
5156 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5157 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5159 info->valid_sections |=
5160 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5162 return I40E_SUCCESS;
5166 i40e_veb_release(struct i40e_veb *veb)
5168 struct i40e_vsi *vsi;
5174 if (!TAILQ_EMPTY(&veb->head)) {
5175 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5178 /* associate_vsi field is NULL for floating VEB */
5179 if (veb->associate_vsi != NULL) {
5180 vsi = veb->associate_vsi;
5181 hw = I40E_VSI_TO_HW(vsi);
5183 vsi->uplink_seid = veb->uplink_seid;
5186 veb->associate_pf->main_vsi->floating_veb = NULL;
5187 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5190 i40e_aq_delete_element(hw, veb->seid, NULL);
5192 return I40E_SUCCESS;
5196 static struct i40e_veb *
5197 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5199 struct i40e_veb *veb;
5205 "veb setup failed, associated PF shouldn't null");
5208 hw = I40E_PF_TO_HW(pf);
5210 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5212 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5216 veb->associate_vsi = vsi;
5217 veb->associate_pf = pf;
5218 TAILQ_INIT(&veb->head);
5219 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5221 /* create floating veb if vsi is NULL */
5223 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5224 I40E_DEFAULT_TCMAP, false,
5225 &veb->seid, false, NULL);
5227 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5228 true, &veb->seid, false, NULL);
5231 if (ret != I40E_SUCCESS) {
5232 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5233 hw->aq.asq_last_status);
5236 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5238 /* get statistics index */
5239 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5240 &veb->stats_idx, NULL, NULL, NULL);
5241 if (ret != I40E_SUCCESS) {
5242 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5243 hw->aq.asq_last_status);
5246 /* Get VEB bandwidth, to be implemented */
5247 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5249 vsi->uplink_seid = veb->seid;
5258 i40e_vsi_release(struct i40e_vsi *vsi)
5262 struct i40e_vsi_list *vsi_list;
5265 struct i40e_mac_filter *f;
5266 uint16_t user_param;
5269 return I40E_SUCCESS;
5274 user_param = vsi->user_param;
5276 pf = I40E_VSI_TO_PF(vsi);
5277 hw = I40E_VSI_TO_HW(vsi);
5279 /* VSI has child to attach, release child first */
5281 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5282 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5285 i40e_veb_release(vsi->veb);
5288 if (vsi->floating_veb) {
5289 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5290 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5295 /* Remove all macvlan filters of the VSI */
5296 i40e_vsi_remove_all_macvlan_filter(vsi);
5297 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5300 if (vsi->type != I40E_VSI_MAIN &&
5301 ((vsi->type != I40E_VSI_SRIOV) ||
5302 !pf->floating_veb_list[user_param])) {
5303 /* Remove vsi from parent's sibling list */
5304 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5305 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5306 return I40E_ERR_PARAM;
5308 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5309 &vsi->sib_vsi_list, list);
5311 /* Remove all switch element of the VSI */
5312 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5313 if (ret != I40E_SUCCESS)
5314 PMD_DRV_LOG(ERR, "Failed to delete element");
5317 if ((vsi->type == I40E_VSI_SRIOV) &&
5318 pf->floating_veb_list[user_param]) {
5319 /* Remove vsi from parent's sibling list */
5320 if (vsi->parent_vsi == NULL ||
5321 vsi->parent_vsi->floating_veb == NULL) {
5322 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5323 return I40E_ERR_PARAM;
5325 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5326 &vsi->sib_vsi_list, list);
5328 /* Remove all switch element of the VSI */
5329 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5330 if (ret != I40E_SUCCESS)
5331 PMD_DRV_LOG(ERR, "Failed to delete element");
5334 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5336 if (vsi->type != I40E_VSI_SRIOV)
5337 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5340 return I40E_SUCCESS;
5344 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5346 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5347 struct i40e_aqc_remove_macvlan_element_data def_filter;
5348 struct i40e_mac_filter_info filter;
5351 if (vsi->type != I40E_VSI_MAIN)
5352 return I40E_ERR_CONFIG;
5353 memset(&def_filter, 0, sizeof(def_filter));
5354 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5356 def_filter.vlan_tag = 0;
5357 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5358 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5359 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5360 if (ret != I40E_SUCCESS) {
5361 struct i40e_mac_filter *f;
5362 struct rte_ether_addr *mac;
5365 "Cannot remove the default macvlan filter");
5366 /* It needs to add the permanent mac into mac list */
5367 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5369 PMD_DRV_LOG(ERR, "failed to allocate memory");
5370 return I40E_ERR_NO_MEMORY;
5372 mac = &f->mac_info.mac_addr;
5373 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5375 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5376 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5381 rte_memcpy(&filter.mac_addr,
5382 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5383 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5384 return i40e_vsi_add_mac(vsi, &filter);
5388 * i40e_vsi_get_bw_config - Query VSI BW Information
5389 * @vsi: the VSI to be queried
5391 * Returns 0 on success, negative value on failure
5393 static enum i40e_status_code
5394 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5396 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5397 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5398 struct i40e_hw *hw = &vsi->adapter->hw;
5403 memset(&bw_config, 0, sizeof(bw_config));
5404 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5405 if (ret != I40E_SUCCESS) {
5406 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5407 hw->aq.asq_last_status);
5411 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5412 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5413 &ets_sla_config, NULL);
5414 if (ret != I40E_SUCCESS) {
5416 "VSI failed to get TC bandwdith configuration %u",
5417 hw->aq.asq_last_status);
5421 /* store and print out BW info */
5422 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5423 vsi->bw_info.bw_max = bw_config.max_bw;
5424 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5425 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5426 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5427 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5429 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5430 vsi->bw_info.bw_ets_share_credits[i] =
5431 ets_sla_config.share_credits[i];
5432 vsi->bw_info.bw_ets_credits[i] =
5433 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5434 /* 4 bits per TC, 4th bit is reserved */
5435 vsi->bw_info.bw_ets_max[i] =
5436 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5437 RTE_LEN2MASK(3, uint8_t));
5438 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5439 vsi->bw_info.bw_ets_share_credits[i]);
5440 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5441 vsi->bw_info.bw_ets_credits[i]);
5442 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5443 vsi->bw_info.bw_ets_max[i]);
5446 return I40E_SUCCESS;
5449 /* i40e_enable_pf_lb
5450 * @pf: pointer to the pf structure
5452 * allow loopback on pf
5455 i40e_enable_pf_lb(struct i40e_pf *pf)
5457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5458 struct i40e_vsi_context ctxt;
5461 /* Use the FW API if FW >= v5.0 */
5462 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5463 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5467 memset(&ctxt, 0, sizeof(ctxt));
5468 ctxt.seid = pf->main_vsi_seid;
5469 ctxt.pf_num = hw->pf_id;
5470 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5472 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5473 ret, hw->aq.asq_last_status);
5476 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5477 ctxt.info.valid_sections =
5478 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5479 ctxt.info.switch_id |=
5480 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5482 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5484 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5485 hw->aq.asq_last_status);
5490 i40e_vsi_setup(struct i40e_pf *pf,
5491 enum i40e_vsi_type type,
5492 struct i40e_vsi *uplink_vsi,
5493 uint16_t user_param)
5495 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5496 struct i40e_vsi *vsi;
5497 struct i40e_mac_filter_info filter;
5499 struct i40e_vsi_context ctxt;
5500 struct rte_ether_addr broadcast =
5501 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5503 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5504 uplink_vsi == NULL) {
5506 "VSI setup failed, VSI link shouldn't be NULL");
5510 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5512 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5517 * 1.type is not MAIN and uplink vsi is not NULL
5518 * If uplink vsi didn't setup VEB, create one first under veb field
5519 * 2.type is SRIOV and the uplink is NULL
5520 * If floating VEB is NULL, create one veb under floating veb field
5523 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5524 uplink_vsi->veb == NULL) {
5525 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5527 if (uplink_vsi->veb == NULL) {
5528 PMD_DRV_LOG(ERR, "VEB setup failed");
5531 /* set ALLOWLOOPBACk on pf, when veb is created */
5532 i40e_enable_pf_lb(pf);
5535 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5536 pf->main_vsi->floating_veb == NULL) {
5537 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5539 if (pf->main_vsi->floating_veb == NULL) {
5540 PMD_DRV_LOG(ERR, "VEB setup failed");
5545 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5547 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5550 TAILQ_INIT(&vsi->mac_list);
5552 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5553 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5554 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5555 vsi->user_param = user_param;
5556 vsi->vlan_anti_spoof_on = 0;
5557 vsi->vlan_filter_on = 0;
5558 /* Allocate queues */
5559 switch (vsi->type) {
5560 case I40E_VSI_MAIN :
5561 vsi->nb_qps = pf->lan_nb_qps;
5563 case I40E_VSI_SRIOV :
5564 vsi->nb_qps = pf->vf_nb_qps;
5566 case I40E_VSI_VMDQ2:
5567 vsi->nb_qps = pf->vmdq_nb_qps;
5570 vsi->nb_qps = pf->fdir_nb_qps;
5576 * The filter status descriptor is reported in rx queue 0,
5577 * while the tx queue for fdir filter programming has no
5578 * such constraints, can be non-zero queues.
5579 * To simplify it, choose FDIR vsi use queue 0 pair.
5580 * To make sure it will use queue 0 pair, queue allocation
5581 * need be done before this function is called
5583 if (type != I40E_VSI_FDIR) {
5584 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5586 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5590 vsi->base_queue = ret;
5592 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5594 /* VF has MSIX interrupt in VF range, don't allocate here */
5595 if (type == I40E_VSI_MAIN) {
5596 if (pf->support_multi_driver) {
5597 /* If support multi-driver, need to use INT0 instead of
5598 * allocating from msix pool. The Msix pool is init from
5599 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5600 * to 1 without calling i40e_res_pool_alloc.
5605 ret = i40e_res_pool_alloc(&pf->msix_pool,
5606 RTE_MIN(vsi->nb_qps,
5607 RTE_MAX_RXTX_INTR_VEC_ID));
5610 "VSI MAIN %d get heap failed %d",
5612 goto fail_queue_alloc;
5614 vsi->msix_intr = ret;
5615 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5616 RTE_MAX_RXTX_INTR_VEC_ID);
5618 } else if (type != I40E_VSI_SRIOV) {
5619 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5621 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5622 goto fail_queue_alloc;
5624 vsi->msix_intr = ret;
5632 if (type == I40E_VSI_MAIN) {
5633 /* For main VSI, no need to add since it's default one */
5634 vsi->uplink_seid = pf->mac_seid;
5635 vsi->seid = pf->main_vsi_seid;
5636 /* Bind queues with specific MSIX interrupt */
5638 * Needs 2 interrupt at least, one for misc cause which will
5639 * enabled from OS side, Another for queues binding the
5640 * interrupt from device side only.
5643 /* Get default VSI parameters from hardware */
5644 memset(&ctxt, 0, sizeof(ctxt));
5645 ctxt.seid = vsi->seid;
5646 ctxt.pf_num = hw->pf_id;
5647 ctxt.uplink_seid = vsi->uplink_seid;
5649 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5650 if (ret != I40E_SUCCESS) {
5651 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5652 goto fail_msix_alloc;
5654 rte_memcpy(&vsi->info, &ctxt.info,
5655 sizeof(struct i40e_aqc_vsi_properties_data));
5656 vsi->vsi_id = ctxt.vsi_number;
5657 vsi->info.valid_sections = 0;
5659 /* Configure tc, enabled TC0 only */
5660 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5662 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5663 goto fail_msix_alloc;
5666 /* TC, queue mapping */
5667 memset(&ctxt, 0, sizeof(ctxt));
5668 vsi->info.valid_sections |=
5669 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5670 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5671 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5672 rte_memcpy(&ctxt.info, &vsi->info,
5673 sizeof(struct i40e_aqc_vsi_properties_data));
5674 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5675 I40E_DEFAULT_TCMAP);
5676 if (ret != I40E_SUCCESS) {
5678 "Failed to configure TC queue mapping");
5679 goto fail_msix_alloc;
5681 ctxt.seid = vsi->seid;
5682 ctxt.pf_num = hw->pf_id;
5683 ctxt.uplink_seid = vsi->uplink_seid;
5686 /* Update VSI parameters */
5687 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5688 if (ret != I40E_SUCCESS) {
5689 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5690 goto fail_msix_alloc;
5693 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5694 sizeof(vsi->info.tc_mapping));
5695 rte_memcpy(&vsi->info.queue_mapping,
5696 &ctxt.info.queue_mapping,
5697 sizeof(vsi->info.queue_mapping));
5698 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5699 vsi->info.valid_sections = 0;
5701 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5705 * Updating default filter settings are necessary to prevent
5706 * reception of tagged packets.
5707 * Some old firmware configurations load a default macvlan
5708 * filter which accepts both tagged and untagged packets.
5709 * The updating is to use a normal filter instead if needed.
5710 * For NVM 4.2.2 or after, the updating is not needed anymore.
5711 * The firmware with correct configurations load the default
5712 * macvlan filter which is expected and cannot be removed.
5714 i40e_update_default_filter_setting(vsi);
5715 i40e_config_qinq(hw, vsi);
5716 } else if (type == I40E_VSI_SRIOV) {
5717 memset(&ctxt, 0, sizeof(ctxt));
5719 * For other VSI, the uplink_seid equals to uplink VSI's
5720 * uplink_seid since they share same VEB
5722 if (uplink_vsi == NULL)
5723 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5725 vsi->uplink_seid = uplink_vsi->uplink_seid;
5726 ctxt.pf_num = hw->pf_id;
5727 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5728 ctxt.uplink_seid = vsi->uplink_seid;
5729 ctxt.connection_type = 0x1;
5730 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5732 /* Use the VEB configuration if FW >= v5.0 */
5733 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5734 /* Configure switch ID */
5735 ctxt.info.valid_sections |=
5736 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5737 ctxt.info.switch_id =
5738 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5741 /* Configure port/vlan */
5742 ctxt.info.valid_sections |=
5743 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5744 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5745 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5746 hw->func_caps.enabled_tcmap);
5747 if (ret != I40E_SUCCESS) {
5749 "Failed to configure TC queue mapping");
5750 goto fail_msix_alloc;
5753 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5754 ctxt.info.valid_sections |=
5755 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5757 * Since VSI is not created yet, only configure parameter,
5758 * will add vsi below.
5761 i40e_config_qinq(hw, vsi);
5762 } else if (type == I40E_VSI_VMDQ2) {
5763 memset(&ctxt, 0, sizeof(ctxt));
5765 * For other VSI, the uplink_seid equals to uplink VSI's
5766 * uplink_seid since they share same VEB
5768 vsi->uplink_seid = uplink_vsi->uplink_seid;
5769 ctxt.pf_num = hw->pf_id;
5771 ctxt.uplink_seid = vsi->uplink_seid;
5772 ctxt.connection_type = 0x1;
5773 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5775 ctxt.info.valid_sections |=
5776 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5777 /* user_param carries flag to enable loop back */
5779 ctxt.info.switch_id =
5780 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5781 ctxt.info.switch_id |=
5782 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5785 /* Configure port/vlan */
5786 ctxt.info.valid_sections |=
5787 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5788 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5789 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5790 I40E_DEFAULT_TCMAP);
5791 if (ret != I40E_SUCCESS) {
5793 "Failed to configure TC queue mapping");
5794 goto fail_msix_alloc;
5796 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5797 ctxt.info.valid_sections |=
5798 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5799 } else if (type == I40E_VSI_FDIR) {
5800 memset(&ctxt, 0, sizeof(ctxt));
5801 vsi->uplink_seid = uplink_vsi->uplink_seid;
5802 ctxt.pf_num = hw->pf_id;
5804 ctxt.uplink_seid = vsi->uplink_seid;
5805 ctxt.connection_type = 0x1; /* regular data port */
5806 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5807 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5808 I40E_DEFAULT_TCMAP);
5809 if (ret != I40E_SUCCESS) {
5811 "Failed to configure TC queue mapping.");
5812 goto fail_msix_alloc;
5814 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5815 ctxt.info.valid_sections |=
5816 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5818 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5819 goto fail_msix_alloc;
5822 if (vsi->type != I40E_VSI_MAIN) {
5823 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5824 if (ret != I40E_SUCCESS) {
5825 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5826 hw->aq.asq_last_status);
5827 goto fail_msix_alloc;
5829 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5830 vsi->info.valid_sections = 0;
5831 vsi->seid = ctxt.seid;
5832 vsi->vsi_id = ctxt.vsi_number;
5833 vsi->sib_vsi_list.vsi = vsi;
5834 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5835 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5836 &vsi->sib_vsi_list, list);
5838 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5839 &vsi->sib_vsi_list, list);
5843 /* MAC/VLAN configuration */
5844 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5845 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5847 ret = i40e_vsi_add_mac(vsi, &filter);
5848 if (ret != I40E_SUCCESS) {
5849 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5850 goto fail_msix_alloc;
5853 /* Get VSI BW information */
5854 i40e_vsi_get_bw_config(vsi);
5857 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5859 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5865 /* Configure vlan filter on or off */
5867 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5870 struct i40e_mac_filter *f;
5872 struct i40e_mac_filter_info *mac_filter;
5873 enum rte_mac_filter_type desired_filter;
5874 int ret = I40E_SUCCESS;
5877 /* Filter to match MAC and VLAN */
5878 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5880 /* Filter to match only MAC */
5881 desired_filter = RTE_MAC_PERFECT_MATCH;
5886 mac_filter = rte_zmalloc("mac_filter_info_data",
5887 num * sizeof(*mac_filter), 0);
5888 if (mac_filter == NULL) {
5889 PMD_DRV_LOG(ERR, "failed to allocate memory");
5890 return I40E_ERR_NO_MEMORY;
5895 /* Remove all existing mac */
5896 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5897 mac_filter[i] = f->mac_info;
5898 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5900 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5901 on ? "enable" : "disable");
5907 /* Override with new filter */
5908 for (i = 0; i < num; i++) {
5909 mac_filter[i].filter_type = desired_filter;
5910 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5912 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5913 on ? "enable" : "disable");
5919 rte_free(mac_filter);
5923 /* Configure vlan stripping on or off */
5925 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5927 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5928 struct i40e_vsi_context ctxt;
5930 int ret = I40E_SUCCESS;
5932 /* Check if it has been already on or off */
5933 if (vsi->info.valid_sections &
5934 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5936 if ((vsi->info.port_vlan_flags &
5937 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5938 return 0; /* already on */
5940 if ((vsi->info.port_vlan_flags &
5941 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5942 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5943 return 0; /* already off */
5948 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5950 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5951 vsi->info.valid_sections =
5952 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5953 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5954 vsi->info.port_vlan_flags |= vlan_flags;
5955 ctxt.seid = vsi->seid;
5956 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5957 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5959 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5960 on ? "enable" : "disable");
5966 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5968 struct rte_eth_dev_data *data = dev->data;
5972 /* Apply vlan offload setting */
5973 mask = ETH_VLAN_STRIP_MASK |
5974 ETH_VLAN_FILTER_MASK |
5975 ETH_VLAN_EXTEND_MASK;
5976 ret = i40e_vlan_offload_set(dev, mask);
5978 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5982 /* Apply pvid setting */
5983 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5984 data->dev_conf.txmode.hw_vlan_insert_pvid);
5986 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5992 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5994 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5996 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6000 i40e_update_flow_control(struct i40e_hw *hw)
6002 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6003 struct i40e_link_status link_status;
6004 uint32_t rxfc = 0, txfc = 0, reg;
6008 memset(&link_status, 0, sizeof(link_status));
6009 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6010 if (ret != I40E_SUCCESS) {
6011 PMD_DRV_LOG(ERR, "Failed to get link status information");
6012 goto write_reg; /* Disable flow control */
6015 an_info = hw->phy.link_info.an_info;
6016 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6017 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6018 ret = I40E_ERR_NOT_READY;
6019 goto write_reg; /* Disable flow control */
6022 * If link auto negotiation is enabled, flow control needs to
6023 * be configured according to it
6025 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6026 case I40E_LINK_PAUSE_RXTX:
6029 hw->fc.current_mode = I40E_FC_FULL;
6031 case I40E_AQ_LINK_PAUSE_RX:
6033 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6035 case I40E_AQ_LINK_PAUSE_TX:
6037 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6040 hw->fc.current_mode = I40E_FC_NONE;
6045 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6046 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6047 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6048 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6049 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6050 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6057 i40e_pf_setup(struct i40e_pf *pf)
6059 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6060 struct i40e_filter_control_settings settings;
6061 struct i40e_vsi *vsi;
6064 /* Clear all stats counters */
6065 pf->offset_loaded = FALSE;
6066 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6067 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6068 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6069 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6071 ret = i40e_pf_get_switch_config(pf);
6072 if (ret != I40E_SUCCESS) {
6073 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6077 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6079 PMD_INIT_LOG(WARNING,
6080 "failed to allocate switch domain for device %d", ret);
6082 if (pf->flags & I40E_FLAG_FDIR) {
6083 /* make queue allocated first, let FDIR use queue pair 0*/
6084 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6085 if (ret != I40E_FDIR_QUEUE_ID) {
6087 "queue allocation fails for FDIR: ret =%d",
6089 pf->flags &= ~I40E_FLAG_FDIR;
6092 /* main VSI setup */
6093 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6095 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6096 return I40E_ERR_NOT_READY;
6100 /* Configure filter control */
6101 memset(&settings, 0, sizeof(settings));
6102 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6103 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6104 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6105 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6107 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6108 hw->func_caps.rss_table_size);
6109 return I40E_ERR_PARAM;
6111 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6112 hw->func_caps.rss_table_size);
6113 pf->hash_lut_size = hw->func_caps.rss_table_size;
6115 /* Enable ethtype and macvlan filters */
6116 settings.enable_ethtype = TRUE;
6117 settings.enable_macvlan = TRUE;
6118 ret = i40e_set_filter_control(hw, &settings);
6120 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6123 /* Update flow control according to the auto negotiation */
6124 i40e_update_flow_control(hw);
6126 return I40E_SUCCESS;
6130 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6136 * Set or clear TX Queue Disable flags,
6137 * which is required by hardware.
6139 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6140 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6142 /* Wait until the request is finished */
6143 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6144 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6145 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6146 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6147 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6153 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6154 return I40E_SUCCESS; /* already on, skip next steps */
6156 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6157 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6159 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6160 return I40E_SUCCESS; /* already off, skip next steps */
6161 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6163 /* Write the register */
6164 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6165 /* Check the result */
6166 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6167 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6168 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6170 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6171 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6174 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6175 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6179 /* Check if it is timeout */
6180 if (j >= I40E_CHK_Q_ENA_COUNT) {
6181 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6182 (on ? "enable" : "disable"), q_idx);
6183 return I40E_ERR_TIMEOUT;
6186 return I40E_SUCCESS;
6189 /* Swith on or off the tx queues */
6191 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6193 struct rte_eth_dev_data *dev_data = pf->dev_data;
6194 struct i40e_tx_queue *txq;
6195 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6199 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6200 txq = dev_data->tx_queues[i];
6201 /* Don't operate the queue if not configured or
6202 * if starting only per queue */
6203 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6206 ret = i40e_dev_tx_queue_start(dev, i);
6208 ret = i40e_dev_tx_queue_stop(dev, i);
6209 if ( ret != I40E_SUCCESS)
6213 return I40E_SUCCESS;
6217 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6222 /* Wait until the request is finished */
6223 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6224 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6225 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6226 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6227 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6232 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6233 return I40E_SUCCESS; /* Already on, skip next steps */
6234 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6236 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6237 return I40E_SUCCESS; /* Already off, skip next steps */
6238 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6241 /* Write the register */
6242 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6243 /* Check the result */
6244 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6245 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6246 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6248 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6249 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6252 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6253 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6258 /* Check if it is timeout */
6259 if (j >= I40E_CHK_Q_ENA_COUNT) {
6260 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6261 (on ? "enable" : "disable"), q_idx);
6262 return I40E_ERR_TIMEOUT;
6265 return I40E_SUCCESS;
6267 /* Switch on or off the rx queues */
6269 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6271 struct rte_eth_dev_data *dev_data = pf->dev_data;
6272 struct i40e_rx_queue *rxq;
6273 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6277 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6278 rxq = dev_data->rx_queues[i];
6279 /* Don't operate the queue if not configured or
6280 * if starting only per queue */
6281 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6284 ret = i40e_dev_rx_queue_start(dev, i);
6286 ret = i40e_dev_rx_queue_stop(dev, i);
6287 if (ret != I40E_SUCCESS)
6291 return I40E_SUCCESS;
6294 /* Switch on or off all the rx/tx queues */
6296 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6301 /* enable rx queues before enabling tx queues */
6302 ret = i40e_dev_switch_rx_queues(pf, on);
6304 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6307 ret = i40e_dev_switch_tx_queues(pf, on);
6309 /* Stop tx queues before stopping rx queues */
6310 ret = i40e_dev_switch_tx_queues(pf, on);
6312 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6315 ret = i40e_dev_switch_rx_queues(pf, on);
6321 /* Initialize VSI for TX */
6323 i40e_dev_tx_init(struct i40e_pf *pf)
6325 struct rte_eth_dev_data *data = pf->dev_data;
6327 uint32_t ret = I40E_SUCCESS;
6328 struct i40e_tx_queue *txq;
6330 for (i = 0; i < data->nb_tx_queues; i++) {
6331 txq = data->tx_queues[i];
6332 if (!txq || !txq->q_set)
6334 ret = i40e_tx_queue_init(txq);
6335 if (ret != I40E_SUCCESS)
6338 if (ret == I40E_SUCCESS)
6339 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6345 /* Initialize VSI for RX */
6347 i40e_dev_rx_init(struct i40e_pf *pf)
6349 struct rte_eth_dev_data *data = pf->dev_data;
6350 int ret = I40E_SUCCESS;
6352 struct i40e_rx_queue *rxq;
6354 i40e_pf_config_mq_rx(pf);
6355 for (i = 0; i < data->nb_rx_queues; i++) {
6356 rxq = data->rx_queues[i];
6357 if (!rxq || !rxq->q_set)
6360 ret = i40e_rx_queue_init(rxq);
6361 if (ret != I40E_SUCCESS) {
6363 "Failed to do RX queue initialization");
6367 if (ret == I40E_SUCCESS)
6368 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6375 i40e_dev_rxtx_init(struct i40e_pf *pf)
6379 err = i40e_dev_tx_init(pf);
6381 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6384 err = i40e_dev_rx_init(pf);
6386 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6394 i40e_vmdq_setup(struct rte_eth_dev *dev)
6396 struct rte_eth_conf *conf = &dev->data->dev_conf;
6397 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6398 int i, err, conf_vsis, j, loop;
6399 struct i40e_vsi *vsi;
6400 struct i40e_vmdq_info *vmdq_info;
6401 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6405 * Disable interrupt to avoid message from VF. Furthermore, it will
6406 * avoid race condition in VSI creation/destroy.
6408 i40e_pf_disable_irq0(hw);
6410 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6411 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6415 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6416 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6417 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6418 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6419 pf->max_nb_vmdq_vsi);
6423 if (pf->vmdq != NULL) {
6424 PMD_INIT_LOG(INFO, "VMDQ already configured");
6428 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6429 sizeof(*vmdq_info) * conf_vsis, 0);
6431 if (pf->vmdq == NULL) {
6432 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6436 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6438 /* Create VMDQ VSI */
6439 for (i = 0; i < conf_vsis; i++) {
6440 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6441 vmdq_conf->enable_loop_back);
6443 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6447 vmdq_info = &pf->vmdq[i];
6449 vmdq_info->vsi = vsi;
6451 pf->nb_cfg_vmdq_vsi = conf_vsis;
6453 /* Configure Vlan */
6454 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6455 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6456 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6457 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6458 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6459 vmdq_conf->pool_map[i].vlan_id, j);
6461 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6462 vmdq_conf->pool_map[i].vlan_id);
6464 PMD_INIT_LOG(ERR, "Failed to add vlan");
6472 i40e_pf_enable_irq0(hw);
6477 for (i = 0; i < conf_vsis; i++)
6478 if (pf->vmdq[i].vsi == NULL)
6481 i40e_vsi_release(pf->vmdq[i].vsi);
6485 i40e_pf_enable_irq0(hw);
6490 i40e_stat_update_32(struct i40e_hw *hw,
6498 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6502 if (new_data >= *offset)
6503 *stat = (uint64_t)(new_data - *offset);
6505 *stat = (uint64_t)((new_data +
6506 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6510 i40e_stat_update_48(struct i40e_hw *hw,
6519 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6520 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6521 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6526 if (new_data >= *offset)
6527 *stat = new_data - *offset;
6529 *stat = (uint64_t)((new_data +
6530 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6532 *stat &= I40E_48_BIT_MASK;
6537 i40e_pf_disable_irq0(struct i40e_hw *hw)
6539 /* Disable all interrupt types */
6540 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6541 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6542 I40E_WRITE_FLUSH(hw);
6547 i40e_pf_enable_irq0(struct i40e_hw *hw)
6549 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6550 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6551 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6552 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6553 I40E_WRITE_FLUSH(hw);
6557 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6559 /* read pending request and disable first */
6560 i40e_pf_disable_irq0(hw);
6561 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6562 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6563 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6566 /* Link no queues with irq0 */
6567 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6568 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6572 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6575 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6578 uint32_t index, offset, val;
6583 * Try to find which VF trigger a reset, use absolute VF id to access
6584 * since the reg is global register.
6586 for (i = 0; i < pf->vf_num; i++) {
6587 abs_vf_id = hw->func_caps.vf_base_id + i;
6588 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6589 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6590 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6591 /* VFR event occurred */
6592 if (val & (0x1 << offset)) {
6595 /* Clear the event first */
6596 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6598 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6600 * Only notify a VF reset event occurred,
6601 * don't trigger another SW reset
6603 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6604 if (ret != I40E_SUCCESS)
6605 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6611 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6616 for (i = 0; i < pf->vf_num; i++)
6617 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6621 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6623 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6624 struct i40e_arq_event_info info;
6625 uint16_t pending, opcode;
6628 info.buf_len = I40E_AQ_BUF_SZ;
6629 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6630 if (!info.msg_buf) {
6631 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6637 ret = i40e_clean_arq_element(hw, &info, &pending);
6639 if (ret != I40E_SUCCESS) {
6641 "Failed to read msg from AdminQ, aq_err: %u",
6642 hw->aq.asq_last_status);
6645 opcode = rte_le_to_cpu_16(info.desc.opcode);
6648 case i40e_aqc_opc_send_msg_to_pf:
6649 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6650 i40e_pf_host_handle_vf_msg(dev,
6651 rte_le_to_cpu_16(info.desc.retval),
6652 rte_le_to_cpu_32(info.desc.cookie_high),
6653 rte_le_to_cpu_32(info.desc.cookie_low),
6657 case i40e_aqc_opc_get_link_status:
6658 ret = i40e_dev_link_update(dev, 0);
6660 _rte_eth_dev_callback_process(dev,
6661 RTE_ETH_EVENT_INTR_LSC, NULL);
6664 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6669 rte_free(info.msg_buf);
6673 * Interrupt handler triggered by NIC for handling
6674 * specific interrupt.
6677 * Pointer to interrupt handle.
6679 * The address of parameter (struct rte_eth_dev *) regsitered before.
6685 i40e_dev_interrupt_handler(void *param)
6687 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691 /* Disable interrupt */
6692 i40e_pf_disable_irq0(hw);
6694 /* read out interrupt causes */
6695 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6697 /* No interrupt event indicated */
6698 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6699 PMD_DRV_LOG(INFO, "No interrupt event");
6702 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6703 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6704 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6705 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6706 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6707 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6708 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6709 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6710 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6711 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6712 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6713 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6714 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6715 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6717 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6718 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6719 i40e_dev_handle_vfr_event(dev);
6721 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6722 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6723 i40e_dev_handle_aq_msg(dev);
6727 /* Enable interrupt */
6728 i40e_pf_enable_irq0(hw);
6732 i40e_dev_alarm_handler(void *param)
6734 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6735 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6738 /* Disable interrupt */
6739 i40e_pf_disable_irq0(hw);
6741 /* read out interrupt causes */
6742 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6744 /* No interrupt event indicated */
6745 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6747 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6748 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6749 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6750 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6751 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6752 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6753 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6754 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6755 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6756 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6757 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6758 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6759 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6760 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6762 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6763 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6764 i40e_dev_handle_vfr_event(dev);
6766 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6767 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6768 i40e_dev_handle_aq_msg(dev);
6772 /* Enable interrupt */
6773 i40e_pf_enable_irq0(hw);
6774 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6775 i40e_dev_alarm_handler, dev);
6779 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6780 struct i40e_macvlan_filter *filter,
6783 int ele_num, ele_buff_size;
6784 int num, actual_num, i;
6786 int ret = I40E_SUCCESS;
6787 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6788 struct i40e_aqc_add_macvlan_element_data *req_list;
6790 if (filter == NULL || total == 0)
6791 return I40E_ERR_PARAM;
6792 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6793 ele_buff_size = hw->aq.asq_buf_size;
6795 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6796 if (req_list == NULL) {
6797 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6798 return I40E_ERR_NO_MEMORY;
6803 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6804 memset(req_list, 0, ele_buff_size);
6806 for (i = 0; i < actual_num; i++) {
6807 rte_memcpy(req_list[i].mac_addr,
6808 &filter[num + i].macaddr, ETH_ADDR_LEN);
6809 req_list[i].vlan_tag =
6810 rte_cpu_to_le_16(filter[num + i].vlan_id);
6812 switch (filter[num + i].filter_type) {
6813 case RTE_MAC_PERFECT_MATCH:
6814 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6815 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6817 case RTE_MACVLAN_PERFECT_MATCH:
6818 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6820 case RTE_MAC_HASH_MATCH:
6821 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6822 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6824 case RTE_MACVLAN_HASH_MATCH:
6825 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6828 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6829 ret = I40E_ERR_PARAM;
6833 req_list[i].queue_number = 0;
6835 req_list[i].flags = rte_cpu_to_le_16(flags);
6838 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6840 if (ret != I40E_SUCCESS) {
6841 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6845 } while (num < total);
6853 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6854 struct i40e_macvlan_filter *filter,
6857 int ele_num, ele_buff_size;
6858 int num, actual_num, i;
6860 int ret = I40E_SUCCESS;
6861 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6862 struct i40e_aqc_remove_macvlan_element_data *req_list;
6864 if (filter == NULL || total == 0)
6865 return I40E_ERR_PARAM;
6867 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6868 ele_buff_size = hw->aq.asq_buf_size;
6870 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6871 if (req_list == NULL) {
6872 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6873 return I40E_ERR_NO_MEMORY;
6878 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6879 memset(req_list, 0, ele_buff_size);
6881 for (i = 0; i < actual_num; i++) {
6882 rte_memcpy(req_list[i].mac_addr,
6883 &filter[num + i].macaddr, ETH_ADDR_LEN);
6884 req_list[i].vlan_tag =
6885 rte_cpu_to_le_16(filter[num + i].vlan_id);
6887 switch (filter[num + i].filter_type) {
6888 case RTE_MAC_PERFECT_MATCH:
6889 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6890 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6892 case RTE_MACVLAN_PERFECT_MATCH:
6893 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6895 case RTE_MAC_HASH_MATCH:
6896 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6897 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6899 case RTE_MACVLAN_HASH_MATCH:
6900 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6903 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6904 ret = I40E_ERR_PARAM;
6907 req_list[i].flags = rte_cpu_to_le_16(flags);
6910 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6912 if (ret != I40E_SUCCESS) {
6913 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6917 } while (num < total);
6924 /* Find out specific MAC filter */
6925 static struct i40e_mac_filter *
6926 i40e_find_mac_filter(struct i40e_vsi *vsi,
6927 struct rte_ether_addr *macaddr)
6929 struct i40e_mac_filter *f;
6931 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6932 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6940 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6943 uint32_t vid_idx, vid_bit;
6945 if (vlan_id > ETH_VLAN_ID_MAX)
6948 vid_idx = I40E_VFTA_IDX(vlan_id);
6949 vid_bit = I40E_VFTA_BIT(vlan_id);
6951 if (vsi->vfta[vid_idx] & vid_bit)
6958 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6959 uint16_t vlan_id, bool on)
6961 uint32_t vid_idx, vid_bit;
6963 vid_idx = I40E_VFTA_IDX(vlan_id);
6964 vid_bit = I40E_VFTA_BIT(vlan_id);
6967 vsi->vfta[vid_idx] |= vid_bit;
6969 vsi->vfta[vid_idx] &= ~vid_bit;
6973 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6974 uint16_t vlan_id, bool on)
6976 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6977 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6980 if (vlan_id > ETH_VLAN_ID_MAX)
6983 i40e_store_vlan_filter(vsi, vlan_id, on);
6985 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6988 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6991 ret = i40e_aq_add_vlan(hw, vsi->seid,
6992 &vlan_data, 1, NULL);
6993 if (ret != I40E_SUCCESS)
6994 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6996 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6997 &vlan_data, 1, NULL);
6998 if (ret != I40E_SUCCESS)
7000 "Failed to remove vlan filter");
7005 * Find all vlan options for specific mac addr,
7006 * return with actual vlan found.
7009 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7010 struct i40e_macvlan_filter *mv_f,
7011 int num, struct rte_ether_addr *addr)
7017 * Not to use i40e_find_vlan_filter to decrease the loop time,
7018 * although the code looks complex.
7020 if (num < vsi->vlan_num)
7021 return I40E_ERR_PARAM;
7024 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7026 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7027 if (vsi->vfta[j] & (1 << k)) {
7030 "vlan number doesn't match");
7031 return I40E_ERR_PARAM;
7033 rte_memcpy(&mv_f[i].macaddr,
7034 addr, ETH_ADDR_LEN);
7036 j * I40E_UINT32_BIT_SIZE + k;
7042 return I40E_SUCCESS;
7046 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7047 struct i40e_macvlan_filter *mv_f,
7052 struct i40e_mac_filter *f;
7054 if (num < vsi->mac_num)
7055 return I40E_ERR_PARAM;
7057 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7059 PMD_DRV_LOG(ERR, "buffer number not match");
7060 return I40E_ERR_PARAM;
7062 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7064 mv_f[i].vlan_id = vlan;
7065 mv_f[i].filter_type = f->mac_info.filter_type;
7069 return I40E_SUCCESS;
7073 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7076 struct i40e_mac_filter *f;
7077 struct i40e_macvlan_filter *mv_f;
7078 int ret = I40E_SUCCESS;
7080 if (vsi == NULL || vsi->mac_num == 0)
7081 return I40E_ERR_PARAM;
7083 /* Case that no vlan is set */
7084 if (vsi->vlan_num == 0)
7087 num = vsi->mac_num * vsi->vlan_num;
7089 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7091 PMD_DRV_LOG(ERR, "failed to allocate memory");
7092 return I40E_ERR_NO_MEMORY;
7096 if (vsi->vlan_num == 0) {
7097 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7098 rte_memcpy(&mv_f[i].macaddr,
7099 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7100 mv_f[i].filter_type = f->mac_info.filter_type;
7101 mv_f[i].vlan_id = 0;
7105 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7106 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7107 vsi->vlan_num, &f->mac_info.mac_addr);
7108 if (ret != I40E_SUCCESS)
7110 for (j = i; j < i + vsi->vlan_num; j++)
7111 mv_f[j].filter_type = f->mac_info.filter_type;
7116 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7124 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7126 struct i40e_macvlan_filter *mv_f;
7128 int ret = I40E_SUCCESS;
7130 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7131 return I40E_ERR_PARAM;
7133 /* If it's already set, just return */
7134 if (i40e_find_vlan_filter(vsi,vlan))
7135 return I40E_SUCCESS;
7137 mac_num = vsi->mac_num;
7140 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7141 return I40E_ERR_PARAM;
7144 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7147 PMD_DRV_LOG(ERR, "failed to allocate memory");
7148 return I40E_ERR_NO_MEMORY;
7151 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7153 if (ret != I40E_SUCCESS)
7156 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7158 if (ret != I40E_SUCCESS)
7161 i40e_set_vlan_filter(vsi, vlan, 1);
7171 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7173 struct i40e_macvlan_filter *mv_f;
7175 int ret = I40E_SUCCESS;
7178 * Vlan 0 is the generic filter for untagged packets
7179 * and can't be removed.
7181 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7182 return I40E_ERR_PARAM;
7184 /* If can't find it, just return */
7185 if (!i40e_find_vlan_filter(vsi, vlan))
7186 return I40E_ERR_PARAM;
7188 mac_num = vsi->mac_num;
7191 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7192 return I40E_ERR_PARAM;
7195 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7198 PMD_DRV_LOG(ERR, "failed to allocate memory");
7199 return I40E_ERR_NO_MEMORY;
7202 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7204 if (ret != I40E_SUCCESS)
7207 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7209 if (ret != I40E_SUCCESS)
7212 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7213 if (vsi->vlan_num == 1) {
7214 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7215 if (ret != I40E_SUCCESS)
7218 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7219 if (ret != I40E_SUCCESS)
7223 i40e_set_vlan_filter(vsi, vlan, 0);
7233 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7235 struct i40e_mac_filter *f;
7236 struct i40e_macvlan_filter *mv_f;
7237 int i, vlan_num = 0;
7238 int ret = I40E_SUCCESS;
7240 /* If it's add and we've config it, return */
7241 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7243 return I40E_SUCCESS;
7244 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7245 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7248 * If vlan_num is 0, that's the first time to add mac,
7249 * set mask for vlan_id 0.
7251 if (vsi->vlan_num == 0) {
7252 i40e_set_vlan_filter(vsi, 0, 1);
7255 vlan_num = vsi->vlan_num;
7256 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7257 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7260 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7262 PMD_DRV_LOG(ERR, "failed to allocate memory");
7263 return I40E_ERR_NO_MEMORY;
7266 for (i = 0; i < vlan_num; i++) {
7267 mv_f[i].filter_type = mac_filter->filter_type;
7268 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7272 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7273 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7274 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7275 &mac_filter->mac_addr);
7276 if (ret != I40E_SUCCESS)
7280 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7281 if (ret != I40E_SUCCESS)
7284 /* Add the mac addr into mac list */
7285 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7287 PMD_DRV_LOG(ERR, "failed to allocate memory");
7288 ret = I40E_ERR_NO_MEMORY;
7291 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7293 f->mac_info.filter_type = mac_filter->filter_type;
7294 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7305 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7307 struct i40e_mac_filter *f;
7308 struct i40e_macvlan_filter *mv_f;
7310 enum rte_mac_filter_type filter_type;
7311 int ret = I40E_SUCCESS;
7313 /* Can't find it, return an error */
7314 f = i40e_find_mac_filter(vsi, addr);
7316 return I40E_ERR_PARAM;
7318 vlan_num = vsi->vlan_num;
7319 filter_type = f->mac_info.filter_type;
7320 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7321 filter_type == RTE_MACVLAN_HASH_MATCH) {
7322 if (vlan_num == 0) {
7323 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7324 return I40E_ERR_PARAM;
7326 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7327 filter_type == RTE_MAC_HASH_MATCH)
7330 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7332 PMD_DRV_LOG(ERR, "failed to allocate memory");
7333 return I40E_ERR_NO_MEMORY;
7336 for (i = 0; i < vlan_num; i++) {
7337 mv_f[i].filter_type = filter_type;
7338 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7341 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7342 filter_type == RTE_MACVLAN_HASH_MATCH) {
7343 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7344 if (ret != I40E_SUCCESS)
7348 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7349 if (ret != I40E_SUCCESS)
7352 /* Remove the mac addr into mac list */
7353 TAILQ_REMOVE(&vsi->mac_list, f, next);
7363 /* Configure hash enable flags for RSS */
7365 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7373 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7374 if (flags & (1ULL << i))
7375 hena |= adapter->pctypes_tbl[i];
7381 /* Parse the hash enable flags */
7383 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7385 uint64_t rss_hf = 0;
7391 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7392 if (flags & adapter->pctypes_tbl[i])
7393 rss_hf |= (1ULL << i);
7400 i40e_pf_disable_rss(struct i40e_pf *pf)
7402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7404 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7405 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7406 I40E_WRITE_FLUSH(hw);
7410 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7412 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7413 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7414 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7415 I40E_VFQF_HKEY_MAX_INDEX :
7416 I40E_PFQF_HKEY_MAX_INDEX;
7419 if (!key || key_len == 0) {
7420 PMD_DRV_LOG(DEBUG, "No key to be configured");
7422 } else if (key_len != (key_idx + 1) *
7424 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7428 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7429 struct i40e_aqc_get_set_rss_key_data *key_dw =
7430 (struct i40e_aqc_get_set_rss_key_data *)key;
7432 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7434 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7436 uint32_t *hash_key = (uint32_t *)key;
7439 if (vsi->type == I40E_VSI_SRIOV) {
7440 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7443 I40E_VFQF_HKEY1(i, vsi->user_param),
7447 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7448 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7451 I40E_WRITE_FLUSH(hw);
7458 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7460 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7461 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7465 if (!key || !key_len)
7468 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7469 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7470 (struct i40e_aqc_get_set_rss_key_data *)key);
7472 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7476 uint32_t *key_dw = (uint32_t *)key;
7479 if (vsi->type == I40E_VSI_SRIOV) {
7480 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7481 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7482 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7484 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7487 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7488 reg = I40E_PFQF_HKEY(i);
7489 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7491 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7499 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7501 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7505 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7506 rss_conf->rss_key_len);
7510 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7511 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7512 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7513 I40E_WRITE_FLUSH(hw);
7519 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7520 struct rte_eth_rss_conf *rss_conf)
7522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7523 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7524 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7527 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7528 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7530 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7531 if (rss_hf != 0) /* Enable RSS */
7533 return 0; /* Nothing to do */
7536 if (rss_hf == 0) /* Disable RSS */
7539 return i40e_hw_rss_hash_set(pf, rss_conf);
7543 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7544 struct rte_eth_rss_conf *rss_conf)
7546 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7554 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7555 &rss_conf->rss_key_len);
7559 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7560 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7561 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7567 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7569 switch (filter_type) {
7570 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7571 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7573 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7574 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7576 case RTE_TUNNEL_FILTER_IMAC_TENID:
7577 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7579 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7580 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7582 case ETH_TUNNEL_FILTER_IMAC:
7583 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7585 case ETH_TUNNEL_FILTER_OIP:
7586 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7588 case ETH_TUNNEL_FILTER_IIP:
7589 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7592 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7599 /* Convert tunnel filter structure */
7601 i40e_tunnel_filter_convert(
7602 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7603 struct i40e_tunnel_filter *tunnel_filter)
7605 rte_ether_addr_copy((struct rte_ether_addr *)
7606 &cld_filter->element.outer_mac,
7607 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7608 rte_ether_addr_copy((struct rte_ether_addr *)
7609 &cld_filter->element.inner_mac,
7610 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7611 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7612 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7613 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7614 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7615 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7617 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7618 tunnel_filter->input.flags = cld_filter->element.flags;
7619 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7620 tunnel_filter->queue = cld_filter->element.queue_number;
7621 rte_memcpy(tunnel_filter->input.general_fields,
7622 cld_filter->general_fields,
7623 sizeof(cld_filter->general_fields));
7628 /* Check if there exists the tunnel filter */
7629 struct i40e_tunnel_filter *
7630 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7631 const struct i40e_tunnel_filter_input *input)
7635 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7639 return tunnel_rule->hash_map[ret];
7642 /* Add a tunnel filter into the SW list */
7644 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7645 struct i40e_tunnel_filter *tunnel_filter)
7647 struct i40e_tunnel_rule *rule = &pf->tunnel;
7650 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7653 "Failed to insert tunnel filter to hash table %d!",
7657 rule->hash_map[ret] = tunnel_filter;
7659 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7664 /* Delete a tunnel filter from the SW list */
7666 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7667 struct i40e_tunnel_filter_input *input)
7669 struct i40e_tunnel_rule *rule = &pf->tunnel;
7670 struct i40e_tunnel_filter *tunnel_filter;
7673 ret = rte_hash_del_key(rule->hash_table, input);
7676 "Failed to delete tunnel filter to hash table %d!",
7680 tunnel_filter = rule->hash_map[ret];
7681 rule->hash_map[ret] = NULL;
7683 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7684 rte_free(tunnel_filter);
7690 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7691 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7695 uint32_t ipv4_addr, ipv4_addr_le;
7696 uint8_t i, tun_type = 0;
7697 /* internal varialbe to convert ipv6 byte order */
7698 uint32_t convert_ipv6[4];
7700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7701 struct i40e_vsi *vsi = pf->main_vsi;
7702 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7703 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7704 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7705 struct i40e_tunnel_filter *tunnel, *node;
7706 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7708 cld_filter = rte_zmalloc("tunnel_filter",
7709 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7712 if (NULL == cld_filter) {
7713 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7716 pfilter = cld_filter;
7718 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7719 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7720 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7721 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7723 pfilter->element.inner_vlan =
7724 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7725 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7726 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7727 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7728 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7729 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7731 sizeof(pfilter->element.ipaddr.v4.data));
7733 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7734 for (i = 0; i < 4; i++) {
7736 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7738 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7740 sizeof(pfilter->element.ipaddr.v6.data));
7743 /* check tunneled type */
7744 switch (tunnel_filter->tunnel_type) {
7745 case RTE_TUNNEL_TYPE_VXLAN:
7746 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7748 case RTE_TUNNEL_TYPE_NVGRE:
7749 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7751 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7752 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7754 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7755 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7758 /* Other tunnel types is not supported. */
7759 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7760 rte_free(cld_filter);
7764 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7765 &pfilter->element.flags);
7767 rte_free(cld_filter);
7771 pfilter->element.flags |= rte_cpu_to_le_16(
7772 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7773 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7774 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7775 pfilter->element.queue_number =
7776 rte_cpu_to_le_16(tunnel_filter->queue_id);
7778 /* Check if there is the filter in SW list */
7779 memset(&check_filter, 0, sizeof(check_filter));
7780 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7781 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7783 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7784 rte_free(cld_filter);
7788 if (!add && !node) {
7789 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7790 rte_free(cld_filter);
7795 ret = i40e_aq_add_cloud_filters(hw,
7796 vsi->seid, &cld_filter->element, 1);
7798 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7799 rte_free(cld_filter);
7802 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7803 if (tunnel == NULL) {
7804 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7805 rte_free(cld_filter);
7809 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7810 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7814 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7815 &cld_filter->element, 1);
7817 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7818 rte_free(cld_filter);
7821 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7824 rte_free(cld_filter);
7828 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7829 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7830 #define I40E_TR_GENEVE_KEY_MASK 0x8
7831 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7832 #define I40E_TR_GRE_KEY_MASK 0x400
7833 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7834 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7837 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7839 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7840 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7841 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7842 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7843 enum i40e_status_code status = I40E_SUCCESS;
7845 if (pf->support_multi_driver) {
7846 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7847 return I40E_NOT_SUPPORTED;
7850 memset(&filter_replace, 0,
7851 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7852 memset(&filter_replace_buf, 0,
7853 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7855 /* create L1 filter */
7856 filter_replace.old_filter_type =
7857 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7858 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7859 filter_replace.tr_bit = 0;
7861 /* Prepare the buffer, 3 entries */
7862 filter_replace_buf.data[0] =
7863 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7864 filter_replace_buf.data[0] |=
7865 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7866 filter_replace_buf.data[2] = 0xFF;
7867 filter_replace_buf.data[3] = 0xFF;
7868 filter_replace_buf.data[4] =
7869 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7870 filter_replace_buf.data[4] |=
7871 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7872 filter_replace_buf.data[7] = 0xF0;
7873 filter_replace_buf.data[8]
7874 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7875 filter_replace_buf.data[8] |=
7876 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7877 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7878 I40E_TR_GENEVE_KEY_MASK |
7879 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7880 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7881 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7882 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7884 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7885 &filter_replace_buf);
7886 if (!status && (filter_replace.old_filter_type !=
7887 filter_replace.new_filter_type))
7888 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7889 " original: 0x%x, new: 0x%x",
7891 filter_replace.old_filter_type,
7892 filter_replace.new_filter_type);
7898 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7900 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7901 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7902 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7903 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7904 enum i40e_status_code status = I40E_SUCCESS;
7906 if (pf->support_multi_driver) {
7907 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7908 return I40E_NOT_SUPPORTED;
7912 memset(&filter_replace, 0,
7913 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7914 memset(&filter_replace_buf, 0,
7915 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7916 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7917 I40E_AQC_MIRROR_CLOUD_FILTER;
7918 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7919 filter_replace.new_filter_type =
7920 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7921 /* Prepare the buffer, 2 entries */
7922 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7923 filter_replace_buf.data[0] |=
7924 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7925 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7926 filter_replace_buf.data[4] |=
7927 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7928 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7929 &filter_replace_buf);
7932 if (filter_replace.old_filter_type !=
7933 filter_replace.new_filter_type)
7934 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7935 " original: 0x%x, new: 0x%x",
7937 filter_replace.old_filter_type,
7938 filter_replace.new_filter_type);
7941 memset(&filter_replace, 0,
7942 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7943 memset(&filter_replace_buf, 0,
7944 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7946 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7947 I40E_AQC_MIRROR_CLOUD_FILTER;
7948 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7949 filter_replace.new_filter_type =
7950 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7951 /* Prepare the buffer, 2 entries */
7952 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7953 filter_replace_buf.data[0] |=
7954 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7955 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7956 filter_replace_buf.data[4] |=
7957 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7959 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7960 &filter_replace_buf);
7961 if (!status && (filter_replace.old_filter_type !=
7962 filter_replace.new_filter_type))
7963 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7964 " original: 0x%x, new: 0x%x",
7966 filter_replace.old_filter_type,
7967 filter_replace.new_filter_type);
7972 static enum i40e_status_code
7973 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7975 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7976 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7977 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7978 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7979 enum i40e_status_code status = I40E_SUCCESS;
7981 if (pf->support_multi_driver) {
7982 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7983 return I40E_NOT_SUPPORTED;
7987 memset(&filter_replace, 0,
7988 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7989 memset(&filter_replace_buf, 0,
7990 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7991 /* create L1 filter */
7992 filter_replace.old_filter_type =
7993 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7994 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7995 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7996 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7997 /* Prepare the buffer, 2 entries */
7998 filter_replace_buf.data[0] =
7999 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8000 filter_replace_buf.data[0] |=
8001 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8002 filter_replace_buf.data[2] = 0xFF;
8003 filter_replace_buf.data[3] = 0xFF;
8004 filter_replace_buf.data[4] =
8005 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8006 filter_replace_buf.data[4] |=
8007 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008 filter_replace_buf.data[6] = 0xFF;
8009 filter_replace_buf.data[7] = 0xFF;
8010 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8011 &filter_replace_buf);
8014 if (filter_replace.old_filter_type !=
8015 filter_replace.new_filter_type)
8016 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8017 " original: 0x%x, new: 0x%x",
8019 filter_replace.old_filter_type,
8020 filter_replace.new_filter_type);
8023 memset(&filter_replace, 0,
8024 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8025 memset(&filter_replace_buf, 0,
8026 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8027 /* create L1 filter */
8028 filter_replace.old_filter_type =
8029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8030 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8031 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8032 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8033 /* Prepare the buffer, 2 entries */
8034 filter_replace_buf.data[0] =
8035 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8036 filter_replace_buf.data[0] |=
8037 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8038 filter_replace_buf.data[2] = 0xFF;
8039 filter_replace_buf.data[3] = 0xFF;
8040 filter_replace_buf.data[4] =
8041 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8042 filter_replace_buf.data[4] |=
8043 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8044 filter_replace_buf.data[6] = 0xFF;
8045 filter_replace_buf.data[7] = 0xFF;
8047 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8048 &filter_replace_buf);
8049 if (!status && (filter_replace.old_filter_type !=
8050 filter_replace.new_filter_type))
8051 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8052 " original: 0x%x, new: 0x%x",
8054 filter_replace.old_filter_type,
8055 filter_replace.new_filter_type);
8061 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8063 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8064 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8065 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8066 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8067 enum i40e_status_code status = I40E_SUCCESS;
8069 if (pf->support_multi_driver) {
8070 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8071 return I40E_NOT_SUPPORTED;
8075 memset(&filter_replace, 0,
8076 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8077 memset(&filter_replace_buf, 0,
8078 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8079 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8080 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8081 filter_replace.new_filter_type =
8082 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8083 /* Prepare the buffer, 2 entries */
8084 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8085 filter_replace_buf.data[0] |=
8086 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8087 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8088 filter_replace_buf.data[4] |=
8089 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8090 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8091 &filter_replace_buf);
8094 if (filter_replace.old_filter_type !=
8095 filter_replace.new_filter_type)
8096 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8097 " original: 0x%x, new: 0x%x",
8099 filter_replace.old_filter_type,
8100 filter_replace.new_filter_type);
8103 memset(&filter_replace, 0,
8104 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8105 memset(&filter_replace_buf, 0,
8106 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8107 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8108 filter_replace.old_filter_type =
8109 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8110 filter_replace.new_filter_type =
8111 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8112 /* Prepare the buffer, 2 entries */
8113 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8114 filter_replace_buf.data[0] |=
8115 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8116 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8117 filter_replace_buf.data[4] |=
8118 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8120 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8121 &filter_replace_buf);
8122 if (!status && (filter_replace.old_filter_type !=
8123 filter_replace.new_filter_type))
8124 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8125 " original: 0x%x, new: 0x%x",
8127 filter_replace.old_filter_type,
8128 filter_replace.new_filter_type);
8134 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8135 struct i40e_tunnel_filter_conf *tunnel_filter,
8139 uint32_t ipv4_addr, ipv4_addr_le;
8140 uint8_t i, tun_type = 0;
8141 /* internal variable to convert ipv6 byte order */
8142 uint32_t convert_ipv6[4];
8144 struct i40e_pf_vf *vf = NULL;
8145 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8146 struct i40e_vsi *vsi;
8147 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8148 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8149 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8150 struct i40e_tunnel_filter *tunnel, *node;
8151 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8153 bool big_buffer = 0;
8155 cld_filter = rte_zmalloc("tunnel_filter",
8156 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8159 if (cld_filter == NULL) {
8160 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8163 pfilter = cld_filter;
8165 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8166 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8167 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8168 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8170 pfilter->element.inner_vlan =
8171 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8172 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8173 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8174 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8175 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8176 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8178 sizeof(pfilter->element.ipaddr.v4.data));
8180 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8181 for (i = 0; i < 4; i++) {
8183 rte_cpu_to_le_32(rte_be_to_cpu_32(
8184 tunnel_filter->ip_addr.ipv6_addr[i]));
8186 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8188 sizeof(pfilter->element.ipaddr.v6.data));
8191 /* check tunneled type */
8192 switch (tunnel_filter->tunnel_type) {
8193 case I40E_TUNNEL_TYPE_VXLAN:
8194 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8196 case I40E_TUNNEL_TYPE_NVGRE:
8197 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8199 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8200 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8202 case I40E_TUNNEL_TYPE_MPLSoUDP:
8203 if (!pf->mpls_replace_flag) {
8204 i40e_replace_mpls_l1_filter(pf);
8205 i40e_replace_mpls_cloud_filter(pf);
8206 pf->mpls_replace_flag = 1;
8208 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8209 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8211 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8212 (teid_le & 0xF) << 12;
8213 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8216 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8218 case I40E_TUNNEL_TYPE_MPLSoGRE:
8219 if (!pf->mpls_replace_flag) {
8220 i40e_replace_mpls_l1_filter(pf);
8221 i40e_replace_mpls_cloud_filter(pf);
8222 pf->mpls_replace_flag = 1;
8224 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8225 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8227 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8228 (teid_le & 0xF) << 12;
8229 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8232 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8234 case I40E_TUNNEL_TYPE_GTPC:
8235 if (!pf->gtp_replace_flag) {
8236 i40e_replace_gtp_l1_filter(pf);
8237 i40e_replace_gtp_cloud_filter(pf);
8238 pf->gtp_replace_flag = 1;
8240 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8241 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8242 (teid_le >> 16) & 0xFFFF;
8243 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8245 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8249 case I40E_TUNNEL_TYPE_GTPU:
8250 if (!pf->gtp_replace_flag) {
8251 i40e_replace_gtp_l1_filter(pf);
8252 i40e_replace_gtp_cloud_filter(pf);
8253 pf->gtp_replace_flag = 1;
8255 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8256 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8257 (teid_le >> 16) & 0xFFFF;
8258 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8260 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8264 case I40E_TUNNEL_TYPE_QINQ:
8265 if (!pf->qinq_replace_flag) {
8266 ret = i40e_cloud_filter_qinq_create(pf);
8269 "QinQ tunnel filter already created.");
8270 pf->qinq_replace_flag = 1;
8272 /* Add in the General fields the values of
8273 * the Outer and Inner VLAN
8274 * Big Buffer should be set, see changes in
8275 * i40e_aq_add_cloud_filters
8277 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8278 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8282 /* Other tunnel types is not supported. */
8283 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8284 rte_free(cld_filter);
8288 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8289 pfilter->element.flags =
8290 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8291 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8292 pfilter->element.flags =
8293 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8294 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8295 pfilter->element.flags =
8296 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8297 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8298 pfilter->element.flags =
8299 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8300 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8301 pfilter->element.flags |=
8302 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8304 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8305 &pfilter->element.flags);
8307 rte_free(cld_filter);
8312 pfilter->element.flags |= rte_cpu_to_le_16(
8313 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8314 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8315 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8316 pfilter->element.queue_number =
8317 rte_cpu_to_le_16(tunnel_filter->queue_id);
8319 if (!tunnel_filter->is_to_vf)
8322 if (tunnel_filter->vf_id >= pf->vf_num) {
8323 PMD_DRV_LOG(ERR, "Invalid argument.");
8324 rte_free(cld_filter);
8327 vf = &pf->vfs[tunnel_filter->vf_id];
8331 /* Check if there is the filter in SW list */
8332 memset(&check_filter, 0, sizeof(check_filter));
8333 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8334 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8335 check_filter.vf_id = tunnel_filter->vf_id;
8336 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8338 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8339 rte_free(cld_filter);
8343 if (!add && !node) {
8344 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8345 rte_free(cld_filter);
8351 ret = i40e_aq_add_cloud_filters_bb(hw,
8352 vsi->seid, cld_filter, 1);
8354 ret = i40e_aq_add_cloud_filters(hw,
8355 vsi->seid, &cld_filter->element, 1);
8357 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8358 rte_free(cld_filter);
8361 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8362 if (tunnel == NULL) {
8363 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8364 rte_free(cld_filter);
8368 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8369 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8374 ret = i40e_aq_rem_cloud_filters_bb(
8375 hw, vsi->seid, cld_filter, 1);
8377 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8378 &cld_filter->element, 1);
8380 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8381 rte_free(cld_filter);
8384 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8387 rte_free(cld_filter);
8392 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8396 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8397 if (pf->vxlan_ports[i] == port)
8405 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8409 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8411 idx = i40e_get_vxlan_port_idx(pf, port);
8413 /* Check if port already exists */
8415 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8419 /* Now check if there is space to add the new port */
8420 idx = i40e_get_vxlan_port_idx(pf, 0);
8423 "Maximum number of UDP ports reached, not adding port %d",
8428 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8431 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8435 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8438 /* New port: add it and mark its index in the bitmap */
8439 pf->vxlan_ports[idx] = port;
8440 pf->vxlan_bitmap |= (1 << idx);
8442 if (!(pf->flags & I40E_FLAG_VXLAN))
8443 pf->flags |= I40E_FLAG_VXLAN;
8449 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8452 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8454 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8455 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8459 idx = i40e_get_vxlan_port_idx(pf, port);
8462 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8466 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8467 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8471 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8474 pf->vxlan_ports[idx] = 0;
8475 pf->vxlan_bitmap &= ~(1 << idx);
8477 if (!pf->vxlan_bitmap)
8478 pf->flags &= ~I40E_FLAG_VXLAN;
8483 /* Add UDP tunneling port */
8485 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8486 struct rte_eth_udp_tunnel *udp_tunnel)
8489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8491 if (udp_tunnel == NULL)
8494 switch (udp_tunnel->prot_type) {
8495 case RTE_TUNNEL_TYPE_VXLAN:
8496 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8497 I40E_AQC_TUNNEL_TYPE_VXLAN);
8499 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8500 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8501 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8503 case RTE_TUNNEL_TYPE_GENEVE:
8504 case RTE_TUNNEL_TYPE_TEREDO:
8505 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8510 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8518 /* Remove UDP tunneling port */
8520 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8521 struct rte_eth_udp_tunnel *udp_tunnel)
8524 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8526 if (udp_tunnel == NULL)
8529 switch (udp_tunnel->prot_type) {
8530 case RTE_TUNNEL_TYPE_VXLAN:
8531 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8532 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8534 case RTE_TUNNEL_TYPE_GENEVE:
8535 case RTE_TUNNEL_TYPE_TEREDO:
8536 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8540 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8548 /* Calculate the maximum number of contiguous PF queues that are configured */
8550 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8552 struct rte_eth_dev_data *data = pf->dev_data;
8554 struct i40e_rx_queue *rxq;
8557 for (i = 0; i < pf->lan_nb_qps; i++) {
8558 rxq = data->rx_queues[i];
8559 if (rxq && rxq->q_set)
8570 i40e_pf_config_rss(struct i40e_pf *pf)
8572 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8573 struct rte_eth_rss_conf rss_conf;
8574 uint32_t i, lut = 0;
8578 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8579 * It's necessary to calculate the actual PF queues that are configured.
8581 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8582 num = i40e_pf_calc_configured_queues_num(pf);
8584 num = pf->dev_data->nb_rx_queues;
8586 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8587 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8591 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8595 if (pf->adapter->rss_reta_updated == 0) {
8596 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8599 lut = (lut << 8) | (j & ((0x1 <<
8600 hw->func_caps.rss_table_entry_width) - 1));
8602 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8607 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8608 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8609 i40e_pf_disable_rss(pf);
8612 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8613 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8614 /* Random default keys */
8615 static uint32_t rss_key_default[] = {0x6b793944,
8616 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8617 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8618 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8620 rss_conf.rss_key = (uint8_t *)rss_key_default;
8621 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8625 return i40e_hw_rss_hash_set(pf, &rss_conf);
8629 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8630 struct rte_eth_tunnel_filter_conf *filter)
8632 if (pf == NULL || filter == NULL) {
8633 PMD_DRV_LOG(ERR, "Invalid parameter");
8637 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8638 PMD_DRV_LOG(ERR, "Invalid queue ID");
8642 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8643 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8647 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8648 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8649 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8653 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8654 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8655 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8662 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8663 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8665 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8667 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8671 if (pf->support_multi_driver) {
8672 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8676 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8677 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8680 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8681 } else if (len == 4) {
8682 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8684 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8689 ret = i40e_aq_debug_write_global_register(hw,
8690 I40E_GL_PRS_FVBM(2),
8694 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8695 "with value 0x%08x",
8696 I40E_GL_PRS_FVBM(2), reg);
8700 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8701 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8707 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8714 switch (cfg->cfg_type) {
8715 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8716 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8719 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8727 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8728 enum rte_filter_op filter_op,
8731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8732 int ret = I40E_ERR_PARAM;
8734 switch (filter_op) {
8735 case RTE_ETH_FILTER_SET:
8736 ret = i40e_dev_global_config_set(hw,
8737 (struct rte_eth_global_cfg *)arg);
8740 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8748 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8749 enum rte_filter_op filter_op,
8752 struct rte_eth_tunnel_filter_conf *filter;
8753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8754 int ret = I40E_SUCCESS;
8756 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8758 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8759 return I40E_ERR_PARAM;
8761 switch (filter_op) {
8762 case RTE_ETH_FILTER_NOP:
8763 if (!(pf->flags & I40E_FLAG_VXLAN))
8764 ret = I40E_NOT_SUPPORTED;
8766 case RTE_ETH_FILTER_ADD:
8767 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8769 case RTE_ETH_FILTER_DELETE:
8770 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8773 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8774 ret = I40E_ERR_PARAM;
8782 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8785 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8788 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8789 ret = i40e_pf_config_rss(pf);
8791 i40e_pf_disable_rss(pf);
8796 /* Get the symmetric hash enable configurations per port */
8798 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8800 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8802 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8805 /* Set the symmetric hash enable configurations per port */
8807 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8809 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8812 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8814 "Symmetric hash has already been enabled");
8817 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8819 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8821 "Symmetric hash has already been disabled");
8824 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8826 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8827 I40E_WRITE_FLUSH(hw);
8831 * Get global configurations of hash function type and symmetric hash enable
8832 * per flow type (pctype). Note that global configuration means it affects all
8833 * the ports on the same NIC.
8836 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8837 struct rte_eth_hash_global_conf *g_cfg)
8839 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8843 memset(g_cfg, 0, sizeof(*g_cfg));
8844 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8845 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8846 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8848 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8849 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8850 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8853 * As i40e supports less than 64 flow types, only first 64 bits need to
8856 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8857 g_cfg->valid_bit_mask[i] = 0ULL;
8858 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8861 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8863 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8864 if (!adapter->pctypes_tbl[i])
8866 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8867 j < I40E_FILTER_PCTYPE_MAX; j++) {
8868 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8869 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8870 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8871 g_cfg->sym_hash_enable_mask[0] |=
8882 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8883 const struct rte_eth_hash_global_conf *g_cfg)
8886 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8888 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8889 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8890 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8891 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8897 * As i40e supports less than 64 flow types, only first 64 bits need to
8900 mask0 = g_cfg->valid_bit_mask[0];
8901 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8903 /* Check if any unsupported flow type configured */
8904 if ((mask0 | i40e_mask) ^ i40e_mask)
8907 if (g_cfg->valid_bit_mask[i])
8915 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8921 * Set global configurations of hash function type and symmetric hash enable
8922 * per flow type (pctype). Note any modifying global configuration will affect
8923 * all the ports on the same NIC.
8926 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8927 struct rte_eth_hash_global_conf *g_cfg)
8929 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8930 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8934 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8936 if (pf->support_multi_driver) {
8937 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8941 /* Check the input parameters */
8942 ret = i40e_hash_global_config_check(adapter, g_cfg);
8947 * As i40e supports less than 64 flow types, only first 64 bits need to
8950 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8951 if (mask0 & (1UL << i)) {
8952 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8953 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8955 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8956 j < I40E_FILTER_PCTYPE_MAX; j++) {
8957 if (adapter->pctypes_tbl[i] & (1ULL << j))
8958 i40e_write_global_rx_ctl(hw,
8965 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8966 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8968 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8970 "Hash function already set to Toeplitz");
8973 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8974 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8976 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8978 "Hash function already set to Simple XOR");
8981 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8983 /* Use the default, and keep it as it is */
8986 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8989 I40E_WRITE_FLUSH(hw);
8995 * Valid input sets for hash and flow director filters per PCTYPE
8998 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8999 enum rte_filter_type filter)
9003 static const uint64_t valid_hash_inset_table[] = {
9004 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9005 I40E_INSET_DMAC | I40E_INSET_SMAC |
9006 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9007 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9008 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9009 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9010 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9011 I40E_INSET_FLEX_PAYLOAD,
9012 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9013 I40E_INSET_DMAC | I40E_INSET_SMAC |
9014 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9015 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9016 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9017 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9018 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9019 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9020 I40E_INSET_FLEX_PAYLOAD,
9021 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9022 I40E_INSET_DMAC | I40E_INSET_SMAC |
9023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9025 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9026 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9027 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9028 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9029 I40E_INSET_FLEX_PAYLOAD,
9030 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9031 I40E_INSET_DMAC | I40E_INSET_SMAC |
9032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9034 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9035 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9036 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9037 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9038 I40E_INSET_FLEX_PAYLOAD,
9039 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9040 I40E_INSET_DMAC | I40E_INSET_SMAC |
9041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9043 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9044 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9045 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9047 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9048 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9049 I40E_INSET_DMAC | I40E_INSET_SMAC |
9050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9052 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9053 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9055 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9056 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9057 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9058 I40E_INSET_DMAC | I40E_INSET_SMAC |
9059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9061 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9062 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9063 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9065 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9066 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9067 I40E_INSET_DMAC | I40E_INSET_SMAC |
9068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9070 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9071 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9072 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9073 I40E_INSET_FLEX_PAYLOAD,
9074 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9075 I40E_INSET_DMAC | I40E_INSET_SMAC |
9076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9078 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9079 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9080 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9081 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9082 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9083 I40E_INSET_DMAC | I40E_INSET_SMAC |
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9086 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9087 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9088 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9089 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9090 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9091 I40E_INSET_DMAC | I40E_INSET_SMAC |
9092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9094 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9095 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9096 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9097 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9098 I40E_INSET_FLEX_PAYLOAD,
9099 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9100 I40E_INSET_DMAC | I40E_INSET_SMAC |
9101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9103 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9104 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9105 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9106 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9107 I40E_INSET_FLEX_PAYLOAD,
9108 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9109 I40E_INSET_DMAC | I40E_INSET_SMAC |
9110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9112 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9113 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9114 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9115 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9116 I40E_INSET_FLEX_PAYLOAD,
9117 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9118 I40E_INSET_DMAC | I40E_INSET_SMAC |
9119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9120 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9121 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9122 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9123 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9124 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9125 I40E_INSET_FLEX_PAYLOAD,
9126 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9127 I40E_INSET_DMAC | I40E_INSET_SMAC |
9128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9130 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9131 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9132 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9133 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9134 I40E_INSET_FLEX_PAYLOAD,
9135 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9136 I40E_INSET_DMAC | I40E_INSET_SMAC |
9137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9139 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9140 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9141 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9142 I40E_INSET_FLEX_PAYLOAD,
9143 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9144 I40E_INSET_DMAC | I40E_INSET_SMAC |
9145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9146 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9147 I40E_INSET_FLEX_PAYLOAD,
9151 * Flow director supports only fields defined in
9152 * union rte_eth_fdir_flow.
9154 static const uint64_t valid_fdir_inset_table[] = {
9155 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9156 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9159 I40E_INSET_IPV4_TTL,
9160 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9163 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9164 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9165 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9166 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9169 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9170 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9171 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9175 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9176 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9178 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9179 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9180 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9181 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9182 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9183 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9184 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9185 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9186 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9187 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9188 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9189 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9191 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9192 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9194 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9195 I40E_INSET_IPV4_TTL,
9196 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9197 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9198 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9200 I40E_INSET_IPV6_HOP_LIMIT,
9201 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9202 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9204 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9210 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9211 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9215 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9216 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9220 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9221 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9222 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9224 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9228 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9229 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9230 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9232 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9233 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9234 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9235 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9236 I40E_INSET_IPV6_HOP_LIMIT,
9237 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9238 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9239 I40E_INSET_LAST_ETHER_TYPE,
9242 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9244 if (filter == RTE_ETH_FILTER_HASH)
9245 valid = valid_hash_inset_table[pctype];
9247 valid = valid_fdir_inset_table[pctype];
9253 * Validate if the input set is allowed for a specific PCTYPE
9256 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9257 enum rte_filter_type filter, uint64_t inset)
9261 valid = i40e_get_valid_input_set(pctype, filter);
9262 if (inset & (~valid))
9268 /* default input set fields combination per pctype */
9270 i40e_get_default_input_set(uint16_t pctype)
9272 static const uint64_t default_inset_table[] = {
9273 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9274 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9275 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9276 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9277 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9278 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9279 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9282 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9283 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9284 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9285 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9286 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9287 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9288 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9289 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9290 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9291 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9292 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9294 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9295 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9296 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9297 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9298 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9299 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9302 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9304 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9305 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9306 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9307 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9308 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9310 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9311 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9313 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9314 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9315 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9317 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9318 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9319 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9320 I40E_INSET_LAST_ETHER_TYPE,
9323 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9326 return default_inset_table[pctype];
9330 * Parse the input set from index to logical bit masks
9333 i40e_parse_input_set(uint64_t *inset,
9334 enum i40e_filter_pctype pctype,
9335 enum rte_eth_input_set_field *field,
9341 static const struct {
9342 enum rte_eth_input_set_field field;
9344 } inset_convert_table[] = {
9345 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9346 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9347 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9348 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9349 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9350 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9351 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9352 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9353 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9354 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9355 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9356 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9357 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9358 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9359 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9360 I40E_INSET_IPV6_NEXT_HDR},
9361 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9362 I40E_INSET_IPV6_HOP_LIMIT},
9363 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9364 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9365 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9366 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9367 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9368 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9369 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9370 I40E_INSET_SCTP_VT},
9371 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9372 I40E_INSET_TUNNEL_DMAC},
9373 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9374 I40E_INSET_VLAN_TUNNEL},
9375 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9376 I40E_INSET_TUNNEL_ID},
9377 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9378 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9379 I40E_INSET_FLEX_PAYLOAD_W1},
9380 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9381 I40E_INSET_FLEX_PAYLOAD_W2},
9382 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9383 I40E_INSET_FLEX_PAYLOAD_W3},
9384 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9385 I40E_INSET_FLEX_PAYLOAD_W4},
9386 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9387 I40E_INSET_FLEX_PAYLOAD_W5},
9388 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9389 I40E_INSET_FLEX_PAYLOAD_W6},
9390 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9391 I40E_INSET_FLEX_PAYLOAD_W7},
9392 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9393 I40E_INSET_FLEX_PAYLOAD_W8},
9396 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9399 /* Only one item allowed for default or all */
9401 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9402 *inset = i40e_get_default_input_set(pctype);
9404 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9405 *inset = I40E_INSET_NONE;
9410 for (i = 0, *inset = 0; i < size; i++) {
9411 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9412 if (field[i] == inset_convert_table[j].field) {
9413 *inset |= inset_convert_table[j].inset;
9418 /* It contains unsupported input set, return immediately */
9419 if (j == RTE_DIM(inset_convert_table))
9427 * Translate the input set from bit masks to register aware bit masks
9431 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9441 static const struct inset_map inset_map_common[] = {
9442 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9443 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9444 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9445 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9446 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9447 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9448 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9449 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9450 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9451 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9452 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9453 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9454 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9455 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9456 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9457 {I40E_INSET_TUNNEL_DMAC,
9458 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9459 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9460 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9461 {I40E_INSET_TUNNEL_SRC_PORT,
9462 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9463 {I40E_INSET_TUNNEL_DST_PORT,
9464 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9465 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9466 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9467 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9468 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9469 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9470 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9471 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9472 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9473 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9476 /* some different registers map in x722*/
9477 static const struct inset_map inset_map_diff_x722[] = {
9478 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9479 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9480 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9481 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9484 static const struct inset_map inset_map_diff_not_x722[] = {
9485 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9486 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9487 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9488 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9494 /* Translate input set to register aware inset */
9495 if (type == I40E_MAC_X722) {
9496 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9497 if (input & inset_map_diff_x722[i].inset)
9498 val |= inset_map_diff_x722[i].inset_reg;
9501 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9502 if (input & inset_map_diff_not_x722[i].inset)
9503 val |= inset_map_diff_not_x722[i].inset_reg;
9507 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9508 if (input & inset_map_common[i].inset)
9509 val |= inset_map_common[i].inset_reg;
9516 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9519 uint64_t inset_need_mask = inset;
9521 static const struct {
9524 } inset_mask_map[] = {
9525 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9526 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9527 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9528 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9529 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9530 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9531 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9532 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9535 if (!inset || !mask || !nb_elem)
9538 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9539 /* Clear the inset bit, if no MASK is required,
9540 * for example proto + ttl
9542 if ((inset & inset_mask_map[i].inset) ==
9543 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9544 inset_need_mask &= ~inset_mask_map[i].inset;
9545 if (!inset_need_mask)
9548 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9549 if ((inset_need_mask & inset_mask_map[i].inset) ==
9550 inset_mask_map[i].inset) {
9551 if (idx >= nb_elem) {
9552 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9555 mask[idx] = inset_mask_map[i].mask;
9564 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9566 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9568 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9570 i40e_write_rx_ctl(hw, addr, val);
9571 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9572 (uint32_t)i40e_read_rx_ctl(hw, addr));
9576 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9578 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9579 struct rte_eth_dev *dev;
9581 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9583 i40e_write_rx_ctl(hw, addr, val);
9584 PMD_DRV_LOG(WARNING,
9585 "i40e device %s changed global register [0x%08x]."
9586 " original: 0x%08x, new: 0x%08x",
9587 dev->device->name, addr, reg,
9588 (uint32_t)i40e_read_rx_ctl(hw, addr));
9593 i40e_filter_input_set_init(struct i40e_pf *pf)
9595 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9596 enum i40e_filter_pctype pctype;
9597 uint64_t input_set, inset_reg;
9598 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9602 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9603 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9604 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9606 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9609 input_set = i40e_get_default_input_set(pctype);
9611 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9612 I40E_INSET_MASK_NUM_REG);
9615 if (pf->support_multi_driver && num > 0) {
9616 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9619 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9622 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9623 (uint32_t)(inset_reg & UINT32_MAX));
9624 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9625 (uint32_t)((inset_reg >>
9626 I40E_32_BIT_WIDTH) & UINT32_MAX));
9627 if (!pf->support_multi_driver) {
9628 i40e_check_write_global_reg(hw,
9629 I40E_GLQF_HASH_INSET(0, pctype),
9630 (uint32_t)(inset_reg & UINT32_MAX));
9631 i40e_check_write_global_reg(hw,
9632 I40E_GLQF_HASH_INSET(1, pctype),
9633 (uint32_t)((inset_reg >>
9634 I40E_32_BIT_WIDTH) & UINT32_MAX));
9636 for (i = 0; i < num; i++) {
9637 i40e_check_write_global_reg(hw,
9638 I40E_GLQF_FD_MSK(i, pctype),
9640 i40e_check_write_global_reg(hw,
9641 I40E_GLQF_HASH_MSK(i, pctype),
9644 /*clear unused mask registers of the pctype */
9645 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9646 i40e_check_write_global_reg(hw,
9647 I40E_GLQF_FD_MSK(i, pctype),
9649 i40e_check_write_global_reg(hw,
9650 I40E_GLQF_HASH_MSK(i, pctype),
9654 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9656 I40E_WRITE_FLUSH(hw);
9658 /* store the default input set */
9659 if (!pf->support_multi_driver)
9660 pf->hash_input_set[pctype] = input_set;
9661 pf->fdir.input_set[pctype] = input_set;
9666 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9667 struct rte_eth_input_set_conf *conf)
9669 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9670 enum i40e_filter_pctype pctype;
9671 uint64_t input_set, inset_reg = 0;
9672 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9676 PMD_DRV_LOG(ERR, "Invalid pointer");
9679 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9680 conf->op != RTE_ETH_INPUT_SET_ADD) {
9681 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9685 if (pf->support_multi_driver) {
9686 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9690 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9691 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9692 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9696 if (hw->mac.type == I40E_MAC_X722) {
9697 /* get translated pctype value in fd pctype register */
9698 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9699 I40E_GLQF_FD_PCTYPES((int)pctype));
9702 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9705 PMD_DRV_LOG(ERR, "Failed to parse input set");
9709 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9710 /* get inset value in register */
9711 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9712 inset_reg <<= I40E_32_BIT_WIDTH;
9713 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9714 input_set |= pf->hash_input_set[pctype];
9716 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9717 I40E_INSET_MASK_NUM_REG);
9721 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9723 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9724 (uint32_t)(inset_reg & UINT32_MAX));
9725 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9726 (uint32_t)((inset_reg >>
9727 I40E_32_BIT_WIDTH) & UINT32_MAX));
9729 for (i = 0; i < num; i++)
9730 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9732 /*clear unused mask registers of the pctype */
9733 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9734 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9736 I40E_WRITE_FLUSH(hw);
9738 pf->hash_input_set[pctype] = input_set;
9743 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9744 struct rte_eth_input_set_conf *conf)
9746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9747 enum i40e_filter_pctype pctype;
9748 uint64_t input_set, inset_reg = 0;
9749 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9753 PMD_DRV_LOG(ERR, "Invalid pointer");
9756 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9757 conf->op != RTE_ETH_INPUT_SET_ADD) {
9758 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9762 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9764 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9765 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9769 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9772 PMD_DRV_LOG(ERR, "Failed to parse input set");
9776 /* get inset value in register */
9777 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9778 inset_reg <<= I40E_32_BIT_WIDTH;
9779 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9781 /* Can not change the inset reg for flex payload for fdir,
9782 * it is done by writing I40E_PRTQF_FD_FLXINSET
9783 * in i40e_set_flex_mask_on_pctype.
9785 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9786 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9788 input_set |= pf->fdir.input_set[pctype];
9789 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9790 I40E_INSET_MASK_NUM_REG);
9793 if (pf->support_multi_driver && num > 0) {
9794 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9798 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9800 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9801 (uint32_t)(inset_reg & UINT32_MAX));
9802 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9803 (uint32_t)((inset_reg >>
9804 I40E_32_BIT_WIDTH) & UINT32_MAX));
9806 if (!pf->support_multi_driver) {
9807 for (i = 0; i < num; i++)
9808 i40e_check_write_global_reg(hw,
9809 I40E_GLQF_FD_MSK(i, pctype),
9811 /*clear unused mask registers of the pctype */
9812 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9813 i40e_check_write_global_reg(hw,
9814 I40E_GLQF_FD_MSK(i, pctype),
9817 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9819 I40E_WRITE_FLUSH(hw);
9821 pf->fdir.input_set[pctype] = input_set;
9826 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9831 PMD_DRV_LOG(ERR, "Invalid pointer");
9835 switch (info->info_type) {
9836 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9837 i40e_get_symmetric_hash_enable_per_port(hw,
9838 &(info->info.enable));
9840 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9841 ret = i40e_get_hash_filter_global_config(hw,
9842 &(info->info.global_conf));
9845 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9855 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9860 PMD_DRV_LOG(ERR, "Invalid pointer");
9864 switch (info->info_type) {
9865 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9866 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9868 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9869 ret = i40e_set_hash_filter_global_config(hw,
9870 &(info->info.global_conf));
9872 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9873 ret = i40e_hash_filter_inset_select(hw,
9874 &(info->info.input_set_conf));
9878 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9887 /* Operations for hash function */
9889 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9890 enum rte_filter_op filter_op,
9893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9896 switch (filter_op) {
9897 case RTE_ETH_FILTER_NOP:
9899 case RTE_ETH_FILTER_GET:
9900 ret = i40e_hash_filter_get(hw,
9901 (struct rte_eth_hash_filter_info *)arg);
9903 case RTE_ETH_FILTER_SET:
9904 ret = i40e_hash_filter_set(hw,
9905 (struct rte_eth_hash_filter_info *)arg);
9908 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9917 /* Convert ethertype filter structure */
9919 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9920 struct i40e_ethertype_filter *filter)
9922 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9923 RTE_ETHER_ADDR_LEN);
9924 filter->input.ether_type = input->ether_type;
9925 filter->flags = input->flags;
9926 filter->queue = input->queue;
9931 /* Check if there exists the ehtertype filter */
9932 struct i40e_ethertype_filter *
9933 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9934 const struct i40e_ethertype_filter_input *input)
9938 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9942 return ethertype_rule->hash_map[ret];
9945 /* Add ethertype filter in SW list */
9947 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9948 struct i40e_ethertype_filter *filter)
9950 struct i40e_ethertype_rule *rule = &pf->ethertype;
9953 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9956 "Failed to insert ethertype filter"
9957 " to hash table %d!",
9961 rule->hash_map[ret] = filter;
9963 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9968 /* Delete ethertype filter in SW list */
9970 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9971 struct i40e_ethertype_filter_input *input)
9973 struct i40e_ethertype_rule *rule = &pf->ethertype;
9974 struct i40e_ethertype_filter *filter;
9977 ret = rte_hash_del_key(rule->hash_table, input);
9980 "Failed to delete ethertype filter"
9981 " to hash table %d!",
9985 filter = rule->hash_map[ret];
9986 rule->hash_map[ret] = NULL;
9988 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9995 * Configure ethertype filter, which can director packet by filtering
9996 * with mac address and ether_type or only ether_type
9999 i40e_ethertype_filter_set(struct i40e_pf *pf,
10000 struct rte_eth_ethertype_filter *filter,
10003 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10004 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10005 struct i40e_ethertype_filter *ethertype_filter, *node;
10006 struct i40e_ethertype_filter check_filter;
10007 struct i40e_control_filter_stats stats;
10008 uint16_t flags = 0;
10011 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10012 PMD_DRV_LOG(ERR, "Invalid queue ID");
10015 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10016 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10018 "unsupported ether_type(0x%04x) in control packet filter.",
10019 filter->ether_type);
10022 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10023 PMD_DRV_LOG(WARNING,
10024 "filter vlan ether_type in first tag is not supported.");
10026 /* Check if there is the filter in SW list */
10027 memset(&check_filter, 0, sizeof(check_filter));
10028 i40e_ethertype_filter_convert(filter, &check_filter);
10029 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10030 &check_filter.input);
10032 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10036 if (!add && !node) {
10037 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10041 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10042 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10043 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10044 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10045 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10047 memset(&stats, 0, sizeof(stats));
10048 ret = i40e_aq_add_rem_control_packet_filter(hw,
10049 filter->mac_addr.addr_bytes,
10050 filter->ether_type, flags,
10051 pf->main_vsi->seid,
10052 filter->queue, add, &stats, NULL);
10055 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10056 ret, stats.mac_etype_used, stats.etype_used,
10057 stats.mac_etype_free, stats.etype_free);
10061 /* Add or delete a filter in SW list */
10063 ethertype_filter = rte_zmalloc("ethertype_filter",
10064 sizeof(*ethertype_filter), 0);
10065 if (ethertype_filter == NULL) {
10066 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10070 rte_memcpy(ethertype_filter, &check_filter,
10071 sizeof(check_filter));
10072 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10074 rte_free(ethertype_filter);
10076 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10083 * Handle operations for ethertype filter.
10086 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10087 enum rte_filter_op filter_op,
10090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10093 if (filter_op == RTE_ETH_FILTER_NOP)
10097 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10102 switch (filter_op) {
10103 case RTE_ETH_FILTER_ADD:
10104 ret = i40e_ethertype_filter_set(pf,
10105 (struct rte_eth_ethertype_filter *)arg,
10108 case RTE_ETH_FILTER_DELETE:
10109 ret = i40e_ethertype_filter_set(pf,
10110 (struct rte_eth_ethertype_filter *)arg,
10114 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10122 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10123 enum rte_filter_type filter_type,
10124 enum rte_filter_op filter_op,
10132 switch (filter_type) {
10133 case RTE_ETH_FILTER_NONE:
10134 /* For global configuration */
10135 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10137 case RTE_ETH_FILTER_HASH:
10138 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10140 case RTE_ETH_FILTER_MACVLAN:
10141 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10143 case RTE_ETH_FILTER_ETHERTYPE:
10144 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10146 case RTE_ETH_FILTER_TUNNEL:
10147 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10149 case RTE_ETH_FILTER_FDIR:
10150 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10152 case RTE_ETH_FILTER_GENERIC:
10153 if (filter_op != RTE_ETH_FILTER_GET)
10155 *(const void **)arg = &i40e_flow_ops;
10158 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10168 * Check and enable Extended Tag.
10169 * Enabling Extended Tag is important for 40G performance.
10172 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10174 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10178 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10181 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10185 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10186 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10191 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10194 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10198 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10199 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10202 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10203 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10206 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10213 * As some registers wouldn't be reset unless a global hardware reset,
10214 * hardware initialization is needed to put those registers into an
10215 * expected initial state.
10218 i40e_hw_init(struct rte_eth_dev *dev)
10220 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10222 i40e_enable_extended_tag(dev);
10224 /* clear the PF Queue Filter control register */
10225 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10227 /* Disable symmetric hash per port */
10228 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10232 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10233 * however this function will return only one highest pctype index,
10234 * which is not quite correct. This is known problem of i40e driver
10235 * and needs to be fixed later.
10237 enum i40e_filter_pctype
10238 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10241 uint64_t pctype_mask;
10243 if (flow_type < I40E_FLOW_TYPE_MAX) {
10244 pctype_mask = adapter->pctypes_tbl[flow_type];
10245 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10246 if (pctype_mask & (1ULL << i))
10247 return (enum i40e_filter_pctype)i;
10250 return I40E_FILTER_PCTYPE_INVALID;
10254 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10255 enum i40e_filter_pctype pctype)
10258 uint64_t pctype_mask = 1ULL << pctype;
10260 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10262 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10266 return RTE_ETH_FLOW_UNKNOWN;
10270 * On X710, performance number is far from the expectation on recent firmware
10271 * versions; on XL710, performance number is also far from the expectation on
10272 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10273 * mode is enabled and port MAC address is equal to the packet destination MAC
10274 * address. The fix for this issue may not be integrated in the following
10275 * firmware version. So the workaround in software driver is needed. It needs
10276 * to modify the initial values of 3 internal only registers for both X710 and
10277 * XL710. Note that the values for X710 or XL710 could be different, and the
10278 * workaround can be removed when it is fixed in firmware in the future.
10281 /* For both X710 and XL710 */
10282 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10283 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10284 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10286 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10287 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10290 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10291 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10294 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10296 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10297 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10300 * GL_SWR_PM_UP_THR:
10301 * The value is not impacted from the link speed, its value is set according
10302 * to the total number of ports for a better pipe-monitor configuration.
10305 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10307 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10308 .device_id = (dev), \
10309 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10311 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10312 .device_id = (dev), \
10313 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10315 static const struct {
10316 uint16_t device_id;
10318 } swr_pm_table[] = {
10319 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10320 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10321 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10322 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10324 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10325 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10326 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10327 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10328 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10329 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10330 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10334 if (value == NULL) {
10335 PMD_DRV_LOG(ERR, "value is NULL");
10339 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10340 if (hw->device_id == swr_pm_table[i].device_id) {
10341 *value = swr_pm_table[i].val;
10343 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10345 hw->device_id, *value);
10354 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10356 enum i40e_status_code status;
10357 struct i40e_aq_get_phy_abilities_resp phy_ab;
10358 int ret = -ENOTSUP;
10361 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10365 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10368 rte_delay_us(100000);
10370 status = i40e_aq_get_phy_capabilities(hw, false,
10371 true, &phy_ab, NULL);
10379 i40e_configure_registers(struct i40e_hw *hw)
10385 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10386 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10387 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10393 for (i = 0; i < RTE_DIM(reg_table); i++) {
10394 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10395 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10397 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10398 else /* For X710/XL710/XXV710 */
10399 if (hw->aq.fw_maj_ver < 6)
10401 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10404 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10407 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10408 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10410 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10411 else /* For X710/XL710/XXV710 */
10413 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10416 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10419 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10420 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10421 "GL_SWR_PM_UP_THR value fixup",
10426 reg_table[i].val = cfg_val;
10429 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10432 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10433 reg_table[i].addr);
10436 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10437 reg_table[i].addr, reg);
10438 if (reg == reg_table[i].val)
10441 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10442 reg_table[i].val, NULL);
10445 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10446 reg_table[i].val, reg_table[i].addr);
10449 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10450 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10454 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10455 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10456 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10457 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10459 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10464 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10465 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10469 /* Configure for double VLAN RX stripping */
10470 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10471 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10472 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10473 ret = i40e_aq_debug_write_register(hw,
10474 I40E_VSI_TSR(vsi->vsi_id),
10477 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10479 return I40E_ERR_CONFIG;
10483 /* Configure for double VLAN TX insertion */
10484 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10485 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10486 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10487 ret = i40e_aq_debug_write_register(hw,
10488 I40E_VSI_L2TAGSTXVALID(
10489 vsi->vsi_id), reg, NULL);
10492 "Failed to update VSI_L2TAGSTXVALID[%d]",
10494 return I40E_ERR_CONFIG;
10502 * i40e_aq_add_mirror_rule
10503 * @hw: pointer to the hardware structure
10504 * @seid: VEB seid to add mirror rule to
10505 * @dst_id: destination vsi seid
10506 * @entries: Buffer which contains the entities to be mirrored
10507 * @count: number of entities contained in the buffer
10508 * @rule_id:the rule_id of the rule to be added
10510 * Add a mirror rule for a given veb.
10513 static enum i40e_status_code
10514 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10515 uint16_t seid, uint16_t dst_id,
10516 uint16_t rule_type, uint16_t *entries,
10517 uint16_t count, uint16_t *rule_id)
10519 struct i40e_aq_desc desc;
10520 struct i40e_aqc_add_delete_mirror_rule cmd;
10521 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10522 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10525 enum i40e_status_code status;
10527 i40e_fill_default_direct_cmd_desc(&desc,
10528 i40e_aqc_opc_add_mirror_rule);
10529 memset(&cmd, 0, sizeof(cmd));
10531 buff_len = sizeof(uint16_t) * count;
10532 desc.datalen = rte_cpu_to_le_16(buff_len);
10534 desc.flags |= rte_cpu_to_le_16(
10535 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10536 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10537 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10538 cmd.num_entries = rte_cpu_to_le_16(count);
10539 cmd.seid = rte_cpu_to_le_16(seid);
10540 cmd.destination = rte_cpu_to_le_16(dst_id);
10542 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10543 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10545 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10546 hw->aq.asq_last_status, resp->rule_id,
10547 resp->mirror_rules_used, resp->mirror_rules_free);
10548 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10554 * i40e_aq_del_mirror_rule
10555 * @hw: pointer to the hardware structure
10556 * @seid: VEB seid to add mirror rule to
10557 * @entries: Buffer which contains the entities to be mirrored
10558 * @count: number of entities contained in the buffer
10559 * @rule_id:the rule_id of the rule to be delete
10561 * Delete a mirror rule for a given veb.
10564 static enum i40e_status_code
10565 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10566 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10567 uint16_t count, uint16_t rule_id)
10569 struct i40e_aq_desc desc;
10570 struct i40e_aqc_add_delete_mirror_rule cmd;
10571 uint16_t buff_len = 0;
10572 enum i40e_status_code status;
10575 i40e_fill_default_direct_cmd_desc(&desc,
10576 i40e_aqc_opc_delete_mirror_rule);
10577 memset(&cmd, 0, sizeof(cmd));
10578 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10579 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10581 cmd.num_entries = count;
10582 buff_len = sizeof(uint16_t) * count;
10583 desc.datalen = rte_cpu_to_le_16(buff_len);
10584 buff = (void *)entries;
10586 /* rule id is filled in destination field for deleting mirror rule */
10587 cmd.destination = rte_cpu_to_le_16(rule_id);
10589 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10590 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10591 cmd.seid = rte_cpu_to_le_16(seid);
10593 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10594 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10600 * i40e_mirror_rule_set
10601 * @dev: pointer to the hardware structure
10602 * @mirror_conf: mirror rule info
10603 * @sw_id: mirror rule's sw_id
10604 * @on: enable/disable
10606 * set a mirror rule.
10610 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10611 struct rte_eth_mirror_conf *mirror_conf,
10612 uint8_t sw_id, uint8_t on)
10614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10616 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10617 struct i40e_mirror_rule *parent = NULL;
10618 uint16_t seid, dst_seid, rule_id;
10622 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10624 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10626 "mirror rule can not be configured without veb or vfs.");
10629 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10630 PMD_DRV_LOG(ERR, "mirror table is full.");
10633 if (mirror_conf->dst_pool > pf->vf_num) {
10634 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10635 mirror_conf->dst_pool);
10639 seid = pf->main_vsi->veb->seid;
10641 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10642 if (sw_id <= it->index) {
10648 if (mirr_rule && sw_id == mirr_rule->index) {
10650 PMD_DRV_LOG(ERR, "mirror rule exists.");
10653 ret = i40e_aq_del_mirror_rule(hw, seid,
10654 mirr_rule->rule_type,
10655 mirr_rule->entries,
10656 mirr_rule->num_entries, mirr_rule->id);
10659 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10660 ret, hw->aq.asq_last_status);
10663 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10664 rte_free(mirr_rule);
10665 pf->nb_mirror_rule--;
10669 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10673 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10674 sizeof(struct i40e_mirror_rule) , 0);
10676 PMD_DRV_LOG(ERR, "failed to allocate memory");
10677 return I40E_ERR_NO_MEMORY;
10679 switch (mirror_conf->rule_type) {
10680 case ETH_MIRROR_VLAN:
10681 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10682 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10683 mirr_rule->entries[j] =
10684 mirror_conf->vlan.vlan_id[i];
10689 PMD_DRV_LOG(ERR, "vlan is not specified.");
10690 rte_free(mirr_rule);
10693 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10695 case ETH_MIRROR_VIRTUAL_POOL_UP:
10696 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10697 /* check if the specified pool bit is out of range */
10698 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10699 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10700 rte_free(mirr_rule);
10703 for (i = 0, j = 0; i < pf->vf_num; i++) {
10704 if (mirror_conf->pool_mask & (1ULL << i)) {
10705 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10709 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10710 /* add pf vsi to entries */
10711 mirr_rule->entries[j] = pf->main_vsi_seid;
10715 PMD_DRV_LOG(ERR, "pool is not specified.");
10716 rte_free(mirr_rule);
10719 /* egress and ingress in aq commands means from switch but not port */
10720 mirr_rule->rule_type =
10721 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10722 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10723 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10725 case ETH_MIRROR_UPLINK_PORT:
10726 /* egress and ingress in aq commands means from switch but not port*/
10727 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10729 case ETH_MIRROR_DOWNLINK_PORT:
10730 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10733 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10734 mirror_conf->rule_type);
10735 rte_free(mirr_rule);
10739 /* If the dst_pool is equal to vf_num, consider it as PF */
10740 if (mirror_conf->dst_pool == pf->vf_num)
10741 dst_seid = pf->main_vsi_seid;
10743 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10745 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10746 mirr_rule->rule_type, mirr_rule->entries,
10750 "failed to add mirror rule: ret = %d, aq_err = %d.",
10751 ret, hw->aq.asq_last_status);
10752 rte_free(mirr_rule);
10756 mirr_rule->index = sw_id;
10757 mirr_rule->num_entries = j;
10758 mirr_rule->id = rule_id;
10759 mirr_rule->dst_vsi_seid = dst_seid;
10762 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10764 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10766 pf->nb_mirror_rule++;
10771 * i40e_mirror_rule_reset
10772 * @dev: pointer to the device
10773 * @sw_id: mirror rule's sw_id
10775 * reset a mirror rule.
10779 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10781 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10783 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10787 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10789 seid = pf->main_vsi->veb->seid;
10791 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10792 if (sw_id == it->index) {
10798 ret = i40e_aq_del_mirror_rule(hw, seid,
10799 mirr_rule->rule_type,
10800 mirr_rule->entries,
10801 mirr_rule->num_entries, mirr_rule->id);
10804 "failed to remove mirror rule: status = %d, aq_err = %d.",
10805 ret, hw->aq.asq_last_status);
10808 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10809 rte_free(mirr_rule);
10810 pf->nb_mirror_rule--;
10812 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10819 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10822 uint64_t systim_cycles;
10824 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10825 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10828 return systim_cycles;
10832 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10835 uint64_t rx_tstamp;
10837 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10838 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10845 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10847 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10848 uint64_t tx_tstamp;
10850 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10851 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10858 i40e_start_timecounters(struct rte_eth_dev *dev)
10860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10861 struct i40e_adapter *adapter = dev->data->dev_private;
10862 struct rte_eth_link link;
10863 uint32_t tsync_inc_l;
10864 uint32_t tsync_inc_h;
10866 /* Get current link speed. */
10867 i40e_dev_link_update(dev, 1);
10868 rte_eth_linkstatus_get(dev, &link);
10870 switch (link.link_speed) {
10871 case ETH_SPEED_NUM_40G:
10872 case ETH_SPEED_NUM_25G:
10873 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10874 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10876 case ETH_SPEED_NUM_10G:
10877 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10878 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10880 case ETH_SPEED_NUM_1G:
10881 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10882 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10889 /* Set the timesync increment value. */
10890 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10891 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10893 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10894 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10895 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10897 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10898 adapter->systime_tc.cc_shift = 0;
10899 adapter->systime_tc.nsec_mask = 0;
10901 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10902 adapter->rx_tstamp_tc.cc_shift = 0;
10903 adapter->rx_tstamp_tc.nsec_mask = 0;
10905 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10906 adapter->tx_tstamp_tc.cc_shift = 0;
10907 adapter->tx_tstamp_tc.nsec_mask = 0;
10911 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10913 struct i40e_adapter *adapter = dev->data->dev_private;
10915 adapter->systime_tc.nsec += delta;
10916 adapter->rx_tstamp_tc.nsec += delta;
10917 adapter->tx_tstamp_tc.nsec += delta;
10923 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10926 struct i40e_adapter *adapter = dev->data->dev_private;
10928 ns = rte_timespec_to_ns(ts);
10930 /* Set the timecounters to a new value. */
10931 adapter->systime_tc.nsec = ns;
10932 adapter->rx_tstamp_tc.nsec = ns;
10933 adapter->tx_tstamp_tc.nsec = ns;
10939 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10941 uint64_t ns, systime_cycles;
10942 struct i40e_adapter *adapter = dev->data->dev_private;
10944 systime_cycles = i40e_read_systime_cyclecounter(dev);
10945 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10946 *ts = rte_ns_to_timespec(ns);
10952 i40e_timesync_enable(struct rte_eth_dev *dev)
10954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10955 uint32_t tsync_ctl_l;
10956 uint32_t tsync_ctl_h;
10958 /* Stop the timesync system time. */
10959 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10960 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10961 /* Reset the timesync system time value. */
10962 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10963 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10965 i40e_start_timecounters(dev);
10967 /* Clear timesync registers. */
10968 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10969 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10970 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10971 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10972 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10973 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10975 /* Enable timestamping of PTP packets. */
10976 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10977 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10979 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10980 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10981 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10983 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10984 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10990 i40e_timesync_disable(struct rte_eth_dev *dev)
10992 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10993 uint32_t tsync_ctl_l;
10994 uint32_t tsync_ctl_h;
10996 /* Disable timestamping of transmitted PTP packets. */
10997 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10998 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11000 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11001 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11003 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11004 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11006 /* Reset the timesync increment value. */
11007 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11008 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11014 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11015 struct timespec *timestamp, uint32_t flags)
11017 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11018 struct i40e_adapter *adapter = dev->data->dev_private;
11019 uint32_t sync_status;
11020 uint32_t index = flags & 0x03;
11021 uint64_t rx_tstamp_cycles;
11024 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11025 if ((sync_status & (1 << index)) == 0)
11028 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11029 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11030 *timestamp = rte_ns_to_timespec(ns);
11036 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11037 struct timespec *timestamp)
11039 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11040 struct i40e_adapter *adapter = dev->data->dev_private;
11041 uint32_t sync_status;
11042 uint64_t tx_tstamp_cycles;
11045 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11046 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11049 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11050 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11051 *timestamp = rte_ns_to_timespec(ns);
11057 * i40e_parse_dcb_configure - parse dcb configure from user
11058 * @dev: the device being configured
11059 * @dcb_cfg: pointer of the result of parse
11060 * @*tc_map: bit map of enabled traffic classes
11062 * Returns 0 on success, negative value on failure
11065 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11066 struct i40e_dcbx_config *dcb_cfg,
11069 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11070 uint8_t i, tc_bw, bw_lf;
11072 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11074 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11075 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11076 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11080 /* assume each tc has the same bw */
11081 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11082 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11083 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11084 /* to ensure the sum of tcbw is equal to 100 */
11085 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11086 for (i = 0; i < bw_lf; i++)
11087 dcb_cfg->etscfg.tcbwtable[i]++;
11089 /* assume each tc has the same Transmission Selection Algorithm */
11090 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11091 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11093 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11094 dcb_cfg->etscfg.prioritytable[i] =
11095 dcb_rx_conf->dcb_tc[i];
11097 /* FW needs one App to configure HW */
11098 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11099 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11100 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11101 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11103 if (dcb_rx_conf->nb_tcs == 0)
11104 *tc_map = 1; /* tc0 only */
11106 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11108 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11109 dcb_cfg->pfc.willing = 0;
11110 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11111 dcb_cfg->pfc.pfcenable = *tc_map;
11117 static enum i40e_status_code
11118 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11119 struct i40e_aqc_vsi_properties_data *info,
11120 uint8_t enabled_tcmap)
11122 enum i40e_status_code ret;
11123 int i, total_tc = 0;
11124 uint16_t qpnum_per_tc, bsf, qp_idx;
11125 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11126 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11127 uint16_t used_queues;
11129 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11130 if (ret != I40E_SUCCESS)
11133 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11134 if (enabled_tcmap & (1 << i))
11139 vsi->enabled_tc = enabled_tcmap;
11141 /* different VSI has different queues assigned */
11142 if (vsi->type == I40E_VSI_MAIN)
11143 used_queues = dev_data->nb_rx_queues -
11144 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11145 else if (vsi->type == I40E_VSI_VMDQ2)
11146 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11148 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11149 return I40E_ERR_NO_AVAILABLE_VSI;
11152 qpnum_per_tc = used_queues / total_tc;
11153 /* Number of queues per enabled TC */
11154 if (qpnum_per_tc == 0) {
11155 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11156 return I40E_ERR_INVALID_QP_ID;
11158 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11159 I40E_MAX_Q_PER_TC);
11160 bsf = rte_bsf32(qpnum_per_tc);
11163 * Configure TC and queue mapping parameters, for enabled TC,
11164 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11165 * default queue will serve it.
11168 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11169 if (vsi->enabled_tc & (1 << i)) {
11170 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11171 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11172 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11173 qp_idx += qpnum_per_tc;
11175 info->tc_mapping[i] = 0;
11178 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11179 if (vsi->type == I40E_VSI_SRIOV) {
11180 info->mapping_flags |=
11181 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11182 for (i = 0; i < vsi->nb_qps; i++)
11183 info->queue_mapping[i] =
11184 rte_cpu_to_le_16(vsi->base_queue + i);
11186 info->mapping_flags |=
11187 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11188 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11190 info->valid_sections |=
11191 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11193 return I40E_SUCCESS;
11197 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11198 * @veb: VEB to be configured
11199 * @tc_map: enabled TC bitmap
11201 * Returns 0 on success, negative value on failure
11203 static enum i40e_status_code
11204 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11206 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11207 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11208 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11209 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11210 enum i40e_status_code ret = I40E_SUCCESS;
11214 /* Check if enabled_tc is same as existing or new TCs */
11215 if (veb->enabled_tc == tc_map)
11218 /* configure tc bandwidth */
11219 memset(&veb_bw, 0, sizeof(veb_bw));
11220 veb_bw.tc_valid_bits = tc_map;
11221 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11222 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11223 if (tc_map & BIT_ULL(i))
11224 veb_bw.tc_bw_share_credits[i] = 1;
11226 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11230 "AQ command Config switch_comp BW allocation per TC failed = %d",
11231 hw->aq.asq_last_status);
11235 memset(&ets_query, 0, sizeof(ets_query));
11236 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11238 if (ret != I40E_SUCCESS) {
11240 "Failed to get switch_comp ETS configuration %u",
11241 hw->aq.asq_last_status);
11244 memset(&bw_query, 0, sizeof(bw_query));
11245 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11247 if (ret != I40E_SUCCESS) {
11249 "Failed to get switch_comp bandwidth configuration %u",
11250 hw->aq.asq_last_status);
11254 /* store and print out BW info */
11255 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11256 veb->bw_info.bw_max = ets_query.tc_bw_max;
11257 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11258 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11259 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11260 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11261 I40E_16_BIT_WIDTH);
11262 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11263 veb->bw_info.bw_ets_share_credits[i] =
11264 bw_query.tc_bw_share_credits[i];
11265 veb->bw_info.bw_ets_credits[i] =
11266 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11267 /* 4 bits per TC, 4th bit is reserved */
11268 veb->bw_info.bw_ets_max[i] =
11269 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11270 RTE_LEN2MASK(3, uint8_t));
11271 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11272 veb->bw_info.bw_ets_share_credits[i]);
11273 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11274 veb->bw_info.bw_ets_credits[i]);
11275 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11276 veb->bw_info.bw_ets_max[i]);
11279 veb->enabled_tc = tc_map;
11286 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11287 * @vsi: VSI to be configured
11288 * @tc_map: enabled TC bitmap
11290 * Returns 0 on success, negative value on failure
11292 static enum i40e_status_code
11293 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11295 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11296 struct i40e_vsi_context ctxt;
11297 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11298 enum i40e_status_code ret = I40E_SUCCESS;
11301 /* Check if enabled_tc is same as existing or new TCs */
11302 if (vsi->enabled_tc == tc_map)
11305 /* configure tc bandwidth */
11306 memset(&bw_data, 0, sizeof(bw_data));
11307 bw_data.tc_valid_bits = tc_map;
11308 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11309 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11310 if (tc_map & BIT_ULL(i))
11311 bw_data.tc_bw_credits[i] = 1;
11313 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11316 "AQ command Config VSI BW allocation per TC failed = %d",
11317 hw->aq.asq_last_status);
11320 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11321 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11323 /* Update Queue Pairs Mapping for currently enabled UPs */
11324 ctxt.seid = vsi->seid;
11325 ctxt.pf_num = hw->pf_id;
11327 ctxt.uplink_seid = vsi->uplink_seid;
11328 ctxt.info = vsi->info;
11330 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11334 /* Update the VSI after updating the VSI queue-mapping information */
11335 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11337 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11338 hw->aq.asq_last_status);
11341 /* update the local VSI info with updated queue map */
11342 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11343 sizeof(vsi->info.tc_mapping));
11344 rte_memcpy(&vsi->info.queue_mapping,
11345 &ctxt.info.queue_mapping,
11346 sizeof(vsi->info.queue_mapping));
11347 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11348 vsi->info.valid_sections = 0;
11350 /* query and update current VSI BW information */
11351 ret = i40e_vsi_get_bw_config(vsi);
11354 "Failed updating vsi bw info, err %s aq_err %s",
11355 i40e_stat_str(hw, ret),
11356 i40e_aq_str(hw, hw->aq.asq_last_status));
11360 vsi->enabled_tc = tc_map;
11367 * i40e_dcb_hw_configure - program the dcb setting to hw
11368 * @pf: pf the configuration is taken on
11369 * @new_cfg: new configuration
11370 * @tc_map: enabled TC bitmap
11372 * Returns 0 on success, negative value on failure
11374 static enum i40e_status_code
11375 i40e_dcb_hw_configure(struct i40e_pf *pf,
11376 struct i40e_dcbx_config *new_cfg,
11379 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11380 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11381 struct i40e_vsi *main_vsi = pf->main_vsi;
11382 struct i40e_vsi_list *vsi_list;
11383 enum i40e_status_code ret;
11387 /* Use the FW API if FW > v4.4*/
11388 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11389 (hw->aq.fw_maj_ver >= 5))) {
11391 "FW < v4.4, can not use FW LLDP API to configure DCB");
11392 return I40E_ERR_FIRMWARE_API_VERSION;
11395 /* Check if need reconfiguration */
11396 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11397 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11398 return I40E_SUCCESS;
11401 /* Copy the new config to the current config */
11402 *old_cfg = *new_cfg;
11403 old_cfg->etsrec = old_cfg->etscfg;
11404 ret = i40e_set_dcb_config(hw);
11406 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11407 i40e_stat_str(hw, ret),
11408 i40e_aq_str(hw, hw->aq.asq_last_status));
11411 /* set receive Arbiter to RR mode and ETS scheme by default */
11412 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11413 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11414 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11415 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11416 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11417 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11418 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11419 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11420 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11421 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11422 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11423 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11424 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11426 /* get local mib to check whether it is configured correctly */
11428 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11429 /* Get Local DCB Config */
11430 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11431 &hw->local_dcbx_config);
11433 /* if Veb is created, need to update TC of it at first */
11434 if (main_vsi->veb) {
11435 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11437 PMD_INIT_LOG(WARNING,
11438 "Failed configuring TC for VEB seid=%d",
11439 main_vsi->veb->seid);
11441 /* Update each VSI */
11442 i40e_vsi_config_tc(main_vsi, tc_map);
11443 if (main_vsi->veb) {
11444 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11445 /* Beside main VSI and VMDQ VSIs, only enable default
11446 * TC for other VSIs
11448 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11449 ret = i40e_vsi_config_tc(vsi_list->vsi,
11452 ret = i40e_vsi_config_tc(vsi_list->vsi,
11453 I40E_DEFAULT_TCMAP);
11455 PMD_INIT_LOG(WARNING,
11456 "Failed configuring TC for VSI seid=%d",
11457 vsi_list->vsi->seid);
11461 return I40E_SUCCESS;
11465 * i40e_dcb_init_configure - initial dcb config
11466 * @dev: device being configured
11467 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11469 * Returns 0 on success, negative value on failure
11472 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11474 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11475 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11478 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11479 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11483 /* DCB initialization:
11484 * Update DCB configuration from the Firmware and configure
11485 * LLDP MIB change event.
11487 if (sw_dcb == TRUE) {
11488 if (i40e_need_stop_lldp(dev)) {
11489 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11490 if (ret != I40E_SUCCESS)
11491 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11494 ret = i40e_init_dcb(hw);
11495 /* If lldp agent is stopped, the return value from
11496 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11497 * adminq status. Otherwise, it should return success.
11499 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11500 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11501 memset(&hw->local_dcbx_config, 0,
11502 sizeof(struct i40e_dcbx_config));
11503 /* set dcb default configuration */
11504 hw->local_dcbx_config.etscfg.willing = 0;
11505 hw->local_dcbx_config.etscfg.maxtcs = 0;
11506 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11507 hw->local_dcbx_config.etscfg.tsatable[0] =
11509 /* all UPs mapping to TC0 */
11510 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11511 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11512 hw->local_dcbx_config.etsrec =
11513 hw->local_dcbx_config.etscfg;
11514 hw->local_dcbx_config.pfc.willing = 0;
11515 hw->local_dcbx_config.pfc.pfccap =
11516 I40E_MAX_TRAFFIC_CLASS;
11517 /* FW needs one App to configure HW */
11518 hw->local_dcbx_config.numapps = 1;
11519 hw->local_dcbx_config.app[0].selector =
11520 I40E_APP_SEL_ETHTYPE;
11521 hw->local_dcbx_config.app[0].priority = 3;
11522 hw->local_dcbx_config.app[0].protocolid =
11523 I40E_APP_PROTOID_FCOE;
11524 ret = i40e_set_dcb_config(hw);
11527 "default dcb config fails. err = %d, aq_err = %d.",
11528 ret, hw->aq.asq_last_status);
11533 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11534 ret, hw->aq.asq_last_status);
11538 ret = i40e_aq_start_lldp(hw, NULL);
11539 if (ret != I40E_SUCCESS)
11540 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11542 ret = i40e_init_dcb(hw);
11544 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11546 "HW doesn't support DCBX offload.");
11551 "DCBX configuration failed, err = %d, aq_err = %d.",
11552 ret, hw->aq.asq_last_status);
11560 * i40e_dcb_setup - setup dcb related config
11561 * @dev: device being configured
11563 * Returns 0 on success, negative value on failure
11566 i40e_dcb_setup(struct rte_eth_dev *dev)
11568 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11569 struct i40e_dcbx_config dcb_cfg;
11570 uint8_t tc_map = 0;
11573 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11574 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11578 if (pf->vf_num != 0)
11579 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11581 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11583 PMD_INIT_LOG(ERR, "invalid dcb config");
11586 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11588 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11596 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11597 struct rte_eth_dcb_info *dcb_info)
11599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11601 struct i40e_vsi *vsi = pf->main_vsi;
11602 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11603 uint16_t bsf, tc_mapping;
11606 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11607 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11609 dcb_info->nb_tcs = 1;
11610 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11611 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11612 for (i = 0; i < dcb_info->nb_tcs; i++)
11613 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11615 /* get queue mapping if vmdq is disabled */
11616 if (!pf->nb_cfg_vmdq_vsi) {
11617 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11618 if (!(vsi->enabled_tc & (1 << i)))
11620 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11621 dcb_info->tc_queue.tc_rxq[j][i].base =
11622 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11623 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11624 dcb_info->tc_queue.tc_txq[j][i].base =
11625 dcb_info->tc_queue.tc_rxq[j][i].base;
11626 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11627 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11628 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11629 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11630 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11635 /* get queue mapping if vmdq is enabled */
11637 vsi = pf->vmdq[j].vsi;
11638 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11639 if (!(vsi->enabled_tc & (1 << i)))
11641 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11642 dcb_info->tc_queue.tc_rxq[j][i].base =
11643 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11644 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11645 dcb_info->tc_queue.tc_txq[j][i].base =
11646 dcb_info->tc_queue.tc_rxq[j][i].base;
11647 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11648 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11649 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11650 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11651 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11654 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11659 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11661 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11662 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11664 uint16_t msix_intr;
11666 msix_intr = intr_handle->intr_vec[queue_id];
11667 if (msix_intr == I40E_MISC_VEC_ID)
11668 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11669 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11670 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11671 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11674 I40E_PFINT_DYN_CTLN(msix_intr -
11675 I40E_RX_VEC_START),
11676 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11677 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11678 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11680 I40E_WRITE_FLUSH(hw);
11681 rte_intr_ack(&pci_dev->intr_handle);
11687 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11689 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11690 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11691 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11692 uint16_t msix_intr;
11694 msix_intr = intr_handle->intr_vec[queue_id];
11695 if (msix_intr == I40E_MISC_VEC_ID)
11696 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11697 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11700 I40E_PFINT_DYN_CTLN(msix_intr -
11701 I40E_RX_VEC_START),
11702 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11703 I40E_WRITE_FLUSH(hw);
11709 * This function is used to check if the register is valid.
11710 * Below is the valid registers list for X722 only:
11714 * 0x208e00--0x209000
11715 * 0x20be00--0x20c000
11716 * 0x263c00--0x264000
11717 * 0x265c00--0x266000
11719 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11721 if ((type != I40E_MAC_X722) &&
11722 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11723 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11724 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11725 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11726 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11727 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11728 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11734 static int i40e_get_regs(struct rte_eth_dev *dev,
11735 struct rte_dev_reg_info *regs)
11737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11738 uint32_t *ptr_data = regs->data;
11739 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11740 const struct i40e_reg_info *reg_info;
11742 if (ptr_data == NULL) {
11743 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11744 regs->width = sizeof(uint32_t);
11748 /* The first few registers have to be read using AQ operations */
11750 while (i40e_regs_adminq[reg_idx].name) {
11751 reg_info = &i40e_regs_adminq[reg_idx++];
11752 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11754 arr_idx2 <= reg_info->count2;
11756 reg_offset = arr_idx * reg_info->stride1 +
11757 arr_idx2 * reg_info->stride2;
11758 reg_offset += reg_info->base_addr;
11759 ptr_data[reg_offset >> 2] =
11760 i40e_read_rx_ctl(hw, reg_offset);
11764 /* The remaining registers can be read using primitives */
11766 while (i40e_regs_others[reg_idx].name) {
11767 reg_info = &i40e_regs_others[reg_idx++];
11768 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11770 arr_idx2 <= reg_info->count2;
11772 reg_offset = arr_idx * reg_info->stride1 +
11773 arr_idx2 * reg_info->stride2;
11774 reg_offset += reg_info->base_addr;
11775 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11776 ptr_data[reg_offset >> 2] = 0;
11778 ptr_data[reg_offset >> 2] =
11779 I40E_READ_REG(hw, reg_offset);
11786 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11788 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11790 /* Convert word count to byte count */
11791 return hw->nvm.sr_size << 1;
11794 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11795 struct rte_dev_eeprom_info *eeprom)
11797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11798 uint16_t *data = eeprom->data;
11799 uint16_t offset, length, cnt_words;
11802 offset = eeprom->offset >> 1;
11803 length = eeprom->length >> 1;
11804 cnt_words = length;
11806 if (offset > hw->nvm.sr_size ||
11807 offset + length > hw->nvm.sr_size) {
11808 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11812 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11814 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11815 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11816 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11823 static int i40e_get_module_info(struct rte_eth_dev *dev,
11824 struct rte_eth_dev_module_info *modinfo)
11826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11827 uint32_t sff8472_comp = 0;
11828 uint32_t sff8472_swap = 0;
11829 uint32_t sff8636_rev = 0;
11830 i40e_status status;
11833 /* Check if firmware supports reading module EEPROM. */
11834 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11836 "Module EEPROM memory read not supported. "
11837 "Please update the NVM image.\n");
11841 status = i40e_update_link_info(hw);
11845 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11847 "Cannot read module EEPROM memory. "
11848 "No module connected.\n");
11852 type = hw->phy.link_info.module_type[0];
11855 case I40E_MODULE_TYPE_SFP:
11856 status = i40e_aq_get_phy_register(hw,
11857 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11858 I40E_I2C_EEPROM_DEV_ADDR, 1,
11859 I40E_MODULE_SFF_8472_COMP,
11860 &sff8472_comp, NULL);
11864 status = i40e_aq_get_phy_register(hw,
11865 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11866 I40E_I2C_EEPROM_DEV_ADDR, 1,
11867 I40E_MODULE_SFF_8472_SWAP,
11868 &sff8472_swap, NULL);
11872 /* Check if the module requires address swap to access
11873 * the other EEPROM memory page.
11875 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11876 PMD_DRV_LOG(WARNING,
11877 "Module address swap to access "
11878 "page 0xA2 is not supported.\n");
11879 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11880 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11881 } else if (sff8472_comp == 0x00) {
11882 /* Module is not SFF-8472 compliant */
11883 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11884 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11886 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11887 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11890 case I40E_MODULE_TYPE_QSFP_PLUS:
11891 /* Read from memory page 0. */
11892 status = i40e_aq_get_phy_register(hw,
11893 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11895 I40E_MODULE_REVISION_ADDR,
11896 &sff8636_rev, NULL);
11899 /* Determine revision compliance byte */
11900 if (sff8636_rev > 0x02) {
11901 /* Module is SFF-8636 compliant */
11902 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11903 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11905 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11906 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11909 case I40E_MODULE_TYPE_QSFP28:
11910 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11911 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11914 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11920 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11921 struct rte_dev_eeprom_info *info)
11923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11924 bool is_sfp = false;
11925 i40e_status status;
11927 uint32_t value = 0;
11930 if (!info || !info->length || !info->data)
11933 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11937 for (i = 0; i < info->length; i++) {
11938 u32 offset = i + info->offset;
11939 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11941 /* Check if we need to access the other memory page */
11943 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11944 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11945 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11948 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11949 /* Compute memory page number and offset. */
11950 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11954 status = i40e_aq_get_phy_register(hw,
11955 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11956 addr, offset, 1, &value, NULL);
11959 data[i] = (uint8_t)value;
11964 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11965 struct rte_ether_addr *mac_addr)
11967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11968 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11969 struct i40e_vsi *vsi = pf->main_vsi;
11970 struct i40e_mac_filter_info mac_filter;
11971 struct i40e_mac_filter *f;
11974 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11975 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11979 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11980 if (rte_is_same_ether_addr(&pf->dev_addr,
11981 &f->mac_info.mac_addr))
11986 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11990 mac_filter = f->mac_info;
11991 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11992 if (ret != I40E_SUCCESS) {
11993 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11996 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11997 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11998 if (ret != I40E_SUCCESS) {
11999 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12002 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12004 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12005 mac_addr->addr_bytes, NULL);
12006 if (ret != I40E_SUCCESS) {
12007 PMD_DRV_LOG(ERR, "Failed to change mac");
12015 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12018 struct rte_eth_dev_data *dev_data = pf->dev_data;
12019 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12022 /* check if mtu is within the allowed range */
12023 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12026 /* mtu setting is forbidden if port is start */
12027 if (dev_data->dev_started) {
12028 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12029 dev_data->port_id);
12033 if (frame_size > RTE_ETHER_MAX_LEN)
12034 dev_data->dev_conf.rxmode.offloads |=
12035 DEV_RX_OFFLOAD_JUMBO_FRAME;
12037 dev_data->dev_conf.rxmode.offloads &=
12038 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12040 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12045 /* Restore ethertype filter */
12047 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12049 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12050 struct i40e_ethertype_filter_list
12051 *ethertype_list = &pf->ethertype.ethertype_list;
12052 struct i40e_ethertype_filter *f;
12053 struct i40e_control_filter_stats stats;
12056 TAILQ_FOREACH(f, ethertype_list, rules) {
12058 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12059 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12060 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12061 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12062 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12064 memset(&stats, 0, sizeof(stats));
12065 i40e_aq_add_rem_control_packet_filter(hw,
12066 f->input.mac_addr.addr_bytes,
12067 f->input.ether_type,
12068 flags, pf->main_vsi->seid,
12069 f->queue, 1, &stats, NULL);
12071 PMD_DRV_LOG(INFO, "Ethertype filter:"
12072 " mac_etype_used = %u, etype_used = %u,"
12073 " mac_etype_free = %u, etype_free = %u",
12074 stats.mac_etype_used, stats.etype_used,
12075 stats.mac_etype_free, stats.etype_free);
12078 /* Restore tunnel filter */
12080 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12082 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12083 struct i40e_vsi *vsi;
12084 struct i40e_pf_vf *vf;
12085 struct i40e_tunnel_filter_list
12086 *tunnel_list = &pf->tunnel.tunnel_list;
12087 struct i40e_tunnel_filter *f;
12088 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12089 bool big_buffer = 0;
12091 TAILQ_FOREACH(f, tunnel_list, rules) {
12093 vsi = pf->main_vsi;
12095 vf = &pf->vfs[f->vf_id];
12098 memset(&cld_filter, 0, sizeof(cld_filter));
12099 rte_ether_addr_copy((struct rte_ether_addr *)
12100 &f->input.outer_mac,
12101 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12102 rte_ether_addr_copy((struct rte_ether_addr *)
12103 &f->input.inner_mac,
12104 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12105 cld_filter.element.inner_vlan = f->input.inner_vlan;
12106 cld_filter.element.flags = f->input.flags;
12107 cld_filter.element.tenant_id = f->input.tenant_id;
12108 cld_filter.element.queue_number = f->queue;
12109 rte_memcpy(cld_filter.general_fields,
12110 f->input.general_fields,
12111 sizeof(f->input.general_fields));
12113 if (((f->input.flags &
12114 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12115 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12117 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12118 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12120 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12121 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12125 i40e_aq_add_cloud_filters_bb(hw,
12126 vsi->seid, &cld_filter, 1);
12128 i40e_aq_add_cloud_filters(hw, vsi->seid,
12129 &cld_filter.element, 1);
12133 /* Restore rss filter */
12135 i40e_rss_filter_restore(struct i40e_pf *pf)
12137 struct i40e_rte_flow_rss_conf *conf =
12139 if (conf->conf.queue_num)
12140 i40e_config_rss_filter(pf, conf, TRUE);
12144 i40e_filter_restore(struct i40e_pf *pf)
12146 i40e_ethertype_filter_restore(pf);
12147 i40e_tunnel_filter_restore(pf);
12148 i40e_fdir_filter_restore(pf);
12149 i40e_rss_filter_restore(pf);
12153 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12155 if (strcmp(dev->device->driver->name, drv->driver.name))
12162 is_i40e_supported(struct rte_eth_dev *dev)
12164 return is_device_supported(dev, &rte_i40e_pmd);
12167 struct i40e_customized_pctype*
12168 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12172 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12173 if (pf->customized_pctype[i].index == index)
12174 return &pf->customized_pctype[i];
12180 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12181 uint32_t pkg_size, uint32_t proto_num,
12182 struct rte_pmd_i40e_proto_info *proto,
12183 enum rte_pmd_i40e_package_op op)
12185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12186 uint32_t pctype_num;
12187 struct rte_pmd_i40e_ptype_info *pctype;
12188 uint32_t buff_size;
12189 struct i40e_customized_pctype *new_pctype = NULL;
12191 uint8_t pctype_value;
12196 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12197 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12198 PMD_DRV_LOG(ERR, "Unsupported operation.");
12202 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12203 (uint8_t *)&pctype_num, sizeof(pctype_num),
12204 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12206 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12210 PMD_DRV_LOG(INFO, "No new pctype added");
12214 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12215 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12217 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12220 /* get information about new pctype list */
12221 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12222 (uint8_t *)pctype, buff_size,
12223 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12225 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12230 /* Update customized pctype. */
12231 for (i = 0; i < pctype_num; i++) {
12232 pctype_value = pctype[i].ptype_id;
12233 memset(name, 0, sizeof(name));
12234 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12235 proto_id = pctype[i].protocols[j];
12236 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12238 for (n = 0; n < proto_num; n++) {
12239 if (proto[n].proto_id != proto_id)
12241 strlcat(name, proto[n].name, sizeof(name));
12242 strlcat(name, "_", sizeof(name));
12246 name[strlen(name) - 1] = '\0';
12247 if (!strcmp(name, "GTPC"))
12249 i40e_find_customized_pctype(pf,
12250 I40E_CUSTOMIZED_GTPC);
12251 else if (!strcmp(name, "GTPU_IPV4"))
12253 i40e_find_customized_pctype(pf,
12254 I40E_CUSTOMIZED_GTPU_IPV4);
12255 else if (!strcmp(name, "GTPU_IPV6"))
12257 i40e_find_customized_pctype(pf,
12258 I40E_CUSTOMIZED_GTPU_IPV6);
12259 else if (!strcmp(name, "GTPU"))
12261 i40e_find_customized_pctype(pf,
12262 I40E_CUSTOMIZED_GTPU);
12264 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12265 new_pctype->pctype = pctype_value;
12266 new_pctype->valid = true;
12268 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12269 new_pctype->valid = false;
12279 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12280 uint32_t pkg_size, uint32_t proto_num,
12281 struct rte_pmd_i40e_proto_info *proto,
12282 enum rte_pmd_i40e_package_op op)
12284 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12285 uint16_t port_id = dev->data->port_id;
12286 uint32_t ptype_num;
12287 struct rte_pmd_i40e_ptype_info *ptype;
12288 uint32_t buff_size;
12290 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12295 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12296 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12297 PMD_DRV_LOG(ERR, "Unsupported operation.");
12301 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12302 rte_pmd_i40e_ptype_mapping_reset(port_id);
12306 /* get information about new ptype num */
12307 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12308 (uint8_t *)&ptype_num, sizeof(ptype_num),
12309 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12311 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12315 PMD_DRV_LOG(INFO, "No new ptype added");
12319 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12320 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12322 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12326 /* get information about new ptype list */
12327 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12328 (uint8_t *)ptype, buff_size,
12329 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12331 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12336 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12337 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12338 if (!ptype_mapping) {
12339 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12344 /* Update ptype mapping table. */
12345 for (i = 0; i < ptype_num; i++) {
12346 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12347 ptype_mapping[i].sw_ptype = 0;
12349 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12350 proto_id = ptype[i].protocols[j];
12351 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12353 for (n = 0; n < proto_num; n++) {
12354 if (proto[n].proto_id != proto_id)
12356 memset(name, 0, sizeof(name));
12357 strcpy(name, proto[n].name);
12358 if (!strncasecmp(name, "PPPOE", 5))
12359 ptype_mapping[i].sw_ptype |=
12360 RTE_PTYPE_L2_ETHER_PPPOE;
12361 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12363 ptype_mapping[i].sw_ptype |=
12364 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12365 ptype_mapping[i].sw_ptype |=
12367 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12369 ptype_mapping[i].sw_ptype |=
12370 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12371 ptype_mapping[i].sw_ptype |=
12372 RTE_PTYPE_INNER_L4_FRAG;
12373 } else if (!strncasecmp(name, "OIPV4", 5)) {
12374 ptype_mapping[i].sw_ptype |=
12375 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12377 } else if (!strncasecmp(name, "IPV4", 4) &&
12379 ptype_mapping[i].sw_ptype |=
12380 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12381 else if (!strncasecmp(name, "IPV4", 4) &&
12383 ptype_mapping[i].sw_ptype |=
12384 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12385 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12387 ptype_mapping[i].sw_ptype |=
12388 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12389 ptype_mapping[i].sw_ptype |=
12391 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12393 ptype_mapping[i].sw_ptype |=
12394 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12395 ptype_mapping[i].sw_ptype |=
12396 RTE_PTYPE_INNER_L4_FRAG;
12397 } else if (!strncasecmp(name, "OIPV6", 5)) {
12398 ptype_mapping[i].sw_ptype |=
12399 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12401 } else if (!strncasecmp(name, "IPV6", 4) &&
12403 ptype_mapping[i].sw_ptype |=
12404 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12405 else if (!strncasecmp(name, "IPV6", 4) &&
12407 ptype_mapping[i].sw_ptype |=
12408 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12409 else if (!strncasecmp(name, "UDP", 3) &&
12411 ptype_mapping[i].sw_ptype |=
12413 else if (!strncasecmp(name, "UDP", 3) &&
12415 ptype_mapping[i].sw_ptype |=
12416 RTE_PTYPE_INNER_L4_UDP;
12417 else if (!strncasecmp(name, "TCP", 3) &&
12419 ptype_mapping[i].sw_ptype |=
12421 else if (!strncasecmp(name, "TCP", 3) &&
12423 ptype_mapping[i].sw_ptype |=
12424 RTE_PTYPE_INNER_L4_TCP;
12425 else if (!strncasecmp(name, "SCTP", 4) &&
12427 ptype_mapping[i].sw_ptype |=
12429 else if (!strncasecmp(name, "SCTP", 4) &&
12431 ptype_mapping[i].sw_ptype |=
12432 RTE_PTYPE_INNER_L4_SCTP;
12433 else if ((!strncasecmp(name, "ICMP", 4) ||
12434 !strncasecmp(name, "ICMPV6", 6)) &&
12436 ptype_mapping[i].sw_ptype |=
12438 else if ((!strncasecmp(name, "ICMP", 4) ||
12439 !strncasecmp(name, "ICMPV6", 6)) &&
12441 ptype_mapping[i].sw_ptype |=
12442 RTE_PTYPE_INNER_L4_ICMP;
12443 else if (!strncasecmp(name, "GTPC", 4)) {
12444 ptype_mapping[i].sw_ptype |=
12445 RTE_PTYPE_TUNNEL_GTPC;
12447 } else if (!strncasecmp(name, "GTPU", 4)) {
12448 ptype_mapping[i].sw_ptype |=
12449 RTE_PTYPE_TUNNEL_GTPU;
12451 } else if (!strncasecmp(name, "GRENAT", 6)) {
12452 ptype_mapping[i].sw_ptype |=
12453 RTE_PTYPE_TUNNEL_GRENAT;
12455 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12456 !strncasecmp(name, "L2TPV2", 6)) {
12457 ptype_mapping[i].sw_ptype |=
12458 RTE_PTYPE_TUNNEL_L2TP;
12467 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12470 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12472 rte_free(ptype_mapping);
12478 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12479 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12482 uint32_t proto_num;
12483 struct rte_pmd_i40e_proto_info *proto;
12484 uint32_t buff_size;
12488 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12489 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12490 PMD_DRV_LOG(ERR, "Unsupported operation.");
12494 /* get information about protocol number */
12495 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12496 (uint8_t *)&proto_num, sizeof(proto_num),
12497 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12499 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12503 PMD_DRV_LOG(INFO, "No new protocol added");
12507 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12508 proto = rte_zmalloc("new_proto", buff_size, 0);
12510 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12514 /* get information about protocol list */
12515 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12516 (uint8_t *)proto, buff_size,
12517 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12519 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12524 /* Check if GTP is supported. */
12525 for (i = 0; i < proto_num; i++) {
12526 if (!strncmp(proto[i].name, "GTP", 3)) {
12527 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12528 pf->gtp_support = true;
12530 pf->gtp_support = false;
12535 /* Update customized pctype info */
12536 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12537 proto_num, proto, op);
12539 PMD_DRV_LOG(INFO, "No pctype is updated.");
12541 /* Update customized ptype info */
12542 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12543 proto_num, proto, op);
12545 PMD_DRV_LOG(INFO, "No ptype is updated.");
12550 /* Create a QinQ cloud filter
12552 * The Fortville NIC has limited resources for tunnel filters,
12553 * so we can only reuse existing filters.
12555 * In step 1 we define which Field Vector fields can be used for
12557 * As we do not have the inner tag defined as a field,
12558 * we have to define it first, by reusing one of L1 entries.
12560 * In step 2 we are replacing one of existing filter types with
12561 * a new one for QinQ.
12562 * As we reusing L1 and replacing L2, some of the default filter
12563 * types will disappear,which depends on L1 and L2 entries we reuse.
12565 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12567 * 1. Create L1 filter of outer vlan (12b) which will be in use
12568 * later when we define the cloud filter.
12569 * a. Valid_flags.replace_cloud = 0
12570 * b. Old_filter = 10 (Stag_Inner_Vlan)
12571 * c. New_filter = 0x10
12572 * d. TR bit = 0xff (optional, not used here)
12573 * e. Buffer – 2 entries:
12574 * i. Byte 0 = 8 (outer vlan FV index).
12576 * Byte 2-3 = 0x0fff
12577 * ii. Byte 0 = 37 (inner vlan FV index).
12579 * Byte 2-3 = 0x0fff
12582 * 2. Create cloud filter using two L1 filters entries: stag and
12583 * new filter(outer vlan+ inner vlan)
12584 * a. Valid_flags.replace_cloud = 1
12585 * b. Old_filter = 1 (instead of outer IP)
12586 * c. New_filter = 0x10
12587 * d. Buffer – 2 entries:
12588 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12589 * Byte 1-3 = 0 (rsv)
12590 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12591 * Byte 9-11 = 0 (rsv)
12594 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12596 int ret = -ENOTSUP;
12597 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12598 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12600 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12602 if (pf->support_multi_driver) {
12603 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12608 memset(&filter_replace, 0,
12609 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12610 memset(&filter_replace_buf, 0,
12611 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12613 /* create L1 filter */
12614 filter_replace.old_filter_type =
12615 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12616 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12617 filter_replace.tr_bit = 0;
12619 /* Prepare the buffer, 2 entries */
12620 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12621 filter_replace_buf.data[0] |=
12622 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12623 /* Field Vector 12b mask */
12624 filter_replace_buf.data[2] = 0xff;
12625 filter_replace_buf.data[3] = 0x0f;
12626 filter_replace_buf.data[4] =
12627 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12628 filter_replace_buf.data[4] |=
12629 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12630 /* Field Vector 12b mask */
12631 filter_replace_buf.data[6] = 0xff;
12632 filter_replace_buf.data[7] = 0x0f;
12633 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12634 &filter_replace_buf);
12635 if (ret != I40E_SUCCESS)
12638 if (filter_replace.old_filter_type !=
12639 filter_replace.new_filter_type)
12640 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12641 " original: 0x%x, new: 0x%x",
12643 filter_replace.old_filter_type,
12644 filter_replace.new_filter_type);
12646 /* Apply the second L2 cloud filter */
12647 memset(&filter_replace, 0,
12648 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12649 memset(&filter_replace_buf, 0,
12650 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12652 /* create L2 filter, input for L2 filter will be L1 filter */
12653 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12654 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12655 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12657 /* Prepare the buffer, 2 entries */
12658 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12659 filter_replace_buf.data[0] |=
12660 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12661 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12662 filter_replace_buf.data[4] |=
12663 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12664 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12665 &filter_replace_buf);
12666 if (!ret && (filter_replace.old_filter_type !=
12667 filter_replace.new_filter_type))
12668 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12669 " original: 0x%x, new: 0x%x",
12671 filter_replace.old_filter_type,
12672 filter_replace.new_filter_type);
12678 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12679 const struct rte_flow_action_rss *in)
12681 if (in->key_len > RTE_DIM(out->key) ||
12682 in->queue_num > RTE_DIM(out->queue))
12684 if (!in->key && in->key_len)
12686 out->conf = (struct rte_flow_action_rss){
12688 .level = in->level,
12689 .types = in->types,
12690 .key_len = in->key_len,
12691 .queue_num = in->queue_num,
12692 .queue = memcpy(out->queue, in->queue,
12693 sizeof(*in->queue) * in->queue_num),
12696 out->conf.key = memcpy(out->key, in->key, in->key_len);
12701 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12702 const struct rte_flow_action_rss *with)
12704 return (comp->func == with->func &&
12705 comp->level == with->level &&
12706 comp->types == with->types &&
12707 comp->key_len == with->key_len &&
12708 comp->queue_num == with->queue_num &&
12709 !memcmp(comp->key, with->key, with->key_len) &&
12710 !memcmp(comp->queue, with->queue,
12711 sizeof(*with->queue) * with->queue_num));
12715 i40e_config_rss_filter(struct i40e_pf *pf,
12716 struct i40e_rte_flow_rss_conf *conf, bool add)
12718 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12719 uint32_t i, lut = 0;
12721 struct rte_eth_rss_conf rss_conf = {
12722 .rss_key = conf->conf.key_len ?
12723 (void *)(uintptr_t)conf->conf.key : NULL,
12724 .rss_key_len = conf->conf.key_len,
12725 .rss_hf = conf->conf.types,
12727 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12730 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12731 i40e_pf_disable_rss(pf);
12732 memset(rss_info, 0,
12733 sizeof(struct i40e_rte_flow_rss_conf));
12739 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12740 * It's necessary to calculate the actual PF queues that are configured.
12742 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12743 num = i40e_pf_calc_configured_queues_num(pf);
12745 num = pf->dev_data->nb_rx_queues;
12747 num = RTE_MIN(num, conf->conf.queue_num);
12748 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12752 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12756 /* Fill in redirection table */
12757 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12760 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12761 hw->func_caps.rss_table_entry_width) - 1));
12763 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12766 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12767 i40e_pf_disable_rss(pf);
12770 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12771 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12772 /* Random default keys */
12773 static uint32_t rss_key_default[] = {0x6b793944,
12774 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12775 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12776 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12778 rss_conf.rss_key = (uint8_t *)rss_key_default;
12779 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12782 "No valid RSS key config for i40e, using default\n");
12785 i40e_hw_rss_hash_set(pf, &rss_conf);
12787 if (i40e_rss_conf_init(rss_info, &conf->conf))
12793 RTE_INIT(i40e_init_log)
12795 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12796 if (i40e_logtype_init >= 0)
12797 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12798 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12799 if (i40e_logtype_driver >= 0)
12800 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12803 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12804 ETH_I40E_FLOATING_VEB_ARG "=1"
12805 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12806 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12807 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12808 ETH_I40E_USE_LATEST_VEC "=0|1");