drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 328                                 char *fw_version, size_t fw_size);
 329 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 330                               struct rte_eth_dev_info *dev_info);
 331 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 332                                 uint16_t vlan_id,
 333                                 int on);
 334 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 335                               enum rte_vlan_type vlan_type,
 336                               uint16_t tpid);
 337 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 338 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 339                                       uint16_t queue,
 340                                       int on);
 341 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 342 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 343 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 344 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 347                               struct rte_eth_fc_conf *fc_conf);
 348 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 349                                        struct rte_eth_pfc_conf *pfc_conf);
 350 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 351                           struct ether_addr *mac_addr,
 352                           uint32_t index,
 353                           uint32_t pool);
 354 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 355 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 356                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 357                                     uint16_t reta_size);
 358 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 359                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 360                                    uint16_t reta_size);
 361
 362 static int i40e_get_cap(struct i40e_hw *hw);
 363 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 364 static int i40e_pf_setup(struct i40e_pf *pf);
 365 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 366 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 367 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 368 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 369 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 370                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 371 static void i40e_stat_update_48(struct i40e_hw *hw,
 372                                uint32_t hireg,
 373                                uint32_t loreg,
 374                                bool offset_loaded,
 375                                uint64_t *offset,
 376                                uint64_t *stat);
 377 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 378 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 379                                        void *param);
 380 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 381                                 uint32_t base, uint32_t num);
 382 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 383 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 384                         uint32_t base);
 385 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 386                         uint16_t num);
 387 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 388 static int i40e_veb_release(struct i40e_veb *veb);
 389 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 390                                                 struct i40e_vsi *vsi);
 391 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 392 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 393 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 394                                              struct i40e_macvlan_filter *mv_f,
 395                                              int num,
 396                                              struct ether_addr *addr);
 397 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 398                                              struct i40e_macvlan_filter *mv_f,
 399                                              int num,
 400                                              uint16_t vlan);
 401 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 402 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 403                                     struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 405                                       struct rte_eth_rss_conf *rss_conf);
 406 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 409                                         struct rte_eth_udp_tunnel *udp_tunnel);
 410 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 411 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 412                         struct rte_eth_ethertype_filter *filter,
 413                         bool add);
 414 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 415                                 enum rte_filter_op filter_op,
 416                                 void *arg);
 417 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 418                                 enum rte_filter_type filter_type,
 419                                 enum rte_filter_op filter_op,
 420                                 void *arg);
 421 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 422                                   struct rte_eth_dcb_info *dcb_info);
 423 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 424 static void i40e_configure_registers(struct i40e_hw *hw);
 425 static void i40e_hw_init(struct rte_eth_dev *dev);
 426 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 427 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 428                         struct rte_eth_mirror_conf *mirror_conf,
 429                         uint8_t sw_id, uint8_t on);
 430 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 431
 432 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 433 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 434 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 435                                            struct timespec *timestamp,
 436                                            uint32_t flags);
 437 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 438                                            struct timespec *timestamp);
 439 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 440
 441 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 442
 443 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 444                                    struct timespec *timestamp);
 445 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 446                                     const struct timespec *timestamp);
 447
 448 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 449                                          uint16_t queue_id);
 450 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 451                                           uint16_t queue_id);
 452
 453 static int i40e_get_regs(struct rte_eth_dev *dev,
 454                          struct rte_dev_reg_info *regs);
 455
 456 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 457
 458 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 459                            struct rte_dev_eeprom_info *eeprom);
 460
 461 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 462                                       struct ether_addr *mac_addr);
 463
 464 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 465
 466 static const struct rte_pci_id pci_id_i40e_map[] = {
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 static const struct eth_dev_ops i40e_eth_dev_ops = {
 491         .dev_configure                = i40e_dev_configure,
 492         .dev_start                    = i40e_dev_start,
 493         .dev_stop                     = i40e_dev_stop,
 494         .dev_close                    = i40e_dev_close,
 495         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 496         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 497         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 498         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 499         .dev_set_link_up              = i40e_dev_set_link_up,
 500         .dev_set_link_down            = i40e_dev_set_link_down,
 501         .link_update                  = i40e_dev_link_update,
 502         .stats_get                    = i40e_dev_stats_get,
 503         .xstats_get                   = i40e_dev_xstats_get,
 504         .xstats_get_names             = i40e_dev_xstats_get_names,
 505         .stats_reset                  = i40e_dev_stats_reset,
 506         .xstats_reset                 = i40e_dev_stats_reset,
 507         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 508         .fw_version_get               = i40e_fw_version_get,
 509         .dev_infos_get                = i40e_dev_info_get,
 510         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 511         .vlan_filter_set              = i40e_vlan_filter_set,
 512         .vlan_tpid_set                = i40e_vlan_tpid_set,
 513         .vlan_offload_set             = i40e_vlan_offload_set,
 514         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 515         .vlan_pvid_set                = i40e_vlan_pvid_set,
 516         .rx_queue_start               = i40e_dev_rx_queue_start,
 517         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 518         .tx_queue_start               = i40e_dev_tx_queue_start,
 519         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 520         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 521         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 522         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 523         .rx_queue_release             = i40e_dev_rx_queue_release,
 524         .rx_queue_count               = i40e_dev_rx_queue_count,
 525         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 526         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 527         .tx_queue_release             = i40e_dev_tx_queue_release,
 528         .dev_led_on                   = i40e_dev_led_on,
 529         .dev_led_off                  = i40e_dev_led_off,
 530         .flow_ctrl_get                = i40e_flow_ctrl_get,
 531         .flow_ctrl_set                = i40e_flow_ctrl_set,
 532         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 533         .mac_addr_add                 = i40e_macaddr_add,
 534         .mac_addr_remove              = i40e_macaddr_remove,
 535         .reta_update                  = i40e_dev_rss_reta_update,
 536         .reta_query                   = i40e_dev_rss_reta_query,
 537         .rss_hash_update              = i40e_dev_rss_hash_update,
 538         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 539         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 541         .filter_ctrl                  = i40e_dev_filter_ctrl,
 542         .rxq_info_get                 = i40e_rxq_info_get,
 543         .txq_info_get                 = i40e_txq_info_get,
 544         .mirror_rule_set              = i40e_mirror_rule_set,
 545         .mirror_rule_reset            = i40e_mirror_rule_reset,
 546         .timesync_enable              = i40e_timesync_enable,
 547         .timesync_disable             = i40e_timesync_disable,
 548         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 549         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 550         .get_dcb_info                 = i40e_dev_get_dcb_info,
 551         .timesync_adjust_time         = i40e_timesync_adjust_time,
 552         .timesync_read_time           = i40e_timesync_read_time,
 553         .timesync_write_time          = i40e_timesync_write_time,
 554         .get_reg                      = i40e_get_regs,
 555         .get_eeprom_length            = i40e_get_eeprom_length,
 556         .get_eeprom                   = i40e_get_eeprom,
 557         .mac_addr_set                 = i40e_set_default_mac_addr,
 558         .mtu_set                      = i40e_dev_mtu_set,
 559 };
 560
 561 /* store statistics names and its offset in stats structure */
 562 struct rte_i40e_xstats_name_off {
 563         char name[RTE_ETH_XSTATS_NAME_SIZE];
 564         unsigned offset;
 565 };
 566
 567 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 568         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 569         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 570         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 571         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 572         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 573                 rx_unknown_protocol)},
 574         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 575         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 576         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 577         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 578 };
 579
 580 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 581                 sizeof(rte_i40e_stats_strings[0]))
 582
 583 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 584         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 585                 tx_dropped_link_down)},
 586         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 587         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 588                 illegal_bytes)},
 589         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 590         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 591                 mac_local_faults)},
 592         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 593                 mac_remote_faults)},
 594         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 595                 rx_length_errors)},
 596         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 597         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 598         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 599         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 600         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 601         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_127)},
 603         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 604                 rx_size_255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_511)},
 607         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_1023)},
 609         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_1522)},
 611         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 612                 rx_size_big)},
 613         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 614                 rx_undersize)},
 615         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 616                 rx_oversize)},
 617         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 618                 mac_short_packet_dropped)},
 619         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 620                 rx_fragments)},
 621         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 622         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_127)},
 625         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 626                 tx_size_255)},
 627         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_1023)},
 631         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_1522)},
 633         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 634                 tx_size_big)},
 635         {"rx_flow_director_atr_match_packets",
 636                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 637         {"rx_flow_director_sb_match_packets",
 638                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 639         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 640                 tx_lpi_status)},
 641         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 642                 rx_lpi_status)},
 643         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 644                 tx_lpi_count)},
 645         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 646                 rx_lpi_count)},
 647 };
 648
 649 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 650                 sizeof(rte_i40e_hw_port_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_rx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_rx)},
 657 };
 658
 659 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 660                 sizeof(rte_i40e_rxq_prio_strings[0]))
 661
 662 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 663         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 664                 priority_xon_tx)},
 665         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 666                 priority_xoff_tx)},
 667         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 668                 priority_xon_2_xoff)},
 669 };
 670
 671 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 672                 sizeof(rte_i40e_txq_prio_strings[0]))
 673
 674 static struct eth_driver rte_i40e_pmd = {
 675         .pci_drv = {
 676                 .id_table = pci_id_i40e_map,
 677                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 678                 .probe = rte_eth_dev_pci_probe,
 679                 .remove = rte_eth_dev_pci_remove,
 680         },
 681         .eth_dev_init = eth_i40e_dev_init,
 682         .eth_dev_uninit = eth_i40e_dev_uninit,
 683         .dev_private_size = sizeof(struct i40e_adapter),
 684 };
 685
 686 static inline int
 687 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 688                                      struct rte_eth_link *link)
 689 {
 690         struct rte_eth_link *dst = link;
 691         struct rte_eth_link *src = &(dev->data->dev_link);
 692
 693         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 694                                         *(uint64_t *)src) == 0)
 695                 return -1;
 696
 697         return 0;
 698 }
 699
 700 static inline int
 701 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 702                                       struct rte_eth_link *link)
 703 {
 704         struct rte_eth_link *dst = &(dev->data->dev_link);
 705         struct rte_eth_link *src = link;
 706
 707         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 708                                         *(uint64_t *)src) == 0)
 709                 return -1;
 710
 711         return 0;
 712 }
 713
 714 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 715 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 716 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 717
 718 #ifndef I40E_GLQF_ORT
 719 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 720 #endif
 721 #ifndef I40E_GLQF_PIT
 722 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 723 #endif
 724
 725 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 726 {
 727         /*
 728          * Initialize registers for flexible payload, which should be set by NVM.
 729          * This should be removed from code once it is fixed in NVM.
 730          */
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 739         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 740         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 741         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 742         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 743
 744         /* Initialize registers for parsing packet type of QinQ */
 745         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 750
 751 /*
 752  * Add a ethertype filter to drop all flow control frames transmitted
 753  * from VSIs.
 754 */
 755 static void
 756 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 757 {
 758         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 759         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 760                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 761                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 762         int ret;
 763
 764         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 765                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 766                                 pf->main_vsi_seid, 0,
 767                                 TRUE, NULL, NULL);
 768         if (ret)
 769                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 770                                   " frames from VSIs.");
 771 }
 772
 773 static int
 774 floating_veb_list_handler(__rte_unused const char *key,
 775                           const char *floating_veb_value,
 776                           void *opaque)
 777 {
 778         int idx = 0;
 779         unsigned int count = 0;
 780         char *end = NULL;
 781         int min, max;
 782         bool *vf_floating_veb = opaque;
 783
 784         while (isblank(*floating_veb_value))
 785                 floating_veb_value++;
 786
 787         /* Reset floating VEB configuration for VFs */
 788         for (idx = 0; idx < I40E_MAX_VF; idx++)
 789                 vf_floating_veb[idx] = false;
 790
 791         min = I40E_MAX_VF;
 792         do {
 793                 while (isblank(*floating_veb_value))
 794                         floating_veb_value++;
 795                 if (*floating_veb_value == '\0')
 796                         return -1;
 797                 errno = 0;
 798                 idx = strtoul(floating_veb_value, &end, 10);
 799                 if (errno || end == NULL)
 800                         return -1;
 801                 while (isblank(*end))
 802                         end++;
 803                 if (*end == '-') {
 804                         min = idx;
 805                 } else if ((*end == ';') || (*end == '\0')) {
 806                         max = idx;
 807                         if (min == I40E_MAX_VF)
 808                                 min = idx;
 809                         if (max >= I40E_MAX_VF)
 810                                 max = I40E_MAX_VF - 1;
 811                         for (idx = min; idx <= max; idx++) {
 812                                 vf_floating_veb[idx] = true;
 813                                 count++;
 814                         }
 815                         min = I40E_MAX_VF;
 816                 } else {
 817                         return -1;
 818                 }
 819                 floating_veb_value = end + 1;
 820         } while (*end != '\0');
 821
 822         if (count == 0)
 823                 return -1;
 824
 825         return 0;
 826 }
 827
 828 static void
 829 config_vf_floating_veb(struct rte_devargs *devargs,
 830                        uint16_t floating_veb,
 831                        bool *vf_floating_veb)
 832 {
 833         struct rte_kvargs *kvlist;
 834         int i;
 835         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 836
 837         if (!floating_veb)
 838                 return;
 839         /* All the VFs attach to the floating VEB by default
 840          * when the floating VEB is enabled.
 841          */
 842         for (i = 0; i < I40E_MAX_VF; i++)
 843                 vf_floating_veb[i] = true;
 844
 845         if (devargs == NULL)
 846                 return;
 847
 848         kvlist = rte_kvargs_parse(devargs->args, NULL);
 849         if (kvlist == NULL)
 850                 return;
 851
 852         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 853                 rte_kvargs_free(kvlist);
 854                 return;
 855         }
 856         /* When the floating_veb_list parameter exists, all the VFs
 857          * will attach to the legacy VEB firstly, then configure VFs
 858          * to the floating VEB according to the floating_veb_list.
 859          */
 860         if (rte_kvargs_process(kvlist, floating_veb_list,
 861                                floating_veb_list_handler,
 862                                vf_floating_veb) < 0) {
 863                 rte_kvargs_free(kvlist);
 864                 return;
 865         }
 866         rte_kvargs_free(kvlist);
 867 }
 868
 869 static int
 870 i40e_check_floating_handler(__rte_unused const char *key,
 871                             const char *value,
 872                             __rte_unused void *opaque)
 873 {
 874         if (strcmp(value, "1"))
 875                 return -1;
 876
 877         return 0;
 878 }
 879
 880 static int
 881 is_floating_veb_supported(struct rte_devargs *devargs)
 882 {
 883         struct rte_kvargs *kvlist;
 884         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 885
 886         if (devargs == NULL)
 887                 return 0;
 888
 889         kvlist = rte_kvargs_parse(devargs->args, NULL);
 890         if (kvlist == NULL)
 891                 return 0;
 892
 893         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 894                 rte_kvargs_free(kvlist);
 895                 return 0;
 896         }
 897         /* Floating VEB is enabled when there's key-value:
 898          * enable_floating_veb=1
 899          */
 900         if (rte_kvargs_process(kvlist, floating_veb_key,
 901                                i40e_check_floating_handler, NULL) < 0) {
 902                 rte_kvargs_free(kvlist);
 903                 return 0;
 904         }
 905         rte_kvargs_free(kvlist);
 906
 907         return 1;
 908 }
 909
 910 static void
 911 config_floating_veb(struct rte_eth_dev *dev)
 912 {
 913         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916
 917         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 918
 919         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 920                 pf->floating_veb =
 921                         is_floating_veb_supported(pci_dev->device.devargs);
 922                 config_vf_floating_veb(pci_dev->device.devargs,
 923                                        pf->floating_veb,
 924                                        pf->floating_veb_list);
 925         } else {
 926                 pf->floating_veb = false;
 927         }
 928 }
 929
 930 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 931 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 932
 933 static int
 934 eth_i40e_dev_init(struct rte_eth_dev *dev)
 935 {
 936         struct rte_pci_device *pci_dev;
 937         struct rte_intr_handle *intr_handle;
 938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 940         struct i40e_vsi *vsi;
 941         int ret;
 942         uint32_t len;
 943         uint8_t aq_fail = 0;
 944
 945         PMD_INIT_FUNC_TRACE();
 946
 947         dev->dev_ops = &i40e_eth_dev_ops;
 948         dev->rx_pkt_burst = i40e_recv_pkts;
 949         dev->tx_pkt_burst = i40e_xmit_pkts;
 950         dev->tx_pkt_prepare = i40e_prep_pkts;
 951
 952         /* for secondary processes, we don't initialise any further as primary
 953          * has already done this work. Only check we don't need a different
 954          * RX function */
 955         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 956                 i40e_set_rx_function(dev);
 957                 i40e_set_tx_function(dev);
 958                 return 0;
 959         }
 960         pci_dev = I40E_DEV_TO_PCI(dev);
 961         intr_handle = &pci_dev->intr_handle;
 962
 963         rte_eth_copy_pci_info(dev, pci_dev);
 964         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
 965
 966         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 967         pf->adapter->eth_dev = dev;
 968         pf->dev_data = dev->data;
 969
 970         hw->back = I40E_PF_TO_ADAPTER(pf);
 971         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 972         if (!hw->hw_addr) {
 973                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 974                              "as address is NULL");
 975                 return -ENODEV;
 976         }
 977
 978         hw->vendor_id = pci_dev->id.vendor_id;
 979         hw->device_id = pci_dev->id.device_id;
 980         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 981         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 982         hw->bus.device = pci_dev->addr.devid;
 983         hw->bus.func = pci_dev->addr.function;
 984         hw->adapter_stopped = 0;
 985
 986         /* Make sure all is clean before doing PF reset */
 987         i40e_clear_hw(hw);
 988
 989         /* Initialize the hardware */
 990         i40e_hw_init(dev);
 991
 992         /* Reset here to make sure all is clean for each PF */
 993         ret = i40e_pf_reset(hw);
 994         if (ret) {
 995                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 996                 return ret;
 997         }
 998
 999         /* Initialize the shared code (base driver) */
1000         ret = i40e_init_shared_code(hw);
1001         if (ret) {
1002                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1003                 return ret;
1004         }
1005
1006         /*
1007          * To work around the NVM issue, initialize registers
1008          * for flexible payload and packet type of QinQ by
1009          * software. It should be removed once issues are fixed
1010          * in NVM.
1011          */
1012         i40e_GLQF_reg_init(hw);
1013
1014         /* Initialize the input set for filters (hash and fd) to default value */
1015         i40e_filter_input_set_init(pf);
1016
1017         /* Initialize the parameters for adminq */
1018         i40e_init_adminq_parameter(hw);
1019         ret = i40e_init_adminq(hw);
1020         if (ret != I40E_SUCCESS) {
1021                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1022                 return -EIO;
1023         }
1024         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1025                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1026                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1027                      ((hw->nvm.version >> 12) & 0xf),
1028                      ((hw->nvm.version >> 4) & 0xff),
1029                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1030
1031         /* Need the special FW version to support floating VEB */
1032         config_floating_veb(dev);
1033         /* Clear PXE mode */
1034         i40e_clear_pxe_mode(hw);
1035         ret = i40e_dev_sync_phy_type(hw);
1036         if (ret) {
1037                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1038                 goto err_sync_phy_type;
1039         }
1040         /*
1041          * On X710, performance number is far from the expectation on recent
1042          * firmware versions. The fix for this issue may not be integrated in
1043          * the following firmware version. So the workaround in software driver
1044          * is needed. It needs to modify the initial values of 3 internal only
1045          * registers. Note that the workaround can be removed when it is fixed
1046          * in firmware in the future.
1047          */
1048         i40e_configure_registers(hw);
1049
1050         /* Get hw capabilities */
1051         ret = i40e_get_cap(hw);
1052         if (ret != I40E_SUCCESS) {
1053                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1054                 goto err_get_capabilities;
1055         }
1056
1057         /* Initialize parameters for PF */
1058         ret = i40e_pf_parameter_init(dev);
1059         if (ret != 0) {
1060                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1061                 goto err_parameter_init;
1062         }
1063
1064         /* Initialize the queue management */
1065         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1066         if (ret < 0) {
1067                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1068                 goto err_qp_pool_init;
1069         }
1070         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1071                                 hw->func_caps.num_msix_vectors - 1);
1072         if (ret < 0) {
1073                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1074                 goto err_msix_pool_init;
1075         }
1076
1077         /* Initialize lan hmc */
1078         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1079                                 hw->func_caps.num_rx_qp, 0, 0);
1080         if (ret != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1082                 goto err_init_lan_hmc;
1083         }
1084
1085         /* Configure lan hmc */
1086         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1087         if (ret != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1089                 goto err_configure_lan_hmc;
1090         }
1091
1092         /* Get and check the mac address */
1093         i40e_get_mac_addr(hw, hw->mac.addr);
1094         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1095                 PMD_INIT_LOG(ERR, "mac address is not valid");
1096                 ret = -EIO;
1097                 goto err_get_mac_addr;
1098         }
1099         /* Copy the permanent MAC address */
1100         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1101                         (struct ether_addr *) hw->mac.perm_addr);
1102
1103         /* Disable flow control */
1104         hw->fc.requested_mode = I40E_FC_NONE;
1105         i40e_set_fc(hw, &aq_fail, TRUE);
1106
1107         /* Set the global registers with default ether type value */
1108         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1109         if (ret != I40E_SUCCESS) {
1110                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1111                              "VLAN ether type");
1112                 goto err_setup_pf_switch;
1113         }
1114
1115         /* PF setup, which includes VSI setup */
1116         ret = i40e_pf_setup(pf);
1117         if (ret) {
1118                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1119                 goto err_setup_pf_switch;
1120         }
1121
1122         /* reset all stats of the device, including pf and main vsi */
1123         i40e_dev_stats_reset(dev);
1124
1125         vsi = pf->main_vsi;
1126
1127         /* Disable double vlan by default */
1128         i40e_vsi_config_double_vlan(vsi, FALSE);
1129
1130         /* Disable S-TAG identification when floating_veb is disabled */
1131         if (!pf->floating_veb) {
1132                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1133                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1134                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1135                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1136                 }
1137         }
1138
1139         if (!vsi->max_macaddrs)
1140                 len = ETHER_ADDR_LEN;
1141         else
1142                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1143
1144         /* Should be after VSI initialized */
1145         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1146         if (!dev->data->mac_addrs) {
1147                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1148                                         "for storing mac address");
1149                 goto err_mac_alloc;
1150         }
1151         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1152                                         &dev->data->mac_addrs[0]);
1153
1154         /* initialize pf host driver to setup SRIOV resource if applicable */
1155         i40e_pf_host_init(dev);
1156
1157         /* register callback func to eal lib */
1158         rte_intr_callback_register(intr_handle,
1159                                    i40e_dev_interrupt_handler, dev);
1160
1161         /* configure and enable device interrupt */
1162         i40e_pf_config_irq0(hw, TRUE);
1163         i40e_pf_enable_irq0(hw);
1164
1165         /* enable uio intr after callback register */
1166         rte_intr_enable(intr_handle);
1167         /*
1168          * Add an ethertype filter to drop all flow control frames transmitted
1169          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1170          * frames to wire.
1171          */
1172         i40e_add_tx_flow_control_drop_filter(pf);
1173
1174         /* Set the max frame size to 0x2600 by default,
1175          * in case other drivers changed the default value.
1176          */
1177         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1178
1179         /* initialize mirror rule list */
1180         TAILQ_INIT(&pf->mirror_list);
1181
1182         /* Init dcb to sw mode by default */
1183         ret = i40e_dcb_init_configure(dev, TRUE);
1184         if (ret != I40E_SUCCESS) {
1185                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1186                 pf->flags &= ~I40E_FLAG_DCB;
1187         }
1188
1189         return 0;
1190
1191 err_mac_alloc:
1192         i40e_vsi_release(pf->main_vsi);
1193 err_setup_pf_switch:
1194 err_get_mac_addr:
1195 err_configure_lan_hmc:
1196         (void)i40e_shutdown_lan_hmc(hw);
1197 err_init_lan_hmc:
1198         i40e_res_pool_destroy(&pf->msix_pool);
1199 err_msix_pool_init:
1200         i40e_res_pool_destroy(&pf->qp_pool);
1201 err_qp_pool_init:
1202 err_parameter_init:
1203 err_get_capabilities:
1204 err_sync_phy_type:
1205         (void)i40e_shutdown_adminq(hw);
1206
1207         return ret;
1208 }
1209
1210 static int
1211 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1212 {
1213         struct rte_pci_device *pci_dev;
1214         struct rte_intr_handle *intr_handle;
1215         struct i40e_hw *hw;
1216         struct i40e_filter_control_settings settings;
1217         int ret;
1218         uint8_t aq_fail = 0;
1219
1220         PMD_INIT_FUNC_TRACE();
1221
1222         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1223                 return 0;
1224
1225         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226         pci_dev = I40E_DEV_TO_PCI(dev);
1227         intr_handle = &pci_dev->intr_handle;
1228
1229         if (hw->adapter_stopped == 0)
1230                 i40e_dev_close(dev);
1231
1232         dev->dev_ops = NULL;
1233         dev->rx_pkt_burst = NULL;
1234         dev->tx_pkt_burst = NULL;
1235
1236         /* Clear PXE mode */
1237         i40e_clear_pxe_mode(hw);
1238
1239         /* Unconfigure filter control */
1240         memset(&settings, 0, sizeof(settings));
1241         ret = i40e_set_filter_control(hw, &settings);
1242         if (ret)
1243                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1244                                         ret);
1245
1246         /* Disable flow control */
1247         hw->fc.requested_mode = I40E_FC_NONE;
1248         i40e_set_fc(hw, &aq_fail, TRUE);
1249
1250         /* uninitialize pf host driver */
1251         i40e_pf_host_uninit(dev);
1252
1253         rte_free(dev->data->mac_addrs);
1254         dev->data->mac_addrs = NULL;
1255
1256         /* disable uio intr before callback unregister */
1257         rte_intr_disable(intr_handle);
1258
1259         /* register callback func to eal lib */
1260         rte_intr_callback_unregister(intr_handle,
1261                                      i40e_dev_interrupt_handler, dev);
1262
1263         return 0;
1264 }
1265
1266 static int
1267 i40e_dev_configure(struct rte_eth_dev *dev)
1268 {
1269         struct i40e_adapter *ad =
1270                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1272         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1273         int i, ret;
1274
1275         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1276          * bulk allocation or vector Rx preconditions we will reset it.
1277          */
1278         ad->rx_bulk_alloc_allowed = true;
1279         ad->rx_vec_allowed = true;
1280         ad->tx_simple_allowed = true;
1281         ad->tx_vec_allowed = true;
1282
1283         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1284                 ret = i40e_fdir_setup(pf);
1285                 if (ret != I40E_SUCCESS) {
1286                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1287                         return -ENOTSUP;
1288                 }
1289                 ret = i40e_fdir_configure(dev);
1290                 if (ret < 0) {
1291                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1292                         goto err;
1293                 }
1294         } else
1295                 i40e_fdir_teardown(pf);
1296
1297         ret = i40e_dev_init_vlan(dev);
1298         if (ret < 0)
1299                 goto err;
1300
1301         /* VMDQ setup.
1302          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1303          *  RSS setting have different requirements.
1304          *  General PMD driver call sequence are NIC init, configure,
1305          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1306          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1307          *  applicable. So, VMDQ setting has to be done before
1308          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1309          *  For RSS setting, it will try to calculate actual configured RX queue
1310          *  number, which will be available after rx_queue_setup(). dev_start()
1311          *  function is good to place RSS setup.
1312          */
1313         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1314                 ret = i40e_vmdq_setup(dev);
1315                 if (ret)
1316                         goto err;
1317         }
1318
1319         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1320                 ret = i40e_dcb_setup(dev);
1321                 if (ret) {
1322                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1323                         goto err_dcb;
1324                 }
1325         }
1326
1327         return 0;
1328
1329 err_dcb:
1330         /* need to release vmdq resource if exists */
1331         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1332                 i40e_vsi_release(pf->vmdq[i].vsi);
1333                 pf->vmdq[i].vsi = NULL;
1334         }
1335         rte_free(pf->vmdq);
1336         pf->vmdq = NULL;
1337 err:
1338         /* need to release fdir resource if exists */
1339         i40e_fdir_teardown(pf);
1340         return ret;
1341 }
1342
1343 void
1344 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1345 {
1346         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1347         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1348         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1349         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1350         uint16_t msix_vect = vsi->msix_intr;
1351         uint16_t i;
1352
1353         for (i = 0; i < vsi->nb_qps; i++) {
1354                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1355                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1356                 rte_wmb();
1357         }
1358
1359         if (vsi->type != I40E_VSI_SRIOV) {
1360                 if (!rte_intr_allow_others(intr_handle)) {
1361                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1362                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1363                         I40E_WRITE_REG(hw,
1364                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1365                                        0);
1366                 } else {
1367                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1368                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1369                         I40E_WRITE_REG(hw,
1370                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1371                                                        msix_vect - 1), 0);
1372                 }
1373         } else {
1374                 uint32_t reg;
1375                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1376                         vsi->user_param + (msix_vect - 1);
1377
1378                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1379                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1380         }
1381         I40E_WRITE_FLUSH(hw);
1382 }
1383
1384 static void
1385 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1386                        int base_queue, int nb_queue)
1387 {
1388         int i;
1389         uint32_t val;
1390         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1391
1392         /* Bind all RX queues to allocated MSIX interrupt */
1393         for (i = 0; i < nb_queue; i++) {
1394                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1395                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1396                         ((base_queue + i + 1) <<
1397                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1398                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1399                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1400
1401                 if (i == nb_queue - 1)
1402                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1403                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1404         }
1405
1406         /* Write first RX queue to Link list register as the head element */
1407         if (vsi->type != I40E_VSI_SRIOV) {
1408                 uint16_t interval =
1409                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1410
1411                 if (msix_vect == I40E_MISC_VEC_ID) {
1412                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1413                                        (base_queue <<
1414                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1417                         I40E_WRITE_REG(hw,
1418                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1419                                        interval);
1420                 } else {
1421                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1422                                        (base_queue <<
1423                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1424                                        (0x0 <<
1425                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1426                         I40E_WRITE_REG(hw,
1427                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1428                                                        msix_vect - 1),
1429                                        interval);
1430                 }
1431         } else {
1432                 uint32_t reg;
1433
1434                 if (msix_vect == I40E_MISC_VEC_ID) {
1435                         I40E_WRITE_REG(hw,
1436                                        I40E_VPINT_LNKLST0(vsi->user_param),
1437                                        (base_queue <<
1438                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1439                                        (0x0 <<
1440                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1441                 } else {
1442                         /* num_msix_vectors_vf needs to minus irq0 */
1443                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1444                                 vsi->user_param + (msix_vect - 1);
1445
1446                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1447                                        (base_queue <<
1448                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1449                                        (0x0 <<
1450                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1451                 }
1452         }
1453
1454         I40E_WRITE_FLUSH(hw);
1455 }
1456
1457 void
1458 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1459 {
1460         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1461         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1462         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1463         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1464         uint16_t msix_vect = vsi->msix_intr;
1465         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1466         uint16_t queue_idx = 0;
1467         int record = 0;
1468         uint32_t val;
1469         int i;
1470
1471         for (i = 0; i < vsi->nb_qps; i++) {
1472                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1473                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1474         }
1475
1476         /* INTENA flag is not auto-cleared for interrupt */
1477         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1478         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1479                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1480                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1481         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1482
1483         /* VF bind interrupt */
1484         if (vsi->type == I40E_VSI_SRIOV) {
1485                 __vsi_queues_bind_intr(vsi, msix_vect,
1486                                        vsi->base_queue, vsi->nb_qps);
1487                 return;
1488         }
1489
1490         /* PF & VMDq bind interrupt */
1491         if (rte_intr_dp_is_en(intr_handle)) {
1492                 if (vsi->type == I40E_VSI_MAIN) {
1493                         queue_idx = 0;
1494                         record = 1;
1495                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1496                         struct i40e_vsi *main_vsi =
1497                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1498                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1499                         record = 1;
1500                 }
1501         }
1502
1503         for (i = 0; i < vsi->nb_used_qps; i++) {
1504                 if (nb_msix <= 1) {
1505                         if (!rte_intr_allow_others(intr_handle))
1506                                 /* allow to share MISC_VEC_ID */
1507                                 msix_vect = I40E_MISC_VEC_ID;
1508
1509                         /* no enough msix_vect, map all to one */
1510                         __vsi_queues_bind_intr(vsi, msix_vect,
1511                                                vsi->base_queue + i,
1512                                                vsi->nb_used_qps - i);
1513                         for (; !!record && i < vsi->nb_used_qps; i++)
1514                                 intr_handle->intr_vec[queue_idx + i] =
1515                                         msix_vect;
1516                         break;
1517                 }
1518                 /* 1:1 queue/msix_vect mapping */
1519                 __vsi_queues_bind_intr(vsi, msix_vect,
1520                                        vsi->base_queue + i, 1);
1521                 if (!!record)
1522                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1523
1524                 msix_vect++;
1525                 nb_msix--;
1526         }
1527 }
1528
1529 static void
1530 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1531 {
1532         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1533         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1536         uint16_t interval = i40e_calc_itr_interval(\
1537                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1538         uint16_t msix_intr, i;
1539
1540         if (rte_intr_allow_others(intr_handle))
1541                 for (i = 0; i < vsi->nb_msix; i++) {
1542                         msix_intr = vsi->msix_intr + i;
1543                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1544                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1545                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1546                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1547                                 (interval <<
1548                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1549                 }
1550         else
1551                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1552                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1553                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1554                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1555                                (interval <<
1556                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1557
1558         I40E_WRITE_FLUSH(hw);
1559 }
1560
1561 static void
1562 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1563 {
1564         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1565         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1566         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1567         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1568         uint16_t msix_intr, i;
1569
1570         if (rte_intr_allow_others(intr_handle))
1571                 for (i = 0; i < vsi->nb_msix; i++) {
1572                         msix_intr = vsi->msix_intr + i;
1573                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1574                                        0);
1575                 }
1576         else
1577                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1578
1579         I40E_WRITE_FLUSH(hw);
1580 }
1581
1582 static inline uint8_t
1583 i40e_parse_link_speeds(uint16_t link_speeds)
1584 {
1585         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1586
1587         if (link_speeds & ETH_LINK_SPEED_40G)
1588                 link_speed |= I40E_LINK_SPEED_40GB;
1589         if (link_speeds & ETH_LINK_SPEED_25G)
1590                 link_speed |= I40E_LINK_SPEED_25GB;
1591         if (link_speeds & ETH_LINK_SPEED_20G)
1592                 link_speed |= I40E_LINK_SPEED_20GB;
1593         if (link_speeds & ETH_LINK_SPEED_10G)
1594                 link_speed |= I40E_LINK_SPEED_10GB;
1595         if (link_speeds & ETH_LINK_SPEED_1G)
1596                 link_speed |= I40E_LINK_SPEED_1GB;
1597         if (link_speeds & ETH_LINK_SPEED_100M)
1598                 link_speed |= I40E_LINK_SPEED_100MB;
1599
1600         return link_speed;
1601 }
1602
1603 static int
1604 i40e_phy_conf_link(struct i40e_hw *hw,
1605                    uint8_t abilities,
1606                    uint8_t force_speed)
1607 {
1608         enum i40e_status_code status;
1609         struct i40e_aq_get_phy_abilities_resp phy_ab;
1610         struct i40e_aq_set_phy_config phy_conf;
1611         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1612                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1613                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1614                         I40E_AQ_PHY_FLAG_LOW_POWER;
1615         const uint8_t advt = I40E_LINK_SPEED_40GB |
1616                         I40E_LINK_SPEED_25GB |
1617                         I40E_LINK_SPEED_10GB |
1618                         I40E_LINK_SPEED_1GB |
1619                         I40E_LINK_SPEED_100MB;
1620         int ret = -ENOTSUP;
1621
1622
1623         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1624                                               NULL);
1625         if (status)
1626                 return ret;
1627
1628         memset(&phy_conf, 0, sizeof(phy_conf));
1629
1630         /* bits 0-2 use the values from get_phy_abilities_resp */
1631         abilities &= ~mask;
1632         abilities |= phy_ab.abilities & mask;
1633
1634         /* update ablities and speed */
1635         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1636                 phy_conf.link_speed = advt;
1637         else
1638                 phy_conf.link_speed = force_speed;
1639
1640         phy_conf.abilities = abilities;
1641
1642         /* use get_phy_abilities_resp value for the rest */
1643         phy_conf.phy_type = phy_ab.phy_type;
1644         phy_conf.eee_capability = phy_ab.eee_capability;
1645         phy_conf.eeer = phy_ab.eeer_val;
1646         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1647
1648         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1649                     phy_ab.abilities, phy_ab.link_speed);
1650         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1651                     phy_conf.abilities, phy_conf.link_speed);
1652
1653         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1654         if (status)
1655                 return ret;
1656
1657         return I40E_SUCCESS;
1658 }
1659
1660 static int
1661 i40e_apply_link_speed(struct rte_eth_dev *dev)
1662 {
1663         uint8_t speed;
1664         uint8_t abilities = 0;
1665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666         struct rte_eth_conf *conf = &dev->data->dev_conf;
1667
1668         speed = i40e_parse_link_speeds(conf->link_speeds);
1669         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1670                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1671         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1672                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1673         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1674
1675         /* Skip changing speed on 40G interfaces, FW does not support */
1676         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1677                 speed =  I40E_LINK_SPEED_UNKNOWN;
1678                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1679         }
1680
1681         return i40e_phy_conf_link(hw, abilities, speed);
1682 }
1683
1684 static int
1685 i40e_dev_start(struct rte_eth_dev *dev)
1686 {
1687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         struct i40e_vsi *main_vsi = pf->main_vsi;
1690         int ret, i;
1691         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1693         uint32_t intr_vector = 0;
1694
1695         hw->adapter_stopped = 0;
1696
1697         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1698                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1699                              dev->data->port_id);
1700                 return -EINVAL;
1701         }
1702
1703         rte_intr_disable(intr_handle);
1704
1705         if ((rte_intr_cap_multiple(intr_handle) ||
1706              !RTE_ETH_DEV_SRIOV(dev).active) &&
1707             dev->data->dev_conf.intr_conf.rxq != 0) {
1708                 intr_vector = dev->data->nb_rx_queues;
1709                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1710                         return -1;
1711         }
1712
1713         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1714                 intr_handle->intr_vec =
1715                         rte_zmalloc("intr_vec",
1716                                     dev->data->nb_rx_queues * sizeof(int),
1717                                     0);
1718                 if (!intr_handle->intr_vec) {
1719                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1720                                      " intr_vec\n", dev->data->nb_rx_queues);
1721                         return -ENOMEM;
1722                 }
1723         }
1724
1725         /* Initialize VSI */
1726         ret = i40e_dev_rxtx_init(pf);
1727         if (ret != I40E_SUCCESS) {
1728                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1729                 goto err_up;
1730         }
1731
1732         /* Map queues with MSIX interrupt */
1733         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1734                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1735         i40e_vsi_queues_bind_intr(main_vsi);
1736         i40e_vsi_enable_queues_intr(main_vsi);
1737
1738         /* Map VMDQ VSI queues with MSIX interrupt */
1739         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1740                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1741                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1742                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1743         }
1744
1745         /* enable FDIR MSIX interrupt */
1746         if (pf->fdir.fdir_vsi) {
1747                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1748                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1749         }
1750
1751         /* Enable all queues which have been configured */
1752         ret = i40e_dev_switch_queues(pf, TRUE);
1753         if (ret != I40E_SUCCESS) {
1754                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1755                 goto err_up;
1756         }
1757
1758         /* Enable receiving broadcast packets */
1759         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1760         if (ret != I40E_SUCCESS)
1761                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1762
1763         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1764                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1765                                                 true, NULL);
1766                 if (ret != I40E_SUCCESS)
1767                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1768         }
1769
1770         /* Apply link configure */
1771         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1772                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1773                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1774                                 ETH_LINK_SPEED_40G)) {
1775                 PMD_DRV_LOG(ERR, "Invalid link setting");
1776                 goto err_up;
1777         }
1778         ret = i40e_apply_link_speed(dev);
1779         if (I40E_SUCCESS != ret) {
1780                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1781                 goto err_up;
1782         }
1783
1784         if (!rte_intr_allow_others(intr_handle)) {
1785                 rte_intr_callback_unregister(intr_handle,
1786                                              i40e_dev_interrupt_handler,
1787                                              (void *)dev);
1788                 /* configure and enable device interrupt */
1789                 i40e_pf_config_irq0(hw, FALSE);
1790                 i40e_pf_enable_irq0(hw);
1791
1792                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1793                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1794                                      " no intr multiplex\n");
1795         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1796                 ret = i40e_aq_set_phy_int_mask(hw,
1797                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1798                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1799                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1800                 if (ret != I40E_SUCCESS)
1801                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1802
1803                 /* Call get_link_info aq commond to enable LSE */
1804                 i40e_dev_link_update(dev, 0);
1805         }
1806
1807         /* enable uio intr after callback register */
1808         rte_intr_enable(intr_handle);
1809
1810         return I40E_SUCCESS;
1811
1812 err_up:
1813         i40e_dev_switch_queues(pf, FALSE);
1814         i40e_dev_clear_queues(dev);
1815
1816         return ret;
1817 }
1818
1819 static void
1820 i40e_dev_stop(struct rte_eth_dev *dev)
1821 {
1822         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1823         struct i40e_vsi *main_vsi = pf->main_vsi;
1824         struct i40e_mirror_rule *p_mirror;
1825         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1826         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1827         int i;
1828
1829         /* Disable all queues */
1830         i40e_dev_switch_queues(pf, FALSE);
1831
1832         /* un-map queues with interrupt registers */
1833         i40e_vsi_disable_queues_intr(main_vsi);
1834         i40e_vsi_queues_unbind_intr(main_vsi);
1835
1836         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1837                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1838                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1839         }
1840
1841         if (pf->fdir.fdir_vsi) {
1842                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1843                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1844         }
1845         /* Clear all queues and release memory */
1846         i40e_dev_clear_queues(dev);
1847
1848         /* Set link down */
1849         i40e_dev_set_link_down(dev);
1850
1851         /* Remove all mirror rules */
1852         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1853                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1854                 rte_free(p_mirror);
1855         }
1856         pf->nb_mirror_rule = 0;
1857
1858         if (!rte_intr_allow_others(intr_handle))
1859                 /* resume to the default handler */
1860                 rte_intr_callback_register(intr_handle,
1861                                            i40e_dev_interrupt_handler,
1862                                            (void *)dev);
1863
1864         /* Clean datapath event and queue/vec mapping */
1865         rte_intr_efd_disable(intr_handle);
1866         if (intr_handle->intr_vec) {
1867                 rte_free(intr_handle->intr_vec);
1868                 intr_handle->intr_vec = NULL;
1869         }
1870 }
1871
1872 static void
1873 i40e_dev_close(struct rte_eth_dev *dev)
1874 {
1875         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1876         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1878         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1879         uint32_t reg;
1880         int i;
1881
1882         PMD_INIT_FUNC_TRACE();
1883
1884         i40e_dev_stop(dev);
1885         hw->adapter_stopped = 1;
1886         i40e_dev_free_queues(dev);
1887
1888         /* Disable interrupt */
1889         i40e_pf_disable_irq0(hw);
1890         rte_intr_disable(intr_handle);
1891
1892         /* shutdown and destroy the HMC */
1893         i40e_shutdown_lan_hmc(hw);
1894
1895         /* release all the existing VSIs and VEBs */
1896         i40e_fdir_teardown(pf);
1897         i40e_vsi_release(pf->main_vsi);
1898
1899         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1900                 i40e_vsi_release(pf->vmdq[i].vsi);
1901                 pf->vmdq[i].vsi = NULL;
1902         }
1903
1904         rte_free(pf->vmdq);
1905         pf->vmdq = NULL;
1906
1907         /* shutdown the adminq */
1908         i40e_aq_queue_shutdown(hw, true);
1909         i40e_shutdown_adminq(hw);
1910
1911         i40e_res_pool_destroy(&pf->qp_pool);
1912         i40e_res_pool_destroy(&pf->msix_pool);
1913
1914         /* force a PF reset to clean anything leftover */
1915         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1916         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1917                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1918         I40E_WRITE_FLUSH(hw);
1919 }
1920
1921 static void
1922 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1923 {
1924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct i40e_vsi *vsi = pf->main_vsi;
1927         int status;
1928
1929         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1930                                                      true, NULL, true);
1931         if (status != I40E_SUCCESS)
1932                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1933
1934         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1935                                                         TRUE, NULL);
1936         if (status != I40E_SUCCESS)
1937                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1938
1939 }
1940
1941 static void
1942 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1943 {
1944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         struct i40e_vsi *vsi = pf->main_vsi;
1947         int status;
1948
1949         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1950                                                      false, NULL, true);
1951         if (status != I40E_SUCCESS)
1952                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1953
1954         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1955                                                         false, NULL);
1956         if (status != I40E_SUCCESS)
1957                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1958 }
1959
1960 static void
1961 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1962 {
1963         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct i40e_vsi *vsi = pf->main_vsi;
1966         int ret;
1967
1968         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1969         if (ret != I40E_SUCCESS)
1970                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1971 }
1972
1973 static void
1974 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1975 {
1976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         struct i40e_vsi *vsi = pf->main_vsi;
1979         int ret;
1980
1981         if (dev->data->promiscuous == 1)
1982                 return; /* must remain in all_multicast mode */
1983
1984         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1985                                 vsi->seid, FALSE, NULL);
1986         if (ret != I40E_SUCCESS)
1987                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1988 }
1989
1990 /*
1991  * Set device link up.
1992  */
1993 static int
1994 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1995 {
1996         /* re-apply link speed setting */
1997         return i40e_apply_link_speed(dev);
1998 }
1999
2000 /*
2001  * Set device link down.
2002  */
2003 static int
2004 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2005 {
2006         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2007         uint8_t abilities = 0;
2008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009
2010         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2011                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2012         return i40e_phy_conf_link(hw, abilities, speed);
2013 }
2014
2015 int
2016 i40e_dev_link_update(struct rte_eth_dev *dev,
2017                      int wait_to_complete)
2018 {
2019 #define CHECK_INTERVAL 100  /* 100ms */
2020 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         struct i40e_link_status link_status;
2023         struct rte_eth_link link, old;
2024         int status;
2025         unsigned rep_cnt = MAX_REPEAT_TIME;
2026         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2027
2028         memset(&link, 0, sizeof(link));
2029         memset(&old, 0, sizeof(old));
2030         memset(&link_status, 0, sizeof(link_status));
2031         rte_i40e_dev_atomic_read_link_status(dev, &old);
2032
2033         do {
2034                 /* Get link status information from hardware */
2035                 status = i40e_aq_get_link_info(hw, enable_lse,
2036                                                 &link_status, NULL);
2037                 if (status != I40E_SUCCESS) {
2038                         link.link_speed = ETH_SPEED_NUM_100M;
2039                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2040                         PMD_DRV_LOG(ERR, "Failed to get link info");
2041                         goto out;
2042                 }
2043
2044                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2045                 if (!wait_to_complete)
2046                         break;
2047
2048                 rte_delay_ms(CHECK_INTERVAL);
2049         } while (!link.link_status && rep_cnt--);
2050
2051         if (!link.link_status)
2052                 goto out;
2053
2054         /* i40e uses full duplex only */
2055         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2056
2057         /* Parse the link status */
2058         switch (link_status.link_speed) {
2059         case I40E_LINK_SPEED_100MB:
2060                 link.link_speed = ETH_SPEED_NUM_100M;
2061                 break;
2062         case I40E_LINK_SPEED_1GB:
2063                 link.link_speed = ETH_SPEED_NUM_1G;
2064                 break;
2065         case I40E_LINK_SPEED_10GB:
2066                 link.link_speed = ETH_SPEED_NUM_10G;
2067                 break;
2068         case I40E_LINK_SPEED_20GB:
2069                 link.link_speed = ETH_SPEED_NUM_20G;
2070                 break;
2071         case I40E_LINK_SPEED_25GB:
2072                 link.link_speed = ETH_SPEED_NUM_25G;
2073                 break;
2074         case I40E_LINK_SPEED_40GB:
2075                 link.link_speed = ETH_SPEED_NUM_40G;
2076                 break;
2077         default:
2078                 link.link_speed = ETH_SPEED_NUM_100M;
2079                 break;
2080         }
2081
2082         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2083                         ETH_LINK_SPEED_FIXED);
2084
2085 out:
2086         rte_i40e_dev_atomic_write_link_status(dev, &link);
2087         if (link.link_status == old.link_status)
2088                 return -1;
2089
2090         return 0;
2091 }
2092
2093 /* Get all the statistics of a VSI */
2094 void
2095 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2096 {
2097         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2098         struct i40e_eth_stats *nes = &vsi->eth_stats;
2099         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2100         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2101
2102         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2103                             vsi->offset_loaded, &oes->rx_bytes,
2104                             &nes->rx_bytes);
2105         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2106                             vsi->offset_loaded, &oes->rx_unicast,
2107                             &nes->rx_unicast);
2108         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2109                             vsi->offset_loaded, &oes->rx_multicast,
2110                             &nes->rx_multicast);
2111         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2112                             vsi->offset_loaded, &oes->rx_broadcast,
2113                             &nes->rx_broadcast);
2114         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2115                             &oes->rx_discards, &nes->rx_discards);
2116         /* GLV_REPC not supported */
2117         /* GLV_RMPC not supported */
2118         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2119                             &oes->rx_unknown_protocol,
2120                             &nes->rx_unknown_protocol);
2121         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2122                             vsi->offset_loaded, &oes->tx_bytes,
2123                             &nes->tx_bytes);
2124         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2125                             vsi->offset_loaded, &oes->tx_unicast,
2126                             &nes->tx_unicast);
2127         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2128                             vsi->offset_loaded, &oes->tx_multicast,
2129                             &nes->tx_multicast);
2130         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2131                             vsi->offset_loaded,  &oes->tx_broadcast,
2132                             &nes->tx_broadcast);
2133         /* GLV_TDPC not supported */
2134         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2135                             &oes->tx_errors, &nes->tx_errors);
2136         vsi->offset_loaded = true;
2137
2138         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2139                     vsi->vsi_id);
2140         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2141         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2142         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2143         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2144         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2145         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2146                     nes->rx_unknown_protocol);
2147         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2148         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2149         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2150         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2151         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2152         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2153         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2154                     vsi->vsi_id);
2155 }
2156
2157 static void
2158 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2159 {
2160         unsigned int i;
2161         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2162         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2163
2164         /* Get statistics of struct i40e_eth_stats */
2165         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2166                             I40E_GLPRT_GORCL(hw->port),
2167                             pf->offset_loaded, &os->eth.rx_bytes,
2168                             &ns->eth.rx_bytes);
2169         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2170                             I40E_GLPRT_UPRCL(hw->port),
2171                             pf->offset_loaded, &os->eth.rx_unicast,
2172                             &ns->eth.rx_unicast);
2173         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2174                             I40E_GLPRT_MPRCL(hw->port),
2175                             pf->offset_loaded, &os->eth.rx_multicast,
2176                             &ns->eth.rx_multicast);
2177         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2178                             I40E_GLPRT_BPRCL(hw->port),
2179                             pf->offset_loaded, &os->eth.rx_broadcast,
2180                             &ns->eth.rx_broadcast);
2181         /* Workaround: CRC size should not be included in byte statistics,
2182          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2183          */
2184         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2185                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2186
2187         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2188                             pf->offset_loaded, &os->eth.rx_discards,
2189                             &ns->eth.rx_discards);
2190         /* GLPRT_REPC not supported */
2191         /* GLPRT_RMPC not supported */
2192         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2193                             pf->offset_loaded,
2194                             &os->eth.rx_unknown_protocol,
2195                             &ns->eth.rx_unknown_protocol);
2196         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2197                             I40E_GLPRT_GOTCL(hw->port),
2198                             pf->offset_loaded, &os->eth.tx_bytes,
2199                             &ns->eth.tx_bytes);
2200         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2201                             I40E_GLPRT_UPTCL(hw->port),
2202                             pf->offset_loaded, &os->eth.tx_unicast,
2203                             &ns->eth.tx_unicast);
2204         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2205                             I40E_GLPRT_MPTCL(hw->port),
2206                             pf->offset_loaded, &os->eth.tx_multicast,
2207                             &ns->eth.tx_multicast);
2208         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2209                             I40E_GLPRT_BPTCL(hw->port),
2210                             pf->offset_loaded, &os->eth.tx_broadcast,
2211                             &ns->eth.tx_broadcast);
2212         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2213                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2214         /* GLPRT_TEPC not supported */
2215
2216         /* additional port specific stats */
2217         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2218                             pf->offset_loaded, &os->tx_dropped_link_down,
2219                             &ns->tx_dropped_link_down);
2220         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2221                             pf->offset_loaded, &os->crc_errors,
2222                             &ns->crc_errors);
2223         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2224                             pf->offset_loaded, &os->illegal_bytes,
2225                             &ns->illegal_bytes);
2226         /* GLPRT_ERRBC not supported */
2227         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2228                             pf->offset_loaded, &os->mac_local_faults,
2229                             &ns->mac_local_faults);
2230         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2231                             pf->offset_loaded, &os->mac_remote_faults,
2232                             &ns->mac_remote_faults);
2233         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2234                             pf->offset_loaded, &os->rx_length_errors,
2235                             &ns->rx_length_errors);
2236         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2237                             pf->offset_loaded, &os->link_xon_rx,
2238                             &ns->link_xon_rx);
2239         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2240                             pf->offset_loaded, &os->link_xoff_rx,
2241                             &ns->link_xoff_rx);
2242         for (i = 0; i < 8; i++) {
2243                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2244                                     pf->offset_loaded,
2245                                     &os->priority_xon_rx[i],
2246                                     &ns->priority_xon_rx[i]);
2247                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2248                                     pf->offset_loaded,
2249                                     &os->priority_xoff_rx[i],
2250                                     &ns->priority_xoff_rx[i]);
2251         }
2252         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2253                             pf->offset_loaded, &os->link_xon_tx,
2254                             &ns->link_xon_tx);
2255         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2256                             pf->offset_loaded, &os->link_xoff_tx,
2257                             &ns->link_xoff_tx);
2258         for (i = 0; i < 8; i++) {
2259                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2260                                     pf->offset_loaded,
2261                                     &os->priority_xon_tx[i],
2262                                     &ns->priority_xon_tx[i]);
2263                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2264                                     pf->offset_loaded,
2265                                     &os->priority_xoff_tx[i],
2266                                     &ns->priority_xoff_tx[i]);
2267                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2268                                     pf->offset_loaded,
2269                                     &os->priority_xon_2_xoff[i],
2270                                     &ns->priority_xon_2_xoff[i]);
2271         }
2272         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2273                             I40E_GLPRT_PRC64L(hw->port),
2274                             pf->offset_loaded, &os->rx_size_64,
2275                             &ns->rx_size_64);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2277                             I40E_GLPRT_PRC127L(hw->port),
2278                             pf->offset_loaded, &os->rx_size_127,
2279                             &ns->rx_size_127);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2281                             I40E_GLPRT_PRC255L(hw->port),
2282                             pf->offset_loaded, &os->rx_size_255,
2283                             &ns->rx_size_255);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2285                             I40E_GLPRT_PRC511L(hw->port),
2286                             pf->offset_loaded, &os->rx_size_511,
2287                             &ns->rx_size_511);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2289                             I40E_GLPRT_PRC1023L(hw->port),
2290                             pf->offset_loaded, &os->rx_size_1023,
2291                             &ns->rx_size_1023);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2293                             I40E_GLPRT_PRC1522L(hw->port),
2294                             pf->offset_loaded, &os->rx_size_1522,
2295                             &ns->rx_size_1522);
2296         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2297                             I40E_GLPRT_PRC9522L(hw->port),
2298                             pf->offset_loaded, &os->rx_size_big,
2299                             &ns->rx_size_big);
2300         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2301                             pf->offset_loaded, &os->rx_undersize,
2302                             &ns->rx_undersize);
2303         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2304                             pf->offset_loaded, &os->rx_fragments,
2305                             &ns->rx_fragments);
2306         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2307                             pf->offset_loaded, &os->rx_oversize,
2308                             &ns->rx_oversize);
2309         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2310                             pf->offset_loaded, &os->rx_jabber,
2311                             &ns->rx_jabber);
2312         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2313                             I40E_GLPRT_PTC64L(hw->port),
2314                             pf->offset_loaded, &os->tx_size_64,
2315                             &ns->tx_size_64);
2316         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2317                             I40E_GLPRT_PTC127L(hw->port),
2318                             pf->offset_loaded, &os->tx_size_127,
2319                             &ns->tx_size_127);
2320         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2321                             I40E_GLPRT_PTC255L(hw->port),
2322                             pf->offset_loaded, &os->tx_size_255,
2323                             &ns->tx_size_255);
2324         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2325                             I40E_GLPRT_PTC511L(hw->port),
2326                             pf->offset_loaded, &os->tx_size_511,
2327                             &ns->tx_size_511);
2328         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2329                             I40E_GLPRT_PTC1023L(hw->port),
2330                             pf->offset_loaded, &os->tx_size_1023,
2331                             &ns->tx_size_1023);
2332         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2333                             I40E_GLPRT_PTC1522L(hw->port),
2334                             pf->offset_loaded, &os->tx_size_1522,
2335                             &ns->tx_size_1522);
2336         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2337                             I40E_GLPRT_PTC9522L(hw->port),
2338                             pf->offset_loaded, &os->tx_size_big,
2339                             &ns->tx_size_big);
2340         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2341                            pf->offset_loaded,
2342                            &os->fd_sb_match, &ns->fd_sb_match);
2343         /* GLPRT_MSPDC not supported */
2344         /* GLPRT_XEC not supported */
2345
2346         pf->offset_loaded = true;
2347
2348         if (pf->main_vsi)
2349                 i40e_update_vsi_stats(pf->main_vsi);
2350 }
2351
2352 /* Get all statistics of a port */
2353 static void
2354 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2355 {
2356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2359         unsigned i;
2360
2361         /* call read registers - updates values, now write them to struct */
2362         i40e_read_stats_registers(pf, hw);
2363
2364         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2365                         pf->main_vsi->eth_stats.rx_multicast +
2366                         pf->main_vsi->eth_stats.rx_broadcast -
2367                         pf->main_vsi->eth_stats.rx_discards;
2368         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2369                         pf->main_vsi->eth_stats.tx_multicast +
2370                         pf->main_vsi->eth_stats.tx_broadcast;
2371         stats->ibytes   = ns->eth.rx_bytes;
2372         stats->obytes   = ns->eth.tx_bytes;
2373         stats->oerrors  = ns->eth.tx_errors +
2374                         pf->main_vsi->eth_stats.tx_errors;
2375
2376         /* Rx Errors */
2377         stats->imissed  = ns->eth.rx_discards +
2378                         pf->main_vsi->eth_stats.rx_discards;
2379         stats->ierrors  = ns->crc_errors +
2380                         ns->rx_length_errors + ns->rx_undersize +
2381                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2382
2383         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2384         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2385         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2386         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2387         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2388         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2389         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2390                     ns->eth.rx_unknown_protocol);
2391         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2392         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2393         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2394         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2395         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2396         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2397
2398         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2399                     ns->tx_dropped_link_down);
2400         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2401         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2402                     ns->illegal_bytes);
2403         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2404         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2405                     ns->mac_local_faults);
2406         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2407                     ns->mac_remote_faults);
2408         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2409                     ns->rx_length_errors);
2410         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2411         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2412         for (i = 0; i < 8; i++) {
2413                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2414                                 i, ns->priority_xon_rx[i]);
2415                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2416                                 i, ns->priority_xoff_rx[i]);
2417         }
2418         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2419         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2420         for (i = 0; i < 8; i++) {
2421                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2422                                 i, ns->priority_xon_tx[i]);
2423                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2424                                 i, ns->priority_xoff_tx[i]);
2425                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2426                                 i, ns->priority_xon_2_xoff[i]);
2427         }
2428         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2429         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2430         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2431         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2432         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2433         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2434         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2435         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2436         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2437         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2438         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2439         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2440         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2441         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2442         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2443         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2444         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2445         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2446         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2447                         ns->mac_short_packet_dropped);
2448         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2449                     ns->checksum_error);
2450         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2451         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2452 }
2453
2454 /* Reset the statistics */
2455 static void
2456 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2457 {
2458         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460
2461         /* Mark PF and VSI stats to update the offset, aka "reset" */
2462         pf->offset_loaded = false;
2463         if (pf->main_vsi)
2464                 pf->main_vsi->offset_loaded = false;
2465
2466         /* read the stats, reading current register values into offset */
2467         i40e_read_stats_registers(pf, hw);
2468 }
2469
2470 static uint32_t
2471 i40e_xstats_calc_num(void)
2472 {
2473         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2474                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2475                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2476 }
2477
2478 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2479                                      struct rte_eth_xstat_name *xstats_names,
2480                                      __rte_unused unsigned limit)
2481 {
2482         unsigned count = 0;
2483         unsigned i, prio;
2484
2485         if (xstats_names == NULL)
2486                 return i40e_xstats_calc_num();
2487
2488         /* Note: limit checked in rte_eth_xstats_names() */
2489
2490         /* Get stats from i40e_eth_stats struct */
2491         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2492                 snprintf(xstats_names[count].name,
2493                          sizeof(xstats_names[count].name),
2494                          "%s", rte_i40e_stats_strings[i].name);
2495                 count++;
2496         }
2497
2498         /* Get individiual stats from i40e_hw_port struct */
2499         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2500                 snprintf(xstats_names[count].name,
2501                         sizeof(xstats_names[count].name),
2502                          "%s", rte_i40e_hw_port_strings[i].name);
2503                 count++;
2504         }
2505
2506         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2507                 for (prio = 0; prio < 8; prio++) {
2508                         snprintf(xstats_names[count].name,
2509                                  sizeof(xstats_names[count].name),
2510                                  "rx_priority%u_%s", prio,
2511                                  rte_i40e_rxq_prio_strings[i].name);
2512                         count++;
2513                 }
2514         }
2515
2516         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2517                 for (prio = 0; prio < 8; prio++) {
2518                         snprintf(xstats_names[count].name,
2519                                  sizeof(xstats_names[count].name),
2520                                  "tx_priority%u_%s", prio,
2521                                  rte_i40e_txq_prio_strings[i].name);
2522                         count++;
2523                 }
2524         }
2525         return count;
2526 }
2527
2528 static int
2529 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2530                     unsigned n)
2531 {
2532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2533         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         unsigned i, count, prio;
2535         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2536
2537         count = i40e_xstats_calc_num();
2538         if (n < count)
2539                 return count;
2540
2541         i40e_read_stats_registers(pf, hw);
2542
2543         if (xstats == NULL)
2544                 return 0;
2545
2546         count = 0;
2547
2548         /* Get stats from i40e_eth_stats struct */
2549         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2550                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2551                         rte_i40e_stats_strings[i].offset);
2552                 xstats[count].id = count;
2553                 count++;
2554         }
2555
2556         /* Get individiual stats from i40e_hw_port struct */
2557         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2558                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2559                         rte_i40e_hw_port_strings[i].offset);
2560                 xstats[count].id = count;
2561                 count++;
2562         }
2563
2564         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2565                 for (prio = 0; prio < 8; prio++) {
2566                         xstats[count].value =
2567                                 *(uint64_t *)(((char *)hw_stats) +
2568                                 rte_i40e_rxq_prio_strings[i].offset +
2569                                 (sizeof(uint64_t) * prio));
2570                         xstats[count].id = count;
2571                         count++;
2572                 }
2573         }
2574
2575         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2576                 for (prio = 0; prio < 8; prio++) {
2577                         xstats[count].value =
2578                                 *(uint64_t *)(((char *)hw_stats) +
2579                                 rte_i40e_txq_prio_strings[i].offset +
2580                                 (sizeof(uint64_t) * prio));
2581                         xstats[count].id = count;
2582                         count++;
2583                 }
2584         }
2585
2586         return count;
2587 }
2588
2589 static int
2590 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2591                                  __rte_unused uint16_t queue_id,
2592                                  __rte_unused uint8_t stat_idx,
2593                                  __rte_unused uint8_t is_rx)
2594 {
2595         PMD_INIT_FUNC_TRACE();
2596
2597         return -ENOSYS;
2598 }
2599
2600 static int
2601 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2602 {
2603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604         u32 full_ver;
2605         u8 ver, patch;
2606         u16 build;
2607         int ret;
2608
2609         full_ver = hw->nvm.oem_ver;
2610         ver = (u8)(full_ver >> 24);
2611         build = (u16)((full_ver >> 8) & 0xffff);
2612         patch = (u8)(full_ver & 0xff);
2613
2614         ret = snprintf(fw_version, fw_size,
2615                  "%d.%d%d 0x%08x %d.%d.%d",
2616                  ((hw->nvm.version >> 12) & 0xf),
2617                  ((hw->nvm.version >> 4) & 0xff),
2618                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2619                  ver, build, patch);
2620
2621         ret += 1; /* add the size of '\0' */
2622         if (fw_size < (u32)ret)
2623                 return ret;
2624         else
2625                 return 0;
2626 }
2627
2628 static void
2629 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2630 {
2631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633         struct i40e_vsi *vsi = pf->main_vsi;
2634         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2635
2636         dev_info->pci_dev = pci_dev;
2637         dev_info->max_rx_queues = vsi->nb_qps;
2638         dev_info->max_tx_queues = vsi->nb_qps;
2639         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2640         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2641         dev_info->max_mac_addrs = vsi->max_macaddrs;
2642         dev_info->max_vfs = pci_dev->max_vfs;
2643         dev_info->rx_offload_capa =
2644                 DEV_RX_OFFLOAD_VLAN_STRIP |
2645                 DEV_RX_OFFLOAD_QINQ_STRIP |
2646                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2647                 DEV_RX_OFFLOAD_UDP_CKSUM |
2648                 DEV_RX_OFFLOAD_TCP_CKSUM;
2649         dev_info->tx_offload_capa =
2650                 DEV_TX_OFFLOAD_VLAN_INSERT |
2651                 DEV_TX_OFFLOAD_QINQ_INSERT |
2652                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2653                 DEV_TX_OFFLOAD_UDP_CKSUM |
2654                 DEV_TX_OFFLOAD_TCP_CKSUM |
2655                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2656                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2657                 DEV_TX_OFFLOAD_TCP_TSO |
2658                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2659                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2660                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2661                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2662         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2663                                                 sizeof(uint32_t);
2664         dev_info->reta_size = pf->hash_lut_size;
2665         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2666
2667         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2668                 .rx_thresh = {
2669                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2670                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2671                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2672                 },
2673                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2674                 .rx_drop_en = 0,
2675         };
2676
2677         dev_info->default_txconf = (struct rte_eth_txconf) {
2678                 .tx_thresh = {
2679                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2680                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2681                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2682                 },
2683                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2684                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2685                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2686                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2687         };
2688
2689         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2690                 .nb_max = I40E_MAX_RING_DESC,
2691                 .nb_min = I40E_MIN_RING_DESC,
2692                 .nb_align = I40E_ALIGN_RING_DESC,
2693         };
2694
2695         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2696                 .nb_max = I40E_MAX_RING_DESC,
2697                 .nb_min = I40E_MIN_RING_DESC,
2698                 .nb_align = I40E_ALIGN_RING_DESC,
2699                 .nb_seg_max = I40E_TX_MAX_SEG,
2700                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2701         };
2702
2703         if (pf->flags & I40E_FLAG_VMDQ) {
2704                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2705                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2706                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2707                                                 pf->max_nb_vmdq_vsi;
2708                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2709                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2710                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2711         }
2712
2713         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2714                 /* For XL710 */
2715                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2716         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2717                 /* For XXV710 */
2718                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2719         else
2720                 /* For X710 */
2721                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2722 }
2723
2724 static int
2725 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2726 {
2727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2728         struct i40e_vsi *vsi = pf->main_vsi;
2729         PMD_INIT_FUNC_TRACE();
2730
2731         if (on)
2732                 return i40e_vsi_add_vlan(vsi, vlan_id);
2733         else
2734                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2735 }
2736
2737 static int
2738 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2739                    enum rte_vlan_type vlan_type,
2740                    uint16_t tpid)
2741 {
2742         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         uint64_t reg_r = 0, reg_w = 0;
2744         uint16_t reg_id = 0;
2745         int ret = 0;
2746         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2747
2748         switch (vlan_type) {
2749         case ETH_VLAN_TYPE_OUTER:
2750                 if (qinq)
2751                         reg_id = 2;
2752                 else
2753                         reg_id = 3;
2754                 break;
2755         case ETH_VLAN_TYPE_INNER:
2756                 if (qinq)
2757                         reg_id = 3;
2758                 else {
2759                         ret = -EINVAL;
2760                         PMD_DRV_LOG(ERR,
2761                                 "Unsupported vlan type in single vlan.\n");
2762                         return ret;
2763                 }
2764                 break;
2765         default:
2766                 ret = -EINVAL;
2767                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2768                 return ret;
2769         }
2770         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2771                                           &reg_r, NULL);
2772         if (ret != I40E_SUCCESS) {
2773                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2774                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2775                 ret = -EIO;
2776                 return ret;
2777         }
2778         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2779                     "0x%08"PRIx64"", reg_id, reg_r);
2780
2781         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2782         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2783         if (reg_r == reg_w) {
2784                 ret = 0;
2785                 PMD_DRV_LOG(DEBUG, "No need to write");
2786                 return ret;
2787         }
2788
2789         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2790                                            reg_w, NULL);
2791         if (ret != I40E_SUCCESS) {
2792                 ret = -EIO;
2793                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2794                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2795                 return ret;
2796         }
2797         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2798                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2799
2800         return ret;
2801 }
2802
2803 static void
2804 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2805 {
2806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2807         struct i40e_vsi *vsi = pf->main_vsi;
2808
2809         if (mask & ETH_VLAN_FILTER_MASK) {
2810                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2811                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2812                 else
2813                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2814         }
2815
2816         if (mask & ETH_VLAN_STRIP_MASK) {
2817                 /* Enable or disable VLAN stripping */
2818                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2819                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2820                 else
2821                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2822         }
2823
2824         if (mask & ETH_VLAN_EXTEND_MASK) {
2825                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2826                         i40e_vsi_config_double_vlan(vsi, TRUE);
2827                         /* Set global registers with default ether type value */
2828                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2829                                            ETHER_TYPE_VLAN);
2830                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2831                                            ETHER_TYPE_VLAN);
2832                 }
2833                 else
2834                         i40e_vsi_config_double_vlan(vsi, FALSE);
2835         }
2836 }
2837
2838 static void
2839 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2840                           __rte_unused uint16_t queue,
2841                           __rte_unused int on)
2842 {
2843         PMD_INIT_FUNC_TRACE();
2844 }
2845
2846 static int
2847 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2848 {
2849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850         struct i40e_vsi *vsi = pf->main_vsi;
2851         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2852         struct i40e_vsi_vlan_pvid_info info;
2853
2854         memset(&info, 0, sizeof(info));
2855         info.on = on;
2856         if (info.on)
2857                 info.config.pvid = pvid;
2858         else {
2859                 info.config.reject.tagged =
2860                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2861                 info.config.reject.untagged =
2862                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2863         }
2864
2865         return i40e_vsi_vlan_pvid_set(vsi, &info);
2866 }
2867
2868 static int
2869 i40e_dev_led_on(struct rte_eth_dev *dev)
2870 {
2871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872         uint32_t mode = i40e_led_get(hw);
2873
2874         if (mode == 0)
2875                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2876
2877         return 0;
2878 }
2879
2880 static int
2881 i40e_dev_led_off(struct rte_eth_dev *dev)
2882 {
2883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         uint32_t mode = i40e_led_get(hw);
2885
2886         if (mode != 0)
2887                 i40e_led_set(hw, 0, false);
2888
2889         return 0;
2890 }
2891
2892 static int
2893 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2894 {
2895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897
2898         fc_conf->pause_time = pf->fc_conf.pause_time;
2899         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2900         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2901
2902          /* Return current mode according to actual setting*/
2903         switch (hw->fc.current_mode) {
2904         case I40E_FC_FULL:
2905                 fc_conf->mode = RTE_FC_FULL;
2906                 break;
2907         case I40E_FC_TX_PAUSE:
2908                 fc_conf->mode = RTE_FC_TX_PAUSE;
2909                 break;
2910         case I40E_FC_RX_PAUSE:
2911                 fc_conf->mode = RTE_FC_RX_PAUSE;
2912                 break;
2913         case I40E_FC_NONE:
2914         default:
2915                 fc_conf->mode = RTE_FC_NONE;
2916         };
2917
2918         return 0;
2919 }
2920
2921 static int
2922 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2923 {
2924         uint32_t mflcn_reg, fctrl_reg, reg;
2925         uint32_t max_high_water;
2926         uint8_t i, aq_failure;
2927         int err;
2928         struct i40e_hw *hw;
2929         struct i40e_pf *pf;
2930         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2931                 [RTE_FC_NONE] = I40E_FC_NONE,
2932                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2933                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2934                 [RTE_FC_FULL] = I40E_FC_FULL
2935         };
2936
2937         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2938
2939         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2940         if ((fc_conf->high_water > max_high_water) ||
2941                         (fc_conf->high_water < fc_conf->low_water)) {
2942                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2943                         "High_water must <= %d.", max_high_water);
2944                 return -EINVAL;
2945         }
2946
2947         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2949         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2950
2951         pf->fc_conf.pause_time = fc_conf->pause_time;
2952         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2953         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2954
2955         PMD_INIT_FUNC_TRACE();
2956
2957         /* All the link flow control related enable/disable register
2958          * configuration is handle by the F/W
2959          */
2960         err = i40e_set_fc(hw, &aq_failure, true);
2961         if (err < 0)
2962                 return -ENOSYS;
2963
2964         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2965                 /* Configure flow control refresh threshold,
2966                  * the value for stat_tx_pause_refresh_timer[8]
2967                  * is used for global pause operation.
2968                  */
2969
2970                 I40E_WRITE_REG(hw,
2971                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2972                                pf->fc_conf.pause_time);
2973
2974                 /* configure the timer value included in transmitted pause
2975                  * frame,
2976                  * the value for stat_tx_pause_quanta[8] is used for global
2977                  * pause operation
2978                  */
2979                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2980                                pf->fc_conf.pause_time);
2981
2982                 fctrl_reg = I40E_READ_REG(hw,
2983                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2984
2985                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2986                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2987                 else
2988                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2989
2990                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2991                                fctrl_reg);
2992         } else {
2993                 /* Configure pause time (2 TCs per register) */
2994                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2995                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2996                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2997
2998                 /* Configure flow control refresh threshold value */
2999                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3000                                pf->fc_conf.pause_time / 2);
3001
3002                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3003
3004                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3005                  *depending on configuration
3006                  */
3007                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3008                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3009                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3010                 } else {
3011                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3012                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3013                 }
3014
3015                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3016         }
3017
3018         /* config the water marker both based on the packets and bytes */
3019         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3020                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3021                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3022         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3023                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3024                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3025         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3026                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3027                        << I40E_KILOSHIFT);
3028         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3029                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3030                        << I40E_KILOSHIFT);
3031
3032         I40E_WRITE_FLUSH(hw);
3033
3034         return 0;
3035 }
3036
3037 static int
3038 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3039                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3040 {
3041         PMD_INIT_FUNC_TRACE();
3042
3043         return -ENOSYS;
3044 }
3045
3046 /* Add a MAC address, and update filters */
3047 static void
3048 i40e_macaddr_add(struct rte_eth_dev *dev,
3049                  struct ether_addr *mac_addr,
3050                  __rte_unused uint32_t index,
3051                  uint32_t pool)
3052 {
3053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3054         struct i40e_mac_filter_info mac_filter;
3055         struct i40e_vsi *vsi;
3056         int ret;
3057
3058         /* If VMDQ not enabled or configured, return */
3059         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3060                           !pf->nb_cfg_vmdq_vsi)) {
3061                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3062                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3063                         pool);
3064                 return;
3065         }
3066
3067         if (pool > pf->nb_cfg_vmdq_vsi) {
3068                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3069                                 pool, pf->nb_cfg_vmdq_vsi);
3070                 return;
3071         }
3072
3073         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3074         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3075                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3076         else
3077                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3078
3079         if (pool == 0)
3080                 vsi = pf->main_vsi;
3081         else
3082                 vsi = pf->vmdq[pool - 1].vsi;
3083
3084         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3085         if (ret != I40E_SUCCESS) {
3086                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3087                 return;
3088         }
3089 }
3090
3091 /* Remove a MAC address, and update filters */
3092 static void
3093 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3094 {
3095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3096         struct i40e_vsi *vsi;
3097         struct rte_eth_dev_data *data = dev->data;
3098         struct ether_addr *macaddr;
3099         int ret;
3100         uint32_t i;
3101         uint64_t pool_sel;
3102
3103         macaddr = &(data->mac_addrs[index]);
3104
3105         pool_sel = dev->data->mac_pool_sel[index];
3106
3107         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3108                 if (pool_sel & (1ULL << i)) {
3109                         if (i == 0)
3110                                 vsi = pf->main_vsi;
3111                         else {
3112                                 /* No VMDQ pool enabled or configured */
3113                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3114                                         (i > pf->nb_cfg_vmdq_vsi)) {
3115                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3116                                                         "/configured");
3117                                         return;
3118                                 }
3119                                 vsi = pf->vmdq[i - 1].vsi;
3120                         }
3121                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3122
3123                         if (ret) {
3124                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3125                                 return;
3126                         }
3127                 }
3128         }
3129 }
3130
3131 /* Set perfect match or hash match of MAC and VLAN for a VF */
3132 static int
3133 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3134                  struct rte_eth_mac_filter *filter,
3135                  bool add)
3136 {
3137         struct i40e_hw *hw;
3138         struct i40e_mac_filter_info mac_filter;
3139         struct ether_addr old_mac;
3140         struct ether_addr *new_mac;
3141         struct i40e_pf_vf *vf = NULL;
3142         uint16_t vf_id;
3143         int ret;
3144
3145         if (pf == NULL) {
3146                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3147                 return -EINVAL;
3148         }
3149         hw = I40E_PF_TO_HW(pf);
3150
3151         if (filter == NULL) {
3152                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3153                 return -EINVAL;
3154         }
3155
3156         new_mac = &filter->mac_addr;
3157
3158         if (is_zero_ether_addr(new_mac)) {
3159                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3160                 return -EINVAL;
3161         }
3162
3163         vf_id = filter->dst_id;
3164
3165         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3166                 PMD_DRV_LOG(ERR, "Invalid argument.");
3167                 return -EINVAL;
3168         }
3169         vf = &pf->vfs[vf_id];
3170
3171         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3172                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3173                 return -EINVAL;
3174         }
3175
3176         if (add) {
3177                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3178                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3179                                 ETHER_ADDR_LEN);
3180                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3181                                  ETHER_ADDR_LEN);
3182
3183                 mac_filter.filter_type = filter->filter_type;
3184                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3185                 if (ret != I40E_SUCCESS) {
3186                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3187                         return -1;
3188                 }
3189                 ether_addr_copy(new_mac, &pf->dev_addr);
3190         } else {
3191                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3192                                 ETHER_ADDR_LEN);
3193                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3194                 if (ret != I40E_SUCCESS) {
3195                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3196                         return -1;
3197                 }
3198
3199                 /* Clear device address as it has been removed */
3200                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3201                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3202         }
3203
3204         return 0;
3205 }
3206
3207 /* MAC filter handle */
3208 static int
3209 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3210                 void *arg)
3211 {
3212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3213         struct rte_eth_mac_filter *filter;
3214         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3215         int ret = I40E_NOT_SUPPORTED;
3216
3217         filter = (struct rte_eth_mac_filter *)(arg);
3218
3219         switch (filter_op) {
3220         case RTE_ETH_FILTER_NOP:
3221                 ret = I40E_SUCCESS;
3222                 break;
3223         case RTE_ETH_FILTER_ADD:
3224                 i40e_pf_disable_irq0(hw);
3225                 if (filter->is_vf)
3226                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3227                 i40e_pf_enable_irq0(hw);
3228                 break;
3229         case RTE_ETH_FILTER_DELETE:
3230                 i40e_pf_disable_irq0(hw);
3231                 if (filter->is_vf)
3232                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3233                 i40e_pf_enable_irq0(hw);
3234                 break;
3235         default:
3236                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3237                 ret = I40E_ERR_PARAM;
3238                 break;
3239         }
3240
3241         return ret;
3242 }
3243
3244 static int
3245 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3246 {
3247         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3248         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3249         int ret;
3250
3251         if (!lut)
3252                 return -EINVAL;
3253
3254         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3255                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3256                                           lut, lut_size);
3257                 if (ret) {
3258                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3259                         return ret;
3260                 }
3261         } else {
3262                 uint32_t *lut_dw = (uint32_t *)lut;
3263                 uint16_t i, lut_size_dw = lut_size / 4;
3264
3265                 for (i = 0; i < lut_size_dw; i++)
3266                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3267         }
3268
3269         return 0;
3270 }
3271
3272 static int
3273 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3274 {
3275         struct i40e_pf *pf;
3276         struct i40e_hw *hw;
3277         int ret;
3278
3279         if (!vsi || !lut)
3280                 return -EINVAL;
3281
3282         pf = I40E_VSI_TO_PF(vsi);
3283         hw = I40E_VSI_TO_HW(vsi);
3284
3285         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3286                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3287                                           lut, lut_size);
3288                 if (ret) {
3289                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3290                         return ret;
3291                 }
3292         } else {
3293                 uint32_t *lut_dw = (uint32_t *)lut;
3294                 uint16_t i, lut_size_dw = lut_size / 4;
3295
3296                 for (i = 0; i < lut_size_dw; i++)
3297                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3298                 I40E_WRITE_FLUSH(hw);
3299         }
3300
3301         return 0;
3302 }
3303
3304 static int
3305 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3306                          struct rte_eth_rss_reta_entry64 *reta_conf,
3307                          uint16_t reta_size)
3308 {
3309         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3310         uint16_t i, lut_size = pf->hash_lut_size;
3311         uint16_t idx, shift;
3312         uint8_t *lut;
3313         int ret;
3314
3315         if (reta_size != lut_size ||
3316                 reta_size > ETH_RSS_RETA_SIZE_512) {
3317                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318                         "(%d) doesn't match the number hardware can supported "
3319                                         "(%d)\n", reta_size, lut_size);
3320                 return -EINVAL;
3321         }
3322
3323         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3324         if (!lut) {
3325                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3326                 return -ENOMEM;
3327         }
3328         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3329         if (ret)
3330                 goto out;
3331         for (i = 0; i < reta_size; i++) {
3332                 idx = i / RTE_RETA_GROUP_SIZE;
3333                 shift = i % RTE_RETA_GROUP_SIZE;
3334                 if (reta_conf[idx].mask & (1ULL << shift))
3335                         lut[i] = reta_conf[idx].reta[shift];
3336         }
3337         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3338
3339 out:
3340         rte_free(lut);
3341
3342         return ret;
3343 }
3344
3345 static int
3346 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3347                         struct rte_eth_rss_reta_entry64 *reta_conf,
3348                         uint16_t reta_size)
3349 {
3350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3351         uint16_t i, lut_size = pf->hash_lut_size;
3352         uint16_t idx, shift;
3353         uint8_t *lut;
3354         int ret;
3355
3356         if (reta_size != lut_size ||
3357                 reta_size > ETH_RSS_RETA_SIZE_512) {
3358                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359                         "(%d) doesn't match the number hardware can supported "
3360                                         "(%d)\n", reta_size, lut_size);
3361                 return -EINVAL;
3362         }
3363
3364         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3365         if (!lut) {
3366                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3367                 return -ENOMEM;
3368         }
3369
3370         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3371         if (ret)
3372                 goto out;
3373         for (i = 0; i < reta_size; i++) {
3374                 idx = i / RTE_RETA_GROUP_SIZE;
3375                 shift = i % RTE_RETA_GROUP_SIZE;
3376                 if (reta_conf[idx].mask & (1ULL << shift))
3377                         reta_conf[idx].reta[shift] = lut[i];
3378         }
3379
3380 out:
3381         rte_free(lut);
3382
3383         return ret;
3384 }
3385
3386 /**
3387  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3388  * @hw:   pointer to the HW structure
3389  * @mem:  pointer to mem struct to fill out
3390  * @size: size of memory requested
3391  * @alignment: what to align the allocation to
3392  **/
3393 enum i40e_status_code
3394 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3395                         struct i40e_dma_mem *mem,
3396                         u64 size,
3397                         u32 alignment)
3398 {
3399         const struct rte_memzone *mz = NULL;
3400         char z_name[RTE_MEMZONE_NAMESIZE];
3401
3402         if (!mem)
3403                 return I40E_ERR_PARAM;
3404
3405         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3406         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3407                                          alignment, RTE_PGSIZE_2M);
3408         if (!mz)
3409                 return I40E_ERR_NO_MEMORY;
3410
3411         mem->size = size;
3412         mem->va = mz->addr;
3413         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3414         mem->zone = (const void *)mz;
3415         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3416                     "%"PRIu64, mz->name, mem->pa);
3417
3418         return I40E_SUCCESS;
3419 }
3420
3421 /**
3422  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3423  * @hw:   pointer to the HW structure
3424  * @mem:  ptr to mem struct to free
3425  **/
3426 enum i40e_status_code
3427 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3428                     struct i40e_dma_mem *mem)
3429 {
3430         if (!mem)
3431                 return I40E_ERR_PARAM;
3432
3433         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3434                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3435                     mem->pa);
3436         rte_memzone_free((const struct rte_memzone *)mem->zone);
3437         mem->zone = NULL;
3438         mem->va = NULL;
3439         mem->pa = (u64)0;
3440
3441         return I40E_SUCCESS;
3442 }
3443
3444 /**
3445  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3446  * @hw:   pointer to the HW structure
3447  * @mem:  pointer to mem struct to fill out
3448  * @size: size of memory requested
3449  **/
3450 enum i40e_status_code
3451 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3452                          struct i40e_virt_mem *mem,
3453                          u32 size)
3454 {
3455         if (!mem)
3456                 return I40E_ERR_PARAM;
3457
3458         mem->size = size;
3459         mem->va = rte_zmalloc("i40e", size, 0);
3460
3461         if (mem->va)
3462                 return I40E_SUCCESS;
3463         else
3464                 return I40E_ERR_NO_MEMORY;
3465 }
3466
3467 /**
3468  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3469  * @hw:   pointer to the HW structure
3470  * @mem:  pointer to mem struct to free
3471  **/
3472 enum i40e_status_code
3473 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3474                      struct i40e_virt_mem *mem)
3475 {
3476         if (!mem)
3477                 return I40E_ERR_PARAM;
3478
3479         rte_free(mem->va);
3480         mem->va = NULL;
3481
3482         return I40E_SUCCESS;
3483 }
3484
3485 void
3486 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3487 {
3488         rte_spinlock_init(&sp->spinlock);
3489 }
3490
3491 void
3492 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3493 {
3494         rte_spinlock_lock(&sp->spinlock);
3495 }
3496
3497 void
3498 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3499 {
3500         rte_spinlock_unlock(&sp->spinlock);
3501 }
3502
3503 void
3504 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3505 {
3506         return;
3507 }
3508
3509 /**
3510  * Get the hardware capabilities, which will be parsed
3511  * and saved into struct i40e_hw.
3512  */
3513 static int
3514 i40e_get_cap(struct i40e_hw *hw)
3515 {
3516         struct i40e_aqc_list_capabilities_element_resp *buf;
3517         uint16_t len, size = 0;
3518         int ret;
3519
3520         /* Calculate a huge enough buff for saving response data temporarily */
3521         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3522                                                 I40E_MAX_CAP_ELE_NUM;
3523         buf = rte_zmalloc("i40e", len, 0);
3524         if (!buf) {
3525                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3526                 return I40E_ERR_NO_MEMORY;
3527         }
3528
3529         /* Get, parse the capabilities and save it to hw */
3530         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3531                         i40e_aqc_opc_list_func_capabilities, NULL);
3532         if (ret != I40E_SUCCESS)
3533                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3534
3535         /* Free the temporary buffer after being used */
3536         rte_free(buf);
3537
3538         return ret;
3539 }
3540
3541 static int
3542 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3543 {
3544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3546         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3547         uint16_t qp_count = 0, vsi_count = 0;
3548
3549         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3550                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3551                 return -EINVAL;
3552         }
3553         /* Add the parameter init for LFC */
3554         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3555         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3556         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3557
3558         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3559         pf->max_num_vsi = hw->func_caps.num_vsis;
3560         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3561         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3562         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3563
3564         /* FDir queue/VSI allocation */
3565         pf->fdir_qp_offset = 0;
3566         if (hw->func_caps.fd) {
3567                 pf->flags |= I40E_FLAG_FDIR;
3568                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3569         } else {
3570                 pf->fdir_nb_qps = 0;
3571         }
3572         qp_count += pf->fdir_nb_qps;
3573         vsi_count += 1;
3574
3575         /* LAN queue/VSI allocation */
3576         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3577         if (!hw->func_caps.rss) {
3578                 pf->lan_nb_qps = 1;
3579         } else {
3580                 pf->flags |= I40E_FLAG_RSS;
3581                 if (hw->mac.type == I40E_MAC_X722)
3582                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3583                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3584         }
3585         qp_count += pf->lan_nb_qps;
3586         vsi_count += 1;
3587
3588         /* VF queue/VSI allocation */
3589         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3590         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3591                 pf->flags |= I40E_FLAG_SRIOV;
3592                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3593                 pf->vf_num = pci_dev->max_vfs;
3594                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3595                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3596                             pf->vf_nb_qps * pf->vf_num);
3597         } else {
3598                 pf->vf_nb_qps = 0;
3599                 pf->vf_num = 0;
3600         }
3601         qp_count += pf->vf_nb_qps * pf->vf_num;
3602         vsi_count += pf->vf_num;
3603
3604         /* VMDq queue/VSI allocation */
3605         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3606         pf->vmdq_nb_qps = 0;
3607         pf->max_nb_vmdq_vsi = 0;
3608         if (hw->func_caps.vmdq) {
3609                 if (qp_count < hw->func_caps.num_tx_qp &&
3610                         vsi_count < hw->func_caps.num_vsis) {
3611                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3612                                 qp_count) / pf->vmdq_nb_qp_max;
3613
3614                         /* Limit the maximum number of VMDq vsi to the maximum
3615                          * ethdev can support
3616                          */
3617                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3618                                 hw->func_caps.num_vsis - vsi_count);
3619                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3620                                 ETH_64_POOLS);
3621                         if (pf->max_nb_vmdq_vsi) {
3622                                 pf->flags |= I40E_FLAG_VMDQ;
3623                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3624                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3625                                             "per VMDQ VSI, in total %u queues",
3626                                             pf->max_nb_vmdq_vsi,
3627                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3628                                             pf->max_nb_vmdq_vsi);
3629                         } else {
3630                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3631                                             "VMDq");
3632                         }
3633                 } else {
3634                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3635                 }
3636         }
3637         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3638         vsi_count += pf->max_nb_vmdq_vsi;
3639
3640         if (hw->func_caps.dcb)
3641                 pf->flags |= I40E_FLAG_DCB;
3642
3643         if (qp_count > hw->func_caps.num_tx_qp) {
3644                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3645                             "the hardware maximum %u", qp_count,
3646                             hw->func_caps.num_tx_qp);
3647                 return -EINVAL;
3648         }
3649         if (vsi_count > hw->func_caps.num_vsis) {
3650                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3651                             "the hardware maximum %u", vsi_count,
3652                             hw->func_caps.num_vsis);
3653                 return -EINVAL;
3654         }
3655
3656         return 0;
3657 }
3658
3659 static int
3660 i40e_pf_get_switch_config(struct i40e_pf *pf)
3661 {
3662         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3663         struct i40e_aqc_get_switch_config_resp *switch_config;
3664         struct i40e_aqc_switch_config_element_resp *element;
3665         uint16_t start_seid = 0, num_reported;
3666         int ret;
3667
3668         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3669                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3670         if (!switch_config) {
3671                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3672                 return -ENOMEM;
3673         }
3674
3675         /* Get the switch configurations */
3676         ret = i40e_aq_get_switch_config(hw, switch_config,
3677                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3678         if (ret != I40E_SUCCESS) {
3679                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3680                 goto fail;
3681         }
3682         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3683         if (num_reported != 1) { /* The number should be 1 */
3684                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3685                 goto fail;
3686         }
3687
3688         /* Parse the switch configuration elements */
3689         element = &(switch_config->element[0]);
3690         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3691                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3692                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3693         } else
3694                 PMD_DRV_LOG(INFO, "Unknown element type");
3695
3696 fail:
3697         rte_free(switch_config);
3698
3699         return ret;
3700 }
3701
3702 static int
3703 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3704                         uint32_t num)
3705 {
3706         struct pool_entry *entry;
3707
3708         if (pool == NULL || num == 0)
3709                 return -EINVAL;
3710
3711         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3712         if (entry == NULL) {
3713                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3714                 return -ENOMEM;
3715         }
3716
3717         /* queue heap initialize */
3718         pool->num_free = num;
3719         pool->num_alloc = 0;
3720         pool->base = base;
3721         LIST_INIT(&pool->alloc_list);
3722         LIST_INIT(&pool->free_list);
3723
3724         /* Initialize element  */
3725         entry->base = 0;
3726         entry->len = num;
3727
3728         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3729         return 0;
3730 }
3731
3732 static void
3733 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3734 {
3735         struct pool_entry *entry, *next_entry;
3736
3737         if (pool == NULL)
3738                 return;
3739
3740         for (entry = LIST_FIRST(&pool->alloc_list);
3741                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3742                         entry = next_entry) {
3743                 LIST_REMOVE(entry, next);
3744                 rte_free(entry);
3745         }
3746
3747         for (entry = LIST_FIRST(&pool->free_list);
3748                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3749                         entry = next_entry) {
3750                 LIST_REMOVE(entry, next);
3751                 rte_free(entry);
3752         }
3753
3754         pool->num_free = 0;
3755         pool->num_alloc = 0;
3756         pool->base = 0;
3757         LIST_INIT(&pool->alloc_list);
3758         LIST_INIT(&pool->free_list);
3759 }
3760
3761 static int
3762 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3763                        uint32_t base)
3764 {
3765         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3766         uint32_t pool_offset;
3767         int insert;
3768
3769         if (pool == NULL) {
3770                 PMD_DRV_LOG(ERR, "Invalid parameter");
3771                 return -EINVAL;
3772         }
3773
3774         pool_offset = base - pool->base;
3775         /* Lookup in alloc list */
3776         LIST_FOREACH(entry, &pool->alloc_list, next) {
3777                 if (entry->base == pool_offset) {
3778                         valid_entry = entry;
3779                         LIST_REMOVE(entry, next);
3780                         break;
3781                 }
3782         }
3783
3784         /* Not find, return */
3785         if (valid_entry == NULL) {
3786                 PMD_DRV_LOG(ERR, "Failed to find entry");
3787                 return -EINVAL;
3788         }
3789
3790         /**
3791          * Found it, move it to free list  and try to merge.
3792          * In order to make merge easier, always sort it by qbase.
3793          * Find adjacent prev and last entries.
3794          */
3795         prev = next = NULL;
3796         LIST_FOREACH(entry, &pool->free_list, next) {
3797                 if (entry->base > valid_entry->base) {
3798                         next = entry;
3799                         break;
3800                 }
3801                 prev = entry;
3802         }
3803
3804         insert = 0;
3805         /* Try to merge with next one*/
3806         if (next != NULL) {
3807                 /* Merge with next one */
3808                 if (valid_entry->base + valid_entry->len == next->base) {
3809                         next->base = valid_entry->base;
3810                         next->len += valid_entry->len;
3811                         rte_free(valid_entry);
3812                         valid_entry = next;
3813                         insert = 1;
3814                 }
3815         }
3816
3817         if (prev != NULL) {
3818                 /* Merge with previous one */
3819                 if (prev->base + prev->len == valid_entry->base) {
3820                         prev->len += valid_entry->len;
3821                         /* If it merge with next one, remove next node */
3822                         if (insert == 1) {
3823                                 LIST_REMOVE(valid_entry, next);
3824                                 rte_free(valid_entry);
3825                         } else {
3826                                 rte_free(valid_entry);
3827                                 insert = 1;
3828                         }
3829                 }
3830         }
3831
3832         /* Not find any entry to merge, insert */
3833         if (insert == 0) {
3834                 if (prev != NULL)
3835                         LIST_INSERT_AFTER(prev, valid_entry, next);
3836                 else if (next != NULL)
3837                         LIST_INSERT_BEFORE(next, valid_entry, next);
3838                 else /* It's empty list, insert to head */
3839                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3840         }
3841
3842         pool->num_free += valid_entry->len;
3843         pool->num_alloc -= valid_entry->len;
3844
3845         return 0;
3846 }
3847
3848 static int
3849 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3850                        uint16_t num)
3851 {
3852         struct pool_entry *entry, *valid_entry;
3853
3854         if (pool == NULL || num == 0) {
3855                 PMD_DRV_LOG(ERR, "Invalid parameter");
3856                 return -EINVAL;
3857         }
3858
3859         if (pool->num_free < num) {
3860                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3861                             num, pool->num_free);
3862                 return -ENOMEM;
3863         }
3864
3865         valid_entry = NULL;
3866         /* Lookup  in free list and find most fit one */
3867         LIST_FOREACH(entry, &pool->free_list, next) {
3868                 if (entry->len >= num) {
3869                         /* Find best one */
3870                         if (entry->len == num) {
3871                                 valid_entry = entry;
3872                                 break;
3873                         }
3874                         if (valid_entry == NULL || valid_entry->len > entry->len)
3875                                 valid_entry = entry;
3876                 }
3877         }
3878
3879         /* Not find one to satisfy the request, return */
3880         if (valid_entry == NULL) {
3881                 PMD_DRV_LOG(ERR, "No valid entry found");
3882                 return -ENOMEM;
3883         }
3884         /**
3885          * The entry have equal queue number as requested,
3886          * remove it from alloc_list.
3887          */
3888         if (valid_entry->len == num) {
3889                 LIST_REMOVE(valid_entry, next);
3890         } else {
3891                 /**
3892                  * The entry have more numbers than requested,
3893                  * create a new entry for alloc_list and minus its
3894                  * queue base and number in free_list.
3895                  */
3896                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3897                 if (entry == NULL) {
3898                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3899                                     "resource pool");
3900                         return -ENOMEM;
3901                 }
3902                 entry->base = valid_entry->base;
3903                 entry->len = num;
3904                 valid_entry->base += num;
3905                 valid_entry->len -= num;
3906                 valid_entry = entry;
3907         }
3908
3909         /* Insert it into alloc list, not sorted */
3910         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3911
3912         pool->num_free -= valid_entry->len;
3913         pool->num_alloc += valid_entry->len;
3914
3915         return valid_entry->base + pool->base;
3916 }
3917
3918 /**
3919  * bitmap_is_subset - Check whether src2 is subset of src1
3920  **/
3921 static inline int
3922 bitmap_is_subset(uint8_t src1, uint8_t src2)
3923 {
3924         return !((src1 ^ src2) & src2);
3925 }
3926
3927 static enum i40e_status_code
3928 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3929 {
3930         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3931
3932         /* If DCB is not supported, only default TC is supported */
3933         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3934                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3935                 return I40E_NOT_SUPPORTED;
3936         }
3937
3938         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3939                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3940                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3941                             enabled_tcmap);
3942                 return I40E_NOT_SUPPORTED;
3943         }
3944         return I40E_SUCCESS;
3945 }
3946
3947 int
3948 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3949                                 struct i40e_vsi_vlan_pvid_info *info)
3950 {
3951         struct i40e_hw *hw;
3952         struct i40e_vsi_context ctxt;
3953         uint8_t vlan_flags = 0;
3954         int ret;
3955
3956         if (vsi == NULL || info == NULL) {
3957                 PMD_DRV_LOG(ERR, "invalid parameters");
3958                 return I40E_ERR_PARAM;
3959         }
3960
3961         if (info->on) {
3962                 vsi->info.pvid = info->config.pvid;
3963                 /**
3964                  * If insert pvid is enabled, only tagged pkts are
3965                  * allowed to be sent out.
3966                  */
3967                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3968                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3969         } else {
3970                 vsi->info.pvid = 0;
3971                 if (info->config.reject.tagged == 0)
3972                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3973
3974                 if (info->config.reject.untagged == 0)
3975                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3976         }
3977         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3978                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3979         vsi->info.port_vlan_flags |= vlan_flags;
3980         vsi->info.valid_sections =
3981                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3982         memset(&ctxt, 0, sizeof(ctxt));
3983         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3984         ctxt.seid = vsi->seid;
3985
3986         hw = I40E_VSI_TO_HW(vsi);
3987         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3988         if (ret != I40E_SUCCESS)
3989                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3990
3991         return ret;
3992 }
3993
3994 static int
3995 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3996 {
3997         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3998         int i, ret;
3999         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4000
4001         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4002         if (ret != I40E_SUCCESS)
4003                 return ret;
4004
4005         if (!vsi->seid) {
4006                 PMD_DRV_LOG(ERR, "seid not valid");
4007                 return -EINVAL;
4008         }
4009
4010         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4011         tc_bw_data.tc_valid_bits = enabled_tcmap;
4012         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4013                 tc_bw_data.tc_bw_credits[i] =
4014                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4015
4016         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4017         if (ret != I40E_SUCCESS) {
4018                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4019                 return ret;
4020         }
4021
4022         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4023                                         sizeof(vsi->info.qs_handle));
4024         return I40E_SUCCESS;
4025 }
4026
4027 static enum i40e_status_code
4028 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4029                                  struct i40e_aqc_vsi_properties_data *info,
4030                                  uint8_t enabled_tcmap)
4031 {
4032         enum i40e_status_code ret;
4033         int i, total_tc = 0;
4034         uint16_t qpnum_per_tc, bsf, qp_idx;
4035
4036         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4037         if (ret != I40E_SUCCESS)
4038                 return ret;
4039
4040         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4041                 if (enabled_tcmap & (1 << i))
4042                         total_tc++;
4043         vsi->enabled_tc = enabled_tcmap;
4044
4045         /* Number of queues per enabled TC */
4046         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4047         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4048         bsf = rte_bsf32(qpnum_per_tc);
4049
4050         /* Adjust the queue number to actual queues that can be applied */
4051         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4052                 vsi->nb_qps = qpnum_per_tc * total_tc;
4053
4054         /**
4055          * Configure TC and queue mapping parameters, for enabled TC,
4056          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4057          * default queue will serve it.
4058          */
4059         qp_idx = 0;
4060         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4061                 if (vsi->enabled_tc & (1 << i)) {
4062                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4063                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4064                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4065                         qp_idx += qpnum_per_tc;
4066                 } else
4067                         info->tc_mapping[i] = 0;
4068         }
4069
4070         /* Associate queue number with VSI */
4071         if (vsi->type == I40E_VSI_SRIOV) {
4072                 info->mapping_flags |=
4073                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4074                 for (i = 0; i < vsi->nb_qps; i++)
4075                         info->queue_mapping[i] =
4076                                 rte_cpu_to_le_16(vsi->base_queue + i);
4077         } else {
4078                 info->mapping_flags |=
4079                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4080                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4081         }
4082         info->valid_sections |=
4083                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4084
4085         return I40E_SUCCESS;
4086 }
4087
4088 static int
4089 i40e_veb_release(struct i40e_veb *veb)
4090 {
4091         struct i40e_vsi *vsi;
4092         struct i40e_hw *hw;
4093
4094         if (veb == NULL)
4095                 return -EINVAL;
4096
4097         if (!TAILQ_EMPTY(&veb->head)) {
4098                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4099                 return -EACCES;
4100         }
4101         /* associate_vsi field is NULL for floating VEB */
4102         if (veb->associate_vsi != NULL) {
4103                 vsi = veb->associate_vsi;
4104                 hw = I40E_VSI_TO_HW(vsi);
4105
4106                 vsi->uplink_seid = veb->uplink_seid;
4107                 vsi->veb = NULL;
4108         } else {
4109                 veb->associate_pf->main_vsi->floating_veb = NULL;
4110                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4111         }
4112
4113         i40e_aq_delete_element(hw, veb->seid, NULL);
4114         rte_free(veb);
4115         return I40E_SUCCESS;
4116 }
4117
4118 /* Setup a veb */
4119 static struct i40e_veb *
4120 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4121 {
4122         struct i40e_veb *veb;
4123         int ret;
4124         struct i40e_hw *hw;
4125
4126         if (pf == NULL) {
4127                 PMD_DRV_LOG(ERR,
4128                             "veb setup failed, associated PF shouldn't null");
4129                 return NULL;
4130         }
4131         hw = I40E_PF_TO_HW(pf);
4132
4133         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4134         if (!veb) {
4135                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4136                 goto fail;
4137         }
4138
4139         veb->associate_vsi = vsi;
4140         veb->associate_pf = pf;
4141         TAILQ_INIT(&veb->head);
4142         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4143
4144         /* create floating veb if vsi is NULL */
4145         if (vsi != NULL) {
4146                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4147                                       I40E_DEFAULT_TCMAP, false,
4148                                       &veb->seid, false, NULL);
4149         } else {
4150                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4151                                       true, &veb->seid, false, NULL);
4152         }
4153
4154         if (ret != I40E_SUCCESS) {
4155                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4156                             hw->aq.asq_last_status);
4157                 goto fail;
4158         }
4159
4160         /* get statistics index */
4161         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4162                                 &veb->stats_idx, NULL, NULL, NULL);
4163         if (ret != I40E_SUCCESS) {
4164                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4165                             hw->aq.asq_last_status);
4166                 goto fail;
4167         }
4168         /* Get VEB bandwidth, to be implemented */
4169         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4170         if (vsi)
4171                 vsi->uplink_seid = veb->seid;
4172
4173         return veb;
4174 fail:
4175         rte_free(veb);
4176         return NULL;
4177 }
4178
4179 int
4180 i40e_vsi_release(struct i40e_vsi *vsi)
4181 {
4182         struct i40e_pf *pf;
4183         struct i40e_hw *hw;
4184         struct i40e_vsi_list *vsi_list;
4185         void *temp;
4186         int ret;
4187         struct i40e_mac_filter *f;
4188         uint16_t user_param;
4189
4190         if (!vsi)
4191                 return I40E_SUCCESS;
4192
4193         user_param = vsi->user_param;
4194
4195         pf = I40E_VSI_TO_PF(vsi);
4196         hw = I40E_VSI_TO_HW(vsi);
4197
4198         /* VSI has child to attach, release child first */
4199         if (vsi->veb) {
4200                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4201                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4202                                 return -1;
4203                 }
4204                 i40e_veb_release(vsi->veb);
4205         }
4206
4207         if (vsi->floating_veb) {
4208                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4209                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4210                                 return -1;
4211                 }
4212         }
4213
4214         /* Remove all macvlan filters of the VSI */
4215         i40e_vsi_remove_all_macvlan_filter(vsi);
4216         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4217                 rte_free(f);
4218
4219         if (vsi->type != I40E_VSI_MAIN &&
4220             ((vsi->type != I40E_VSI_SRIOV) ||
4221             !pf->floating_veb_list[user_param])) {
4222                 /* Remove vsi from parent's sibling list */
4223                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4224                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4225                         return I40E_ERR_PARAM;
4226                 }
4227                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4228                                 &vsi->sib_vsi_list, list);
4229
4230                 /* Remove all switch element of the VSI */
4231                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4232                 if (ret != I40E_SUCCESS)
4233                         PMD_DRV_LOG(ERR, "Failed to delete element");
4234         }
4235
4236         if ((vsi->type == I40E_VSI_SRIOV) &&
4237             pf->floating_veb_list[user_param]) {
4238                 /* Remove vsi from parent's sibling list */
4239                 if (vsi->parent_vsi == NULL ||
4240                     vsi->parent_vsi->floating_veb == NULL) {
4241                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4242                         return I40E_ERR_PARAM;
4243                 }
4244                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4245                              &vsi->sib_vsi_list, list);
4246
4247                 /* Remove all switch element of the VSI */
4248                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4249                 if (ret != I40E_SUCCESS)
4250                         PMD_DRV_LOG(ERR, "Failed to delete element");
4251         }
4252
4253         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4254
4255         if (vsi->type != I40E_VSI_SRIOV)
4256                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4257         rte_free(vsi);
4258
4259         return I40E_SUCCESS;
4260 }
4261
4262 static int
4263 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4264 {
4265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4266         struct i40e_aqc_remove_macvlan_element_data def_filter;
4267         struct i40e_mac_filter_info filter;
4268         int ret;
4269
4270         if (vsi->type != I40E_VSI_MAIN)
4271                 return I40E_ERR_CONFIG;
4272         memset(&def_filter, 0, sizeof(def_filter));
4273         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4274                                         ETH_ADDR_LEN);
4275         def_filter.vlan_tag = 0;
4276         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4277                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4278         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4279         if (ret != I40E_SUCCESS) {
4280                 struct i40e_mac_filter *f;
4281                 struct ether_addr *mac;
4282
4283                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4284                             "macvlan filter");
4285                 /* It needs to add the permanent mac into mac list */
4286                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4287                 if (f == NULL) {
4288                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4289                         return I40E_ERR_NO_MEMORY;
4290                 }
4291                 mac = &f->mac_info.mac_addr;
4292                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4293                                 ETH_ADDR_LEN);
4294                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4295                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4296                 vsi->mac_num++;
4297
4298                 return ret;
4299         }
4300         (void)rte_memcpy(&filter.mac_addr,
4301                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4302         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4303         return i40e_vsi_add_mac(vsi, &filter);
4304 }
4305
4306 /*
4307  * i40e_vsi_get_bw_config - Query VSI BW Information
4308  * @vsi: the VSI to be queried
4309  *
4310  * Returns 0 on success, negative value on failure
4311  */
4312 static enum i40e_status_code
4313 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4314 {
4315         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4316         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4317         struct i40e_hw *hw = &vsi->adapter->hw;
4318         i40e_status ret;
4319         int i;
4320         uint32_t bw_max;
4321
4322         memset(&bw_config, 0, sizeof(bw_config));
4323         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4324         if (ret != I40E_SUCCESS) {
4325                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4326                             hw->aq.asq_last_status);
4327                 return ret;
4328         }
4329
4330         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4331         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4332                                         &ets_sla_config, NULL);
4333         if (ret != I40E_SUCCESS) {
4334                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4335                             "configuration %u", hw->aq.asq_last_status);
4336                 return ret;
4337         }
4338
4339         /* store and print out BW info */
4340         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4341         vsi->bw_info.bw_max = bw_config.max_bw;
4342         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4343         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4344         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4345                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4346                      I40E_16_BIT_WIDTH);
4347         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4348                 vsi->bw_info.bw_ets_share_credits[i] =
4349                                 ets_sla_config.share_credits[i];
4350                 vsi->bw_info.bw_ets_credits[i] =
4351                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4352                 /* 4 bits per TC, 4th bit is reserved */
4353                 vsi->bw_info.bw_ets_max[i] =
4354                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4355                                   RTE_LEN2MASK(3, uint8_t));
4356                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4357                             vsi->bw_info.bw_ets_share_credits[i]);
4358                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4359                             vsi->bw_info.bw_ets_credits[i]);
4360                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4361                             vsi->bw_info.bw_ets_max[i]);
4362         }
4363
4364         return I40E_SUCCESS;
4365 }
4366
4367 /* i40e_enable_pf_lb
4368  * @pf: pointer to the pf structure
4369  *
4370  * allow loopback on pf
4371  */
4372 static inline void
4373 i40e_enable_pf_lb(struct i40e_pf *pf)
4374 {
4375         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4376         struct i40e_vsi_context ctxt;
4377         int ret;
4378
4379         /* Use the FW API if FW >= v5.0 */
4380         if (hw->aq.fw_maj_ver < 5) {
4381                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4382                 return;
4383         }
4384
4385         memset(&ctxt, 0, sizeof(ctxt));
4386         ctxt.seid = pf->main_vsi_seid;
4387         ctxt.pf_num = hw->pf_id;
4388         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4389         if (ret) {
4390                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4391                             ret, hw->aq.asq_last_status);
4392                 return;
4393         }
4394         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4395         ctxt.info.valid_sections =
4396                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4397         ctxt.info.switch_id |=
4398                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4399
4400         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401         if (ret)
4402                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4403                             hw->aq.asq_last_status);
4404 }
4405
4406 /* Setup a VSI */
4407 struct i40e_vsi *
4408 i40e_vsi_setup(struct i40e_pf *pf,
4409                enum i40e_vsi_type type,
4410                struct i40e_vsi *uplink_vsi,
4411                uint16_t user_param)
4412 {
4413         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4414         struct i40e_vsi *vsi;
4415         struct i40e_mac_filter_info filter;
4416         int ret;
4417         struct i40e_vsi_context ctxt;
4418         struct ether_addr broadcast =
4419                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4420
4421         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4422             uplink_vsi == NULL) {
4423                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4424                             "VSI link shouldn't be NULL");
4425                 return NULL;
4426         }
4427
4428         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4429                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4430                             "uplink VSI should be NULL");
4431                 return NULL;
4432         }
4433
4434         /* two situations
4435          * 1.type is not MAIN and uplink vsi is not NULL
4436          * If uplink vsi didn't setup VEB, create one first under veb field
4437          * 2.type is SRIOV and the uplink is NULL
4438          * If floating VEB is NULL, create one veb under floating veb field
4439          */
4440
4441         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4442             uplink_vsi->veb == NULL) {
4443                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4444
4445                 if (uplink_vsi->veb == NULL) {
4446                         PMD_DRV_LOG(ERR, "VEB setup failed");
4447                         return NULL;
4448                 }
4449                 /* set ALLOWLOOPBACk on pf, when veb is created */
4450                 i40e_enable_pf_lb(pf);
4451         }
4452
4453         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4454             pf->main_vsi->floating_veb == NULL) {
4455                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4456
4457                 if (pf->main_vsi->floating_veb == NULL) {
4458                         PMD_DRV_LOG(ERR, "VEB setup failed");
4459                         return NULL;
4460                 }
4461         }
4462
4463         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4464         if (!vsi) {
4465                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4466                 return NULL;
4467         }
4468         TAILQ_INIT(&vsi->mac_list);
4469         vsi->type = type;
4470         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4471         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4472         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4473         vsi->user_param = user_param;
4474         /* Allocate queues */
4475         switch (vsi->type) {
4476         case I40E_VSI_MAIN  :
4477                 vsi->nb_qps = pf->lan_nb_qps;
4478                 break;
4479         case I40E_VSI_SRIOV :
4480                 vsi->nb_qps = pf->vf_nb_qps;
4481                 break;
4482         case I40E_VSI_VMDQ2:
4483                 vsi->nb_qps = pf->vmdq_nb_qps;
4484                 break;
4485         case I40E_VSI_FDIR:
4486                 vsi->nb_qps = pf->fdir_nb_qps;
4487                 break;
4488         default:
4489                 goto fail_mem;
4490         }
4491         /*
4492          * The filter status descriptor is reported in rx queue 0,
4493          * while the tx queue for fdir filter programming has no
4494          * such constraints, can be non-zero queues.
4495          * To simplify it, choose FDIR vsi use queue 0 pair.
4496          * To make sure it will use queue 0 pair, queue allocation
4497          * need be done before this function is called
4498          */
4499         if (type != I40E_VSI_FDIR) {
4500                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4501                         if (ret < 0) {
4502                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4503                                                 vsi->seid, ret);
4504                                 goto fail_mem;
4505                         }
4506                         vsi->base_queue = ret;
4507         } else
4508                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4509
4510         /* VF has MSIX interrupt in VF range, don't allocate here */
4511         if (type == I40E_VSI_MAIN) {
4512                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4513                                           RTE_MIN(vsi->nb_qps,
4514                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4515                 if (ret < 0) {
4516                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4517                                     vsi->seid, ret);
4518                         goto fail_queue_alloc;
4519                 }
4520                 vsi->msix_intr = ret;
4521                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4522         } else if (type != I40E_VSI_SRIOV) {
4523                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4524                 if (ret < 0) {
4525                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4526                         goto fail_queue_alloc;
4527                 }
4528                 vsi->msix_intr = ret;
4529                 vsi->nb_msix = 1;
4530         } else {
4531                 vsi->msix_intr = 0;
4532                 vsi->nb_msix = 0;
4533         }
4534
4535         /* Add VSI */
4536         if (type == I40E_VSI_MAIN) {
4537                 /* For main VSI, no need to add since it's default one */
4538                 vsi->uplink_seid = pf->mac_seid;
4539                 vsi->seid = pf->main_vsi_seid;
4540                 /* Bind queues with specific MSIX interrupt */
4541                 /**
4542                  * Needs 2 interrupt at least, one for misc cause which will
4543                  * enabled from OS side, Another for queues binding the
4544                  * interrupt from device side only.
4545                  */
4546
4547                 /* Get default VSI parameters from hardware */
4548                 memset(&ctxt, 0, sizeof(ctxt));
4549                 ctxt.seid = vsi->seid;
4550                 ctxt.pf_num = hw->pf_id;
4551                 ctxt.uplink_seid = vsi->uplink_seid;
4552                 ctxt.vf_num = 0;
4553                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4554                 if (ret != I40E_SUCCESS) {
4555                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4556                         goto fail_msix_alloc;
4557                 }
4558                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4559                         sizeof(struct i40e_aqc_vsi_properties_data));
4560                 vsi->vsi_id = ctxt.vsi_number;
4561                 vsi->info.valid_sections = 0;
4562
4563                 /* Configure tc, enabled TC0 only */
4564                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4565                         I40E_SUCCESS) {
4566                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4567                         goto fail_msix_alloc;
4568                 }
4569
4570                 /* TC, queue mapping */
4571                 memset(&ctxt, 0, sizeof(ctxt));
4572                 vsi->info.valid_sections |=
4573                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4574                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4575                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4576                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4577                         sizeof(struct i40e_aqc_vsi_properties_data));
4578                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4579                                                 I40E_DEFAULT_TCMAP);
4580                 if (ret != I40E_SUCCESS) {
4581                         PMD_DRV_LOG(ERR, "Failed to configure "
4582                                     "TC queue mapping");
4583                         goto fail_msix_alloc;
4584                 }
4585                 ctxt.seid = vsi->seid;
4586                 ctxt.pf_num = hw->pf_id;
4587                 ctxt.uplink_seid = vsi->uplink_seid;
4588                 ctxt.vf_num = 0;
4589
4590                 /* Update VSI parameters */
4591                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4592                 if (ret != I40E_SUCCESS) {
4593                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4594                         goto fail_msix_alloc;
4595                 }
4596
4597                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4598                                                 sizeof(vsi->info.tc_mapping));
4599                 (void)rte_memcpy(&vsi->info.queue_mapping,
4600                                 &ctxt.info.queue_mapping,
4601                         sizeof(vsi->info.queue_mapping));
4602                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4603                 vsi->info.valid_sections = 0;
4604
4605                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4606                                 ETH_ADDR_LEN);
4607
4608                 /**
4609                  * Updating default filter settings are necessary to prevent
4610                  * reception of tagged packets.
4611                  * Some old firmware configurations load a default macvlan
4612                  * filter which accepts both tagged and untagged packets.
4613                  * The updating is to use a normal filter instead if needed.
4614                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4615                  * The firmware with correct configurations load the default
4616                  * macvlan filter which is expected and cannot be removed.
4617                  */
4618                 i40e_update_default_filter_setting(vsi);
4619                 i40e_config_qinq(hw, vsi);
4620         } else if (type == I40E_VSI_SRIOV) {
4621                 memset(&ctxt, 0, sizeof(ctxt));
4622                 /**
4623                  * For other VSI, the uplink_seid equals to uplink VSI's
4624                  * uplink_seid since they share same VEB
4625                  */
4626                 if (uplink_vsi == NULL)
4627                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4628                 else
4629                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4630                 ctxt.pf_num = hw->pf_id;
4631                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4632                 ctxt.uplink_seid = vsi->uplink_seid;
4633                 ctxt.connection_type = 0x1;
4634                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4635
4636                 /* Use the VEB configuration if FW >= v5.0 */
4637                 if (hw->aq.fw_maj_ver >= 5) {
4638                         /* Configure switch ID */
4639                         ctxt.info.valid_sections |=
4640                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4641                         ctxt.info.switch_id =
4642                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4643                 }
4644
4645                 /* Configure port/vlan */
4646                 ctxt.info.valid_sections |=
4647                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4648                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4649                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4650                                                 I40E_DEFAULT_TCMAP);
4651                 if (ret != I40E_SUCCESS) {
4652                         PMD_DRV_LOG(ERR, "Failed to configure "
4653                                     "TC queue mapping");
4654                         goto fail_msix_alloc;
4655                 }
4656                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4657                 ctxt.info.valid_sections |=
4658                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4659                 /**
4660                  * Since VSI is not created yet, only configure parameter,
4661                  * will add vsi below.
4662                  */
4663
4664                 i40e_config_qinq(hw, vsi);
4665         } else if (type == I40E_VSI_VMDQ2) {
4666                 memset(&ctxt, 0, sizeof(ctxt));
4667                 /*
4668                  * For other VSI, the uplink_seid equals to uplink VSI's
4669                  * uplink_seid since they share same VEB
4670                  */
4671                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4672                 ctxt.pf_num = hw->pf_id;
4673                 ctxt.vf_num = 0;
4674                 ctxt.uplink_seid = vsi->uplink_seid;
4675                 ctxt.connection_type = 0x1;
4676                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4677
4678                 ctxt.info.valid_sections |=
4679                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4680                 /* user_param carries flag to enable loop back */
4681                 if (user_param) {
4682                         ctxt.info.switch_id =
4683                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4684                         ctxt.info.switch_id |=
4685                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4686                 }
4687
4688                 /* Configure port/vlan */
4689                 ctxt.info.valid_sections |=
4690                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4691                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4692                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4693                                                 I40E_DEFAULT_TCMAP);
4694                 if (ret != I40E_SUCCESS) {
4695                         PMD_DRV_LOG(ERR, "Failed to configure "
4696                                         "TC queue mapping");
4697                         goto fail_msix_alloc;
4698                 }
4699                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4700                 ctxt.info.valid_sections |=
4701                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4702         } else if (type == I40E_VSI_FDIR) {
4703                 memset(&ctxt, 0, sizeof(ctxt));
4704                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4705                 ctxt.pf_num = hw->pf_id;
4706                 ctxt.vf_num = 0;
4707                 ctxt.uplink_seid = vsi->uplink_seid;
4708                 ctxt.connection_type = 0x1;     /* regular data port */
4709                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4710                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4711                                                 I40E_DEFAULT_TCMAP);
4712                 if (ret != I40E_SUCCESS) {
4713                         PMD_DRV_LOG(ERR, "Failed to configure "
4714                                         "TC queue mapping.");
4715                         goto fail_msix_alloc;
4716                 }
4717                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4718                 ctxt.info.valid_sections |=
4719                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4720         } else {
4721                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4722                 goto fail_msix_alloc;
4723         }
4724
4725         if (vsi->type != I40E_VSI_MAIN) {
4726                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4727                 if (ret != I40E_SUCCESS) {
4728                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4729                                     hw->aq.asq_last_status);
4730                         goto fail_msix_alloc;
4731                 }
4732                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4733                 vsi->info.valid_sections = 0;
4734                 vsi->seid = ctxt.seid;
4735                 vsi->vsi_id = ctxt.vsi_number;
4736                 vsi->sib_vsi_list.vsi = vsi;
4737                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4738                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4739                                           &vsi->sib_vsi_list, list);
4740                 } else {
4741                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4742                                           &vsi->sib_vsi_list, list);
4743                 }
4744         }
4745
4746         /* MAC/VLAN configuration */
4747         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4748         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4749
4750         ret = i40e_vsi_add_mac(vsi, &filter);
4751         if (ret != I40E_SUCCESS) {
4752                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4753                 goto fail_msix_alloc;
4754         }
4755
4756         /* Get VSI BW information */
4757         i40e_vsi_get_bw_config(vsi);
4758         return vsi;
4759 fail_msix_alloc:
4760         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4761 fail_queue_alloc:
4762         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4763 fail_mem:
4764         rte_free(vsi);
4765         return NULL;
4766 }
4767
4768 /* Configure vlan filter on or off */
4769 int
4770 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4771 {
4772         int i, num;
4773         struct i40e_mac_filter *f;
4774         void *temp;
4775         struct i40e_mac_filter_info *mac_filter;
4776         enum rte_mac_filter_type desired_filter;
4777         int ret = I40E_SUCCESS;
4778
4779         if (on) {
4780                 /* Filter to match MAC and VLAN */
4781                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4782         } else {
4783                 /* Filter to match only MAC */
4784                 desired_filter = RTE_MAC_PERFECT_MATCH;
4785         }
4786
4787         num = vsi->mac_num;
4788
4789         mac_filter = rte_zmalloc("mac_filter_info_data",
4790                                  num * sizeof(*mac_filter), 0);
4791         if (mac_filter == NULL) {
4792                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4793                 return I40E_ERR_NO_MEMORY;
4794         }
4795
4796         i = 0;
4797
4798         /* Remove all existing mac */
4799         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4800                 mac_filter[i] = f->mac_info;
4801                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4802                 if (ret) {
4803                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4804                                     on ? "enable" : "disable");
4805                         goto DONE;
4806                 }
4807                 i++;
4808         }
4809
4810         /* Override with new filter */
4811         for (i = 0; i < num; i++) {
4812                 mac_filter[i].filter_type = desired_filter;
4813                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4814                 if (ret) {
4815                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4816                                     on ? "enable" : "disable");
4817                         goto DONE;
4818                 }
4819         }
4820
4821 DONE:
4822         rte_free(mac_filter);
4823         return ret;
4824 }
4825
4826 /* Configure vlan stripping on or off */
4827 int
4828 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4829 {
4830         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4831         struct i40e_vsi_context ctxt;
4832         uint8_t vlan_flags;
4833         int ret = I40E_SUCCESS;
4834
4835         /* Check if it has been already on or off */
4836         if (vsi->info.valid_sections &
4837                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4838                 if (on) {
4839                         if ((vsi->info.port_vlan_flags &
4840                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4841                                 return 0; /* already on */
4842                 } else {
4843                         if ((vsi->info.port_vlan_flags &
4844                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4845                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4846                                 return 0; /* already off */
4847                 }
4848         }
4849
4850         if (on)
4851                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4852         else
4853                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4854         vsi->info.valid_sections =
4855                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4856         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4857         vsi->info.port_vlan_flags |= vlan_flags;
4858         ctxt.seid = vsi->seid;
4859         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4860         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4861         if (ret)
4862                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4863                             on ? "enable" : "disable");
4864
4865         return ret;
4866 }
4867
4868 static int
4869 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4870 {
4871         struct rte_eth_dev_data *data = dev->data;
4872         int ret;
4873         int mask = 0;
4874
4875         /* Apply vlan offload setting */
4876         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4877         i40e_vlan_offload_set(dev, mask);
4878
4879         /* Apply double-vlan setting, not implemented yet */
4880
4881         /* Apply pvid setting */
4882         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4883                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4884         if (ret)
4885                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4886
4887         return ret;
4888 }
4889
4890 static int
4891 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4892 {
4893         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4894
4895         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4896 }
4897
4898 static int
4899 i40e_update_flow_control(struct i40e_hw *hw)
4900 {
4901 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4902         struct i40e_link_status link_status;
4903         uint32_t rxfc = 0, txfc = 0, reg;
4904         uint8_t an_info;
4905         int ret;
4906
4907         memset(&link_status, 0, sizeof(link_status));
4908         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4909         if (ret != I40E_SUCCESS) {
4910                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4911                 goto write_reg; /* Disable flow control */
4912         }
4913
4914         an_info = hw->phy.link_info.an_info;
4915         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4916                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4917                 ret = I40E_ERR_NOT_READY;
4918                 goto write_reg; /* Disable flow control */
4919         }
4920         /**
4921          * If link auto negotiation is enabled, flow control needs to
4922          * be configured according to it
4923          */
4924         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4925         case I40E_LINK_PAUSE_RXTX:
4926                 rxfc = 1;
4927                 txfc = 1;
4928                 hw->fc.current_mode = I40E_FC_FULL;
4929                 break;
4930         case I40E_AQ_LINK_PAUSE_RX:
4931                 rxfc = 1;
4932                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4933                 break;
4934         case I40E_AQ_LINK_PAUSE_TX:
4935                 txfc = 1;
4936                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4937                 break;
4938         default:
4939                 hw->fc.current_mode = I40E_FC_NONE;
4940                 break;
4941         }
4942
4943 write_reg:
4944         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4945                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4946         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4947         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4948         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4949         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4950
4951         return ret;
4952 }
4953
4954 /* PF setup */
4955 static int
4956 i40e_pf_setup(struct i40e_pf *pf)
4957 {
4958         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4959         struct i40e_filter_control_settings settings;
4960         struct i40e_vsi *vsi;
4961         int ret;
4962
4963         /* Clear all stats counters */
4964         pf->offset_loaded = FALSE;
4965         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4966         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4967
4968         ret = i40e_pf_get_switch_config(pf);
4969         if (ret != I40E_SUCCESS) {
4970                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4971                 return ret;
4972         }
4973         if (pf->flags & I40E_FLAG_FDIR) {
4974                 /* make queue allocated first, let FDIR use queue pair 0*/
4975                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4976                 if (ret != I40E_FDIR_QUEUE_ID) {
4977                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4978                                     " ret =%d", ret);
4979                         pf->flags &= ~I40E_FLAG_FDIR;
4980                 }
4981         }
4982         /*  main VSI setup */
4983         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4984         if (!vsi) {
4985                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4986                 return I40E_ERR_NOT_READY;
4987         }
4988         pf->main_vsi = vsi;
4989
4990         /* Configure filter control */
4991         memset(&settings, 0, sizeof(settings));
4992         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4993                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4994         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4995                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4996         else {
4997                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4998                                                 hw->func_caps.rss_table_size);
4999                 return I40E_ERR_PARAM;
5000         }
5001         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5002                         "size: %u\n", hw->func_caps.rss_table_size);
5003         pf->hash_lut_size = hw->func_caps.rss_table_size;
5004
5005         /* Enable ethtype and macvlan filters */
5006         settings.enable_ethtype = TRUE;
5007         settings.enable_macvlan = TRUE;
5008         ret = i40e_set_filter_control(hw, &settings);
5009         if (ret)
5010                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5011                                                                 ret);
5012
5013         /* Update flow control according to the auto negotiation */
5014         i40e_update_flow_control(hw);
5015
5016         return I40E_SUCCESS;
5017 }
5018
5019 int
5020 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5021 {
5022         uint32_t reg;
5023         uint16_t j;
5024
5025         /**
5026          * Set or clear TX Queue Disable flags,
5027          * which is required by hardware.
5028          */
5029         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5030         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5031
5032         /* Wait until the request is finished */
5033         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5034                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5035                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5036                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5037                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5038                                                         & 0x1))) {
5039                         break;
5040                 }
5041         }
5042         if (on) {
5043                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5044                         return I40E_SUCCESS; /* already on, skip next steps */
5045
5046                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5047                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5048         } else {
5049                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5050                         return I40E_SUCCESS; /* already off, skip next steps */
5051                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5052         }
5053         /* Write the register */
5054         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5055         /* Check the result */
5056         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5057                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5058                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5059                 if (on) {
5060                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5061                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5062                                 break;
5063                 } else {
5064                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5065                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5066                                 break;
5067                 }
5068         }
5069         /* Check if it is timeout */
5070         if (j >= I40E_CHK_Q_ENA_COUNT) {
5071                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5072                             (on ? "enable" : "disable"), q_idx);
5073                 return I40E_ERR_TIMEOUT;
5074         }
5075
5076         return I40E_SUCCESS;
5077 }
5078
5079 /* Swith on or off the tx queues */
5080 static int
5081 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5082 {
5083         struct rte_eth_dev_data *dev_data = pf->dev_data;
5084         struct i40e_tx_queue *txq;
5085         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5086         uint16_t i;
5087         int ret;
5088
5089         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5090                 txq = dev_data->tx_queues[i];
5091                 /* Don't operate the queue if not configured or
5092                  * if starting only per queue */
5093                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5094                         continue;
5095                 if (on)
5096                         ret = i40e_dev_tx_queue_start(dev, i);
5097                 else
5098                         ret = i40e_dev_tx_queue_stop(dev, i);
5099                 if ( ret != I40E_SUCCESS)
5100                         return ret;
5101         }
5102
5103         return I40E_SUCCESS;
5104 }
5105
5106 int
5107 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5108 {
5109         uint32_t reg;
5110         uint16_t j;
5111
5112         /* Wait until the request is finished */
5113         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5114                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5115                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5116                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5117                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5118                         break;
5119         }
5120
5121         if (on) {
5122                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5123                         return I40E_SUCCESS; /* Already on, skip next steps */
5124                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5125         } else {
5126                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5127                         return I40E_SUCCESS; /* Already off, skip next steps */
5128                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5129         }
5130
5131         /* Write the register */
5132         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5133         /* Check the result */
5134         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5135                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5136                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5137                 if (on) {
5138                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5139                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5140                                 break;
5141                 } else {
5142                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5143                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5144                                 break;
5145                 }
5146         }
5147
5148         /* Check if it is timeout */
5149         if (j >= I40E_CHK_Q_ENA_COUNT) {
5150                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5151                             (on ? "enable" : "disable"), q_idx);
5152                 return I40E_ERR_TIMEOUT;
5153         }
5154
5155         return I40E_SUCCESS;
5156 }
5157 /* Switch on or off the rx queues */
5158 static int
5159 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5160 {
5161         struct rte_eth_dev_data *dev_data = pf->dev_data;
5162         struct i40e_rx_queue *rxq;
5163         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5164         uint16_t i;
5165         int ret;
5166
5167         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5168                 rxq = dev_data->rx_queues[i];
5169                 /* Don't operate the queue if not configured or
5170                  * if starting only per queue */
5171                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5172                         continue;
5173                 if (on)
5174                         ret = i40e_dev_rx_queue_start(dev, i);
5175                 else
5176                         ret = i40e_dev_rx_queue_stop(dev, i);
5177                 if (ret != I40E_SUCCESS)
5178                         return ret;
5179         }
5180
5181         return I40E_SUCCESS;
5182 }
5183
5184 /* Switch on or off all the rx/tx queues */
5185 int
5186 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5187 {
5188         int ret;
5189
5190         if (on) {
5191                 /* enable rx queues before enabling tx queues */
5192                 ret = i40e_dev_switch_rx_queues(pf, on);
5193                 if (ret) {
5194                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5195                         return ret;
5196                 }
5197                 ret = i40e_dev_switch_tx_queues(pf, on);
5198         } else {
5199                 /* Stop tx queues before stopping rx queues */
5200                 ret = i40e_dev_switch_tx_queues(pf, on);
5201                 if (ret) {
5202                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5203                         return ret;
5204                 }
5205                 ret = i40e_dev_switch_rx_queues(pf, on);
5206         }
5207
5208         return ret;
5209 }
5210
5211 /* Initialize VSI for TX */
5212 static int
5213 i40e_dev_tx_init(struct i40e_pf *pf)
5214 {
5215         struct rte_eth_dev_data *data = pf->dev_data;
5216         uint16_t i;
5217         uint32_t ret = I40E_SUCCESS;
5218         struct i40e_tx_queue *txq;
5219
5220         for (i = 0; i < data->nb_tx_queues; i++) {
5221                 txq = data->tx_queues[i];
5222                 if (!txq || !txq->q_set)
5223                         continue;
5224                 ret = i40e_tx_queue_init(txq);
5225                 if (ret != I40E_SUCCESS)
5226                         break;
5227         }
5228         if (ret == I40E_SUCCESS)
5229                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5230                                      ->eth_dev);
5231
5232         return ret;
5233 }
5234
5235 /* Initialize VSI for RX */
5236 static int
5237 i40e_dev_rx_init(struct i40e_pf *pf)
5238 {
5239         struct rte_eth_dev_data *data = pf->dev_data;
5240         int ret = I40E_SUCCESS;
5241         uint16_t i;
5242         struct i40e_rx_queue *rxq;
5243
5244         i40e_pf_config_mq_rx(pf);
5245         for (i = 0; i < data->nb_rx_queues; i++) {
5246                 rxq = data->rx_queues[i];
5247                 if (!rxq || !rxq->q_set)
5248                         continue;
5249
5250                 ret = i40e_rx_queue_init(rxq);
5251                 if (ret != I40E_SUCCESS) {
5252                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5253                                     "initialization");
5254                         break;
5255                 }
5256         }
5257         if (ret == I40E_SUCCESS)
5258                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5259                                      ->eth_dev);
5260
5261         return ret;
5262 }
5263
5264 static int
5265 i40e_dev_rxtx_init(struct i40e_pf *pf)
5266 {
5267         int err;
5268
5269         err = i40e_dev_tx_init(pf);
5270         if (err) {
5271                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5272                 return err;
5273         }
5274         err = i40e_dev_rx_init(pf);
5275         if (err) {
5276                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5277                 return err;
5278         }
5279
5280         return err;
5281 }
5282
5283 static int
5284 i40e_vmdq_setup(struct rte_eth_dev *dev)
5285 {
5286         struct rte_eth_conf *conf = &dev->data->dev_conf;
5287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5288         int i, err, conf_vsis, j, loop;
5289         struct i40e_vsi *vsi;
5290         struct i40e_vmdq_info *vmdq_info;
5291         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5292         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5293
5294         /*
5295          * Disable interrupt to avoid message from VF. Furthermore, it will
5296          * avoid race condition in VSI creation/destroy.
5297          */
5298         i40e_pf_disable_irq0(hw);
5299
5300         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5301                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5302                 return -ENOTSUP;
5303         }
5304
5305         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5306         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5307                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5308                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5309                         pf->max_nb_vmdq_vsi);
5310                 return -ENOTSUP;
5311         }
5312
5313         if (pf->vmdq != NULL) {
5314                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5315                 return 0;
5316         }
5317
5318         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5319                                 sizeof(*vmdq_info) * conf_vsis, 0);
5320
5321         if (pf->vmdq == NULL) {
5322                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5323                 return -ENOMEM;
5324         }
5325
5326         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5327
5328         /* Create VMDQ VSI */
5329         for (i = 0; i < conf_vsis; i++) {
5330                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5331                                 vmdq_conf->enable_loop_back);
5332                 if (vsi == NULL) {
5333                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5334                         err = -1;
5335                         goto err_vsi_setup;
5336                 }
5337                 vmdq_info = &pf->vmdq[i];
5338                 vmdq_info->pf = pf;
5339                 vmdq_info->vsi = vsi;
5340         }
5341         pf->nb_cfg_vmdq_vsi = conf_vsis;
5342
5343         /* Configure Vlan */
5344         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5345         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5346                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5347                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5348                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5349                                         vmdq_conf->pool_map[i].vlan_id, j);
5350
5351                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5352                                                 vmdq_conf->pool_map[i].vlan_id);
5353                                 if (err) {
5354                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5355                                         err = -1;
5356                                         goto err_vsi_setup;
5357                                 }
5358                         }
5359                 }
5360         }
5361
5362         i40e_pf_enable_irq0(hw);
5363
5364         return 0;
5365
5366 err_vsi_setup:
5367         for (i = 0; i < conf_vsis; i++)
5368                 if (pf->vmdq[i].vsi == NULL)
5369                         break;
5370                 else
5371                         i40e_vsi_release(pf->vmdq[i].vsi);
5372
5373         rte_free(pf->vmdq);
5374         pf->vmdq = NULL;
5375         i40e_pf_enable_irq0(hw);
5376         return err;
5377 }
5378
5379 static void
5380 i40e_stat_update_32(struct i40e_hw *hw,
5381                    uint32_t reg,
5382                    bool offset_loaded,
5383                    uint64_t *offset,
5384                    uint64_t *stat)
5385 {
5386         uint64_t new_data;
5387
5388         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5389         if (!offset_loaded)
5390                 *offset = new_data;
5391
5392         if (new_data >= *offset)
5393                 *stat = (uint64_t)(new_data - *offset);
5394         else
5395                 *stat = (uint64_t)((new_data +
5396                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5397 }
5398
5399 static void
5400 i40e_stat_update_48(struct i40e_hw *hw,
5401                    uint32_t hireg,
5402                    uint32_t loreg,
5403                    bool offset_loaded,
5404                    uint64_t *offset,
5405                    uint64_t *stat)
5406 {
5407         uint64_t new_data;
5408
5409         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5410         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5411                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5412
5413         if (!offset_loaded)
5414                 *offset = new_data;
5415
5416         if (new_data >= *offset)
5417                 *stat = new_data - *offset;
5418         else
5419                 *stat = (uint64_t)((new_data +
5420                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5421
5422         *stat &= I40E_48_BIT_MASK;
5423 }
5424
5425 /* Disable IRQ0 */
5426 void
5427 i40e_pf_disable_irq0(struct i40e_hw *hw)
5428 {
5429         /* Disable all interrupt types */
5430         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5431         I40E_WRITE_FLUSH(hw);
5432 }
5433
5434 /* Enable IRQ0 */
5435 void
5436 i40e_pf_enable_irq0(struct i40e_hw *hw)
5437 {
5438         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5439                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5440                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5441                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5442         I40E_WRITE_FLUSH(hw);
5443 }
5444
5445 static void
5446 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5447 {
5448         /* read pending request and disable first */
5449         i40e_pf_disable_irq0(hw);
5450         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5451         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5452                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5453
5454         if (no_queue)
5455                 /* Link no queues with irq0 */
5456                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5457                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5458 }
5459
5460 static void
5461 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5462 {
5463         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5465         int i;
5466         uint16_t abs_vf_id;
5467         uint32_t index, offset, val;
5468
5469         if (!pf->vfs)
5470                 return;
5471         /**
5472          * Try to find which VF trigger a reset, use absolute VF id to access
5473          * since the reg is global register.
5474          */
5475         for (i = 0; i < pf->vf_num; i++) {
5476                 abs_vf_id = hw->func_caps.vf_base_id + i;
5477                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5478                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5479                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5480                 /* VFR event occured */
5481                 if (val & (0x1 << offset)) {
5482                         int ret;
5483
5484                         /* Clear the event first */
5485                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5486                                                         (0x1 << offset));
5487                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5488                         /**
5489                          * Only notify a VF reset event occured,
5490                          * don't trigger another SW reset
5491                          */
5492                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5493                         if (ret != I40E_SUCCESS)
5494                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5495                 }
5496         }
5497 }
5498
5499 static void
5500 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5501 {
5502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5503         struct i40e_virtchnl_pf_event event;
5504         int i;
5505
5506         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5507         event.event_data.link_event.link_status =
5508                 dev->data->dev_link.link_status;
5509         event.event_data.link_event.link_speed =
5510                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5511
5512         for (i = 0; i < pf->vf_num; i++)
5513                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5514                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5515 }
5516
5517 static void
5518 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5519 {
5520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521         struct i40e_arq_event_info info;
5522         uint16_t pending, opcode;
5523         int ret;
5524
5525         info.buf_len = I40E_AQ_BUF_SZ;
5526         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5527         if (!info.msg_buf) {
5528                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5529                 return;
5530         }
5531
5532         pending = 1;
5533         while (pending) {
5534                 ret = i40e_clean_arq_element(hw, &info, &pending);
5535
5536                 if (ret != I40E_SUCCESS) {
5537                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5538                                     "aq_err: %u", hw->aq.asq_last_status);
5539                         break;
5540                 }
5541                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5542
5543                 switch (opcode) {
5544                 case i40e_aqc_opc_send_msg_to_pf:
5545                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5546                         i40e_pf_host_handle_vf_msg(dev,
5547                                         rte_le_to_cpu_16(info.desc.retval),
5548                                         rte_le_to_cpu_32(info.desc.cookie_high),
5549                                         rte_le_to_cpu_32(info.desc.cookie_low),
5550                                         info.msg_buf,
5551                                         info.msg_len);
5552                         break;
5553                 case i40e_aqc_opc_get_link_status:
5554                         ret = i40e_dev_link_update(dev, 0);
5555                         if (!ret) {
5556                                 i40e_notify_all_vfs_link_status(dev);
5557                                 _rte_eth_dev_callback_process(dev,
5558                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5559                         }
5560                         break;
5561                 default:
5562                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5563                                     opcode);
5564                         break;
5565                 }
5566         }
5567         rte_free(info.msg_buf);
5568 }
5569
5570 /**
5571  * Interrupt handler triggered by NIC  for handling
5572  * specific interrupt.
5573  *
5574  * @param handle
5575  *  Pointer to interrupt handle.
5576  * @param param
5577  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5578  *
5579  * @return
5580  *  void
5581  */
5582 static void
5583 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5584                            void *param)
5585 {
5586         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588         uint32_t icr0;
5589
5590         /* Disable interrupt */
5591         i40e_pf_disable_irq0(hw);
5592
5593         /* read out interrupt causes */
5594         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5595
5596         /* No interrupt event indicated */
5597         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5598                 PMD_DRV_LOG(INFO, "No interrupt event");
5599                 goto done;
5600         }
5601 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5602         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5603                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5604         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5605                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5606         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5607                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5608         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5609                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5610         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5611                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5612         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5613                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5614         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5615                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5616 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5617
5618         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5619                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5620                 i40e_dev_handle_vfr_event(dev);
5621         }
5622         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5623                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5624                 i40e_dev_handle_aq_msg(dev);
5625         }
5626
5627 done:
5628         /* Enable interrupt */
5629         i40e_pf_enable_irq0(hw);
5630         rte_intr_enable(intr_handle);
5631 }
5632
5633 static int
5634 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5635                          struct i40e_macvlan_filter *filter,
5636                          int total)
5637 {
5638         int ele_num, ele_buff_size;
5639         int num, actual_num, i;
5640         uint16_t flags;
5641         int ret = I40E_SUCCESS;
5642         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5643         struct i40e_aqc_add_macvlan_element_data *req_list;
5644
5645         if (filter == NULL  || total == 0)
5646                 return I40E_ERR_PARAM;
5647         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5648         ele_buff_size = hw->aq.asq_buf_size;
5649
5650         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5651         if (req_list == NULL) {
5652                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5653                 return I40E_ERR_NO_MEMORY;
5654         }
5655
5656         num = 0;
5657         do {
5658                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5659                 memset(req_list, 0, ele_buff_size);
5660
5661                 for (i = 0; i < actual_num; i++) {
5662                         (void)rte_memcpy(req_list[i].mac_addr,
5663                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5664                         req_list[i].vlan_tag =
5665                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5666
5667                         switch (filter[num + i].filter_type) {
5668                         case RTE_MAC_PERFECT_MATCH:
5669                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5670                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5671                                 break;
5672                         case RTE_MACVLAN_PERFECT_MATCH:
5673                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5674                                 break;
5675                         case RTE_MAC_HASH_MATCH:
5676                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5677                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5678                                 break;
5679                         case RTE_MACVLAN_HASH_MATCH:
5680                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5681                                 break;
5682                         default:
5683                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5684                                 ret = I40E_ERR_PARAM;
5685                                 goto DONE;
5686                         }
5687
5688                         req_list[i].queue_number = 0;
5689
5690                         req_list[i].flags = rte_cpu_to_le_16(flags);
5691                 }
5692
5693                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5694                                                 actual_num, NULL);
5695                 if (ret != I40E_SUCCESS) {
5696                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5697                         goto DONE;
5698                 }
5699                 num += actual_num;
5700         } while (num < total);
5701
5702 DONE:
5703         rte_free(req_list);
5704         return ret;
5705 }
5706
5707 static int
5708 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5709                             struct i40e_macvlan_filter *filter,
5710                             int total)
5711 {
5712         int ele_num, ele_buff_size;
5713         int num, actual_num, i;
5714         uint16_t flags;
5715         int ret = I40E_SUCCESS;
5716         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5717         struct i40e_aqc_remove_macvlan_element_data *req_list;
5718
5719         if (filter == NULL  || total == 0)
5720                 return I40E_ERR_PARAM;
5721
5722         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5723         ele_buff_size = hw->aq.asq_buf_size;
5724
5725         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5726         if (req_list == NULL) {
5727                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5728                 return I40E_ERR_NO_MEMORY;
5729         }
5730
5731         num = 0;
5732         do {
5733                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5734                 memset(req_list, 0, ele_buff_size);
5735
5736                 for (i = 0; i < actual_num; i++) {
5737                         (void)rte_memcpy(req_list[i].mac_addr,
5738                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5739                         req_list[i].vlan_tag =
5740                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5741
5742                         switch (filter[num + i].filter_type) {
5743                         case RTE_MAC_PERFECT_MATCH:
5744                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5745                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5746                                 break;
5747                         case RTE_MACVLAN_PERFECT_MATCH:
5748                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5749                                 break;
5750                         case RTE_MAC_HASH_MATCH:
5751                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5752                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5753                                 break;
5754                         case RTE_MACVLAN_HASH_MATCH:
5755                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5756                                 break;
5757                         default:
5758                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5759                                 ret = I40E_ERR_PARAM;
5760                                 goto DONE;
5761                         }
5762                         req_list[i].flags = rte_cpu_to_le_16(flags);
5763                 }
5764
5765                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5766                                                 actual_num, NULL);
5767                 if (ret != I40E_SUCCESS) {
5768                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5769                         goto DONE;
5770                 }
5771                 num += actual_num;
5772         } while (num < total);
5773
5774 DONE:
5775         rte_free(req_list);
5776         return ret;
5777 }
5778
5779 /* Find out specific MAC filter */
5780 static struct i40e_mac_filter *
5781 i40e_find_mac_filter(struct i40e_vsi *vsi,
5782                          struct ether_addr *macaddr)
5783 {
5784         struct i40e_mac_filter *f;
5785
5786         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5787                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5788                         return f;
5789         }
5790
5791         return NULL;
5792 }
5793
5794 static bool
5795 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5796                          uint16_t vlan_id)
5797 {
5798         uint32_t vid_idx, vid_bit;
5799
5800         if (vlan_id > ETH_VLAN_ID_MAX)
5801                 return 0;
5802
5803         vid_idx = I40E_VFTA_IDX(vlan_id);
5804         vid_bit = I40E_VFTA_BIT(vlan_id);
5805
5806         if (vsi->vfta[vid_idx] & vid_bit)
5807                 return 1;
5808         else
5809                 return 0;
5810 }
5811
5812 static void
5813 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5814                          uint16_t vlan_id, bool on)
5815 {
5816         uint32_t vid_idx, vid_bit;
5817
5818         if (vlan_id > ETH_VLAN_ID_MAX)
5819                 return;
5820
5821         vid_idx = I40E_VFTA_IDX(vlan_id);
5822         vid_bit = I40E_VFTA_BIT(vlan_id);
5823
5824         if (on)
5825                 vsi->vfta[vid_idx] |= vid_bit;
5826         else
5827                 vsi->vfta[vid_idx] &= ~vid_bit;
5828 }
5829
5830 /**
5831  * Find all vlan options for specific mac addr,
5832  * return with actual vlan found.
5833  */
5834 static inline int
5835 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5836                            struct i40e_macvlan_filter *mv_f,
5837                            int num, struct ether_addr *addr)
5838 {
5839         int i;
5840         uint32_t j, k;
5841
5842         /**
5843          * Not to use i40e_find_vlan_filter to decrease the loop time,
5844          * although the code looks complex.
5845           */
5846         if (num < vsi->vlan_num)
5847                 return I40E_ERR_PARAM;
5848
5849         i = 0;
5850         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5851                 if (vsi->vfta[j]) {
5852                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5853                                 if (vsi->vfta[j] & (1 << k)) {
5854                                         if (i > num - 1) {
5855                                                 PMD_DRV_LOG(ERR, "vlan number "
5856                                                             "not match");
5857                                                 return I40E_ERR_PARAM;
5858                                         }
5859                                         (void)rte_memcpy(&mv_f[i].macaddr,
5860                                                         addr, ETH_ADDR_LEN);
5861                                         mv_f[i].vlan_id =
5862                                                 j * I40E_UINT32_BIT_SIZE + k;
5863                                         i++;
5864                                 }
5865                         }
5866                 }
5867         }
5868         return I40E_SUCCESS;
5869 }
5870
5871 static inline int
5872 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5873                            struct i40e_macvlan_filter *mv_f,
5874                            int num,
5875                            uint16_t vlan)
5876 {
5877         int i = 0;
5878         struct i40e_mac_filter *f;
5879
5880         if (num < vsi->mac_num)
5881                 return I40E_ERR_PARAM;
5882
5883         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5884                 if (i > num - 1) {
5885                         PMD_DRV_LOG(ERR, "buffer number not match");
5886                         return I40E_ERR_PARAM;
5887                 }
5888                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5889                                 ETH_ADDR_LEN);
5890                 mv_f[i].vlan_id = vlan;
5891                 mv_f[i].filter_type = f->mac_info.filter_type;
5892                 i++;
5893         }
5894
5895         return I40E_SUCCESS;
5896 }
5897
5898 static int
5899 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5900 {
5901         int i, num;
5902         struct i40e_mac_filter *f;
5903         struct i40e_macvlan_filter *mv_f;
5904         int ret = I40E_SUCCESS;
5905
5906         if (vsi == NULL || vsi->mac_num == 0)
5907                 return I40E_ERR_PARAM;
5908
5909         /* Case that no vlan is set */
5910         if (vsi->vlan_num == 0)
5911                 num = vsi->mac_num;
5912         else
5913                 num = vsi->mac_num * vsi->vlan_num;
5914
5915         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5916         if (mv_f == NULL) {
5917                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5918                 return I40E_ERR_NO_MEMORY;
5919         }
5920
5921         i = 0;
5922         if (vsi->vlan_num == 0) {
5923                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5924                         (void)rte_memcpy(&mv_f[i].macaddr,
5925                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5926                         mv_f[i].vlan_id = 0;
5927                         i++;
5928                 }
5929         } else {
5930                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5931                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5932                                         vsi->vlan_num, &f->mac_info.mac_addr);
5933                         if (ret != I40E_SUCCESS)
5934                                 goto DONE;
5935                         i += vsi->vlan_num;
5936                 }
5937         }
5938
5939         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5940 DONE:
5941         rte_free(mv_f);
5942
5943         return ret;
5944 }
5945
5946 int
5947 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5948 {
5949         struct i40e_macvlan_filter *mv_f;
5950         int mac_num;
5951         int ret = I40E_SUCCESS;
5952
5953         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5954                 return I40E_ERR_PARAM;
5955
5956         /* If it's already set, just return */
5957         if (i40e_find_vlan_filter(vsi,vlan))
5958                 return I40E_SUCCESS;
5959
5960         mac_num = vsi->mac_num;
5961
5962         if (mac_num == 0) {
5963                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5964                 return I40E_ERR_PARAM;
5965         }
5966
5967         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5968
5969         if (mv_f == NULL) {
5970                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5971                 return I40E_ERR_NO_MEMORY;
5972         }
5973
5974         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5975
5976         if (ret != I40E_SUCCESS)
5977                 goto DONE;
5978
5979         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5980
5981         if (ret != I40E_SUCCESS)
5982                 goto DONE;
5983
5984         i40e_set_vlan_filter(vsi, vlan, 1);
5985
5986         vsi->vlan_num++;
5987         ret = I40E_SUCCESS;
5988 DONE:
5989         rte_free(mv_f);
5990         return ret;
5991 }
5992
5993 int
5994 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5995 {
5996         struct i40e_macvlan_filter *mv_f;
5997         int mac_num;
5998         int ret = I40E_SUCCESS;
5999
6000         /**
6001          * Vlan 0 is the generic filter for untagged packets
6002          * and can't be removed.
6003          */
6004         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6005                 return I40E_ERR_PARAM;
6006
6007         /* If can't find it, just return */
6008         if (!i40e_find_vlan_filter(vsi, vlan))
6009                 return I40E_ERR_PARAM;
6010
6011         mac_num = vsi->mac_num;
6012
6013         if (mac_num == 0) {
6014                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6015                 return I40E_ERR_PARAM;
6016         }
6017
6018         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6019
6020         if (mv_f == NULL) {
6021                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6022                 return I40E_ERR_NO_MEMORY;
6023         }
6024
6025         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6026
6027         if (ret != I40E_SUCCESS)
6028                 goto DONE;
6029
6030         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6031
6032         if (ret != I40E_SUCCESS)
6033                 goto DONE;
6034
6035         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6036         if (vsi->vlan_num == 1) {
6037                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6038                 if (ret != I40E_SUCCESS)
6039                         goto DONE;
6040
6041                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6042                 if (ret != I40E_SUCCESS)
6043                         goto DONE;
6044         }
6045
6046         i40e_set_vlan_filter(vsi, vlan, 0);
6047
6048         vsi->vlan_num--;
6049         ret = I40E_SUCCESS;
6050 DONE:
6051         rte_free(mv_f);
6052         return ret;
6053 }
6054
6055 int
6056 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6057 {
6058         struct i40e_mac_filter *f;
6059         struct i40e_macvlan_filter *mv_f;
6060         int i, vlan_num = 0;
6061         int ret = I40E_SUCCESS;
6062
6063         /* If it's add and we've config it, return */
6064         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6065         if (f != NULL)
6066                 return I40E_SUCCESS;
6067         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6068                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6069
6070                 /**
6071                  * If vlan_num is 0, that's the first time to add mac,
6072                  * set mask for vlan_id 0.
6073                  */
6074                 if (vsi->vlan_num == 0) {
6075                         i40e_set_vlan_filter(vsi, 0, 1);
6076                         vsi->vlan_num = 1;
6077                 }
6078                 vlan_num = vsi->vlan_num;
6079         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6080                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6081                 vlan_num = 1;
6082
6083         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6084         if (mv_f == NULL) {
6085                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6086                 return I40E_ERR_NO_MEMORY;
6087         }
6088
6089         for (i = 0; i < vlan_num; i++) {
6090                 mv_f[i].filter_type = mac_filter->filter_type;
6091                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6092                                 ETH_ADDR_LEN);
6093         }
6094
6095         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6096                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6097                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6098                                         &mac_filter->mac_addr);
6099                 if (ret != I40E_SUCCESS)
6100                         goto DONE;
6101         }
6102
6103         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6104         if (ret != I40E_SUCCESS)
6105                 goto DONE;
6106
6107         /* Add the mac addr into mac list */
6108         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6109         if (f == NULL) {
6110                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6111                 ret = I40E_ERR_NO_MEMORY;
6112                 goto DONE;
6113         }
6114         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6115                         ETH_ADDR_LEN);
6116         f->mac_info.filter_type = mac_filter->filter_type;
6117         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6118         vsi->mac_num++;
6119
6120         ret = I40E_SUCCESS;
6121 DONE:
6122         rte_free(mv_f);
6123
6124         return ret;
6125 }
6126
6127 int
6128 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6129 {
6130         struct i40e_mac_filter *f;
6131         struct i40e_macvlan_filter *mv_f;
6132         int i, vlan_num;
6133         enum rte_mac_filter_type filter_type;
6134         int ret = I40E_SUCCESS;
6135
6136         /* Can't find it, return an error */
6137         f = i40e_find_mac_filter(vsi, addr);
6138         if (f == NULL)
6139                 return I40E_ERR_PARAM;
6140
6141         vlan_num = vsi->vlan_num;
6142         filter_type = f->mac_info.filter_type;
6143         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6144                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6145                 if (vlan_num == 0) {
6146                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6147                         return I40E_ERR_PARAM;
6148                 }
6149         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6150                         filter_type == RTE_MAC_HASH_MATCH)
6151                 vlan_num = 1;
6152
6153         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6154         if (mv_f == NULL) {
6155                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6156                 return I40E_ERR_NO_MEMORY;
6157         }
6158
6159         for (i = 0; i < vlan_num; i++) {
6160                 mv_f[i].filter_type = filter_type;
6161                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6162                                 ETH_ADDR_LEN);
6163         }
6164         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6165                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6166                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6167                 if (ret != I40E_SUCCESS)
6168                         goto DONE;
6169         }
6170
6171         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6172         if (ret != I40E_SUCCESS)
6173                 goto DONE;
6174
6175         /* Remove the mac addr into mac list */
6176         TAILQ_REMOVE(&vsi->mac_list, f, next);
6177         rte_free(f);
6178         vsi->mac_num--;
6179
6180         ret = I40E_SUCCESS;
6181 DONE:
6182         rte_free(mv_f);
6183         return ret;
6184 }
6185
6186 /* Configure hash enable flags for RSS */
6187 uint64_t
6188 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6189 {
6190         uint64_t hena = 0;
6191
6192         if (!flags)
6193                 return hena;
6194
6195         if (flags & ETH_RSS_FRAG_IPV4)
6196                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6197         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6198                 if (type == I40E_MAC_X722) {
6199                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6200                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6201                 } else
6202                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6203         }
6204         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6205                 if (type == I40E_MAC_X722) {
6206                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6207                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6208                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6209                 } else
6210                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6211         }
6212         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6213                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6214         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6215                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6216         if (flags & ETH_RSS_FRAG_IPV6)
6217                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6218         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6219                 if (type == I40E_MAC_X722) {
6220                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6221                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6222                 } else
6223                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6224         }
6225         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6226                 if (type == I40E_MAC_X722) {
6227                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6228                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6229                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6230                 } else
6231                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6232         }
6233         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6234                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6235         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6236                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6237         if (flags & ETH_RSS_L2_PAYLOAD)
6238                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6239
6240         return hena;
6241 }
6242
6243 /* Parse the hash enable flags */
6244 uint64_t
6245 i40e_parse_hena(uint64_t flags)
6246 {
6247         uint64_t rss_hf = 0;
6248
6249         if (!flags)
6250                 return rss_hf;
6251         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6252                 rss_hf |= ETH_RSS_FRAG_IPV4;
6253         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6254                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6255 #ifdef X722_SUPPORT
6256         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6257                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6258 #endif
6259         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6260                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6261 #ifdef X722_SUPPORT
6262         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6263                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6264         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6265                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6266 #endif
6267         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6268                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6269         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6270                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6271         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6272                 rss_hf |= ETH_RSS_FRAG_IPV6;
6273         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6274                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6275 #ifdef X722_SUPPORT
6276         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6277                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6278 #endif
6279         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6280                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6281 #ifdef X722_SUPPORT
6282         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6283                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6284         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6285                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6286 #endif
6287         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6288                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6289         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6290                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6291         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6292                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6293
6294         return rss_hf;
6295 }
6296
6297 /* Disable RSS */
6298 static void
6299 i40e_pf_disable_rss(struct i40e_pf *pf)
6300 {
6301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6302         uint64_t hena;
6303
6304         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6305         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6306         if (hw->mac.type == I40E_MAC_X722)
6307                 hena &= ~I40E_RSS_HENA_ALL_X722;
6308         else
6309                 hena &= ~I40E_RSS_HENA_ALL;
6310         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6311         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6312         I40E_WRITE_FLUSH(hw);
6313 }
6314
6315 static int
6316 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6317 {
6318         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6319         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6320         int ret = 0;
6321
6322         if (!key || key_len == 0) {
6323                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6324                 return 0;
6325         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6326                 sizeof(uint32_t)) {
6327                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6328                 return -EINVAL;
6329         }
6330
6331         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6332                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6333                         (struct i40e_aqc_get_set_rss_key_data *)key;
6334
6335                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6336                 if (ret)
6337                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6338                                      "via AQ");
6339         } else {
6340                 uint32_t *hash_key = (uint32_t *)key;
6341                 uint16_t i;
6342
6343                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6344                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6345                 I40E_WRITE_FLUSH(hw);
6346         }
6347
6348         return ret;
6349 }
6350
6351 static int
6352 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6353 {
6354         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6355         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6356         int ret;
6357
6358         if (!key || !key_len)
6359                 return -EINVAL;
6360
6361         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6362                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6363                         (struct i40e_aqc_get_set_rss_key_data *)key);
6364                 if (ret) {
6365                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6366                         return ret;
6367                 }
6368         } else {
6369                 uint32_t *key_dw = (uint32_t *)key;
6370                 uint16_t i;
6371
6372                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6373                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6374         }
6375         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6376
6377         return 0;
6378 }
6379
6380 static int
6381 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6382 {
6383         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6384         uint64_t rss_hf;
6385         uint64_t hena;
6386         int ret;
6387
6388         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6389                                rss_conf->rss_key_len);
6390         if (ret)
6391                 return ret;
6392
6393         rss_hf = rss_conf->rss_hf;
6394         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6395         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6396         if (hw->mac.type == I40E_MAC_X722)
6397                 hena &= ~I40E_RSS_HENA_ALL_X722;
6398         else
6399                 hena &= ~I40E_RSS_HENA_ALL;
6400         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6401         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6402         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6403         I40E_WRITE_FLUSH(hw);
6404
6405         return 0;
6406 }
6407
6408 static int
6409 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6410                          struct rte_eth_rss_conf *rss_conf)
6411 {
6412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6414         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6415         uint64_t hena;
6416
6417         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6418         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6419         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6420                  ? I40E_RSS_HENA_ALL_X722
6421                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6422                 if (rss_hf != 0) /* Enable RSS */
6423                         return -EINVAL;
6424                 return 0; /* Nothing to do */
6425         }
6426         /* RSS enabled */
6427         if (rss_hf == 0) /* Disable RSS */
6428                 return -EINVAL;
6429
6430         return i40e_hw_rss_hash_set(pf, rss_conf);
6431 }
6432
6433 static int
6434 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6435                            struct rte_eth_rss_conf *rss_conf)
6436 {
6437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6439         uint64_t hena;
6440
6441         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6442                          &rss_conf->rss_key_len);
6443
6444         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6445         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6446         rss_conf->rss_hf = i40e_parse_hena(hena);
6447
6448         return 0;
6449 }
6450
6451 static int
6452 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6453 {
6454         switch (filter_type) {
6455         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6456                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6457                 break;
6458         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6459                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6460                 break;
6461         case RTE_TUNNEL_FILTER_IMAC_TENID:
6462                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6463                 break;
6464         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6465                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6466                 break;
6467         case ETH_TUNNEL_FILTER_IMAC:
6468                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6469                 break;
6470         case ETH_TUNNEL_FILTER_OIP:
6471                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6472                 break;
6473         case ETH_TUNNEL_FILTER_IIP:
6474                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6475                 break;
6476         default:
6477                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6478                 return -EINVAL;
6479         }
6480
6481         return 0;
6482 }
6483
6484 static int
6485 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6486                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6487                         uint8_t add)
6488 {
6489         uint16_t ip_type;
6490         uint32_t ipv4_addr;
6491         uint8_t i, tun_type = 0;
6492         /* internal varialbe to convert ipv6 byte order */
6493         uint32_t convert_ipv6[4];
6494         int val, ret = 0;
6495         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6496         struct i40e_vsi *vsi = pf->main_vsi;
6497         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6498         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6499
6500         cld_filter = rte_zmalloc("tunnel_filter",
6501                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6502                 0);
6503
6504         if (NULL == cld_filter) {
6505                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6506                 return -EINVAL;
6507         }
6508         pfilter = cld_filter;
6509
6510         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6511         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6512
6513         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6514         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6515                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6516                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6517                 rte_memcpy(&pfilter->ipaddr.v4.data,
6518                                 &rte_cpu_to_le_32(ipv4_addr),
6519                                 sizeof(pfilter->ipaddr.v4.data));
6520         } else {
6521                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6522                 for (i = 0; i < 4; i++) {
6523                         convert_ipv6[i] =
6524                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6525                 }
6526                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6527                                 sizeof(pfilter->ipaddr.v6.data));
6528         }
6529
6530         /* check tunneled type */
6531         switch (tunnel_filter->tunnel_type) {
6532         case RTE_TUNNEL_TYPE_VXLAN:
6533                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6534                 break;
6535         case RTE_TUNNEL_TYPE_NVGRE:
6536                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6537                 break;
6538         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6539                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6540                 break;
6541         default:
6542                 /* Other tunnel types is not supported. */
6543                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6544                 rte_free(cld_filter);
6545                 return -EINVAL;
6546         }
6547
6548         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6549                                                 &pfilter->flags);
6550         if (val < 0) {
6551                 rte_free(cld_filter);
6552                 return -EINVAL;
6553         }
6554
6555         pfilter->flags |= rte_cpu_to_le_16(
6556                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6557                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6558         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6559         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6560
6561         if (add)
6562                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6563         else
6564                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6565                                                 cld_filter, 1);
6566
6567         rte_free(cld_filter);
6568         return ret;
6569 }
6570
6571 static int
6572 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6573 {
6574         uint8_t i;
6575
6576         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6577                 if (pf->vxlan_ports[i] == port)
6578                         return i;
6579         }
6580
6581         return -1;
6582 }
6583
6584 static int
6585 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6586 {
6587         int  idx, ret;
6588         uint8_t filter_idx;
6589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6590
6591         idx = i40e_get_vxlan_port_idx(pf, port);
6592
6593         /* Check if port already exists */
6594         if (idx >= 0) {
6595                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6596                 return -EINVAL;
6597         }
6598
6599         /* Now check if there is space to add the new port */
6600         idx = i40e_get_vxlan_port_idx(pf, 0);
6601         if (idx < 0) {
6602                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6603                         "not adding port %d", port);
6604                 return -ENOSPC;
6605         }
6606
6607         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6608                                         &filter_idx, NULL);
6609         if (ret < 0) {
6610                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6611                 return -1;
6612         }
6613
6614         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6615                          port,  filter_idx);
6616
6617         /* New port: add it and mark its index in the bitmap */
6618         pf->vxlan_ports[idx] = port;
6619         pf->vxlan_bitmap |= (1 << idx);
6620
6621         if (!(pf->flags & I40E_FLAG_VXLAN))
6622                 pf->flags |= I40E_FLAG_VXLAN;
6623
6624         return 0;
6625 }
6626
6627 static int
6628 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6629 {
6630         int idx;
6631         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6632
6633         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6634                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6635                 return -EINVAL;
6636         }
6637
6638         idx = i40e_get_vxlan_port_idx(pf, port);
6639
6640         if (idx < 0) {
6641                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6642                 return -EINVAL;
6643         }
6644
6645         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6646                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6647                 return -1;
6648         }
6649
6650         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6651                         port, idx);
6652
6653         pf->vxlan_ports[idx] = 0;
6654         pf->vxlan_bitmap &= ~(1 << idx);
6655
6656         if (!pf->vxlan_bitmap)
6657                 pf->flags &= ~I40E_FLAG_VXLAN;
6658
6659         return 0;
6660 }
6661
6662 /* Add UDP tunneling port */
6663 static int
6664 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6665                              struct rte_eth_udp_tunnel *udp_tunnel)
6666 {
6667         int ret = 0;
6668         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6669
6670         if (udp_tunnel == NULL)
6671                 return -EINVAL;
6672
6673         switch (udp_tunnel->prot_type) {
6674         case RTE_TUNNEL_TYPE_VXLAN:
6675                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6676                 break;
6677
6678         case RTE_TUNNEL_TYPE_GENEVE:
6679         case RTE_TUNNEL_TYPE_TEREDO:
6680                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6681                 ret = -1;
6682                 break;
6683
6684         default:
6685                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6686                 ret = -1;
6687                 break;
6688         }
6689
6690         return ret;
6691 }
6692
6693 /* Remove UDP tunneling port */
6694 static int
6695 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6696                              struct rte_eth_udp_tunnel *udp_tunnel)
6697 {
6698         int ret = 0;
6699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6700
6701         if (udp_tunnel == NULL)
6702                 return -EINVAL;
6703
6704         switch (udp_tunnel->prot_type) {
6705         case RTE_TUNNEL_TYPE_VXLAN:
6706                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6707                 break;
6708         case RTE_TUNNEL_TYPE_GENEVE:
6709         case RTE_TUNNEL_TYPE_TEREDO:
6710                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6711                 ret = -1;
6712                 break;
6713         default:
6714                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6715                 ret = -1;
6716                 break;
6717         }
6718
6719         return ret;
6720 }
6721
6722 /* Calculate the maximum number of contiguous PF queues that are configured */
6723 static int
6724 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6725 {
6726         struct rte_eth_dev_data *data = pf->dev_data;
6727         int i, num;
6728         struct i40e_rx_queue *rxq;
6729
6730         num = 0;
6731         for (i = 0; i < pf->lan_nb_qps; i++) {
6732                 rxq = data->rx_queues[i];
6733                 if (rxq && rxq->q_set)
6734                         num++;
6735                 else
6736                         break;
6737         }
6738
6739         return num;
6740 }
6741
6742 /* Configure RSS */
6743 static int
6744 i40e_pf_config_rss(struct i40e_pf *pf)
6745 {
6746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6747         struct rte_eth_rss_conf rss_conf;
6748         uint32_t i, lut = 0;
6749         uint16_t j, num;
6750
6751         /*
6752          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6753          * It's necessary to calulate the actual PF queues that are configured.
6754          */
6755         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6756                 num = i40e_pf_calc_configured_queues_num(pf);
6757         else
6758                 num = pf->dev_data->nb_rx_queues;
6759
6760         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6761         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6762                         num);
6763
6764         if (num == 0) {
6765                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6766                 return -ENOTSUP;
6767         }
6768
6769         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6770                 if (j == num)
6771                         j = 0;
6772                 lut = (lut << 8) | (j & ((0x1 <<
6773                         hw->func_caps.rss_table_entry_width) - 1));
6774                 if ((i & 3) == 3)
6775                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6776         }
6777
6778         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6779         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6780                 i40e_pf_disable_rss(pf);
6781                 return 0;
6782         }
6783         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6784                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6785                 /* Random default keys */
6786                 static uint32_t rss_key_default[] = {0x6b793944,
6787                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6788                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6789                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6790
6791                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6792                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6793                                                         sizeof(uint32_t);
6794         }
6795
6796         return i40e_hw_rss_hash_set(pf, &rss_conf);
6797 }
6798
6799 static int
6800 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6801                                struct rte_eth_tunnel_filter_conf *filter)
6802 {
6803         if (pf == NULL || filter == NULL) {
6804                 PMD_DRV_LOG(ERR, "Invalid parameter");
6805                 return -EINVAL;
6806         }
6807
6808         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6809                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6810                 return -EINVAL;
6811         }
6812
6813         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6814                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6815                 return -EINVAL;
6816         }
6817
6818         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6819                 (is_zero_ether_addr(&filter->outer_mac))) {
6820                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6821                 return -EINVAL;
6822         }
6823
6824         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6825                 (is_zero_ether_addr(&filter->inner_mac))) {
6826                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6827                 return -EINVAL;
6828         }
6829
6830         return 0;
6831 }
6832
6833 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6834 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6835 static int
6836 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6837 {
6838         uint32_t val, reg;
6839         int ret = -EINVAL;
6840
6841         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6842         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6843
6844         if (len == 3) {
6845                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6846         } else if (len == 4) {
6847                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6848         } else {
6849                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6850                 return ret;
6851         }
6852
6853         if (reg != val) {
6854                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6855                                                    reg, NULL);
6856                 if (ret != 0)
6857                         return ret;
6858         } else {
6859                 ret = 0;
6860         }
6861         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6862                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6863
6864         return ret;
6865 }
6866
6867 static int
6868 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6869 {
6870         int ret = -EINVAL;
6871
6872         if (!hw || !cfg)
6873                 return -EINVAL;
6874
6875         switch (cfg->cfg_type) {
6876         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6877                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6878                 break;
6879         default:
6880                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6881                 break;
6882         }
6883
6884         return ret;
6885 }
6886
6887 static int
6888 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6889                                enum rte_filter_op filter_op,
6890                                void *arg)
6891 {
6892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893         int ret = I40E_ERR_PARAM;
6894
6895         switch (filter_op) {
6896         case RTE_ETH_FILTER_SET:
6897                 ret = i40e_dev_global_config_set(hw,
6898                         (struct rte_eth_global_cfg *)arg);
6899                 break;
6900         default:
6901                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6902                 break;
6903         }
6904
6905         return ret;
6906 }
6907
6908 static int
6909 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6910                           enum rte_filter_op filter_op,
6911                           void *arg)
6912 {
6913         struct rte_eth_tunnel_filter_conf *filter;
6914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6915         int ret = I40E_SUCCESS;
6916
6917         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6918
6919         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6920                 return I40E_ERR_PARAM;
6921
6922         switch (filter_op) {
6923         case RTE_ETH_FILTER_NOP:
6924                 if (!(pf->flags & I40E_FLAG_VXLAN))
6925                         ret = I40E_NOT_SUPPORTED;
6926                 break;
6927         case RTE_ETH_FILTER_ADD:
6928                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6929                 break;
6930         case RTE_ETH_FILTER_DELETE:
6931                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6932                 break;
6933         default:
6934                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6935                 ret = I40E_ERR_PARAM;
6936                 break;
6937         }
6938
6939         return ret;
6940 }
6941
6942 static int
6943 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6944 {
6945         int ret = 0;
6946         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6947
6948         /* RSS setup */
6949         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6950                 ret = i40e_pf_config_rss(pf);
6951         else
6952                 i40e_pf_disable_rss(pf);
6953
6954         return ret;
6955 }
6956
6957 /* Get the symmetric hash enable configurations per port */
6958 static void
6959 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6960 {
6961         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6962
6963         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6964 }
6965
6966 /* Set the symmetric hash enable configurations per port */
6967 static void
6968 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6969 {
6970         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6971
6972         if (enable > 0) {
6973                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6974                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6975                                                         "been enabled");
6976                         return;
6977                 }
6978                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6979         } else {
6980                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6981                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6982                                                         "been disabled");
6983                         return;
6984                 }
6985                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6986         }
6987         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6988         I40E_WRITE_FLUSH(hw);
6989 }
6990
6991 /*
6992  * Get global configurations of hash function type and symmetric hash enable
6993  * per flow type (pctype). Note that global configuration means it affects all
6994  * the ports on the same NIC.
6995  */
6996 static int
6997 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6998                                    struct rte_eth_hash_global_conf *g_cfg)
6999 {
7000         uint32_t reg, mask = I40E_FLOW_TYPES;
7001         uint16_t i;
7002         enum i40e_filter_pctype pctype;
7003
7004         memset(g_cfg, 0, sizeof(*g_cfg));
7005         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7006         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7007                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7008         else
7009                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7010         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7011                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7012
7013         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7014                 if (!(mask & (1UL << i)))
7015                         continue;
7016                 mask &= ~(1UL << i);
7017                 /* Bit set indicats the coresponding flow type is supported */
7018                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7019                 /* if flowtype is invalid, continue */
7020                 if (!I40E_VALID_FLOW(i))
7021                         continue;
7022                 pctype = i40e_flowtype_to_pctype(i);
7023                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7024                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7025                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7026         }
7027
7028         return 0;
7029 }
7030
7031 static int
7032 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7033 {
7034         uint32_t i;
7035         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7036
7037         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7038                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7039                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7040                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7041                                                 g_cfg->hash_func);
7042                 return -EINVAL;
7043         }
7044
7045         /*
7046          * As i40e supports less than 32 flow types, only first 32 bits need to
7047          * be checked.
7048          */
7049         mask0 = g_cfg->valid_bit_mask[0];
7050         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7051                 if (i == 0) {
7052                         /* Check if any unsupported flow type configured */
7053                         if ((mask0 | i40e_mask) ^ i40e_mask)
7054                                 goto mask_err;
7055                 } else {
7056                         if (g_cfg->valid_bit_mask[i])
7057                                 goto mask_err;
7058                 }
7059         }
7060
7061         return 0;
7062
7063 mask_err:
7064         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7065
7066         return -EINVAL;
7067 }
7068
7069 /*
7070  * Set global configurations of hash function type and symmetric hash enable
7071  * per flow type (pctype). Note any modifying global configuration will affect
7072  * all the ports on the same NIC.
7073  */
7074 static int
7075 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7076                                    struct rte_eth_hash_global_conf *g_cfg)
7077 {
7078         int ret;
7079         uint16_t i;
7080         uint32_t reg;
7081         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7082         enum i40e_filter_pctype pctype;
7083
7084         /* Check the input parameters */
7085         ret = i40e_hash_global_config_check(g_cfg);
7086         if (ret < 0)
7087                 return ret;
7088
7089         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7090                 if (!(mask0 & (1UL << i)))
7091                         continue;
7092                 mask0 &= ~(1UL << i);
7093                 /* if flowtype is invalid, continue */
7094                 if (!I40E_VALID_FLOW(i))
7095                         continue;
7096                 pctype = i40e_flowtype_to_pctype(i);
7097                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7098                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7099                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7100         }
7101
7102         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7103         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7104                 /* Toeplitz */
7105                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7106                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7107                                                                 "Toeplitz");
7108                         goto out;
7109                 }
7110                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7111         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7112                 /* Simple XOR */
7113                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7114                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7115                                                         "Simple XOR");
7116                         goto out;
7117                 }
7118                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7119         } else
7120                 /* Use the default, and keep it as it is */
7121                 goto out;
7122
7123         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7124
7125 out:
7126         I40E_WRITE_FLUSH(hw);
7127
7128         return 0;
7129 }
7130
7131 /**
7132  * Valid input sets for hash and flow director filters per PCTYPE
7133  */
7134 static uint64_t
7135 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7136                 enum rte_filter_type filter)
7137 {
7138         uint64_t valid;
7139
7140         static const uint64_t valid_hash_inset_table[] = {
7141                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7145                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7146                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7147                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7148                         I40E_INSET_FLEX_PAYLOAD,
7149                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7150                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7151                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7152                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7153                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7154                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7155                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7156                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7157                         I40E_INSET_FLEX_PAYLOAD,
7158 #ifdef X722_SUPPORT
7159                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7163                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7164                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7165                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7167                         I40E_INSET_FLEX_PAYLOAD,
7168                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7169                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7170                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7172                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7173                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7174                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7175                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7176                         I40E_INSET_FLEX_PAYLOAD,
7177 #endif
7178                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7179                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7180                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7181                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7182                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7183                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7184                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7185                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7186                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7187 #ifdef X722_SUPPORT
7188                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7192                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7193                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7194                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7195                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7196                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7197 #endif
7198                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7199                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7200                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7202                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7203                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7204                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7205                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7206                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7207                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7208                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7209                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7210                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7211                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7212                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7213                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7214                         I40E_INSET_FLEX_PAYLOAD,
7215                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7216                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7217                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7218                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7219                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7220                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7221                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7222                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7223                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7227                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7228                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7229                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7230                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7231 #ifdef X722_SUPPORT
7232                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7233                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7234                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7235                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7236                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7237                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7238                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7239                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7240                         I40E_INSET_FLEX_PAYLOAD,
7241                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7242                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7243                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7244                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7245                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7246                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7247                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7248                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7249                         I40E_INSET_FLEX_PAYLOAD,
7250 #endif
7251                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7252                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7253                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7254                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7255                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7256                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7257                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7258                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7259                         I40E_INSET_FLEX_PAYLOAD,
7260 #ifdef X722_SUPPORT
7261                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7262                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7263                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7264                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7265                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7266                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7267                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7268                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7269                         I40E_INSET_FLEX_PAYLOAD,
7270 #endif
7271                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7272                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7273                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7274                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7275                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7276                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7277                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7278                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7279                         I40E_INSET_FLEX_PAYLOAD,
7280                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7281                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7282                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7283                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7284                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7285                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7286                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7287                         I40E_INSET_FLEX_PAYLOAD,
7288                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7289                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7290                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7292                         I40E_INSET_FLEX_PAYLOAD,
7293         };
7294
7295         /**
7296          * Flow director supports only fields defined in
7297          * union rte_eth_fdir_flow.
7298          */
7299         static const uint64_t valid_fdir_inset_table[] = {
7300                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7303                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7304                 I40E_INSET_IPV4_TTL,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7306                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7308                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7309                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7310 #ifdef X722_SUPPORT
7311                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7314                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7315                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7316                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7317                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7318                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7319                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7320                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7321 #endif
7322                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7324                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7325                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7327 #ifdef X722_SUPPORT
7328                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7330                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7331                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7333 #endif
7334                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7337                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7338                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7339                 I40E_INSET_SCTP_VT,
7340                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7341                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7342                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7343                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7344                 I40E_INSET_IPV4_TTL,
7345                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7346                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7347                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7348                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7349                 I40E_INSET_IPV6_HOP_LIMIT,
7350                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7351                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7352                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7353                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7354                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7355 #ifdef X722_SUPPORT
7356                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7357                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7358                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7359                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7360                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7361                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7362                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7363                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7364                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7365                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7366 #endif
7367                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7368                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7369                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7370                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7371                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7372 #ifdef X722_SUPPORT
7373                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7374                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7375                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7376                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7377                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7378 #endif
7379                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7380                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7381                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7382                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7383                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7384                 I40E_INSET_SCTP_VT,
7385                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7386                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7387                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7388                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7389                 I40E_INSET_IPV6_HOP_LIMIT,
7390                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7391                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7392                 I40E_INSET_LAST_ETHER_TYPE,
7393         };
7394
7395         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7396                 return 0;
7397         if (filter == RTE_ETH_FILTER_HASH)
7398                 valid = valid_hash_inset_table[pctype];
7399         else
7400                 valid = valid_fdir_inset_table[pctype];
7401
7402         return valid;
7403 }
7404
7405 /**
7406  * Validate if the input set is allowed for a specific PCTYPE
7407  */
7408 static int
7409 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7410                 enum rte_filter_type filter, uint64_t inset)
7411 {
7412         uint64_t valid;
7413
7414         valid = i40e_get_valid_input_set(pctype, filter);
7415         if (inset & (~valid))
7416                 return -EINVAL;
7417
7418         return 0;
7419 }
7420
7421 /* default input set fields combination per pctype */
7422 static uint64_t
7423 i40e_get_default_input_set(uint16_t pctype)
7424 {
7425         static const uint64_t default_inset_table[] = {
7426                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7427                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7428                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7429                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7431 #ifdef X722_SUPPORT
7432                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7433                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7435                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7436                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7437                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7438 #endif
7439                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7440                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7441                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7442 #ifdef X722_SUPPORT
7443                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7444                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7445                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7446 #endif
7447                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7448                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7449                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7450                         I40E_INSET_SCTP_VT,
7451                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7452                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7453                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7454                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7455                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7456                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7457                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7458 #ifdef X722_SUPPORT
7459                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7460                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7461                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7462                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7463                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7464                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7465 #endif
7466                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7467                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7468                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7469 #ifdef X722_SUPPORT
7470                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7471                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7472                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7473 #endif
7474                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7475                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7476                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7477                         I40E_INSET_SCTP_VT,
7478                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7479                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7480                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7481                         I40E_INSET_LAST_ETHER_TYPE,
7482         };
7483
7484         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7485                 return 0;
7486
7487         return default_inset_table[pctype];
7488 }
7489
7490 /**
7491  * Parse the input set from index to logical bit masks
7492  */
7493 static int
7494 i40e_parse_input_set(uint64_t *inset,
7495                      enum i40e_filter_pctype pctype,
7496                      enum rte_eth_input_set_field *field,
7497                      uint16_t size)
7498 {
7499         uint16_t i, j;
7500         int ret = -EINVAL;
7501
7502         static const struct {
7503                 enum rte_eth_input_set_field field;
7504                 uint64_t inset;
7505         } inset_convert_table[] = {
7506                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7507                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7508                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7509                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7510                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7511                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7512                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7513                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7514                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7515                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7516                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7517                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7518                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7519                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7520                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7521                         I40E_INSET_IPV6_NEXT_HDR},
7522                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7523                         I40E_INSET_IPV6_HOP_LIMIT},
7524                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7525                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7526                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7527                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7528                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7529                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7530                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7531                         I40E_INSET_SCTP_VT},
7532                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7533                         I40E_INSET_TUNNEL_DMAC},
7534                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7535                         I40E_INSET_VLAN_TUNNEL},
7536                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7537                         I40E_INSET_TUNNEL_ID},
7538                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7539                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7540                         I40E_INSET_FLEX_PAYLOAD_W1},
7541                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7542                         I40E_INSET_FLEX_PAYLOAD_W2},
7543                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7544                         I40E_INSET_FLEX_PAYLOAD_W3},
7545                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7546                         I40E_INSET_FLEX_PAYLOAD_W4},
7547                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7548                         I40E_INSET_FLEX_PAYLOAD_W5},
7549                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7550                         I40E_INSET_FLEX_PAYLOAD_W6},
7551                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7552                         I40E_INSET_FLEX_PAYLOAD_W7},
7553                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7554                         I40E_INSET_FLEX_PAYLOAD_W8},
7555         };
7556
7557         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7558                 return ret;
7559
7560         /* Only one item allowed for default or all */
7561         if (size == 1) {
7562                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7563                         *inset = i40e_get_default_input_set(pctype);
7564                         return 0;
7565                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7566                         *inset = I40E_INSET_NONE;
7567                         return 0;
7568                 }
7569         }
7570
7571         for (i = 0, *inset = 0; i < size; i++) {
7572                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7573                         if (field[i] == inset_convert_table[j].field) {
7574                                 *inset |= inset_convert_table[j].inset;
7575                                 break;
7576                         }
7577                 }
7578
7579                 /* It contains unsupported input set, return immediately */
7580                 if (j == RTE_DIM(inset_convert_table))
7581                         return ret;
7582         }
7583
7584         return 0;
7585 }
7586
7587 /**
7588  * Translate the input set from bit masks to register aware bit masks
7589  * and vice versa
7590  */
7591 static uint64_t
7592 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7593 {
7594         uint64_t val = 0;
7595         uint16_t i;
7596
7597         struct inset_map {
7598                 uint64_t inset;
7599                 uint64_t inset_reg;
7600         };
7601
7602         static const struct inset_map inset_map_common[] = {
7603                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7604                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7605                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7606                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7607                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7608                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7609                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7610                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7611                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7612                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7613                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7614                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7615                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7616                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7617                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7618                 {I40E_INSET_TUNNEL_DMAC,
7619                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7620                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7621                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7622                 {I40E_INSET_TUNNEL_SRC_PORT,
7623                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7624                 {I40E_INSET_TUNNEL_DST_PORT,
7625                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7626                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7627                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7628                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7629                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7630                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7631                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7632                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7633                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7634                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7635         };
7636
7637     /* some different registers map in x722*/
7638         static const struct inset_map inset_map_diff_x722[] = {
7639                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7640                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7641                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7642                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7643         };
7644
7645         static const struct inset_map inset_map_diff_not_x722[] = {
7646                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7647                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7648                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7649                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7650         };
7651
7652         if (input == 0)
7653                 return val;
7654
7655         /* Translate input set to register aware inset */
7656         if (type == I40E_MAC_X722) {
7657                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7658                         if (input & inset_map_diff_x722[i].inset)
7659                                 val |= inset_map_diff_x722[i].inset_reg;
7660                 }
7661         } else {
7662                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7663                         if (input & inset_map_diff_not_x722[i].inset)
7664                                 val |= inset_map_diff_not_x722[i].inset_reg;
7665                 }
7666         }
7667
7668         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7669                 if (input & inset_map_common[i].inset)
7670                         val |= inset_map_common[i].inset_reg;
7671         }
7672
7673         return val;
7674 }
7675
7676 static int
7677 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7678 {
7679         uint8_t i, idx = 0;
7680         uint64_t inset_need_mask = inset;
7681
7682         static const struct {
7683                 uint64_t inset;
7684                 uint32_t mask;
7685         } inset_mask_map[] = {
7686                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7687                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7688                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7689                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7690                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7691                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7692                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7693                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7694         };
7695
7696         if (!inset || !mask || !nb_elem)
7697                 return 0;
7698
7699         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7700                 /* Clear the inset bit, if no MASK is required,
7701                  * for example proto + ttl
7702                  */
7703                 if ((inset & inset_mask_map[i].inset) ==
7704                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7705                         inset_need_mask &= ~inset_mask_map[i].inset;
7706                 if (!inset_need_mask)
7707                         return 0;
7708         }
7709         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7710                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7711                     inset_mask_map[i].inset) {
7712                         if (idx >= nb_elem) {
7713                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7714                                 return -EINVAL;
7715                         }
7716                         mask[idx] = inset_mask_map[i].mask;
7717                         idx++;
7718                 }
7719         }
7720
7721         return idx;
7722 }
7723
7724 static void
7725 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7726 {
7727         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7728
7729         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7730         if (reg != val)
7731                 i40e_write_rx_ctl(hw, addr, val);
7732         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7733                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7734 }
7735
7736 static void
7737 i40e_filter_input_set_init(struct i40e_pf *pf)
7738 {
7739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7740         enum i40e_filter_pctype pctype;
7741         uint64_t input_set, inset_reg;
7742         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7743         int num, i;
7744
7745         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7746              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7747                 if (hw->mac.type == I40E_MAC_X722) {
7748                         if (!I40E_VALID_PCTYPE_X722(pctype))
7749                                 continue;
7750                 } else {
7751                         if (!I40E_VALID_PCTYPE(pctype))
7752                                 continue;
7753                 }
7754
7755                 input_set = i40e_get_default_input_set(pctype);
7756
7757                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7758                                                    I40E_INSET_MASK_NUM_REG);
7759                 if (num < 0)
7760                         return;
7761                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7762                                         input_set);
7763
7764                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7765                                       (uint32_t)(inset_reg & UINT32_MAX));
7766                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7767                                      (uint32_t)((inset_reg >>
7768                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7769                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7770                                       (uint32_t)(inset_reg & UINT32_MAX));
7771                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7772                                      (uint32_t)((inset_reg >>
7773                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7774
7775                 for (i = 0; i < num; i++) {
7776                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7777                                              mask_reg[i]);
7778                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7779                                              mask_reg[i]);
7780                 }
7781                 /*clear unused mask registers of the pctype */
7782                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7783                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7784                                              0);
7785                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7786                                              0);
7787                 }
7788                 I40E_WRITE_FLUSH(hw);
7789
7790                 /* store the default input set */
7791                 pf->hash_input_set[pctype] = input_set;
7792                 pf->fdir.input_set[pctype] = input_set;
7793         }
7794 }
7795
7796 int
7797 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7798                          struct rte_eth_input_set_conf *conf)
7799 {
7800         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7801         enum i40e_filter_pctype pctype;
7802         uint64_t input_set, inset_reg = 0;
7803         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7804         int ret, i, num;
7805
7806         if (!conf) {
7807                 PMD_DRV_LOG(ERR, "Invalid pointer");
7808                 return -EFAULT;
7809         }
7810         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7811             conf->op != RTE_ETH_INPUT_SET_ADD) {
7812                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7813                 return -EINVAL;
7814         }
7815
7816         if (!I40E_VALID_FLOW(conf->flow_type)) {
7817                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7818                 return -EINVAL;
7819         }
7820
7821         if (hw->mac.type == I40E_MAC_X722) {
7822                 /* get translated pctype value in fd pctype register */
7823                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7824                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7825                         conf->flow_type)));
7826         } else
7827                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7828
7829         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7830                                    conf->inset_size);
7831         if (ret) {
7832                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7833                 return -EINVAL;
7834         }
7835         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7836                                     input_set) != 0) {
7837                 PMD_DRV_LOG(ERR, "Invalid input set");
7838                 return -EINVAL;
7839         }
7840         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7841                 /* get inset value in register */
7842                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7843                 inset_reg <<= I40E_32_BIT_WIDTH;
7844                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7845                 input_set |= pf->hash_input_set[pctype];
7846         }
7847         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7848                                            I40E_INSET_MASK_NUM_REG);
7849         if (num < 0)
7850                 return -EINVAL;
7851
7852         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7853
7854         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7855                               (uint32_t)(inset_reg & UINT32_MAX));
7856         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7857                              (uint32_t)((inset_reg >>
7858                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7859
7860         for (i = 0; i < num; i++)
7861                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7862                                      mask_reg[i]);
7863         /*clear unused mask registers of the pctype */
7864         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7865                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7866                                      0);
7867         I40E_WRITE_FLUSH(hw);
7868
7869         pf->hash_input_set[pctype] = input_set;
7870         return 0;
7871 }
7872
7873 int
7874 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7875                          struct rte_eth_input_set_conf *conf)
7876 {
7877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7878         enum i40e_filter_pctype pctype;
7879         uint64_t input_set, inset_reg = 0;
7880         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7881         int ret, i, num;
7882
7883         if (!hw || !conf) {
7884                 PMD_DRV_LOG(ERR, "Invalid pointer");
7885                 return -EFAULT;
7886         }
7887         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7888             conf->op != RTE_ETH_INPUT_SET_ADD) {
7889                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7890                 return -EINVAL;
7891         }
7892
7893         if (!I40E_VALID_FLOW(conf->flow_type)) {
7894                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7895                 return -EINVAL;
7896         }
7897
7898         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7899
7900         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7901                                    conf->inset_size);
7902         if (ret) {
7903                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7904                 return -EINVAL;
7905         }
7906         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7907                                     input_set) != 0) {
7908                 PMD_DRV_LOG(ERR, "Invalid input set");
7909                 return -EINVAL;
7910         }
7911
7912         /* get inset value in register */
7913         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7914         inset_reg <<= I40E_32_BIT_WIDTH;
7915         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7916
7917         /* Can not change the inset reg for flex payload for fdir,
7918          * it is done by writing I40E_PRTQF_FD_FLXINSET
7919          * in i40e_set_flex_mask_on_pctype.
7920          */
7921         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7922                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7923         else
7924                 input_set |= pf->fdir.input_set[pctype];
7925         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7926                                            I40E_INSET_MASK_NUM_REG);
7927         if (num < 0)
7928                 return -EINVAL;
7929
7930         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7931
7932         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7933                               (uint32_t)(inset_reg & UINT32_MAX));
7934         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7935                              (uint32_t)((inset_reg >>
7936                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7937
7938         for (i = 0; i < num; i++)
7939                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7940                                      mask_reg[i]);
7941         /*clear unused mask registers of the pctype */
7942         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7943                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7944                                      0);
7945         I40E_WRITE_FLUSH(hw);
7946
7947         pf->fdir.input_set[pctype] = input_set;
7948         return 0;
7949 }
7950
7951 static int
7952 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7953 {
7954         int ret = 0;
7955
7956         if (!hw || !info) {
7957                 PMD_DRV_LOG(ERR, "Invalid pointer");
7958                 return -EFAULT;
7959         }
7960
7961         switch (info->info_type) {
7962         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7963                 i40e_get_symmetric_hash_enable_per_port(hw,
7964                                         &(info->info.enable));
7965                 break;
7966         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7967                 ret = i40e_get_hash_filter_global_config(hw,
7968                                 &(info->info.global_conf));
7969                 break;
7970         default:
7971                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7972                                                         info->info_type);
7973                 ret = -EINVAL;
7974                 break;
7975         }
7976
7977         return ret;
7978 }
7979
7980 static int
7981 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7982 {
7983         int ret = 0;
7984
7985         if (!hw || !info) {
7986                 PMD_DRV_LOG(ERR, "Invalid pointer");
7987                 return -EFAULT;
7988         }
7989
7990         switch (info->info_type) {
7991         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7992                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7993                 break;
7994         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7995                 ret = i40e_set_hash_filter_global_config(hw,
7996                                 &(info->info.global_conf));
7997                 break;
7998         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7999                 ret = i40e_hash_filter_inset_select(hw,
8000                                                &(info->info.input_set_conf));
8001                 break;
8002
8003         default:
8004                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8005                                                         info->info_type);
8006                 ret = -EINVAL;
8007                 break;
8008         }
8009
8010         return ret;
8011 }
8012
8013 /* Operations for hash function */
8014 static int
8015 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8016                       enum rte_filter_op filter_op,
8017                       void *arg)
8018 {
8019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8020         int ret = 0;
8021
8022         switch (filter_op) {
8023         case RTE_ETH_FILTER_NOP:
8024                 break;
8025         case RTE_ETH_FILTER_GET:
8026                 ret = i40e_hash_filter_get(hw,
8027                         (struct rte_eth_hash_filter_info *)arg);
8028                 break;
8029         case RTE_ETH_FILTER_SET:
8030                 ret = i40e_hash_filter_set(hw,
8031                         (struct rte_eth_hash_filter_info *)arg);
8032                 break;
8033         default:
8034                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8035                                                                 filter_op);
8036                 ret = -ENOTSUP;
8037                 break;
8038         }
8039
8040         return ret;
8041 }
8042
8043 /*
8044  * Configure ethertype filter, which can director packet by filtering
8045  * with mac address and ether_type or only ether_type
8046  */
8047 static int
8048 i40e_ethertype_filter_set(struct i40e_pf *pf,
8049                         struct rte_eth_ethertype_filter *filter,
8050                         bool add)
8051 {
8052         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8053         struct i40e_control_filter_stats stats;
8054         uint16_t flags = 0;
8055         int ret;
8056
8057         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8058                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8059                 return -EINVAL;
8060         }
8061         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8062                 filter->ether_type == ETHER_TYPE_IPv6) {
8063                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8064                         " control packet filter.", filter->ether_type);
8065                 return -EINVAL;
8066         }
8067         if (filter->ether_type == ETHER_TYPE_VLAN)
8068                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8069                         " not supported.");
8070
8071         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8072                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8073         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8074                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8075         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8076
8077         memset(&stats, 0, sizeof(stats));
8078         ret = i40e_aq_add_rem_control_packet_filter(hw,
8079                         filter->mac_addr.addr_bytes,
8080                         filter->ether_type, flags,
8081                         pf->main_vsi->seid,
8082                         filter->queue, add, &stats, NULL);
8083
8084         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8085                          " mac_etype_used = %u, etype_used = %u,"
8086                          " mac_etype_free = %u, etype_free = %u\n",
8087                          ret, stats.mac_etype_used, stats.etype_used,
8088                          stats.mac_etype_free, stats.etype_free);
8089         if (ret < 0)
8090                 return -ENOSYS;
8091         return 0;
8092 }
8093
8094 /*
8095  * Handle operations for ethertype filter.
8096  */
8097 static int
8098 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8099                                 enum rte_filter_op filter_op,
8100                                 void *arg)
8101 {
8102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8103         int ret = 0;
8104
8105         if (filter_op == RTE_ETH_FILTER_NOP)
8106                 return ret;
8107
8108         if (arg == NULL) {
8109                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8110                             filter_op);
8111                 return -EINVAL;
8112         }
8113
8114         switch (filter_op) {
8115         case RTE_ETH_FILTER_ADD:
8116                 ret = i40e_ethertype_filter_set(pf,
8117                         (struct rte_eth_ethertype_filter *)arg,
8118                         TRUE);
8119                 break;
8120         case RTE_ETH_FILTER_DELETE:
8121                 ret = i40e_ethertype_filter_set(pf,
8122                         (struct rte_eth_ethertype_filter *)arg,
8123                         FALSE);
8124                 break;
8125         default:
8126                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8127                 ret = -ENOSYS;
8128                 break;
8129         }
8130         return ret;
8131 }
8132
8133 static int
8134 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8135                      enum rte_filter_type filter_type,
8136                      enum rte_filter_op filter_op,
8137                      void *arg)
8138 {
8139         int ret = 0;
8140
8141         if (dev == NULL)
8142                 return -EINVAL;
8143
8144         switch (filter_type) {
8145         case RTE_ETH_FILTER_NONE:
8146                 /* For global configuration */
8147                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8148                 break;
8149         case RTE_ETH_FILTER_HASH:
8150                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8151                 break;
8152         case RTE_ETH_FILTER_MACVLAN:
8153                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8154                 break;
8155         case RTE_ETH_FILTER_ETHERTYPE:
8156                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8157                 break;
8158         case RTE_ETH_FILTER_TUNNEL:
8159                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8160                 break;
8161         case RTE_ETH_FILTER_FDIR:
8162                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8163                 break;
8164         default:
8165                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8166                                                         filter_type);
8167                 ret = -EINVAL;
8168                 break;
8169         }
8170
8171         return ret;
8172 }
8173
8174 /*
8175  * Check and enable Extended Tag.
8176  * Enabling Extended Tag is important for 40G performance.
8177  */
8178 static void
8179 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8180 {
8181         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8182         uint32_t buf = 0;
8183         int ret;
8184
8185         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8186                                       PCI_DEV_CAP_REG);
8187         if (ret < 0) {
8188                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8189                             PCI_DEV_CAP_REG);
8190                 return;
8191         }
8192         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8193                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8194                 return;
8195         }
8196
8197         buf = 0;
8198         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8199                                       PCI_DEV_CTRL_REG);
8200         if (ret < 0) {
8201                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8202                             PCI_DEV_CTRL_REG);
8203                 return;
8204         }
8205         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8206                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8207                 return;
8208         }
8209         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8210         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8211                                        PCI_DEV_CTRL_REG);
8212         if (ret < 0) {
8213                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8214                             PCI_DEV_CTRL_REG);
8215                 return;
8216         }
8217 }
8218
8219 /*
8220  * As some registers wouldn't be reset unless a global hardware reset,
8221  * hardware initialization is needed to put those registers into an
8222  * expected initial state.
8223  */
8224 static void
8225 i40e_hw_init(struct rte_eth_dev *dev)
8226 {
8227         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8228
8229         i40e_enable_extended_tag(dev);
8230
8231         /* clear the PF Queue Filter control register */
8232         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8233
8234         /* Disable symmetric hash per port */
8235         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8236 }
8237
8238 enum i40e_filter_pctype
8239 i40e_flowtype_to_pctype(uint16_t flow_type)
8240 {
8241         static const enum i40e_filter_pctype pctype_table[] = {
8242                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8243                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8244                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8245                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8246                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8247                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8248                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8249                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8250                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8251                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8252                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8253                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8254                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8255                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8256                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8257                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8258                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8259                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8260                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8261         };
8262
8263         return pctype_table[flow_type];
8264 }
8265
8266 uint16_t
8267 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8268 {
8269         static const uint16_t flowtype_table[] = {
8270                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8271                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8272                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8273 #ifdef X722_SUPPORT
8274                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8275                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8276                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8277                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8278 #endif
8279                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8280                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8281 #ifdef X722_SUPPORT
8282                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8283                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8284 #endif
8285                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8286                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8287                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8288                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8289                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8290                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8291                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8292 #ifdef X722_SUPPORT
8293                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8294                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8295                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8296                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8297 #endif
8298                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8299                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8300 #ifdef X722_SUPPORT
8301                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8302                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8303 #endif
8304                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8305                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8306                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8307                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8308                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8309         };
8310
8311         return flowtype_table[pctype];
8312 }
8313
8314 /*
8315  * On X710, performance number is far from the expectation on recent firmware
8316  * versions; on XL710, performance number is also far from the expectation on
8317  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8318  * mode is enabled and port MAC address is equal to the packet destination MAC
8319  * address. The fix for this issue may not be integrated in the following
8320  * firmware version. So the workaround in software driver is needed. It needs
8321  * to modify the initial values of 3 internal only registers for both X710 and
8322  * XL710. Note that the values for X710 or XL710 could be different, and the
8323  * workaround can be removed when it is fixed in firmware in the future.
8324  */
8325
8326 /* For both X710 and XL710 */
8327 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8328 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8329
8330 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8331 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8332
8333 /* For X710 */
8334 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8335 /* For XL710 */
8336 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8337 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8338
8339 static int
8340 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8341 {
8342         enum i40e_status_code status;
8343         struct i40e_aq_get_phy_abilities_resp phy_ab;
8344         int ret = -ENOTSUP;
8345
8346         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8347                                               NULL);
8348
8349         if (status)
8350                 return ret;
8351
8352         return 0;
8353 }
8354
8355
8356 static void
8357 i40e_configure_registers(struct i40e_hw *hw)
8358 {
8359         static struct {
8360                 uint32_t addr;
8361                 uint64_t val;
8362         } reg_table[] = {
8363                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8364                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8365                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8366         };
8367         uint64_t reg;
8368         uint32_t i;
8369         int ret;
8370
8371         for (i = 0; i < RTE_DIM(reg_table); i++) {
8372                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8373                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8374                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8375                                 reg_table[i].val =
8376                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8377                         else /* For X710 */
8378                                 reg_table[i].val =
8379                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8380                 }
8381
8382                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8383                                                         &reg, NULL);
8384                 if (ret < 0) {
8385                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8386                                                         reg_table[i].addr);
8387                         break;
8388                 }
8389                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8390                                                 reg_table[i].addr, reg);
8391                 if (reg == reg_table[i].val)
8392                         continue;
8393
8394                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8395                                                 reg_table[i].val, NULL);
8396                 if (ret < 0) {
8397                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8398                                 "address of 0x%"PRIx32, reg_table[i].val,
8399                                                         reg_table[i].addr);
8400                         break;
8401                 }
8402                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8403                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8404         }
8405 }
8406
8407 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8408 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8409 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8410 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8411 static int
8412 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8413 {
8414         uint32_t reg;
8415         int ret;
8416
8417         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8418                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8419                 return -EINVAL;
8420         }
8421
8422         /* Configure for double VLAN RX stripping */
8423         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8424         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8425                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8426                 ret = i40e_aq_debug_write_register(hw,
8427                                                    I40E_VSI_TSR(vsi->vsi_id),
8428                                                    reg, NULL);
8429                 if (ret < 0) {
8430                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8431                                     vsi->vsi_id);
8432                         return I40E_ERR_CONFIG;
8433                 }
8434         }
8435
8436         /* Configure for double VLAN TX insertion */
8437         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8438         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8439                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8440                 ret = i40e_aq_debug_write_register(hw,
8441                                                    I40E_VSI_L2TAGSTXVALID(
8442                                                    vsi->vsi_id), reg, NULL);
8443                 if (ret < 0) {
8444                         PMD_DRV_LOG(ERR, "Failed to update "
8445                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8446                         return I40E_ERR_CONFIG;
8447                 }
8448         }
8449
8450         return 0;
8451 }
8452
8453 /**
8454  * i40e_aq_add_mirror_rule
8455  * @hw: pointer to the hardware structure
8456  * @seid: VEB seid to add mirror rule to
8457  * @dst_id: destination vsi seid
8458  * @entries: Buffer which contains the entities to be mirrored
8459  * @count: number of entities contained in the buffer
8460  * @rule_id:the rule_id of the rule to be added
8461  *
8462  * Add a mirror rule for a given veb.
8463  *
8464  **/
8465 static enum i40e_status_code
8466 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8467                         uint16_t seid, uint16_t dst_id,
8468                         uint16_t rule_type, uint16_t *entries,
8469                         uint16_t count, uint16_t *rule_id)
8470 {
8471         struct i40e_aq_desc desc;
8472         struct i40e_aqc_add_delete_mirror_rule cmd;
8473         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8474                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8475                 &desc.params.raw;
8476         uint16_t buff_len;
8477         enum i40e_status_code status;
8478
8479         i40e_fill_default_direct_cmd_desc(&desc,
8480                                           i40e_aqc_opc_add_mirror_rule);
8481         memset(&cmd, 0, sizeof(cmd));
8482
8483         buff_len = sizeof(uint16_t) * count;
8484         desc.datalen = rte_cpu_to_le_16(buff_len);
8485         if (buff_len > 0)
8486                 desc.flags |= rte_cpu_to_le_16(
8487                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8488         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8489                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8490         cmd.num_entries = rte_cpu_to_le_16(count);
8491         cmd.seid = rte_cpu_to_le_16(seid);
8492         cmd.destination = rte_cpu_to_le_16(dst_id);
8493
8494         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8495         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8496         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8497                          "rule_id = %u"
8498                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8499                          hw->aq.asq_last_status, resp->rule_id,
8500                          resp->mirror_rules_used, resp->mirror_rules_free);
8501         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8502
8503         return status;
8504 }
8505
8506 /**
8507  * i40e_aq_del_mirror_rule
8508  * @hw: pointer to the hardware structure
8509  * @seid: VEB seid to add mirror rule to
8510  * @entries: Buffer which contains the entities to be mirrored
8511  * @count: number of entities contained in the buffer
8512  * @rule_id:the rule_id of the rule to be delete
8513  *
8514  * Delete a mirror rule for a given veb.
8515  *
8516  **/
8517 static enum i40e_status_code
8518 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8519                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8520                 uint16_t count, uint16_t rule_id)
8521 {
8522         struct i40e_aq_desc desc;
8523         struct i40e_aqc_add_delete_mirror_rule cmd;
8524         uint16_t buff_len = 0;
8525         enum i40e_status_code status;
8526         void *buff = NULL;
8527
8528         i40e_fill_default_direct_cmd_desc(&desc,
8529                                           i40e_aqc_opc_delete_mirror_rule);
8530         memset(&cmd, 0, sizeof(cmd));
8531         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8532                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8533                                                           I40E_AQ_FLAG_RD));
8534                 cmd.num_entries = count;
8535                 buff_len = sizeof(uint16_t) * count;
8536                 desc.datalen = rte_cpu_to_le_16(buff_len);
8537                 buff = (void *)entries;
8538         } else
8539                 /* rule id is filled in destination field for deleting mirror rule */
8540                 cmd.destination = rte_cpu_to_le_16(rule_id);
8541
8542         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8543                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8544         cmd.seid = rte_cpu_to_le_16(seid);
8545
8546         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8547         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8548
8549         return status;
8550 }
8551
8552 /**
8553  * i40e_mirror_rule_set
8554  * @dev: pointer to the hardware structure
8555  * @mirror_conf: mirror rule info
8556  * @sw_id: mirror rule's sw_id
8557  * @on: enable/disable
8558  *
8559  * set a mirror rule.
8560  *
8561  **/
8562 static int
8563 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8564                         struct rte_eth_mirror_conf *mirror_conf,
8565                         uint8_t sw_id, uint8_t on)
8566 {
8567         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8569         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8570         struct i40e_mirror_rule *parent = NULL;
8571         uint16_t seid, dst_seid, rule_id;
8572         uint16_t i, j = 0;
8573         int ret;
8574
8575         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8576
8577         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8578                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8579                         " without veb or vfs.");
8580                 return -ENOSYS;
8581         }
8582         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8583                 PMD_DRV_LOG(ERR, "mirror table is full.");
8584                 return -ENOSPC;
8585         }
8586         if (mirror_conf->dst_pool > pf->vf_num) {
8587                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8588                                  mirror_conf->dst_pool);
8589                 return -EINVAL;
8590         }
8591
8592         seid = pf->main_vsi->veb->seid;
8593
8594         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8595                 if (sw_id <= it->index) {
8596                         mirr_rule = it;
8597                         break;
8598                 }
8599                 parent = it;
8600         }
8601         if (mirr_rule && sw_id == mirr_rule->index) {
8602                 if (on) {
8603                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8604                         return -EEXIST;
8605                 } else {
8606                         ret = i40e_aq_del_mirror_rule(hw, seid,
8607                                         mirr_rule->rule_type,
8608                                         mirr_rule->entries,
8609                                         mirr_rule->num_entries, mirr_rule->id);
8610                         if (ret < 0) {
8611                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8612                                                    " ret = %d, aq_err = %d.",
8613                                                    ret, hw->aq.asq_last_status);
8614                                 return -ENOSYS;
8615                         }
8616                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8617                         rte_free(mirr_rule);
8618                         pf->nb_mirror_rule--;
8619                         return 0;
8620                 }
8621         } else if (!on) {
8622                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8623                 return -ENOENT;
8624         }
8625
8626         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8627                                 sizeof(struct i40e_mirror_rule) , 0);
8628         if (!mirr_rule) {
8629                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8630                 return I40E_ERR_NO_MEMORY;
8631         }
8632         switch (mirror_conf->rule_type) {
8633         case ETH_MIRROR_VLAN:
8634                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8635                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8636                                 mirr_rule->entries[j] =
8637                                         mirror_conf->vlan.vlan_id[i];
8638                                 j++;
8639                         }
8640                 }
8641                 if (j == 0) {
8642                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8643                         rte_free(mirr_rule);
8644                         return -EINVAL;
8645                 }
8646                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8647                 break;
8648         case ETH_MIRROR_VIRTUAL_POOL_UP:
8649         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8650                 /* check if the specified pool bit is out of range */
8651                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8652                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8653                         rte_free(mirr_rule);
8654                         return -EINVAL;
8655                 }
8656                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8657                         if (mirror_conf->pool_mask & (1ULL << i)) {
8658                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8659                                 j++;
8660                         }
8661                 }
8662                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8663                         /* add pf vsi to entries */
8664                         mirr_rule->entries[j] = pf->main_vsi_seid;
8665                         j++;
8666                 }
8667                 if (j == 0) {
8668                         PMD_DRV_LOG(ERR, "pool is not specified.");
8669                         rte_free(mirr_rule);
8670                         return -EINVAL;
8671                 }
8672                 /* egress and ingress in aq commands means from switch but not port */
8673                 mirr_rule->rule_type =
8674                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8675                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8676                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8677                 break;
8678         case ETH_MIRROR_UPLINK_PORT:
8679                 /* egress and ingress in aq commands means from switch but not port*/
8680                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8681                 break;
8682         case ETH_MIRROR_DOWNLINK_PORT:
8683                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8684                 break;
8685         default:
8686                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8687                         mirror_conf->rule_type);
8688                 rte_free(mirr_rule);
8689                 return -EINVAL;
8690         }
8691
8692         /* If the dst_pool is equal to vf_num, consider it as PF */
8693         if (mirror_conf->dst_pool == pf->vf_num)
8694                 dst_seid = pf->main_vsi_seid;
8695         else
8696                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8697
8698         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8699                                       mirr_rule->rule_type, mirr_rule->entries,
8700                                       j, &rule_id);
8701         if (ret < 0) {
8702                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8703                                    " ret = %d, aq_err = %d.",
8704                                    ret, hw->aq.asq_last_status);
8705                 rte_free(mirr_rule);
8706                 return -ENOSYS;
8707         }
8708
8709         mirr_rule->index = sw_id;
8710         mirr_rule->num_entries = j;
8711         mirr_rule->id = rule_id;
8712         mirr_rule->dst_vsi_seid = dst_seid;
8713
8714         if (parent)
8715                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8716         else
8717                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8718
8719         pf->nb_mirror_rule++;
8720         return 0;
8721 }
8722
8723 /**
8724  * i40e_mirror_rule_reset
8725  * @dev: pointer to the device
8726  * @sw_id: mirror rule's sw_id
8727  *
8728  * reset a mirror rule.
8729  *
8730  **/
8731 static int
8732 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8733 {
8734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8736         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8737         uint16_t seid;
8738         int ret;
8739
8740         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8741
8742         seid = pf->main_vsi->veb->seid;
8743
8744         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8745                 if (sw_id == it->index) {
8746                         mirr_rule = it;
8747                         break;
8748                 }
8749         }
8750         if (mirr_rule) {
8751                 ret = i40e_aq_del_mirror_rule(hw, seid,
8752                                 mirr_rule->rule_type,
8753                                 mirr_rule->entries,
8754                                 mirr_rule->num_entries, mirr_rule->id);
8755                 if (ret < 0) {
8756                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8757                                            " status = %d, aq_err = %d.",
8758                                            ret, hw->aq.asq_last_status);
8759                         return -ENOSYS;
8760                 }
8761                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8762                 rte_free(mirr_rule);
8763                 pf->nb_mirror_rule--;
8764         } else {
8765                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8766                 return -ENOENT;
8767         }
8768         return 0;
8769 }
8770
8771 static uint64_t
8772 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8773 {
8774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8775         uint64_t systim_cycles;
8776
8777         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8778         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8779                         << 32;
8780
8781         return systim_cycles;
8782 }
8783
8784 static uint64_t
8785 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8786 {
8787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8788         uint64_t rx_tstamp;
8789
8790         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8791         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8792                         << 32;
8793
8794         return rx_tstamp;
8795 }
8796
8797 static uint64_t
8798 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8799 {
8800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8801         uint64_t tx_tstamp;
8802
8803         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8804         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8805                         << 32;
8806
8807         return tx_tstamp;
8808 }
8809
8810 static void
8811 i40e_start_timecounters(struct rte_eth_dev *dev)
8812 {
8813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8814         struct i40e_adapter *adapter =
8815                         (struct i40e_adapter *)dev->data->dev_private;
8816         struct rte_eth_link link;
8817         uint32_t tsync_inc_l;
8818         uint32_t tsync_inc_h;
8819
8820         /* Get current link speed. */
8821         memset(&link, 0, sizeof(link));
8822         i40e_dev_link_update(dev, 1);
8823         rte_i40e_dev_atomic_read_link_status(dev, &link);
8824
8825         switch (link.link_speed) {
8826         case ETH_SPEED_NUM_40G:
8827                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8828                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8829                 break;
8830         case ETH_SPEED_NUM_10G:
8831                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8832                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8833                 break;
8834         case ETH_SPEED_NUM_1G:
8835                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8836                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8837                 break;
8838         default:
8839                 tsync_inc_l = 0x0;
8840                 tsync_inc_h = 0x0;
8841         }
8842
8843         /* Set the timesync increment value. */
8844         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8845         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8846
8847         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8848         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8849         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8850
8851         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8852         adapter->systime_tc.cc_shift = 0;
8853         adapter->systime_tc.nsec_mask = 0;
8854
8855         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8856         adapter->rx_tstamp_tc.cc_shift = 0;
8857         adapter->rx_tstamp_tc.nsec_mask = 0;
8858
8859         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8860         adapter->tx_tstamp_tc.cc_shift = 0;
8861         adapter->tx_tstamp_tc.nsec_mask = 0;
8862 }
8863
8864 static int
8865 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8866 {
8867         struct i40e_adapter *adapter =
8868                         (struct i40e_adapter *)dev->data->dev_private;
8869
8870         adapter->systime_tc.nsec += delta;
8871         adapter->rx_tstamp_tc.nsec += delta;
8872         adapter->tx_tstamp_tc.nsec += delta;
8873
8874         return 0;
8875 }
8876
8877 static int
8878 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8879 {
8880         uint64_t ns;
8881         struct i40e_adapter *adapter =
8882                         (struct i40e_adapter *)dev->data->dev_private;
8883
8884         ns = rte_timespec_to_ns(ts);
8885
8886         /* Set the timecounters to a new value. */
8887         adapter->systime_tc.nsec = ns;
8888         adapter->rx_tstamp_tc.nsec = ns;
8889         adapter->tx_tstamp_tc.nsec = ns;
8890
8891         return 0;
8892 }
8893
8894 static int
8895 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8896 {
8897         uint64_t ns, systime_cycles;
8898         struct i40e_adapter *adapter =
8899                         (struct i40e_adapter *)dev->data->dev_private;
8900
8901         systime_cycles = i40e_read_systime_cyclecounter(dev);
8902         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8903         *ts = rte_ns_to_timespec(ns);
8904
8905         return 0;
8906 }
8907
8908 static int
8909 i40e_timesync_enable(struct rte_eth_dev *dev)
8910 {
8911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8912         uint32_t tsync_ctl_l;
8913         uint32_t tsync_ctl_h;
8914
8915         /* Stop the timesync system time. */
8916         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8917         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8918         /* Reset the timesync system time value. */
8919         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8920         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8921
8922         i40e_start_timecounters(dev);
8923
8924         /* Clear timesync registers. */
8925         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8926         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8927         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8928         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8929         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8930         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8931
8932         /* Enable timestamping of PTP packets. */
8933         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8934         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8935
8936         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8937         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8938         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8939
8940         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8941         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8942
8943         return 0;
8944 }
8945
8946 static int
8947 i40e_timesync_disable(struct rte_eth_dev *dev)
8948 {
8949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8950         uint32_t tsync_ctl_l;
8951         uint32_t tsync_ctl_h;
8952
8953         /* Disable timestamping of transmitted PTP packets. */
8954         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8955         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8956
8957         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8958         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8959
8960         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8961         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8962
8963         /* Reset the timesync increment value. */
8964         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8965         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8966
8967         return 0;
8968 }
8969
8970 static int
8971 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8972                                 struct timespec *timestamp, uint32_t flags)
8973 {
8974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8975         struct i40e_adapter *adapter =
8976                 (struct i40e_adapter *)dev->data->dev_private;
8977
8978         uint32_t sync_status;
8979         uint32_t index = flags & 0x03;
8980         uint64_t rx_tstamp_cycles;
8981         uint64_t ns;
8982
8983         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8984         if ((sync_status & (1 << index)) == 0)
8985                 return -EINVAL;
8986
8987         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8988         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8989         *timestamp = rte_ns_to_timespec(ns);
8990
8991         return 0;
8992 }
8993
8994 static int
8995 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8996                                 struct timespec *timestamp)
8997 {
8998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8999         struct i40e_adapter *adapter =
9000                 (struct i40e_adapter *)dev->data->dev_private;
9001
9002         uint32_t sync_status;
9003         uint64_t tx_tstamp_cycles;
9004         uint64_t ns;
9005
9006         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9007         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9008                 return -EINVAL;
9009
9010         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9011         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9012         *timestamp = rte_ns_to_timespec(ns);
9013
9014         return 0;
9015 }
9016
9017 /*
9018  * i40e_parse_dcb_configure - parse dcb configure from user
9019  * @dev: the device being configured
9020  * @dcb_cfg: pointer of the result of parse
9021  * @*tc_map: bit map of enabled traffic classes
9022  *
9023  * Returns 0 on success, negative value on failure
9024  */
9025 static int
9026 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9027                          struct i40e_dcbx_config *dcb_cfg,
9028                          uint8_t *tc_map)
9029 {
9030         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9031         uint8_t i, tc_bw, bw_lf;
9032
9033         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9034
9035         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9036         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9037                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9038                 return -EINVAL;
9039         }
9040
9041         /* assume each tc has the same bw */
9042         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9043         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9044                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9045         /* to ensure the sum of tcbw is equal to 100 */
9046         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9047         for (i = 0; i < bw_lf; i++)
9048                 dcb_cfg->etscfg.tcbwtable[i]++;
9049
9050         /* assume each tc has the same Transmission Selection Algorithm */
9051         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9052                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9053
9054         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9055                 dcb_cfg->etscfg.prioritytable[i] =
9056                                 dcb_rx_conf->dcb_tc[i];
9057
9058         /* FW needs one App to configure HW */
9059         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9060         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9061         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9062         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9063
9064         if (dcb_rx_conf->nb_tcs == 0)
9065                 *tc_map = 1; /* tc0 only */
9066         else
9067                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9068
9069         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9070                 dcb_cfg->pfc.willing = 0;
9071                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9072                 dcb_cfg->pfc.pfcenable = *tc_map;
9073         }
9074         return 0;
9075 }
9076
9077
9078 static enum i40e_status_code
9079 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9080                               struct i40e_aqc_vsi_properties_data *info,
9081                               uint8_t enabled_tcmap)
9082 {
9083         enum i40e_status_code ret;
9084         int i, total_tc = 0;
9085         uint16_t qpnum_per_tc, bsf, qp_idx;
9086         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9087         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9088         uint16_t used_queues;
9089
9090         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9091         if (ret != I40E_SUCCESS)
9092                 return ret;
9093
9094         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9095                 if (enabled_tcmap & (1 << i))
9096                         total_tc++;
9097         }
9098         if (total_tc == 0)
9099                 total_tc = 1;
9100         vsi->enabled_tc = enabled_tcmap;
9101
9102         /* different VSI has different queues assigned */
9103         if (vsi->type == I40E_VSI_MAIN)
9104                 used_queues = dev_data->nb_rx_queues -
9105                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9106         else if (vsi->type == I40E_VSI_VMDQ2)
9107                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9108         else {
9109                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9110                 return I40E_ERR_NO_AVAILABLE_VSI;
9111         }
9112
9113         qpnum_per_tc = used_queues / total_tc;
9114         /* Number of queues per enabled TC */
9115         if (qpnum_per_tc == 0) {
9116                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9117                 return I40E_ERR_INVALID_QP_ID;
9118         }
9119         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9120                                 I40E_MAX_Q_PER_TC);
9121         bsf = rte_bsf32(qpnum_per_tc);
9122
9123         /**
9124          * Configure TC and queue mapping parameters, for enabled TC,
9125          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9126          * default queue will serve it.
9127          */
9128         qp_idx = 0;
9129         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9130                 if (vsi->enabled_tc & (1 << i)) {
9131                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9132                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9133                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9134                         qp_idx += qpnum_per_tc;
9135                 } else
9136                         info->tc_mapping[i] = 0;
9137         }
9138
9139         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9140         if (vsi->type == I40E_VSI_SRIOV) {
9141                 info->mapping_flags |=
9142                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9143                 for (i = 0; i < vsi->nb_qps; i++)
9144                         info->queue_mapping[i] =
9145                                 rte_cpu_to_le_16(vsi->base_queue + i);
9146         } else {
9147                 info->mapping_flags |=
9148                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9149                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9150         }
9151         info->valid_sections |=
9152                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9153
9154         return I40E_SUCCESS;
9155 }
9156
9157 /*
9158  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9159  * @veb: VEB to be configured
9160  * @tc_map: enabled TC bitmap
9161  *
9162  * Returns 0 on success, negative value on failure
9163  */
9164 static enum i40e_status_code
9165 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9166 {
9167         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9168         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9169         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9170         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9171         enum i40e_status_code ret = I40E_SUCCESS;
9172         int i;
9173         uint32_t bw_max;
9174
9175         /* Check if enabled_tc is same as existing or new TCs */
9176         if (veb->enabled_tc == tc_map)
9177                 return ret;
9178
9179         /* configure tc bandwidth */
9180         memset(&veb_bw, 0, sizeof(veb_bw));
9181         veb_bw.tc_valid_bits = tc_map;
9182         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9183         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9184                 if (tc_map & BIT_ULL(i))
9185                         veb_bw.tc_bw_share_credits[i] = 1;
9186         }
9187         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9188                                                    &veb_bw, NULL);
9189         if (ret) {
9190                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9191                                   " per TC failed = %d",
9192                                   hw->aq.asq_last_status);
9193                 return ret;
9194         }
9195
9196         memset(&ets_query, 0, sizeof(ets_query));
9197         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9198                                                    &ets_query, NULL);
9199         if (ret != I40E_SUCCESS) {
9200                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9201                                  " configuration %u", hw->aq.asq_last_status);
9202                 return ret;
9203         }
9204         memset(&bw_query, 0, sizeof(bw_query));
9205         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9206                                                   &bw_query, NULL);
9207         if (ret != I40E_SUCCESS) {
9208                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9209                                  " configuration %u", hw->aq.asq_last_status);
9210                 return ret;
9211         }
9212
9213         /* store and print out BW info */
9214         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9215         veb->bw_info.bw_max = ets_query.tc_bw_max;
9216         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9217         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9218         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9219                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9220                      I40E_16_BIT_WIDTH);
9221         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9222                 veb->bw_info.bw_ets_share_credits[i] =
9223                                 bw_query.tc_bw_share_credits[i];
9224                 veb->bw_info.bw_ets_credits[i] =
9225                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9226                 /* 4 bits per TC, 4th bit is reserved */
9227                 veb->bw_info.bw_ets_max[i] =
9228                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9229                                   RTE_LEN2MASK(3, uint8_t));
9230                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9231                             veb->bw_info.bw_ets_share_credits[i]);
9232                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9233                             veb->bw_info.bw_ets_credits[i]);
9234                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9235                             veb->bw_info.bw_ets_max[i]);
9236         }
9237
9238         veb->enabled_tc = tc_map;
9239
9240         return ret;
9241 }
9242
9243
9244 /*
9245  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9246  * @vsi: VSI to be configured
9247  * @tc_map: enabled TC bitmap
9248  *
9249  * Returns 0 on success, negative value on failure
9250  */
9251 static enum i40e_status_code
9252 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9253 {
9254         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9255         struct i40e_vsi_context ctxt;
9256         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9257         enum i40e_status_code ret = I40E_SUCCESS;
9258         int i;
9259
9260         /* Check if enabled_tc is same as existing or new TCs */
9261         if (vsi->enabled_tc == tc_map)
9262                 return ret;
9263
9264         /* configure tc bandwidth */
9265         memset(&bw_data, 0, sizeof(bw_data));
9266         bw_data.tc_valid_bits = tc_map;
9267         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9268         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9269                 if (tc_map & BIT_ULL(i))
9270                         bw_data.tc_bw_credits[i] = 1;
9271         }
9272         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9273         if (ret) {
9274                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9275                         " per TC failed = %d",
9276                         hw->aq.asq_last_status);
9277                 goto out;
9278         }
9279         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9280                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9281
9282         /* Update Queue Pairs Mapping for currently enabled UPs */
9283         ctxt.seid = vsi->seid;
9284         ctxt.pf_num = hw->pf_id;
9285         ctxt.vf_num = 0;
9286         ctxt.uplink_seid = vsi->uplink_seid;
9287         ctxt.info = vsi->info;
9288         i40e_get_cap(hw);
9289         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9290         if (ret)
9291                 goto out;
9292
9293         /* Update the VSI after updating the VSI queue-mapping information */
9294         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9295         if (ret) {
9296                 PMD_INIT_LOG(ERR, "Failed to configure "
9297                             "TC queue mapping = %d",
9298                             hw->aq.asq_last_status);
9299                 goto out;
9300         }
9301         /* update the local VSI info with updated queue map */
9302         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9303                                         sizeof(vsi->info.tc_mapping));
9304         (void)rte_memcpy(&vsi->info.queue_mapping,
9305                         &ctxt.info.queue_mapping,
9306                 sizeof(vsi->info.queue_mapping));
9307         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9308         vsi->info.valid_sections = 0;
9309
9310         /* query and update current VSI BW information */
9311         ret = i40e_vsi_get_bw_config(vsi);
9312         if (ret) {
9313                 PMD_INIT_LOG(ERR,
9314                          "Failed updating vsi bw info, err %s aq_err %s",
9315                          i40e_stat_str(hw, ret),
9316                          i40e_aq_str(hw, hw->aq.asq_last_status));
9317                 goto out;
9318         }
9319
9320         vsi->enabled_tc = tc_map;
9321
9322 out:
9323         return ret;
9324 }
9325
9326 /*
9327  * i40e_dcb_hw_configure - program the dcb setting to hw
9328  * @pf: pf the configuration is taken on
9329  * @new_cfg: new configuration
9330  * @tc_map: enabled TC bitmap
9331  *
9332  * Returns 0 on success, negative value on failure
9333  */
9334 static enum i40e_status_code
9335 i40e_dcb_hw_configure(struct i40e_pf *pf,
9336                       struct i40e_dcbx_config *new_cfg,
9337                       uint8_t tc_map)
9338 {
9339         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9340         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9341         struct i40e_vsi *main_vsi = pf->main_vsi;
9342         struct i40e_vsi_list *vsi_list;
9343         enum i40e_status_code ret;
9344         int i;
9345         uint32_t val;
9346
9347         /* Use the FW API if FW > v4.4*/
9348         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9349               (hw->aq.fw_maj_ver >= 5))) {
9350                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9351                                   " to configure DCB");
9352                 return I40E_ERR_FIRMWARE_API_VERSION;
9353         }
9354
9355         /* Check if need reconfiguration */
9356         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9357                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9358                 return I40E_SUCCESS;
9359         }
9360
9361         /* Copy the new config to the current config */
9362         *old_cfg = *new_cfg;
9363         old_cfg->etsrec = old_cfg->etscfg;
9364         ret = i40e_set_dcb_config(hw);
9365         if (ret) {
9366                 PMD_INIT_LOG(ERR,
9367                          "Set DCB Config failed, err %s aq_err %s\n",
9368                          i40e_stat_str(hw, ret),
9369                          i40e_aq_str(hw, hw->aq.asq_last_status));
9370                 return ret;
9371         }
9372         /* set receive Arbiter to RR mode and ETS scheme by default */
9373         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9374                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9375                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9376                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9377                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9378                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9379                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9380                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9381                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9382                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9383                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9384                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9385                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9386         }
9387         /* get local mib to check whether it is configured correctly */
9388         /* IEEE mode */
9389         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9390         /* Get Local DCB Config */
9391         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9392                                      &hw->local_dcbx_config);
9393
9394         /* if Veb is created, need to update TC of it at first */
9395         if (main_vsi->veb) {
9396                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9397                 if (ret)
9398                         PMD_INIT_LOG(WARNING,
9399                                  "Failed configuring TC for VEB seid=%d\n",
9400                                  main_vsi->veb->seid);
9401         }
9402         /* Update each VSI */
9403         i40e_vsi_config_tc(main_vsi, tc_map);
9404         if (main_vsi->veb) {
9405                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9406                         /* Beside main VSI and VMDQ VSIs, only enable default
9407                          * TC for other VSIs
9408                          */
9409                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9410                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9411                                                          tc_map);
9412                         else
9413                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9414                                                          I40E_DEFAULT_TCMAP);
9415                         if (ret)
9416                                 PMD_INIT_LOG(WARNING,
9417                                          "Failed configuring TC for VSI seid=%d\n",
9418                                          vsi_list->vsi->seid);
9419                         /* continue */
9420                 }
9421         }
9422         return I40E_SUCCESS;
9423 }
9424
9425 /*
9426  * i40e_dcb_init_configure - initial dcb config
9427  * @dev: device being configured
9428  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9429  *
9430  * Returns 0 on success, negative value on failure
9431  */
9432 static int
9433 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9434 {
9435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9437         int ret = 0;
9438
9439         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9440                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9441                 return -ENOTSUP;
9442         }
9443
9444         /* DCB initialization:
9445          * Update DCB configuration from the Firmware and configure
9446          * LLDP MIB change event.
9447          */
9448         if (sw_dcb == TRUE) {
9449                 ret = i40e_init_dcb(hw);
9450                 /* If lldp agent is stopped, the return value from
9451                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9452                  * adminq status. Otherwise, it should return success.
9453                  */
9454                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9455                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9456                         memset(&hw->local_dcbx_config, 0,
9457                                 sizeof(struct i40e_dcbx_config));
9458                         /* set dcb default configuration */
9459                         hw->local_dcbx_config.etscfg.willing = 0;
9460                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9461                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9462                         hw->local_dcbx_config.etscfg.tsatable[0] =
9463                                                 I40E_IEEE_TSA_ETS;
9464                         hw->local_dcbx_config.etsrec =
9465                                 hw->local_dcbx_config.etscfg;
9466                         hw->local_dcbx_config.pfc.willing = 0;
9467                         hw->local_dcbx_config.pfc.pfccap =
9468                                                 I40E_MAX_TRAFFIC_CLASS;
9469                         /* FW needs one App to configure HW */
9470                         hw->local_dcbx_config.numapps = 1;
9471                         hw->local_dcbx_config.app[0].selector =
9472                                                 I40E_APP_SEL_ETHTYPE;
9473                         hw->local_dcbx_config.app[0].priority = 3;
9474                         hw->local_dcbx_config.app[0].protocolid =
9475                                                 I40E_APP_PROTOID_FCOE;
9476                         ret = i40e_set_dcb_config(hw);
9477                         if (ret) {
9478                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9479                                         " err = %d, aq_err = %d.", ret,
9480                                           hw->aq.asq_last_status);
9481                                 return -ENOSYS;
9482                         }
9483                 } else {
9484                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9485                                           " err = %d, aq_err = %d.", ret,
9486                                           hw->aq.asq_last_status);
9487                         return -ENOTSUP;
9488                 }
9489         } else {
9490                 ret = i40e_aq_start_lldp(hw, NULL);
9491                 if (ret != I40E_SUCCESS)
9492                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9493
9494                 ret = i40e_init_dcb(hw);
9495                 if (!ret) {
9496                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9497                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9498                                                   " DCBX offload.");
9499                                 return -ENOTSUP;
9500                         }
9501                 } else {
9502                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9503                                           " aq_err = %d.", ret,
9504                                           hw->aq.asq_last_status);
9505                         return -ENOTSUP;
9506                 }
9507         }
9508         return 0;
9509 }
9510
9511 /*
9512  * i40e_dcb_setup - setup dcb related config
9513  * @dev: device being configured
9514  *
9515  * Returns 0 on success, negative value on failure
9516  */
9517 static int
9518 i40e_dcb_setup(struct rte_eth_dev *dev)
9519 {
9520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9521         struct i40e_dcbx_config dcb_cfg;
9522         uint8_t tc_map = 0;
9523         int ret = 0;
9524
9525         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9526                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9527                 return -ENOTSUP;
9528         }
9529
9530         if (pf->vf_num != 0)
9531                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9532
9533         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9534         if (ret) {
9535                 PMD_INIT_LOG(ERR, "invalid dcb config");
9536                 return -EINVAL;
9537         }
9538         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9539         if (ret) {
9540                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9541                 return -ENOSYS;
9542         }
9543
9544         return 0;
9545 }
9546
9547 static int
9548 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9549                       struct rte_eth_dcb_info *dcb_info)
9550 {
9551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9553         struct i40e_vsi *vsi = pf->main_vsi;
9554         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9555         uint16_t bsf, tc_mapping;
9556         int i, j = 0;
9557
9558         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9559                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9560         else
9561                 dcb_info->nb_tcs = 1;
9562         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9563                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9564         for (i = 0; i < dcb_info->nb_tcs; i++)
9565                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9566
9567         /* get queue mapping if vmdq is disabled */
9568         if (!pf->nb_cfg_vmdq_vsi) {
9569                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9570                         if (!(vsi->enabled_tc & (1 << i)))
9571                                 continue;
9572                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9573                         dcb_info->tc_queue.tc_rxq[j][i].base =
9574                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9575                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9576                         dcb_info->tc_queue.tc_txq[j][i].base =
9577                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9578                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9579                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9580                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9581                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9582                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9583                 }
9584                 return 0;
9585         }
9586
9587         /* get queue mapping if vmdq is enabled */
9588         do {
9589                 vsi = pf->vmdq[j].vsi;
9590                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9591                         if (!(vsi->enabled_tc & (1 << i)))
9592                                 continue;
9593                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9594                         dcb_info->tc_queue.tc_rxq[j][i].base =
9595                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9596                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9597                         dcb_info->tc_queue.tc_txq[j][i].base =
9598                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9599                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9600                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9601                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9602                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9603                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9604                 }
9605                 j++;
9606         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9607         return 0;
9608 }
9609
9610 static int
9611 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9612 {
9613         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9616         uint16_t interval =
9617                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9618         uint16_t msix_intr;
9619
9620         msix_intr = intr_handle->intr_vec[queue_id];
9621         if (msix_intr == I40E_MISC_VEC_ID)
9622                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9623                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9624                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9625                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9626                                (interval <<
9627                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9628         else
9629                 I40E_WRITE_REG(hw,
9630                                I40E_PFINT_DYN_CTLN(msix_intr -
9631                                                    I40E_RX_VEC_START),
9632                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9633                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9634                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9635                                (interval <<
9636                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9637
9638         I40E_WRITE_FLUSH(hw);
9639         rte_intr_enable(&pci_dev->intr_handle);
9640
9641         return 0;
9642 }
9643
9644 static int
9645 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9646 {
9647         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9648         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9650         uint16_t msix_intr;
9651
9652         msix_intr = intr_handle->intr_vec[queue_id];
9653         if (msix_intr == I40E_MISC_VEC_ID)
9654                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9655         else
9656                 I40E_WRITE_REG(hw,
9657                                I40E_PFINT_DYN_CTLN(msix_intr -
9658                                                    I40E_RX_VEC_START),
9659                                0);
9660         I40E_WRITE_FLUSH(hw);
9661
9662         return 0;
9663 }
9664
9665 static int i40e_get_regs(struct rte_eth_dev *dev,
9666                          struct rte_dev_reg_info *regs)
9667 {
9668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9669         uint32_t *ptr_data = regs->data;
9670         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9671         const struct i40e_reg_info *reg_info;
9672
9673         if (ptr_data == NULL) {
9674                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9675                 regs->width = sizeof(uint32_t);
9676                 return 0;
9677         }
9678
9679         /* The first few registers have to be read using AQ operations */
9680         reg_idx = 0;
9681         while (i40e_regs_adminq[reg_idx].name) {
9682                 reg_info = &i40e_regs_adminq[reg_idx++];
9683                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9684                         for (arr_idx2 = 0;
9685                                         arr_idx2 <= reg_info->count2;
9686                                         arr_idx2++) {
9687                                 reg_offset = arr_idx * reg_info->stride1 +
9688                                         arr_idx2 * reg_info->stride2;
9689                                 reg_offset += reg_info->base_addr;
9690                                 ptr_data[reg_offset >> 2] =
9691                                         i40e_read_rx_ctl(hw, reg_offset);
9692                         }
9693         }
9694
9695         /* The remaining registers can be read using primitives */
9696         reg_idx = 0;
9697         while (i40e_regs_others[reg_idx].name) {
9698                 reg_info = &i40e_regs_others[reg_idx++];
9699                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9700                         for (arr_idx2 = 0;
9701                                         arr_idx2 <= reg_info->count2;
9702                                         arr_idx2++) {
9703                                 reg_offset = arr_idx * reg_info->stride1 +
9704                                         arr_idx2 * reg_info->stride2;
9705                                 reg_offset += reg_info->base_addr;
9706                                 ptr_data[reg_offset >> 2] =
9707                                         I40E_READ_REG(hw, reg_offset);
9708                         }
9709         }
9710
9711         return 0;
9712 }
9713
9714 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9715 {
9716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9717
9718         /* Convert word count to byte count */
9719         return hw->nvm.sr_size << 1;
9720 }
9721
9722 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9723                            struct rte_dev_eeprom_info *eeprom)
9724 {
9725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9726         uint16_t *data = eeprom->data;
9727         uint16_t offset, length, cnt_words;
9728         int ret_code;
9729
9730         offset = eeprom->offset >> 1;
9731         length = eeprom->length >> 1;
9732         cnt_words = length;
9733
9734         if (offset > hw->nvm.sr_size ||
9735                 offset + length > hw->nvm.sr_size) {
9736                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9737                 return -EINVAL;
9738         }
9739
9740         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9741
9742         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9743         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9744                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9745                 return -EIO;
9746         }
9747
9748         return 0;
9749 }
9750
9751 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9752                                       struct ether_addr *mac_addr)
9753 {
9754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9755
9756         if (!is_valid_assigned_ether_addr(mac_addr)) {
9757                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9758                 return;
9759         }
9760
9761         /* Flags: 0x3 updates port address */
9762         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9763 }
9764
9765 static int
9766 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9767 {
9768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9769         struct rte_eth_dev_data *dev_data = pf->dev_data;
9770         uint32_t frame_size = mtu + ETHER_HDR_LEN
9771                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9772         int ret = 0;
9773
9774         /* check if mtu is within the allowed range */
9775         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9776                 return -EINVAL;
9777
9778         /* mtu setting is forbidden if port is start */
9779         if (dev_data->dev_started) {
9780                 PMD_DRV_LOG(ERR,
9781                             "port %d must be stopped before configuration\n",
9782                             dev_data->port_id);
9783                 return -EBUSY;
9784         }
9785
9786         if (frame_size > ETHER_MAX_LEN)
9787                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9788         else
9789                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9790
9791         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9792
9793         return ret;
9794 }