drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 /* The max bandwidth of i40e is 40Gbps. */
 247 #define I40E_QOS_BW_MAX 40000
 248 /* The bandwidth should be the multiple of 50Mbps. */
 249 #define I40E_QOS_BW_GRANULARITY 50
 250
 251 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 252 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 253 static int i40e_dev_configure(struct rte_eth_dev *dev);
 254 static int i40e_dev_start(struct rte_eth_dev *dev);
 255 static void i40e_dev_stop(struct rte_eth_dev *dev);
 256 static void i40e_dev_close(struct rte_eth_dev *dev);
 257 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 258 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 259 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 260 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 261 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 262 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 263 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 264                                struct rte_eth_stats *stats);
 265 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 266                                struct rte_eth_xstat *xstats, unsigned n);
 267 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 268                                      struct rte_eth_xstat_name *xstats_names,
 269                                      unsigned limit);
 270 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 271 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 272                                             uint16_t queue_id,
 273                                             uint8_t stat_idx,
 274                                             uint8_t is_rx);
 275 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 276                                 char *fw_version, size_t fw_size);
 277 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 278                               struct rte_eth_dev_info *dev_info);
 279 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 280                                 uint16_t vlan_id,
 281                                 int on);
 282 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 283                               enum rte_vlan_type vlan_type,
 284                               uint16_t tpid);
 285 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 286 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 287                                       uint16_t queue,
 288                                       int on);
 289 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 290 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 291 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 292 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 293                               struct rte_eth_fc_conf *fc_conf);
 294 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 295                               struct rte_eth_fc_conf *fc_conf);
 296 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 297                                        struct rte_eth_pfc_conf *pfc_conf);
 298 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 299                           struct ether_addr *mac_addr,
 300                           uint32_t index,
 301                           uint32_t pool);
 302 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 303 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 304                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 305                                     uint16_t reta_size);
 306 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 307                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 308                                    uint16_t reta_size);
 309
 310 static int i40e_get_cap(struct i40e_hw *hw);
 311 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 312 static int i40e_pf_setup(struct i40e_pf *pf);
 313 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 314 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 315 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 316 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 317 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 318                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 319 static void i40e_stat_update_48(struct i40e_hw *hw,
 320                                uint32_t hireg,
 321                                uint32_t loreg,
 322                                bool offset_loaded,
 323                                uint64_t *offset,
 324                                uint64_t *stat);
 325 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 326 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 327                                        void *param);
 328 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 329                                 uint32_t base, uint32_t num);
 330 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 331 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 332                         uint32_t base);
 333 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 334                         uint16_t num);
 335 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 336 static int i40e_veb_release(struct i40e_veb *veb);
 337 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 338                                                 struct i40e_vsi *vsi);
 339 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 340 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 341 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 342                                              struct i40e_macvlan_filter *mv_f,
 343                                              int num,
 344                                              struct ether_addr *addr);
 345 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 346                                              struct i40e_macvlan_filter *mv_f,
 347                                              int num,
 348                                              uint16_t vlan);
 349 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 350 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 351                                     struct rte_eth_rss_conf *rss_conf);
 352 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 353                                       struct rte_eth_rss_conf *rss_conf);
 354 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 355                                         struct rte_eth_udp_tunnel *udp_tunnel);
 356 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 357                                         struct rte_eth_udp_tunnel *udp_tunnel);
 358 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 359 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 360                                 enum rte_filter_op filter_op,
 361                                 void *arg);
 362 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 363                                 enum rte_filter_type filter_type,
 364                                 enum rte_filter_op filter_op,
 365                                 void *arg);
 366 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 367                                   struct rte_eth_dcb_info *dcb_info);
 368 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 369 static void i40e_configure_registers(struct i40e_hw *hw);
 370 static void i40e_hw_init(struct rte_eth_dev *dev);
 371 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 372 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 373                         struct rte_eth_mirror_conf *mirror_conf,
 374                         uint8_t sw_id, uint8_t on);
 375 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 376
 377 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 378 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 379 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 380                                            struct timespec *timestamp,
 381                                            uint32_t flags);
 382 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 383                                            struct timespec *timestamp);
 384 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 385
 386 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 387
 388 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 389                                    struct timespec *timestamp);
 390 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 391                                     const struct timespec *timestamp);
 392
 393 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 394                                          uint16_t queue_id);
 395 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 396                                           uint16_t queue_id);
 397
 398 static int i40e_get_regs(struct rte_eth_dev *dev,
 399                          struct rte_dev_reg_info *regs);
 400
 401 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 402
 403 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 404                            struct rte_dev_eeprom_info *eeprom);
 405
 406 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 407                                       struct ether_addr *mac_addr);
 408
 409 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 410
 411 static int i40e_ethertype_filter_convert(
 412         const struct rte_eth_ethertype_filter *input,
 413         struct i40e_ethertype_filter *filter);
 414 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 415                                    struct i40e_ethertype_filter *filter);
 416
 417 static int i40e_tunnel_filter_convert(
 418         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 419         struct i40e_tunnel_filter *tunnel_filter);
 420 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 421                                 struct i40e_tunnel_filter *tunnel_filter);
 422
 423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 425 static void i40e_filter_restore(struct i40e_pf *pf);
 426
 427 static const struct rte_pci_id pci_id_i40e_map[] = {
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 448         { .vendor_id = 0, /* sentinel */ },
 449 };
 450
 451 static const struct eth_dev_ops i40e_eth_dev_ops = {
 452         .dev_configure                = i40e_dev_configure,
 453         .dev_start                    = i40e_dev_start,
 454         .dev_stop                     = i40e_dev_stop,
 455         .dev_close                    = i40e_dev_close,
 456         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 457         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 458         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 459         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 460         .dev_set_link_up              = i40e_dev_set_link_up,
 461         .dev_set_link_down            = i40e_dev_set_link_down,
 462         .link_update                  = i40e_dev_link_update,
 463         .stats_get                    = i40e_dev_stats_get,
 464         .xstats_get                   = i40e_dev_xstats_get,
 465         .xstats_get_names             = i40e_dev_xstats_get_names,
 466         .stats_reset                  = i40e_dev_stats_reset,
 467         .xstats_reset                 = i40e_dev_stats_reset,
 468         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 469         .fw_version_get               = i40e_fw_version_get,
 470         .dev_infos_get                = i40e_dev_info_get,
 471         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 472         .vlan_filter_set              = i40e_vlan_filter_set,
 473         .vlan_tpid_set                = i40e_vlan_tpid_set,
 474         .vlan_offload_set             = i40e_vlan_offload_set,
 475         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 476         .vlan_pvid_set                = i40e_vlan_pvid_set,
 477         .rx_queue_start               = i40e_dev_rx_queue_start,
 478         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 479         .tx_queue_start               = i40e_dev_tx_queue_start,
 480         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 481         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 482         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 484         .rx_queue_release             = i40e_dev_rx_queue_release,
 485         .rx_queue_count               = i40e_dev_rx_queue_count,
 486         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 487         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 488         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 489         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 490         .tx_queue_release             = i40e_dev_tx_queue_release,
 491         .dev_led_on                   = i40e_dev_led_on,
 492         .dev_led_off                  = i40e_dev_led_off,
 493         .flow_ctrl_get                = i40e_flow_ctrl_get,
 494         .flow_ctrl_set                = i40e_flow_ctrl_set,
 495         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 496         .mac_addr_add                 = i40e_macaddr_add,
 497         .mac_addr_remove              = i40e_macaddr_remove,
 498         .reta_update                  = i40e_dev_rss_reta_update,
 499         .reta_query                   = i40e_dev_rss_reta_query,
 500         .rss_hash_update              = i40e_dev_rss_hash_update,
 501         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 502         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 503         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 504         .filter_ctrl                  = i40e_dev_filter_ctrl,
 505         .rxq_info_get                 = i40e_rxq_info_get,
 506         .txq_info_get                 = i40e_txq_info_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .mac_addr_set                 = i40e_set_default_mac_addr,
 521         .mtu_set                      = i40e_dev_mtu_set,
 522 };
 523
 524 /* store statistics names and its offset in stats structure */
 525 struct rte_i40e_xstats_name_off {
 526         char name[RTE_ETH_XSTATS_NAME_SIZE];
 527         unsigned offset;
 528 };
 529
 530 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 531         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 532         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 533         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 534         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 535         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 536                 rx_unknown_protocol)},
 537         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 538         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 539         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 540         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 541 };
 542
 543 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 544                 sizeof(rte_i40e_stats_strings[0]))
 545
 546 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 547         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 548                 tx_dropped_link_down)},
 549         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 550         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 551                 illegal_bytes)},
 552         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 553         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 554                 mac_local_faults)},
 555         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 556                 mac_remote_faults)},
 557         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_length_errors)},
 559         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 560         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 561         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 562         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 563         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 564         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_127)},
 566         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_255)},
 568         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_511)},
 570         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_1023)},
 572         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_1522)},
 574         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_big)},
 576         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_undersize)},
 578         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_oversize)},
 580         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 581                 mac_short_packet_dropped)},
 582         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_fragments)},
 584         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 585         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 586         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_127)},
 588         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_255)},
 590         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_511)},
 592         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_1023)},
 594         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_1522)},
 596         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_big)},
 598         {"rx_flow_director_atr_match_packets",
 599                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 600         {"rx_flow_director_sb_match_packets",
 601                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 602         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_status)},
 604         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_status)},
 606         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 607                 tx_lpi_count)},
 608         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 609                 rx_lpi_count)},
 610 };
 611
 612 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 613                 sizeof(rte_i40e_hw_port_strings[0]))
 614
 615 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 616         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 617                 priority_xon_rx)},
 618         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xoff_rx)},
 620 };
 621
 622 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 623                 sizeof(rte_i40e_rxq_prio_strings[0]))
 624
 625 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 626         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_tx)},
 628         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 629                 priority_xoff_tx)},
 630         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 631                 priority_xon_2_xoff)},
 632 };
 633
 634 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 635                 sizeof(rte_i40e_txq_prio_strings[0]))
 636
 637 static struct eth_driver rte_i40e_pmd = {
 638         .pci_drv = {
 639                 .id_table = pci_id_i40e_map,
 640                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 641                 .probe = rte_eth_dev_pci_probe,
 642                 .remove = rte_eth_dev_pci_remove,
 643         },
 644         .eth_dev_init = eth_i40e_dev_init,
 645         .eth_dev_uninit = eth_i40e_dev_uninit,
 646         .dev_private_size = sizeof(struct i40e_adapter),
 647 };
 648
 649 static inline int
 650 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 651                                      struct rte_eth_link *link)
 652 {
 653         struct rte_eth_link *dst = link;
 654         struct rte_eth_link *src = &(dev->data->dev_link);
 655
 656         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 657                                         *(uint64_t *)src) == 0)
 658                 return -1;
 659
 660         return 0;
 661 }
 662
 663 static inline int
 664 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 665                                       struct rte_eth_link *link)
 666 {
 667         struct rte_eth_link *dst = &(dev->data->dev_link);
 668         struct rte_eth_link *src = link;
 669
 670         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 671                                         *(uint64_t *)src) == 0)
 672                 return -1;
 673
 674         return 0;
 675 }
 676
 677 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 678 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 679 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 680
 681 #ifndef I40E_GLQF_ORT
 682 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 683 #endif
 684 #ifndef I40E_GLQF_PIT
 685 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 686 #endif
 687
 688 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 689 {
 690         /*
 691          * Initialize registers for flexible payload, which should be set by NVM.
 692          * This should be removed from code once it is fixed in NVM.
 693          */
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 699         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 705         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 706
 707         /* Initialize registers for parsing packet type of QinQ */
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 709         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 710 }
 711
 712 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 713
 714 /*
 715  * Add a ethertype filter to drop all flow control frames transmitted
 716  * from VSIs.
 717 */
 718 static void
 719 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 720 {
 721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 722         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 723                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 724                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 725         int ret;
 726
 727         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 728                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 729                                 pf->main_vsi_seid, 0,
 730                                 TRUE, NULL, NULL);
 731         if (ret)
 732                 PMD_INIT_LOG(ERR,
 733                         "Failed to add filter to drop flow control frames from VSIs.");
 734 }
 735
 736 static int
 737 floating_veb_list_handler(__rte_unused const char *key,
 738                           const char *floating_veb_value,
 739                           void *opaque)
 740 {
 741         int idx = 0;
 742         unsigned int count = 0;
 743         char *end = NULL;
 744         int min, max;
 745         bool *vf_floating_veb = opaque;
 746
 747         while (isblank(*floating_veb_value))
 748                 floating_veb_value++;
 749
 750         /* Reset floating VEB configuration for VFs */
 751         for (idx = 0; idx < I40E_MAX_VF; idx++)
 752                 vf_floating_veb[idx] = false;
 753
 754         min = I40E_MAX_VF;
 755         do {
 756                 while (isblank(*floating_veb_value))
 757                         floating_veb_value++;
 758                 if (*floating_veb_value == '\0')
 759                         return -1;
 760                 errno = 0;
 761                 idx = strtoul(floating_veb_value, &end, 10);
 762                 if (errno || end == NULL)
 763                         return -1;
 764                 while (isblank(*end))
 765                         end++;
 766                 if (*end == '-') {
 767                         min = idx;
 768                 } else if ((*end == ';') || (*end == '\0')) {
 769                         max = idx;
 770                         if (min == I40E_MAX_VF)
 771                                 min = idx;
 772                         if (max >= I40E_MAX_VF)
 773                                 max = I40E_MAX_VF - 1;
 774                         for (idx = min; idx <= max; idx++) {
 775                                 vf_floating_veb[idx] = true;
 776                                 count++;
 777                         }
 778                         min = I40E_MAX_VF;
 779                 } else {
 780                         return -1;
 781                 }
 782                 floating_veb_value = end + 1;
 783         } while (*end != '\0');
 784
 785         if (count == 0)
 786                 return -1;
 787
 788         return 0;
 789 }
 790
 791 static void
 792 config_vf_floating_veb(struct rte_devargs *devargs,
 793                        uint16_t floating_veb,
 794                        bool *vf_floating_veb)
 795 {
 796         struct rte_kvargs *kvlist;
 797         int i;
 798         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 799
 800         if (!floating_veb)
 801                 return;
 802         /* All the VFs attach to the floating VEB by default
 803          * when the floating VEB is enabled.
 804          */
 805         for (i = 0; i < I40E_MAX_VF; i++)
 806                 vf_floating_veb[i] = true;
 807
 808         if (devargs == NULL)
 809                 return;
 810
 811         kvlist = rte_kvargs_parse(devargs->args, NULL);
 812         if (kvlist == NULL)
 813                 return;
 814
 815         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 816                 rte_kvargs_free(kvlist);
 817                 return;
 818         }
 819         /* When the floating_veb_list parameter exists, all the VFs
 820          * will attach to the legacy VEB firstly, then configure VFs
 821          * to the floating VEB according to the floating_veb_list.
 822          */
 823         if (rte_kvargs_process(kvlist, floating_veb_list,
 824                                floating_veb_list_handler,
 825                                vf_floating_veb) < 0) {
 826                 rte_kvargs_free(kvlist);
 827                 return;
 828         }
 829         rte_kvargs_free(kvlist);
 830 }
 831
 832 static int
 833 i40e_check_floating_handler(__rte_unused const char *key,
 834                             const char *value,
 835                             __rte_unused void *opaque)
 836 {
 837         if (strcmp(value, "1"))
 838                 return -1;
 839
 840         return 0;
 841 }
 842
 843 static int
 844 is_floating_veb_supported(struct rte_devargs *devargs)
 845 {
 846         struct rte_kvargs *kvlist;
 847         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 848
 849         if (devargs == NULL)
 850                 return 0;
 851
 852         kvlist = rte_kvargs_parse(devargs->args, NULL);
 853         if (kvlist == NULL)
 854                 return 0;
 855
 856         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 857                 rte_kvargs_free(kvlist);
 858                 return 0;
 859         }
 860         /* Floating VEB is enabled when there's key-value:
 861          * enable_floating_veb=1
 862          */
 863         if (rte_kvargs_process(kvlist, floating_veb_key,
 864                                i40e_check_floating_handler, NULL) < 0) {
 865                 rte_kvargs_free(kvlist);
 866                 return 0;
 867         }
 868         rte_kvargs_free(kvlist);
 869
 870         return 1;
 871 }
 872
 873 static void
 874 config_floating_veb(struct rte_eth_dev *dev)
 875 {
 876         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 879
 880         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 881
 882         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 883                 pf->floating_veb =
 884                         is_floating_veb_supported(pci_dev->device.devargs);
 885                 config_vf_floating_veb(pci_dev->device.devargs,
 886                                        pf->floating_veb,
 887                                        pf->floating_veb_list);
 888         } else {
 889                 pf->floating_veb = false;
 890         }
 891 }
 892
 893 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 894 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 895
 896 static int
 897 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 898 {
 899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 900         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 901         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 902         int ret;
 903
 904         struct rte_hash_parameters ethertype_hash_params = {
 905                 .name = ethertype_hash_name,
 906                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 907                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 908                 .hash_func = rte_hash_crc,
 909                 .hash_func_init_val = 0,
 910                 .socket_id = rte_socket_id(),
 911         };
 912
 913         /* Initialize ethertype filter rule list and hash */
 914         TAILQ_INIT(&ethertype_rule->ethertype_list);
 915         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 916                  "ethertype_%s", dev->data->name);
 917         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 918         if (!ethertype_rule->hash_table) {
 919                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 920                 return -EINVAL;
 921         }
 922         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 923                                        sizeof(struct i40e_ethertype_filter *) *
 924                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 925                                        0);
 926         if (!ethertype_rule->hash_map) {
 927                 PMD_INIT_LOG(ERR,
 928                              "Failed to allocate memory for ethertype hash map!");
 929                 ret = -ENOMEM;
 930                 goto err_ethertype_hash_map_alloc;
 931         }
 932
 933         return 0;
 934
 935 err_ethertype_hash_map_alloc:
 936         rte_hash_free(ethertype_rule->hash_table);
 937
 938         return ret;
 939 }
 940
 941 static int
 942 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 943 {
 944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 945         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 946         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 947         int ret;
 948
 949         struct rte_hash_parameters tunnel_hash_params = {
 950                 .name = tunnel_hash_name,
 951                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 952                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 953                 .hash_func = rte_hash_crc,
 954                 .hash_func_init_val = 0,
 955                 .socket_id = rte_socket_id(),
 956         };
 957
 958         /* Initialize tunnel filter rule list and hash */
 959         TAILQ_INIT(&tunnel_rule->tunnel_list);
 960         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 961                  "tunnel_%s", dev->data->name);
 962         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 963         if (!tunnel_rule->hash_table) {
 964                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 965                 return -EINVAL;
 966         }
 967         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 968                                     sizeof(struct i40e_tunnel_filter *) *
 969                                     I40E_MAX_TUNNEL_FILTER_NUM,
 970                                     0);
 971         if (!tunnel_rule->hash_map) {
 972                 PMD_INIT_LOG(ERR,
 973                              "Failed to allocate memory for tunnel hash map!");
 974                 ret = -ENOMEM;
 975                 goto err_tunnel_hash_map_alloc;
 976         }
 977
 978         return 0;
 979
 980 err_tunnel_hash_map_alloc:
 981         rte_hash_free(tunnel_rule->hash_table);
 982
 983         return ret;
 984 }
 985
 986 static int
 987 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 988 {
 989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 990         struct i40e_fdir_info *fdir_info = &pf->fdir;
 991         char fdir_hash_name[RTE_HASH_NAMESIZE];
 992         int ret;
 993
 994         struct rte_hash_parameters fdir_hash_params = {
 995                 .name = fdir_hash_name,
 996                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 997                 .key_len = sizeof(struct rte_eth_fdir_input),
 998                 .hash_func = rte_hash_crc,
 999                 .hash_func_init_val = 0,
1000                 .socket_id = rte_socket_id(),
1001         };
1002
1003         /* Initialize flow director filter rule list and hash */
1004         TAILQ_INIT(&fdir_info->fdir_list);
1005         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1006                  "fdir_%s", dev->data->name);
1007         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1008         if (!fdir_info->hash_table) {
1009                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1010                 return -EINVAL;
1011         }
1012         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1013                                           sizeof(struct i40e_fdir_filter *) *
1014                                           I40E_MAX_FDIR_FILTER_NUM,
1015                                           0);
1016         if (!fdir_info->hash_map) {
1017                 PMD_INIT_LOG(ERR,
1018                              "Failed to allocate memory for fdir hash map!");
1019                 ret = -ENOMEM;
1020                 goto err_fdir_hash_map_alloc;
1021         }
1022         return 0;
1023
1024 err_fdir_hash_map_alloc:
1025         rte_hash_free(fdir_info->hash_table);
1026
1027         return ret;
1028 }
1029
1030 static int
1031 eth_i40e_dev_init(struct rte_eth_dev *dev)
1032 {
1033         struct rte_pci_device *pci_dev;
1034         struct rte_intr_handle *intr_handle;
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi;
1038         int ret;
1039         uint32_t len;
1040         uint8_t aq_fail = 0;
1041
1042         PMD_INIT_FUNC_TRACE();
1043
1044         dev->dev_ops = &i40e_eth_dev_ops;
1045         dev->rx_pkt_burst = i40e_recv_pkts;
1046         dev->tx_pkt_burst = i40e_xmit_pkts;
1047         dev->tx_pkt_prepare = i40e_prep_pkts;
1048
1049         /* for secondary processes, we don't initialise any further as primary
1050          * has already done this work. Only check we don't need a different
1051          * RX function */
1052         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1053                 i40e_set_rx_function(dev);
1054                 i40e_set_tx_function(dev);
1055                 return 0;
1056         }
1057         pci_dev = I40E_DEV_TO_PCI(dev);
1058         intr_handle = &pci_dev->intr_handle;
1059
1060         rte_eth_copy_pci_info(dev, pci_dev);
1061         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1062
1063         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1064         pf->adapter->eth_dev = dev;
1065         pf->dev_data = dev->data;
1066
1067         hw->back = I40E_PF_TO_ADAPTER(pf);
1068         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1069         if (!hw->hw_addr) {
1070                 PMD_INIT_LOG(ERR,
1071                         "Hardware is not available, as address is NULL");
1072                 return -ENODEV;
1073         }
1074
1075         hw->vendor_id = pci_dev->id.vendor_id;
1076         hw->device_id = pci_dev->id.device_id;
1077         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1078         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1079         hw->bus.device = pci_dev->addr.devid;
1080         hw->bus.func = pci_dev->addr.function;
1081         hw->adapter_stopped = 0;
1082
1083         /* Make sure all is clean before doing PF reset */
1084         i40e_clear_hw(hw);
1085
1086         /* Initialize the hardware */
1087         i40e_hw_init(dev);
1088
1089         /* Reset here to make sure all is clean for each PF */
1090         ret = i40e_pf_reset(hw);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1093                 return ret;
1094         }
1095
1096         /* Initialize the shared code (base driver) */
1097         ret = i40e_init_shared_code(hw);
1098         if (ret) {
1099                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1100                 return ret;
1101         }
1102
1103         /*
1104          * To work around the NVM issue, initialize registers
1105          * for flexible payload and packet type of QinQ by
1106          * software. It should be removed once issues are fixed
1107          * in NVM.
1108          */
1109         i40e_GLQF_reg_init(hw);
1110
1111         /* Initialize the input set for filters (hash and fd) to default value */
1112         i40e_filter_input_set_init(pf);
1113
1114         /* Initialize the parameters for adminq */
1115         i40e_init_adminq_parameter(hw);
1116         ret = i40e_init_adminq(hw);
1117         if (ret != I40E_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1119                 return -EIO;
1120         }
1121         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1122                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1123                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1124                      ((hw->nvm.version >> 12) & 0xf),
1125                      ((hw->nvm.version >> 4) & 0xff),
1126                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1127
1128         /* Need the special FW version to support floating VEB */
1129         config_floating_veb(dev);
1130         /* Clear PXE mode */
1131         i40e_clear_pxe_mode(hw);
1132         ret = i40e_dev_sync_phy_type(hw);
1133         if (ret) {
1134                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1135                 goto err_sync_phy_type;
1136         }
1137         /*
1138          * On X710, performance number is far from the expectation on recent
1139          * firmware versions. The fix for this issue may not be integrated in
1140          * the following firmware version. So the workaround in software driver
1141          * is needed. It needs to modify the initial values of 3 internal only
1142          * registers. Note that the workaround can be removed when it is fixed
1143          * in firmware in the future.
1144          */
1145         i40e_configure_registers(hw);
1146
1147         /* Get hw capabilities */
1148         ret = i40e_get_cap(hw);
1149         if (ret != I40E_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1151                 goto err_get_capabilities;
1152         }
1153
1154         /* Initialize parameters for PF */
1155         ret = i40e_pf_parameter_init(dev);
1156         if (ret != 0) {
1157                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1158                 goto err_parameter_init;
1159         }
1160
1161         /* Initialize the queue management */
1162         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1163         if (ret < 0) {
1164                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1165                 goto err_qp_pool_init;
1166         }
1167         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1168                                 hw->func_caps.num_msix_vectors - 1);
1169         if (ret < 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1171                 goto err_msix_pool_init;
1172         }
1173
1174         /* Initialize lan hmc */
1175         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1176                                 hw->func_caps.num_rx_qp, 0, 0);
1177         if (ret != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1179                 goto err_init_lan_hmc;
1180         }
1181
1182         /* Configure lan hmc */
1183         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1184         if (ret != I40E_SUCCESS) {
1185                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1186                 goto err_configure_lan_hmc;
1187         }
1188
1189         /* Get and check the mac address */
1190         i40e_get_mac_addr(hw, hw->mac.addr);
1191         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "mac address is not valid");
1193                 ret = -EIO;
1194                 goto err_get_mac_addr;
1195         }
1196         /* Copy the permanent MAC address */
1197         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1198                         (struct ether_addr *) hw->mac.perm_addr);
1199
1200         /* Disable flow control */
1201         hw->fc.requested_mode = I40E_FC_NONE;
1202         i40e_set_fc(hw, &aq_fail, TRUE);
1203
1204         /* Set the global registers with default ether type value */
1205         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1206         if (ret != I40E_SUCCESS) {
1207                 PMD_INIT_LOG(ERR,
1208                         "Failed to set the default outer VLAN ether type");
1209                 goto err_setup_pf_switch;
1210         }
1211
1212         /* PF setup, which includes VSI setup */
1213         ret = i40e_pf_setup(pf);
1214         if (ret) {
1215                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1216                 goto err_setup_pf_switch;
1217         }
1218
1219         /* reset all stats of the device, including pf and main vsi */
1220         i40e_dev_stats_reset(dev);
1221
1222         vsi = pf->main_vsi;
1223
1224         /* Disable double vlan by default */
1225         i40e_vsi_config_double_vlan(vsi, FALSE);
1226
1227         /* Disable S-TAG identification when floating_veb is disabled */
1228         if (!pf->floating_veb) {
1229                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1230                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1231                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1232                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1233                 }
1234         }
1235
1236         if (!vsi->max_macaddrs)
1237                 len = ETHER_ADDR_LEN;
1238         else
1239                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1240
1241         /* Should be after VSI initialized */
1242         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1243         if (!dev->data->mac_addrs) {
1244                 PMD_INIT_LOG(ERR,
1245                         "Failed to allocated memory for storing mac address");
1246                 goto err_mac_alloc;
1247         }
1248         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1249                                         &dev->data->mac_addrs[0]);
1250
1251         /* Init dcb to sw mode by default */
1252         ret = i40e_dcb_init_configure(dev, TRUE);
1253         if (ret != I40E_SUCCESS) {
1254                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1255                 pf->flags &= ~I40E_FLAG_DCB;
1256         }
1257         /* Update HW struct after DCB configuration */
1258         i40e_get_cap(hw);
1259
1260         /* initialize pf host driver to setup SRIOV resource if applicable */
1261         i40e_pf_host_init(dev);
1262
1263         /* register callback func to eal lib */
1264         rte_intr_callback_register(intr_handle,
1265                                    i40e_dev_interrupt_handler, dev);
1266
1267         /* configure and enable device interrupt */
1268         i40e_pf_config_irq0(hw, TRUE);
1269         i40e_pf_enable_irq0(hw);
1270
1271         /* enable uio intr after callback register */
1272         rte_intr_enable(intr_handle);
1273         /*
1274          * Add an ethertype filter to drop all flow control frames transmitted
1275          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1276          * frames to wire.
1277          */
1278         i40e_add_tx_flow_control_drop_filter(pf);
1279
1280         /* Set the max frame size to 0x2600 by default,
1281          * in case other drivers changed the default value.
1282          */
1283         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1284
1285         /* initialize mirror rule list */
1286         TAILQ_INIT(&pf->mirror_list);
1287
1288         ret = i40e_init_ethtype_filter_list(dev);
1289         if (ret < 0)
1290                 goto err_init_ethtype_filter_list;
1291         ret = i40e_init_tunnel_filter_list(dev);
1292         if (ret < 0)
1293                 goto err_init_tunnel_filter_list;
1294         ret = i40e_init_fdir_filter_list(dev);
1295         if (ret < 0)
1296                 goto err_init_fdir_filter_list;
1297
1298         return 0;
1299
1300 err_init_fdir_filter_list:
1301         rte_free(pf->tunnel.hash_table);
1302         rte_free(pf->tunnel.hash_map);
1303 err_init_tunnel_filter_list:
1304         rte_free(pf->ethertype.hash_table);
1305         rte_free(pf->ethertype.hash_map);
1306 err_init_ethtype_filter_list:
1307         rte_free(dev->data->mac_addrs);
1308 err_mac_alloc:
1309         i40e_vsi_release(pf->main_vsi);
1310 err_setup_pf_switch:
1311 err_get_mac_addr:
1312 err_configure_lan_hmc:
1313         (void)i40e_shutdown_lan_hmc(hw);
1314 err_init_lan_hmc:
1315         i40e_res_pool_destroy(&pf->msix_pool);
1316 err_msix_pool_init:
1317         i40e_res_pool_destroy(&pf->qp_pool);
1318 err_qp_pool_init:
1319 err_parameter_init:
1320 err_get_capabilities:
1321 err_sync_phy_type:
1322         (void)i40e_shutdown_adminq(hw);
1323
1324         return ret;
1325 }
1326
1327 static void
1328 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1329 {
1330         struct i40e_ethertype_filter *p_ethertype;
1331         struct i40e_ethertype_rule *ethertype_rule;
1332
1333         ethertype_rule = &pf->ethertype;
1334         /* Remove all ethertype filter rules and hash */
1335         if (ethertype_rule->hash_map)
1336                 rte_free(ethertype_rule->hash_map);
1337         if (ethertype_rule->hash_table)
1338                 rte_hash_free(ethertype_rule->hash_table);
1339
1340         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1341                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1342                              p_ethertype, rules);
1343                 rte_free(p_ethertype);
1344         }
1345 }
1346
1347 static void
1348 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1349 {
1350         struct i40e_tunnel_filter *p_tunnel;
1351         struct i40e_tunnel_rule *tunnel_rule;
1352
1353         tunnel_rule = &pf->tunnel;
1354         /* Remove all tunnel director rules and hash */
1355         if (tunnel_rule->hash_map)
1356                 rte_free(tunnel_rule->hash_map);
1357         if (tunnel_rule->hash_table)
1358                 rte_hash_free(tunnel_rule->hash_table);
1359
1360         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1361                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1362                 rte_free(p_tunnel);
1363         }
1364 }
1365
1366 static void
1367 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1368 {
1369         struct i40e_fdir_filter *p_fdir;
1370         struct i40e_fdir_info *fdir_info;
1371
1372         fdir_info = &pf->fdir;
1373         /* Remove all flow director rules and hash */
1374         if (fdir_info->hash_map)
1375                 rte_free(fdir_info->hash_map);
1376         if (fdir_info->hash_table)
1377                 rte_hash_free(fdir_info->hash_table);
1378
1379         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1380                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1381                 rte_free(p_fdir);
1382         }
1383 }
1384
1385 static int
1386 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1387 {
1388         struct i40e_pf *pf;
1389         struct rte_pci_device *pci_dev;
1390         struct rte_intr_handle *intr_handle;
1391         struct i40e_hw *hw;
1392         struct i40e_filter_control_settings settings;
1393         struct rte_flow *p_flow;
1394         int ret;
1395         uint8_t aq_fail = 0;
1396
1397         PMD_INIT_FUNC_TRACE();
1398
1399         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1400                 return 0;
1401
1402         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1403         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404         pci_dev = I40E_DEV_TO_PCI(dev);
1405         intr_handle = &pci_dev->intr_handle;
1406
1407         if (hw->adapter_stopped == 0)
1408                 i40e_dev_close(dev);
1409
1410         dev->dev_ops = NULL;
1411         dev->rx_pkt_burst = NULL;
1412         dev->tx_pkt_burst = NULL;
1413
1414         /* Clear PXE mode */
1415         i40e_clear_pxe_mode(hw);
1416
1417         /* Unconfigure filter control */
1418         memset(&settings, 0, sizeof(settings));
1419         ret = i40e_set_filter_control(hw, &settings);
1420         if (ret)
1421                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1422                                         ret);
1423
1424         /* Disable flow control */
1425         hw->fc.requested_mode = I40E_FC_NONE;
1426         i40e_set_fc(hw, &aq_fail, TRUE);
1427
1428         /* uninitialize pf host driver */
1429         i40e_pf_host_uninit(dev);
1430
1431         rte_free(dev->data->mac_addrs);
1432         dev->data->mac_addrs = NULL;
1433
1434         /* disable uio intr before callback unregister */
1435         rte_intr_disable(intr_handle);
1436
1437         /* register callback func to eal lib */
1438         rte_intr_callback_unregister(intr_handle,
1439                                      i40e_dev_interrupt_handler, dev);
1440
1441         i40e_rm_ethtype_filter_list(pf);
1442         i40e_rm_tunnel_filter_list(pf);
1443         i40e_rm_fdir_filter_list(pf);
1444
1445         /* Remove all flows */
1446         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1447                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1448                 rte_free(p_flow);
1449         }
1450
1451         return 0;
1452 }
1453
1454 static int
1455 i40e_dev_configure(struct rte_eth_dev *dev)
1456 {
1457         struct i40e_adapter *ad =
1458                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1459         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1460         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1461         int i, ret;
1462
1463         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1464          * bulk allocation or vector Rx preconditions we will reset it.
1465          */
1466         ad->rx_bulk_alloc_allowed = true;
1467         ad->rx_vec_allowed = true;
1468         ad->tx_simple_allowed = true;
1469         ad->tx_vec_allowed = true;
1470
1471         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1472                 ret = i40e_fdir_setup(pf);
1473                 if (ret != I40E_SUCCESS) {
1474                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1475                         return -ENOTSUP;
1476                 }
1477                 ret = i40e_fdir_configure(dev);
1478                 if (ret < 0) {
1479                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1480                         goto err;
1481                 }
1482         } else
1483                 i40e_fdir_teardown(pf);
1484
1485         ret = i40e_dev_init_vlan(dev);
1486         if (ret < 0)
1487                 goto err;
1488
1489         /* VMDQ setup.
1490          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1491          *  RSS setting have different requirements.
1492          *  General PMD driver call sequence are NIC init, configure,
1493          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1494          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1495          *  applicable. So, VMDQ setting has to be done before
1496          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1497          *  For RSS setting, it will try to calculate actual configured RX queue
1498          *  number, which will be available after rx_queue_setup(). dev_start()
1499          *  function is good to place RSS setup.
1500          */
1501         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1502                 ret = i40e_vmdq_setup(dev);
1503                 if (ret)
1504                         goto err;
1505         }
1506
1507         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1508                 ret = i40e_dcb_setup(dev);
1509                 if (ret) {
1510                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1511                         goto err_dcb;
1512                 }
1513         }
1514
1515         TAILQ_INIT(&pf->flow_list);
1516
1517         return 0;
1518
1519 err_dcb:
1520         /* need to release vmdq resource if exists */
1521         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1522                 i40e_vsi_release(pf->vmdq[i].vsi);
1523                 pf->vmdq[i].vsi = NULL;
1524         }
1525         rte_free(pf->vmdq);
1526         pf->vmdq = NULL;
1527 err:
1528         /* need to release fdir resource if exists */
1529         i40e_fdir_teardown(pf);
1530         return ret;
1531 }
1532
1533 void
1534 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1535 {
1536         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1537         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1540         uint16_t msix_vect = vsi->msix_intr;
1541         uint16_t i;
1542
1543         for (i = 0; i < vsi->nb_qps; i++) {
1544                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1545                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1546                 rte_wmb();
1547         }
1548
1549         if (vsi->type != I40E_VSI_SRIOV) {
1550                 if (!rte_intr_allow_others(intr_handle)) {
1551                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1552                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1553                         I40E_WRITE_REG(hw,
1554                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1555                                        0);
1556                 } else {
1557                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1558                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1559                         I40E_WRITE_REG(hw,
1560                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1561                                                        msix_vect - 1), 0);
1562                 }
1563         } else {
1564                 uint32_t reg;
1565                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1566                         vsi->user_param + (msix_vect - 1);
1567
1568                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1569                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1570         }
1571         I40E_WRITE_FLUSH(hw);
1572 }
1573
1574 static void
1575 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1576                        int base_queue, int nb_queue)
1577 {
1578         int i;
1579         uint32_t val;
1580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1581
1582         /* Bind all RX queues to allocated MSIX interrupt */
1583         for (i = 0; i < nb_queue; i++) {
1584                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1585                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1586                         ((base_queue + i + 1) <<
1587                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1588                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1589                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1590
1591                 if (i == nb_queue - 1)
1592                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1593                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1594         }
1595
1596         /* Write first RX queue to Link list register as the head element */
1597         if (vsi->type != I40E_VSI_SRIOV) {
1598                 uint16_t interval =
1599                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1600
1601                 if (msix_vect == I40E_MISC_VEC_ID) {
1602                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1603                                        (base_queue <<
1604                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1605                                        (0x0 <<
1606                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1607                         I40E_WRITE_REG(hw,
1608                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1609                                        interval);
1610                 } else {
1611                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1612                                        (base_queue <<
1613                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1614                                        (0x0 <<
1615                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1616                         I40E_WRITE_REG(hw,
1617                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1618                                                        msix_vect - 1),
1619                                        interval);
1620                 }
1621         } else {
1622                 uint32_t reg;
1623
1624                 if (msix_vect == I40E_MISC_VEC_ID) {
1625                         I40E_WRITE_REG(hw,
1626                                        I40E_VPINT_LNKLST0(vsi->user_param),
1627                                        (base_queue <<
1628                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1629                                        (0x0 <<
1630                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1631                 } else {
1632                         /* num_msix_vectors_vf needs to minus irq0 */
1633                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1634                                 vsi->user_param + (msix_vect - 1);
1635
1636                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1637                                        (base_queue <<
1638                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1639                                        (0x0 <<
1640                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1641                 }
1642         }
1643
1644         I40E_WRITE_FLUSH(hw);
1645 }
1646
1647 void
1648 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1649 {
1650         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1651         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1652         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1653         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1654         uint16_t msix_vect = vsi->msix_intr;
1655         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1656         uint16_t queue_idx = 0;
1657         int record = 0;
1658         uint32_t val;
1659         int i;
1660
1661         for (i = 0; i < vsi->nb_qps; i++) {
1662                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1663                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1664         }
1665
1666         /* INTENA flag is not auto-cleared for interrupt */
1667         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1668         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1669                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1670                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1671         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1672
1673         /* VF bind interrupt */
1674         if (vsi->type == I40E_VSI_SRIOV) {
1675                 __vsi_queues_bind_intr(vsi, msix_vect,
1676                                        vsi->base_queue, vsi->nb_qps);
1677                 return;
1678         }
1679
1680         /* PF & VMDq bind interrupt */
1681         if (rte_intr_dp_is_en(intr_handle)) {
1682                 if (vsi->type == I40E_VSI_MAIN) {
1683                         queue_idx = 0;
1684                         record = 1;
1685                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1686                         struct i40e_vsi *main_vsi =
1687                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1688                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1689                         record = 1;
1690                 }
1691         }
1692
1693         for (i = 0; i < vsi->nb_used_qps; i++) {
1694                 if (nb_msix <= 1) {
1695                         if (!rte_intr_allow_others(intr_handle))
1696                                 /* allow to share MISC_VEC_ID */
1697                                 msix_vect = I40E_MISC_VEC_ID;
1698
1699                         /* no enough msix_vect, map all to one */
1700                         __vsi_queues_bind_intr(vsi, msix_vect,
1701                                                vsi->base_queue + i,
1702                                                vsi->nb_used_qps - i);
1703                         for (; !!record && i < vsi->nb_used_qps; i++)
1704                                 intr_handle->intr_vec[queue_idx + i] =
1705                                         msix_vect;
1706                         break;
1707                 }
1708                 /* 1:1 queue/msix_vect mapping */
1709                 __vsi_queues_bind_intr(vsi, msix_vect,
1710                                        vsi->base_queue + i, 1);
1711                 if (!!record)
1712                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1713
1714                 msix_vect++;
1715                 nb_msix--;
1716         }
1717 }
1718
1719 static void
1720 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1721 {
1722         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1723         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1724         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1725         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1726         uint16_t interval = i40e_calc_itr_interval(\
1727                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1728         uint16_t msix_intr, i;
1729
1730         if (rte_intr_allow_others(intr_handle))
1731                 for (i = 0; i < vsi->nb_msix; i++) {
1732                         msix_intr = vsi->msix_intr + i;
1733                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1734                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1735                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1736                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1737                                 (interval <<
1738                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1739                 }
1740         else
1741                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1742                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1743                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1744                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1745                                (interval <<
1746                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1747
1748         I40E_WRITE_FLUSH(hw);
1749 }
1750
1751 static void
1752 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1753 {
1754         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1755         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1756         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1757         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1758         uint16_t msix_intr, i;
1759
1760         if (rte_intr_allow_others(intr_handle))
1761                 for (i = 0; i < vsi->nb_msix; i++) {
1762                         msix_intr = vsi->msix_intr + i;
1763                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1764                                        0);
1765                 }
1766         else
1767                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static inline uint8_t
1773 i40e_parse_link_speeds(uint16_t link_speeds)
1774 {
1775         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1776
1777         if (link_speeds & ETH_LINK_SPEED_40G)
1778                 link_speed |= I40E_LINK_SPEED_40GB;
1779         if (link_speeds & ETH_LINK_SPEED_25G)
1780                 link_speed |= I40E_LINK_SPEED_25GB;
1781         if (link_speeds & ETH_LINK_SPEED_20G)
1782                 link_speed |= I40E_LINK_SPEED_20GB;
1783         if (link_speeds & ETH_LINK_SPEED_10G)
1784                 link_speed |= I40E_LINK_SPEED_10GB;
1785         if (link_speeds & ETH_LINK_SPEED_1G)
1786                 link_speed |= I40E_LINK_SPEED_1GB;
1787         if (link_speeds & ETH_LINK_SPEED_100M)
1788                 link_speed |= I40E_LINK_SPEED_100MB;
1789
1790         return link_speed;
1791 }
1792
1793 static int
1794 i40e_phy_conf_link(struct i40e_hw *hw,
1795                    uint8_t abilities,
1796                    uint8_t force_speed)
1797 {
1798         enum i40e_status_code status;
1799         struct i40e_aq_get_phy_abilities_resp phy_ab;
1800         struct i40e_aq_set_phy_config phy_conf;
1801         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1802                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1803                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1804                         I40E_AQ_PHY_FLAG_LOW_POWER;
1805         const uint8_t advt = I40E_LINK_SPEED_40GB |
1806                         I40E_LINK_SPEED_25GB |
1807                         I40E_LINK_SPEED_10GB |
1808                         I40E_LINK_SPEED_1GB |
1809                         I40E_LINK_SPEED_100MB;
1810         int ret = -ENOTSUP;
1811
1812
1813         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1814                                               NULL);
1815         if (status)
1816                 return ret;
1817
1818         memset(&phy_conf, 0, sizeof(phy_conf));
1819
1820         /* bits 0-2 use the values from get_phy_abilities_resp */
1821         abilities &= ~mask;
1822         abilities |= phy_ab.abilities & mask;
1823
1824         /* update ablities and speed */
1825         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1826                 phy_conf.link_speed = advt;
1827         else
1828                 phy_conf.link_speed = force_speed;
1829
1830         phy_conf.abilities = abilities;
1831
1832         /* use get_phy_abilities_resp value for the rest */
1833         phy_conf.phy_type = phy_ab.phy_type;
1834         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1835         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1836         phy_conf.eee_capability = phy_ab.eee_capability;
1837         phy_conf.eeer = phy_ab.eeer_val;
1838         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1839
1840         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1841                     phy_ab.abilities, phy_ab.link_speed);
1842         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1843                     phy_conf.abilities, phy_conf.link_speed);
1844
1845         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1846         if (status)
1847                 return ret;
1848
1849         return I40E_SUCCESS;
1850 }
1851
1852 static int
1853 i40e_apply_link_speed(struct rte_eth_dev *dev)
1854 {
1855         uint8_t speed;
1856         uint8_t abilities = 0;
1857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         struct rte_eth_conf *conf = &dev->data->dev_conf;
1859
1860         speed = i40e_parse_link_speeds(conf->link_speeds);
1861         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1862         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1863                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1864         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1865
1866         /* Skip changing speed on 40G interfaces, FW does not support */
1867         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1868                 speed =  I40E_LINK_SPEED_UNKNOWN;
1869                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1870         }
1871
1872         return i40e_phy_conf_link(hw, abilities, speed);
1873 }
1874
1875 static int
1876 i40e_dev_start(struct rte_eth_dev *dev)
1877 {
1878         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880         struct i40e_vsi *main_vsi = pf->main_vsi;
1881         int ret, i;
1882         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1883         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1884         uint32_t intr_vector = 0;
1885         struct i40e_vsi *vsi;
1886
1887         hw->adapter_stopped = 0;
1888
1889         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1890                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1891                              dev->data->port_id);
1892                 return -EINVAL;
1893         }
1894
1895         rte_intr_disable(intr_handle);
1896
1897         if ((rte_intr_cap_multiple(intr_handle) ||
1898              !RTE_ETH_DEV_SRIOV(dev).active) &&
1899             dev->data->dev_conf.intr_conf.rxq != 0) {
1900                 intr_vector = dev->data->nb_rx_queues;
1901                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1902                 if (ret)
1903                         return ret;
1904         }
1905
1906         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1907                 intr_handle->intr_vec =
1908                         rte_zmalloc("intr_vec",
1909                                     dev->data->nb_rx_queues * sizeof(int),
1910                                     0);
1911                 if (!intr_handle->intr_vec) {
1912                         PMD_INIT_LOG(ERR,
1913                                 "Failed to allocate %d rx_queues intr_vec",
1914                                 dev->data->nb_rx_queues);
1915                         return -ENOMEM;
1916                 }
1917         }
1918
1919         /* Initialize VSI */
1920         ret = i40e_dev_rxtx_init(pf);
1921         if (ret != I40E_SUCCESS) {
1922                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1923                 goto err_up;
1924         }
1925
1926         /* Map queues with MSIX interrupt */
1927         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1928                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1929         i40e_vsi_queues_bind_intr(main_vsi);
1930         i40e_vsi_enable_queues_intr(main_vsi);
1931
1932         /* Map VMDQ VSI queues with MSIX interrupt */
1933         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1934                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1935                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1936                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1937         }
1938
1939         /* enable FDIR MSIX interrupt */
1940         if (pf->fdir.fdir_vsi) {
1941                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1942                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1943         }
1944
1945         /* Enable all queues which have been configured */
1946         ret = i40e_dev_switch_queues(pf, TRUE);
1947         if (ret != I40E_SUCCESS) {
1948                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1949                 goto err_up;
1950         }
1951
1952         /* Enable receiving broadcast packets */
1953         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1954         if (ret != I40E_SUCCESS)
1955                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1956
1957         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1958                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1959                                                 true, NULL);
1960                 if (ret != I40E_SUCCESS)
1961                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1962         }
1963
1964         /* Enable the VLAN promiscuous mode. */
1965         if (pf->vfs) {
1966                 for (i = 0; i < pf->vf_num; i++) {
1967                         vsi = pf->vfs[i].vsi;
1968                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1969                                                      true, NULL);
1970                 }
1971         }
1972
1973         /* Apply link configure */
1974         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1975                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1976                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1977                                 ETH_LINK_SPEED_40G)) {
1978                 PMD_DRV_LOG(ERR, "Invalid link setting");
1979                 goto err_up;
1980         }
1981         ret = i40e_apply_link_speed(dev);
1982         if (I40E_SUCCESS != ret) {
1983                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1984                 goto err_up;
1985         }
1986
1987         if (!rte_intr_allow_others(intr_handle)) {
1988                 rte_intr_callback_unregister(intr_handle,
1989                                              i40e_dev_interrupt_handler,
1990                                              (void *)dev);
1991                 /* configure and enable device interrupt */
1992                 i40e_pf_config_irq0(hw, FALSE);
1993                 i40e_pf_enable_irq0(hw);
1994
1995                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1996                         PMD_INIT_LOG(INFO,
1997                                 "lsc won't enable because of no intr multiplex");
1998         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1999                 ret = i40e_aq_set_phy_int_mask(hw,
2000                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2001                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2002                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2003                 if (ret != I40E_SUCCESS)
2004                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2005
2006                 /* Call get_link_info aq commond to enable LSE */
2007                 i40e_dev_link_update(dev, 0);
2008         }
2009
2010         /* enable uio intr after callback register */
2011         rte_intr_enable(intr_handle);
2012
2013         i40e_filter_restore(pf);
2014
2015         return I40E_SUCCESS;
2016
2017 err_up:
2018         i40e_dev_switch_queues(pf, FALSE);
2019         i40e_dev_clear_queues(dev);
2020
2021         return ret;
2022 }
2023
2024 static void
2025 i40e_dev_stop(struct rte_eth_dev *dev)
2026 {
2027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2028         struct i40e_vsi *main_vsi = pf->main_vsi;
2029         struct i40e_mirror_rule *p_mirror;
2030         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2031         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2032         int i;
2033
2034         /* Disable all queues */
2035         i40e_dev_switch_queues(pf, FALSE);
2036
2037         /* un-map queues with interrupt registers */
2038         i40e_vsi_disable_queues_intr(main_vsi);
2039         i40e_vsi_queues_unbind_intr(main_vsi);
2040
2041         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2042                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2043                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2044         }
2045
2046         if (pf->fdir.fdir_vsi) {
2047                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2048                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2049         }
2050         /* Clear all queues and release memory */
2051         i40e_dev_clear_queues(dev);
2052
2053         /* Set link down */
2054         i40e_dev_set_link_down(dev);
2055
2056         /* Remove all mirror rules */
2057         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2058                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2059                 rte_free(p_mirror);
2060         }
2061         pf->nb_mirror_rule = 0;
2062
2063         if (!rte_intr_allow_others(intr_handle))
2064                 /* resume to the default handler */
2065                 rte_intr_callback_register(intr_handle,
2066                                            i40e_dev_interrupt_handler,
2067                                            (void *)dev);
2068
2069         /* Clean datapath event and queue/vec mapping */
2070         rte_intr_efd_disable(intr_handle);
2071         if (intr_handle->intr_vec) {
2072                 rte_free(intr_handle->intr_vec);
2073                 intr_handle->intr_vec = NULL;
2074         }
2075 }
2076
2077 static void
2078 i40e_dev_close(struct rte_eth_dev *dev)
2079 {
2080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2083         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2084         uint32_t reg;
2085         int i;
2086
2087         PMD_INIT_FUNC_TRACE();
2088
2089         i40e_dev_stop(dev);
2090         hw->adapter_stopped = 1;
2091         i40e_dev_free_queues(dev);
2092
2093         /* Disable interrupt */
2094         i40e_pf_disable_irq0(hw);
2095         rte_intr_disable(intr_handle);
2096
2097         /* shutdown and destroy the HMC */
2098         i40e_shutdown_lan_hmc(hw);
2099
2100         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2101                 i40e_vsi_release(pf->vmdq[i].vsi);
2102                 pf->vmdq[i].vsi = NULL;
2103         }
2104         rte_free(pf->vmdq);
2105         pf->vmdq = NULL;
2106
2107         /* release all the existing VSIs and VEBs */
2108         i40e_fdir_teardown(pf);
2109         i40e_vsi_release(pf->main_vsi);
2110
2111         /* shutdown the adminq */
2112         i40e_aq_queue_shutdown(hw, true);
2113         i40e_shutdown_adminq(hw);
2114
2115         i40e_res_pool_destroy(&pf->qp_pool);
2116         i40e_res_pool_destroy(&pf->msix_pool);
2117
2118         /* force a PF reset to clean anything leftover */
2119         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2120         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2121                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2122         I40E_WRITE_FLUSH(hw);
2123 }
2124
2125 static void
2126 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2127 {
2128         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130         struct i40e_vsi *vsi = pf->main_vsi;
2131         int status;
2132
2133         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2134                                                      true, NULL, true);
2135         if (status != I40E_SUCCESS)
2136                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2137
2138         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2139                                                         TRUE, NULL);
2140         if (status != I40E_SUCCESS)
2141                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2142
2143 }
2144
2145 static void
2146 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2147 {
2148         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct i40e_vsi *vsi = pf->main_vsi;
2151         int status;
2152
2153         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2154                                                      false, NULL, true);
2155         if (status != I40E_SUCCESS)
2156                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2157
2158         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2159                                                         false, NULL);
2160         if (status != I40E_SUCCESS)
2161                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2162 }
2163
2164 static void
2165 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2166 {
2167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct i40e_vsi *vsi = pf->main_vsi;
2170         int ret;
2171
2172         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2173         if (ret != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2175 }
2176
2177 static void
2178 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2179 {
2180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         struct i40e_vsi *vsi = pf->main_vsi;
2183         int ret;
2184
2185         if (dev->data->promiscuous == 1)
2186                 return; /* must remain in all_multicast mode */
2187
2188         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2189                                 vsi->seid, FALSE, NULL);
2190         if (ret != I40E_SUCCESS)
2191                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2192 }
2193
2194 /*
2195  * Set device link up.
2196  */
2197 static int
2198 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2199 {
2200         /* re-apply link speed setting */
2201         return i40e_apply_link_speed(dev);
2202 }
2203
2204 /*
2205  * Set device link down.
2206  */
2207 static int
2208 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2209 {
2210         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2211         uint8_t abilities = 0;
2212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2213
2214         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2215         return i40e_phy_conf_link(hw, abilities, speed);
2216 }
2217
2218 int
2219 i40e_dev_link_update(struct rte_eth_dev *dev,
2220                      int wait_to_complete)
2221 {
2222 #define CHECK_INTERVAL 100  /* 100ms */
2223 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         struct i40e_link_status link_status;
2226         struct rte_eth_link link, old;
2227         int status;
2228         unsigned rep_cnt = MAX_REPEAT_TIME;
2229         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2230
2231         memset(&link, 0, sizeof(link));
2232         memset(&old, 0, sizeof(old));
2233         memset(&link_status, 0, sizeof(link_status));
2234         rte_i40e_dev_atomic_read_link_status(dev, &old);
2235
2236         do {
2237                 /* Get link status information from hardware */
2238                 status = i40e_aq_get_link_info(hw, enable_lse,
2239                                                 &link_status, NULL);
2240                 if (status != I40E_SUCCESS) {
2241                         link.link_speed = ETH_SPEED_NUM_100M;
2242                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2243                         PMD_DRV_LOG(ERR, "Failed to get link info");
2244                         goto out;
2245                 }
2246
2247                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2248                 if (!wait_to_complete || link.link_status)
2249                         break;
2250
2251                 rte_delay_ms(CHECK_INTERVAL);
2252         } while (--rep_cnt);
2253
2254         if (!link.link_status)
2255                 goto out;
2256
2257         /* i40e uses full duplex only */
2258         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2259
2260         /* Parse the link status */
2261         switch (link_status.link_speed) {
2262         case I40E_LINK_SPEED_100MB:
2263                 link.link_speed = ETH_SPEED_NUM_100M;
2264                 break;
2265         case I40E_LINK_SPEED_1GB:
2266                 link.link_speed = ETH_SPEED_NUM_1G;
2267                 break;
2268         case I40E_LINK_SPEED_10GB:
2269                 link.link_speed = ETH_SPEED_NUM_10G;
2270                 break;
2271         case I40E_LINK_SPEED_20GB:
2272                 link.link_speed = ETH_SPEED_NUM_20G;
2273                 break;
2274         case I40E_LINK_SPEED_25GB:
2275                 link.link_speed = ETH_SPEED_NUM_25G;
2276                 break;
2277         case I40E_LINK_SPEED_40GB:
2278                 link.link_speed = ETH_SPEED_NUM_40G;
2279                 break;
2280         default:
2281                 link.link_speed = ETH_SPEED_NUM_100M;
2282                 break;
2283         }
2284
2285         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2286                         ETH_LINK_SPEED_FIXED);
2287
2288 out:
2289         rte_i40e_dev_atomic_write_link_status(dev, &link);
2290         if (link.link_status == old.link_status)
2291                 return -1;
2292
2293         return 0;
2294 }
2295
2296 /* Get all the statistics of a VSI */
2297 void
2298 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2299 {
2300         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2301         struct i40e_eth_stats *nes = &vsi->eth_stats;
2302         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2303         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2304
2305         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2306                             vsi->offset_loaded, &oes->rx_bytes,
2307                             &nes->rx_bytes);
2308         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2309                             vsi->offset_loaded, &oes->rx_unicast,
2310                             &nes->rx_unicast);
2311         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2312                             vsi->offset_loaded, &oes->rx_multicast,
2313                             &nes->rx_multicast);
2314         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2315                             vsi->offset_loaded, &oes->rx_broadcast,
2316                             &nes->rx_broadcast);
2317         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2318                             &oes->rx_discards, &nes->rx_discards);
2319         /* GLV_REPC not supported */
2320         /* GLV_RMPC not supported */
2321         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2322                             &oes->rx_unknown_protocol,
2323                             &nes->rx_unknown_protocol);
2324         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2325                             vsi->offset_loaded, &oes->tx_bytes,
2326                             &nes->tx_bytes);
2327         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2328                             vsi->offset_loaded, &oes->tx_unicast,
2329                             &nes->tx_unicast);
2330         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2331                             vsi->offset_loaded, &oes->tx_multicast,
2332                             &nes->tx_multicast);
2333         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2334                             vsi->offset_loaded,  &oes->tx_broadcast,
2335                             &nes->tx_broadcast);
2336         /* GLV_TDPC not supported */
2337         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2338                             &oes->tx_errors, &nes->tx_errors);
2339         vsi->offset_loaded = true;
2340
2341         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2342                     vsi->vsi_id);
2343         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2344         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2345         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2346         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2347         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2348         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2349                     nes->rx_unknown_protocol);
2350         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2351         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2352         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2353         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2354         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2355         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2356         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2357                     vsi->vsi_id);
2358 }
2359
2360 static void
2361 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2362 {
2363         unsigned int i;
2364         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2365         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2366
2367         /* Get statistics of struct i40e_eth_stats */
2368         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2369                             I40E_GLPRT_GORCL(hw->port),
2370                             pf->offset_loaded, &os->eth.rx_bytes,
2371                             &ns->eth.rx_bytes);
2372         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2373                             I40E_GLPRT_UPRCL(hw->port),
2374                             pf->offset_loaded, &os->eth.rx_unicast,
2375                             &ns->eth.rx_unicast);
2376         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2377                             I40E_GLPRT_MPRCL(hw->port),
2378                             pf->offset_loaded, &os->eth.rx_multicast,
2379                             &ns->eth.rx_multicast);
2380         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2381                             I40E_GLPRT_BPRCL(hw->port),
2382                             pf->offset_loaded, &os->eth.rx_broadcast,
2383                             &ns->eth.rx_broadcast);
2384         /* Workaround: CRC size should not be included in byte statistics,
2385          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2386          */
2387         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2388                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2389
2390         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2391                             pf->offset_loaded, &os->eth.rx_discards,
2392                             &ns->eth.rx_discards);
2393         /* GLPRT_REPC not supported */
2394         /* GLPRT_RMPC not supported */
2395         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2396                             pf->offset_loaded,
2397                             &os->eth.rx_unknown_protocol,
2398                             &ns->eth.rx_unknown_protocol);
2399         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2400                             I40E_GLPRT_GOTCL(hw->port),
2401                             pf->offset_loaded, &os->eth.tx_bytes,
2402                             &ns->eth.tx_bytes);
2403         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2404                             I40E_GLPRT_UPTCL(hw->port),
2405                             pf->offset_loaded, &os->eth.tx_unicast,
2406                             &ns->eth.tx_unicast);
2407         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2408                             I40E_GLPRT_MPTCL(hw->port),
2409                             pf->offset_loaded, &os->eth.tx_multicast,
2410                             &ns->eth.tx_multicast);
2411         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2412                             I40E_GLPRT_BPTCL(hw->port),
2413                             pf->offset_loaded, &os->eth.tx_broadcast,
2414                             &ns->eth.tx_broadcast);
2415         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2416                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2417         /* GLPRT_TEPC not supported */
2418
2419         /* additional port specific stats */
2420         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2421                             pf->offset_loaded, &os->tx_dropped_link_down,
2422                             &ns->tx_dropped_link_down);
2423         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2424                             pf->offset_loaded, &os->crc_errors,
2425                             &ns->crc_errors);
2426         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2427                             pf->offset_loaded, &os->illegal_bytes,
2428                             &ns->illegal_bytes);
2429         /* GLPRT_ERRBC not supported */
2430         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2431                             pf->offset_loaded, &os->mac_local_faults,
2432                             &ns->mac_local_faults);
2433         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2434                             pf->offset_loaded, &os->mac_remote_faults,
2435                             &ns->mac_remote_faults);
2436         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2437                             pf->offset_loaded, &os->rx_length_errors,
2438                             &ns->rx_length_errors);
2439         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2440                             pf->offset_loaded, &os->link_xon_rx,
2441                             &ns->link_xon_rx);
2442         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2443                             pf->offset_loaded, &os->link_xoff_rx,
2444                             &ns->link_xoff_rx);
2445         for (i = 0; i < 8; i++) {
2446                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2447                                     pf->offset_loaded,
2448                                     &os->priority_xon_rx[i],
2449                                     &ns->priority_xon_rx[i]);
2450                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2451                                     pf->offset_loaded,
2452                                     &os->priority_xoff_rx[i],
2453                                     &ns->priority_xoff_rx[i]);
2454         }
2455         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2456                             pf->offset_loaded, &os->link_xon_tx,
2457                             &ns->link_xon_tx);
2458         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2459                             pf->offset_loaded, &os->link_xoff_tx,
2460                             &ns->link_xoff_tx);
2461         for (i = 0; i < 8; i++) {
2462                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2463                                     pf->offset_loaded,
2464                                     &os->priority_xon_tx[i],
2465                                     &ns->priority_xon_tx[i]);
2466                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2467                                     pf->offset_loaded,
2468                                     &os->priority_xoff_tx[i],
2469                                     &ns->priority_xoff_tx[i]);
2470                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2471                                     pf->offset_loaded,
2472                                     &os->priority_xon_2_xoff[i],
2473                                     &ns->priority_xon_2_xoff[i]);
2474         }
2475         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2476                             I40E_GLPRT_PRC64L(hw->port),
2477                             pf->offset_loaded, &os->rx_size_64,
2478                             &ns->rx_size_64);
2479         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2480                             I40E_GLPRT_PRC127L(hw->port),
2481                             pf->offset_loaded, &os->rx_size_127,
2482                             &ns->rx_size_127);
2483         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2484                             I40E_GLPRT_PRC255L(hw->port),
2485                             pf->offset_loaded, &os->rx_size_255,
2486                             &ns->rx_size_255);
2487         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2488                             I40E_GLPRT_PRC511L(hw->port),
2489                             pf->offset_loaded, &os->rx_size_511,
2490                             &ns->rx_size_511);
2491         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2492                             I40E_GLPRT_PRC1023L(hw->port),
2493                             pf->offset_loaded, &os->rx_size_1023,
2494                             &ns->rx_size_1023);
2495         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2496                             I40E_GLPRT_PRC1522L(hw->port),
2497                             pf->offset_loaded, &os->rx_size_1522,
2498                             &ns->rx_size_1522);
2499         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2500                             I40E_GLPRT_PRC9522L(hw->port),
2501                             pf->offset_loaded, &os->rx_size_big,
2502                             &ns->rx_size_big);
2503         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2504                             pf->offset_loaded, &os->rx_undersize,
2505                             &ns->rx_undersize);
2506         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2507                             pf->offset_loaded, &os->rx_fragments,
2508                             &ns->rx_fragments);
2509         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2510                             pf->offset_loaded, &os->rx_oversize,
2511                             &ns->rx_oversize);
2512         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2513                             pf->offset_loaded, &os->rx_jabber,
2514                             &ns->rx_jabber);
2515         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2516                             I40E_GLPRT_PTC64L(hw->port),
2517                             pf->offset_loaded, &os->tx_size_64,
2518                             &ns->tx_size_64);
2519         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2520                             I40E_GLPRT_PTC127L(hw->port),
2521                             pf->offset_loaded, &os->tx_size_127,
2522                             &ns->tx_size_127);
2523         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2524                             I40E_GLPRT_PTC255L(hw->port),
2525                             pf->offset_loaded, &os->tx_size_255,
2526                             &ns->tx_size_255);
2527         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2528                             I40E_GLPRT_PTC511L(hw->port),
2529                             pf->offset_loaded, &os->tx_size_511,
2530                             &ns->tx_size_511);
2531         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2532                             I40E_GLPRT_PTC1023L(hw->port),
2533                             pf->offset_loaded, &os->tx_size_1023,
2534                             &ns->tx_size_1023);
2535         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2536                             I40E_GLPRT_PTC1522L(hw->port),
2537                             pf->offset_loaded, &os->tx_size_1522,
2538                             &ns->tx_size_1522);
2539         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2540                             I40E_GLPRT_PTC9522L(hw->port),
2541                             pf->offset_loaded, &os->tx_size_big,
2542                             &ns->tx_size_big);
2543         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2544                            pf->offset_loaded,
2545                            &os->fd_sb_match, &ns->fd_sb_match);
2546         /* GLPRT_MSPDC not supported */
2547         /* GLPRT_XEC not supported */
2548
2549         pf->offset_loaded = true;
2550
2551         if (pf->main_vsi)
2552                 i40e_update_vsi_stats(pf->main_vsi);
2553 }
2554
2555 /* Get all statistics of a port */
2556 static void
2557 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2558 {
2559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2562         unsigned i;
2563
2564         /* call read registers - updates values, now write them to struct */
2565         i40e_read_stats_registers(pf, hw);
2566
2567         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2568                         pf->main_vsi->eth_stats.rx_multicast +
2569                         pf->main_vsi->eth_stats.rx_broadcast -
2570                         pf->main_vsi->eth_stats.rx_discards;
2571         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2572                         pf->main_vsi->eth_stats.tx_multicast +
2573                         pf->main_vsi->eth_stats.tx_broadcast;
2574         stats->ibytes   = ns->eth.rx_bytes;
2575         stats->obytes   = ns->eth.tx_bytes;
2576         stats->oerrors  = ns->eth.tx_errors +
2577                         pf->main_vsi->eth_stats.tx_errors;
2578
2579         /* Rx Errors */
2580         stats->imissed  = ns->eth.rx_discards +
2581                         pf->main_vsi->eth_stats.rx_discards;
2582         stats->ierrors  = ns->crc_errors +
2583                         ns->rx_length_errors + ns->rx_undersize +
2584                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2585
2586         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2587         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2588         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2589         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2590         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2591         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2592         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2593                     ns->eth.rx_unknown_protocol);
2594         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2595         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2596         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2597         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2598         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2599         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2600
2601         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2602                     ns->tx_dropped_link_down);
2603         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2604         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2605                     ns->illegal_bytes);
2606         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2607         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2608                     ns->mac_local_faults);
2609         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2610                     ns->mac_remote_faults);
2611         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2612                     ns->rx_length_errors);
2613         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2614         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2615         for (i = 0; i < 8; i++) {
2616                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2617                                 i, ns->priority_xon_rx[i]);
2618                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2619                                 i, ns->priority_xoff_rx[i]);
2620         }
2621         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2622         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2623         for (i = 0; i < 8; i++) {
2624                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2625                                 i, ns->priority_xon_tx[i]);
2626                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2627                                 i, ns->priority_xoff_tx[i]);
2628                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2629                                 i, ns->priority_xon_2_xoff[i]);
2630         }
2631         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2632         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2633         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2634         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2635         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2636         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2637         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2638         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2639         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2640         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2641         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2642         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2643         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2644         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2645         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2646         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2647         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2648         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2649         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2650                         ns->mac_short_packet_dropped);
2651         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2652                     ns->checksum_error);
2653         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2654         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2655 }
2656
2657 /* Reset the statistics */
2658 static void
2659 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2660 {
2661         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663
2664         /* Mark PF and VSI stats to update the offset, aka "reset" */
2665         pf->offset_loaded = false;
2666         if (pf->main_vsi)
2667                 pf->main_vsi->offset_loaded = false;
2668
2669         /* read the stats, reading current register values into offset */
2670         i40e_read_stats_registers(pf, hw);
2671 }
2672
2673 static uint32_t
2674 i40e_xstats_calc_num(void)
2675 {
2676         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2677                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2678                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2679 }
2680
2681 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2682                                      struct rte_eth_xstat_name *xstats_names,
2683                                      __rte_unused unsigned limit)
2684 {
2685         unsigned count = 0;
2686         unsigned i, prio;
2687
2688         if (xstats_names == NULL)
2689                 return i40e_xstats_calc_num();
2690
2691         /* Note: limit checked in rte_eth_xstats_names() */
2692
2693         /* Get stats from i40e_eth_stats struct */
2694         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2695                 snprintf(xstats_names[count].name,
2696                          sizeof(xstats_names[count].name),
2697                          "%s", rte_i40e_stats_strings[i].name);
2698                 count++;
2699         }
2700
2701         /* Get individiual stats from i40e_hw_port struct */
2702         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2703                 snprintf(xstats_names[count].name,
2704                         sizeof(xstats_names[count].name),
2705                          "%s", rte_i40e_hw_port_strings[i].name);
2706                 count++;
2707         }
2708
2709         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2710                 for (prio = 0; prio < 8; prio++) {
2711                         snprintf(xstats_names[count].name,
2712                                  sizeof(xstats_names[count].name),
2713                                  "rx_priority%u_%s", prio,
2714                                  rte_i40e_rxq_prio_strings[i].name);
2715                         count++;
2716                 }
2717         }
2718
2719         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2720                 for (prio = 0; prio < 8; prio++) {
2721                         snprintf(xstats_names[count].name,
2722                                  sizeof(xstats_names[count].name),
2723                                  "tx_priority%u_%s", prio,
2724                                  rte_i40e_txq_prio_strings[i].name);
2725                         count++;
2726                 }
2727         }
2728         return count;
2729 }
2730
2731 static int
2732 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2733                     unsigned n)
2734 {
2735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2737         unsigned i, count, prio;
2738         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2739
2740         count = i40e_xstats_calc_num();
2741         if (n < count)
2742                 return count;
2743
2744         i40e_read_stats_registers(pf, hw);
2745
2746         if (xstats == NULL)
2747                 return 0;
2748
2749         count = 0;
2750
2751         /* Get stats from i40e_eth_stats struct */
2752         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2753                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2754                         rte_i40e_stats_strings[i].offset);
2755                 xstats[count].id = count;
2756                 count++;
2757         }
2758
2759         /* Get individiual stats from i40e_hw_port struct */
2760         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2761                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2762                         rte_i40e_hw_port_strings[i].offset);
2763                 xstats[count].id = count;
2764                 count++;
2765         }
2766
2767         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2768                 for (prio = 0; prio < 8; prio++) {
2769                         xstats[count].value =
2770                                 *(uint64_t *)(((char *)hw_stats) +
2771                                 rte_i40e_rxq_prio_strings[i].offset +
2772                                 (sizeof(uint64_t) * prio));
2773                         xstats[count].id = count;
2774                         count++;
2775                 }
2776         }
2777
2778         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2779                 for (prio = 0; prio < 8; prio++) {
2780                         xstats[count].value =
2781                                 *(uint64_t *)(((char *)hw_stats) +
2782                                 rte_i40e_txq_prio_strings[i].offset +
2783                                 (sizeof(uint64_t) * prio));
2784                         xstats[count].id = count;
2785                         count++;
2786                 }
2787         }
2788
2789         return count;
2790 }
2791
2792 static int
2793 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2794                                  __rte_unused uint16_t queue_id,
2795                                  __rte_unused uint8_t stat_idx,
2796                                  __rte_unused uint8_t is_rx)
2797 {
2798         PMD_INIT_FUNC_TRACE();
2799
2800         return -ENOSYS;
2801 }
2802
2803 static int
2804 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2805 {
2806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         u32 full_ver;
2808         u8 ver, patch;
2809         u16 build;
2810         int ret;
2811
2812         full_ver = hw->nvm.oem_ver;
2813         ver = (u8)(full_ver >> 24);
2814         build = (u16)((full_ver >> 8) & 0xffff);
2815         patch = (u8)(full_ver & 0xff);
2816
2817         ret = snprintf(fw_version, fw_size,
2818                  "%d.%d%d 0x%08x %d.%d.%d",
2819                  ((hw->nvm.version >> 12) & 0xf),
2820                  ((hw->nvm.version >> 4) & 0xff),
2821                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2822                  ver, build, patch);
2823
2824         ret += 1; /* add the size of '\0' */
2825         if (fw_size < (u32)ret)
2826                 return ret;
2827         else
2828                 return 0;
2829 }
2830
2831 static void
2832 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2833 {
2834         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836         struct i40e_vsi *vsi = pf->main_vsi;
2837         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2838
2839         dev_info->pci_dev = pci_dev;
2840         dev_info->max_rx_queues = vsi->nb_qps;
2841         dev_info->max_tx_queues = vsi->nb_qps;
2842         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2843         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2844         dev_info->max_mac_addrs = vsi->max_macaddrs;
2845         dev_info->max_vfs = pci_dev->max_vfs;
2846         dev_info->rx_offload_capa =
2847                 DEV_RX_OFFLOAD_VLAN_STRIP |
2848                 DEV_RX_OFFLOAD_QINQ_STRIP |
2849                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2850                 DEV_RX_OFFLOAD_UDP_CKSUM |
2851                 DEV_RX_OFFLOAD_TCP_CKSUM;
2852         dev_info->tx_offload_capa =
2853                 DEV_TX_OFFLOAD_VLAN_INSERT |
2854                 DEV_TX_OFFLOAD_QINQ_INSERT |
2855                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2856                 DEV_TX_OFFLOAD_UDP_CKSUM |
2857                 DEV_TX_OFFLOAD_TCP_CKSUM |
2858                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2859                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2860                 DEV_TX_OFFLOAD_TCP_TSO |
2861                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2862                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2863                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2864                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2865         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2866                                                 sizeof(uint32_t);
2867         dev_info->reta_size = pf->hash_lut_size;
2868         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2869
2870         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2871                 .rx_thresh = {
2872                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2873                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2874                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2875                 },
2876                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2877                 .rx_drop_en = 0,
2878         };
2879
2880         dev_info->default_txconf = (struct rte_eth_txconf) {
2881                 .tx_thresh = {
2882                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2883                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2884                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2885                 },
2886                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2887                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2888                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2889                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2890         };
2891
2892         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2893                 .nb_max = I40E_MAX_RING_DESC,
2894                 .nb_min = I40E_MIN_RING_DESC,
2895                 .nb_align = I40E_ALIGN_RING_DESC,
2896         };
2897
2898         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2899                 .nb_max = I40E_MAX_RING_DESC,
2900                 .nb_min = I40E_MIN_RING_DESC,
2901                 .nb_align = I40E_ALIGN_RING_DESC,
2902                 .nb_seg_max = I40E_TX_MAX_SEG,
2903                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2904         };
2905
2906         if (pf->flags & I40E_FLAG_VMDQ) {
2907                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2908                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2909                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2910                                                 pf->max_nb_vmdq_vsi;
2911                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2912                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2913                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2914         }
2915
2916         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2917                 /* For XL710 */
2918                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2919         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2920                 /* For XXV710 */
2921                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2922         else
2923                 /* For X710 */
2924                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2925 }
2926
2927 static int
2928 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2929 {
2930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2931         struct i40e_vsi *vsi = pf->main_vsi;
2932         PMD_INIT_FUNC_TRACE();
2933
2934         if (on)
2935                 return i40e_vsi_add_vlan(vsi, vlan_id);
2936         else
2937                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2938 }
2939
2940 static int
2941 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2942                    enum rte_vlan_type vlan_type,
2943                    uint16_t tpid)
2944 {
2945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946         uint64_t reg_r = 0, reg_w = 0;
2947         uint16_t reg_id = 0;
2948         int ret = 0;
2949         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2950
2951         switch (vlan_type) {
2952         case ETH_VLAN_TYPE_OUTER:
2953                 if (qinq)
2954                         reg_id = 2;
2955                 else
2956                         reg_id = 3;
2957                 break;
2958         case ETH_VLAN_TYPE_INNER:
2959                 if (qinq)
2960                         reg_id = 3;
2961                 else {
2962                         ret = -EINVAL;
2963                         PMD_DRV_LOG(ERR,
2964                                 "Unsupported vlan type in single vlan.");
2965                         return ret;
2966                 }
2967                 break;
2968         default:
2969                 ret = -EINVAL;
2970                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2971                 return ret;
2972         }
2973         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2974                                           &reg_r, NULL);
2975         if (ret != I40E_SUCCESS) {
2976                 PMD_DRV_LOG(ERR,
2977                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2978                            reg_id);
2979                 ret = -EIO;
2980                 return ret;
2981         }
2982         PMD_DRV_LOG(DEBUG,
2983                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2984                 reg_id, reg_r);
2985
2986         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2987         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2988         if (reg_r == reg_w) {
2989                 ret = 0;
2990                 PMD_DRV_LOG(DEBUG, "No need to write");
2991                 return ret;
2992         }
2993
2994         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2995                                            reg_w, NULL);
2996         if (ret != I40E_SUCCESS) {
2997                 ret = -EIO;
2998                 PMD_DRV_LOG(ERR,
2999                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3000                         reg_id);
3001                 return ret;
3002         }
3003         PMD_DRV_LOG(DEBUG,
3004                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3005                 reg_w, reg_id);
3006
3007         return ret;
3008 }
3009
3010 static void
3011 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3012 {
3013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3014         struct i40e_vsi *vsi = pf->main_vsi;
3015
3016         if (mask & ETH_VLAN_FILTER_MASK) {
3017                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3018                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3019                 else
3020                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3021         }
3022
3023         if (mask & ETH_VLAN_STRIP_MASK) {
3024                 /* Enable or disable VLAN stripping */
3025                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3026                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3027                 else
3028                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3029         }
3030
3031         if (mask & ETH_VLAN_EXTEND_MASK) {
3032                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3033                         i40e_vsi_config_double_vlan(vsi, TRUE);
3034                         /* Set global registers with default ether type value */
3035                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3036                                            ETHER_TYPE_VLAN);
3037                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3038                                            ETHER_TYPE_VLAN);
3039                 }
3040                 else
3041                         i40e_vsi_config_double_vlan(vsi, FALSE);
3042         }
3043 }
3044
3045 static void
3046 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3047                           __rte_unused uint16_t queue,
3048                           __rte_unused int on)
3049 {
3050         PMD_INIT_FUNC_TRACE();
3051 }
3052
3053 static int
3054 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3055 {
3056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3057         struct i40e_vsi *vsi = pf->main_vsi;
3058         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3059         struct i40e_vsi_vlan_pvid_info info;
3060
3061         memset(&info, 0, sizeof(info));
3062         info.on = on;
3063         if (info.on)
3064                 info.config.pvid = pvid;
3065         else {
3066                 info.config.reject.tagged =
3067                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3068                 info.config.reject.untagged =
3069                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3070         }
3071
3072         return i40e_vsi_vlan_pvid_set(vsi, &info);
3073 }
3074
3075 static int
3076 i40e_dev_led_on(struct rte_eth_dev *dev)
3077 {
3078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         uint32_t mode = i40e_led_get(hw);
3080
3081         if (mode == 0)
3082                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3083
3084         return 0;
3085 }
3086
3087 static int
3088 i40e_dev_led_off(struct rte_eth_dev *dev)
3089 {
3090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         uint32_t mode = i40e_led_get(hw);
3092
3093         if (mode != 0)
3094                 i40e_led_set(hw, 0, false);
3095
3096         return 0;
3097 }
3098
3099 static int
3100 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3101 {
3102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3104
3105         fc_conf->pause_time = pf->fc_conf.pause_time;
3106         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3107         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3108
3109          /* Return current mode according to actual setting*/
3110         switch (hw->fc.current_mode) {
3111         case I40E_FC_FULL:
3112                 fc_conf->mode = RTE_FC_FULL;
3113                 break;
3114         case I40E_FC_TX_PAUSE:
3115                 fc_conf->mode = RTE_FC_TX_PAUSE;
3116                 break;
3117         case I40E_FC_RX_PAUSE:
3118                 fc_conf->mode = RTE_FC_RX_PAUSE;
3119                 break;
3120         case I40E_FC_NONE:
3121         default:
3122                 fc_conf->mode = RTE_FC_NONE;
3123         };
3124
3125         return 0;
3126 }
3127
3128 static int
3129 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3130 {
3131         uint32_t mflcn_reg, fctrl_reg, reg;
3132         uint32_t max_high_water;
3133         uint8_t i, aq_failure;
3134         int err;
3135         struct i40e_hw *hw;
3136         struct i40e_pf *pf;
3137         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3138                 [RTE_FC_NONE] = I40E_FC_NONE,
3139                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3140                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3141                 [RTE_FC_FULL] = I40E_FC_FULL
3142         };
3143
3144         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3145
3146         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3147         if ((fc_conf->high_water > max_high_water) ||
3148                         (fc_conf->high_water < fc_conf->low_water)) {
3149                 PMD_INIT_LOG(ERR,
3150                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3151                         max_high_water);
3152                 return -EINVAL;
3153         }
3154
3155         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3157         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3158
3159         pf->fc_conf.pause_time = fc_conf->pause_time;
3160         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3161         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3162
3163         PMD_INIT_FUNC_TRACE();
3164
3165         /* All the link flow control related enable/disable register
3166          * configuration is handle by the F/W
3167          */
3168         err = i40e_set_fc(hw, &aq_failure, true);
3169         if (err < 0)
3170                 return -ENOSYS;
3171
3172         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3173                 /* Configure flow control refresh threshold,
3174                  * the value for stat_tx_pause_refresh_timer[8]
3175                  * is used for global pause operation.
3176                  */
3177
3178                 I40E_WRITE_REG(hw,
3179                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3180                                pf->fc_conf.pause_time);
3181
3182                 /* configure the timer value included in transmitted pause
3183                  * frame,
3184                  * the value for stat_tx_pause_quanta[8] is used for global
3185                  * pause operation
3186                  */
3187                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3188                                pf->fc_conf.pause_time);
3189
3190                 fctrl_reg = I40E_READ_REG(hw,
3191                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3192
3193                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3194                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3195                 else
3196                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3197
3198                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3199                                fctrl_reg);
3200         } else {
3201                 /* Configure pause time (2 TCs per register) */
3202                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3203                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3204                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3205
3206                 /* Configure flow control refresh threshold value */
3207                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3208                                pf->fc_conf.pause_time / 2);
3209
3210                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3211
3212                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3213                  *depending on configuration
3214                  */
3215                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3216                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3217                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3218                 } else {
3219                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3220                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3221                 }
3222
3223                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3224         }
3225
3226         /* config the water marker both based on the packets and bytes */
3227         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3228                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3229                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3230         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3231                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3232                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3233         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3234                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3235                        << I40E_KILOSHIFT);
3236         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3237                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3238                        << I40E_KILOSHIFT);
3239
3240         I40E_WRITE_FLUSH(hw);
3241
3242         return 0;
3243 }
3244
3245 static int
3246 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3247                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3248 {
3249         PMD_INIT_FUNC_TRACE();
3250
3251         return -ENOSYS;
3252 }
3253
3254 /* Add a MAC address, and update filters */
3255 static void
3256 i40e_macaddr_add(struct rte_eth_dev *dev,
3257                  struct ether_addr *mac_addr,
3258                  __rte_unused uint32_t index,
3259                  uint32_t pool)
3260 {
3261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3262         struct i40e_mac_filter_info mac_filter;
3263         struct i40e_vsi *vsi;
3264         int ret;
3265
3266         /* If VMDQ not enabled or configured, return */
3267         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3268                           !pf->nb_cfg_vmdq_vsi)) {
3269                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3270                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3271                         pool);
3272                 return;
3273         }
3274
3275         if (pool > pf->nb_cfg_vmdq_vsi) {
3276                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3277                                 pool, pf->nb_cfg_vmdq_vsi);
3278                 return;
3279         }
3280
3281         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3282         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3283                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3284         else
3285                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3286
3287         if (pool == 0)
3288                 vsi = pf->main_vsi;
3289         else
3290                 vsi = pf->vmdq[pool - 1].vsi;
3291
3292         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3293         if (ret != I40E_SUCCESS) {
3294                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3295                 return;
3296         }
3297 }
3298
3299 /* Remove a MAC address, and update filters */
3300 static void
3301 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3302 {
3303         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3304         struct i40e_vsi *vsi;
3305         struct rte_eth_dev_data *data = dev->data;
3306         struct ether_addr *macaddr;
3307         int ret;
3308         uint32_t i;
3309         uint64_t pool_sel;
3310
3311         macaddr = &(data->mac_addrs[index]);
3312
3313         pool_sel = dev->data->mac_pool_sel[index];
3314
3315         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3316                 if (pool_sel & (1ULL << i)) {
3317                         if (i == 0)
3318                                 vsi = pf->main_vsi;
3319                         else {
3320                                 /* No VMDQ pool enabled or configured */
3321                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3322                                         (i > pf->nb_cfg_vmdq_vsi)) {
3323                                         PMD_DRV_LOG(ERR,
3324                                                 "No VMDQ pool enabled/configured");
3325                                         return;
3326                                 }
3327                                 vsi = pf->vmdq[i - 1].vsi;
3328                         }
3329                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3330
3331                         if (ret) {
3332                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3333                                 return;
3334                         }
3335                 }
3336         }
3337 }
3338
3339 /* Set perfect match or hash match of MAC and VLAN for a VF */
3340 static int
3341 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3342                  struct rte_eth_mac_filter *filter,
3343                  bool add)
3344 {
3345         struct i40e_hw *hw;
3346         struct i40e_mac_filter_info mac_filter;
3347         struct ether_addr old_mac;
3348         struct ether_addr *new_mac;
3349         struct i40e_pf_vf *vf = NULL;
3350         uint16_t vf_id;
3351         int ret;
3352
3353         if (pf == NULL) {
3354                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3355                 return -EINVAL;
3356         }
3357         hw = I40E_PF_TO_HW(pf);
3358
3359         if (filter == NULL) {
3360                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3361                 return -EINVAL;
3362         }
3363
3364         new_mac = &filter->mac_addr;
3365
3366         if (is_zero_ether_addr(new_mac)) {
3367                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3368                 return -EINVAL;
3369         }
3370
3371         vf_id = filter->dst_id;
3372
3373         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3374                 PMD_DRV_LOG(ERR, "Invalid argument.");
3375                 return -EINVAL;
3376         }
3377         vf = &pf->vfs[vf_id];
3378
3379         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3380                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3381                 return -EINVAL;
3382         }
3383
3384         if (add) {
3385                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3386                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3387                                 ETHER_ADDR_LEN);
3388                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3389                                  ETHER_ADDR_LEN);
3390
3391                 mac_filter.filter_type = filter->filter_type;
3392                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3393                 if (ret != I40E_SUCCESS) {
3394                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3395                         return -1;
3396                 }
3397                 ether_addr_copy(new_mac, &pf->dev_addr);
3398         } else {
3399                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3400                                 ETHER_ADDR_LEN);
3401                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3402                 if (ret != I40E_SUCCESS) {
3403                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3404                         return -1;
3405                 }
3406
3407                 /* Clear device address as it has been removed */
3408                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3409                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3410         }
3411
3412         return 0;
3413 }
3414
3415 /* MAC filter handle */
3416 static int
3417 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3418                 void *arg)
3419 {
3420         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3421         struct rte_eth_mac_filter *filter;
3422         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3423         int ret = I40E_NOT_SUPPORTED;
3424
3425         filter = (struct rte_eth_mac_filter *)(arg);
3426
3427         switch (filter_op) {
3428         case RTE_ETH_FILTER_NOP:
3429                 ret = I40E_SUCCESS;
3430                 break;
3431         case RTE_ETH_FILTER_ADD:
3432                 i40e_pf_disable_irq0(hw);
3433                 if (filter->is_vf)
3434                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3435                 i40e_pf_enable_irq0(hw);
3436                 break;
3437         case RTE_ETH_FILTER_DELETE:
3438                 i40e_pf_disable_irq0(hw);
3439                 if (filter->is_vf)
3440                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3441                 i40e_pf_enable_irq0(hw);
3442                 break;
3443         default:
3444                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3445                 ret = I40E_ERR_PARAM;
3446                 break;
3447         }
3448
3449         return ret;
3450 }
3451
3452 static int
3453 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3454 {
3455         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3456         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3457         int ret;
3458
3459         if (!lut)
3460                 return -EINVAL;
3461
3462         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3463                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3464                                           lut, lut_size);
3465                 if (ret) {
3466                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3467                         return ret;
3468                 }
3469         } else {
3470                 uint32_t *lut_dw = (uint32_t *)lut;
3471                 uint16_t i, lut_size_dw = lut_size / 4;
3472
3473                 for (i = 0; i < lut_size_dw; i++)
3474                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3475         }
3476
3477         return 0;
3478 }
3479
3480 static int
3481 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3482 {
3483         struct i40e_pf *pf;
3484         struct i40e_hw *hw;
3485         int ret;
3486
3487         if (!vsi || !lut)
3488                 return -EINVAL;
3489
3490         pf = I40E_VSI_TO_PF(vsi);
3491         hw = I40E_VSI_TO_HW(vsi);
3492
3493         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3494                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3495                                           lut, lut_size);
3496                 if (ret) {
3497                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3498                         return ret;
3499                 }
3500         } else {
3501                 uint32_t *lut_dw = (uint32_t *)lut;
3502                 uint16_t i, lut_size_dw = lut_size / 4;
3503
3504                 for (i = 0; i < lut_size_dw; i++)
3505                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3506                 I40E_WRITE_FLUSH(hw);
3507         }
3508
3509         return 0;
3510 }
3511
3512 static int
3513 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3514                          struct rte_eth_rss_reta_entry64 *reta_conf,
3515                          uint16_t reta_size)
3516 {
3517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3518         uint16_t i, lut_size = pf->hash_lut_size;
3519         uint16_t idx, shift;
3520         uint8_t *lut;
3521         int ret;
3522
3523         if (reta_size != lut_size ||
3524                 reta_size > ETH_RSS_RETA_SIZE_512) {
3525                 PMD_DRV_LOG(ERR,
3526                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3527                         reta_size, lut_size);
3528                 return -EINVAL;
3529         }
3530
3531         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3532         if (!lut) {
3533                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3534                 return -ENOMEM;
3535         }
3536         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3537         if (ret)
3538                 goto out;
3539         for (i = 0; i < reta_size; i++) {
3540                 idx = i / RTE_RETA_GROUP_SIZE;
3541                 shift = i % RTE_RETA_GROUP_SIZE;
3542                 if (reta_conf[idx].mask & (1ULL << shift))
3543                         lut[i] = reta_conf[idx].reta[shift];
3544         }
3545         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3546
3547 out:
3548         rte_free(lut);
3549
3550         return ret;
3551 }
3552
3553 static int
3554 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3555                         struct rte_eth_rss_reta_entry64 *reta_conf,
3556                         uint16_t reta_size)
3557 {
3558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3559         uint16_t i, lut_size = pf->hash_lut_size;
3560         uint16_t idx, shift;
3561         uint8_t *lut;
3562         int ret;
3563
3564         if (reta_size != lut_size ||
3565                 reta_size > ETH_RSS_RETA_SIZE_512) {
3566                 PMD_DRV_LOG(ERR,
3567                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3568                         reta_size, lut_size);
3569                 return -EINVAL;
3570         }
3571
3572         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3573         if (!lut) {
3574                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3575                 return -ENOMEM;
3576         }
3577
3578         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3579         if (ret)
3580                 goto out;
3581         for (i = 0; i < reta_size; i++) {
3582                 idx = i / RTE_RETA_GROUP_SIZE;
3583                 shift = i % RTE_RETA_GROUP_SIZE;
3584                 if (reta_conf[idx].mask & (1ULL << shift))
3585                         reta_conf[idx].reta[shift] = lut[i];
3586         }
3587
3588 out:
3589         rte_free(lut);
3590
3591         return ret;
3592 }
3593
3594 /**
3595  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3596  * @hw:   pointer to the HW structure
3597  * @mem:  pointer to mem struct to fill out
3598  * @size: size of memory requested
3599  * @alignment: what to align the allocation to
3600  **/
3601 enum i40e_status_code
3602 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3603                         struct i40e_dma_mem *mem,
3604                         u64 size,
3605                         u32 alignment)
3606 {
3607         const struct rte_memzone *mz = NULL;
3608         char z_name[RTE_MEMZONE_NAMESIZE];
3609
3610         if (!mem)
3611                 return I40E_ERR_PARAM;
3612
3613         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3614         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3615                                          alignment, RTE_PGSIZE_2M);
3616         if (!mz)
3617                 return I40E_ERR_NO_MEMORY;
3618
3619         mem->size = size;
3620         mem->va = mz->addr;
3621         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3622         mem->zone = (const void *)mz;
3623         PMD_DRV_LOG(DEBUG,
3624                 "memzone %s allocated with physical address: %"PRIu64,
3625                 mz->name, mem->pa);
3626
3627         return I40E_SUCCESS;
3628 }
3629
3630 /**
3631  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3632  * @hw:   pointer to the HW structure
3633  * @mem:  ptr to mem struct to free
3634  **/
3635 enum i40e_status_code
3636 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3637                     struct i40e_dma_mem *mem)
3638 {
3639         if (!mem)
3640                 return I40E_ERR_PARAM;
3641
3642         PMD_DRV_LOG(DEBUG,
3643                 "memzone %s to be freed with physical address: %"PRIu64,
3644                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3645         rte_memzone_free((const struct rte_memzone *)mem->zone);
3646         mem->zone = NULL;
3647         mem->va = NULL;
3648         mem->pa = (u64)0;
3649
3650         return I40E_SUCCESS;
3651 }
3652
3653 /**
3654  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3655  * @hw:   pointer to the HW structure
3656  * @mem:  pointer to mem struct to fill out
3657  * @size: size of memory requested
3658  **/
3659 enum i40e_status_code
3660 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3661                          struct i40e_virt_mem *mem,
3662                          u32 size)
3663 {
3664         if (!mem)
3665                 return I40E_ERR_PARAM;
3666
3667         mem->size = size;
3668         mem->va = rte_zmalloc("i40e", size, 0);
3669
3670         if (mem->va)
3671                 return I40E_SUCCESS;
3672         else
3673                 return I40E_ERR_NO_MEMORY;
3674 }
3675
3676 /**
3677  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3678  * @hw:   pointer to the HW structure
3679  * @mem:  pointer to mem struct to free
3680  **/
3681 enum i40e_status_code
3682 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3683                      struct i40e_virt_mem *mem)
3684 {
3685         if (!mem)
3686                 return I40E_ERR_PARAM;
3687
3688         rte_free(mem->va);
3689         mem->va = NULL;
3690
3691         return I40E_SUCCESS;
3692 }
3693
3694 void
3695 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3696 {
3697         rte_spinlock_init(&sp->spinlock);
3698 }
3699
3700 void
3701 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3702 {
3703         rte_spinlock_lock(&sp->spinlock);
3704 }
3705
3706 void
3707 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3708 {
3709         rte_spinlock_unlock(&sp->spinlock);
3710 }
3711
3712 void
3713 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3714 {
3715         return;
3716 }
3717
3718 /**
3719  * Get the hardware capabilities, which will be parsed
3720  * and saved into struct i40e_hw.
3721  */
3722 static int
3723 i40e_get_cap(struct i40e_hw *hw)
3724 {
3725         struct i40e_aqc_list_capabilities_element_resp *buf;
3726         uint16_t len, size = 0;
3727         int ret;
3728
3729         /* Calculate a huge enough buff for saving response data temporarily */
3730         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3731                                                 I40E_MAX_CAP_ELE_NUM;
3732         buf = rte_zmalloc("i40e", len, 0);
3733         if (!buf) {
3734                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3735                 return I40E_ERR_NO_MEMORY;
3736         }
3737
3738         /* Get, parse the capabilities and save it to hw */
3739         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3740                         i40e_aqc_opc_list_func_capabilities, NULL);
3741         if (ret != I40E_SUCCESS)
3742                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3743
3744         /* Free the temporary buffer after being used */
3745         rte_free(buf);
3746
3747         return ret;
3748 }
3749
3750 static int
3751 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3752 {
3753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3755         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3756         uint16_t qp_count = 0, vsi_count = 0;
3757
3758         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3759                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3760                 return -EINVAL;
3761         }
3762         /* Add the parameter init for LFC */
3763         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3764         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3765         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3766
3767         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3768         pf->max_num_vsi = hw->func_caps.num_vsis;
3769         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3770         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3771         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3772
3773         /* FDir queue/VSI allocation */
3774         pf->fdir_qp_offset = 0;
3775         if (hw->func_caps.fd) {
3776                 pf->flags |= I40E_FLAG_FDIR;
3777                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3778         } else {
3779                 pf->fdir_nb_qps = 0;
3780         }
3781         qp_count += pf->fdir_nb_qps;
3782         vsi_count += 1;
3783
3784         /* LAN queue/VSI allocation */
3785         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3786         if (!hw->func_caps.rss) {
3787                 pf->lan_nb_qps = 1;
3788         } else {
3789                 pf->flags |= I40E_FLAG_RSS;
3790                 if (hw->mac.type == I40E_MAC_X722)
3791                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3792                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3793         }
3794         qp_count += pf->lan_nb_qps;
3795         vsi_count += 1;
3796
3797         /* VF queue/VSI allocation */
3798         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3799         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3800                 pf->flags |= I40E_FLAG_SRIOV;
3801                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3802                 pf->vf_num = pci_dev->max_vfs;
3803                 PMD_DRV_LOG(DEBUG,
3804                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3805                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3806         } else {
3807                 pf->vf_nb_qps = 0;
3808                 pf->vf_num = 0;
3809         }
3810         qp_count += pf->vf_nb_qps * pf->vf_num;
3811         vsi_count += pf->vf_num;
3812
3813         /* VMDq queue/VSI allocation */
3814         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3815         pf->vmdq_nb_qps = 0;
3816         pf->max_nb_vmdq_vsi = 0;
3817         if (hw->func_caps.vmdq) {
3818                 if (qp_count < hw->func_caps.num_tx_qp &&
3819                         vsi_count < hw->func_caps.num_vsis) {
3820                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3821                                 qp_count) / pf->vmdq_nb_qp_max;
3822
3823                         /* Limit the maximum number of VMDq vsi to the maximum
3824                          * ethdev can support
3825                          */
3826                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3827                                 hw->func_caps.num_vsis - vsi_count);
3828                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3829                                 ETH_64_POOLS);
3830                         if (pf->max_nb_vmdq_vsi) {
3831                                 pf->flags |= I40E_FLAG_VMDQ;
3832                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3833                                 PMD_DRV_LOG(DEBUG,
3834                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3835                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3836                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3837                         } else {
3838                                 PMD_DRV_LOG(INFO,
3839                                         "No enough queues left for VMDq");
3840                         }
3841                 } else {
3842                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3843                 }
3844         }
3845         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3846         vsi_count += pf->max_nb_vmdq_vsi;
3847
3848         if (hw->func_caps.dcb)
3849                 pf->flags |= I40E_FLAG_DCB;
3850
3851         if (qp_count > hw->func_caps.num_tx_qp) {
3852                 PMD_DRV_LOG(ERR,
3853                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3854                         qp_count, hw->func_caps.num_tx_qp);
3855                 return -EINVAL;
3856         }
3857         if (vsi_count > hw->func_caps.num_vsis) {
3858                 PMD_DRV_LOG(ERR,
3859                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3860                         vsi_count, hw->func_caps.num_vsis);
3861                 return -EINVAL;
3862         }
3863
3864         return 0;
3865 }
3866
3867 static int
3868 i40e_pf_get_switch_config(struct i40e_pf *pf)
3869 {
3870         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3871         struct i40e_aqc_get_switch_config_resp *switch_config;
3872         struct i40e_aqc_switch_config_element_resp *element;
3873         uint16_t start_seid = 0, num_reported;
3874         int ret;
3875
3876         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3877                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3878         if (!switch_config) {
3879                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3880                 return -ENOMEM;
3881         }
3882
3883         /* Get the switch configurations */
3884         ret = i40e_aq_get_switch_config(hw, switch_config,
3885                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3886         if (ret != I40E_SUCCESS) {
3887                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3888                 goto fail;
3889         }
3890         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3891         if (num_reported != 1) { /* The number should be 1 */
3892                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3893                 goto fail;
3894         }
3895
3896         /* Parse the switch configuration elements */
3897         element = &(switch_config->element[0]);
3898         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3899                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3900                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3901         } else
3902                 PMD_DRV_LOG(INFO, "Unknown element type");
3903
3904 fail:
3905         rte_free(switch_config);
3906
3907         return ret;
3908 }
3909
3910 static int
3911 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3912                         uint32_t num)
3913 {
3914         struct pool_entry *entry;
3915
3916         if (pool == NULL || num == 0)
3917                 return -EINVAL;
3918
3919         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3920         if (entry == NULL) {
3921                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3922                 return -ENOMEM;
3923         }
3924
3925         /* queue heap initialize */
3926         pool->num_free = num;
3927         pool->num_alloc = 0;
3928         pool->base = base;
3929         LIST_INIT(&pool->alloc_list);
3930         LIST_INIT(&pool->free_list);
3931
3932         /* Initialize element  */
3933         entry->base = 0;
3934         entry->len = num;
3935
3936         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3937         return 0;
3938 }
3939
3940 static void
3941 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3942 {
3943         struct pool_entry *entry, *next_entry;
3944
3945         if (pool == NULL)
3946                 return;
3947
3948         for (entry = LIST_FIRST(&pool->alloc_list);
3949                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3950                         entry = next_entry) {
3951                 LIST_REMOVE(entry, next);
3952                 rte_free(entry);
3953         }
3954
3955         for (entry = LIST_FIRST(&pool->free_list);
3956                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3957                         entry = next_entry) {
3958                 LIST_REMOVE(entry, next);
3959                 rte_free(entry);
3960         }
3961
3962         pool->num_free = 0;
3963         pool->num_alloc = 0;
3964         pool->base = 0;
3965         LIST_INIT(&pool->alloc_list);
3966         LIST_INIT(&pool->free_list);
3967 }
3968
3969 static int
3970 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3971                        uint32_t base)
3972 {
3973         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3974         uint32_t pool_offset;
3975         int insert;
3976
3977         if (pool == NULL) {
3978                 PMD_DRV_LOG(ERR, "Invalid parameter");
3979                 return -EINVAL;
3980         }
3981
3982         pool_offset = base - pool->base;
3983         /* Lookup in alloc list */
3984         LIST_FOREACH(entry, &pool->alloc_list, next) {
3985                 if (entry->base == pool_offset) {
3986                         valid_entry = entry;
3987                         LIST_REMOVE(entry, next);
3988                         break;
3989                 }
3990         }
3991
3992         /* Not find, return */
3993         if (valid_entry == NULL) {
3994                 PMD_DRV_LOG(ERR, "Failed to find entry");
3995                 return -EINVAL;
3996         }
3997
3998         /**
3999          * Found it, move it to free list  and try to merge.
4000          * In order to make merge easier, always sort it by qbase.
4001          * Find adjacent prev and last entries.
4002          */
4003         prev = next = NULL;
4004         LIST_FOREACH(entry, &pool->free_list, next) {
4005                 if (entry->base > valid_entry->base) {
4006                         next = entry;
4007                         break;
4008                 }
4009                 prev = entry;
4010         }
4011
4012         insert = 0;
4013         /* Try to merge with next one*/
4014         if (next != NULL) {
4015                 /* Merge with next one */
4016                 if (valid_entry->base + valid_entry->len == next->base) {
4017                         next->base = valid_entry->base;
4018                         next->len += valid_entry->len;
4019                         rte_free(valid_entry);
4020                         valid_entry = next;
4021                         insert = 1;
4022                 }
4023         }
4024
4025         if (prev != NULL) {
4026                 /* Merge with previous one */
4027                 if (prev->base + prev->len == valid_entry->base) {
4028                         prev->len += valid_entry->len;
4029                         /* If it merge with next one, remove next node */
4030                         if (insert == 1) {
4031                                 LIST_REMOVE(valid_entry, next);
4032                                 rte_free(valid_entry);
4033                         } else {
4034                                 rte_free(valid_entry);
4035                                 insert = 1;
4036                         }
4037                 }
4038         }
4039
4040         /* Not find any entry to merge, insert */
4041         if (insert == 0) {
4042                 if (prev != NULL)
4043                         LIST_INSERT_AFTER(prev, valid_entry, next);
4044                 else if (next != NULL)
4045                         LIST_INSERT_BEFORE(next, valid_entry, next);
4046                 else /* It's empty list, insert to head */
4047                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4048         }
4049
4050         pool->num_free += valid_entry->len;
4051         pool->num_alloc -= valid_entry->len;
4052
4053         return 0;
4054 }
4055
4056 static int
4057 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4058                        uint16_t num)
4059 {
4060         struct pool_entry *entry, *valid_entry;
4061
4062         if (pool == NULL || num == 0) {
4063                 PMD_DRV_LOG(ERR, "Invalid parameter");
4064                 return -EINVAL;
4065         }
4066
4067         if (pool->num_free < num) {
4068                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4069                             num, pool->num_free);
4070                 return -ENOMEM;
4071         }
4072
4073         valid_entry = NULL;
4074         /* Lookup  in free list and find most fit one */
4075         LIST_FOREACH(entry, &pool->free_list, next) {
4076                 if (entry->len >= num) {
4077                         /* Find best one */
4078                         if (entry->len == num) {
4079                                 valid_entry = entry;
4080                                 break;
4081                         }
4082                         if (valid_entry == NULL || valid_entry->len > entry->len)
4083                                 valid_entry = entry;
4084                 }
4085         }
4086
4087         /* Not find one to satisfy the request, return */
4088         if (valid_entry == NULL) {
4089                 PMD_DRV_LOG(ERR, "No valid entry found");
4090                 return -ENOMEM;
4091         }
4092         /**
4093          * The entry have equal queue number as requested,
4094          * remove it from alloc_list.
4095          */
4096         if (valid_entry->len == num) {
4097                 LIST_REMOVE(valid_entry, next);
4098         } else {
4099                 /**
4100                  * The entry have more numbers than requested,
4101                  * create a new entry for alloc_list and minus its
4102                  * queue base and number in free_list.
4103                  */
4104                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4105                 if (entry == NULL) {
4106                         PMD_DRV_LOG(ERR,
4107                                 "Failed to allocate memory for resource pool");
4108                         return -ENOMEM;
4109                 }
4110                 entry->base = valid_entry->base;
4111                 entry->len = num;
4112                 valid_entry->base += num;
4113                 valid_entry->len -= num;
4114                 valid_entry = entry;
4115         }
4116
4117         /* Insert it into alloc list, not sorted */
4118         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4119
4120         pool->num_free -= valid_entry->len;
4121         pool->num_alloc += valid_entry->len;
4122
4123         return valid_entry->base + pool->base;
4124 }
4125
4126 /**
4127  * bitmap_is_subset - Check whether src2 is subset of src1
4128  **/
4129 static inline int
4130 bitmap_is_subset(uint8_t src1, uint8_t src2)
4131 {
4132         return !((src1 ^ src2) & src2);
4133 }
4134
4135 static enum i40e_status_code
4136 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4137 {
4138         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4139
4140         /* If DCB is not supported, only default TC is supported */
4141         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4142                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4143                 return I40E_NOT_SUPPORTED;
4144         }
4145
4146         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4147                 PMD_DRV_LOG(ERR,
4148                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4149                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4150                 return I40E_NOT_SUPPORTED;
4151         }
4152         return I40E_SUCCESS;
4153 }
4154
4155 int
4156 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4157                                 struct i40e_vsi_vlan_pvid_info *info)
4158 {
4159         struct i40e_hw *hw;
4160         struct i40e_vsi_context ctxt;
4161         uint8_t vlan_flags = 0;
4162         int ret;
4163
4164         if (vsi == NULL || info == NULL) {
4165                 PMD_DRV_LOG(ERR, "invalid parameters");
4166                 return I40E_ERR_PARAM;
4167         }
4168
4169         if (info->on) {
4170                 vsi->info.pvid = info->config.pvid;
4171                 /**
4172                  * If insert pvid is enabled, only tagged pkts are
4173                  * allowed to be sent out.
4174                  */
4175                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4176                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4177         } else {
4178                 vsi->info.pvid = 0;
4179                 if (info->config.reject.tagged == 0)
4180                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4181
4182                 if (info->config.reject.untagged == 0)
4183                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4184         }
4185         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4186                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4187         vsi->info.port_vlan_flags |= vlan_flags;
4188         vsi->info.valid_sections =
4189                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4190         memset(&ctxt, 0, sizeof(ctxt));
4191         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4192         ctxt.seid = vsi->seid;
4193
4194         hw = I40E_VSI_TO_HW(vsi);
4195         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4196         if (ret != I40E_SUCCESS)
4197                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4198
4199         return ret;
4200 }
4201
4202 static int
4203 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4204 {
4205         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4206         int i, ret;
4207         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4208
4209         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4210         if (ret != I40E_SUCCESS)
4211                 return ret;
4212
4213         if (!vsi->seid) {
4214                 PMD_DRV_LOG(ERR, "seid not valid");
4215                 return -EINVAL;
4216         }
4217
4218         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4219         tc_bw_data.tc_valid_bits = enabled_tcmap;
4220         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4221                 tc_bw_data.tc_bw_credits[i] =
4222                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4223
4224         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4225         if (ret != I40E_SUCCESS) {
4226                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4227                 return ret;
4228         }
4229
4230         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4231                                         sizeof(vsi->info.qs_handle));
4232         return I40E_SUCCESS;
4233 }
4234
4235 static enum i40e_status_code
4236 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4237                                  struct i40e_aqc_vsi_properties_data *info,
4238                                  uint8_t enabled_tcmap)
4239 {
4240         enum i40e_status_code ret;
4241         int i, total_tc = 0;
4242         uint16_t qpnum_per_tc, bsf, qp_idx;
4243
4244         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4245         if (ret != I40E_SUCCESS)
4246                 return ret;
4247
4248         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4249                 if (enabled_tcmap & (1 << i))
4250                         total_tc++;
4251         vsi->enabled_tc = enabled_tcmap;
4252
4253         /* Number of queues per enabled TC */
4254         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4255         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4256         bsf = rte_bsf32(qpnum_per_tc);
4257
4258         /* Adjust the queue number to actual queues that can be applied */
4259         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4260                 vsi->nb_qps = qpnum_per_tc * total_tc;
4261
4262         /**
4263          * Configure TC and queue mapping parameters, for enabled TC,
4264          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4265          * default queue will serve it.
4266          */
4267         qp_idx = 0;
4268         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4269                 if (vsi->enabled_tc & (1 << i)) {
4270                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4271                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4272                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4273                         qp_idx += qpnum_per_tc;
4274                 } else
4275                         info->tc_mapping[i] = 0;
4276         }
4277
4278         /* Associate queue number with VSI */
4279         if (vsi->type == I40E_VSI_SRIOV) {
4280                 info->mapping_flags |=
4281                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4282                 for (i = 0; i < vsi->nb_qps; i++)
4283                         info->queue_mapping[i] =
4284                                 rte_cpu_to_le_16(vsi->base_queue + i);
4285         } else {
4286                 info->mapping_flags |=
4287                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4288                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4289         }
4290         info->valid_sections |=
4291                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4292
4293         return I40E_SUCCESS;
4294 }
4295
4296 static int
4297 i40e_veb_release(struct i40e_veb *veb)
4298 {
4299         struct i40e_vsi *vsi;
4300         struct i40e_hw *hw;
4301
4302         if (veb == NULL)
4303                 return -EINVAL;
4304
4305         if (!TAILQ_EMPTY(&veb->head)) {
4306                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4307                 return -EACCES;
4308         }
4309         /* associate_vsi field is NULL for floating VEB */
4310         if (veb->associate_vsi != NULL) {
4311                 vsi = veb->associate_vsi;
4312                 hw = I40E_VSI_TO_HW(vsi);
4313
4314                 vsi->uplink_seid = veb->uplink_seid;
4315                 vsi->veb = NULL;
4316         } else {
4317                 veb->associate_pf->main_vsi->floating_veb = NULL;
4318                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4319         }
4320
4321         i40e_aq_delete_element(hw, veb->seid, NULL);
4322         rte_free(veb);
4323         return I40E_SUCCESS;
4324 }
4325
4326 /* Setup a veb */
4327 static struct i40e_veb *
4328 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4329 {
4330         struct i40e_veb *veb;
4331         int ret;
4332         struct i40e_hw *hw;
4333
4334         if (pf == NULL) {
4335                 PMD_DRV_LOG(ERR,
4336                             "veb setup failed, associated PF shouldn't null");
4337                 return NULL;
4338         }
4339         hw = I40E_PF_TO_HW(pf);
4340
4341         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4342         if (!veb) {
4343                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4344                 goto fail;
4345         }
4346
4347         veb->associate_vsi = vsi;
4348         veb->associate_pf = pf;
4349         TAILQ_INIT(&veb->head);
4350         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4351
4352         /* create floating veb if vsi is NULL */
4353         if (vsi != NULL) {
4354                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4355                                       I40E_DEFAULT_TCMAP, false,
4356                                       &veb->seid, false, NULL);
4357         } else {
4358                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4359                                       true, &veb->seid, false, NULL);
4360         }
4361
4362         if (ret != I40E_SUCCESS) {
4363                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4364                             hw->aq.asq_last_status);
4365                 goto fail;
4366         }
4367         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4368
4369         /* get statistics index */
4370         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4371                                 &veb->stats_idx, NULL, NULL, NULL);
4372         if (ret != I40E_SUCCESS) {
4373                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4374                             hw->aq.asq_last_status);
4375                 goto fail;
4376         }
4377         /* Get VEB bandwidth, to be implemented */
4378         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4379         if (vsi)
4380                 vsi->uplink_seid = veb->seid;
4381
4382         return veb;
4383 fail:
4384         rte_free(veb);
4385         return NULL;
4386 }
4387
4388 int
4389 i40e_vsi_release(struct i40e_vsi *vsi)
4390 {
4391         struct i40e_pf *pf;
4392         struct i40e_hw *hw;
4393         struct i40e_vsi_list *vsi_list;
4394         void *temp;
4395         int ret;
4396         struct i40e_mac_filter *f;
4397         uint16_t user_param;
4398
4399         if (!vsi)
4400                 return I40E_SUCCESS;
4401
4402         if (!vsi->adapter)
4403                 return -EFAULT;
4404
4405         user_param = vsi->user_param;
4406
4407         pf = I40E_VSI_TO_PF(vsi);
4408         hw = I40E_VSI_TO_HW(vsi);
4409
4410         /* VSI has child to attach, release child first */
4411         if (vsi->veb) {
4412                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4413                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4414                                 return -1;
4415                 }
4416                 i40e_veb_release(vsi->veb);
4417         }
4418
4419         if (vsi->floating_veb) {
4420                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4421                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4422                                 return -1;
4423                 }
4424         }
4425
4426         /* Remove all macvlan filters of the VSI */
4427         i40e_vsi_remove_all_macvlan_filter(vsi);
4428         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4429                 rte_free(f);
4430
4431         if (vsi->type != I40E_VSI_MAIN &&
4432             ((vsi->type != I40E_VSI_SRIOV) ||
4433             !pf->floating_veb_list[user_param])) {
4434                 /* Remove vsi from parent's sibling list */
4435                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4436                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4437                         return I40E_ERR_PARAM;
4438                 }
4439                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4440                                 &vsi->sib_vsi_list, list);
4441
4442                 /* Remove all switch element of the VSI */
4443                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4444                 if (ret != I40E_SUCCESS)
4445                         PMD_DRV_LOG(ERR, "Failed to delete element");
4446         }
4447
4448         if ((vsi->type == I40E_VSI_SRIOV) &&
4449             pf->floating_veb_list[user_param]) {
4450                 /* Remove vsi from parent's sibling list */
4451                 if (vsi->parent_vsi == NULL ||
4452                     vsi->parent_vsi->floating_veb == NULL) {
4453                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4454                         return I40E_ERR_PARAM;
4455                 }
4456                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4457                              &vsi->sib_vsi_list, list);
4458
4459                 /* Remove all switch element of the VSI */
4460                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4461                 if (ret != I40E_SUCCESS)
4462                         PMD_DRV_LOG(ERR, "Failed to delete element");
4463         }
4464
4465         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4466
4467         if (vsi->type != I40E_VSI_SRIOV)
4468                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4469         rte_free(vsi);
4470
4471         return I40E_SUCCESS;
4472 }
4473
4474 static int
4475 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4476 {
4477         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4478         struct i40e_aqc_remove_macvlan_element_data def_filter;
4479         struct i40e_mac_filter_info filter;
4480         int ret;
4481
4482         if (vsi->type != I40E_VSI_MAIN)
4483                 return I40E_ERR_CONFIG;
4484         memset(&def_filter, 0, sizeof(def_filter));
4485         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4486                                         ETH_ADDR_LEN);
4487         def_filter.vlan_tag = 0;
4488         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4489                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4490         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4491         if (ret != I40E_SUCCESS) {
4492                 struct i40e_mac_filter *f;
4493                 struct ether_addr *mac;
4494
4495                 PMD_DRV_LOG(WARNING,
4496                         "Cannot remove the default macvlan filter");
4497                 /* It needs to add the permanent mac into mac list */
4498                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4499                 if (f == NULL) {
4500                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4501                         return I40E_ERR_NO_MEMORY;
4502                 }
4503                 mac = &f->mac_info.mac_addr;
4504                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4505                                 ETH_ADDR_LEN);
4506                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4507                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4508                 vsi->mac_num++;
4509
4510                 return ret;
4511         }
4512         (void)rte_memcpy(&filter.mac_addr,
4513                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4514         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4515         return i40e_vsi_add_mac(vsi, &filter);
4516 }
4517
4518 /*
4519  * i40e_vsi_get_bw_config - Query VSI BW Information
4520  * @vsi: the VSI to be queried
4521  *
4522  * Returns 0 on success, negative value on failure
4523  */
4524 static enum i40e_status_code
4525 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4526 {
4527         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4528         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4529         struct i40e_hw *hw = &vsi->adapter->hw;
4530         i40e_status ret;
4531         int i;
4532         uint32_t bw_max;
4533
4534         memset(&bw_config, 0, sizeof(bw_config));
4535         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4536         if (ret != I40E_SUCCESS) {
4537                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4538                             hw->aq.asq_last_status);
4539                 return ret;
4540         }
4541
4542         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4543         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4544                                         &ets_sla_config, NULL);
4545         if (ret != I40E_SUCCESS) {
4546                 PMD_DRV_LOG(ERR,
4547                         "VSI failed to get TC bandwdith configuration %u",
4548                         hw->aq.asq_last_status);
4549                 return ret;
4550         }
4551
4552         /* store and print out BW info */
4553         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4554         vsi->bw_info.bw_max = bw_config.max_bw;
4555         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4556         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4557         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4558                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4559                      I40E_16_BIT_WIDTH);
4560         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4561                 vsi->bw_info.bw_ets_share_credits[i] =
4562                                 ets_sla_config.share_credits[i];
4563                 vsi->bw_info.bw_ets_credits[i] =
4564                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4565                 /* 4 bits per TC, 4th bit is reserved */
4566                 vsi->bw_info.bw_ets_max[i] =
4567                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4568                                   RTE_LEN2MASK(3, uint8_t));
4569                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4570                             vsi->bw_info.bw_ets_share_credits[i]);
4571                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4572                             vsi->bw_info.bw_ets_credits[i]);
4573                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4574                             vsi->bw_info.bw_ets_max[i]);
4575         }
4576
4577         return I40E_SUCCESS;
4578 }
4579
4580 /* i40e_enable_pf_lb
4581  * @pf: pointer to the pf structure
4582  *
4583  * allow loopback on pf
4584  */
4585 static inline void
4586 i40e_enable_pf_lb(struct i40e_pf *pf)
4587 {
4588         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4589         struct i40e_vsi_context ctxt;
4590         int ret;
4591
4592         /* Use the FW API if FW >= v5.0 */
4593         if (hw->aq.fw_maj_ver < 5) {
4594                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4595                 return;
4596         }
4597
4598         memset(&ctxt, 0, sizeof(ctxt));
4599         ctxt.seid = pf->main_vsi_seid;
4600         ctxt.pf_num = hw->pf_id;
4601         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4602         if (ret) {
4603                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4604                             ret, hw->aq.asq_last_status);
4605                 return;
4606         }
4607         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4608         ctxt.info.valid_sections =
4609                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4610         ctxt.info.switch_id |=
4611                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4612
4613         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4614         if (ret)
4615                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4616                             hw->aq.asq_last_status);
4617 }
4618
4619 /* Setup a VSI */
4620 struct i40e_vsi *
4621 i40e_vsi_setup(struct i40e_pf *pf,
4622                enum i40e_vsi_type type,
4623                struct i40e_vsi *uplink_vsi,
4624                uint16_t user_param)
4625 {
4626         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4627         struct i40e_vsi *vsi;
4628         struct i40e_mac_filter_info filter;
4629         int ret;
4630         struct i40e_vsi_context ctxt;
4631         struct ether_addr broadcast =
4632                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4633
4634         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4635             uplink_vsi == NULL) {
4636                 PMD_DRV_LOG(ERR,
4637                         "VSI setup failed, VSI link shouldn't be NULL");
4638                 return NULL;
4639         }
4640
4641         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4642                 PMD_DRV_LOG(ERR,
4643                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4644                 return NULL;
4645         }
4646
4647         /* two situations
4648          * 1.type is not MAIN and uplink vsi is not NULL
4649          * If uplink vsi didn't setup VEB, create one first under veb field
4650          * 2.type is SRIOV and the uplink is NULL
4651          * If floating VEB is NULL, create one veb under floating veb field
4652          */
4653
4654         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4655             uplink_vsi->veb == NULL) {
4656                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4657
4658                 if (uplink_vsi->veb == NULL) {
4659                         PMD_DRV_LOG(ERR, "VEB setup failed");
4660                         return NULL;
4661                 }
4662                 /* set ALLOWLOOPBACk on pf, when veb is created */
4663                 i40e_enable_pf_lb(pf);
4664         }
4665
4666         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4667             pf->main_vsi->floating_veb == NULL) {
4668                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4669
4670                 if (pf->main_vsi->floating_veb == NULL) {
4671                         PMD_DRV_LOG(ERR, "VEB setup failed");
4672                         return NULL;
4673                 }
4674         }
4675
4676         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4677         if (!vsi) {
4678                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4679                 return NULL;
4680         }
4681         TAILQ_INIT(&vsi->mac_list);
4682         vsi->type = type;
4683         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4684         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4685         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4686         vsi->user_param = user_param;
4687         vsi->vlan_anti_spoof_on = 0;
4688         vsi->vlan_filter_on = 0;
4689         /* Allocate queues */
4690         switch (vsi->type) {
4691         case I40E_VSI_MAIN  :
4692                 vsi->nb_qps = pf->lan_nb_qps;
4693                 break;
4694         case I40E_VSI_SRIOV :
4695                 vsi->nb_qps = pf->vf_nb_qps;
4696                 break;
4697         case I40E_VSI_VMDQ2:
4698                 vsi->nb_qps = pf->vmdq_nb_qps;
4699                 break;
4700         case I40E_VSI_FDIR:
4701                 vsi->nb_qps = pf->fdir_nb_qps;
4702                 break;
4703         default:
4704                 goto fail_mem;
4705         }
4706         /*
4707          * The filter status descriptor is reported in rx queue 0,
4708          * while the tx queue for fdir filter programming has no
4709          * such constraints, can be non-zero queues.
4710          * To simplify it, choose FDIR vsi use queue 0 pair.
4711          * To make sure it will use queue 0 pair, queue allocation
4712          * need be done before this function is called
4713          */
4714         if (type != I40E_VSI_FDIR) {
4715                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4716                         if (ret < 0) {
4717                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4718                                                 vsi->seid, ret);
4719                                 goto fail_mem;
4720                         }
4721                         vsi->base_queue = ret;
4722         } else
4723                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4724
4725         /* VF has MSIX interrupt in VF range, don't allocate here */
4726         if (type == I40E_VSI_MAIN) {
4727                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4728                                           RTE_MIN(vsi->nb_qps,
4729                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4730                 if (ret < 0) {
4731                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4732                                     vsi->seid, ret);
4733                         goto fail_queue_alloc;
4734                 }
4735                 vsi->msix_intr = ret;
4736                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4737         } else if (type != I40E_VSI_SRIOV) {
4738                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4739                 if (ret < 0) {
4740                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4741                         goto fail_queue_alloc;
4742                 }
4743                 vsi->msix_intr = ret;
4744                 vsi->nb_msix = 1;
4745         } else {
4746                 vsi->msix_intr = 0;
4747                 vsi->nb_msix = 0;
4748         }
4749
4750         /* Add VSI */
4751         if (type == I40E_VSI_MAIN) {
4752                 /* For main VSI, no need to add since it's default one */
4753                 vsi->uplink_seid = pf->mac_seid;
4754                 vsi->seid = pf->main_vsi_seid;
4755                 /* Bind queues with specific MSIX interrupt */
4756                 /**
4757                  * Needs 2 interrupt at least, one for misc cause which will
4758                  * enabled from OS side, Another for queues binding the
4759                  * interrupt from device side only.
4760                  */
4761
4762                 /* Get default VSI parameters from hardware */
4763                 memset(&ctxt, 0, sizeof(ctxt));
4764                 ctxt.seid = vsi->seid;
4765                 ctxt.pf_num = hw->pf_id;
4766                 ctxt.uplink_seid = vsi->uplink_seid;
4767                 ctxt.vf_num = 0;
4768                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4769                 if (ret != I40E_SUCCESS) {
4770                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4771                         goto fail_msix_alloc;
4772                 }
4773                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4774                         sizeof(struct i40e_aqc_vsi_properties_data));
4775                 vsi->vsi_id = ctxt.vsi_number;
4776                 vsi->info.valid_sections = 0;
4777
4778                 /* Configure tc, enabled TC0 only */
4779                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4780                         I40E_SUCCESS) {
4781                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4782                         goto fail_msix_alloc;
4783                 }
4784
4785                 /* TC, queue mapping */
4786                 memset(&ctxt, 0, sizeof(ctxt));
4787                 vsi->info.valid_sections |=
4788                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4789                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4790                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4791                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4792                         sizeof(struct i40e_aqc_vsi_properties_data));
4793                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4794                                                 I40E_DEFAULT_TCMAP);
4795                 if (ret != I40E_SUCCESS) {
4796                         PMD_DRV_LOG(ERR,
4797                                 "Failed to configure TC queue mapping");
4798                         goto fail_msix_alloc;
4799                 }
4800                 ctxt.seid = vsi->seid;
4801                 ctxt.pf_num = hw->pf_id;
4802                 ctxt.uplink_seid = vsi->uplink_seid;
4803                 ctxt.vf_num = 0;
4804
4805                 /* Update VSI parameters */
4806                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4807                 if (ret != I40E_SUCCESS) {
4808                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4809                         goto fail_msix_alloc;
4810                 }
4811
4812                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4813                                                 sizeof(vsi->info.tc_mapping));
4814                 (void)rte_memcpy(&vsi->info.queue_mapping,
4815                                 &ctxt.info.queue_mapping,
4816                         sizeof(vsi->info.queue_mapping));
4817                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4818                 vsi->info.valid_sections = 0;
4819
4820                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4821                                 ETH_ADDR_LEN);
4822
4823                 /**
4824                  * Updating default filter settings are necessary to prevent
4825                  * reception of tagged packets.
4826                  * Some old firmware configurations load a default macvlan
4827                  * filter which accepts both tagged and untagged packets.
4828                  * The updating is to use a normal filter instead if needed.
4829                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4830                  * The firmware with correct configurations load the default
4831                  * macvlan filter which is expected and cannot be removed.
4832                  */
4833                 i40e_update_default_filter_setting(vsi);
4834                 i40e_config_qinq(hw, vsi);
4835         } else if (type == I40E_VSI_SRIOV) {
4836                 memset(&ctxt, 0, sizeof(ctxt));
4837                 /**
4838                  * For other VSI, the uplink_seid equals to uplink VSI's
4839                  * uplink_seid since they share same VEB
4840                  */
4841                 if (uplink_vsi == NULL)
4842                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4843                 else
4844                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4845                 ctxt.pf_num = hw->pf_id;
4846                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4847                 ctxt.uplink_seid = vsi->uplink_seid;
4848                 ctxt.connection_type = 0x1;
4849                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4850
4851                 /* Use the VEB configuration if FW >= v5.0 */
4852                 if (hw->aq.fw_maj_ver >= 5) {
4853                         /* Configure switch ID */
4854                         ctxt.info.valid_sections |=
4855                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4856                         ctxt.info.switch_id =
4857                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4858                 }
4859
4860                 /* Configure port/vlan */
4861                 ctxt.info.valid_sections |=
4862                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4863                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4864                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4865                                                 hw->func_caps.enabled_tcmap);
4866                 if (ret != I40E_SUCCESS) {
4867                         PMD_DRV_LOG(ERR,
4868                                 "Failed to configure TC queue mapping");
4869                         goto fail_msix_alloc;
4870                 }
4871
4872                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4873                 ctxt.info.valid_sections |=
4874                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4875                 /**
4876                  * Since VSI is not created yet, only configure parameter,
4877                  * will add vsi below.
4878                  */
4879
4880                 i40e_config_qinq(hw, vsi);
4881         } else if (type == I40E_VSI_VMDQ2) {
4882                 memset(&ctxt, 0, sizeof(ctxt));
4883                 /*
4884                  * For other VSI, the uplink_seid equals to uplink VSI's
4885                  * uplink_seid since they share same VEB
4886                  */
4887                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4888                 ctxt.pf_num = hw->pf_id;
4889                 ctxt.vf_num = 0;
4890                 ctxt.uplink_seid = vsi->uplink_seid;
4891                 ctxt.connection_type = 0x1;
4892                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4893
4894                 ctxt.info.valid_sections |=
4895                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4896                 /* user_param carries flag to enable loop back */
4897                 if (user_param) {
4898                         ctxt.info.switch_id =
4899                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4900                         ctxt.info.switch_id |=
4901                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4902                 }
4903
4904                 /* Configure port/vlan */
4905                 ctxt.info.valid_sections |=
4906                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4907                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4908                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4909                                                 I40E_DEFAULT_TCMAP);
4910                 if (ret != I40E_SUCCESS) {
4911                         PMD_DRV_LOG(ERR,
4912                                 "Failed to configure TC queue mapping");
4913                         goto fail_msix_alloc;
4914                 }
4915                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4916                 ctxt.info.valid_sections |=
4917                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4918         } else if (type == I40E_VSI_FDIR) {
4919                 memset(&ctxt, 0, sizeof(ctxt));
4920                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4921                 ctxt.pf_num = hw->pf_id;
4922                 ctxt.vf_num = 0;
4923                 ctxt.uplink_seid = vsi->uplink_seid;
4924                 ctxt.connection_type = 0x1;     /* regular data port */
4925                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4926                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4927                                                 I40E_DEFAULT_TCMAP);
4928                 if (ret != I40E_SUCCESS) {
4929                         PMD_DRV_LOG(ERR,
4930                                 "Failed to configure TC queue mapping.");
4931                         goto fail_msix_alloc;
4932                 }
4933                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4934                 ctxt.info.valid_sections |=
4935                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4936         } else {
4937                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4938                 goto fail_msix_alloc;
4939         }
4940
4941         if (vsi->type != I40E_VSI_MAIN) {
4942                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4943                 if (ret != I40E_SUCCESS) {
4944                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4945                                     hw->aq.asq_last_status);
4946                         goto fail_msix_alloc;
4947                 }
4948                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4949                 vsi->info.valid_sections = 0;
4950                 vsi->seid = ctxt.seid;
4951                 vsi->vsi_id = ctxt.vsi_number;
4952                 vsi->sib_vsi_list.vsi = vsi;
4953                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4954                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4955                                           &vsi->sib_vsi_list, list);
4956                 } else {
4957                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4958                                           &vsi->sib_vsi_list, list);
4959                 }
4960         }
4961
4962         /* MAC/VLAN configuration */
4963         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4964         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4965
4966         ret = i40e_vsi_add_mac(vsi, &filter);
4967         if (ret != I40E_SUCCESS) {
4968                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4969                 goto fail_msix_alloc;
4970         }
4971
4972         /* Get VSI BW information */
4973         i40e_vsi_get_bw_config(vsi);
4974         return vsi;
4975 fail_msix_alloc:
4976         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4977 fail_queue_alloc:
4978         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4979 fail_mem:
4980         rte_free(vsi);
4981         return NULL;
4982 }
4983
4984 /* Configure vlan filter on or off */
4985 int
4986 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4987 {
4988         int i, num;
4989         struct i40e_mac_filter *f;
4990         void *temp;
4991         struct i40e_mac_filter_info *mac_filter;
4992         enum rte_mac_filter_type desired_filter;
4993         int ret = I40E_SUCCESS;
4994
4995         if (on) {
4996                 /* Filter to match MAC and VLAN */
4997                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4998         } else {
4999                 /* Filter to match only MAC */
5000                 desired_filter = RTE_MAC_PERFECT_MATCH;
5001         }
5002
5003         num = vsi->mac_num;
5004
5005         mac_filter = rte_zmalloc("mac_filter_info_data",
5006                                  num * sizeof(*mac_filter), 0);
5007         if (mac_filter == NULL) {
5008                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5009                 return I40E_ERR_NO_MEMORY;
5010         }
5011
5012         i = 0;
5013
5014         /* Remove all existing mac */
5015         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5016                 mac_filter[i] = f->mac_info;
5017                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5018                 if (ret) {
5019                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5020                                     on ? "enable" : "disable");
5021                         goto DONE;
5022                 }
5023                 i++;
5024         }
5025
5026         /* Override with new filter */
5027         for (i = 0; i < num; i++) {
5028                 mac_filter[i].filter_type = desired_filter;
5029                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5030                 if (ret) {
5031                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5032                                     on ? "enable" : "disable");
5033                         goto DONE;
5034                 }
5035         }
5036
5037 DONE:
5038         rte_free(mac_filter);
5039         return ret;
5040 }
5041
5042 /* Configure vlan stripping on or off */
5043 int
5044 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5045 {
5046         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5047         struct i40e_vsi_context ctxt;
5048         uint8_t vlan_flags;
5049         int ret = I40E_SUCCESS;
5050
5051         /* Check if it has been already on or off */
5052         if (vsi->info.valid_sections &
5053                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5054                 if (on) {
5055                         if ((vsi->info.port_vlan_flags &
5056                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5057                                 return 0; /* already on */
5058                 } else {
5059                         if ((vsi->info.port_vlan_flags &
5060                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5061                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5062                                 return 0; /* already off */
5063                 }
5064         }
5065
5066         if (on)
5067                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5068         else
5069                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5070         vsi->info.valid_sections =
5071                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5072         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5073         vsi->info.port_vlan_flags |= vlan_flags;
5074         ctxt.seid = vsi->seid;
5075         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5076         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5077         if (ret)
5078                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5079                             on ? "enable" : "disable");
5080
5081         return ret;
5082 }
5083
5084 static int
5085 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5086 {
5087         struct rte_eth_dev_data *data = dev->data;
5088         int ret;
5089         int mask = 0;
5090
5091         /* Apply vlan offload setting */
5092         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5093         i40e_vlan_offload_set(dev, mask);
5094
5095         /* Apply double-vlan setting, not implemented yet */
5096
5097         /* Apply pvid setting */
5098         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5099                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5100         if (ret)
5101                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5102
5103         return ret;
5104 }
5105
5106 static int
5107 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5108 {
5109         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5110
5111         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5112 }
5113
5114 static int
5115 i40e_update_flow_control(struct i40e_hw *hw)
5116 {
5117 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5118         struct i40e_link_status link_status;
5119         uint32_t rxfc = 0, txfc = 0, reg;
5120         uint8_t an_info;
5121         int ret;
5122
5123         memset(&link_status, 0, sizeof(link_status));
5124         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5125         if (ret != I40E_SUCCESS) {
5126                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5127                 goto write_reg; /* Disable flow control */
5128         }
5129
5130         an_info = hw->phy.link_info.an_info;
5131         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5132                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5133                 ret = I40E_ERR_NOT_READY;
5134                 goto write_reg; /* Disable flow control */
5135         }
5136         /**
5137          * If link auto negotiation is enabled, flow control needs to
5138          * be configured according to it
5139          */
5140         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5141         case I40E_LINK_PAUSE_RXTX:
5142                 rxfc = 1;
5143                 txfc = 1;
5144                 hw->fc.current_mode = I40E_FC_FULL;
5145                 break;
5146         case I40E_AQ_LINK_PAUSE_RX:
5147                 rxfc = 1;
5148                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5149                 break;
5150         case I40E_AQ_LINK_PAUSE_TX:
5151                 txfc = 1;
5152                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5153                 break;
5154         default:
5155                 hw->fc.current_mode = I40E_FC_NONE;
5156                 break;
5157         }
5158
5159 write_reg:
5160         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5161                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5162         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5163         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5164         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5165         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5166
5167         return ret;
5168 }
5169
5170 /* PF setup */
5171 static int
5172 i40e_pf_setup(struct i40e_pf *pf)
5173 {
5174         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5175         struct i40e_filter_control_settings settings;
5176         struct i40e_vsi *vsi;
5177         int ret;
5178
5179         /* Clear all stats counters */
5180         pf->offset_loaded = FALSE;
5181         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5182         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5183
5184         ret = i40e_pf_get_switch_config(pf);
5185         if (ret != I40E_SUCCESS) {
5186                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5187                 return ret;
5188         }
5189         if (pf->flags & I40E_FLAG_FDIR) {
5190                 /* make queue allocated first, let FDIR use queue pair 0*/
5191                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5192                 if (ret != I40E_FDIR_QUEUE_ID) {
5193                         PMD_DRV_LOG(ERR,
5194                                 "queue allocation fails for FDIR: ret =%d",
5195                                 ret);
5196                         pf->flags &= ~I40E_FLAG_FDIR;
5197                 }
5198         }
5199         /*  main VSI setup */
5200         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5201         if (!vsi) {
5202                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5203                 return I40E_ERR_NOT_READY;
5204         }
5205         pf->main_vsi = vsi;
5206
5207         /* Configure filter control */
5208         memset(&settings, 0, sizeof(settings));
5209         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5210                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5211         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5212                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5213         else {
5214                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5215                         hw->func_caps.rss_table_size);
5216                 return I40E_ERR_PARAM;
5217         }
5218         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5219                 hw->func_caps.rss_table_size);
5220         pf->hash_lut_size = hw->func_caps.rss_table_size;
5221
5222         /* Enable ethtype and macvlan filters */
5223         settings.enable_ethtype = TRUE;
5224         settings.enable_macvlan = TRUE;
5225         ret = i40e_set_filter_control(hw, &settings);
5226         if (ret)
5227                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5228                                                                 ret);
5229
5230         /* Update flow control according to the auto negotiation */
5231         i40e_update_flow_control(hw);
5232
5233         return I40E_SUCCESS;
5234 }
5235
5236 int
5237 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5238 {
5239         uint32_t reg;
5240         uint16_t j;
5241
5242         /**
5243          * Set or clear TX Queue Disable flags,
5244          * which is required by hardware.
5245          */
5246         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5247         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5248
5249         /* Wait until the request is finished */
5250         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5251                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5252                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5253                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5254                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5255                                                         & 0x1))) {
5256                         break;
5257                 }
5258         }
5259         if (on) {
5260                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5261                         return I40E_SUCCESS; /* already on, skip next steps */
5262
5263                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5264                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5265         } else {
5266                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5267                         return I40E_SUCCESS; /* already off, skip next steps */
5268                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5269         }
5270         /* Write the register */
5271         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5272         /* Check the result */
5273         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5274                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5275                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5276                 if (on) {
5277                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5278                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5279                                 break;
5280                 } else {
5281                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5282                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5283                                 break;
5284                 }
5285         }
5286         /* Check if it is timeout */
5287         if (j >= I40E_CHK_Q_ENA_COUNT) {
5288                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5289                             (on ? "enable" : "disable"), q_idx);
5290                 return I40E_ERR_TIMEOUT;
5291         }
5292
5293         return I40E_SUCCESS;
5294 }
5295
5296 /* Swith on or off the tx queues */
5297 static int
5298 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5299 {
5300         struct rte_eth_dev_data *dev_data = pf->dev_data;
5301         struct i40e_tx_queue *txq;
5302         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5303         uint16_t i;
5304         int ret;
5305
5306         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5307                 txq = dev_data->tx_queues[i];
5308                 /* Don't operate the queue if not configured or
5309                  * if starting only per queue */
5310                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5311                         continue;
5312                 if (on)
5313                         ret = i40e_dev_tx_queue_start(dev, i);
5314                 else
5315                         ret = i40e_dev_tx_queue_stop(dev, i);
5316                 if ( ret != I40E_SUCCESS)
5317                         return ret;
5318         }
5319
5320         return I40E_SUCCESS;
5321 }
5322
5323 int
5324 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5325 {
5326         uint32_t reg;
5327         uint16_t j;
5328
5329         /* Wait until the request is finished */
5330         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5331                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5332                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5333                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5334                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5335                         break;
5336         }
5337
5338         if (on) {
5339                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5340                         return I40E_SUCCESS; /* Already on, skip next steps */
5341                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5342         } else {
5343                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5344                         return I40E_SUCCESS; /* Already off, skip next steps */
5345                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5346         }
5347
5348         /* Write the register */
5349         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5350         /* Check the result */
5351         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5352                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5353                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5354                 if (on) {
5355                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5356                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5357                                 break;
5358                 } else {
5359                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5360                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5361                                 break;
5362                 }
5363         }
5364
5365         /* Check if it is timeout */
5366         if (j >= I40E_CHK_Q_ENA_COUNT) {
5367                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5368                             (on ? "enable" : "disable"), q_idx);
5369                 return I40E_ERR_TIMEOUT;
5370         }
5371
5372         return I40E_SUCCESS;
5373 }
5374 /* Switch on or off the rx queues */
5375 static int
5376 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5377 {
5378         struct rte_eth_dev_data *dev_data = pf->dev_data;
5379         struct i40e_rx_queue *rxq;
5380         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5381         uint16_t i;
5382         int ret;
5383
5384         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5385                 rxq = dev_data->rx_queues[i];
5386                 /* Don't operate the queue if not configured or
5387                  * if starting only per queue */
5388                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5389                         continue;
5390                 if (on)
5391                         ret = i40e_dev_rx_queue_start(dev, i);
5392                 else
5393                         ret = i40e_dev_rx_queue_stop(dev, i);
5394                 if (ret != I40E_SUCCESS)
5395                         return ret;
5396         }
5397
5398         return I40E_SUCCESS;
5399 }
5400
5401 /* Switch on or off all the rx/tx queues */
5402 int
5403 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5404 {
5405         int ret;
5406
5407         if (on) {
5408                 /* enable rx queues before enabling tx queues */
5409                 ret = i40e_dev_switch_rx_queues(pf, on);
5410                 if (ret) {
5411                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5412                         return ret;
5413                 }
5414                 ret = i40e_dev_switch_tx_queues(pf, on);
5415         } else {
5416                 /* Stop tx queues before stopping rx queues */
5417                 ret = i40e_dev_switch_tx_queues(pf, on);
5418                 if (ret) {
5419                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5420                         return ret;
5421                 }
5422                 ret = i40e_dev_switch_rx_queues(pf, on);
5423         }
5424
5425         return ret;
5426 }
5427
5428 /* Initialize VSI for TX */
5429 static int
5430 i40e_dev_tx_init(struct i40e_pf *pf)
5431 {
5432         struct rte_eth_dev_data *data = pf->dev_data;
5433         uint16_t i;
5434         uint32_t ret = I40E_SUCCESS;
5435         struct i40e_tx_queue *txq;
5436
5437         for (i = 0; i < data->nb_tx_queues; i++) {
5438                 txq = data->tx_queues[i];
5439                 if (!txq || !txq->q_set)
5440                         continue;
5441                 ret = i40e_tx_queue_init(txq);
5442                 if (ret != I40E_SUCCESS)
5443                         break;
5444         }
5445         if (ret == I40E_SUCCESS)
5446                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5447                                      ->eth_dev);
5448
5449         return ret;
5450 }
5451
5452 /* Initialize VSI for RX */
5453 static int
5454 i40e_dev_rx_init(struct i40e_pf *pf)
5455 {
5456         struct rte_eth_dev_data *data = pf->dev_data;
5457         int ret = I40E_SUCCESS;
5458         uint16_t i;
5459         struct i40e_rx_queue *rxq;
5460
5461         i40e_pf_config_mq_rx(pf);
5462         for (i = 0; i < data->nb_rx_queues; i++) {
5463                 rxq = data->rx_queues[i];
5464                 if (!rxq || !rxq->q_set)
5465                         continue;
5466
5467                 ret = i40e_rx_queue_init(rxq);
5468                 if (ret != I40E_SUCCESS) {
5469                         PMD_DRV_LOG(ERR,
5470                                 "Failed to do RX queue initialization");
5471                         break;
5472                 }
5473         }
5474         if (ret == I40E_SUCCESS)
5475                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5476                                      ->eth_dev);
5477
5478         return ret;
5479 }
5480
5481 static int
5482 i40e_dev_rxtx_init(struct i40e_pf *pf)
5483 {
5484         int err;
5485
5486         err = i40e_dev_tx_init(pf);
5487         if (err) {
5488                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5489                 return err;
5490         }
5491         err = i40e_dev_rx_init(pf);
5492         if (err) {
5493                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5494                 return err;
5495         }
5496
5497         return err;
5498 }
5499
5500 static int
5501 i40e_vmdq_setup(struct rte_eth_dev *dev)
5502 {
5503         struct rte_eth_conf *conf = &dev->data->dev_conf;
5504         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5505         int i, err, conf_vsis, j, loop;
5506         struct i40e_vsi *vsi;
5507         struct i40e_vmdq_info *vmdq_info;
5508         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5509         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5510
5511         /*
5512          * Disable interrupt to avoid message from VF. Furthermore, it will
5513          * avoid race condition in VSI creation/destroy.
5514          */
5515         i40e_pf_disable_irq0(hw);
5516
5517         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5518                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5519                 return -ENOTSUP;
5520         }
5521
5522         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5523         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5524                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5525                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5526                         pf->max_nb_vmdq_vsi);
5527                 return -ENOTSUP;
5528         }
5529
5530         if (pf->vmdq != NULL) {
5531                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5532                 return 0;
5533         }
5534
5535         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5536                                 sizeof(*vmdq_info) * conf_vsis, 0);
5537
5538         if (pf->vmdq == NULL) {
5539                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5540                 return -ENOMEM;
5541         }
5542
5543         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5544
5545         /* Create VMDQ VSI */
5546         for (i = 0; i < conf_vsis; i++) {
5547                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5548                                 vmdq_conf->enable_loop_back);
5549                 if (vsi == NULL) {
5550                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5551                         err = -1;
5552                         goto err_vsi_setup;
5553                 }
5554                 vmdq_info = &pf->vmdq[i];
5555                 vmdq_info->pf = pf;
5556                 vmdq_info->vsi = vsi;
5557         }
5558         pf->nb_cfg_vmdq_vsi = conf_vsis;
5559
5560         /* Configure Vlan */
5561         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5562         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5563                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5564                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5565                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5566                                         vmdq_conf->pool_map[i].vlan_id, j);
5567
5568                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5569                                                 vmdq_conf->pool_map[i].vlan_id);
5570                                 if (err) {
5571                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5572                                         err = -1;
5573                                         goto err_vsi_setup;
5574                                 }
5575                         }
5576                 }
5577         }
5578
5579         i40e_pf_enable_irq0(hw);
5580
5581         return 0;
5582
5583 err_vsi_setup:
5584         for (i = 0; i < conf_vsis; i++)
5585                 if (pf->vmdq[i].vsi == NULL)
5586                         break;
5587                 else
5588                         i40e_vsi_release(pf->vmdq[i].vsi);
5589
5590         rte_free(pf->vmdq);
5591         pf->vmdq = NULL;
5592         i40e_pf_enable_irq0(hw);
5593         return err;
5594 }
5595
5596 static void
5597 i40e_stat_update_32(struct i40e_hw *hw,
5598                    uint32_t reg,
5599                    bool offset_loaded,
5600                    uint64_t *offset,
5601                    uint64_t *stat)
5602 {
5603         uint64_t new_data;
5604
5605         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5606         if (!offset_loaded)
5607                 *offset = new_data;
5608
5609         if (new_data >= *offset)
5610                 *stat = (uint64_t)(new_data - *offset);
5611         else
5612                 *stat = (uint64_t)((new_data +
5613                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5614 }
5615
5616 static void
5617 i40e_stat_update_48(struct i40e_hw *hw,
5618                    uint32_t hireg,
5619                    uint32_t loreg,
5620                    bool offset_loaded,
5621                    uint64_t *offset,
5622                    uint64_t *stat)
5623 {
5624         uint64_t new_data;
5625
5626         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5627         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5628                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5629
5630         if (!offset_loaded)
5631                 *offset = new_data;
5632
5633         if (new_data >= *offset)
5634                 *stat = new_data - *offset;
5635         else
5636                 *stat = (uint64_t)((new_data +
5637                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5638
5639         *stat &= I40E_48_BIT_MASK;
5640 }
5641
5642 /* Disable IRQ0 */
5643 void
5644 i40e_pf_disable_irq0(struct i40e_hw *hw)
5645 {
5646         /* Disable all interrupt types */
5647         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5648         I40E_WRITE_FLUSH(hw);
5649 }
5650
5651 /* Enable IRQ0 */
5652 void
5653 i40e_pf_enable_irq0(struct i40e_hw *hw)
5654 {
5655         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5656                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5657                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5658                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5659         I40E_WRITE_FLUSH(hw);
5660 }
5661
5662 static void
5663 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5664 {
5665         /* read pending request and disable first */
5666         i40e_pf_disable_irq0(hw);
5667         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5668         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5669                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5670
5671         if (no_queue)
5672                 /* Link no queues with irq0 */
5673                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5674                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5675 }
5676
5677 static void
5678 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5679 {
5680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5682         int i;
5683         uint16_t abs_vf_id;
5684         uint32_t index, offset, val;
5685
5686         if (!pf->vfs)
5687                 return;
5688         /**
5689          * Try to find which VF trigger a reset, use absolute VF id to access
5690          * since the reg is global register.
5691          */
5692         for (i = 0; i < pf->vf_num; i++) {
5693                 abs_vf_id = hw->func_caps.vf_base_id + i;
5694                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5695                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5696                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5697                 /* VFR event occured */
5698                 if (val & (0x1 << offset)) {
5699                         int ret;
5700
5701                         /* Clear the event first */
5702                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5703                                                         (0x1 << offset));
5704                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5705                         /**
5706                          * Only notify a VF reset event occured,
5707                          * don't trigger another SW reset
5708                          */
5709                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5710                         if (ret != I40E_SUCCESS)
5711                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5712                 }
5713         }
5714 }
5715
5716 static void
5717 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5718 {
5719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5720         struct i40e_virtchnl_pf_event event;
5721         int i;
5722
5723         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5724         event.event_data.link_event.link_status =
5725                 dev->data->dev_link.link_status;
5726         event.event_data.link_event.link_speed =
5727                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5728
5729         for (i = 0; i < pf->vf_num; i++)
5730                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5731                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5732 }
5733
5734 static void
5735 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5736 {
5737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         struct i40e_arq_event_info info;
5739         uint16_t pending, opcode;
5740         int ret;
5741
5742         info.buf_len = I40E_AQ_BUF_SZ;
5743         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5744         if (!info.msg_buf) {
5745                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5746                 return;
5747         }
5748
5749         pending = 1;
5750         while (pending) {
5751                 ret = i40e_clean_arq_element(hw, &info, &pending);
5752
5753                 if (ret != I40E_SUCCESS) {
5754                         PMD_DRV_LOG(INFO,
5755                                 "Failed to read msg from AdminQ, aq_err: %u",
5756                                 hw->aq.asq_last_status);
5757                         break;
5758                 }
5759                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5760
5761                 switch (opcode) {
5762                 case i40e_aqc_opc_send_msg_to_pf:
5763                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5764                         i40e_pf_host_handle_vf_msg(dev,
5765                                         rte_le_to_cpu_16(info.desc.retval),
5766                                         rte_le_to_cpu_32(info.desc.cookie_high),
5767                                         rte_le_to_cpu_32(info.desc.cookie_low),
5768                                         info.msg_buf,
5769                                         info.msg_len);
5770                         break;
5771                 case i40e_aqc_opc_get_link_status:
5772                         ret = i40e_dev_link_update(dev, 0);
5773                         if (!ret) {
5774                                 i40e_notify_all_vfs_link_status(dev);
5775                                 _rte_eth_dev_callback_process(dev,
5776                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5777                         }
5778                         break;
5779                 default:
5780                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5781                                     opcode);
5782                         break;
5783                 }
5784         }
5785         rte_free(info.msg_buf);
5786 }
5787
5788 /**
5789  * Interrupt handler triggered by NIC  for handling
5790  * specific interrupt.
5791  *
5792  * @param handle
5793  *  Pointer to interrupt handle.
5794  * @param param
5795  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5796  *
5797  * @return
5798  *  void
5799  */
5800 static void
5801 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5802                            void *param)
5803 {
5804         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5806         uint32_t icr0;
5807
5808         /* Disable interrupt */
5809         i40e_pf_disable_irq0(hw);
5810
5811         /* read out interrupt causes */
5812         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5813
5814         /* No interrupt event indicated */
5815         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5816                 PMD_DRV_LOG(INFO, "No interrupt event");
5817                 goto done;
5818         }
5819 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5820         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5821                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5822         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5823                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5824         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5825                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5826         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5827                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5828         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5829                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5830         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5831                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5832         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5833                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5834 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5835
5836         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5837                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5838                 i40e_dev_handle_vfr_event(dev);
5839         }
5840         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5841                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5842                 i40e_dev_handle_aq_msg(dev);
5843         }
5844
5845 done:
5846         /* Enable interrupt */
5847         i40e_pf_enable_irq0(hw);
5848         rte_intr_enable(intr_handle);
5849 }
5850
5851 static int
5852 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5853                          struct i40e_macvlan_filter *filter,
5854                          int total)
5855 {
5856         int ele_num, ele_buff_size;
5857         int num, actual_num, i;
5858         uint16_t flags;
5859         int ret = I40E_SUCCESS;
5860         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5861         struct i40e_aqc_add_macvlan_element_data *req_list;
5862
5863         if (filter == NULL  || total == 0)
5864                 return I40E_ERR_PARAM;
5865         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5866         ele_buff_size = hw->aq.asq_buf_size;
5867
5868         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5869         if (req_list == NULL) {
5870                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5871                 return I40E_ERR_NO_MEMORY;
5872         }
5873
5874         num = 0;
5875         do {
5876                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5877                 memset(req_list, 0, ele_buff_size);
5878
5879                 for (i = 0; i < actual_num; i++) {
5880                         (void)rte_memcpy(req_list[i].mac_addr,
5881                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5882                         req_list[i].vlan_tag =
5883                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5884
5885                         switch (filter[num + i].filter_type) {
5886                         case RTE_MAC_PERFECT_MATCH:
5887                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5888                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5889                                 break;
5890                         case RTE_MACVLAN_PERFECT_MATCH:
5891                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5892                                 break;
5893                         case RTE_MAC_HASH_MATCH:
5894                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5895                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5896                                 break;
5897                         case RTE_MACVLAN_HASH_MATCH:
5898                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5899                                 break;
5900                         default:
5901                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5902                                 ret = I40E_ERR_PARAM;
5903                                 goto DONE;
5904                         }
5905
5906                         req_list[i].queue_number = 0;
5907
5908                         req_list[i].flags = rte_cpu_to_le_16(flags);
5909                 }
5910
5911                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5912                                                 actual_num, NULL);
5913                 if (ret != I40E_SUCCESS) {
5914                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5915                         goto DONE;
5916                 }
5917                 num += actual_num;
5918         } while (num < total);
5919
5920 DONE:
5921         rte_free(req_list);
5922         return ret;
5923 }
5924
5925 static int
5926 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5927                             struct i40e_macvlan_filter *filter,
5928                             int total)
5929 {
5930         int ele_num, ele_buff_size;
5931         int num, actual_num, i;
5932         uint16_t flags;
5933         int ret = I40E_SUCCESS;
5934         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5935         struct i40e_aqc_remove_macvlan_element_data *req_list;
5936
5937         if (filter == NULL  || total == 0)
5938                 return I40E_ERR_PARAM;
5939
5940         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5941         ele_buff_size = hw->aq.asq_buf_size;
5942
5943         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5944         if (req_list == NULL) {
5945                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5946                 return I40E_ERR_NO_MEMORY;
5947         }
5948
5949         num = 0;
5950         do {
5951                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5952                 memset(req_list, 0, ele_buff_size);
5953
5954                 for (i = 0; i < actual_num; i++) {
5955                         (void)rte_memcpy(req_list[i].mac_addr,
5956                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5957                         req_list[i].vlan_tag =
5958                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5959
5960                         switch (filter[num + i].filter_type) {
5961                         case RTE_MAC_PERFECT_MATCH:
5962                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5963                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5964                                 break;
5965                         case RTE_MACVLAN_PERFECT_MATCH:
5966                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5967                                 break;
5968                         case RTE_MAC_HASH_MATCH:
5969                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5970                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5971                                 break;
5972                         case RTE_MACVLAN_HASH_MATCH:
5973                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5974                                 break;
5975                         default:
5976                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5977                                 ret = I40E_ERR_PARAM;
5978                                 goto DONE;
5979                         }
5980                         req_list[i].flags = rte_cpu_to_le_16(flags);
5981                 }
5982
5983                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5984                                                 actual_num, NULL);
5985                 if (ret != I40E_SUCCESS) {
5986                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5987                         goto DONE;
5988                 }
5989                 num += actual_num;
5990         } while (num < total);
5991
5992 DONE:
5993         rte_free(req_list);
5994         return ret;
5995 }
5996
5997 /* Find out specific MAC filter */
5998 static struct i40e_mac_filter *
5999 i40e_find_mac_filter(struct i40e_vsi *vsi,
6000                          struct ether_addr *macaddr)
6001 {
6002         struct i40e_mac_filter *f;
6003
6004         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6005                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6006                         return f;
6007         }
6008
6009         return NULL;
6010 }
6011
6012 static bool
6013 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6014                          uint16_t vlan_id)
6015 {
6016         uint32_t vid_idx, vid_bit;
6017
6018         if (vlan_id > ETH_VLAN_ID_MAX)
6019                 return 0;
6020
6021         vid_idx = I40E_VFTA_IDX(vlan_id);
6022         vid_bit = I40E_VFTA_BIT(vlan_id);
6023
6024         if (vsi->vfta[vid_idx] & vid_bit)
6025                 return 1;
6026         else
6027                 return 0;
6028 }
6029
6030 static void
6031 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6032                        uint16_t vlan_id, bool on)
6033 {
6034         uint32_t vid_idx, vid_bit;
6035
6036         vid_idx = I40E_VFTA_IDX(vlan_id);
6037         vid_bit = I40E_VFTA_BIT(vlan_id);
6038
6039         if (on)
6040                 vsi->vfta[vid_idx] |= vid_bit;
6041         else
6042                 vsi->vfta[vid_idx] &= ~vid_bit;
6043 }
6044
6045 static void
6046 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6047                      uint16_t vlan_id, bool on)
6048 {
6049         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6050         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6051         int ret;
6052
6053         if (vlan_id > ETH_VLAN_ID_MAX)
6054                 return;
6055
6056         i40e_store_vlan_filter(vsi, vlan_id, on);
6057
6058         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6059                 return;
6060
6061         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6062
6063         if (on) {
6064                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6065                                        &vlan_data, 1, NULL);
6066                 if (ret != I40E_SUCCESS)
6067                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6068         } else {
6069                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6070                                           &vlan_data, 1, NULL);
6071                 if (ret != I40E_SUCCESS)
6072                         PMD_DRV_LOG(ERR,
6073                                     "Failed to remove vlan filter");
6074         }
6075 }
6076
6077 /**
6078  * Find all vlan options for specific mac addr,
6079  * return with actual vlan found.
6080  */
6081 static inline int
6082 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6083                            struct i40e_macvlan_filter *mv_f,
6084                            int num, struct ether_addr *addr)
6085 {
6086         int i;
6087         uint32_t j, k;
6088
6089         /**
6090          * Not to use i40e_find_vlan_filter to decrease the loop time,
6091          * although the code looks complex.
6092           */
6093         if (num < vsi->vlan_num)
6094                 return I40E_ERR_PARAM;
6095
6096         i = 0;
6097         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6098                 if (vsi->vfta[j]) {
6099                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6100                                 if (vsi->vfta[j] & (1 << k)) {
6101                                         if (i > num - 1) {
6102                                                 PMD_DRV_LOG(ERR,
6103                                                         "vlan number doesn't match");
6104                                                 return I40E_ERR_PARAM;
6105                                         }
6106                                         (void)rte_memcpy(&mv_f[i].macaddr,
6107                                                         addr, ETH_ADDR_LEN);
6108                                         mv_f[i].vlan_id =
6109                                                 j * I40E_UINT32_BIT_SIZE + k;
6110                                         i++;
6111                                 }
6112                         }
6113                 }
6114         }
6115         return I40E_SUCCESS;
6116 }
6117
6118 static inline int
6119 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6120                            struct i40e_macvlan_filter *mv_f,
6121                            int num,
6122                            uint16_t vlan)
6123 {
6124         int i = 0;
6125         struct i40e_mac_filter *f;
6126
6127         if (num < vsi->mac_num)
6128                 return I40E_ERR_PARAM;
6129
6130         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6131                 if (i > num - 1) {
6132                         PMD_DRV_LOG(ERR, "buffer number not match");
6133                         return I40E_ERR_PARAM;
6134                 }
6135                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6136                                 ETH_ADDR_LEN);
6137                 mv_f[i].vlan_id = vlan;
6138                 mv_f[i].filter_type = f->mac_info.filter_type;
6139                 i++;
6140         }
6141
6142         return I40E_SUCCESS;
6143 }
6144
6145 static int
6146 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6147 {
6148         int i, j, num;
6149         struct i40e_mac_filter *f;
6150         struct i40e_macvlan_filter *mv_f;
6151         int ret = I40E_SUCCESS;
6152
6153         if (vsi == NULL || vsi->mac_num == 0)
6154                 return I40E_ERR_PARAM;
6155
6156         /* Case that no vlan is set */
6157         if (vsi->vlan_num == 0)
6158                 num = vsi->mac_num;
6159         else
6160                 num = vsi->mac_num * vsi->vlan_num;
6161
6162         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6163         if (mv_f == NULL) {
6164                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6165                 return I40E_ERR_NO_MEMORY;
6166         }
6167
6168         i = 0;
6169         if (vsi->vlan_num == 0) {
6170                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6171                         (void)rte_memcpy(&mv_f[i].macaddr,
6172                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6173                         mv_f[i].filter_type = f->mac_info.filter_type;
6174                         mv_f[i].vlan_id = 0;
6175                         i++;
6176                 }
6177         } else {
6178                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6179                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6180                                         vsi->vlan_num, &f->mac_info.mac_addr);
6181                         if (ret != I40E_SUCCESS)
6182                                 goto DONE;
6183                         for (j = i; j < i + vsi->vlan_num; j++)
6184                                 mv_f[j].filter_type = f->mac_info.filter_type;
6185                         i += vsi->vlan_num;
6186                 }
6187         }
6188
6189         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6190 DONE:
6191         rte_free(mv_f);
6192
6193         return ret;
6194 }
6195
6196 int
6197 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6198 {
6199         struct i40e_macvlan_filter *mv_f;
6200         int mac_num;
6201         int ret = I40E_SUCCESS;
6202
6203         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6204                 return I40E_ERR_PARAM;
6205
6206         /* If it's already set, just return */
6207         if (i40e_find_vlan_filter(vsi,vlan))
6208                 return I40E_SUCCESS;
6209
6210         mac_num = vsi->mac_num;
6211
6212         if (mac_num == 0) {
6213                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6214                 return I40E_ERR_PARAM;
6215         }
6216
6217         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6218
6219         if (mv_f == NULL) {
6220                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6221                 return I40E_ERR_NO_MEMORY;
6222         }
6223
6224         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6225
6226         if (ret != I40E_SUCCESS)
6227                 goto DONE;
6228
6229         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6230
6231         if (ret != I40E_SUCCESS)
6232                 goto DONE;
6233
6234         i40e_set_vlan_filter(vsi, vlan, 1);
6235
6236         vsi->vlan_num++;
6237         ret = I40E_SUCCESS;
6238 DONE:
6239         rte_free(mv_f);
6240         return ret;
6241 }
6242
6243 int
6244 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6245 {
6246         struct i40e_macvlan_filter *mv_f;
6247         int mac_num;
6248         int ret = I40E_SUCCESS;
6249
6250         /**
6251          * Vlan 0 is the generic filter for untagged packets
6252          * and can't be removed.
6253          */
6254         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6255                 return I40E_ERR_PARAM;
6256
6257         /* If can't find it, just return */
6258         if (!i40e_find_vlan_filter(vsi, vlan))
6259                 return I40E_ERR_PARAM;
6260
6261         mac_num = vsi->mac_num;
6262
6263         if (mac_num == 0) {
6264                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6265                 return I40E_ERR_PARAM;
6266         }
6267
6268         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6269
6270         if (mv_f == NULL) {
6271                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6272                 return I40E_ERR_NO_MEMORY;
6273         }
6274
6275         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6276
6277         if (ret != I40E_SUCCESS)
6278                 goto DONE;
6279
6280         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6281
6282         if (ret != I40E_SUCCESS)
6283                 goto DONE;
6284
6285         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6286         if (vsi->vlan_num == 1) {
6287                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6288                 if (ret != I40E_SUCCESS)
6289                         goto DONE;
6290
6291                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6292                 if (ret != I40E_SUCCESS)
6293                         goto DONE;
6294         }
6295
6296         i40e_set_vlan_filter(vsi, vlan, 0);
6297
6298         vsi->vlan_num--;
6299         ret = I40E_SUCCESS;
6300 DONE:
6301         rte_free(mv_f);
6302         return ret;
6303 }
6304
6305 int
6306 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6307 {
6308         struct i40e_mac_filter *f;
6309         struct i40e_macvlan_filter *mv_f;
6310         int i, vlan_num = 0;
6311         int ret = I40E_SUCCESS;
6312
6313         /* If it's add and we've config it, return */
6314         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6315         if (f != NULL)
6316                 return I40E_SUCCESS;
6317         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6318                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6319
6320                 /**
6321                  * If vlan_num is 0, that's the first time to add mac,
6322                  * set mask for vlan_id 0.
6323                  */
6324                 if (vsi->vlan_num == 0) {
6325                         i40e_set_vlan_filter(vsi, 0, 1);
6326                         vsi->vlan_num = 1;
6327                 }
6328                 vlan_num = vsi->vlan_num;
6329         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6330                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6331                 vlan_num = 1;
6332
6333         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6334         if (mv_f == NULL) {
6335                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6336                 return I40E_ERR_NO_MEMORY;
6337         }
6338
6339         for (i = 0; i < vlan_num; i++) {
6340                 mv_f[i].filter_type = mac_filter->filter_type;
6341                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6342                                 ETH_ADDR_LEN);
6343         }
6344
6345         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6346                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6347                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6348                                         &mac_filter->mac_addr);
6349                 if (ret != I40E_SUCCESS)
6350                         goto DONE;
6351         }
6352
6353         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6354         if (ret != I40E_SUCCESS)
6355                 goto DONE;
6356
6357         /* Add the mac addr into mac list */
6358         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6359         if (f == NULL) {
6360                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6361                 ret = I40E_ERR_NO_MEMORY;
6362                 goto DONE;
6363         }
6364         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6365                         ETH_ADDR_LEN);
6366         f->mac_info.filter_type = mac_filter->filter_type;
6367         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6368         vsi->mac_num++;
6369
6370         ret = I40E_SUCCESS;
6371 DONE:
6372         rte_free(mv_f);
6373
6374         return ret;
6375 }
6376
6377 int
6378 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6379 {
6380         struct i40e_mac_filter *f;
6381         struct i40e_macvlan_filter *mv_f;
6382         int i, vlan_num;
6383         enum rte_mac_filter_type filter_type;
6384         int ret = I40E_SUCCESS;
6385
6386         /* Can't find it, return an error */
6387         f = i40e_find_mac_filter(vsi, addr);
6388         if (f == NULL)
6389                 return I40E_ERR_PARAM;
6390
6391         vlan_num = vsi->vlan_num;
6392         filter_type = f->mac_info.filter_type;
6393         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6394                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6395                 if (vlan_num == 0) {
6396                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6397                         return I40E_ERR_PARAM;
6398                 }
6399         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6400                         filter_type == RTE_MAC_HASH_MATCH)
6401                 vlan_num = 1;
6402
6403         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6404         if (mv_f == NULL) {
6405                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6406                 return I40E_ERR_NO_MEMORY;
6407         }
6408
6409         for (i = 0; i < vlan_num; i++) {
6410                 mv_f[i].filter_type = filter_type;
6411                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6412                                 ETH_ADDR_LEN);
6413         }
6414         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6415                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6416                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6417                 if (ret != I40E_SUCCESS)
6418                         goto DONE;
6419         }
6420
6421         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6422         if (ret != I40E_SUCCESS)
6423                 goto DONE;
6424
6425         /* Remove the mac addr into mac list */
6426         TAILQ_REMOVE(&vsi->mac_list, f, next);
6427         rte_free(f);
6428         vsi->mac_num--;
6429
6430         ret = I40E_SUCCESS;
6431 DONE:
6432         rte_free(mv_f);
6433         return ret;
6434 }
6435
6436 /* Configure hash enable flags for RSS */
6437 uint64_t
6438 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6439 {
6440         uint64_t hena = 0;
6441
6442         if (!flags)
6443                 return hena;
6444
6445         if (flags & ETH_RSS_FRAG_IPV4)
6446                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6447         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6448                 if (type == I40E_MAC_X722) {
6449                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6450                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6451                 } else
6452                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6453         }
6454         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6455                 if (type == I40E_MAC_X722) {
6456                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6457                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6458                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6459                 } else
6460                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6461         }
6462         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6463                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6464         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6465                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6466         if (flags & ETH_RSS_FRAG_IPV6)
6467                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6468         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6469                 if (type == I40E_MAC_X722) {
6470                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6471                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6472                 } else
6473                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6474         }
6475         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6476                 if (type == I40E_MAC_X722) {
6477                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6478                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6479                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6480                 } else
6481                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6482         }
6483         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6484                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6485         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6486                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6487         if (flags & ETH_RSS_L2_PAYLOAD)
6488                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6489
6490         return hena;
6491 }
6492
6493 /* Parse the hash enable flags */
6494 uint64_t
6495 i40e_parse_hena(uint64_t flags)
6496 {
6497         uint64_t rss_hf = 0;
6498
6499         if (!flags)
6500                 return rss_hf;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6502                 rss_hf |= ETH_RSS_FRAG_IPV4;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6508                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6511         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6512                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6513         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6514                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6515         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6516                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6518                 rss_hf |= ETH_RSS_FRAG_IPV6;
6519         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6520                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6522                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6524                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6534                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6535
6536         return rss_hf;
6537 }
6538
6539 /* Disable RSS */
6540 static void
6541 i40e_pf_disable_rss(struct i40e_pf *pf)
6542 {
6543         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6544         uint64_t hena;
6545
6546         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6547         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6548         if (hw->mac.type == I40E_MAC_X722)
6549                 hena &= ~I40E_RSS_HENA_ALL_X722;
6550         else
6551                 hena &= ~I40E_RSS_HENA_ALL;
6552         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6553         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6554         I40E_WRITE_FLUSH(hw);
6555 }
6556
6557 static int
6558 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6559 {
6560         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6561         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6562         int ret = 0;
6563
6564         if (!key || key_len == 0) {
6565                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6566                 return 0;
6567         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6568                 sizeof(uint32_t)) {
6569                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6570                 return -EINVAL;
6571         }
6572
6573         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6574                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6575                         (struct i40e_aqc_get_set_rss_key_data *)key;
6576
6577                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6578                 if (ret)
6579                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6580         } else {
6581                 uint32_t *hash_key = (uint32_t *)key;
6582                 uint16_t i;
6583
6584                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6585                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6586                 I40E_WRITE_FLUSH(hw);
6587         }
6588
6589         return ret;
6590 }
6591
6592 static int
6593 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6594 {
6595         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6596         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6597         int ret;
6598
6599         if (!key || !key_len)
6600                 return -EINVAL;
6601
6602         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6603                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6604                         (struct i40e_aqc_get_set_rss_key_data *)key);
6605                 if (ret) {
6606                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6607                         return ret;
6608                 }
6609         } else {
6610                 uint32_t *key_dw = (uint32_t *)key;
6611                 uint16_t i;
6612
6613                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6614                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6615         }
6616         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6617
6618         return 0;
6619 }
6620
6621 static int
6622 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6623 {
6624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6625         uint64_t rss_hf;
6626         uint64_t hena;
6627         int ret;
6628
6629         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6630                                rss_conf->rss_key_len);
6631         if (ret)
6632                 return ret;
6633
6634         rss_hf = rss_conf->rss_hf;
6635         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6636         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6637         if (hw->mac.type == I40E_MAC_X722)
6638                 hena &= ~I40E_RSS_HENA_ALL_X722;
6639         else
6640                 hena &= ~I40E_RSS_HENA_ALL;
6641         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6642         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6643         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6644         I40E_WRITE_FLUSH(hw);
6645
6646         return 0;
6647 }
6648
6649 static int
6650 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6651                          struct rte_eth_rss_conf *rss_conf)
6652 {
6653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6656         uint64_t hena;
6657
6658         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6659         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6660         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6661                  ? I40E_RSS_HENA_ALL_X722
6662                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6663                 if (rss_hf != 0) /* Enable RSS */
6664                         return -EINVAL;
6665                 return 0; /* Nothing to do */
6666         }
6667         /* RSS enabled */
6668         if (rss_hf == 0) /* Disable RSS */
6669                 return -EINVAL;
6670
6671         return i40e_hw_rss_hash_set(pf, rss_conf);
6672 }
6673
6674 static int
6675 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6676                            struct rte_eth_rss_conf *rss_conf)
6677 {
6678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680         uint64_t hena;
6681
6682         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6683                          &rss_conf->rss_key_len);
6684
6685         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6686         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6687         rss_conf->rss_hf = i40e_parse_hena(hena);
6688
6689         return 0;
6690 }
6691
6692 static int
6693 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6694 {
6695         switch (filter_type) {
6696         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6697                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6698                 break;
6699         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6700                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6701                 break;
6702         case RTE_TUNNEL_FILTER_IMAC_TENID:
6703                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6704                 break;
6705         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6706                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6707                 break;
6708         case ETH_TUNNEL_FILTER_IMAC:
6709                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6710                 break;
6711         case ETH_TUNNEL_FILTER_OIP:
6712                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6713                 break;
6714         case ETH_TUNNEL_FILTER_IIP:
6715                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6716                 break;
6717         default:
6718                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6719                 return -EINVAL;
6720         }
6721
6722         return 0;
6723 }
6724
6725 /* Convert tunnel filter structure */
6726 static int
6727 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6728                            *cld_filter,
6729                            struct i40e_tunnel_filter *tunnel_filter)
6730 {
6731         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6732                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6733         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6734                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6735         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6736         if ((rte_le_to_cpu_16(cld_filter->flags) &
6737              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6738             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6739                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6740         else
6741                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6742         tunnel_filter->input.flags = cld_filter->flags;
6743         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6744         tunnel_filter->queue = cld_filter->queue_number;
6745
6746         return 0;
6747 }
6748
6749 /* Check if there exists the tunnel filter */
6750 struct i40e_tunnel_filter *
6751 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6752                              const struct i40e_tunnel_filter_input *input)
6753 {
6754         int ret;
6755
6756         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6757         if (ret < 0)
6758                 return NULL;
6759
6760         return tunnel_rule->hash_map[ret];
6761 }
6762
6763 /* Add a tunnel filter into the SW list */
6764 static int
6765 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6766                              struct i40e_tunnel_filter *tunnel_filter)
6767 {
6768         struct i40e_tunnel_rule *rule = &pf->tunnel;
6769         int ret;
6770
6771         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6772         if (ret < 0) {
6773                 PMD_DRV_LOG(ERR,
6774                             "Failed to insert tunnel filter to hash table %d!",
6775                             ret);
6776                 return ret;
6777         }
6778         rule->hash_map[ret] = tunnel_filter;
6779
6780         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6781
6782         return 0;
6783 }
6784
6785 /* Delete a tunnel filter from the SW list */
6786 int
6787 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6788                           struct i40e_tunnel_filter_input *input)
6789 {
6790         struct i40e_tunnel_rule *rule = &pf->tunnel;
6791         struct i40e_tunnel_filter *tunnel_filter;
6792         int ret;
6793
6794         ret = rte_hash_del_key(rule->hash_table, input);
6795         if (ret < 0) {
6796                 PMD_DRV_LOG(ERR,
6797                             "Failed to delete tunnel filter to hash table %d!",
6798                             ret);
6799                 return ret;
6800         }
6801         tunnel_filter = rule->hash_map[ret];
6802         rule->hash_map[ret] = NULL;
6803
6804         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6805         rte_free(tunnel_filter);
6806
6807         return 0;
6808 }
6809
6810 int
6811 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6812                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6813                         uint8_t add)
6814 {
6815         uint16_t ip_type;
6816         uint32_t ipv4_addr;
6817         uint8_t i, tun_type = 0;
6818         /* internal varialbe to convert ipv6 byte order */
6819         uint32_t convert_ipv6[4];
6820         int val, ret = 0;
6821         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6822         struct i40e_vsi *vsi = pf->main_vsi;
6823         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6824         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6825         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6826         struct i40e_tunnel_filter *tunnel, *node;
6827         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6828
6829         cld_filter = rte_zmalloc("tunnel_filter",
6830                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6831                 0);
6832
6833         if (NULL == cld_filter) {
6834                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6835                 return -EINVAL;
6836         }
6837         pfilter = cld_filter;
6838
6839         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6840         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6841
6842         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6843         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6844                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6845                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6846                 rte_memcpy(&pfilter->ipaddr.v4.data,
6847                                 &rte_cpu_to_le_32(ipv4_addr),
6848                                 sizeof(pfilter->ipaddr.v4.data));
6849         } else {
6850                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6851                 for (i = 0; i < 4; i++) {
6852                         convert_ipv6[i] =
6853                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6854                 }
6855                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6856                                 sizeof(pfilter->ipaddr.v6.data));
6857         }
6858
6859         /* check tunneled type */
6860         switch (tunnel_filter->tunnel_type) {
6861         case RTE_TUNNEL_TYPE_VXLAN:
6862                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6863                 break;
6864         case RTE_TUNNEL_TYPE_NVGRE:
6865                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6866                 break;
6867         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6868                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6869                 break;
6870         default:
6871                 /* Other tunnel types is not supported. */
6872                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6873                 rte_free(cld_filter);
6874                 return -EINVAL;
6875         }
6876
6877         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6878                                                 &pfilter->flags);
6879         if (val < 0) {
6880                 rte_free(cld_filter);
6881                 return -EINVAL;
6882         }
6883
6884         pfilter->flags |= rte_cpu_to_le_16(
6885                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6886                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6887         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6888         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6889
6890         /* Check if there is the filter in SW list */
6891         memset(&check_filter, 0, sizeof(check_filter));
6892         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6893         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6894         if (add && node) {
6895                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6896                 return -EINVAL;
6897         }
6898
6899         if (!add && !node) {
6900                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6901                 return -EINVAL;
6902         }
6903
6904         if (add) {
6905                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6906                 if (ret < 0) {
6907                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6908                         return ret;
6909                 }
6910                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6911                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6912                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6913         } else {
6914                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6915                                                    cld_filter, 1);
6916                 if (ret < 0) {
6917                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6918                         return ret;
6919                 }
6920                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6921         }
6922
6923         rte_free(cld_filter);
6924         return ret;
6925 }
6926
6927 static int
6928 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6929 {
6930         uint8_t i;
6931
6932         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6933                 if (pf->vxlan_ports[i] == port)
6934                         return i;
6935         }
6936
6937         return -1;
6938 }
6939
6940 static int
6941 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6942 {
6943         int  idx, ret;
6944         uint8_t filter_idx;
6945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6946
6947         idx = i40e_get_vxlan_port_idx(pf, port);
6948
6949         /* Check if port already exists */
6950         if (idx >= 0) {
6951                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6952                 return -EINVAL;
6953         }
6954
6955         /* Now check if there is space to add the new port */
6956         idx = i40e_get_vxlan_port_idx(pf, 0);
6957         if (idx < 0) {
6958                 PMD_DRV_LOG(ERR,
6959                         "Maximum number of UDP ports reached, not adding port %d",
6960                         port);
6961                 return -ENOSPC;
6962         }
6963
6964         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6965                                         &filter_idx, NULL);
6966         if (ret < 0) {
6967                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6968                 return -1;
6969         }
6970
6971         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6972                          port,  filter_idx);
6973
6974         /* New port: add it and mark its index in the bitmap */
6975         pf->vxlan_ports[idx] = port;
6976         pf->vxlan_bitmap |= (1 << idx);
6977
6978         if (!(pf->flags & I40E_FLAG_VXLAN))
6979                 pf->flags |= I40E_FLAG_VXLAN;
6980
6981         return 0;
6982 }
6983
6984 static int
6985 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6986 {
6987         int idx;
6988         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6989
6990         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6991                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6992                 return -EINVAL;
6993         }
6994
6995         idx = i40e_get_vxlan_port_idx(pf, port);
6996
6997         if (idx < 0) {
6998                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6999                 return -EINVAL;
7000         }
7001
7002         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7003                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7004                 return -1;
7005         }
7006
7007         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7008                         port, idx);
7009
7010         pf->vxlan_ports[idx] = 0;
7011         pf->vxlan_bitmap &= ~(1 << idx);
7012
7013         if (!pf->vxlan_bitmap)
7014                 pf->flags &= ~I40E_FLAG_VXLAN;
7015
7016         return 0;
7017 }
7018
7019 /* Add UDP tunneling port */
7020 static int
7021 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7022                              struct rte_eth_udp_tunnel *udp_tunnel)
7023 {
7024         int ret = 0;
7025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7026
7027         if (udp_tunnel == NULL)
7028                 return -EINVAL;
7029
7030         switch (udp_tunnel->prot_type) {
7031         case RTE_TUNNEL_TYPE_VXLAN:
7032                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7033                 break;
7034
7035         case RTE_TUNNEL_TYPE_GENEVE:
7036         case RTE_TUNNEL_TYPE_TEREDO:
7037                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7038                 ret = -1;
7039                 break;
7040
7041         default:
7042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7043                 ret = -1;
7044                 break;
7045         }
7046
7047         return ret;
7048 }
7049
7050 /* Remove UDP tunneling port */
7051 static int
7052 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7053                              struct rte_eth_udp_tunnel *udp_tunnel)
7054 {
7055         int ret = 0;
7056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7057
7058         if (udp_tunnel == NULL)
7059                 return -EINVAL;
7060
7061         switch (udp_tunnel->prot_type) {
7062         case RTE_TUNNEL_TYPE_VXLAN:
7063                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7064                 break;
7065         case RTE_TUNNEL_TYPE_GENEVE:
7066         case RTE_TUNNEL_TYPE_TEREDO:
7067                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7068                 ret = -1;
7069                 break;
7070         default:
7071                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7072                 ret = -1;
7073                 break;
7074         }
7075
7076         return ret;
7077 }
7078
7079 /* Calculate the maximum number of contiguous PF queues that are configured */
7080 static int
7081 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7082 {
7083         struct rte_eth_dev_data *data = pf->dev_data;
7084         int i, num;
7085         struct i40e_rx_queue *rxq;
7086
7087         num = 0;
7088         for (i = 0; i < pf->lan_nb_qps; i++) {
7089                 rxq = data->rx_queues[i];
7090                 if (rxq && rxq->q_set)
7091                         num++;
7092                 else
7093                         break;
7094         }
7095
7096         return num;
7097 }
7098
7099 /* Configure RSS */
7100 static int
7101 i40e_pf_config_rss(struct i40e_pf *pf)
7102 {
7103         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7104         struct rte_eth_rss_conf rss_conf;
7105         uint32_t i, lut = 0;
7106         uint16_t j, num;
7107
7108         /*
7109          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7110          * It's necessary to calulate the actual PF queues that are configured.
7111          */
7112         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7113                 num = i40e_pf_calc_configured_queues_num(pf);
7114         else
7115                 num = pf->dev_data->nb_rx_queues;
7116
7117         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7118         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7119                         num);
7120
7121         if (num == 0) {
7122                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7123                 return -ENOTSUP;
7124         }
7125
7126         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7127                 if (j == num)
7128                         j = 0;
7129                 lut = (lut << 8) | (j & ((0x1 <<
7130                         hw->func_caps.rss_table_entry_width) - 1));
7131                 if ((i & 3) == 3)
7132                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7133         }
7134
7135         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7136         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7137                 i40e_pf_disable_rss(pf);
7138                 return 0;
7139         }
7140         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7141                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7142                 /* Random default keys */
7143                 static uint32_t rss_key_default[] = {0x6b793944,
7144                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7145                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7146                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7147
7148                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7149                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7150                                                         sizeof(uint32_t);
7151         }
7152
7153         return i40e_hw_rss_hash_set(pf, &rss_conf);
7154 }
7155
7156 static int
7157 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7158                                struct rte_eth_tunnel_filter_conf *filter)
7159 {
7160         if (pf == NULL || filter == NULL) {
7161                 PMD_DRV_LOG(ERR, "Invalid parameter");
7162                 return -EINVAL;
7163         }
7164
7165         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7166                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7167                 return -EINVAL;
7168         }
7169
7170         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7171                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7172                 return -EINVAL;
7173         }
7174
7175         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7176                 (is_zero_ether_addr(&filter->outer_mac))) {
7177                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7178                 return -EINVAL;
7179         }
7180
7181         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7182                 (is_zero_ether_addr(&filter->inner_mac))) {
7183                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7184                 return -EINVAL;
7185         }
7186
7187         return 0;
7188 }
7189
7190 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7191 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7192 static int
7193 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7194 {
7195         uint32_t val, reg;
7196         int ret = -EINVAL;
7197
7198         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7199         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7200
7201         if (len == 3) {
7202                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7203         } else if (len == 4) {
7204                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7205         } else {
7206                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7207                 return ret;
7208         }
7209
7210         if (reg != val) {
7211                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7212                                                    reg, NULL);
7213                 if (ret != 0)
7214                         return ret;
7215         } else {
7216                 ret = 0;
7217         }
7218         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7219                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7220
7221         return ret;
7222 }
7223
7224 static int
7225 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7226 {
7227         int ret = -EINVAL;
7228
7229         if (!hw || !cfg)
7230                 return -EINVAL;
7231
7232         switch (cfg->cfg_type) {
7233         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7234                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7235                 break;
7236         default:
7237                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7238                 break;
7239         }
7240
7241         return ret;
7242 }
7243
7244 static int
7245 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7246                                enum rte_filter_op filter_op,
7247                                void *arg)
7248 {
7249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7250         int ret = I40E_ERR_PARAM;
7251
7252         switch (filter_op) {
7253         case RTE_ETH_FILTER_SET:
7254                 ret = i40e_dev_global_config_set(hw,
7255                         (struct rte_eth_global_cfg *)arg);
7256                 break;
7257         default:
7258                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7259                 break;
7260         }
7261
7262         return ret;
7263 }
7264
7265 static int
7266 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7267                           enum rte_filter_op filter_op,
7268                           void *arg)
7269 {
7270         struct rte_eth_tunnel_filter_conf *filter;
7271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7272         int ret = I40E_SUCCESS;
7273
7274         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7275
7276         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7277                 return I40E_ERR_PARAM;
7278
7279         switch (filter_op) {
7280         case RTE_ETH_FILTER_NOP:
7281                 if (!(pf->flags & I40E_FLAG_VXLAN))
7282                         ret = I40E_NOT_SUPPORTED;
7283                 break;
7284         case RTE_ETH_FILTER_ADD:
7285                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7286                 break;
7287         case RTE_ETH_FILTER_DELETE:
7288                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7289                 break;
7290         default:
7291                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7292                 ret = I40E_ERR_PARAM;
7293                 break;
7294         }
7295
7296         return ret;
7297 }
7298
7299 static int
7300 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7301 {
7302         int ret = 0;
7303         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7304
7305         /* RSS setup */
7306         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7307                 ret = i40e_pf_config_rss(pf);
7308         else
7309                 i40e_pf_disable_rss(pf);
7310
7311         return ret;
7312 }
7313
7314 /* Get the symmetric hash enable configurations per port */
7315 static void
7316 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7317 {
7318         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7319
7320         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7321 }
7322
7323 /* Set the symmetric hash enable configurations per port */
7324 static void
7325 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7326 {
7327         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7328
7329         if (enable > 0) {
7330                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7331                         PMD_DRV_LOG(INFO,
7332                                 "Symmetric hash has already been enabled");
7333                         return;
7334                 }
7335                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7336         } else {
7337                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7338                         PMD_DRV_LOG(INFO,
7339                                 "Symmetric hash has already been disabled");
7340                         return;
7341                 }
7342                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7343         }
7344         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7345         I40E_WRITE_FLUSH(hw);
7346 }
7347
7348 /*
7349  * Get global configurations of hash function type and symmetric hash enable
7350  * per flow type (pctype). Note that global configuration means it affects all
7351  * the ports on the same NIC.
7352  */
7353 static int
7354 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7355                                    struct rte_eth_hash_global_conf *g_cfg)
7356 {
7357         uint32_t reg, mask = I40E_FLOW_TYPES;
7358         uint16_t i;
7359         enum i40e_filter_pctype pctype;
7360
7361         memset(g_cfg, 0, sizeof(*g_cfg));
7362         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7363         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7364                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7365         else
7366                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7367         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7368                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7369
7370         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7371                 if (!(mask & (1UL << i)))
7372                         continue;
7373                 mask &= ~(1UL << i);
7374                 /* Bit set indicats the coresponding flow type is supported */
7375                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7376                 /* if flowtype is invalid, continue */
7377                 if (!I40E_VALID_FLOW(i))
7378                         continue;
7379                 pctype = i40e_flowtype_to_pctype(i);
7380                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7381                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7382                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7383         }
7384
7385         return 0;
7386 }
7387
7388 static int
7389 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7390 {
7391         uint32_t i;
7392         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7393
7394         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7395                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7396                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7397                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7398                                                 g_cfg->hash_func);
7399                 return -EINVAL;
7400         }
7401
7402         /*
7403          * As i40e supports less than 32 flow types, only first 32 bits need to
7404          * be checked.
7405          */
7406         mask0 = g_cfg->valid_bit_mask[0];
7407         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7408                 if (i == 0) {
7409                         /* Check if any unsupported flow type configured */
7410                         if ((mask0 | i40e_mask) ^ i40e_mask)
7411                                 goto mask_err;
7412                 } else {
7413                         if (g_cfg->valid_bit_mask[i])
7414                                 goto mask_err;
7415                 }
7416         }
7417
7418         return 0;
7419
7420 mask_err:
7421         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7422
7423         return -EINVAL;
7424 }
7425
7426 /*
7427  * Set global configurations of hash function type and symmetric hash enable
7428  * per flow type (pctype). Note any modifying global configuration will affect
7429  * all the ports on the same NIC.
7430  */
7431 static int
7432 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7433                                    struct rte_eth_hash_global_conf *g_cfg)
7434 {
7435         int ret;
7436         uint16_t i;
7437         uint32_t reg;
7438         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7439         enum i40e_filter_pctype pctype;
7440
7441         /* Check the input parameters */
7442         ret = i40e_hash_global_config_check(g_cfg);
7443         if (ret < 0)
7444                 return ret;
7445
7446         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7447                 if (!(mask0 & (1UL << i)))
7448                         continue;
7449                 mask0 &= ~(1UL << i);
7450                 /* if flowtype is invalid, continue */
7451                 if (!I40E_VALID_FLOW(i))
7452                         continue;
7453                 pctype = i40e_flowtype_to_pctype(i);
7454                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7455                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7456                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7457         }
7458
7459         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7460         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7461                 /* Toeplitz */
7462                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7463                         PMD_DRV_LOG(DEBUG,
7464                                 "Hash function already set to Toeplitz");
7465                         goto out;
7466                 }
7467                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7468         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7469                 /* Simple XOR */
7470                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7471                         PMD_DRV_LOG(DEBUG,
7472                                 "Hash function already set to Simple XOR");
7473                         goto out;
7474                 }
7475                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7476         } else
7477                 /* Use the default, and keep it as it is */
7478                 goto out;
7479
7480         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7481
7482 out:
7483         I40E_WRITE_FLUSH(hw);
7484
7485         return 0;
7486 }
7487
7488 /**
7489  * Valid input sets for hash and flow director filters per PCTYPE
7490  */
7491 static uint64_t
7492 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7493                 enum rte_filter_type filter)
7494 {
7495         uint64_t valid;
7496
7497         static const uint64_t valid_hash_inset_table[] = {
7498                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7502                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7503                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7504                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7505                         I40E_INSET_FLEX_PAYLOAD,
7506                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7507                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7508                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7509                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7510                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7511                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7512                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7513                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7514                         I40E_INSET_FLEX_PAYLOAD,
7515                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7516                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7517                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7518                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7519                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7520                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7521                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7522                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7523                         I40E_INSET_FLEX_PAYLOAD,
7524                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7525                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7526                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7527                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7528                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7529                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7530                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7531                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7532                         I40E_INSET_FLEX_PAYLOAD,
7533                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7534                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7535                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7536                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7537                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7538                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7539                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7540                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7541                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7542                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7543                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7544                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7545                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7546                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7547                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7548                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7549                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7550                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7551                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7552                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7553                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7554                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7555                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7556                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7557                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7558                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7559                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7560                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7561                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7562                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7563                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7564                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7565                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7566                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7567                         I40E_INSET_FLEX_PAYLOAD,
7568                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7569                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7570                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7572                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7573                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7574                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7575                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7576                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7577                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7578                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7579                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7580                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7581                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7582                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7583                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7584                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7585                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7586                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7588                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7589                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7590                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7591                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7592                         I40E_INSET_FLEX_PAYLOAD,
7593                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7594                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7595                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7597                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7598                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7599                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7600                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7601                         I40E_INSET_FLEX_PAYLOAD,
7602                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7603                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7604                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7605                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7606                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7607                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7608                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7609                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7610                         I40E_INSET_FLEX_PAYLOAD,
7611                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7612                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7613                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7614                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7615                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7616                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7617                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7618                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7619                         I40E_INSET_FLEX_PAYLOAD,
7620                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7621                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7622                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7624                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7625                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7626                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7627                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7628                         I40E_INSET_FLEX_PAYLOAD,
7629                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7630                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7631                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7633                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7634                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7635                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7636                         I40E_INSET_FLEX_PAYLOAD,
7637                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7638                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7639                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7641                         I40E_INSET_FLEX_PAYLOAD,
7642         };
7643
7644         /**
7645          * Flow director supports only fields defined in
7646          * union rte_eth_fdir_flow.
7647          */
7648         static const uint64_t valid_fdir_inset_table[] = {
7649                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7650                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7651                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7652                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7653                 I40E_INSET_IPV4_TTL,
7654                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7655                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7656                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7657                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7658                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7659                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7660                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7661                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7662                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7663                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7664                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7665                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7666                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7667                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7668                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7669                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7670                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7672                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7673                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7674                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7675                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7677                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7678                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7679                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7680                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7681                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7682                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7683                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7684                 I40E_INSET_SCTP_VT,
7685                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7686                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7687                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7688                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7689                 I40E_INSET_IPV4_TTL,
7690                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7691                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7692                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7693                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7694                 I40E_INSET_IPV6_HOP_LIMIT,
7695                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7696                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7697                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7698                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7699                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7700                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7701                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7702                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7703                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7704                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7705                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7706                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7707                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7708                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7709                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7710                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7711                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7712                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7713                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7714                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7715                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7716                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7717                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7718                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7719                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7720                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7721                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7722                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7723                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7724                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7725                 I40E_INSET_SCTP_VT,
7726                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7727                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7728                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7729                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7730                 I40E_INSET_IPV6_HOP_LIMIT,
7731                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7732                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7733                 I40E_INSET_LAST_ETHER_TYPE,
7734         };
7735
7736         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7737                 return 0;
7738         if (filter == RTE_ETH_FILTER_HASH)
7739                 valid = valid_hash_inset_table[pctype];
7740         else
7741                 valid = valid_fdir_inset_table[pctype];
7742
7743         return valid;
7744 }
7745
7746 /**
7747  * Validate if the input set is allowed for a specific PCTYPE
7748  */
7749 static int
7750 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7751                 enum rte_filter_type filter, uint64_t inset)
7752 {
7753         uint64_t valid;
7754
7755         valid = i40e_get_valid_input_set(pctype, filter);
7756         if (inset & (~valid))
7757                 return -EINVAL;
7758
7759         return 0;
7760 }
7761
7762 /* default input set fields combination per pctype */
7763 uint64_t
7764 i40e_get_default_input_set(uint16_t pctype)
7765 {
7766         static const uint64_t default_inset_table[] = {
7767                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7768                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7769                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7770                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7771                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7772                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7773                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7774                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7775                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7776                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7777                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7778                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7779                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7780                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7781                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7782                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7783                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7784                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7785                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7786                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7787                         I40E_INSET_SCTP_VT,
7788                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7789                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7790                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7791                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7792                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7793                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7794                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7795                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7796                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7797                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7798                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7799                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7800                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7801                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7802                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7803                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7804                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7805                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7806                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7807                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7808                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7809                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7810                         I40E_INSET_SCTP_VT,
7811                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7812                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7813                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7814                         I40E_INSET_LAST_ETHER_TYPE,
7815         };
7816
7817         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7818                 return 0;
7819
7820         return default_inset_table[pctype];
7821 }
7822
7823 /**
7824  * Parse the input set from index to logical bit masks
7825  */
7826 static int
7827 i40e_parse_input_set(uint64_t *inset,
7828                      enum i40e_filter_pctype pctype,
7829                      enum rte_eth_input_set_field *field,
7830                      uint16_t size)
7831 {
7832         uint16_t i, j;
7833         int ret = -EINVAL;
7834
7835         static const struct {
7836                 enum rte_eth_input_set_field field;
7837                 uint64_t inset;
7838         } inset_convert_table[] = {
7839                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7840                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7841                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7842                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7843                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7844                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7845                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7846                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7847                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7848                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7849                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7850                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7851                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7852                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7853                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7854                         I40E_INSET_IPV6_NEXT_HDR},
7855                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7856                         I40E_INSET_IPV6_HOP_LIMIT},
7857                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7858                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7859                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7860                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7861                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7862                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7863                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7864                         I40E_INSET_SCTP_VT},
7865                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7866                         I40E_INSET_TUNNEL_DMAC},
7867                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7868                         I40E_INSET_VLAN_TUNNEL},
7869                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7870                         I40E_INSET_TUNNEL_ID},
7871                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7872                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7873                         I40E_INSET_FLEX_PAYLOAD_W1},
7874                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7875                         I40E_INSET_FLEX_PAYLOAD_W2},
7876                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7877                         I40E_INSET_FLEX_PAYLOAD_W3},
7878                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7879                         I40E_INSET_FLEX_PAYLOAD_W4},
7880                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7881                         I40E_INSET_FLEX_PAYLOAD_W5},
7882                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7883                         I40E_INSET_FLEX_PAYLOAD_W6},
7884                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7885                         I40E_INSET_FLEX_PAYLOAD_W7},
7886                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7887                         I40E_INSET_FLEX_PAYLOAD_W8},
7888         };
7889
7890         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7891                 return ret;
7892
7893         /* Only one item allowed for default or all */
7894         if (size == 1) {
7895                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7896                         *inset = i40e_get_default_input_set(pctype);
7897                         return 0;
7898                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7899                         *inset = I40E_INSET_NONE;
7900                         return 0;
7901                 }
7902         }
7903
7904         for (i = 0, *inset = 0; i < size; i++) {
7905                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7906                         if (field[i] == inset_convert_table[j].field) {
7907                                 *inset |= inset_convert_table[j].inset;
7908                                 break;
7909                         }
7910                 }
7911
7912                 /* It contains unsupported input set, return immediately */
7913                 if (j == RTE_DIM(inset_convert_table))
7914                         return ret;
7915         }
7916
7917         return 0;
7918 }
7919
7920 /**
7921  * Translate the input set from bit masks to register aware bit masks
7922  * and vice versa
7923  */
7924 static uint64_t
7925 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7926 {
7927         uint64_t val = 0;
7928         uint16_t i;
7929
7930         struct inset_map {
7931                 uint64_t inset;
7932                 uint64_t inset_reg;
7933         };
7934
7935         static const struct inset_map inset_map_common[] = {
7936                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7937                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7938                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7939                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7940                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7941                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7942                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7943                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7944                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7945                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7946                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7947                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7948                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7949                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7950                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7951                 {I40E_INSET_TUNNEL_DMAC,
7952                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7953                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7954                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7955                 {I40E_INSET_TUNNEL_SRC_PORT,
7956                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7957                 {I40E_INSET_TUNNEL_DST_PORT,
7958                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7959                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7960                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7961                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7962                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7963                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7964                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7965                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7966                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7967                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7968         };
7969
7970     /* some different registers map in x722*/
7971         static const struct inset_map inset_map_diff_x722[] = {
7972                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7973                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7974                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7975                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7976         };
7977
7978         static const struct inset_map inset_map_diff_not_x722[] = {
7979                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7980                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7981                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7982                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7983         };
7984
7985         if (input == 0)
7986                 return val;
7987
7988         /* Translate input set to register aware inset */
7989         if (type == I40E_MAC_X722) {
7990                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7991                         if (input & inset_map_diff_x722[i].inset)
7992                                 val |= inset_map_diff_x722[i].inset_reg;
7993                 }
7994         } else {
7995                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7996                         if (input & inset_map_diff_not_x722[i].inset)
7997                                 val |= inset_map_diff_not_x722[i].inset_reg;
7998                 }
7999         }
8000
8001         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8002                 if (input & inset_map_common[i].inset)
8003                         val |= inset_map_common[i].inset_reg;
8004         }
8005
8006         return val;
8007 }
8008
8009 static int
8010 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8011 {
8012         uint8_t i, idx = 0;
8013         uint64_t inset_need_mask = inset;
8014
8015         static const struct {
8016                 uint64_t inset;
8017                 uint32_t mask;
8018         } inset_mask_map[] = {
8019                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8020                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8021                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8022                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8023                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8024                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8025                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8026                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8027         };
8028
8029         if (!inset || !mask || !nb_elem)
8030                 return 0;
8031
8032         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8033                 /* Clear the inset bit, if no MASK is required,
8034                  * for example proto + ttl
8035                  */
8036                 if ((inset & inset_mask_map[i].inset) ==
8037                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8038                         inset_need_mask &= ~inset_mask_map[i].inset;
8039                 if (!inset_need_mask)
8040                         return 0;
8041         }
8042         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8043                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8044                     inset_mask_map[i].inset) {
8045                         if (idx >= nb_elem) {
8046                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8047                                 return -EINVAL;
8048                         }
8049                         mask[idx] = inset_mask_map[i].mask;
8050                         idx++;
8051                 }
8052         }
8053
8054         return idx;
8055 }
8056
8057 static void
8058 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8059 {
8060         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8061
8062         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8063         if (reg != val)
8064                 i40e_write_rx_ctl(hw, addr, val);
8065         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8066                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8067 }
8068
8069 static void
8070 i40e_filter_input_set_init(struct i40e_pf *pf)
8071 {
8072         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8073         enum i40e_filter_pctype pctype;
8074         uint64_t input_set, inset_reg;
8075         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8076         int num, i;
8077
8078         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8079              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8080                 if (hw->mac.type == I40E_MAC_X722) {
8081                         if (!I40E_VALID_PCTYPE_X722(pctype))
8082                                 continue;
8083                 } else {
8084                         if (!I40E_VALID_PCTYPE(pctype))
8085                                 continue;
8086                 }
8087
8088                 input_set = i40e_get_default_input_set(pctype);
8089
8090                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8091                                                    I40E_INSET_MASK_NUM_REG);
8092                 if (num < 0)
8093                         return;
8094                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8095                                         input_set);
8096
8097                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8098                                       (uint32_t)(inset_reg & UINT32_MAX));
8099                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8100                                      (uint32_t)((inset_reg >>
8101                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8102                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8103                                       (uint32_t)(inset_reg & UINT32_MAX));
8104                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8105                                      (uint32_t)((inset_reg >>
8106                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8107
8108                 for (i = 0; i < num; i++) {
8109                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8110                                              mask_reg[i]);
8111                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8112                                              mask_reg[i]);
8113                 }
8114                 /*clear unused mask registers of the pctype */
8115                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8116                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8117                                              0);
8118                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8119                                              0);
8120                 }
8121                 I40E_WRITE_FLUSH(hw);
8122
8123                 /* store the default input set */
8124                 pf->hash_input_set[pctype] = input_set;
8125                 pf->fdir.input_set[pctype] = input_set;
8126         }
8127 }
8128
8129 int
8130 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8131                          struct rte_eth_input_set_conf *conf)
8132 {
8133         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8134         enum i40e_filter_pctype pctype;
8135         uint64_t input_set, inset_reg = 0;
8136         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8137         int ret, i, num;
8138
8139         if (!conf) {
8140                 PMD_DRV_LOG(ERR, "Invalid pointer");
8141                 return -EFAULT;
8142         }
8143         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8144             conf->op != RTE_ETH_INPUT_SET_ADD) {
8145                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8146                 return -EINVAL;
8147         }
8148
8149         if (!I40E_VALID_FLOW(conf->flow_type)) {
8150                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8151                 return -EINVAL;
8152         }
8153
8154         if (hw->mac.type == I40E_MAC_X722) {
8155                 /* get translated pctype value in fd pctype register */
8156                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8157                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8158                         conf->flow_type)));
8159         } else
8160                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8161
8162         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8163                                    conf->inset_size);
8164         if (ret) {
8165                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8166                 return -EINVAL;
8167         }
8168         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8169                                     input_set) != 0) {
8170                 PMD_DRV_LOG(ERR, "Invalid input set");
8171                 return -EINVAL;
8172         }
8173         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8174                 /* get inset value in register */
8175                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8176                 inset_reg <<= I40E_32_BIT_WIDTH;
8177                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8178                 input_set |= pf->hash_input_set[pctype];
8179         }
8180         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8181                                            I40E_INSET_MASK_NUM_REG);
8182         if (num < 0)
8183                 return -EINVAL;
8184
8185         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8186
8187         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8188                               (uint32_t)(inset_reg & UINT32_MAX));
8189         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8190                              (uint32_t)((inset_reg >>
8191                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8192
8193         for (i = 0; i < num; i++)
8194                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8195                                      mask_reg[i]);
8196         /*clear unused mask registers of the pctype */
8197         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8198                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8199                                      0);
8200         I40E_WRITE_FLUSH(hw);
8201
8202         pf->hash_input_set[pctype] = input_set;
8203         return 0;
8204 }
8205
8206 int
8207 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8208                          struct rte_eth_input_set_conf *conf)
8209 {
8210         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8211         enum i40e_filter_pctype pctype;
8212         uint64_t input_set, inset_reg = 0;
8213         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8214         int ret, i, num;
8215
8216         if (!hw || !conf) {
8217                 PMD_DRV_LOG(ERR, "Invalid pointer");
8218                 return -EFAULT;
8219         }
8220         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8221             conf->op != RTE_ETH_INPUT_SET_ADD) {
8222                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8223                 return -EINVAL;
8224         }
8225
8226         if (!I40E_VALID_FLOW(conf->flow_type)) {
8227                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8228                 return -EINVAL;
8229         }
8230
8231         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8232
8233         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8234                                    conf->inset_size);
8235         if (ret) {
8236                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8237                 return -EINVAL;
8238         }
8239         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8240                                     input_set) != 0) {
8241                 PMD_DRV_LOG(ERR, "Invalid input set");
8242                 return -EINVAL;
8243         }
8244
8245         /* get inset value in register */
8246         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8247         inset_reg <<= I40E_32_BIT_WIDTH;
8248         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8249
8250         /* Can not change the inset reg for flex payload for fdir,
8251          * it is done by writing I40E_PRTQF_FD_FLXINSET
8252          * in i40e_set_flex_mask_on_pctype.
8253          */
8254         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8255                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8256         else
8257                 input_set |= pf->fdir.input_set[pctype];
8258         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8259                                            I40E_INSET_MASK_NUM_REG);
8260         if (num < 0)
8261                 return -EINVAL;
8262
8263         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8264
8265         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8266                               (uint32_t)(inset_reg & UINT32_MAX));
8267         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8268                              (uint32_t)((inset_reg >>
8269                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8270
8271         for (i = 0; i < num; i++)
8272                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8273                                      mask_reg[i]);
8274         /*clear unused mask registers of the pctype */
8275         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8276                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8277                                      0);
8278         I40E_WRITE_FLUSH(hw);
8279
8280         pf->fdir.input_set[pctype] = input_set;
8281         return 0;
8282 }
8283
8284 static int
8285 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8286 {
8287         int ret = 0;
8288
8289         if (!hw || !info) {
8290                 PMD_DRV_LOG(ERR, "Invalid pointer");
8291                 return -EFAULT;
8292         }
8293
8294         switch (info->info_type) {
8295         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8296                 i40e_get_symmetric_hash_enable_per_port(hw,
8297                                         &(info->info.enable));
8298                 break;
8299         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8300                 ret = i40e_get_hash_filter_global_config(hw,
8301                                 &(info->info.global_conf));
8302                 break;
8303         default:
8304                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8305                                                         info->info_type);
8306                 ret = -EINVAL;
8307                 break;
8308         }
8309
8310         return ret;
8311 }
8312
8313 static int
8314 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8315 {
8316         int ret = 0;
8317
8318         if (!hw || !info) {
8319                 PMD_DRV_LOG(ERR, "Invalid pointer");
8320                 return -EFAULT;
8321         }
8322
8323         switch (info->info_type) {
8324         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8325                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8326                 break;
8327         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8328                 ret = i40e_set_hash_filter_global_config(hw,
8329                                 &(info->info.global_conf));
8330                 break;
8331         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8332                 ret = i40e_hash_filter_inset_select(hw,
8333                                                &(info->info.input_set_conf));
8334                 break;
8335
8336         default:
8337                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8338                                                         info->info_type);
8339                 ret = -EINVAL;
8340                 break;
8341         }
8342
8343         return ret;
8344 }
8345
8346 /* Operations for hash function */
8347 static int
8348 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8349                       enum rte_filter_op filter_op,
8350                       void *arg)
8351 {
8352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353         int ret = 0;
8354
8355         switch (filter_op) {
8356         case RTE_ETH_FILTER_NOP:
8357                 break;
8358         case RTE_ETH_FILTER_GET:
8359                 ret = i40e_hash_filter_get(hw,
8360                         (struct rte_eth_hash_filter_info *)arg);
8361                 break;
8362         case RTE_ETH_FILTER_SET:
8363                 ret = i40e_hash_filter_set(hw,
8364                         (struct rte_eth_hash_filter_info *)arg);
8365                 break;
8366         default:
8367                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8368                                                                 filter_op);
8369                 ret = -ENOTSUP;
8370                 break;
8371         }
8372
8373         return ret;
8374 }
8375
8376 /* Convert ethertype filter structure */
8377 static int
8378 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8379                               struct i40e_ethertype_filter *filter)
8380 {
8381         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8382         filter->input.ether_type = input->ether_type;
8383         filter->flags = input->flags;
8384         filter->queue = input->queue;
8385
8386         return 0;
8387 }
8388
8389 /* Check if there exists the ehtertype filter */
8390 struct i40e_ethertype_filter *
8391 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8392                                 const struct i40e_ethertype_filter_input *input)
8393 {
8394         int ret;
8395
8396         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8397         if (ret < 0)
8398                 return NULL;
8399
8400         return ethertype_rule->hash_map[ret];
8401 }
8402
8403 /* Add ethertype filter in SW list */
8404 static int
8405 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8406                                 struct i40e_ethertype_filter *filter)
8407 {
8408         struct i40e_ethertype_rule *rule = &pf->ethertype;
8409         int ret;
8410
8411         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8412         if (ret < 0) {
8413                 PMD_DRV_LOG(ERR,
8414                             "Failed to insert ethertype filter"
8415                             " to hash table %d!",
8416                             ret);
8417                 return ret;
8418         }
8419         rule->hash_map[ret] = filter;
8420
8421         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8422
8423         return 0;
8424 }
8425
8426 /* Delete ethertype filter in SW list */
8427 int
8428 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8429                              struct i40e_ethertype_filter_input *input)
8430 {
8431         struct i40e_ethertype_rule *rule = &pf->ethertype;
8432         struct i40e_ethertype_filter *filter;
8433         int ret;
8434
8435         ret = rte_hash_del_key(rule->hash_table, input);
8436         if (ret < 0) {
8437                 PMD_DRV_LOG(ERR,
8438                             "Failed to delete ethertype filter"
8439                             " to hash table %d!",
8440                             ret);
8441                 return ret;
8442         }
8443         filter = rule->hash_map[ret];
8444         rule->hash_map[ret] = NULL;
8445
8446         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8447         rte_free(filter);
8448
8449         return 0;
8450 }
8451
8452 /*
8453  * Configure ethertype filter, which can director packet by filtering
8454  * with mac address and ether_type or only ether_type
8455  */
8456 int
8457 i40e_ethertype_filter_set(struct i40e_pf *pf,
8458                         struct rte_eth_ethertype_filter *filter,
8459                         bool add)
8460 {
8461         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8462         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8463         struct i40e_ethertype_filter *ethertype_filter, *node;
8464         struct i40e_ethertype_filter check_filter;
8465         struct i40e_control_filter_stats stats;
8466         uint16_t flags = 0;
8467         int ret;
8468
8469         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8470                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8471                 return -EINVAL;
8472         }
8473         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8474                 filter->ether_type == ETHER_TYPE_IPv6) {
8475                 PMD_DRV_LOG(ERR,
8476                         "unsupported ether_type(0x%04x) in control packet filter.",
8477                         filter->ether_type);
8478                 return -EINVAL;
8479         }
8480         if (filter->ether_type == ETHER_TYPE_VLAN)
8481                 PMD_DRV_LOG(WARNING,
8482                         "filter vlan ether_type in first tag is not supported.");
8483
8484         /* Check if there is the filter in SW list */
8485         memset(&check_filter, 0, sizeof(check_filter));
8486         i40e_ethertype_filter_convert(filter, &check_filter);
8487         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8488                                                &check_filter.input);
8489         if (add && node) {
8490                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8491                 return -EINVAL;
8492         }
8493
8494         if (!add && !node) {
8495                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8496                 return -EINVAL;
8497         }
8498
8499         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8500                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8501         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8502                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8503         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8504
8505         memset(&stats, 0, sizeof(stats));
8506         ret = i40e_aq_add_rem_control_packet_filter(hw,
8507                         filter->mac_addr.addr_bytes,
8508                         filter->ether_type, flags,
8509                         pf->main_vsi->seid,
8510                         filter->queue, add, &stats, NULL);
8511
8512         PMD_DRV_LOG(INFO,
8513                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8514                 ret, stats.mac_etype_used, stats.etype_used,
8515                 stats.mac_etype_free, stats.etype_free);
8516         if (ret < 0)
8517                 return -ENOSYS;
8518
8519         /* Add or delete a filter in SW list */
8520         if (add) {
8521                 ethertype_filter = rte_zmalloc("ethertype_filter",
8522                                        sizeof(*ethertype_filter), 0);
8523                 rte_memcpy(ethertype_filter, &check_filter,
8524                            sizeof(check_filter));
8525                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8526         } else {
8527                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8528         }
8529
8530         return ret;
8531 }
8532
8533 /*
8534  * Handle operations for ethertype filter.
8535  */
8536 static int
8537 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8538                                 enum rte_filter_op filter_op,
8539                                 void *arg)
8540 {
8541         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8542         int ret = 0;
8543
8544         if (filter_op == RTE_ETH_FILTER_NOP)
8545                 return ret;
8546
8547         if (arg == NULL) {
8548                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8549                             filter_op);
8550                 return -EINVAL;
8551         }
8552
8553         switch (filter_op) {
8554         case RTE_ETH_FILTER_ADD:
8555                 ret = i40e_ethertype_filter_set(pf,
8556                         (struct rte_eth_ethertype_filter *)arg,
8557                         TRUE);
8558                 break;
8559         case RTE_ETH_FILTER_DELETE:
8560                 ret = i40e_ethertype_filter_set(pf,
8561                         (struct rte_eth_ethertype_filter *)arg,
8562                         FALSE);
8563                 break;
8564         default:
8565                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8566                 ret = -ENOSYS;
8567                 break;
8568         }
8569         return ret;
8570 }
8571
8572 static int
8573 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8574                      enum rte_filter_type filter_type,
8575                      enum rte_filter_op filter_op,
8576                      void *arg)
8577 {
8578         int ret = 0;
8579
8580         if (dev == NULL)
8581                 return -EINVAL;
8582
8583         switch (filter_type) {
8584         case RTE_ETH_FILTER_NONE:
8585                 /* For global configuration */
8586                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8587                 break;
8588         case RTE_ETH_FILTER_HASH:
8589                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8590                 break;
8591         case RTE_ETH_FILTER_MACVLAN:
8592                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8593                 break;
8594         case RTE_ETH_FILTER_ETHERTYPE:
8595                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8596                 break;
8597         case RTE_ETH_FILTER_TUNNEL:
8598                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8599                 break;
8600         case RTE_ETH_FILTER_FDIR:
8601                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8602                 break;
8603         case RTE_ETH_FILTER_GENERIC:
8604                 if (filter_op != RTE_ETH_FILTER_GET)
8605                         return -EINVAL;
8606                 *(const void **)arg = &i40e_flow_ops;
8607                 break;
8608         default:
8609                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8610                                                         filter_type);
8611                 ret = -EINVAL;
8612                 break;
8613         }
8614
8615         return ret;
8616 }
8617
8618 /*
8619  * Check and enable Extended Tag.
8620  * Enabling Extended Tag is important for 40G performance.
8621  */
8622 static void
8623 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8624 {
8625         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8626         uint32_t buf = 0;
8627         int ret;
8628
8629         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8630                                       PCI_DEV_CAP_REG);
8631         if (ret < 0) {
8632                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8633                             PCI_DEV_CAP_REG);
8634                 return;
8635         }
8636         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8637                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8638                 return;
8639         }
8640
8641         buf = 0;
8642         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8643                                       PCI_DEV_CTRL_REG);
8644         if (ret < 0) {
8645                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8646                             PCI_DEV_CTRL_REG);
8647                 return;
8648         }
8649         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8650                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8651                 return;
8652         }
8653         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8654         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8655                                        PCI_DEV_CTRL_REG);
8656         if (ret < 0) {
8657                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8658                             PCI_DEV_CTRL_REG);
8659                 return;
8660         }
8661 }
8662
8663 /*
8664  * As some registers wouldn't be reset unless a global hardware reset,
8665  * hardware initialization is needed to put those registers into an
8666  * expected initial state.
8667  */
8668 static void
8669 i40e_hw_init(struct rte_eth_dev *dev)
8670 {
8671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8672
8673         i40e_enable_extended_tag(dev);
8674
8675         /* clear the PF Queue Filter control register */
8676         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8677
8678         /* Disable symmetric hash per port */
8679         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8680 }
8681
8682 enum i40e_filter_pctype
8683 i40e_flowtype_to_pctype(uint16_t flow_type)
8684 {
8685         static const enum i40e_filter_pctype pctype_table[] = {
8686                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8687                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8688                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8689                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8690                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8691                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8692                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8693                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8694                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8695                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8696                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8697                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8698                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8699                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8700                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8701                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8702                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8703                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8704                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8705         };
8706
8707         return pctype_table[flow_type];
8708 }
8709
8710 uint16_t
8711 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8712 {
8713         static const uint16_t flowtype_table[] = {
8714                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8715                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8716                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8717                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8718                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8719                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8720                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8721                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8722                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8723                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8724                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8725                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8726                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8727                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8728                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8729                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8730                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8731                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8732                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8733                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8734                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8735                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8736                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8737                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8738                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8739                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8740                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8741                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8742                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8743                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8744                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8745         };
8746
8747         return flowtype_table[pctype];
8748 }
8749
8750 /*
8751  * On X710, performance number is far from the expectation on recent firmware
8752  * versions; on XL710, performance number is also far from the expectation on
8753  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8754  * mode is enabled and port MAC address is equal to the packet destination MAC
8755  * address. The fix for this issue may not be integrated in the following
8756  * firmware version. So the workaround in software driver is needed. It needs
8757  * to modify the initial values of 3 internal only registers for both X710 and
8758  * XL710. Note that the values for X710 or XL710 could be different, and the
8759  * workaround can be removed when it is fixed in firmware in the future.
8760  */
8761
8762 /* For both X710 and XL710 */
8763 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8764 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8765
8766 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8767 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8768
8769 /* For X722 */
8770 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8771 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8772
8773 /* For X710 */
8774 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8775 /* For XL710 */
8776 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8777 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8778
8779 static int
8780 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8781 {
8782         enum i40e_status_code status;
8783         struct i40e_aq_get_phy_abilities_resp phy_ab;
8784         int ret = -ENOTSUP;
8785
8786         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8787                                               NULL);
8788
8789         if (status)
8790                 return ret;
8791
8792         return 0;
8793 }
8794
8795 static void
8796 i40e_configure_registers(struct i40e_hw *hw)
8797 {
8798         static struct {
8799                 uint32_t addr;
8800                 uint64_t val;
8801         } reg_table[] = {
8802                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8803                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8804                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8805         };
8806         uint64_t reg;
8807         uint32_t i;
8808         int ret;
8809
8810         for (i = 0; i < RTE_DIM(reg_table); i++) {
8811                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8812                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8813                                 reg_table[i].val =
8814                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8815                         else /* For X710/XL710/XXV710 */
8816                                 reg_table[i].val =
8817                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8818                 }
8819
8820                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8821                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8822                                 reg_table[i].val =
8823                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8824                         else /* For X710/XL710/XXV710 */
8825                                 reg_table[i].val =
8826                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8827                 }
8828
8829                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8830                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8831                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8832                                 reg_table[i].val =
8833                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8834                         else /* For X710 */
8835                                 reg_table[i].val =
8836                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8837                 }
8838
8839                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8840                                                         &reg, NULL);
8841                 if (ret < 0) {
8842                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8843                                                         reg_table[i].addr);
8844                         break;
8845                 }
8846                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8847                                                 reg_table[i].addr, reg);
8848                 if (reg == reg_table[i].val)
8849                         continue;
8850
8851                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8852                                                 reg_table[i].val, NULL);
8853                 if (ret < 0) {
8854                         PMD_DRV_LOG(ERR,
8855                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8856                                 reg_table[i].val, reg_table[i].addr);
8857                         break;
8858                 }
8859                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8860                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8861         }
8862 }
8863
8864 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8865 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8866 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8867 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8868 static int
8869 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8870 {
8871         uint32_t reg;
8872         int ret;
8873
8874         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8875                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8876                 return -EINVAL;
8877         }
8878
8879         /* Configure for double VLAN RX stripping */
8880         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8881         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8882                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8883                 ret = i40e_aq_debug_write_register(hw,
8884                                                    I40E_VSI_TSR(vsi->vsi_id),
8885                                                    reg, NULL);
8886                 if (ret < 0) {
8887                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8888                                     vsi->vsi_id);
8889                         return I40E_ERR_CONFIG;
8890                 }
8891         }
8892
8893         /* Configure for double VLAN TX insertion */
8894         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8895         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8896                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8897                 ret = i40e_aq_debug_write_register(hw,
8898                                                    I40E_VSI_L2TAGSTXVALID(
8899                                                    vsi->vsi_id), reg, NULL);
8900                 if (ret < 0) {
8901                         PMD_DRV_LOG(ERR,
8902                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8903                                 vsi->vsi_id);
8904                         return I40E_ERR_CONFIG;
8905                 }
8906         }
8907
8908         return 0;
8909 }
8910
8911 /**
8912  * i40e_aq_add_mirror_rule
8913  * @hw: pointer to the hardware structure
8914  * @seid: VEB seid to add mirror rule to
8915  * @dst_id: destination vsi seid
8916  * @entries: Buffer which contains the entities to be mirrored
8917  * @count: number of entities contained in the buffer
8918  * @rule_id:the rule_id of the rule to be added
8919  *
8920  * Add a mirror rule for a given veb.
8921  *
8922  **/
8923 static enum i40e_status_code
8924 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8925                         uint16_t seid, uint16_t dst_id,
8926                         uint16_t rule_type, uint16_t *entries,
8927                         uint16_t count, uint16_t *rule_id)
8928 {
8929         struct i40e_aq_desc desc;
8930         struct i40e_aqc_add_delete_mirror_rule cmd;
8931         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8932                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8933                 &desc.params.raw;
8934         uint16_t buff_len;
8935         enum i40e_status_code status;
8936
8937         i40e_fill_default_direct_cmd_desc(&desc,
8938                                           i40e_aqc_opc_add_mirror_rule);
8939         memset(&cmd, 0, sizeof(cmd));
8940
8941         buff_len = sizeof(uint16_t) * count;
8942         desc.datalen = rte_cpu_to_le_16(buff_len);
8943         if (buff_len > 0)
8944                 desc.flags |= rte_cpu_to_le_16(
8945                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8946         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8947                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8948         cmd.num_entries = rte_cpu_to_le_16(count);
8949         cmd.seid = rte_cpu_to_le_16(seid);
8950         cmd.destination = rte_cpu_to_le_16(dst_id);
8951
8952         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8953         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8954         PMD_DRV_LOG(INFO,
8955                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8956                 hw->aq.asq_last_status, resp->rule_id,
8957                 resp->mirror_rules_used, resp->mirror_rules_free);
8958         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8959
8960         return status;
8961 }
8962
8963 /**
8964  * i40e_aq_del_mirror_rule
8965  * @hw: pointer to the hardware structure
8966  * @seid: VEB seid to add mirror rule to
8967  * @entries: Buffer which contains the entities to be mirrored
8968  * @count: number of entities contained in the buffer
8969  * @rule_id:the rule_id of the rule to be delete
8970  *
8971  * Delete a mirror rule for a given veb.
8972  *
8973  **/
8974 static enum i40e_status_code
8975 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8976                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8977                 uint16_t count, uint16_t rule_id)
8978 {
8979         struct i40e_aq_desc desc;
8980         struct i40e_aqc_add_delete_mirror_rule cmd;
8981         uint16_t buff_len = 0;
8982         enum i40e_status_code status;
8983         void *buff = NULL;
8984
8985         i40e_fill_default_direct_cmd_desc(&desc,
8986                                           i40e_aqc_opc_delete_mirror_rule);
8987         memset(&cmd, 0, sizeof(cmd));
8988         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8989                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8990                                                           I40E_AQ_FLAG_RD));
8991                 cmd.num_entries = count;
8992                 buff_len = sizeof(uint16_t) * count;
8993                 desc.datalen = rte_cpu_to_le_16(buff_len);
8994                 buff = (void *)entries;
8995         } else
8996                 /* rule id is filled in destination field for deleting mirror rule */
8997                 cmd.destination = rte_cpu_to_le_16(rule_id);
8998
8999         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9000                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9001         cmd.seid = rte_cpu_to_le_16(seid);
9002
9003         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9004         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9005
9006         return status;
9007 }
9008
9009 /**
9010  * i40e_mirror_rule_set
9011  * @dev: pointer to the hardware structure
9012  * @mirror_conf: mirror rule info
9013  * @sw_id: mirror rule's sw_id
9014  * @on: enable/disable
9015  *
9016  * set a mirror rule.
9017  *
9018  **/
9019 static int
9020 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9021                         struct rte_eth_mirror_conf *mirror_conf,
9022                         uint8_t sw_id, uint8_t on)
9023 {
9024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9026         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9027         struct i40e_mirror_rule *parent = NULL;
9028         uint16_t seid, dst_seid, rule_id;
9029         uint16_t i, j = 0;
9030         int ret;
9031
9032         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9033
9034         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9035                 PMD_DRV_LOG(ERR,
9036                         "mirror rule can not be configured without veb or vfs.");
9037                 return -ENOSYS;
9038         }
9039         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9040                 PMD_DRV_LOG(ERR, "mirror table is full.");
9041                 return -ENOSPC;
9042         }
9043         if (mirror_conf->dst_pool > pf->vf_num) {
9044                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9045                                  mirror_conf->dst_pool);
9046                 return -EINVAL;
9047         }
9048
9049         seid = pf->main_vsi->veb->seid;
9050
9051         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9052                 if (sw_id <= it->index) {
9053                         mirr_rule = it;
9054                         break;
9055                 }
9056                 parent = it;
9057         }
9058         if (mirr_rule && sw_id == mirr_rule->index) {
9059                 if (on) {
9060                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9061                         return -EEXIST;
9062                 } else {
9063                         ret = i40e_aq_del_mirror_rule(hw, seid,
9064                                         mirr_rule->rule_type,
9065                                         mirr_rule->entries,
9066                                         mirr_rule->num_entries, mirr_rule->id);
9067                         if (ret < 0) {
9068                                 PMD_DRV_LOG(ERR,
9069                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9070                                         ret, hw->aq.asq_last_status);
9071                                 return -ENOSYS;
9072                         }
9073                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9074                         rte_free(mirr_rule);
9075                         pf->nb_mirror_rule--;
9076                         return 0;
9077                 }
9078         } else if (!on) {
9079                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9080                 return -ENOENT;
9081         }
9082
9083         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9084                                 sizeof(struct i40e_mirror_rule) , 0);
9085         if (!mirr_rule) {
9086                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9087                 return I40E_ERR_NO_MEMORY;
9088         }
9089         switch (mirror_conf->rule_type) {
9090         case ETH_MIRROR_VLAN:
9091                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9092                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9093                                 mirr_rule->entries[j] =
9094                                         mirror_conf->vlan.vlan_id[i];
9095                                 j++;
9096                         }
9097                 }
9098                 if (j == 0) {
9099                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9100                         rte_free(mirr_rule);
9101                         return -EINVAL;
9102                 }
9103                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9104                 break;
9105         case ETH_MIRROR_VIRTUAL_POOL_UP:
9106         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9107                 /* check if the specified pool bit is out of range */
9108                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9109                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9110                         rte_free(mirr_rule);
9111                         return -EINVAL;
9112                 }
9113                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9114                         if (mirror_conf->pool_mask & (1ULL << i)) {
9115                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9116                                 j++;
9117                         }
9118                 }
9119                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9120                         /* add pf vsi to entries */
9121                         mirr_rule->entries[j] = pf->main_vsi_seid;
9122                         j++;
9123                 }
9124                 if (j == 0) {
9125                         PMD_DRV_LOG(ERR, "pool is not specified.");
9126                         rte_free(mirr_rule);
9127                         return -EINVAL;
9128                 }
9129                 /* egress and ingress in aq commands means from switch but not port */
9130                 mirr_rule->rule_type =
9131                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9132                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9133                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9134                 break;
9135         case ETH_MIRROR_UPLINK_PORT:
9136                 /* egress and ingress in aq commands means from switch but not port*/
9137                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9138                 break;
9139         case ETH_MIRROR_DOWNLINK_PORT:
9140                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9141                 break;
9142         default:
9143                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9144                         mirror_conf->rule_type);
9145                 rte_free(mirr_rule);
9146                 return -EINVAL;
9147         }
9148
9149         /* If the dst_pool is equal to vf_num, consider it as PF */
9150         if (mirror_conf->dst_pool == pf->vf_num)
9151                 dst_seid = pf->main_vsi_seid;
9152         else
9153                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9154
9155         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9156                                       mirr_rule->rule_type, mirr_rule->entries,
9157                                       j, &rule_id);
9158         if (ret < 0) {
9159                 PMD_DRV_LOG(ERR,
9160                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9161                         ret, hw->aq.asq_last_status);
9162                 rte_free(mirr_rule);
9163                 return -ENOSYS;
9164         }
9165
9166         mirr_rule->index = sw_id;
9167         mirr_rule->num_entries = j;
9168         mirr_rule->id = rule_id;
9169         mirr_rule->dst_vsi_seid = dst_seid;
9170
9171         if (parent)
9172                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9173         else
9174                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9175
9176         pf->nb_mirror_rule++;
9177         return 0;
9178 }
9179
9180 /**
9181  * i40e_mirror_rule_reset
9182  * @dev: pointer to the device
9183  * @sw_id: mirror rule's sw_id
9184  *
9185  * reset a mirror rule.
9186  *
9187  **/
9188 static int
9189 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9190 {
9191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9193         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9194         uint16_t seid;
9195         int ret;
9196
9197         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9198
9199         seid = pf->main_vsi->veb->seid;
9200
9201         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9202                 if (sw_id == it->index) {
9203                         mirr_rule = it;
9204                         break;
9205                 }
9206         }
9207         if (mirr_rule) {
9208                 ret = i40e_aq_del_mirror_rule(hw, seid,
9209                                 mirr_rule->rule_type,
9210                                 mirr_rule->entries,
9211                                 mirr_rule->num_entries, mirr_rule->id);
9212                 if (ret < 0) {
9213                         PMD_DRV_LOG(ERR,
9214                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9215                                 ret, hw->aq.asq_last_status);
9216                         return -ENOSYS;
9217                 }
9218                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9219                 rte_free(mirr_rule);
9220                 pf->nb_mirror_rule--;
9221         } else {
9222                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9223                 return -ENOENT;
9224         }
9225         return 0;
9226 }
9227
9228 static uint64_t
9229 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9230 {
9231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9232         uint64_t systim_cycles;
9233
9234         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9235         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9236                         << 32;
9237
9238         return systim_cycles;
9239 }
9240
9241 static uint64_t
9242 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9243 {
9244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9245         uint64_t rx_tstamp;
9246
9247         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9248         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9249                         << 32;
9250
9251         return rx_tstamp;
9252 }
9253
9254 static uint64_t
9255 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9256 {
9257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9258         uint64_t tx_tstamp;
9259
9260         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9261         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9262                         << 32;
9263
9264         return tx_tstamp;
9265 }
9266
9267 static void
9268 i40e_start_timecounters(struct rte_eth_dev *dev)
9269 {
9270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9271         struct i40e_adapter *adapter =
9272                         (struct i40e_adapter *)dev->data->dev_private;
9273         struct rte_eth_link link;
9274         uint32_t tsync_inc_l;
9275         uint32_t tsync_inc_h;
9276
9277         /* Get current link speed. */
9278         memset(&link, 0, sizeof(link));
9279         i40e_dev_link_update(dev, 1);
9280         rte_i40e_dev_atomic_read_link_status(dev, &link);
9281
9282         switch (link.link_speed) {
9283         case ETH_SPEED_NUM_40G:
9284                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9285                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9286                 break;
9287         case ETH_SPEED_NUM_10G:
9288                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9289                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9290                 break;
9291         case ETH_SPEED_NUM_1G:
9292                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9293                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9294                 break;
9295         default:
9296                 tsync_inc_l = 0x0;
9297                 tsync_inc_h = 0x0;
9298         }
9299
9300         /* Set the timesync increment value. */
9301         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9302         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9303
9304         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9305         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9306         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9307
9308         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9309         adapter->systime_tc.cc_shift = 0;
9310         adapter->systime_tc.nsec_mask = 0;
9311
9312         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9313         adapter->rx_tstamp_tc.cc_shift = 0;
9314         adapter->rx_tstamp_tc.nsec_mask = 0;
9315
9316         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9317         adapter->tx_tstamp_tc.cc_shift = 0;
9318         adapter->tx_tstamp_tc.nsec_mask = 0;
9319 }
9320
9321 static int
9322 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9323 {
9324         struct i40e_adapter *adapter =
9325                         (struct i40e_adapter *)dev->data->dev_private;
9326
9327         adapter->systime_tc.nsec += delta;
9328         adapter->rx_tstamp_tc.nsec += delta;
9329         adapter->tx_tstamp_tc.nsec += delta;
9330
9331         return 0;
9332 }
9333
9334 static int
9335 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9336 {
9337         uint64_t ns;
9338         struct i40e_adapter *adapter =
9339                         (struct i40e_adapter *)dev->data->dev_private;
9340
9341         ns = rte_timespec_to_ns(ts);
9342
9343         /* Set the timecounters to a new value. */
9344         adapter->systime_tc.nsec = ns;
9345         adapter->rx_tstamp_tc.nsec = ns;
9346         adapter->tx_tstamp_tc.nsec = ns;
9347
9348         return 0;
9349 }
9350
9351 static int
9352 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9353 {
9354         uint64_t ns, systime_cycles;
9355         struct i40e_adapter *adapter =
9356                         (struct i40e_adapter *)dev->data->dev_private;
9357
9358         systime_cycles = i40e_read_systime_cyclecounter(dev);
9359         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9360         *ts = rte_ns_to_timespec(ns);
9361
9362         return 0;
9363 }
9364
9365 static int
9366 i40e_timesync_enable(struct rte_eth_dev *dev)
9367 {
9368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9369         uint32_t tsync_ctl_l;
9370         uint32_t tsync_ctl_h;
9371
9372         /* Stop the timesync system time. */
9373         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9374         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9375         /* Reset the timesync system time value. */
9376         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9377         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9378
9379         i40e_start_timecounters(dev);
9380
9381         /* Clear timesync registers. */
9382         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9383         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9384         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9385         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9386         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9387         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9388
9389         /* Enable timestamping of PTP packets. */
9390         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9391         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9392
9393         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9394         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9395         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9396
9397         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9398         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9399
9400         return 0;
9401 }
9402
9403 static int
9404 i40e_timesync_disable(struct rte_eth_dev *dev)
9405 {
9406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9407         uint32_t tsync_ctl_l;
9408         uint32_t tsync_ctl_h;
9409
9410         /* Disable timestamping of transmitted PTP packets. */
9411         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9412         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9413
9414         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9415         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9416
9417         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9418         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9419
9420         /* Reset the timesync increment value. */
9421         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9422         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9423
9424         return 0;
9425 }
9426
9427 static int
9428 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9429                                 struct timespec *timestamp, uint32_t flags)
9430 {
9431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9432         struct i40e_adapter *adapter =
9433                 (struct i40e_adapter *)dev->data->dev_private;
9434
9435         uint32_t sync_status;
9436         uint32_t index = flags & 0x03;
9437         uint64_t rx_tstamp_cycles;
9438         uint64_t ns;
9439
9440         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9441         if ((sync_status & (1 << index)) == 0)
9442                 return -EINVAL;
9443
9444         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9445         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9446         *timestamp = rte_ns_to_timespec(ns);
9447
9448         return 0;
9449 }
9450
9451 static int
9452 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9453                                 struct timespec *timestamp)
9454 {
9455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9456         struct i40e_adapter *adapter =
9457                 (struct i40e_adapter *)dev->data->dev_private;
9458
9459         uint32_t sync_status;
9460         uint64_t tx_tstamp_cycles;
9461         uint64_t ns;
9462
9463         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9464         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9465                 return -EINVAL;
9466
9467         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9468         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9469         *timestamp = rte_ns_to_timespec(ns);
9470
9471         return 0;
9472 }
9473
9474 /*
9475  * i40e_parse_dcb_configure - parse dcb configure from user
9476  * @dev: the device being configured
9477  * @dcb_cfg: pointer of the result of parse
9478  * @*tc_map: bit map of enabled traffic classes
9479  *
9480  * Returns 0 on success, negative value on failure
9481  */
9482 static int
9483 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9484                          struct i40e_dcbx_config *dcb_cfg,
9485                          uint8_t *tc_map)
9486 {
9487         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9488         uint8_t i, tc_bw, bw_lf;
9489
9490         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9491
9492         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9493         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9494                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9495                 return -EINVAL;
9496         }
9497
9498         /* assume each tc has the same bw */
9499         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9500         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9501                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9502         /* to ensure the sum of tcbw is equal to 100 */
9503         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9504         for (i = 0; i < bw_lf; i++)
9505                 dcb_cfg->etscfg.tcbwtable[i]++;
9506
9507         /* assume each tc has the same Transmission Selection Algorithm */
9508         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9509                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9510
9511         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9512                 dcb_cfg->etscfg.prioritytable[i] =
9513                                 dcb_rx_conf->dcb_tc[i];
9514
9515         /* FW needs one App to configure HW */
9516         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9517         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9518         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9519         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9520
9521         if (dcb_rx_conf->nb_tcs == 0)
9522                 *tc_map = 1; /* tc0 only */
9523         else
9524                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9525
9526         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9527                 dcb_cfg->pfc.willing = 0;
9528                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9529                 dcb_cfg->pfc.pfcenable = *tc_map;
9530         }
9531         return 0;
9532 }
9533
9534
9535 static enum i40e_status_code
9536 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9537                               struct i40e_aqc_vsi_properties_data *info,
9538                               uint8_t enabled_tcmap)
9539 {
9540         enum i40e_status_code ret;
9541         int i, total_tc = 0;
9542         uint16_t qpnum_per_tc, bsf, qp_idx;
9543         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9544         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9545         uint16_t used_queues;
9546
9547         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9548         if (ret != I40E_SUCCESS)
9549                 return ret;
9550
9551         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9552                 if (enabled_tcmap & (1 << i))
9553                         total_tc++;
9554         }
9555         if (total_tc == 0)
9556                 total_tc = 1;
9557         vsi->enabled_tc = enabled_tcmap;
9558
9559         /* different VSI has different queues assigned */
9560         if (vsi->type == I40E_VSI_MAIN)
9561                 used_queues = dev_data->nb_rx_queues -
9562                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9563         else if (vsi->type == I40E_VSI_VMDQ2)
9564                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9565         else {
9566                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9567                 return I40E_ERR_NO_AVAILABLE_VSI;
9568         }
9569
9570         qpnum_per_tc = used_queues / total_tc;
9571         /* Number of queues per enabled TC */
9572         if (qpnum_per_tc == 0) {
9573                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9574                 return I40E_ERR_INVALID_QP_ID;
9575         }
9576         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9577                                 I40E_MAX_Q_PER_TC);
9578         bsf = rte_bsf32(qpnum_per_tc);
9579
9580         /**
9581          * Configure TC and queue mapping parameters, for enabled TC,
9582          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9583          * default queue will serve it.
9584          */
9585         qp_idx = 0;
9586         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9587                 if (vsi->enabled_tc & (1 << i)) {
9588                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9589                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9590                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9591                         qp_idx += qpnum_per_tc;
9592                 } else
9593                         info->tc_mapping[i] = 0;
9594         }
9595
9596         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9597         if (vsi->type == I40E_VSI_SRIOV) {
9598                 info->mapping_flags |=
9599                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9600                 for (i = 0; i < vsi->nb_qps; i++)
9601                         info->queue_mapping[i] =
9602                                 rte_cpu_to_le_16(vsi->base_queue + i);
9603         } else {
9604                 info->mapping_flags |=
9605                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9606                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9607         }
9608         info->valid_sections |=
9609                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9610
9611         return I40E_SUCCESS;
9612 }
9613
9614 /*
9615  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9616  * @veb: VEB to be configured
9617  * @tc_map: enabled TC bitmap
9618  *
9619  * Returns 0 on success, negative value on failure
9620  */
9621 static enum i40e_status_code
9622 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9623 {
9624         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9625         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9626         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9627         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9628         enum i40e_status_code ret = I40E_SUCCESS;
9629         int i;
9630         uint32_t bw_max;
9631
9632         /* Check if enabled_tc is same as existing or new TCs */
9633         if (veb->enabled_tc == tc_map)
9634                 return ret;
9635
9636         /* configure tc bandwidth */
9637         memset(&veb_bw, 0, sizeof(veb_bw));
9638         veb_bw.tc_valid_bits = tc_map;
9639         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9640         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9641                 if (tc_map & BIT_ULL(i))
9642                         veb_bw.tc_bw_share_credits[i] = 1;
9643         }
9644         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9645                                                    &veb_bw, NULL);
9646         if (ret) {
9647                 PMD_INIT_LOG(ERR,
9648                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9649                         hw->aq.asq_last_status);
9650                 return ret;
9651         }
9652
9653         memset(&ets_query, 0, sizeof(ets_query));
9654         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9655                                                    &ets_query, NULL);
9656         if (ret != I40E_SUCCESS) {
9657                 PMD_DRV_LOG(ERR,
9658                         "Failed to get switch_comp ETS configuration %u",
9659                         hw->aq.asq_last_status);
9660                 return ret;
9661         }
9662         memset(&bw_query, 0, sizeof(bw_query));
9663         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9664                                                   &bw_query, NULL);
9665         if (ret != I40E_SUCCESS) {
9666                 PMD_DRV_LOG(ERR,
9667                         "Failed to get switch_comp bandwidth configuration %u",
9668                         hw->aq.asq_last_status);
9669                 return ret;
9670         }
9671
9672         /* store and print out BW info */
9673         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9674         veb->bw_info.bw_max = ets_query.tc_bw_max;
9675         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9676         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9677         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9678                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9679                      I40E_16_BIT_WIDTH);
9680         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9681                 veb->bw_info.bw_ets_share_credits[i] =
9682                                 bw_query.tc_bw_share_credits[i];
9683                 veb->bw_info.bw_ets_credits[i] =
9684                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9685                 /* 4 bits per TC, 4th bit is reserved */
9686                 veb->bw_info.bw_ets_max[i] =
9687                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9688                                   RTE_LEN2MASK(3, uint8_t));
9689                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9690                             veb->bw_info.bw_ets_share_credits[i]);
9691                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9692                             veb->bw_info.bw_ets_credits[i]);
9693                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9694                             veb->bw_info.bw_ets_max[i]);
9695         }
9696
9697         veb->enabled_tc = tc_map;
9698
9699         return ret;
9700 }
9701
9702
9703 /*
9704  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9705  * @vsi: VSI to be configured
9706  * @tc_map: enabled TC bitmap
9707  *
9708  * Returns 0 on success, negative value on failure
9709  */
9710 static enum i40e_status_code
9711 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9712 {
9713         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9714         struct i40e_vsi_context ctxt;
9715         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9716         enum i40e_status_code ret = I40E_SUCCESS;
9717         int i;
9718
9719         /* Check if enabled_tc is same as existing or new TCs */
9720         if (vsi->enabled_tc == tc_map)
9721                 return ret;
9722
9723         /* configure tc bandwidth */
9724         memset(&bw_data, 0, sizeof(bw_data));
9725         bw_data.tc_valid_bits = tc_map;
9726         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9727         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9728                 if (tc_map & BIT_ULL(i))
9729                         bw_data.tc_bw_credits[i] = 1;
9730         }
9731         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9732         if (ret) {
9733                 PMD_INIT_LOG(ERR,
9734                         "AQ command Config VSI BW allocation per TC failed = %d",
9735                         hw->aq.asq_last_status);
9736                 goto out;
9737         }
9738         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9739                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9740
9741         /* Update Queue Pairs Mapping for currently enabled UPs */
9742         ctxt.seid = vsi->seid;
9743         ctxt.pf_num = hw->pf_id;
9744         ctxt.vf_num = 0;
9745         ctxt.uplink_seid = vsi->uplink_seid;
9746         ctxt.info = vsi->info;
9747         i40e_get_cap(hw);
9748         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9749         if (ret)
9750                 goto out;
9751
9752         /* Update the VSI after updating the VSI queue-mapping information */
9753         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9754         if (ret) {
9755                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9756                         hw->aq.asq_last_status);
9757                 goto out;
9758         }
9759         /* update the local VSI info with updated queue map */
9760         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9761                                         sizeof(vsi->info.tc_mapping));
9762         (void)rte_memcpy(&vsi->info.queue_mapping,
9763                         &ctxt.info.queue_mapping,
9764                 sizeof(vsi->info.queue_mapping));
9765         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9766         vsi->info.valid_sections = 0;
9767
9768         /* query and update current VSI BW information */
9769         ret = i40e_vsi_get_bw_config(vsi);
9770         if (ret) {
9771                 PMD_INIT_LOG(ERR,
9772                          "Failed updating vsi bw info, err %s aq_err %s",
9773                          i40e_stat_str(hw, ret),
9774                          i40e_aq_str(hw, hw->aq.asq_last_status));
9775                 goto out;
9776         }
9777
9778         vsi->enabled_tc = tc_map;
9779
9780 out:
9781         return ret;
9782 }
9783
9784 /*
9785  * i40e_dcb_hw_configure - program the dcb setting to hw
9786  * @pf: pf the configuration is taken on
9787  * @new_cfg: new configuration
9788  * @tc_map: enabled TC bitmap
9789  *
9790  * Returns 0 on success, negative value on failure
9791  */
9792 static enum i40e_status_code
9793 i40e_dcb_hw_configure(struct i40e_pf *pf,
9794                       struct i40e_dcbx_config *new_cfg,
9795                       uint8_t tc_map)
9796 {
9797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9798         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9799         struct i40e_vsi *main_vsi = pf->main_vsi;
9800         struct i40e_vsi_list *vsi_list;
9801         enum i40e_status_code ret;
9802         int i;
9803         uint32_t val;
9804
9805         /* Use the FW API if FW > v4.4*/
9806         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9807               (hw->aq.fw_maj_ver >= 5))) {
9808                 PMD_INIT_LOG(ERR,
9809                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9810                 return I40E_ERR_FIRMWARE_API_VERSION;
9811         }
9812
9813         /* Check if need reconfiguration */
9814         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9815                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9816                 return I40E_SUCCESS;
9817         }
9818
9819         /* Copy the new config to the current config */
9820         *old_cfg = *new_cfg;
9821         old_cfg->etsrec = old_cfg->etscfg;
9822         ret = i40e_set_dcb_config(hw);
9823         if (ret) {
9824                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9825                          i40e_stat_str(hw, ret),
9826                          i40e_aq_str(hw, hw->aq.asq_last_status));
9827                 return ret;
9828         }
9829         /* set receive Arbiter to RR mode and ETS scheme by default */
9830         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9831                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9832                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9833                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9834                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9835                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9836                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9837                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9838                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9839                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9840                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9841                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9842                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9843         }
9844         /* get local mib to check whether it is configured correctly */
9845         /* IEEE mode */
9846         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9847         /* Get Local DCB Config */
9848         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9849                                      &hw->local_dcbx_config);
9850
9851         /* if Veb is created, need to update TC of it at first */
9852         if (main_vsi->veb) {
9853                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9854                 if (ret)
9855                         PMD_INIT_LOG(WARNING,
9856                                  "Failed configuring TC for VEB seid=%d",
9857                                  main_vsi->veb->seid);
9858         }
9859         /* Update each VSI */
9860         i40e_vsi_config_tc(main_vsi, tc_map);
9861         if (main_vsi->veb) {
9862                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9863                         /* Beside main VSI and VMDQ VSIs, only enable default
9864                          * TC for other VSIs
9865                          */
9866                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9867                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9868                                                          tc_map);
9869                         else
9870                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9871                                                          I40E_DEFAULT_TCMAP);
9872                         if (ret)
9873                                 PMD_INIT_LOG(WARNING,
9874                                         "Failed configuring TC for VSI seid=%d",
9875                                         vsi_list->vsi->seid);
9876                         /* continue */
9877                 }
9878         }
9879         return I40E_SUCCESS;
9880 }
9881
9882 /*
9883  * i40e_dcb_init_configure - initial dcb config
9884  * @dev: device being configured
9885  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9886  *
9887  * Returns 0 on success, negative value on failure
9888  */
9889 static int
9890 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9891 {
9892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9894         int i, ret = 0;
9895
9896         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9897                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9898                 return -ENOTSUP;
9899         }
9900
9901         /* DCB initialization:
9902          * Update DCB configuration from the Firmware and configure
9903          * LLDP MIB change event.
9904          */
9905         if (sw_dcb == TRUE) {
9906                 ret = i40e_init_dcb(hw);
9907                 /* If lldp agent is stopped, the return value from
9908                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9909                  * adminq status. Otherwise, it should return success.
9910                  */
9911                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9912                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9913                         memset(&hw->local_dcbx_config, 0,
9914                                 sizeof(struct i40e_dcbx_config));
9915                         /* set dcb default configuration */
9916                         hw->local_dcbx_config.etscfg.willing = 0;
9917                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9918                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9919                         hw->local_dcbx_config.etscfg.tsatable[0] =
9920                                                 I40E_IEEE_TSA_ETS;
9921                         /* all UPs mapping to TC0 */
9922                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9923                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
9924                         hw->local_dcbx_config.etsrec =
9925                                 hw->local_dcbx_config.etscfg;
9926                         hw->local_dcbx_config.pfc.willing = 0;
9927                         hw->local_dcbx_config.pfc.pfccap =
9928                                                 I40E_MAX_TRAFFIC_CLASS;
9929                         hw->local_dcbx_config.pfc.pfcenable =
9930                                                 I40E_DEFAULT_TCMAP;
9931                         /* FW needs one App to configure HW */
9932                         hw->local_dcbx_config.numapps = 1;
9933                         hw->local_dcbx_config.app[0].selector =
9934                                                 I40E_APP_SEL_ETHTYPE;
9935                         hw->local_dcbx_config.app[0].priority = 3;
9936                         hw->local_dcbx_config.app[0].protocolid =
9937                                                 I40E_APP_PROTOID_FCOE;
9938                         ret = i40e_set_dcb_config(hw);
9939                         if (ret) {
9940                                 PMD_INIT_LOG(ERR,
9941                                         "default dcb config fails. err = %d, aq_err = %d.",
9942                                         ret, hw->aq.asq_last_status);
9943                                 return -ENOSYS;
9944                         }
9945                 } else {
9946                         PMD_INIT_LOG(ERR,
9947                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9948                                 ret, hw->aq.asq_last_status);
9949                         return -ENOTSUP;
9950                 }
9951         } else {
9952                 ret = i40e_aq_start_lldp(hw, NULL);
9953                 if (ret != I40E_SUCCESS)
9954                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9955
9956                 ret = i40e_init_dcb(hw);
9957                 if (!ret) {
9958                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9959                                 PMD_INIT_LOG(ERR,
9960                                         "HW doesn't support DCBX offload.");
9961                                 return -ENOTSUP;
9962                         }
9963                 } else {
9964                         PMD_INIT_LOG(ERR,
9965                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9966                                 ret, hw->aq.asq_last_status);
9967                         return -ENOTSUP;
9968                 }
9969         }
9970         return 0;
9971 }
9972
9973 /*
9974  * i40e_dcb_setup - setup dcb related config
9975  * @dev: device being configured
9976  *
9977  * Returns 0 on success, negative value on failure
9978  */
9979 static int
9980 i40e_dcb_setup(struct rte_eth_dev *dev)
9981 {
9982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9983         struct i40e_dcbx_config dcb_cfg;
9984         uint8_t tc_map = 0;
9985         int ret = 0;
9986
9987         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9988                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9989                 return -ENOTSUP;
9990         }
9991
9992         if (pf->vf_num != 0)
9993                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9994
9995         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9996         if (ret) {
9997                 PMD_INIT_LOG(ERR, "invalid dcb config");
9998                 return -EINVAL;
9999         }
10000         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10001         if (ret) {
10002                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10003                 return -ENOSYS;
10004         }
10005
10006         return 0;
10007 }
10008
10009 static int
10010 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10011                       struct rte_eth_dcb_info *dcb_info)
10012 {
10013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10015         struct i40e_vsi *vsi = pf->main_vsi;
10016         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10017         uint16_t bsf, tc_mapping;
10018         int i, j = 0;
10019
10020         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10021                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10022         else
10023                 dcb_info->nb_tcs = 1;
10024         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10025                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10026         for (i = 0; i < dcb_info->nb_tcs; i++)
10027                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10028
10029         /* get queue mapping if vmdq is disabled */
10030         if (!pf->nb_cfg_vmdq_vsi) {
10031                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10032                         if (!(vsi->enabled_tc & (1 << i)))
10033                                 continue;
10034                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10035                         dcb_info->tc_queue.tc_rxq[j][i].base =
10036                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10037                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10038                         dcb_info->tc_queue.tc_txq[j][i].base =
10039                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10040                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10041                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10042                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10043                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10044                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10045                 }
10046                 return 0;
10047         }
10048
10049         /* get queue mapping if vmdq is enabled */
10050         do {
10051                 vsi = pf->vmdq[j].vsi;
10052                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10053                         if (!(vsi->enabled_tc & (1 << i)))
10054                                 continue;
10055                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10056                         dcb_info->tc_queue.tc_rxq[j][i].base =
10057                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10058                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10059                         dcb_info->tc_queue.tc_txq[j][i].base =
10060                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10061                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10062                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10063                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10064                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10065                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10066                 }
10067                 j++;
10068         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10069         return 0;
10070 }
10071
10072 static int
10073 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10074 {
10075         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10076         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10078         uint16_t interval =
10079                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10080         uint16_t msix_intr;
10081
10082         msix_intr = intr_handle->intr_vec[queue_id];
10083         if (msix_intr == I40E_MISC_VEC_ID)
10084                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10085                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10086                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10087                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10088                                (interval <<
10089                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10090         else
10091                 I40E_WRITE_REG(hw,
10092                                I40E_PFINT_DYN_CTLN(msix_intr -
10093                                                    I40E_RX_VEC_START),
10094                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10095                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10096                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10097                                (interval <<
10098                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10099
10100         I40E_WRITE_FLUSH(hw);
10101         rte_intr_enable(&pci_dev->intr_handle);
10102
10103         return 0;
10104 }
10105
10106 static int
10107 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10108 {
10109         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10112         uint16_t msix_intr;
10113
10114         msix_intr = intr_handle->intr_vec[queue_id];
10115         if (msix_intr == I40E_MISC_VEC_ID)
10116                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10117         else
10118                 I40E_WRITE_REG(hw,
10119                                I40E_PFINT_DYN_CTLN(msix_intr -
10120                                                    I40E_RX_VEC_START),
10121                                0);
10122         I40E_WRITE_FLUSH(hw);
10123
10124         return 0;
10125 }
10126
10127 static int i40e_get_regs(struct rte_eth_dev *dev,
10128                          struct rte_dev_reg_info *regs)
10129 {
10130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10131         uint32_t *ptr_data = regs->data;
10132         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10133         const struct i40e_reg_info *reg_info;
10134
10135         if (ptr_data == NULL) {
10136                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10137                 regs->width = sizeof(uint32_t);
10138                 return 0;
10139         }
10140
10141         /* The first few registers have to be read using AQ operations */
10142         reg_idx = 0;
10143         while (i40e_regs_adminq[reg_idx].name) {
10144                 reg_info = &i40e_regs_adminq[reg_idx++];
10145                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10146                         for (arr_idx2 = 0;
10147                                         arr_idx2 <= reg_info->count2;
10148                                         arr_idx2++) {
10149                                 reg_offset = arr_idx * reg_info->stride1 +
10150                                         arr_idx2 * reg_info->stride2;
10151                                 reg_offset += reg_info->base_addr;
10152                                 ptr_data[reg_offset >> 2] =
10153                                         i40e_read_rx_ctl(hw, reg_offset);
10154                         }
10155         }
10156
10157         /* The remaining registers can be read using primitives */
10158         reg_idx = 0;
10159         while (i40e_regs_others[reg_idx].name) {
10160                 reg_info = &i40e_regs_others[reg_idx++];
10161                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10162                         for (arr_idx2 = 0;
10163                                         arr_idx2 <= reg_info->count2;
10164                                         arr_idx2++) {
10165                                 reg_offset = arr_idx * reg_info->stride1 +
10166                                         arr_idx2 * reg_info->stride2;
10167                                 reg_offset += reg_info->base_addr;
10168                                 ptr_data[reg_offset >> 2] =
10169                                         I40E_READ_REG(hw, reg_offset);
10170                         }
10171         }
10172
10173         return 0;
10174 }
10175
10176 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10177 {
10178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10179
10180         /* Convert word count to byte count */
10181         return hw->nvm.sr_size << 1;
10182 }
10183
10184 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10185                            struct rte_dev_eeprom_info *eeprom)
10186 {
10187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10188         uint16_t *data = eeprom->data;
10189         uint16_t offset, length, cnt_words;
10190         int ret_code;
10191
10192         offset = eeprom->offset >> 1;
10193         length = eeprom->length >> 1;
10194         cnt_words = length;
10195
10196         if (offset > hw->nvm.sr_size ||
10197                 offset + length > hw->nvm.sr_size) {
10198                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10199                 return -EINVAL;
10200         }
10201
10202         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10203
10204         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10205         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10206                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10207                 return -EIO;
10208         }
10209
10210         return 0;
10211 }
10212
10213 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10214                                       struct ether_addr *mac_addr)
10215 {
10216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10217
10218         if (!is_valid_assigned_ether_addr(mac_addr)) {
10219                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10220                 return;
10221         }
10222
10223         /* Flags: 0x3 updates port address */
10224         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10225 }
10226
10227 static int
10228 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10229 {
10230         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10231         struct rte_eth_dev_data *dev_data = pf->dev_data;
10232         uint32_t frame_size = mtu + ETHER_HDR_LEN
10233                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10234         int ret = 0;
10235
10236         /* check if mtu is within the allowed range */
10237         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10238                 return -EINVAL;
10239
10240         /* mtu setting is forbidden if port is start */
10241         if (dev_data->dev_started) {
10242                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10243                             dev_data->port_id);
10244                 return -EBUSY;
10245         }
10246
10247         if (frame_size > ETHER_MAX_LEN)
10248                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10249         else
10250                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10251
10252         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10253
10254         return ret;
10255 }
10256
10257 /* Restore ethertype filter */
10258 static void
10259 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10260 {
10261         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10262         struct i40e_ethertype_filter_list
10263                 *ethertype_list = &pf->ethertype.ethertype_list;
10264         struct i40e_ethertype_filter *f;
10265         struct i40e_control_filter_stats stats;
10266         uint16_t flags;
10267
10268         TAILQ_FOREACH(f, ethertype_list, rules) {
10269                 flags = 0;
10270                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10271                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10272                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10273                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10274                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10275
10276                 memset(&stats, 0, sizeof(stats));
10277                 i40e_aq_add_rem_control_packet_filter(hw,
10278                                             f->input.mac_addr.addr_bytes,
10279                                             f->input.ether_type,
10280                                             flags, pf->main_vsi->seid,
10281                                             f->queue, 1, &stats, NULL);
10282         }
10283         PMD_DRV_LOG(INFO, "Ethertype filter:"
10284                     " mac_etype_used = %u, etype_used = %u,"
10285                     " mac_etype_free = %u, etype_free = %u",
10286                     stats.mac_etype_used, stats.etype_used,
10287                     stats.mac_etype_free, stats.etype_free);
10288 }
10289
10290 /* Restore tunnel filter */
10291 static void
10292 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10293 {
10294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10295         struct i40e_vsi *vsi = pf->main_vsi;
10296         struct i40e_tunnel_filter_list
10297                 *tunnel_list = &pf->tunnel.tunnel_list;
10298         struct i40e_tunnel_filter *f;
10299         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10300
10301         TAILQ_FOREACH(f, tunnel_list, rules) {
10302                 memset(&cld_filter, 0, sizeof(cld_filter));
10303                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10304                 cld_filter.queue_number = f->queue;
10305                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10306         }
10307 }
10308
10309 static void
10310 i40e_filter_restore(struct i40e_pf *pf)
10311 {
10312         i40e_ethertype_filter_restore(pf);
10313         i40e_tunnel_filter_restore(pf);
10314         i40e_fdir_filter_restore(pf);
10315 }
10316
10317 static bool
10318 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10319 {
10320         if (strcmp(dev->driver->pci_drv.driver.name,
10321                    drv->pci_drv.driver.name))
10322                 return false;
10323
10324         return true;
10325 }
10326
10327 int
10328 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10329 {
10330         struct rte_eth_dev *dev;
10331         struct i40e_pf *pf;
10332
10333         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10334
10335         dev = &rte_eth_devices[port];
10336
10337         if (!is_device_supported(dev, &rte_i40e_pmd))
10338                 return -ENOTSUP;
10339
10340         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10341
10342         if (vf >= pf->vf_num || !pf->vfs) {
10343                 PMD_DRV_LOG(ERR, "Invalid argument.");
10344                 return -EINVAL;
10345         }
10346
10347         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10348
10349         return 0;
10350 }
10351
10352 int
10353 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10354 {
10355         struct rte_eth_dev *dev;
10356         struct i40e_pf *pf;
10357         struct i40e_vsi *vsi;
10358         struct i40e_hw *hw;
10359         struct i40e_vsi_context ctxt;
10360         int ret;
10361
10362         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10363
10364         dev = &rte_eth_devices[port];
10365
10366         if (!is_device_supported(dev, &rte_i40e_pmd))
10367                 return -ENOTSUP;
10368
10369         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10370
10371         if (vf_id >= pf->vf_num || !pf->vfs) {
10372                 PMD_DRV_LOG(ERR, "Invalid argument.");
10373                 return -EINVAL;
10374         }
10375
10376         vsi = pf->vfs[vf_id].vsi;
10377         if (!vsi) {
10378                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10379                 return -EINVAL;
10380         }
10381
10382         /* Check if it has been already on or off */
10383         if (vsi->info.valid_sections &
10384                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10385                 if (on) {
10386                         if ((vsi->info.sec_flags &
10387                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10388                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10389                                 return 0; /* already on */
10390                 } else {
10391                         if ((vsi->info.sec_flags &
10392                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10393                                 return 0; /* already off */
10394                 }
10395         }
10396
10397         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10398         if (on)
10399                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10400         else
10401                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10402
10403         memset(&ctxt, 0, sizeof(ctxt));
10404         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10405         ctxt.seid = vsi->seid;
10406
10407         hw = I40E_VSI_TO_HW(vsi);
10408         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10409         if (ret != I40E_SUCCESS) {
10410                 ret = -ENOTSUP;
10411                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10412         }
10413
10414         return ret;
10415 }
10416
10417 static int
10418 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10419 {
10420         uint32_t j, k;
10421         uint16_t vlan_id;
10422         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10423         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10424         int ret;
10425
10426         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10427                 if (!vsi->vfta[j])
10428                         continue;
10429
10430                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10431                         if (!(vsi->vfta[j] & (1 << k)))
10432                                 continue;
10433
10434                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10435                         if (!vlan_id)
10436                                 continue;
10437
10438                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10439                         if (add)
10440                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10441                                                        &vlan_data, 1, NULL);
10442                         else
10443                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10444                                                           &vlan_data, 1, NULL);
10445                         if (ret != I40E_SUCCESS) {
10446                                 PMD_DRV_LOG(ERR,
10447                                             "Failed to add/rm vlan filter");
10448                                 return ret;
10449                         }
10450                 }
10451         }
10452
10453         return I40E_SUCCESS;
10454 }
10455
10456 int
10457 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10458 {
10459         struct rte_eth_dev *dev;
10460         struct i40e_pf *pf;
10461         struct i40e_vsi *vsi;
10462         struct i40e_hw *hw;
10463         struct i40e_vsi_context ctxt;
10464         int ret;
10465
10466         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10467
10468         dev = &rte_eth_devices[port];
10469
10470         if (!is_device_supported(dev, &rte_i40e_pmd))
10471                 return -ENOTSUP;
10472
10473         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10474
10475         if (vf_id >= pf->vf_num || !pf->vfs) {
10476                 PMD_DRV_LOG(ERR, "Invalid argument.");
10477                 return -EINVAL;
10478         }
10479
10480         vsi = pf->vfs[vf_id].vsi;
10481         if (!vsi) {
10482                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10483                 return -EINVAL;
10484         }
10485
10486         /* Check if it has been already on or off */
10487         if (vsi->vlan_anti_spoof_on == on)
10488                 return 0; /* already on or off */
10489
10490         vsi->vlan_anti_spoof_on = on;
10491         if (!vsi->vlan_filter_on) {
10492                 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10493                 if (ret) {
10494                         PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10495                         return -ENOTSUP;
10496                 }
10497         }
10498
10499         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10500         if (on)
10501                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10502         else
10503                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10504
10505         memset(&ctxt, 0, sizeof(ctxt));
10506         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10507         ctxt.seid = vsi->seid;
10508
10509         hw = I40E_VSI_TO_HW(vsi);
10510         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10511         if (ret != I40E_SUCCESS) {
10512                 ret = -ENOTSUP;
10513                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10514         }
10515
10516         return ret;
10517 }
10518
10519 static int
10520 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10521 {
10522         struct i40e_mac_filter *f;
10523         struct i40e_macvlan_filter *mv_f;
10524         int i, vlan_num;
10525         enum rte_mac_filter_type filter_type;
10526         int ret = I40E_SUCCESS;
10527         void *temp;
10528
10529         /* remove all the MACs */
10530         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10531                 vlan_num = vsi->vlan_num;
10532                 filter_type = f->mac_info.filter_type;
10533                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10534                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10535                         if (vlan_num == 0) {
10536                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10537                                 return I40E_ERR_PARAM;
10538                         }
10539                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10540                            filter_type == RTE_MAC_HASH_MATCH)
10541                         vlan_num = 1;
10542
10543                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10544                 if (!mv_f) {
10545                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10546                         return I40E_ERR_NO_MEMORY;
10547                 }
10548
10549                 for (i = 0; i < vlan_num; i++) {
10550                         mv_f[i].filter_type = filter_type;
10551                         (void)rte_memcpy(&mv_f[i].macaddr,
10552                                          &f->mac_info.mac_addr,
10553                                          ETH_ADDR_LEN);
10554                 }
10555                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10556                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10557                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10558                                                          &f->mac_info.mac_addr);
10559                         if (ret != I40E_SUCCESS) {
10560                                 rte_free(mv_f);
10561                                 return ret;
10562                         }
10563                 }
10564
10565                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10566                 if (ret != I40E_SUCCESS) {
10567                         rte_free(mv_f);
10568                         return ret;
10569                 }
10570
10571                 rte_free(mv_f);
10572                 ret = I40E_SUCCESS;
10573         }
10574
10575         return ret;
10576 }
10577
10578 static int
10579 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10580 {
10581         struct i40e_mac_filter *f;
10582         struct i40e_macvlan_filter *mv_f;
10583         int i, vlan_num = 0;
10584         int ret = I40E_SUCCESS;
10585         void *temp;
10586
10587         /* restore all the MACs */
10588         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10589                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10590                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10591                         /**
10592                          * If vlan_num is 0, that's the first time to add mac,
10593                          * set mask for vlan_id 0.
10594                          */
10595                         if (vsi->vlan_num == 0) {
10596                                 i40e_set_vlan_filter(vsi, 0, 1);
10597                                 vsi->vlan_num = 1;
10598                         }
10599                         vlan_num = vsi->vlan_num;
10600                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10601                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10602                         vlan_num = 1;
10603
10604                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10605                 if (!mv_f) {
10606                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10607                         return I40E_ERR_NO_MEMORY;
10608                 }
10609
10610                 for (i = 0; i < vlan_num; i++) {
10611                         mv_f[i].filter_type = f->mac_info.filter_type;
10612                         (void)rte_memcpy(&mv_f[i].macaddr,
10613                                          &f->mac_info.mac_addr,
10614                                          ETH_ADDR_LEN);
10615                 }
10616
10617                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10618                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10619                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10620                                                          &f->mac_info.mac_addr);
10621                         if (ret != I40E_SUCCESS) {
10622                                 rte_free(mv_f);
10623                                 return ret;
10624                         }
10625                 }
10626
10627                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10628                 if (ret != I40E_SUCCESS) {
10629                         rte_free(mv_f);
10630                         return ret;
10631                 }
10632
10633                 rte_free(mv_f);
10634                 ret = I40E_SUCCESS;
10635         }
10636
10637         return ret;
10638 }
10639
10640 static int
10641 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10642 {
10643         struct i40e_vsi_context ctxt;
10644         struct i40e_hw *hw;
10645         int ret;
10646
10647         if (!vsi)
10648                 return -EINVAL;
10649
10650         hw = I40E_VSI_TO_HW(vsi);
10651
10652         /* Use the FW API if FW >= v5.0 */
10653         if (hw->aq.fw_maj_ver < 5) {
10654                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10655                 return -ENOTSUP;
10656         }
10657
10658         /* Check if it has been already on or off */
10659         if (vsi->info.valid_sections &
10660                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10661                 if (on) {
10662                         if ((vsi->info.switch_id &
10663                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10664                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10665                                 return 0; /* already on */
10666                 } else {
10667                         if ((vsi->info.switch_id &
10668                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10669                                 return 0; /* already off */
10670                 }
10671         }
10672
10673         /* remove all the MAC and VLAN first */
10674         ret = i40e_vsi_rm_mac_filter(vsi);
10675         if (ret) {
10676                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10677                 return ret;
10678         }
10679         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10680                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10681                 if (ret) {
10682                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10683                         return ret;
10684                 }
10685         }
10686
10687         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10688         if (on)
10689                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10690         else
10691                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10692
10693         memset(&ctxt, 0, sizeof(ctxt));
10694         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10695         ctxt.seid = vsi->seid;
10696
10697         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10698         if (ret != I40E_SUCCESS) {
10699                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10700                 return ret;
10701         }
10702
10703         /* add all the MAC and VLAN back */
10704         ret = i40e_vsi_restore_mac_filter(vsi);
10705         if (ret)
10706                 return ret;
10707         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10708                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10709                 if (ret)
10710                         return ret;
10711         }
10712
10713         return ret;
10714 }
10715
10716 int
10717 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10718 {
10719         struct rte_eth_dev *dev;
10720         struct i40e_pf *pf;
10721         struct i40e_pf_vf *vf;
10722         struct i40e_vsi *vsi;
10723         uint16_t vf_id;
10724         int ret;
10725
10726         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10727
10728         dev = &rte_eth_devices[port];
10729
10730         if (!is_device_supported(dev, &rte_i40e_pmd))
10731                 return -ENOTSUP;
10732
10733         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10734
10735         /* setup PF TX loopback */
10736         vsi = pf->main_vsi;
10737         ret = i40e_vsi_set_tx_loopback(vsi, on);
10738         if (ret)
10739                 return -ENOTSUP;
10740
10741         /* setup TX loopback for all the VFs */
10742         if (!pf->vfs) {
10743                 /* if no VF, do nothing. */
10744                 return 0;
10745         }
10746
10747         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10748                 vf = &pf->vfs[vf_id];
10749                 vsi = vf->vsi;
10750
10751                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10752                 if (ret)
10753                         return -ENOTSUP;
10754         }
10755
10756         return ret;
10757 }
10758
10759 int
10760 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10761 {
10762         struct rte_eth_dev *dev;
10763         struct i40e_pf *pf;
10764         struct i40e_vsi *vsi;
10765         struct i40e_hw *hw;
10766         int ret;
10767
10768         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10769
10770         dev = &rte_eth_devices[port];
10771
10772         if (!is_device_supported(dev, &rte_i40e_pmd))
10773                 return -ENOTSUP;
10774
10775         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10776
10777         if (vf_id >= pf->vf_num || !pf->vfs) {
10778                 PMD_DRV_LOG(ERR, "Invalid argument.");
10779                 return -EINVAL;
10780         }
10781
10782         vsi = pf->vfs[vf_id].vsi;
10783         if (!vsi) {
10784                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10785                 return -EINVAL;
10786         }
10787
10788         hw = I40E_VSI_TO_HW(vsi);
10789
10790         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10791                                                   on, NULL, true);
10792         if (ret != I40E_SUCCESS) {
10793                 ret = -ENOTSUP;
10794                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10795         }
10796
10797         return ret;
10798 }
10799
10800 int
10801 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10802 {
10803         struct rte_eth_dev *dev;
10804         struct i40e_pf *pf;
10805         struct i40e_vsi *vsi;
10806         struct i40e_hw *hw;
10807         int ret;
10808
10809         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10810
10811         dev = &rte_eth_devices[port];
10812
10813         if (!is_device_supported(dev, &rte_i40e_pmd))
10814                 return -ENOTSUP;
10815
10816         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10817
10818         if (vf_id >= pf->vf_num || !pf->vfs) {
10819                 PMD_DRV_LOG(ERR, "Invalid argument.");
10820                 return -EINVAL;
10821         }
10822
10823         vsi = pf->vfs[vf_id].vsi;
10824         if (!vsi) {
10825                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10826                 return -EINVAL;
10827         }
10828
10829         hw = I40E_VSI_TO_HW(vsi);
10830
10831         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10832                                                     on, NULL);
10833         if (ret != I40E_SUCCESS) {
10834                 ret = -ENOTSUP;
10835                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10836         }
10837
10838         return ret;
10839 }
10840
10841 int
10842 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10843                              struct ether_addr *mac_addr)
10844 {
10845         struct i40e_mac_filter *f;
10846         struct rte_eth_dev *dev;
10847         struct i40e_pf_vf *vf;
10848         struct i40e_vsi *vsi;
10849         struct i40e_pf *pf;
10850         void *temp;
10851
10852         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10853                 return -EINVAL;
10854
10855         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10856
10857         dev = &rte_eth_devices[port];
10858
10859         if (!is_device_supported(dev, &rte_i40e_pmd))
10860                 return -ENOTSUP;
10861
10862         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10863
10864         if (vf_id >= pf->vf_num || !pf->vfs)
10865                 return -EINVAL;
10866
10867         vf = &pf->vfs[vf_id];
10868         vsi = vf->vsi;
10869         if (!vsi) {
10870                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10871                 return -EINVAL;
10872         }
10873
10874         ether_addr_copy(mac_addr, &vf->mac_addr);
10875
10876         /* Remove all existing mac */
10877         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10878                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10879
10880         return 0;
10881 }
10882
10883 /* Set vlan strip on/off for specific VF from host */
10884 int
10885 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10886 {
10887         struct rte_eth_dev *dev;
10888         struct i40e_pf *pf;
10889         struct i40e_vsi *vsi;
10890         int ret;
10891
10892         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10893
10894         dev = &rte_eth_devices[port];
10895
10896         if (!is_device_supported(dev, &rte_i40e_pmd))
10897                 return -ENOTSUP;
10898
10899         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10900
10901         if (vf_id >= pf->vf_num || !pf->vfs) {
10902                 PMD_DRV_LOG(ERR, "Invalid argument.");
10903                 return -EINVAL;
10904         }
10905
10906         vsi = pf->vfs[vf_id].vsi;
10907
10908         if (!vsi)
10909                 return -EINVAL;
10910
10911         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10912         if (ret != I40E_SUCCESS) {
10913                 ret = -ENOTSUP;
10914                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10915         }
10916
10917         return ret;
10918 }
10919
10920 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10921                                     uint16_t vlan_id)
10922 {
10923         struct rte_eth_dev *dev;
10924         struct i40e_pf *pf;
10925         struct i40e_hw *hw;
10926         struct i40e_vsi *vsi;
10927         struct i40e_vsi_context ctxt;
10928         int ret;
10929
10930         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10931
10932         if (vlan_id > ETHER_MAX_VLAN_ID) {
10933                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10934                 return -EINVAL;
10935         }
10936
10937         dev = &rte_eth_devices[port];
10938
10939         if (!is_device_supported(dev, &rte_i40e_pmd))
10940                 return -ENOTSUP;
10941
10942         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10943         hw = I40E_PF_TO_HW(pf);
10944
10945         /**
10946          * return -ENODEV if SRIOV not enabled, VF number not configured
10947          * or no queue assigned.
10948          */
10949         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10950             pf->vf_nb_qps == 0)
10951                 return -ENODEV;
10952
10953         if (vf_id >= pf->vf_num || !pf->vfs) {
10954                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10955                 return -EINVAL;
10956         }
10957
10958         vsi = pf->vfs[vf_id].vsi;
10959         if (!vsi) {
10960                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10961                 return -EINVAL;
10962         }
10963
10964         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10965         vsi->info.pvid = vlan_id;
10966         if (vlan_id > 0)
10967                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10968         else
10969                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10970
10971         memset(&ctxt, 0, sizeof(ctxt));
10972         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10973         ctxt.seid = vsi->seid;
10974
10975         hw = I40E_VSI_TO_HW(vsi);
10976         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10977         if (ret != I40E_SUCCESS) {
10978                 ret = -ENOTSUP;
10979                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10980         }
10981
10982         return ret;
10983 }
10984
10985 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10986                                   uint8_t on)
10987 {
10988         struct rte_eth_dev *dev;
10989         struct i40e_pf *pf;
10990         struct i40e_vsi *vsi;
10991         struct i40e_hw *hw;
10992         struct i40e_mac_filter_info filter;
10993         struct ether_addr broadcast = {
10994                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
10995         int ret;
10996
10997         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10998
10999         if (on > 1) {
11000                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11001                 return -EINVAL;
11002         }
11003
11004         dev = &rte_eth_devices[port];
11005
11006         if (!is_device_supported(dev, &rte_i40e_pmd))
11007                 return -ENOTSUP;
11008
11009         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11010         hw = I40E_PF_TO_HW(pf);
11011
11012         if (vf_id >= pf->vf_num || !pf->vfs) {
11013                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11014                 return -EINVAL;
11015         }
11016
11017         /**
11018          * return -ENODEV if SRIOV not enabled, VF number not configured
11019          * or no queue assigned.
11020          */
11021         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11022             pf->vf_nb_qps == 0) {
11023                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11024                 return -ENODEV;
11025         }
11026
11027         vsi = pf->vfs[vf_id].vsi;
11028         if (!vsi) {
11029                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11030                 return -EINVAL;
11031         }
11032
11033         if (on) {
11034                 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11035                 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11036                 ret = i40e_vsi_add_mac(vsi, &filter);
11037         } else {
11038                 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11039         }
11040
11041         if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11042                 ret = -ENOTSUP;
11043                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11044         } else {
11045                 ret = 0;
11046         }
11047
11048         return ret;
11049 }
11050
11051 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11052 {
11053         struct rte_eth_dev *dev;
11054         struct i40e_pf *pf;
11055         struct i40e_hw *hw;
11056         struct i40e_vsi *vsi;
11057         struct i40e_vsi_context ctxt;
11058         int ret;
11059
11060         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11061
11062         if (on > 1) {
11063                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11064                 return -EINVAL;
11065         }
11066
11067         dev = &rte_eth_devices[port];
11068
11069         if (!is_device_supported(dev, &rte_i40e_pmd))
11070                 return -ENOTSUP;
11071
11072         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11073         hw = I40E_PF_TO_HW(pf);
11074
11075         /**
11076          * return -ENODEV if SRIOV not enabled, VF number not configured
11077          * or no queue assigned.
11078          */
11079         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11080             pf->vf_nb_qps == 0) {
11081                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11082                 return -ENODEV;
11083         }
11084
11085         if (vf_id >= pf->vf_num || !pf->vfs) {
11086                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11087                 return -EINVAL;
11088         }
11089
11090         vsi = pf->vfs[vf_id].vsi;
11091         if (!vsi) {
11092                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11093                 return -EINVAL;
11094         }
11095
11096         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11097         if (on) {
11098                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11099                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11100         } else {
11101                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11102                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11103         }
11104
11105         memset(&ctxt, 0, sizeof(ctxt));
11106         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11107         ctxt.seid = vsi->seid;
11108
11109         hw = I40E_VSI_TO_HW(vsi);
11110         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11111         if (ret != I40E_SUCCESS) {
11112                 ret = -ENOTSUP;
11113                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11114         }
11115
11116         return ret;
11117 }
11118
11119 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11120                                     uint64_t vf_mask, uint8_t on)
11121 {
11122         struct rte_eth_dev *dev;
11123         struct i40e_pf *pf;
11124         struct i40e_hw *hw;
11125         struct i40e_vsi *vsi;
11126         uint16_t vf_idx;
11127         int ret = I40E_SUCCESS;
11128
11129         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11130
11131         dev = &rte_eth_devices[port];
11132
11133         if (!is_device_supported(dev, &rte_i40e_pmd))
11134                 return -ENOTSUP;
11135
11136         if (vlan_id > ETHER_MAX_VLAN_ID) {
11137                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11138                 return -EINVAL;
11139         }
11140
11141         if (vf_mask == 0) {
11142                 PMD_DRV_LOG(ERR, "No VF.");
11143                 return -EINVAL;
11144         }
11145
11146         if (on > 1) {
11147                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11148                 return -EINVAL;
11149         }
11150
11151         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11152         hw = I40E_PF_TO_HW(pf);
11153
11154         /**
11155          * return -ENODEV if SRIOV not enabled, VF number not configured
11156          * or no queue assigned.
11157          */
11158         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11159             pf->vf_nb_qps == 0) {
11160                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11161                 return -ENODEV;
11162         }
11163
11164         for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11165                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11166                         vsi = pf->vfs[vf_idx].vsi;
11167                         if (on) {
11168                                 if (!vsi->vlan_filter_on) {
11169                                         vsi->vlan_filter_on = true;
11170                                         if (!vsi->vlan_anti_spoof_on)
11171                                                 i40e_add_rm_all_vlan_filter(
11172                                                         vsi, true);
11173                                 }
11174                                 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11175                                                              false, NULL);
11176                                 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11177                         } else {
11178                                 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11179                         }
11180                 }
11181         }
11182
11183         if (ret != I40E_SUCCESS) {
11184                 ret = -ENOTSUP;
11185                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11186         }
11187
11188         return ret;
11189 }
11190
11191 int
11192 rte_pmd_i40e_get_vf_stats(uint8_t port,
11193                           uint16_t vf_id,
11194                           struct rte_eth_stats *stats)
11195 {
11196         struct rte_eth_dev *dev;
11197         struct i40e_pf *pf;
11198         struct i40e_vsi *vsi;
11199
11200         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11201
11202         dev = &rte_eth_devices[port];
11203
11204         if (!is_device_supported(dev, &rte_i40e_pmd))
11205                 return -ENOTSUP;
11206
11207         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11208
11209         if (vf_id >= pf->vf_num || !pf->vfs) {
11210                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11211                 return -EINVAL;
11212         }
11213
11214         vsi = pf->vfs[vf_id].vsi;
11215         if (!vsi) {
11216                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11217                 return -EINVAL;
11218         }
11219
11220         i40e_update_vsi_stats(vsi);
11221
11222         stats->ipackets = vsi->eth_stats.rx_unicast +
11223                         vsi->eth_stats.rx_multicast +
11224                         vsi->eth_stats.rx_broadcast;
11225         stats->opackets = vsi->eth_stats.tx_unicast +
11226                         vsi->eth_stats.tx_multicast +
11227                         vsi->eth_stats.tx_broadcast;
11228         stats->ibytes   = vsi->eth_stats.rx_bytes;
11229         stats->obytes   = vsi->eth_stats.tx_bytes;
11230         stats->ierrors  = vsi->eth_stats.rx_discards;
11231         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11232
11233         return 0;
11234 }
11235
11236 int
11237 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11238                             uint16_t vf_id)
11239 {
11240         struct rte_eth_dev *dev;
11241         struct i40e_pf *pf;
11242         struct i40e_vsi *vsi;
11243
11244         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11245
11246         dev = &rte_eth_devices[port];
11247
11248         if (!is_device_supported(dev, &rte_i40e_pmd))
11249                 return -ENOTSUP;
11250
11251         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11252
11253         if (vf_id >= pf->vf_num || !pf->vfs) {
11254                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11255                 return -EINVAL;
11256         }
11257
11258         vsi = pf->vfs[vf_id].vsi;
11259         if (!vsi) {
11260                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11261                 return -EINVAL;
11262         }
11263
11264         vsi->offset_loaded = false;
11265         i40e_update_vsi_stats(vsi);
11266
11267         return 0;
11268 }
11269
11270 int
11271 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11272 {
11273         struct rte_eth_dev *dev;
11274         struct i40e_pf *pf;
11275         struct i40e_vsi *vsi;
11276         struct i40e_hw *hw;
11277         int ret = 0;
11278         int i;
11279
11280         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11281
11282         dev = &rte_eth_devices[port];
11283
11284         if (!is_device_supported(dev, &rte_i40e_pmd))
11285                 return -ENOTSUP;
11286
11287         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11288
11289         if (vf_id >= pf->vf_num || !pf->vfs) {
11290                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11291                 return -EINVAL;
11292         }
11293
11294         vsi = pf->vfs[vf_id].vsi;
11295         if (!vsi) {
11296                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11297                 return -EINVAL;
11298         }
11299
11300         if (bw > I40E_QOS_BW_MAX) {
11301                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11302                             I40E_QOS_BW_MAX);
11303                 return -EINVAL;
11304         }
11305
11306         if (bw % I40E_QOS_BW_GRANULARITY) {
11307                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11308                             I40E_QOS_BW_GRANULARITY);
11309                 return -EINVAL;
11310         }
11311
11312         bw /= I40E_QOS_BW_GRANULARITY;
11313
11314         hw = I40E_VSI_TO_HW(vsi);
11315
11316         /* No change. */
11317         if (bw == vsi->bw_info.bw_limit) {
11318                 PMD_DRV_LOG(INFO,
11319                             "No change for VF max bandwidth. Nothing to do.");
11320                 return 0;
11321         }
11322
11323         /**
11324          * VF bandwidth limitation and TC bandwidth limitation cannot be
11325          * enabled in parallel, quit if TC bandwidth limitation is enabled.
11326          *
11327          * If bw is 0, means disable bandwidth limitation. Then no need to
11328          * check TC bandwidth limitation.
11329          */
11330         if (bw) {
11331                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11332                         if ((vsi->enabled_tc & BIT_ULL(i)) &&
11333                             vsi->bw_info.bw_ets_credits[i])
11334                                 break;
11335                 }
11336                 if (i != I40E_MAX_TRAFFIC_CLASS) {
11337                         PMD_DRV_LOG(ERR,
11338                                     "TC max bandwidth has been set on this VF,"
11339                                     " please disable it first.");
11340                         return -EINVAL;
11341                 }
11342         }
11343
11344         ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11345         if (ret) {
11346                 PMD_DRV_LOG(ERR,
11347                             "Failed to set VF %d bandwidth, err(%d).",
11348                             vf_id, ret);
11349                 return -EINVAL;
11350         }
11351
11352         /* Store the configuration. */
11353         vsi->bw_info.bw_limit = (uint16_t)bw;
11354         vsi->bw_info.bw_max = 0;
11355
11356         return 0;
11357 }