1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
10 #include <rte_eth_ctrl.h>
12 #include <rte_kvargs.h>
15 #include <rte_flow_driver.h>
16 #include <rte_tm_driver.h>
17 #include "rte_pmd_i40e.h"
19 #include "base/i40e_register.h"
21 #define I40E_VLAN_TAG_SIZE 4
23 #define I40E_AQ_LEN 32
24 #define I40E_AQ_BUF_SZ 4096
25 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
26 #define I40E_MAX_Q_PER_TC 64
27 #define I40E_NUM_DESC_DEFAULT 512
28 #define I40E_NUM_DESC_ALIGN 32
29 #define I40E_BUF_SIZE_MIN 1024
30 #define I40E_FRAME_SIZE_MAX 9728
31 #define I40E_TSO_FRAME_SIZE_MAX 262144
32 #define I40E_QUEUE_BASE_ADDR_UNIT 128
33 /* number of VSIs and queue default setting */
34 #define I40E_MAX_QP_NUM_PER_VF 16
35 #define I40E_DEFAULT_QP_NUM_FDIR 1
36 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
37 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
38 /* Maximun number of MAC addresses */
39 #define I40E_NUM_MACADDR_MAX 64
40 /* Maximum number of VFs */
41 #define I40E_MAX_VF 128
42 /*flag of no loopback*/
43 #define I40E_AQ_LB_MODE_NONE 0x0
45 * vlan_id is a 12 bit number.
46 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
47 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
48 * The higher 7 bit val specifies VFTA array index.
50 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
51 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
53 /* Default TC traffic in case DCB is not enabled */
54 #define I40E_DEFAULT_TCMAP 0x1
55 #define I40E_FDIR_QUEUE_ID 0
57 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
58 #define I40E_VMDQ_POOL_BASE 1
60 #define I40E_DEFAULT_RX_FREE_THRESH 32
61 #define I40E_DEFAULT_RX_PTHRESH 8
62 #define I40E_DEFAULT_RX_HTHRESH 8
63 #define I40E_DEFAULT_RX_WTHRESH 0
65 #define I40E_DEFAULT_TX_FREE_THRESH 32
66 #define I40E_DEFAULT_TX_PTHRESH 32
67 #define I40E_DEFAULT_TX_HTHRESH 0
68 #define I40E_DEFAULT_TX_WTHRESH 0
69 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
71 /* Bit shift and mask */
72 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
73 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
74 #define I40E_8_BIT_WIDTH CHAR_BIT
75 #define I40E_8_BIT_MASK UINT8_MAX
76 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
77 #define I40E_16_BIT_MASK UINT16_MAX
78 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
79 #define I40E_32_BIT_MASK UINT32_MAX
80 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
81 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
83 /* Linux PF host with virtchnl version 1.1 */
84 #define PF_IS_V11(vf) \
85 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
86 ((vf)->version_minor == 1))
88 #define I40E_WRITE_GLB_REG(hw, reg, value) \
91 struct rte_eth_dev *dev; \
92 ori_val = I40E_READ_REG((hw), (reg)); \
93 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
94 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
96 if (ori_val != value) \
97 PMD_DRV_LOG(WARNING, \
98 "i40e device %s changed global " \
99 "register [0x%08x]. original: 0x%08x, " \
101 (dev->device->name), (reg), \
102 (ori_val), (value)); \
105 /* index flex payload per layer */
106 enum i40e_flxpld_layer_idx {
107 I40E_FLXPLD_L2_IDX = 0,
108 I40E_FLXPLD_L3_IDX = 1,
109 I40E_FLXPLD_L4_IDX = 2,
110 I40E_MAX_FLXPLD_LAYER = 3,
112 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
113 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
114 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
115 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
116 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
119 #define I40E_FLAG_RSS (1ULL << 0)
120 #define I40E_FLAG_DCB (1ULL << 1)
121 #define I40E_FLAG_VMDQ (1ULL << 2)
122 #define I40E_FLAG_SRIOV (1ULL << 3)
123 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
124 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
125 #define I40E_FLAG_FDIR (1ULL << 6)
126 #define I40E_FLAG_VXLAN (1ULL << 7)
127 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
128 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
129 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
133 I40E_FLAG_HEADER_SPLIT_DISABLED | \
134 I40E_FLAG_HEADER_SPLIT_ENABLED | \
137 I40E_FLAG_RSS_AQ_CAPABLE | \
138 I40E_FLAG_VF_MAC_BY_PF)
140 #define I40E_RSS_OFFLOAD_ALL ( \
141 ETH_RSS_FRAG_IPV4 | \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
144 ETH_RSS_NONFRAG_IPV4_SCTP | \
145 ETH_RSS_NONFRAG_IPV4_OTHER | \
146 ETH_RSS_FRAG_IPV6 | \
147 ETH_RSS_NONFRAG_IPV6_TCP | \
148 ETH_RSS_NONFRAG_IPV6_UDP | \
149 ETH_RSS_NONFRAG_IPV6_SCTP | \
150 ETH_RSS_NONFRAG_IPV6_OTHER | \
153 /* All bits of RSS hash enable for X722*/
154 #define I40E_RSS_HENA_ALL_X722 ( \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
163 /* All bits of RSS hash enable */
164 #define I40E_RSS_HENA_ALL ( \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
169 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
174 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
175 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
177 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
178 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
180 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
181 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
183 /* Default queue interrupt throttling time in microseconds */
184 #define I40E_ITR_INDEX_DEFAULT 0
185 #define I40E_ITR_INDEX_NONE 3
186 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
187 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
188 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
189 /* Special FW support this floating VEB feature */
190 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
191 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
193 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
195 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
196 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
198 #define I40E_INSET_NONE 0x00000000000000000ULL
201 #define I40E_INSET_DMAC 0x0000000000000001ULL
202 #define I40E_INSET_SMAC 0x0000000000000002ULL
203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
216 /* bit 16 ~ bit 31 */
217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
226 /* bit 32 ~ bit 47, tunnel fields */
227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
234 /* bit 48 ~ bit 55 */
235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
237 /* bit 56 ~ bit 63, Flex Payload */
238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD \
247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
252 /* The max bandwidth of i40e is 40Gbps. */
253 #define I40E_QOS_BW_MAX 40000
254 /* The bandwidth should be the multiple of 50Mbps. */
255 #define I40E_QOS_BW_GRANULARITY 50
256 /* The min bandwidth weight is 1. */
257 #define I40E_QOS_BW_WEIGHT_MIN 1
258 /* The max bandwidth weight is 127. */
259 #define I40E_QOS_BW_WEIGHT_MAX 127
260 /* The max queue region index is 7. */
261 #define I40E_REGION_MAX_INDEX 7
263 #define I40E_MAX_PERCENT 100
264 #define I40E_DEFAULT_DCB_APP_NUM 1
265 #define I40E_DEFAULT_DCB_APP_PRIO 3
268 * The overhead from MTU to max frame size.
269 * Considering QinQ packet, the VLAN tag needs to be counted twice.
271 #define I40E_ETH_OVERHEAD \
272 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
277 * MAC filter structure
279 struct i40e_mac_filter_info {
280 enum rte_mac_filter_type filter_type;
281 struct ether_addr mac_addr;
284 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
286 /* MAC filter list structure */
287 struct i40e_mac_filter {
288 TAILQ_ENTRY(i40e_mac_filter) next;
289 struct i40e_mac_filter_info mac_info;
292 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
296 /* VSI list structure */
297 struct i40e_vsi_list {
298 TAILQ_ENTRY(i40e_vsi_list) list;
299 struct i40e_vsi *vsi;
302 struct i40e_rx_queue;
303 struct i40e_tx_queue;
305 /* Bandwidth limit information */
306 struct i40e_bw_info {
307 uint16_t bw_limit; /* BW Limit (0 = disabled) */
308 uint8_t bw_max; /* Max BW limit if enabled */
310 /* Relative credits within same TC with respect to other VSIs or Comps */
311 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
312 /* Bandwidth limit per TC */
313 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
314 /* Max bandwidth limit per TC */
315 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
318 /* Structure that defines a VEB */
320 struct i40e_vsi_list_head head;
321 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
322 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
323 uint16_t seid; /* The seid of VEB itself */
324 uint16_t uplink_seid; /* The uplink seid of this VEB */
326 struct i40e_eth_stats stats;
327 uint8_t enabled_tc; /* The traffic class enabled */
328 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
329 struct i40e_bw_info bw_info; /* VEB bandwidth information */
332 /* i40e MACVLAN filter structure */
333 struct i40e_macvlan_filter {
334 struct ether_addr macaddr;
335 enum rte_mac_filter_type filter_type;
340 * Structure that defines a VSI, associated with a adapter.
343 struct i40e_adapter *adapter; /* Backreference to associated adapter */
344 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
346 struct i40e_eth_stats eth_stats_offset;
347 struct i40e_eth_stats eth_stats;
349 * When drivers loaded, only a default main VSI exists. In case new VSI
350 * needs to add, HW needs to know the layout that VSIs are organized.
351 * Besides that, VSI isan element and can't switch packets, which needs
352 * to add new component VEB to perform switching. So, a new VSI needs
353 * to specify the uplink VSI (Parent VSI) before created. The
354 * uplink VSI will check whether it had a VEB to switch packets. If no,
355 * it will try to create one. Then, uplink VSI will move the new VSI
356 * into its' sib_vsi_list to manage all the downlink VSI.
357 * sib_vsi_list: the VSI list that shared the same uplink VSI.
358 * parent_vsi : the uplink VSI. It's NULL for main VSI.
359 * veb : the VEB associates with the VSI.
361 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
362 struct i40e_vsi *parent_vsi;
363 struct i40e_veb *veb; /* Associated veb, could be null */
364 struct i40e_veb *floating_veb; /* Associated floating veb */
366 enum i40e_vsi_type type; /* VSI types */
367 uint16_t vlan_num; /* Total VLAN number */
368 uint16_t mac_num; /* Total mac number */
369 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
370 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
371 /* specific VSI-defined parameters, SRIOV stored the vf_id */
373 uint16_t seid; /* The seid of VSI itself */
374 uint16_t uplink_seid; /* The uplink seid of this VSI */
375 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
376 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
377 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
378 uint16_t base_queue; /* The first queue index of this VSI */
380 * The offset to visit VSI related register, assigned by HW when
384 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
385 uint16_t nb_msix; /* The max number of msix vector */
386 uint8_t enabled_tc; /* The traffic class enabled */
387 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
388 uint8_t vlan_filter_on; /* The VLAN filter enabled */
389 struct i40e_bw_info bw_info; /* VSI bandwidth information */
393 LIST_ENTRY(pool_entry) next;
398 LIST_HEAD(res_list, pool_entry);
400 struct i40e_res_pool_info {
401 uint32_t base; /* Resource start index */
402 uint32_t num_alloc; /* Allocated resource number */
403 uint32_t num_free; /* Total available resource number */
404 struct res_list alloc_list; /* Allocated resource list */
405 struct res_list free_list; /* Available resource list */
409 I40E_VF_INACTIVE = 0,
416 * Structure to store private data for PF host.
420 struct i40e_vsi *vsi;
421 enum I40E_VF_STATE state; /* The number of queue pairs available */
422 uint16_t vf_idx; /* VF index in pf->vfs */
423 uint16_t lan_nb_qps; /* Actual queues allocated */
424 uint16_t reset_cnt; /* Total vf reset times */
425 struct ether_addr mac_addr; /* Default MAC address */
426 /* version of the virtchnl from VF */
427 struct virtchnl_version_info version;
428 uint32_t request_caps; /* offload caps requested from VF */
432 * Structure to store private data for flow control.
434 struct i40e_fc_conf {
435 uint16_t pause_time; /* Flow control pause timer */
436 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
437 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
438 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
439 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
443 * Structure to store private data for VMDQ instance
445 struct i40e_vmdq_info {
447 struct i40e_vsi *vsi;
450 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
451 #define I40E_MAX_FLX_SOURCE_OFF 480
452 #define NONUSE_FLX_PIT_DEST_OFF 63
453 #define NONUSE_FLX_PIT_FSIZE 1
454 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
455 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
456 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
457 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
458 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
459 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
460 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
461 NONUSE_FLX_PIT_DEST_OFF : \
462 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
463 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
464 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
465 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
466 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
467 #define I40E_FDIR_IPv6_TC_OFFSET 20
469 /* A structure used to define the input for GTP flow */
470 struct i40e_gtp_flow {
471 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
472 uint8_t msg_type; /* Message type. */
473 uint32_t teid; /* TEID in big endian. */
476 /* A structure used to define the input for GTP IPV4 flow */
477 struct i40e_gtp_ipv4_flow {
478 struct i40e_gtp_flow gtp;
479 struct rte_eth_ipv4_flow ip4;
482 /* A structure used to define the input for GTP IPV6 flow */
483 struct i40e_gtp_ipv6_flow {
484 struct i40e_gtp_flow gtp;
485 struct rte_eth_ipv6_flow ip6;
488 /* A structure used to define the input for raw type flow */
489 struct i40e_raw_flow {
496 * A union contains the inputs for all types of flow
497 * items in flows need to be in big endian
499 union i40e_fdir_flow {
500 struct rte_eth_l2_flow l2_flow;
501 struct rte_eth_udpv4_flow udp4_flow;
502 struct rte_eth_tcpv4_flow tcp4_flow;
503 struct rte_eth_sctpv4_flow sctp4_flow;
504 struct rte_eth_ipv4_flow ip4_flow;
505 struct rte_eth_udpv6_flow udp6_flow;
506 struct rte_eth_tcpv6_flow tcp6_flow;
507 struct rte_eth_sctpv6_flow sctp6_flow;
508 struct rte_eth_ipv6_flow ipv6_flow;
509 struct i40e_gtp_flow gtp_flow;
510 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
511 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
512 struct i40e_raw_flow raw_flow;
515 enum i40e_fdir_ip_type {
516 I40E_FDIR_IPTYPE_IPV4,
517 I40E_FDIR_IPTYPE_IPV6,
520 /* A structure used to contain extend input of flow */
521 struct i40e_fdir_flow_ext {
523 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
524 /* It is filled by the flexible payload to match. */
525 uint8_t is_vf; /* 1 for VF, 0 for port dev */
526 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
527 bool inner_ip; /* If there is inner ip */
528 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
529 bool customized_pctype; /* If customized pctype is used */
530 bool pkt_template; /* If raw packet template is used */
533 /* A structure used to define the input for a flow director filter entry */
534 struct i40e_fdir_input {
535 enum i40e_filter_pctype pctype;
536 union i40e_fdir_flow flow;
537 /* Flow fields to match, dependent on flow_type */
538 struct i40e_fdir_flow_ext flow_ext;
539 /* Additional fields to match */
542 /* Behavior will be taken if FDIR match */
543 enum i40e_fdir_behavior {
544 I40E_FDIR_ACCEPT = 0,
549 /* Flow director report status
550 * It defines what will be reported if FDIR entry is matched.
552 enum i40e_fdir_status {
553 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
554 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
555 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
556 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
559 /* A structure used to define an action when match FDIR packet filter. */
560 struct i40e_fdir_action {
561 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
562 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
563 enum i40e_fdir_status report_status; /* Status report option */
564 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
565 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
566 * flex bytes start from in flexible payload.
571 /* A structure used to define the flow director filter entry by filter_ctrl API
572 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
573 * RTE_ETH_FILTER_DELETE operations.
575 struct i40e_fdir_filter_conf {
577 /* ID, an unique value is required when deal with FDIR entry */
578 struct i40e_fdir_input input; /* Input set */
579 struct i40e_fdir_action action; /* Action taken when match */
583 * Structure to store flex pit for flow diretor.
585 struct i40e_fdir_flex_pit {
586 uint8_t src_offset; /* offset in words from the beginning of payload */
587 uint8_t size; /* size in words */
588 uint8_t dst_offset; /* offset in words of flexible payload */
591 struct i40e_fdir_flex_mask {
592 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
597 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
600 #define I40E_FILTER_PCTYPE_INVALID 0
601 #define I40E_FILTER_PCTYPE_MAX 64
602 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
604 struct i40e_fdir_filter {
605 TAILQ_ENTRY(i40e_fdir_filter) rules;
606 struct i40e_fdir_filter_conf fdir;
609 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
611 * A structure used to define fields of a FDIR related info.
613 struct i40e_fdir_info {
614 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
615 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
616 struct i40e_tx_queue *txq;
617 struct i40e_rx_queue *rxq;
618 void *prg_pkt; /* memory for fdir program packet */
619 uint64_t dma_addr; /* physic address of packet memory*/
620 /* input set bits for each pctype */
621 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
623 * the rule how bytes stream is extracted as flexible payload
624 * for each payload layer, the setting can up to three elements
626 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
627 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
629 struct i40e_fdir_filter_list fdir_list;
630 struct i40e_fdir_filter **hash_map;
631 struct rte_hash *hash_table;
633 /* Mark if flex pit and mask is set */
634 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
635 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
637 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
640 /* Ethertype filter number HW supports */
641 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
643 /* Ethertype filter struct */
644 struct i40e_ethertype_filter_input {
645 struct ether_addr mac_addr; /* Mac address to match */
646 uint16_t ether_type; /* Ether type to match */
649 struct i40e_ethertype_filter {
650 TAILQ_ENTRY(i40e_ethertype_filter) rules;
651 struct i40e_ethertype_filter_input input;
652 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
653 uint16_t queue; /* Queue assigned to when match */
656 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
658 struct i40e_ethertype_rule {
659 struct i40e_ethertype_filter_list ethertype_list;
660 struct i40e_ethertype_filter **hash_map;
661 struct rte_hash *hash_table;
664 /* queue region info */
665 struct i40e_queue_region_info {
666 /* the region id for this configuration */
668 /* the start queue index for this region */
669 uint8_t queue_start_index;
670 /* the total queue number of this queue region */
672 /* the total number of user priority for this region */
673 uint8_t user_priority_num;
674 /* the packet's user priority for this region */
675 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
676 /* the total number of flowtype for this region */
677 uint8_t flowtype_num;
679 * the pctype or hardware flowtype of packet,
680 * the specific index for each type has been defined
681 * in file i40e_type.h as enum i40e_filter_pctype.
683 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
686 struct i40e_queue_regions {
687 /* the total number of queue region for this port */
688 uint16_t queue_region_number;
689 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
692 /* Tunnel filter number HW supports */
693 #define I40E_MAX_TUNNEL_FILTER_NUM 400
695 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
696 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
697 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
698 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
699 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
700 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
701 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
702 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
703 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
704 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
705 #define I40E_AQC_NEW_TR_21 21
706 #define I40E_AQC_NEW_TR_22 22
708 enum i40e_tunnel_iptype {
709 I40E_TUNNEL_IPTYPE_IPV4,
710 I40E_TUNNEL_IPTYPE_IPV6,
713 /* Tunnel filter struct */
714 struct i40e_tunnel_filter_input {
715 uint8_t outer_mac[6]; /* Outer mac address to match */
716 uint8_t inner_mac[6]; /* Inner mac address to match */
717 uint16_t inner_vlan; /* Inner vlan address to match */
718 enum i40e_tunnel_iptype ip_type;
719 uint16_t flags; /* Filter type flag */
720 uint32_t tenant_id; /* Tenant id to match */
721 uint16_t general_fields[32]; /* Big buffer */
724 struct i40e_tunnel_filter {
725 TAILQ_ENTRY(i40e_tunnel_filter) rules;
726 struct i40e_tunnel_filter_input input;
727 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
728 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
729 uint16_t queue; /* Queue assigned to when match */
732 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
734 struct i40e_tunnel_rule {
735 struct i40e_tunnel_filter_list tunnel_list;
736 struct i40e_tunnel_filter **hash_map;
737 struct rte_hash *hash_table;
743 enum i40e_tunnel_type {
744 I40E_TUNNEL_TYPE_NONE = 0,
745 I40E_TUNNEL_TYPE_VXLAN,
746 I40E_TUNNEL_TYPE_GENEVE,
747 I40E_TUNNEL_TYPE_TEREDO,
748 I40E_TUNNEL_TYPE_NVGRE,
749 I40E_TUNNEL_TYPE_IP_IN_GRE,
750 I40E_L2_TUNNEL_TYPE_E_TAG,
751 I40E_TUNNEL_TYPE_MPLSoUDP,
752 I40E_TUNNEL_TYPE_MPLSoGRE,
753 I40E_TUNNEL_TYPE_QINQ,
754 I40E_TUNNEL_TYPE_GTPC,
755 I40E_TUNNEL_TYPE_GTPU,
756 I40E_TUNNEL_TYPE_MAX,
760 * Tunneling Packet filter configuration.
762 struct i40e_tunnel_filter_conf {
763 struct ether_addr outer_mac; /**< Outer MAC address to match. */
764 struct ether_addr inner_mac; /**< Inner MAC address to match. */
765 uint16_t inner_vlan; /**< Inner VLAN to match. */
766 uint32_t outer_vlan; /**< Outer VLAN to match */
767 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
769 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
770 * is set in filter_type, or inner destination IP address to match
771 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
774 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
775 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
777 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
778 uint16_t filter_type;
779 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
780 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
781 uint16_t queue_id; /**< Queue assigned to if match. */
782 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
783 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
786 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
787 #define I40E_MAX_MIRROR_RULES 64
789 * Mirror rule structure
791 struct i40e_mirror_rule {
792 TAILQ_ENTRY(i40e_mirror_rule) rules;
794 uint16_t index; /* the sw index of mirror rule */
795 uint16_t id; /* the rule id assigned by firmware */
796 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
797 uint16_t num_entries;
798 /* the info stores depend on the rule type.
799 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
800 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
802 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
805 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
808 * Struct to store flow created.
811 TAILQ_ENTRY(rte_flow) node;
812 enum rte_filter_type filter_type;
816 TAILQ_HEAD(i40e_flow_list, rte_flow);
818 /* Struct to store Traffic Manager shaper profile. */
819 struct i40e_tm_shaper_profile {
820 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
821 uint32_t shaper_profile_id;
822 uint32_t reference_count;
823 struct rte_tm_shaper_params profile;
826 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
828 /* node type of Traffic Manager */
829 enum i40e_tm_node_type {
830 I40E_TM_NODE_TYPE_PORT,
831 I40E_TM_NODE_TYPE_TC,
832 I40E_TM_NODE_TYPE_QUEUE,
833 I40E_TM_NODE_TYPE_MAX,
836 /* Struct to store Traffic Manager node configuration. */
837 struct i40e_tm_node {
838 TAILQ_ENTRY(i40e_tm_node) node;
842 uint32_t reference_count;
843 struct i40e_tm_node *parent;
844 struct i40e_tm_shaper_profile *shaper_profile;
845 struct rte_tm_node_params params;
848 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
850 /* Struct to store all the Traffic Manager configuration. */
851 struct i40e_tm_conf {
852 struct i40e_shaper_profile_list shaper_profile_list;
853 struct i40e_tm_node *root; /* root node - port */
854 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
855 struct i40e_tm_node_list queue_list; /* node list for all the queues */
857 * The number of added TC nodes.
858 * It should be no more than the TC number of this port.
862 * The number of added queue nodes.
863 * It should be no more than the queue number of this port.
865 uint32_t nb_queue_node;
867 * This flag is used to check if APP can change the TM node
869 * When it's true, means the configuration is applied to HW,
870 * APP should not change the configuration.
871 * As we don't support on-the-fly configuration, when starting
872 * the port, APP should call the hierarchy_commit API to set this
873 * flag to true. When stopping the port, this flag should be set
879 enum i40e_new_pctype {
880 I40E_CUSTOMIZED_GTPC = 0,
881 I40E_CUSTOMIZED_GTPU_IPV4,
882 I40E_CUSTOMIZED_GTPU_IPV6,
883 I40E_CUSTOMIZED_GTPU,
887 #define I40E_FILTER_PCTYPE_INVALID 0
888 struct i40e_customized_pctype {
889 enum i40e_new_pctype index; /* Indicate which customized pctype */
890 uint8_t pctype; /* New pctype value */
891 bool valid; /* Check if it's valid */
894 struct i40e_rte_flow_rss_conf {
895 struct rte_flow_action_rss conf; /**< RSS parameters. */
896 uint16_t queue_region_conf; /**< Queue region config flag */
897 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
898 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
899 sizeof(uint32_t)]; /* Hash key. */
900 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
904 * Structure to store private data specific for PF instance.
907 struct i40e_adapter *adapter; /* The adapter this PF associate to */
908 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
909 uint16_t mac_seid; /* The seid of the MAC of this PF */
910 uint16_t main_vsi_seid; /* The seid of the main VSI */
911 uint16_t max_num_vsi;
912 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
913 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
915 struct i40e_hw_port_stats stats_offset;
916 struct i40e_hw_port_stats stats;
917 /* internal packet statistics, it should be excluded from the total */
918 struct i40e_eth_stats internal_stats_offset;
919 struct i40e_eth_stats internal_stats;
922 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
923 struct ether_addr dev_addr; /* PF device mac address */
924 uint64_t flags; /* PF feature flags */
925 /* All kinds of queue pair setting for different VSIs */
926 struct i40e_pf_vf *vfs;
928 /* Each of below queue pairs should be power of 2 since it's the
929 precondition after TC configuration applied */
930 uint16_t lan_nb_qp_max;
931 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
932 uint16_t lan_qp_offset;
933 uint16_t vmdq_nb_qp_max;
934 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
935 uint16_t vmdq_qp_offset;
936 uint16_t vf_nb_qp_max;
937 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
938 uint16_t vf_qp_offset;
939 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
940 uint16_t fdir_qp_offset;
942 uint16_t hash_lut_size; /* The size of hash lookup table */
943 /* input set bits for each pctype */
944 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
945 /* store VXLAN UDP ports */
946 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
947 uint16_t vxlan_bitmap; /* Vxlan bit mask */
949 /* VMDQ related info */
950 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
951 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
952 struct i40e_vmdq_info *vmdq;
954 struct i40e_fdir_info fdir; /* flow director info */
955 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
956 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
957 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
958 struct i40e_queue_regions queue_region; /* queue region info */
959 struct i40e_fc_conf fc_conf; /* Flow control conf */
960 struct i40e_mirror_rule_list mirror_list;
961 uint16_t nb_mirror_rule; /* The number of mirror rules */
962 bool floating_veb; /* The flag to use the floating VEB */
963 /* The floating enable flag for the specific VF */
964 bool floating_veb_list[I40E_MAX_VF];
965 struct i40e_flow_list flow_list;
966 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
967 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
968 bool qinq_replace_flag; /* QINQ filter replace is done */
969 struct i40e_tm_conf tm_conf;
970 bool support_multi_driver; /* 1 - support multiple driver */
972 /* Dynamic Device Personalization */
973 bool gtp_support; /* 1 - support GTP-C and GTP-U */
974 /* customer customized pctype */
975 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
976 /* Switch Domain Id */
977 uint16_t switch_domain_id;
981 PFMSG_LINK_CHANGE = 0x1,
982 PFMSG_RESET_IMPENDING = 0x2,
983 PFMSG_DRIVER_CLOSE = 0x4,
986 struct i40e_vsi_vlan_pvid_info {
987 uint16_t on; /* Enable or disable pvid */
989 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
991 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
992 * while 'untagged' will reject untagged packets.
1000 struct i40e_vf_rx_queues {
1001 uint64_t rx_dma_addr;
1002 uint32_t rx_ring_len;
1006 struct i40e_vf_tx_queues {
1007 uint64_t tx_dma_addr;
1008 uint32_t tx_ring_len;
1012 * Structure to store private data specific for VF instance.
1015 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1016 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1017 uint16_t num_queue_pairs;
1018 uint16_t max_pkt_len; /* Maximum packet length */
1019 bool promisc_unicast_enabled;
1020 bool promisc_multicast_enabled;
1022 uint32_t version_major; /* Major version number */
1023 uint32_t version_minor; /* Minor version number */
1024 uint16_t promisc_flags; /* Promiscuous setting */
1025 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1027 struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */
1028 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1033 enum virtchnl_link_speed link_speed;
1035 volatile uint32_t pend_cmd; /* pending command not finished yet */
1036 int32_t cmd_retval; /* return value of the cmd response from PF */
1037 u16 pend_msg; /* flags indicates events from pf not handled yet */
1038 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1041 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1042 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1043 struct i40e_vsi vsi;
1047 #define I40E_MAX_PKT_TYPE 256
1048 #define I40E_FLOW_TYPE_MAX 64
1051 * Structure to store private data for each PF/VF instance.
1053 struct i40e_adapter {
1054 /* Common for both PF and VF */
1056 struct rte_eth_dev *eth_dev;
1058 /* Specific for PF or VF */
1064 /* For vector PMD */
1065 bool rx_bulk_alloc_allowed;
1066 bool rx_vec_allowed;
1067 bool tx_simple_allowed;
1068 bool tx_vec_allowed;
1071 struct rte_timecounter systime_tc;
1072 struct rte_timecounter rx_tstamp_tc;
1073 struct rte_timecounter tx_tstamp_tc;
1075 /* ptype mapping table */
1076 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1077 /* flow type to pctype mapping table */
1078 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1079 uint64_t flow_types_mask;
1080 uint64_t pctypes_mask;
1083 uint8_t use_latest_vec;
1087 * Strucute to store private data for each VF representor instance
1089 struct i40e_vf_representor {
1090 uint16_t switch_domain_id;
1091 /**< Virtual Function ID */
1093 /**< Virtual Function ID */
1094 struct i40e_adapter *adapter;
1095 /**< Private data store of assocaiated physical function */
1096 struct i40e_eth_stats stats_offset;
1097 /**< Zero-point of VF statistics*/
1100 extern const struct rte_flow_ops i40e_flow_ops;
1102 union i40e_filter_t {
1103 struct rte_eth_ethertype_filter ethertype_filter;
1104 struct i40e_fdir_filter_conf fdir_filter;
1105 struct rte_eth_tunnel_filter_conf tunnel_filter;
1106 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1107 struct i40e_rte_flow_rss_conf rss_conf;
1110 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1111 const struct rte_flow_attr *attr,
1112 const struct rte_flow_item pattern[],
1113 const struct rte_flow_action actions[],
1114 struct rte_flow_error *error,
1115 union i40e_filter_t *filter);
1116 struct i40e_valid_pattern {
1117 enum rte_flow_item_type *items;
1118 parse_filter_t parse_filter;
1121 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1122 int i40e_vsi_release(struct i40e_vsi *vsi);
1123 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1124 enum i40e_vsi_type type,
1125 struct i40e_vsi *uplink_vsi,
1126 uint16_t user_param);
1127 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1128 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1129 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1130 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1131 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1132 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1133 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1134 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1135 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1136 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1137 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1138 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1139 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1140 struct i40e_vsi_vlan_pvid_info *info);
1141 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1142 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1143 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1144 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1145 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1146 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1147 int i40e_fdir_setup(struct i40e_pf *pf);
1148 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1151 int i40e_fdir_configure(struct rte_eth_dev *dev);
1152 void i40e_fdir_teardown(struct i40e_pf *pf);
1153 enum i40e_filter_pctype
1154 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1155 uint16_t flow_type);
1156 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1157 enum i40e_filter_pctype pctype);
1158 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1159 enum rte_filter_op filter_op,
1161 int i40e_select_filter_input_set(struct i40e_hw *hw,
1162 struct rte_eth_input_set_conf *conf,
1163 enum rte_filter_type filter);
1164 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1165 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1166 struct rte_eth_input_set_conf *conf);
1167 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1168 struct rte_eth_input_set_conf *conf);
1169 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1170 uint32_t retval, uint8_t *msg,
1172 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1173 struct rte_eth_rxq_info *qinfo);
1174 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1175 struct rte_eth_txq_info *qinfo);
1176 struct i40e_ethertype_filter *
1177 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1178 const struct i40e_ethertype_filter_input *input);
1179 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1180 struct i40e_ethertype_filter_input *input);
1181 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1182 struct i40e_fdir_input *input);
1183 struct i40e_tunnel_filter *
1184 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1185 const struct i40e_tunnel_filter_input *input);
1186 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1187 struct i40e_tunnel_filter_input *input);
1188 uint64_t i40e_get_default_input_set(uint16_t pctype);
1189 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1190 struct rte_eth_ethertype_filter *filter,
1192 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1193 const struct rte_eth_fdir_filter *filter,
1195 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1196 const struct i40e_fdir_filter_conf *filter,
1198 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1199 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1201 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1202 struct i40e_tunnel_filter_conf *tunnel_filter,
1204 int i40e_fdir_flush(struct rte_eth_dev *dev);
1205 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1206 struct i40e_macvlan_filter *mv_f,
1207 int num, struct ether_addr *addr);
1208 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1209 struct i40e_macvlan_filter *filter,
1211 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1212 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1213 struct i40e_macvlan_filter *filter,
1215 bool is_i40e_supported(struct rte_eth_dev *dev);
1217 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1218 enum rte_filter_type filter, uint64_t inset);
1219 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1221 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1222 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1223 void i40e_check_write_global_reg(struct i40e_hw *hw,
1224 uint32_t addr, uint32_t val);
1226 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1227 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1228 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1229 struct i40e_customized_pctype*
1230 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1231 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1233 enum rte_pmd_i40e_package_op op);
1234 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1235 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1236 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1237 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1238 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1239 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1240 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1241 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1242 const struct rte_flow_action_rss *in);
1243 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1244 const struct rte_flow_action_rss *with);
1245 int i40e_config_rss_filter(struct i40e_pf *pf,
1246 struct i40e_rte_flow_rss_conf *conf, bool add);
1247 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1248 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1250 #define I40E_DEV_TO_PCI(eth_dev) \
1251 RTE_DEV_TO_PCI((eth_dev)->device)
1253 /* I40E_DEV_PRIVATE_TO */
1254 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1255 (&((struct i40e_adapter *)adapter)->pf)
1256 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1257 (&((struct i40e_adapter *)adapter)->hw)
1258 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1259 ((struct i40e_adapter *)adapter)
1261 /* I40EVF_DEV_PRIVATE_TO */
1262 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1263 (&((struct i40e_adapter *)adapter)->vf)
1265 static inline struct i40e_vsi *
1266 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1273 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1274 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1275 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1279 return pf->main_vsi;
1282 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1283 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1286 #define I40E_VSI_TO_HW(vsi) \
1287 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1288 #define I40E_VSI_TO_PF(vsi) \
1289 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1290 #define I40E_VSI_TO_VF(vsi) \
1291 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1292 #define I40E_VSI_TO_DEV_DATA(vsi) \
1293 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1294 #define I40E_VSI_TO_ETH_DEV(vsi) \
1295 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1298 #define I40E_PF_TO_HW(pf) \
1299 (&(((struct i40e_pf *)pf)->adapter->hw))
1300 #define I40E_PF_TO_ADAPTER(pf) \
1301 ((struct i40e_adapter *)pf->adapter)
1304 #define I40E_VF_TO_HW(vf) \
1305 (&(((struct i40e_vf *)vf)->adapter->hw))
1308 i40e_init_adminq_parameter(struct i40e_hw *hw)
1310 hw->aq.num_arq_entries = I40E_AQ_LEN;
1311 hw->aq.num_asq_entries = I40E_AQ_LEN;
1312 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1313 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1317 i40e_align_floor(int n)
1321 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1324 static inline uint16_t
1325 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
1327 uint16_t interval = 0;
1330 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1333 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1335 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1338 /* Convert to hardware count, as writing each 1 represents 2 us */
1339 return interval / 2;
1342 #define I40E_VALID_FLOW(flow_type) \
1343 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1344 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1345 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1346 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1347 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1348 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1349 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1350 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1351 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1352 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1353 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1355 #define I40E_VALID_PCTYPE_X722(pctype) \
1356 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1357 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1358 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1359 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1360 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1361 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1362 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1363 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1364 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1365 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1366 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1367 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1368 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1369 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1370 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1371 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1372 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1374 #define I40E_VALID_PCTYPE(pctype) \
1375 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1376 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1377 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1378 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1379 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1380 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1381 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1382 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1383 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1384 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1385 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1387 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1388 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1389 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1390 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1391 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1392 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1393 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1395 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1396 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1397 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1398 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1399 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
1400 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
1401 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
1403 #endif /* _I40E_ETHDEV_H_ */