1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
11 #include <rte_kvargs.h>
14 #include <rte_flow_driver.h>
15 #include <rte_tm_driver.h>
16 #include "rte_pmd_i40e.h"
18 #include "base/i40e_register.h"
20 #define I40E_VLAN_TAG_SIZE 4
22 #define I40E_AQ_LEN 32
23 #define I40E_AQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define I40E_MAX_Q_PER_TC 64
26 #define I40E_NUM_DESC_DEFAULT 512
27 #define I40E_NUM_DESC_ALIGN 32
28 #define I40E_BUF_SIZE_MIN 1024
29 #define I40E_FRAME_SIZE_MAX 9728
30 #define I40E_TSO_FRAME_SIZE_MAX 262144
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
90 struct rte_eth_dev *dev; \
91 ori_val = I40E_READ_REG((hw), (reg)); \
92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
95 if (ori_val != value) \
96 PMD_DRV_LOG(WARNING, \
97 "i40e device %s changed global " \
98 "register [0x%08x]. original: 0x%08x, " \
100 (dev->device->name), (reg), \
101 (ori_val), (value)); \
104 /* index flex payload per layer */
105 enum i40e_flxpld_layer_idx {
106 I40E_FLXPLD_L2_IDX = 0,
107 I40E_FLXPLD_L3_IDX = 1,
108 I40E_FLXPLD_L4_IDX = 2,
109 I40E_MAX_FLXPLD_LAYER = 3,
111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
118 #define I40E_FLAG_RSS (1ULL << 0)
119 #define I40E_FLAG_DCB (1ULL << 1)
120 #define I40E_FLAG_VMDQ (1ULL << 2)
121 #define I40E_FLAG_SRIOV (1ULL << 3)
122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
124 #define I40E_FLAG_FDIR (1ULL << 6)
125 #define I40E_FLAG_VXLAN (1ULL << 7)
126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
127 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
128 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
132 I40E_FLAG_HEADER_SPLIT_DISABLED | \
133 I40E_FLAG_HEADER_SPLIT_ENABLED | \
136 I40E_FLAG_RSS_AQ_CAPABLE | \
137 I40E_FLAG_VF_MAC_BY_PF)
139 #define I40E_RSS_OFFLOAD_ALL ( \
140 ETH_RSS_FRAG_IPV4 | \
141 ETH_RSS_NONFRAG_IPV4_TCP | \
142 ETH_RSS_NONFRAG_IPV4_UDP | \
143 ETH_RSS_NONFRAG_IPV4_SCTP | \
144 ETH_RSS_NONFRAG_IPV4_OTHER | \
145 ETH_RSS_FRAG_IPV6 | \
146 ETH_RSS_NONFRAG_IPV6_TCP | \
147 ETH_RSS_NONFRAG_IPV6_UDP | \
148 ETH_RSS_NONFRAG_IPV6_SCTP | \
149 ETH_RSS_NONFRAG_IPV6_OTHER | \
152 /* All bits of RSS hash enable for X722*/
153 #define I40E_RSS_HENA_ALL_X722 ( \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
162 /* All bits of RSS hash enable */
163 #define I40E_RSS_HENA_ALL ( \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
168 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
175 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
177 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
179 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
180 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
182 /* Default queue interrupt throttling time in microseconds */
183 #define I40E_ITR_INDEX_DEFAULT 0
184 #define I40E_ITR_INDEX_NONE 3
185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
187 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
188 /* Special FW support this floating VEB feature */
189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
192 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
193 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
195 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
197 #define I40E_INSET_NONE 0x00000000000000000ULL
200 #define I40E_INSET_DMAC 0x0000000000000001ULL
201 #define I40E_INSET_SMAC 0x0000000000000002ULL
202 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
203 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
204 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
207 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
208 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
209 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
210 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
211 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
212 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
213 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
215 /* bit 16 ~ bit 31 */
216 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
217 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
218 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
219 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
220 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
221 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
222 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
223 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
225 /* bit 32 ~ bit 47, tunnel fields */
226 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
227 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
228 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
229 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
230 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
231 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
233 /* bit 48 ~ bit 55 */
234 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
236 /* bit 56 ~ bit 63, Flex Payload */
237 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
238 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD \
246 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
247 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
248 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
249 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
251 /* The max bandwidth of i40e is 40Gbps. */
252 #define I40E_QOS_BW_MAX 40000
253 /* The bandwidth should be the multiple of 50Mbps. */
254 #define I40E_QOS_BW_GRANULARITY 50
255 /* The min bandwidth weight is 1. */
256 #define I40E_QOS_BW_WEIGHT_MIN 1
257 /* The max bandwidth weight is 127. */
258 #define I40E_QOS_BW_WEIGHT_MAX 127
259 /* The max queue region index is 7. */
260 #define I40E_REGION_MAX_INDEX 7
262 #define I40E_MAX_PERCENT 100
263 #define I40E_DEFAULT_DCB_APP_NUM 1
264 #define I40E_DEFAULT_DCB_APP_PRIO 3
267 * The overhead from MTU to max frame size.
268 * Considering QinQ packet, the VLAN tag needs to be counted twice.
270 #define I40E_ETH_OVERHEAD \
271 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
274 struct rte_pci_driver;
277 * MAC filter structure
279 struct i40e_mac_filter_info {
280 enum rte_mac_filter_type filter_type;
281 struct rte_ether_addr mac_addr;
284 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
286 /* MAC filter list structure */
287 struct i40e_mac_filter {
288 TAILQ_ENTRY(i40e_mac_filter) next;
289 struct i40e_mac_filter_info mac_info;
292 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
296 /* VSI list structure */
297 struct i40e_vsi_list {
298 TAILQ_ENTRY(i40e_vsi_list) list;
299 struct i40e_vsi *vsi;
302 struct i40e_rx_queue;
303 struct i40e_tx_queue;
305 /* Bandwidth limit information */
306 struct i40e_bw_info {
307 uint16_t bw_limit; /* BW Limit (0 = disabled) */
308 uint8_t bw_max; /* Max BW limit if enabled */
310 /* Relative credits within same TC with respect to other VSIs or Comps */
311 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
312 /* Bandwidth limit per TC */
313 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
314 /* Max bandwidth limit per TC */
315 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
318 /* Structure that defines a VEB */
320 struct i40e_vsi_list_head head;
321 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
322 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
323 uint16_t seid; /* The seid of VEB itself */
324 uint16_t uplink_seid; /* The uplink seid of this VEB */
326 struct i40e_eth_stats stats;
327 uint8_t enabled_tc; /* The traffic class enabled */
328 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
329 struct i40e_bw_info bw_info; /* VEB bandwidth information */
332 /* i40e MACVLAN filter structure */
333 struct i40e_macvlan_filter {
334 struct rte_ether_addr macaddr;
335 enum rte_mac_filter_type filter_type;
340 * Structure that defines a VSI, associated with a adapter.
343 struct i40e_adapter *adapter; /* Backreference to associated adapter */
344 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
346 struct i40e_eth_stats eth_stats_offset;
347 struct i40e_eth_stats eth_stats;
349 * When drivers loaded, only a default main VSI exists. In case new VSI
350 * needs to add, HW needs to know the layout that VSIs are organized.
351 * Besides that, VSI isan element and can't switch packets, which needs
352 * to add new component VEB to perform switching. So, a new VSI needs
353 * to specify the uplink VSI (Parent VSI) before created. The
354 * uplink VSI will check whether it had a VEB to switch packets. If no,
355 * it will try to create one. Then, uplink VSI will move the new VSI
356 * into its' sib_vsi_list to manage all the downlink VSI.
357 * sib_vsi_list: the VSI list that shared the same uplink VSI.
358 * parent_vsi : the uplink VSI. It's NULL for main VSI.
359 * veb : the VEB associates with the VSI.
361 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
362 struct i40e_vsi *parent_vsi;
363 struct i40e_veb *veb; /* Associated veb, could be null */
364 struct i40e_veb *floating_veb; /* Associated floating veb */
366 enum i40e_vsi_type type; /* VSI types */
367 uint16_t vlan_num; /* Total VLAN number */
368 uint16_t mac_num; /* Total mac number */
369 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
370 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
371 /* specific VSI-defined parameters, SRIOV stored the vf_id */
373 uint16_t seid; /* The seid of VSI itself */
374 uint16_t uplink_seid; /* The uplink seid of this VSI */
375 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
376 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
377 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
378 uint16_t base_queue; /* The first queue index of this VSI */
380 * The offset to visit VSI related register, assigned by HW when
384 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
385 uint16_t nb_msix; /* The max number of msix vector */
386 uint8_t enabled_tc; /* The traffic class enabled */
387 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
388 uint8_t vlan_filter_on; /* The VLAN filter enabled */
389 struct i40e_bw_info bw_info; /* VSI bandwidth information */
393 LIST_ENTRY(pool_entry) next;
398 LIST_HEAD(res_list, pool_entry);
400 struct i40e_res_pool_info {
401 uint32_t base; /* Resource start index */
402 uint32_t num_alloc; /* Allocated resource number */
403 uint32_t num_free; /* Total available resource number */
404 struct res_list alloc_list; /* Allocated resource list */
405 struct res_list free_list; /* Available resource list */
409 I40E_VF_INACTIVE = 0,
416 * Structure to store private data for PF host.
420 struct i40e_vsi *vsi;
421 enum I40E_VF_STATE state; /* The number of queue pairs available */
422 uint16_t vf_idx; /* VF index in pf->vfs */
423 uint16_t lan_nb_qps; /* Actual queues allocated */
424 uint16_t reset_cnt; /* Total vf reset times */
425 struct rte_ether_addr mac_addr; /* Default MAC address */
426 /* version of the virtchnl from VF */
427 struct virtchnl_version_info version;
428 uint32_t request_caps; /* offload caps requested from VF */
431 * Variables for store the arrival timestamp of VF messages.
432 * If the timestamp of latest message stored at
433 * `msg_timestamps[index % max]` then the timestamp of
434 * earliest message stored at `msg_time[(index + 1) % max]`.
435 * When a new message come, the timestamp of this message
436 * will be stored at `msg_timestamps[(index + 1) % max]` and the
437 * earliest message timestamp is at
438 * `msg_timestamps[(index + 2) % max]` now...
441 uint64_t *msg_timestamps;
443 /* cycle of stop ignoring VF message */
444 uint64_t ignore_end_cycle;
448 * Structure to store private data for flow control.
450 struct i40e_fc_conf {
451 uint16_t pause_time; /* Flow control pause timer */
452 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
453 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
454 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
455 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
459 * Structure to store private data for VMDQ instance
461 struct i40e_vmdq_info {
463 struct i40e_vsi *vsi;
466 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
467 #define I40E_MAX_FLX_SOURCE_OFF 480
468 #define NONUSE_FLX_PIT_DEST_OFF 63
469 #define NONUSE_FLX_PIT_FSIZE 1
470 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
471 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
472 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
473 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
474 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
475 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
476 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
477 NONUSE_FLX_PIT_DEST_OFF : \
478 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
479 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
480 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
481 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
482 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
483 #define I40E_FDIR_IPv6_TC_OFFSET 20
485 /* A structure used to define the input for GTP flow */
486 struct i40e_gtp_flow {
487 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
488 uint8_t msg_type; /* Message type. */
489 uint32_t teid; /* TEID in big endian. */
492 /* A structure used to define the input for GTP IPV4 flow */
493 struct i40e_gtp_ipv4_flow {
494 struct i40e_gtp_flow gtp;
495 struct rte_eth_ipv4_flow ip4;
498 /* A structure used to define the input for GTP IPV6 flow */
499 struct i40e_gtp_ipv6_flow {
500 struct i40e_gtp_flow gtp;
501 struct rte_eth_ipv6_flow ip6;
504 /* A structure used to define the input for raw type flow */
505 struct i40e_raw_flow {
512 * A union contains the inputs for all types of flow
513 * items in flows need to be in big endian
515 union i40e_fdir_flow {
516 struct rte_eth_l2_flow l2_flow;
517 struct rte_eth_udpv4_flow udp4_flow;
518 struct rte_eth_tcpv4_flow tcp4_flow;
519 struct rte_eth_sctpv4_flow sctp4_flow;
520 struct rte_eth_ipv4_flow ip4_flow;
521 struct rte_eth_udpv6_flow udp6_flow;
522 struct rte_eth_tcpv6_flow tcp6_flow;
523 struct rte_eth_sctpv6_flow sctp6_flow;
524 struct rte_eth_ipv6_flow ipv6_flow;
525 struct i40e_gtp_flow gtp_flow;
526 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
527 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
528 struct i40e_raw_flow raw_flow;
531 enum i40e_fdir_ip_type {
532 I40E_FDIR_IPTYPE_IPV4,
533 I40E_FDIR_IPTYPE_IPV6,
536 /* A structure used to contain extend input of flow */
537 struct i40e_fdir_flow_ext {
539 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
540 /* It is filled by the flexible payload to match. */
541 uint8_t is_vf; /* 1 for VF, 0 for port dev */
542 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
543 bool inner_ip; /* If there is inner ip */
544 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
545 bool customized_pctype; /* If customized pctype is used */
546 bool pkt_template; /* If raw packet template is used */
549 /* A structure used to define the input for a flow director filter entry */
550 struct i40e_fdir_input {
551 enum i40e_filter_pctype pctype;
552 union i40e_fdir_flow flow;
553 /* Flow fields to match, dependent on flow_type */
554 struct i40e_fdir_flow_ext flow_ext;
555 /* Additional fields to match */
558 /* Behavior will be taken if FDIR match */
559 enum i40e_fdir_behavior {
560 I40E_FDIR_ACCEPT = 0,
565 /* Flow director report status
566 * It defines what will be reported if FDIR entry is matched.
568 enum i40e_fdir_status {
569 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
570 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
571 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
572 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
575 /* A structure used to define an action when match FDIR packet filter. */
576 struct i40e_fdir_action {
577 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
578 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
579 enum i40e_fdir_status report_status; /* Status report option */
580 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
581 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
582 * flex bytes start from in flexible payload.
587 /* A structure used to define the flow director filter entry by filter_ctrl API
588 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
589 * RTE_ETH_FILTER_DELETE operations.
591 struct i40e_fdir_filter_conf {
593 /* ID, an unique value is required when deal with FDIR entry */
594 struct i40e_fdir_input input; /* Input set */
595 struct i40e_fdir_action action; /* Action taken when match */
599 * Structure to store flex pit for flow diretor.
601 struct i40e_fdir_flex_pit {
602 uint8_t src_offset; /* offset in words from the beginning of payload */
603 uint8_t size; /* size in words */
604 uint8_t dst_offset; /* offset in words of flexible payload */
607 struct i40e_fdir_flex_mask {
608 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
613 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
616 #define I40E_FILTER_PCTYPE_INVALID 0
617 #define I40E_FILTER_PCTYPE_MAX 64
618 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
620 struct i40e_fdir_filter {
621 TAILQ_ENTRY(i40e_fdir_filter) rules;
622 struct i40e_fdir_filter_conf fdir;
625 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
627 * A structure used to define fields of a FDIR related info.
629 struct i40e_fdir_info {
630 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
631 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
632 struct i40e_tx_queue *txq;
633 struct i40e_rx_queue *rxq;
634 void *prg_pkt; /* memory for fdir program packet */
635 uint64_t dma_addr; /* physic address of packet memory*/
636 /* input set bits for each pctype */
637 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
639 * the rule how bytes stream is extracted as flexible payload
640 * for each payload layer, the setting can up to three elements
642 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
643 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
645 struct i40e_fdir_filter_list fdir_list;
646 struct i40e_fdir_filter **hash_map;
647 struct rte_hash *hash_table;
649 /* Mark if flex pit and mask is set */
650 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
651 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
653 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
656 /* Ethertype filter number HW supports */
657 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
659 /* Ethertype filter struct */
660 struct i40e_ethertype_filter_input {
661 struct rte_ether_addr mac_addr; /* Mac address to match */
662 uint16_t ether_type; /* Ether type to match */
665 struct i40e_ethertype_filter {
666 TAILQ_ENTRY(i40e_ethertype_filter) rules;
667 struct i40e_ethertype_filter_input input;
668 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
669 uint16_t queue; /* Queue assigned to when match */
672 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
674 struct i40e_ethertype_rule {
675 struct i40e_ethertype_filter_list ethertype_list;
676 struct i40e_ethertype_filter **hash_map;
677 struct rte_hash *hash_table;
680 /* queue region info */
681 struct i40e_queue_region_info {
682 /* the region id for this configuration */
684 /* the start queue index for this region */
685 uint8_t queue_start_index;
686 /* the total queue number of this queue region */
688 /* the total number of user priority for this region */
689 uint8_t user_priority_num;
690 /* the packet's user priority for this region */
691 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
692 /* the total number of flowtype for this region */
693 uint8_t flowtype_num;
695 * the pctype or hardware flowtype of packet,
696 * the specific index for each type has been defined
697 * in file i40e_type.h as enum i40e_filter_pctype.
699 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
702 struct i40e_queue_regions {
703 /* the total number of queue region for this port */
704 uint16_t queue_region_number;
705 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
708 /* Tunnel filter number HW supports */
709 #define I40E_MAX_TUNNEL_FILTER_NUM 400
711 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
712 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
713 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
714 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
715 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
716 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
717 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
718 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
719 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
720 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
721 #define I40E_AQC_NEW_TR_21 21
722 #define I40E_AQC_NEW_TR_22 22
724 enum i40e_tunnel_iptype {
725 I40E_TUNNEL_IPTYPE_IPV4,
726 I40E_TUNNEL_IPTYPE_IPV6,
729 /* Tunnel filter struct */
730 struct i40e_tunnel_filter_input {
731 uint8_t outer_mac[6]; /* Outer mac address to match */
732 uint8_t inner_mac[6]; /* Inner mac address to match */
733 uint16_t inner_vlan; /* Inner vlan address to match */
734 enum i40e_tunnel_iptype ip_type;
735 uint16_t flags; /* Filter type flag */
736 uint32_t tenant_id; /* Tenant id to match */
737 uint16_t general_fields[32]; /* Big buffer */
740 struct i40e_tunnel_filter {
741 TAILQ_ENTRY(i40e_tunnel_filter) rules;
742 struct i40e_tunnel_filter_input input;
743 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
744 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
745 uint16_t queue; /* Queue assigned to when match */
748 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
750 struct i40e_tunnel_rule {
751 struct i40e_tunnel_filter_list tunnel_list;
752 struct i40e_tunnel_filter **hash_map;
753 struct rte_hash *hash_table;
759 enum i40e_tunnel_type {
760 I40E_TUNNEL_TYPE_NONE = 0,
761 I40E_TUNNEL_TYPE_VXLAN,
762 I40E_TUNNEL_TYPE_GENEVE,
763 I40E_TUNNEL_TYPE_TEREDO,
764 I40E_TUNNEL_TYPE_NVGRE,
765 I40E_TUNNEL_TYPE_IP_IN_GRE,
766 I40E_L2_TUNNEL_TYPE_E_TAG,
767 I40E_TUNNEL_TYPE_MPLSoUDP,
768 I40E_TUNNEL_TYPE_MPLSoGRE,
769 I40E_TUNNEL_TYPE_QINQ,
770 I40E_TUNNEL_TYPE_GTPC,
771 I40E_TUNNEL_TYPE_GTPU,
772 I40E_TUNNEL_TYPE_MAX,
776 * Tunneling Packet filter configuration.
778 struct i40e_tunnel_filter_conf {
779 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */
780 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */
781 uint16_t inner_vlan; /**< Inner VLAN to match. */
782 uint32_t outer_vlan; /**< Outer VLAN to match */
783 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
785 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
786 * is set in filter_type, or inner destination IP address to match
787 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
790 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
791 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
793 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
794 uint16_t filter_type;
795 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
796 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
797 uint16_t queue_id; /**< Queue assigned to if match. */
798 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
799 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
802 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
803 #define I40E_MAX_MIRROR_RULES 64
805 * Mirror rule structure
807 struct i40e_mirror_rule {
808 TAILQ_ENTRY(i40e_mirror_rule) rules;
810 uint16_t index; /* the sw index of mirror rule */
811 uint16_t id; /* the rule id assigned by firmware */
812 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
813 uint16_t num_entries;
814 /* the info stores depend on the rule type.
815 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
816 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
818 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
821 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
824 * Struct to store flow created.
827 TAILQ_ENTRY(rte_flow) node;
828 enum rte_filter_type filter_type;
832 TAILQ_HEAD(i40e_flow_list, rte_flow);
834 /* Struct to store Traffic Manager shaper profile. */
835 struct i40e_tm_shaper_profile {
836 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
837 uint32_t shaper_profile_id;
838 uint32_t reference_count;
839 struct rte_tm_shaper_params profile;
842 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
844 /* node type of Traffic Manager */
845 enum i40e_tm_node_type {
846 I40E_TM_NODE_TYPE_PORT,
847 I40E_TM_NODE_TYPE_TC,
848 I40E_TM_NODE_TYPE_QUEUE,
849 I40E_TM_NODE_TYPE_MAX,
852 /* Struct to store Traffic Manager node configuration. */
853 struct i40e_tm_node {
854 TAILQ_ENTRY(i40e_tm_node) node;
858 uint32_t reference_count;
859 struct i40e_tm_node *parent;
860 struct i40e_tm_shaper_profile *shaper_profile;
861 struct rte_tm_node_params params;
864 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
866 /* Struct to store all the Traffic Manager configuration. */
867 struct i40e_tm_conf {
868 struct i40e_shaper_profile_list shaper_profile_list;
869 struct i40e_tm_node *root; /* root node - port */
870 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
871 struct i40e_tm_node_list queue_list; /* node list for all the queues */
873 * The number of added TC nodes.
874 * It should be no more than the TC number of this port.
878 * The number of added queue nodes.
879 * It should be no more than the queue number of this port.
881 uint32_t nb_queue_node;
883 * This flag is used to check if APP can change the TM node
885 * When it's true, means the configuration is applied to HW,
886 * APP should not change the configuration.
887 * As we don't support on-the-fly configuration, when starting
888 * the port, APP should call the hierarchy_commit API to set this
889 * flag to true. When stopping the port, this flag should be set
895 enum i40e_new_pctype {
896 I40E_CUSTOMIZED_GTPC = 0,
897 I40E_CUSTOMIZED_GTPU_IPV4,
898 I40E_CUSTOMIZED_GTPU_IPV6,
899 I40E_CUSTOMIZED_GTPU,
903 #define I40E_FILTER_PCTYPE_INVALID 0
904 struct i40e_customized_pctype {
905 enum i40e_new_pctype index; /* Indicate which customized pctype */
906 uint8_t pctype; /* New pctype value */
907 bool valid; /* Check if it's valid */
910 struct i40e_rte_flow_rss_conf {
911 struct rte_flow_action_rss conf; /**< RSS parameters. */
912 uint16_t queue_region_conf; /**< Queue region config flag */
913 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
914 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
915 sizeof(uint32_t)]; /* Hash key. */
916 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
919 struct i40e_vf_msg_cfg {
920 /* maximal VF message during a statistic period */
923 /* statistic period, in second */
926 * If message statistics from a VF exceed the maximal limitation,
927 * the PF will ignore any new message from that VF for
928 * 'ignor_second' time.
930 uint32_t ignore_second;
934 * Structure to store private data specific for PF instance.
937 struct i40e_adapter *adapter; /* The adapter this PF associate to */
938 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
939 uint16_t mac_seid; /* The seid of the MAC of this PF */
940 uint16_t main_vsi_seid; /* The seid of the main VSI */
941 uint16_t max_num_vsi;
942 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
943 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
945 struct i40e_hw_port_stats stats_offset;
946 struct i40e_hw_port_stats stats;
947 /* internal packet statistics, it should be excluded from the total */
948 struct i40e_eth_stats internal_stats_offset;
949 struct i40e_eth_stats internal_stats;
952 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
953 struct rte_ether_addr dev_addr; /* PF device mac address */
954 uint64_t flags; /* PF feature flags */
955 /* All kinds of queue pair setting for different VSIs */
956 struct i40e_pf_vf *vfs;
958 /* Each of below queue pairs should be power of 2 since it's the
959 precondition after TC configuration applied */
960 uint16_t lan_nb_qp_max;
961 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
962 uint16_t lan_qp_offset;
963 uint16_t vmdq_nb_qp_max;
964 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
965 uint16_t vmdq_qp_offset;
966 uint16_t vf_nb_qp_max;
967 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
968 uint16_t vf_qp_offset;
969 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
970 uint16_t fdir_qp_offset;
972 uint16_t hash_lut_size; /* The size of hash lookup table */
973 /* input set bits for each pctype */
974 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
975 /* store VXLAN UDP ports */
976 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
977 uint16_t vxlan_bitmap; /* Vxlan bit mask */
979 /* VMDQ related info */
980 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
981 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
982 struct i40e_vmdq_info *vmdq;
984 struct i40e_fdir_info fdir; /* flow director info */
985 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
986 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
987 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
988 struct i40e_queue_regions queue_region; /* queue region info */
989 struct i40e_fc_conf fc_conf; /* Flow control conf */
990 struct i40e_mirror_rule_list mirror_list;
991 uint16_t nb_mirror_rule; /* The number of mirror rules */
992 bool floating_veb; /* The flag to use the floating VEB */
993 /* The floating enable flag for the specific VF */
994 bool floating_veb_list[I40E_MAX_VF];
995 struct i40e_flow_list flow_list;
996 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
997 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
998 bool qinq_replace_flag; /* QINQ filter replace is done */
999 struct i40e_tm_conf tm_conf;
1000 bool support_multi_driver; /* 1 - support multiple driver */
1002 /* Dynamic Device Personalization */
1003 bool gtp_support; /* 1 - support GTP-C and GTP-U */
1004 /* customer customized pctype */
1005 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
1006 /* Switch Domain Id */
1007 uint16_t switch_domain_id;
1009 struct i40e_vf_msg_cfg vf_msg_cfg;
1013 PFMSG_LINK_CHANGE = 0x1,
1014 PFMSG_RESET_IMPENDING = 0x2,
1015 PFMSG_DRIVER_CLOSE = 0x4,
1018 struct i40e_vsi_vlan_pvid_info {
1019 uint16_t on; /* Enable or disable pvid */
1021 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
1023 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
1024 * while 'untagged' will reject untagged packets.
1032 struct i40e_vf_rx_queues {
1033 uint64_t rx_dma_addr;
1034 uint32_t rx_ring_len;
1038 struct i40e_vf_tx_queues {
1039 uint64_t tx_dma_addr;
1040 uint32_t tx_ring_len;
1044 * Structure to store private data specific for VF instance.
1047 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1048 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1049 uint16_t num_queue_pairs;
1050 uint16_t max_pkt_len; /* Maximum packet length */
1051 bool promisc_unicast_enabled;
1052 bool promisc_multicast_enabled;
1054 uint32_t version_major; /* Major version number */
1055 uint32_t version_minor; /* Minor version number */
1056 uint16_t promisc_flags; /* Promiscuous setting */
1057 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1059 /* Multicast addrs */
1060 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX];
1061 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1066 enum virtchnl_link_speed link_speed;
1068 volatile uint32_t pend_cmd; /* pending command not finished yet */
1069 int32_t cmd_retval; /* return value of the cmd response from PF */
1070 u16 pend_msg; /* flags indicates events from pf not handled yet */
1071 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1074 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1075 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1076 struct i40e_vsi vsi;
1080 #define I40E_MAX_PKT_TYPE 256
1081 #define I40E_FLOW_TYPE_MAX 64
1084 * Structure to store private data for each PF/VF instance.
1086 struct i40e_adapter {
1087 /* Common for both PF and VF */
1089 struct rte_eth_dev *eth_dev;
1091 /* Specific for PF or VF */
1097 /* For vector PMD */
1098 bool rx_bulk_alloc_allowed;
1099 bool rx_vec_allowed;
1100 bool tx_simple_allowed;
1101 bool tx_vec_allowed;
1104 struct rte_timecounter systime_tc;
1105 struct rte_timecounter rx_tstamp_tc;
1106 struct rte_timecounter tx_tstamp_tc;
1108 /* ptype mapping table */
1109 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1110 /* flow type to pctype mapping table */
1111 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1112 uint64_t flow_types_mask;
1113 uint64_t pctypes_mask;
1116 uint8_t use_latest_vec;
1118 /* For RSS reta table update */
1119 uint8_t rss_reta_updated;
1123 * Strucute to store private data for each VF representor instance
1125 struct i40e_vf_representor {
1126 uint16_t switch_domain_id;
1127 /**< Virtual Function ID */
1129 /**< Virtual Function ID */
1130 struct i40e_adapter *adapter;
1131 /**< Private data store of assocaiated physical function */
1132 struct i40e_eth_stats stats_offset;
1133 /**< Zero-point of VF statistics*/
1136 extern const struct rte_flow_ops i40e_flow_ops;
1138 union i40e_filter_t {
1139 struct rte_eth_ethertype_filter ethertype_filter;
1140 struct i40e_fdir_filter_conf fdir_filter;
1141 struct rte_eth_tunnel_filter_conf tunnel_filter;
1142 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1143 struct i40e_rte_flow_rss_conf rss_conf;
1146 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1147 const struct rte_flow_attr *attr,
1148 const struct rte_flow_item pattern[],
1149 const struct rte_flow_action actions[],
1150 struct rte_flow_error *error,
1151 union i40e_filter_t *filter);
1152 struct i40e_valid_pattern {
1153 enum rte_flow_item_type *items;
1154 parse_filter_t parse_filter;
1157 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1158 int i40e_vsi_release(struct i40e_vsi *vsi);
1159 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1160 enum i40e_vsi_type type,
1161 struct i40e_vsi *uplink_vsi,
1162 uint16_t user_param);
1163 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1164 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1165 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1166 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1167 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1168 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr);
1169 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1170 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1171 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1172 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1173 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1174 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1175 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1176 struct i40e_vsi_vlan_pvid_info *info);
1177 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1178 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1179 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1180 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1181 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1182 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1183 int i40e_fdir_setup(struct i40e_pf *pf);
1184 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1187 int i40e_fdir_configure(struct rte_eth_dev *dev);
1188 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on);
1189 void i40e_fdir_teardown(struct i40e_pf *pf);
1190 enum i40e_filter_pctype
1191 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1192 uint16_t flow_type);
1193 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1194 enum i40e_filter_pctype pctype);
1195 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1196 enum rte_filter_op filter_op,
1198 int i40e_select_filter_input_set(struct i40e_hw *hw,
1199 struct rte_eth_input_set_conf *conf,
1200 enum rte_filter_type filter);
1201 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1202 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1203 struct rte_eth_input_set_conf *conf);
1204 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1205 struct rte_eth_input_set_conf *conf);
1206 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1207 uint32_t retval, uint8_t *msg,
1209 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1210 struct rte_eth_rxq_info *qinfo);
1211 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1212 struct rte_eth_txq_info *qinfo);
1213 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1214 struct rte_eth_burst_mode *mode);
1215 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1216 struct rte_eth_burst_mode *mode);
1217 struct i40e_ethertype_filter *
1218 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1219 const struct i40e_ethertype_filter_input *input);
1220 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1221 struct i40e_ethertype_filter_input *input);
1222 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1223 struct i40e_fdir_input *input);
1224 struct i40e_tunnel_filter *
1225 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1226 const struct i40e_tunnel_filter_input *input);
1227 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1228 struct i40e_tunnel_filter_input *input);
1229 uint64_t i40e_get_default_input_set(uint16_t pctype);
1230 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1231 struct rte_eth_ethertype_filter *filter,
1233 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1234 const struct rte_eth_fdir_filter *filter,
1236 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1237 const struct i40e_fdir_filter_conf *filter,
1239 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1240 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1242 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1243 struct i40e_tunnel_filter_conf *tunnel_filter,
1245 int i40e_fdir_flush(struct rte_eth_dev *dev);
1246 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1247 struct i40e_macvlan_filter *mv_f,
1248 int num, struct rte_ether_addr *addr);
1249 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1250 struct i40e_macvlan_filter *filter,
1252 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1253 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1254 struct i40e_macvlan_filter *filter,
1256 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv);
1257 bool is_i40e_supported(struct rte_eth_dev *dev);
1258 bool is_i40evf_supported(struct rte_eth_dev *dev);
1260 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1261 enum rte_filter_type filter, uint64_t inset);
1262 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1264 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1265 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1266 void i40e_check_write_global_reg(struct i40e_hw *hw,
1267 uint32_t addr, uint32_t val);
1269 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1270 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1271 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1272 struct i40e_customized_pctype*
1273 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1274 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1276 enum rte_pmd_i40e_package_op op);
1277 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1278 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1279 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1280 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1281 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1282 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1283 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1284 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1285 const struct rte_flow_action_rss *in);
1286 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1287 const struct rte_flow_action_rss *with);
1288 int i40e_config_rss_filter(struct i40e_pf *pf,
1289 struct i40e_rte_flow_rss_conf *conf, bool add);
1290 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1291 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1293 #define I40E_DEV_TO_PCI(eth_dev) \
1294 RTE_DEV_TO_PCI((eth_dev)->device)
1296 /* I40E_DEV_PRIVATE_TO */
1297 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1298 (&((struct i40e_adapter *)adapter)->pf)
1299 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1300 (&((struct i40e_adapter *)adapter)->hw)
1301 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1302 ((struct i40e_adapter *)adapter)
1304 /* I40EVF_DEV_PRIVATE_TO */
1305 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1306 (&((struct i40e_adapter *)adapter)->vf)
1308 static inline struct i40e_vsi *
1309 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1316 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1317 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1318 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1322 return pf->main_vsi;
1325 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1326 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1329 #define I40E_VSI_TO_HW(vsi) \
1330 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1331 #define I40E_VSI_TO_PF(vsi) \
1332 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1333 #define I40E_VSI_TO_VF(vsi) \
1334 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1335 #define I40E_VSI_TO_DEV_DATA(vsi) \
1336 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1337 #define I40E_VSI_TO_ETH_DEV(vsi) \
1338 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1341 #define I40E_PF_TO_HW(pf) \
1342 (&(((struct i40e_pf *)pf)->adapter->hw))
1343 #define I40E_PF_TO_ADAPTER(pf) \
1344 ((struct i40e_adapter *)pf->adapter)
1347 #define I40E_VF_TO_HW(vf) \
1348 (&(((struct i40e_vf *)vf)->adapter->hw))
1351 i40e_init_adminq_parameter(struct i40e_hw *hw)
1353 hw->aq.num_arq_entries = I40E_AQ_LEN;
1354 hw->aq.num_asq_entries = I40E_AQ_LEN;
1355 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1356 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1360 i40e_align_floor(int n)
1364 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1367 static inline uint16_t
1368 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
1370 uint16_t interval = 0;
1373 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1376 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1378 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1381 /* Convert to hardware count, as writing each 1 represents 2 us */
1382 return interval / 2;
1385 #define I40E_VALID_FLOW(flow_type) \
1386 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1387 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1388 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1389 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1390 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1391 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1392 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1393 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1394 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1395 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1396 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1398 #define I40E_VALID_PCTYPE_X722(pctype) \
1399 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1400 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1401 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1402 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1403 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1404 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1405 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1406 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1407 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1408 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1409 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1410 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1411 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1412 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1413 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1414 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1415 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1417 #define I40E_VALID_PCTYPE(pctype) \
1418 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1419 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1420 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1421 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1422 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1423 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1424 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1425 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1426 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1427 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1428 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1430 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1431 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1432 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1433 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1434 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1435 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1436 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1438 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1439 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1440 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1441 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1442 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
1443 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
1444 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
1446 #endif /* _I40E_ETHDEV_H_ */