1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
10 #include <rte_eth_ctrl.h>
12 #include <rte_kvargs.h>
15 #include <rte_flow_driver.h>
16 #include <rte_tm_driver.h>
17 #include "rte_pmd_i40e.h"
19 #include "base/i40e_register.h"
21 #define I40E_VLAN_TAG_SIZE 4
23 #define I40E_AQ_LEN 32
24 #define I40E_AQ_BUF_SZ 4096
25 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
26 #define I40E_MAX_Q_PER_TC 64
27 #define I40E_NUM_DESC_DEFAULT 512
28 #define I40E_NUM_DESC_ALIGN 32
29 #define I40E_BUF_SIZE_MIN 1024
30 #define I40E_FRAME_SIZE_MAX 9728
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
90 struct rte_eth_dev *dev; \
91 ori_val = I40E_READ_REG((hw), (reg)); \
92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
95 if (ori_val != value) \
96 PMD_DRV_LOG(WARNING, \
97 "i40e device %s changed global " \
98 "register [0x%08x]. original: 0x%08x, " \
100 (dev->device->name), (reg), \
101 (ori_val), (value)); \
104 /* index flex payload per layer */
105 enum i40e_flxpld_layer_idx {
106 I40E_FLXPLD_L2_IDX = 0,
107 I40E_FLXPLD_L3_IDX = 1,
108 I40E_FLXPLD_L4_IDX = 2,
109 I40E_MAX_FLXPLD_LAYER = 3,
111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
118 #define I40E_FLAG_RSS (1ULL << 0)
119 #define I40E_FLAG_DCB (1ULL << 1)
120 #define I40E_FLAG_VMDQ (1ULL << 2)
121 #define I40E_FLAG_SRIOV (1ULL << 3)
122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
124 #define I40E_FLAG_FDIR (1ULL << 6)
125 #define I40E_FLAG_VXLAN (1ULL << 7)
126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
127 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
128 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
132 I40E_FLAG_HEADER_SPLIT_DISABLED | \
133 I40E_FLAG_HEADER_SPLIT_ENABLED | \
136 I40E_FLAG_RSS_AQ_CAPABLE | \
137 I40E_FLAG_VF_MAC_BY_PF)
139 #define I40E_RSS_OFFLOAD_ALL ( \
140 ETH_RSS_FRAG_IPV4 | \
141 ETH_RSS_NONFRAG_IPV4_TCP | \
142 ETH_RSS_NONFRAG_IPV4_UDP | \
143 ETH_RSS_NONFRAG_IPV4_SCTP | \
144 ETH_RSS_NONFRAG_IPV4_OTHER | \
145 ETH_RSS_FRAG_IPV6 | \
146 ETH_RSS_NONFRAG_IPV6_TCP | \
147 ETH_RSS_NONFRAG_IPV6_UDP | \
148 ETH_RSS_NONFRAG_IPV6_SCTP | \
149 ETH_RSS_NONFRAG_IPV6_OTHER | \
152 /* All bits of RSS hash enable for X722*/
153 #define I40E_RSS_HENA_ALL_X722 ( \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
162 /* All bits of RSS hash enable */
163 #define I40E_RSS_HENA_ALL ( \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
168 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
175 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
177 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
179 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
180 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
182 /* Default queue interrupt throttling time in microseconds */
183 #define I40E_ITR_INDEX_DEFAULT 0
184 #define I40E_ITR_INDEX_NONE 3
185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
187 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */
188 /* Special FW support this floating VEB feature */
189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
192 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
193 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
195 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
197 #define I40E_INSET_NONE 0x00000000000000000ULL
200 #define I40E_INSET_DMAC 0x0000000000000001ULL
201 #define I40E_INSET_SMAC 0x0000000000000002ULL
202 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
203 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
204 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
207 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
208 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
209 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
210 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
211 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
212 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
213 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
215 /* bit 16 ~ bit 31 */
216 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
217 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
218 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
219 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
220 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
221 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
222 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
223 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
225 /* bit 32 ~ bit 47, tunnel fields */
226 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
227 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
228 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
229 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
230 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
231 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
233 /* bit 48 ~ bit 55 */
234 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
236 /* bit 56 ~ bit 63, Flex Payload */
237 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
238 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD \
246 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
247 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
248 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
249 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
251 /* The max bandwidth of i40e is 40Gbps. */
252 #define I40E_QOS_BW_MAX 40000
253 /* The bandwidth should be the multiple of 50Mbps. */
254 #define I40E_QOS_BW_GRANULARITY 50
255 /* The min bandwidth weight is 1. */
256 #define I40E_QOS_BW_WEIGHT_MIN 1
257 /* The max bandwidth weight is 127. */
258 #define I40E_QOS_BW_WEIGHT_MAX 127
259 /* The max queue region index is 7. */
260 #define I40E_REGION_MAX_INDEX 7
262 #define I40E_MAX_PERCENT 100
263 #define I40E_DEFAULT_DCB_APP_NUM 1
264 #define I40E_DEFAULT_DCB_APP_PRIO 3
267 * The overhead from MTU to max frame size.
268 * Considering QinQ packet, the VLAN tag needs to be counted twice.
270 #define I40E_ETH_OVERHEAD \
271 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
276 * MAC filter structure
278 struct i40e_mac_filter_info {
279 enum rte_mac_filter_type filter_type;
280 struct ether_addr mac_addr;
283 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
285 /* MAC filter list structure */
286 struct i40e_mac_filter {
287 TAILQ_ENTRY(i40e_mac_filter) next;
288 struct i40e_mac_filter_info mac_info;
291 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
295 /* VSI list structure */
296 struct i40e_vsi_list {
297 TAILQ_ENTRY(i40e_vsi_list) list;
298 struct i40e_vsi *vsi;
301 struct i40e_rx_queue;
302 struct i40e_tx_queue;
304 /* Bandwidth limit information */
305 struct i40e_bw_info {
306 uint16_t bw_limit; /* BW Limit (0 = disabled) */
307 uint8_t bw_max; /* Max BW limit if enabled */
309 /* Relative credits within same TC with respect to other VSIs or Comps */
310 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
311 /* Bandwidth limit per TC */
312 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
313 /* Max bandwidth limit per TC */
314 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
317 /* Structure that defines a VEB */
319 struct i40e_vsi_list_head head;
320 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
321 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
322 uint16_t seid; /* The seid of VEB itself */
323 uint16_t uplink_seid; /* The uplink seid of this VEB */
325 struct i40e_eth_stats stats;
326 uint8_t enabled_tc; /* The traffic class enabled */
327 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
328 struct i40e_bw_info bw_info; /* VEB bandwidth information */
331 /* i40e MACVLAN filter structure */
332 struct i40e_macvlan_filter {
333 struct ether_addr macaddr;
334 enum rte_mac_filter_type filter_type;
339 * Structure that defines a VSI, associated with a adapter.
342 struct i40e_adapter *adapter; /* Backreference to associated adapter */
343 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
345 struct i40e_eth_stats eth_stats_offset;
346 struct i40e_eth_stats eth_stats;
348 * When drivers loaded, only a default main VSI exists. In case new VSI
349 * needs to add, HW needs to know the layout that VSIs are organized.
350 * Besides that, VSI isan element and can't switch packets, which needs
351 * to add new component VEB to perform switching. So, a new VSI needs
352 * to specify the uplink VSI (Parent VSI) before created. The
353 * uplink VSI will check whether it had a VEB to switch packets. If no,
354 * it will try to create one. Then, uplink VSI will move the new VSI
355 * into its' sib_vsi_list to manage all the downlink VSI.
356 * sib_vsi_list: the VSI list that shared the same uplink VSI.
357 * parent_vsi : the uplink VSI. It's NULL for main VSI.
358 * veb : the VEB associates with the VSI.
360 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
361 struct i40e_vsi *parent_vsi;
362 struct i40e_veb *veb; /* Associated veb, could be null */
363 struct i40e_veb *floating_veb; /* Associated floating veb */
365 enum i40e_vsi_type type; /* VSI types */
366 uint16_t vlan_num; /* Total VLAN number */
367 uint16_t mac_num; /* Total mac number */
368 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
369 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
370 /* specific VSI-defined parameters, SRIOV stored the vf_id */
372 uint16_t seid; /* The seid of VSI itself */
373 uint16_t uplink_seid; /* The uplink seid of this VSI */
374 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
375 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
376 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
377 uint16_t base_queue; /* The first queue index of this VSI */
379 * The offset to visit VSI related register, assigned by HW when
383 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
384 uint16_t nb_msix; /* The max number of msix vector */
385 uint8_t enabled_tc; /* The traffic class enabled */
386 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
387 uint8_t vlan_filter_on; /* The VLAN filter enabled */
388 struct i40e_bw_info bw_info; /* VSI bandwidth information */
392 LIST_ENTRY(pool_entry) next;
397 LIST_HEAD(res_list, pool_entry);
399 struct i40e_res_pool_info {
400 uint32_t base; /* Resource start index */
401 uint32_t num_alloc; /* Allocated resource number */
402 uint32_t num_free; /* Total available resource number */
403 struct res_list alloc_list; /* Allocated resource list */
404 struct res_list free_list; /* Available resource list */
408 I40E_VF_INACTIVE = 0,
415 * Structure to store private data for PF host.
419 struct i40e_vsi *vsi;
420 enum I40E_VF_STATE state; /* The number of queue pairs available */
421 uint16_t vf_idx; /* VF index in pf->vfs */
422 uint16_t lan_nb_qps; /* Actual queues allocated */
423 uint16_t reset_cnt; /* Total vf reset times */
424 struct ether_addr mac_addr; /* Default MAC address */
425 /* version of the virtchnl from VF */
426 struct virtchnl_version_info version;
427 uint32_t request_caps; /* offload caps requested from VF */
431 * Structure to store private data for flow control.
433 struct i40e_fc_conf {
434 uint16_t pause_time; /* Flow control pause timer */
435 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
436 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
437 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
438 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
442 * Structure to store private data for VMDQ instance
444 struct i40e_vmdq_info {
446 struct i40e_vsi *vsi;
449 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
450 #define I40E_MAX_FLX_SOURCE_OFF 480
451 #define NONUSE_FLX_PIT_DEST_OFF 63
452 #define NONUSE_FLX_PIT_FSIZE 1
453 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
454 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
455 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
456 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
457 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
458 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
459 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
460 NONUSE_FLX_PIT_DEST_OFF : \
461 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
462 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
463 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
464 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
465 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
466 #define I40E_FDIR_IPv6_TC_OFFSET 20
468 /* A structure used to define the input for GTP flow */
469 struct i40e_gtp_flow {
470 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
471 uint8_t msg_type; /* Message type. */
472 uint32_t teid; /* TEID in big endian. */
475 /* A structure used to define the input for GTP IPV4 flow */
476 struct i40e_gtp_ipv4_flow {
477 struct i40e_gtp_flow gtp;
478 struct rte_eth_ipv4_flow ip4;
481 /* A structure used to define the input for GTP IPV6 flow */
482 struct i40e_gtp_ipv6_flow {
483 struct i40e_gtp_flow gtp;
484 struct rte_eth_ipv6_flow ip6;
487 /* A structure used to define the input for raw type flow */
488 struct i40e_raw_flow {
495 * A union contains the inputs for all types of flow
496 * items in flows need to be in big endian
498 union i40e_fdir_flow {
499 struct rte_eth_l2_flow l2_flow;
500 struct rte_eth_udpv4_flow udp4_flow;
501 struct rte_eth_tcpv4_flow tcp4_flow;
502 struct rte_eth_sctpv4_flow sctp4_flow;
503 struct rte_eth_ipv4_flow ip4_flow;
504 struct rte_eth_udpv6_flow udp6_flow;
505 struct rte_eth_tcpv6_flow tcp6_flow;
506 struct rte_eth_sctpv6_flow sctp6_flow;
507 struct rte_eth_ipv6_flow ipv6_flow;
508 struct i40e_gtp_flow gtp_flow;
509 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
510 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
511 struct i40e_raw_flow raw_flow;
514 enum i40e_fdir_ip_type {
515 I40E_FDIR_IPTYPE_IPV4,
516 I40E_FDIR_IPTYPE_IPV6,
519 /* A structure used to contain extend input of flow */
520 struct i40e_fdir_flow_ext {
522 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
523 /* It is filled by the flexible payload to match. */
524 uint8_t is_vf; /* 1 for VF, 0 for port dev */
525 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
526 bool inner_ip; /* If there is inner ip */
527 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
528 bool customized_pctype; /* If customized pctype is used */
529 bool pkt_template; /* If raw packet template is used */
532 /* A structure used to define the input for a flow director filter entry */
533 struct i40e_fdir_input {
534 enum i40e_filter_pctype pctype;
535 union i40e_fdir_flow flow;
536 /* Flow fields to match, dependent on flow_type */
537 struct i40e_fdir_flow_ext flow_ext;
538 /* Additional fields to match */
541 /* Behavior will be taken if FDIR match */
542 enum i40e_fdir_behavior {
543 I40E_FDIR_ACCEPT = 0,
548 /* Flow director report status
549 * It defines what will be reported if FDIR entry is matched.
551 enum i40e_fdir_status {
552 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
553 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
554 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
555 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
558 /* A structure used to define an action when match FDIR packet filter. */
559 struct i40e_fdir_action {
560 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
561 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
562 enum i40e_fdir_status report_status; /* Status report option */
563 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
564 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
565 * flex bytes start from in flexible payload.
570 /* A structure used to define the flow director filter entry by filter_ctrl API
571 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
572 * RTE_ETH_FILTER_DELETE operations.
574 struct i40e_fdir_filter_conf {
576 /* ID, an unique value is required when deal with FDIR entry */
577 struct i40e_fdir_input input; /* Input set */
578 struct i40e_fdir_action action; /* Action taken when match */
582 * Structure to store flex pit for flow diretor.
584 struct i40e_fdir_flex_pit {
585 uint8_t src_offset; /* offset in words from the beginning of payload */
586 uint8_t size; /* size in words */
587 uint8_t dst_offset; /* offset in words of flexible payload */
590 struct i40e_fdir_flex_mask {
591 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
596 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
599 #define I40E_FILTER_PCTYPE_INVALID 0
600 #define I40E_FILTER_PCTYPE_MAX 64
601 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
603 struct i40e_fdir_filter {
604 TAILQ_ENTRY(i40e_fdir_filter) rules;
605 struct i40e_fdir_filter_conf fdir;
608 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
610 * A structure used to define fields of a FDIR related info.
612 struct i40e_fdir_info {
613 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
614 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
615 struct i40e_tx_queue *txq;
616 struct i40e_rx_queue *rxq;
617 void *prg_pkt; /* memory for fdir program packet */
618 uint64_t dma_addr; /* physic address of packet memory*/
619 /* input set bits for each pctype */
620 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
622 * the rule how bytes stream is extracted as flexible payload
623 * for each payload layer, the setting can up to three elements
625 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
626 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
628 struct i40e_fdir_filter_list fdir_list;
629 struct i40e_fdir_filter **hash_map;
630 struct rte_hash *hash_table;
632 /* Mark if flex pit and mask is set */
633 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
634 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
636 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
639 /* Ethertype filter number HW supports */
640 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
642 /* Ethertype filter struct */
643 struct i40e_ethertype_filter_input {
644 struct ether_addr mac_addr; /* Mac address to match */
645 uint16_t ether_type; /* Ether type to match */
648 struct i40e_ethertype_filter {
649 TAILQ_ENTRY(i40e_ethertype_filter) rules;
650 struct i40e_ethertype_filter_input input;
651 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
652 uint16_t queue; /* Queue assigned to when match */
655 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
657 struct i40e_ethertype_rule {
658 struct i40e_ethertype_filter_list ethertype_list;
659 struct i40e_ethertype_filter **hash_map;
660 struct rte_hash *hash_table;
663 /* queue region info */
664 struct i40e_queue_region_info {
665 /* the region id for this configuration */
667 /* the start queue index for this region */
668 uint8_t queue_start_index;
669 /* the total queue number of this queue region */
671 /* the total number of user priority for this region */
672 uint8_t user_priority_num;
673 /* the packet's user priority for this region */
674 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
675 /* the total number of flowtype for this region */
676 uint8_t flowtype_num;
678 * the pctype or hardware flowtype of packet,
679 * the specific index for each type has been defined
680 * in file i40e_type.h as enum i40e_filter_pctype.
682 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
685 struct i40e_queue_regions {
686 /* the total number of queue region for this port */
687 uint16_t queue_region_number;
688 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
691 /* Tunnel filter number HW supports */
692 #define I40E_MAX_TUNNEL_FILTER_NUM 400
694 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
695 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
696 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
697 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
698 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
699 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
700 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
701 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
702 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
703 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
704 #define I40E_AQC_NEW_TR_21 21
705 #define I40E_AQC_NEW_TR_22 22
707 enum i40e_tunnel_iptype {
708 I40E_TUNNEL_IPTYPE_IPV4,
709 I40E_TUNNEL_IPTYPE_IPV6,
712 /* Tunnel filter struct */
713 struct i40e_tunnel_filter_input {
714 uint8_t outer_mac[6]; /* Outer mac address to match */
715 uint8_t inner_mac[6]; /* Inner mac address to match */
716 uint16_t inner_vlan; /* Inner vlan address to match */
717 enum i40e_tunnel_iptype ip_type;
718 uint16_t flags; /* Filter type flag */
719 uint32_t tenant_id; /* Tenant id to match */
720 uint16_t general_fields[32]; /* Big buffer */
723 struct i40e_tunnel_filter {
724 TAILQ_ENTRY(i40e_tunnel_filter) rules;
725 struct i40e_tunnel_filter_input input;
726 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
727 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
728 uint16_t queue; /* Queue assigned to when match */
731 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
733 struct i40e_tunnel_rule {
734 struct i40e_tunnel_filter_list tunnel_list;
735 struct i40e_tunnel_filter **hash_map;
736 struct rte_hash *hash_table;
742 enum i40e_tunnel_type {
743 I40E_TUNNEL_TYPE_NONE = 0,
744 I40E_TUNNEL_TYPE_VXLAN,
745 I40E_TUNNEL_TYPE_GENEVE,
746 I40E_TUNNEL_TYPE_TEREDO,
747 I40E_TUNNEL_TYPE_NVGRE,
748 I40E_TUNNEL_TYPE_IP_IN_GRE,
749 I40E_L2_TUNNEL_TYPE_E_TAG,
750 I40E_TUNNEL_TYPE_MPLSoUDP,
751 I40E_TUNNEL_TYPE_MPLSoGRE,
752 I40E_TUNNEL_TYPE_QINQ,
753 I40E_TUNNEL_TYPE_GTPC,
754 I40E_TUNNEL_TYPE_GTPU,
755 I40E_TUNNEL_TYPE_MAX,
759 * Tunneling Packet filter configuration.
761 struct i40e_tunnel_filter_conf {
762 struct ether_addr outer_mac; /**< Outer MAC address to match. */
763 struct ether_addr inner_mac; /**< Inner MAC address to match. */
764 uint16_t inner_vlan; /**< Inner VLAN to match. */
765 uint32_t outer_vlan; /**< Outer VLAN to match */
766 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
768 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
769 * is set in filter_type, or inner destination IP address to match
770 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
773 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
774 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
776 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
777 uint16_t filter_type;
778 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
779 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
780 uint16_t queue_id; /**< Queue assigned to if match. */
781 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
782 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
785 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
786 #define I40E_MAX_MIRROR_RULES 64
788 * Mirror rule structure
790 struct i40e_mirror_rule {
791 TAILQ_ENTRY(i40e_mirror_rule) rules;
793 uint16_t index; /* the sw index of mirror rule */
794 uint16_t id; /* the rule id assigned by firmware */
795 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
796 uint16_t num_entries;
797 /* the info stores depend on the rule type.
798 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
799 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
801 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
804 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
807 * Struct to store flow created.
810 TAILQ_ENTRY(rte_flow) node;
811 enum rte_filter_type filter_type;
815 TAILQ_HEAD(i40e_flow_list, rte_flow);
817 /* Struct to store Traffic Manager shaper profile. */
818 struct i40e_tm_shaper_profile {
819 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
820 uint32_t shaper_profile_id;
821 uint32_t reference_count;
822 struct rte_tm_shaper_params profile;
825 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
827 /* node type of Traffic Manager */
828 enum i40e_tm_node_type {
829 I40E_TM_NODE_TYPE_PORT,
830 I40E_TM_NODE_TYPE_TC,
831 I40E_TM_NODE_TYPE_QUEUE,
832 I40E_TM_NODE_TYPE_MAX,
835 /* Struct to store Traffic Manager node configuration. */
836 struct i40e_tm_node {
837 TAILQ_ENTRY(i40e_tm_node) node;
841 uint32_t reference_count;
842 struct i40e_tm_node *parent;
843 struct i40e_tm_shaper_profile *shaper_profile;
844 struct rte_tm_node_params params;
847 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
849 /* Struct to store all the Traffic Manager configuration. */
850 struct i40e_tm_conf {
851 struct i40e_shaper_profile_list shaper_profile_list;
852 struct i40e_tm_node *root; /* root node - port */
853 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
854 struct i40e_tm_node_list queue_list; /* node list for all the queues */
856 * The number of added TC nodes.
857 * It should be no more than the TC number of this port.
861 * The number of added queue nodes.
862 * It should be no more than the queue number of this port.
864 uint32_t nb_queue_node;
866 * This flag is used to check if APP can change the TM node
868 * When it's true, means the configuration is applied to HW,
869 * APP should not change the configuration.
870 * As we don't support on-the-fly configuration, when starting
871 * the port, APP should call the hierarchy_commit API to set this
872 * flag to true. When stopping the port, this flag should be set
878 enum i40e_new_pctype {
879 I40E_CUSTOMIZED_GTPC = 0,
880 I40E_CUSTOMIZED_GTPU_IPV4,
881 I40E_CUSTOMIZED_GTPU_IPV6,
882 I40E_CUSTOMIZED_GTPU,
886 #define I40E_FILTER_PCTYPE_INVALID 0
887 struct i40e_customized_pctype {
888 enum i40e_new_pctype index; /* Indicate which customized pctype */
889 uint8_t pctype; /* New pctype value */
890 bool valid; /* Check if it's valid */
893 struct i40e_rte_flow_rss_conf {
894 struct rte_flow_action_rss conf; /**< RSS parameters. */
895 uint16_t queue_region_conf; /**< Queue region config flag */
896 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
897 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
898 sizeof(uint32_t)]; /* Hash key. */
899 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
903 * Structure to store private data specific for PF instance.
906 struct i40e_adapter *adapter; /* The adapter this PF associate to */
907 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
908 uint16_t mac_seid; /* The seid of the MAC of this PF */
909 uint16_t main_vsi_seid; /* The seid of the main VSI */
910 uint16_t max_num_vsi;
911 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
912 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
914 struct i40e_hw_port_stats stats_offset;
915 struct i40e_hw_port_stats stats;
916 /* internal packet statistics, it should be excluded from the total */
917 struct i40e_eth_stats internal_stats_offset;
918 struct i40e_eth_stats internal_stats;
921 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
922 struct ether_addr dev_addr; /* PF device mac address */
923 uint64_t flags; /* PF feature flags */
924 /* All kinds of queue pair setting for different VSIs */
925 struct i40e_pf_vf *vfs;
927 /* Each of below queue pairs should be power of 2 since it's the
928 precondition after TC configuration applied */
929 uint16_t lan_nb_qp_max;
930 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
931 uint16_t lan_qp_offset;
932 uint16_t vmdq_nb_qp_max;
933 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
934 uint16_t vmdq_qp_offset;
935 uint16_t vf_nb_qp_max;
936 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
937 uint16_t vf_qp_offset;
938 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
939 uint16_t fdir_qp_offset;
941 uint16_t hash_lut_size; /* The size of hash lookup table */
942 /* input set bits for each pctype */
943 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
944 /* store VXLAN UDP ports */
945 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
946 uint16_t vxlan_bitmap; /* Vxlan bit mask */
948 /* VMDQ related info */
949 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
950 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
951 struct i40e_vmdq_info *vmdq;
953 struct i40e_fdir_info fdir; /* flow director info */
954 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
955 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
956 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
957 struct i40e_queue_regions queue_region; /* queue region info */
958 struct i40e_fc_conf fc_conf; /* Flow control conf */
959 struct i40e_mirror_rule_list mirror_list;
960 uint16_t nb_mirror_rule; /* The number of mirror rules */
961 bool floating_veb; /* The flag to use the floating VEB */
962 /* The floating enable flag for the specific VF */
963 bool floating_veb_list[I40E_MAX_VF];
964 struct i40e_flow_list flow_list;
965 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
966 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
967 bool qinq_replace_flag; /* QINQ filter replace is done */
968 struct i40e_tm_conf tm_conf;
969 bool support_multi_driver; /* 1 - support multiple driver */
971 /* Dynamic Device Personalization */
972 bool gtp_support; /* 1 - support GTP-C and GTP-U */
973 /* customer customized pctype */
974 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
975 /* Switch Domain Id */
976 uint16_t switch_domain_id;
980 PFMSG_LINK_CHANGE = 0x1,
981 PFMSG_RESET_IMPENDING = 0x2,
982 PFMSG_DRIVER_CLOSE = 0x4,
985 struct i40e_vsi_vlan_pvid_info {
986 uint16_t on; /* Enable or disable pvid */
988 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
990 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
991 * while 'untagged' will reject untagged packets.
999 struct i40e_vf_rx_queues {
1000 uint64_t rx_dma_addr;
1001 uint32_t rx_ring_len;
1005 struct i40e_vf_tx_queues {
1006 uint64_t tx_dma_addr;
1007 uint32_t tx_ring_len;
1011 * Structure to store private data specific for VF instance.
1014 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1015 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1016 uint16_t num_queue_pairs;
1017 uint16_t max_pkt_len; /* Maximum packet length */
1018 bool promisc_unicast_enabled;
1019 bool promisc_multicast_enabled;
1021 uint32_t version_major; /* Major version number */
1022 uint32_t version_minor; /* Minor version number */
1023 uint16_t promisc_flags; /* Promiscuous setting */
1024 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1026 struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */
1027 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1032 enum virtchnl_link_speed link_speed;
1034 volatile uint32_t pend_cmd; /* pending command not finished yet */
1035 int32_t cmd_retval; /* return value of the cmd response from PF */
1036 u16 pend_msg; /* flags indicates events from pf not handled yet */
1037 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1040 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1041 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1042 struct i40e_vsi vsi;
1046 #define I40E_MAX_PKT_TYPE 256
1047 #define I40E_FLOW_TYPE_MAX 64
1050 * Structure to store private data for each PF/VF instance.
1052 struct i40e_adapter {
1053 /* Common for both PF and VF */
1055 struct rte_eth_dev *eth_dev;
1057 /* Specific for PF or VF */
1063 /* For vector PMD */
1064 bool rx_bulk_alloc_allowed;
1065 bool rx_vec_allowed;
1066 bool tx_simple_allowed;
1067 bool tx_vec_allowed;
1070 struct rte_timecounter systime_tc;
1071 struct rte_timecounter rx_tstamp_tc;
1072 struct rte_timecounter tx_tstamp_tc;
1074 /* ptype mapping table */
1075 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1076 /* flow type to pctype mapping table */
1077 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1078 uint64_t flow_types_mask;
1079 uint64_t pctypes_mask;
1083 * Strucute to store private data for each VF representor instance
1085 struct i40e_vf_representor {
1086 uint16_t switch_domain_id;
1087 /**< Virtual Function ID */
1089 /**< Virtual Function ID */
1090 struct i40e_adapter *adapter;
1091 /**< Private data store of assocaiated physical function */
1092 struct i40e_eth_stats stats_offset;
1093 /**< Zero-point of VF statistics*/
1096 extern const struct rte_flow_ops i40e_flow_ops;
1098 union i40e_filter_t {
1099 struct rte_eth_ethertype_filter ethertype_filter;
1100 struct i40e_fdir_filter_conf fdir_filter;
1101 struct rte_eth_tunnel_filter_conf tunnel_filter;
1102 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1103 struct i40e_rte_flow_rss_conf rss_conf;
1106 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1107 const struct rte_flow_attr *attr,
1108 const struct rte_flow_item pattern[],
1109 const struct rte_flow_action actions[],
1110 struct rte_flow_error *error,
1111 union i40e_filter_t *filter);
1112 struct i40e_valid_pattern {
1113 enum rte_flow_item_type *items;
1114 parse_filter_t parse_filter;
1117 enum I40E_WARNING_IDX {
1118 I40E_WARNING_DIS_FLX_PLD,
1119 I40E_WARNING_ENA_FLX_PLD,
1120 I40E_WARNING_QINQ_PARSER,
1121 I40E_WARNING_QINQ_CLOUD_FILTER,
1123 I40E_WARNING_FLOW_CTL,
1124 I40E_WARNING_GRE_KEY_LEN,
1125 I40E_WARNING_QF_CTL,
1126 I40E_WARNING_HASH_INSET,
1128 I40E_WARNING_HASH_MSK,
1129 I40E_WARNING_FD_MSK,
1130 I40E_WARNING_RPL_CLD_FILTER,
1133 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1134 int i40e_vsi_release(struct i40e_vsi *vsi);
1135 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1136 enum i40e_vsi_type type,
1137 struct i40e_vsi *uplink_vsi,
1138 uint16_t user_param);
1139 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1140 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1141 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1142 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1143 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1144 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1145 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1146 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1147 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1148 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1149 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1150 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1151 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1152 struct i40e_vsi_vlan_pvid_info *info);
1153 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1154 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1155 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1156 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1157 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1158 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1159 int i40e_fdir_setup(struct i40e_pf *pf);
1160 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1163 int i40e_fdir_configure(struct rte_eth_dev *dev);
1164 void i40e_fdir_teardown(struct i40e_pf *pf);
1165 enum i40e_filter_pctype
1166 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1167 uint16_t flow_type);
1168 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1169 enum i40e_filter_pctype pctype);
1170 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1171 enum rte_filter_op filter_op,
1173 int i40e_select_filter_input_set(struct i40e_hw *hw,
1174 struct rte_eth_input_set_conf *conf,
1175 enum rte_filter_type filter);
1176 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1177 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1178 struct rte_eth_input_set_conf *conf);
1179 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1180 struct rte_eth_input_set_conf *conf);
1181 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1182 uint32_t retval, uint8_t *msg,
1184 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1185 struct rte_eth_rxq_info *qinfo);
1186 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1187 struct rte_eth_txq_info *qinfo);
1188 struct i40e_ethertype_filter *
1189 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1190 const struct i40e_ethertype_filter_input *input);
1191 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1192 struct i40e_ethertype_filter_input *input);
1193 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1194 struct i40e_fdir_input *input);
1195 struct i40e_tunnel_filter *
1196 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1197 const struct i40e_tunnel_filter_input *input);
1198 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1199 struct i40e_tunnel_filter_input *input);
1200 uint64_t i40e_get_default_input_set(uint16_t pctype);
1201 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1202 struct rte_eth_ethertype_filter *filter,
1204 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1205 const struct rte_eth_fdir_filter *filter,
1207 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1208 const struct i40e_fdir_filter_conf *filter,
1210 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1211 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1213 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1214 struct i40e_tunnel_filter_conf *tunnel_filter,
1216 int i40e_fdir_flush(struct rte_eth_dev *dev);
1217 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1218 struct i40e_macvlan_filter *mv_f,
1219 int num, struct ether_addr *addr);
1220 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1221 struct i40e_macvlan_filter *filter,
1223 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1224 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1225 struct i40e_macvlan_filter *filter,
1227 bool is_i40e_supported(struct rte_eth_dev *dev);
1229 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1230 enum rte_filter_type filter, uint64_t inset);
1231 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1233 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1234 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1235 void i40e_check_write_global_reg(struct i40e_hw *hw,
1236 uint32_t addr, uint32_t val);
1238 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1239 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1240 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1241 struct i40e_customized_pctype*
1242 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1243 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1245 enum rte_pmd_i40e_package_op op);
1246 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1247 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1248 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1249 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1250 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1251 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1252 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1253 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1254 const struct rte_flow_action_rss *in);
1255 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1256 const struct rte_flow_action_rss *with);
1257 int i40e_config_rss_filter(struct i40e_pf *pf,
1258 struct i40e_rte_flow_rss_conf *conf, bool add);
1259 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1260 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1262 #define I40E_DEV_TO_PCI(eth_dev) \
1263 RTE_DEV_TO_PCI((eth_dev)->device)
1265 /* I40E_DEV_PRIVATE_TO */
1266 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1267 (&((struct i40e_adapter *)adapter)->pf)
1268 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1269 (&((struct i40e_adapter *)adapter)->hw)
1270 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1271 ((struct i40e_adapter *)adapter)
1273 /* I40EVF_DEV_PRIVATE_TO */
1274 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1275 (&((struct i40e_adapter *)adapter)->vf)
1277 static inline struct i40e_vsi *
1278 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1285 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1286 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1287 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1290 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1291 return pf->main_vsi;
1294 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1295 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1298 #define I40E_VSI_TO_HW(vsi) \
1299 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1300 #define I40E_VSI_TO_PF(vsi) \
1301 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1302 #define I40E_VSI_TO_VF(vsi) \
1303 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1304 #define I40E_VSI_TO_DEV_DATA(vsi) \
1305 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1306 #define I40E_VSI_TO_ETH_DEV(vsi) \
1307 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1310 #define I40E_PF_TO_HW(pf) \
1311 (&(((struct i40e_pf *)pf)->adapter->hw))
1312 #define I40E_PF_TO_ADAPTER(pf) \
1313 ((struct i40e_adapter *)pf->adapter)
1316 #define I40E_VF_TO_HW(vf) \
1317 (&(((struct i40e_vf *)vf)->adapter->hw))
1320 i40e_init_adminq_parameter(struct i40e_hw *hw)
1322 hw->aq.num_arq_entries = I40E_AQ_LEN;
1323 hw->aq.num_asq_entries = I40E_AQ_LEN;
1324 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1325 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1329 i40e_align_floor(int n)
1333 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1336 static inline uint16_t
1337 i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
1339 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
1341 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1344 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1346 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1350 /* Convert to hardware count, as writing each 1 represents 2 us */
1351 return interval / 2;
1355 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
1357 const char *warning;
1358 static const char *const warning_list[] = {
1359 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
1360 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
1361 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
1362 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
1363 [I40E_WARNING_TPID] = "support TPID configuration",
1364 [I40E_WARNING_FLOW_CTL] = "configure water marker",
1365 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
1366 [I40E_WARNING_QF_CTL] = "support hash function setting",
1367 [I40E_WARNING_HASH_INSET] = "configure hash input set",
1368 [I40E_WARNING_HSYM] = "set symmetric hash",
1369 [I40E_WARNING_HASH_MSK] = "configure hash mask",
1370 [I40E_WARNING_FD_MSK] = "configure fdir mask",
1371 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
1374 warning = warning_list[idx];
1376 RTE_LOG(WARNING, PMD,
1377 "Global register is changed during %s\n",
1381 #define I40E_VALID_FLOW(flow_type) \
1382 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1383 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1384 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1385 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1386 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1387 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1388 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1389 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1390 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1391 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1392 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1394 #define I40E_VALID_PCTYPE_X722(pctype) \
1395 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1396 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1397 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1398 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1399 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1400 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1401 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1402 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1403 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1404 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1405 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1406 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1407 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1408 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1409 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1410 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1411 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1413 #define I40E_VALID_PCTYPE(pctype) \
1414 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1415 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1416 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1417 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1418 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1419 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1420 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1421 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1422 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1423 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1424 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1426 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1427 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1428 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1429 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1430 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1431 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1432 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1434 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1435 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1436 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1437 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1438 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1440 #endif /* _I40E_ETHDEV_H_ */