4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
43 #define I40E_VLAN_TAG_SIZE 4
45 #define I40E_AQ_LEN 32
46 #define I40E_AQ_BUF_SZ 4096
47 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
48 #define I40E_MAX_Q_PER_TC 64
49 #define I40E_NUM_DESC_DEFAULT 512
50 #define I40E_NUM_DESC_ALIGN 32
51 #define I40E_BUF_SIZE_MIN 1024
52 #define I40E_FRAME_SIZE_MAX 9728
53 #define I40E_QUEUE_BASE_ADDR_UNIT 128
54 /* number of VSIs and queue default setting */
55 #define I40E_MAX_QP_NUM_PER_VF 16
56 #define I40E_DEFAULT_QP_NUM_FDIR 1
57 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
58 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
59 /* Maximun number of MAC addresses */
60 #define I40E_NUM_MACADDR_MAX 64
61 /* Maximum number of VFs */
62 #define I40E_MAX_VF 128
65 * vlan_id is a 12 bit number.
66 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
67 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
68 * The higher 7 bit val specifies VFTA array index.
70 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
71 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
73 /* Default TC traffic in case DCB is not enabled */
74 #define I40E_DEFAULT_TCMAP 0x1
75 #define I40E_FDIR_QUEUE_ID 0
77 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
78 #define I40E_VMDQ_POOL_BASE 1
80 #define I40E_DEFAULT_RX_FREE_THRESH 32
81 #define I40E_DEFAULT_RX_PTHRESH 8
82 #define I40E_DEFAULT_RX_HTHRESH 8
83 #define I40E_DEFAULT_RX_WTHRESH 0
85 #define I40E_DEFAULT_TX_FREE_THRESH 32
86 #define I40E_DEFAULT_TX_PTHRESH 32
87 #define I40E_DEFAULT_TX_HTHRESH 0
88 #define I40E_DEFAULT_TX_WTHRESH 0
89 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
91 /* Bit shift and mask */
92 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
93 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
94 #define I40E_8_BIT_WIDTH CHAR_BIT
95 #define I40E_8_BIT_MASK UINT8_MAX
96 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
97 #define I40E_16_BIT_MASK UINT16_MAX
98 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
99 #define I40E_32_BIT_MASK UINT32_MAX
100 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
101 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
103 /* Linux PF host with virtchnl version 1.1 */
104 #define PF_IS_V11(vf) \
105 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
106 ((vf)->version_minor == 1))
108 /* index flex payload per layer */
109 enum i40e_flxpld_layer_idx {
110 I40E_FLXPLD_L2_IDX = 0,
111 I40E_FLXPLD_L3_IDX = 1,
112 I40E_FLXPLD_L4_IDX = 2,
113 I40E_MAX_FLXPLD_LAYER = 3,
115 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
116 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
117 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
118 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
119 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
122 #define I40E_FLAG_RSS (1ULL << 0)
123 #define I40E_FLAG_DCB (1ULL << 1)
124 #define I40E_FLAG_VMDQ (1ULL << 2)
125 #define I40E_FLAG_SRIOV (1ULL << 3)
126 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
127 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
128 #define I40E_FLAG_FDIR (1ULL << 6)
129 #define I40E_FLAG_VXLAN (1ULL << 7)
130 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
131 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
132 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
136 I40E_FLAG_HEADER_SPLIT_DISABLED | \
137 I40E_FLAG_HEADER_SPLIT_ENABLED | \
140 I40E_FLAG_RSS_AQ_CAPABLE | \
141 I40E_FLAG_VF_MAC_BY_PF)
143 #define I40E_RSS_OFFLOAD_ALL ( \
144 ETH_RSS_FRAG_IPV4 | \
145 ETH_RSS_NONFRAG_IPV4_TCP | \
146 ETH_RSS_NONFRAG_IPV4_UDP | \
147 ETH_RSS_NONFRAG_IPV4_SCTP | \
148 ETH_RSS_NONFRAG_IPV4_OTHER | \
149 ETH_RSS_FRAG_IPV6 | \
150 ETH_RSS_NONFRAG_IPV6_TCP | \
151 ETH_RSS_NONFRAG_IPV6_UDP | \
152 ETH_RSS_NONFRAG_IPV6_SCTP | \
153 ETH_RSS_NONFRAG_IPV6_OTHER | \
156 /* All bits of RSS hash enable for X722*/
157 #define I40E_RSS_HENA_ALL_X722 ( \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
166 /* All bits of RSS hash enable */
167 #define I40E_RSS_HENA_ALL ( \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
172 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
176 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
177 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
178 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
179 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
180 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
181 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
183 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
184 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
186 /* Default queue interrupt throttling time in microseconds */
187 #define I40E_ITR_INDEX_DEFAULT 0
188 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
189 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
191 /* Special FW support this floating VEB feature */
192 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
193 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
195 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
196 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
197 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
198 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
200 #define I40E_INSET_NONE 0x00000000000000000ULL
203 #define I40E_INSET_DMAC 0x0000000000000001ULL
204 #define I40E_INSET_SMAC 0x0000000000000002ULL
205 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
206 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
207 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
210 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
211 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
212 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
213 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
214 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
215 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
216 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
218 /* bit 16 ~ bit 31 */
219 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
220 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
221 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
222 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
223 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
224 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
225 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
226 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
228 /* bit 32 ~ bit 47, tunnel fields */
229 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
230 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
231 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
232 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
233 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
234 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
236 /* bit 48 ~ bit 55 */
237 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
239 /* bit 56 ~ bit 63, Flex Payload */
240 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
247 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
248 #define I40E_INSET_FLEX_PAYLOAD \
249 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
250 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
251 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
252 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
255 * The overhead from MTU to max frame size.
256 * Considering QinQ packet, the VLAN tag needs to be counted twice.
258 #define I40E_ETH_OVERHEAD \
259 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
264 * MAC filter structure
266 struct i40e_mac_filter_info {
267 enum rte_mac_filter_type filter_type;
268 struct ether_addr mac_addr;
271 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
273 /* MAC filter list structure */
274 struct i40e_mac_filter {
275 TAILQ_ENTRY(i40e_mac_filter) next;
276 struct i40e_mac_filter_info mac_info;
279 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
283 /* VSI list structure */
284 struct i40e_vsi_list {
285 TAILQ_ENTRY(i40e_vsi_list) list;
286 struct i40e_vsi *vsi;
289 struct i40e_rx_queue;
290 struct i40e_tx_queue;
292 /* Bandwidth limit information */
293 struct i40e_bw_info {
294 uint16_t bw_limit; /* BW Limit (0 = disabled) */
295 uint8_t bw_max; /* Max BW limit if enabled */
297 /* Relative credits within same TC with respect to other VSIs or Comps */
298 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
299 /* Bandwidth limit per TC */
300 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
301 /* Max bandwidth limit per TC */
302 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
305 /* Structure that defines a VEB */
307 struct i40e_vsi_list_head head;
308 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
309 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
310 uint16_t seid; /* The seid of VEB itself */
311 uint16_t uplink_seid; /* The uplink seid of this VEB */
313 struct i40e_eth_stats stats;
314 uint8_t enabled_tc; /* The traffic class enabled */
315 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
316 struct i40e_bw_info bw_info; /* VEB bandwidth information */
319 /* i40e MACVLAN filter structure */
320 struct i40e_macvlan_filter {
321 struct ether_addr macaddr;
322 enum rte_mac_filter_type filter_type;
327 * Structure that defines a VSI, associated with a adapter.
330 struct i40e_adapter *adapter; /* Backreference to associated adapter */
331 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
333 struct i40e_eth_stats eth_stats_offset;
334 struct i40e_eth_stats eth_stats;
336 * When drivers loaded, only a default main VSI exists. In case new VSI
337 * needs to add, HW needs to know the layout that VSIs are organized.
338 * Besides that, VSI isan element and can't switch packets, which needs
339 * to add new component VEB to perform switching. So, a new VSI needs
340 * to specify the the uplink VSI (Parent VSI) before created. The
341 * uplink VSI will check whether it had a VEB to switch packets. If no,
342 * it will try to create one. Then, uplink VSI will move the new VSI
343 * into its' sib_vsi_list to manage all the downlink VSI.
344 * sib_vsi_list: the VSI list that shared the same uplink VSI.
345 * parent_vsi : the uplink VSI. It's NULL for main VSI.
346 * veb : the VEB associates with the VSI.
348 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
349 struct i40e_vsi *parent_vsi;
350 struct i40e_veb *veb; /* Associated veb, could be null */
351 struct i40e_veb *floating_veb; /* Associated floating veb */
353 enum i40e_vsi_type type; /* VSI types */
354 uint16_t vlan_num; /* Total VLAN number */
355 uint16_t mac_num; /* Total mac number */
356 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
357 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
358 /* specific VSI-defined parameters, SRIOV stored the vf_id */
360 uint16_t seid; /* The seid of VSI itself */
361 uint16_t uplink_seid; /* The uplink seid of this VSI */
362 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
363 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
364 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
365 uint16_t base_queue; /* The first queue index of this VSI */
367 * The offset to visit VSI related register, assigned by HW when
371 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
372 uint16_t nb_msix; /* The max number of msix vector */
373 uint8_t enabled_tc; /* The traffic class enabled */
374 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
375 uint8_t vlan_filter_on; /* The VLAN filter enabled */
376 struct i40e_bw_info bw_info; /* VSI bandwidth information */
380 LIST_ENTRY(pool_entry) next;
385 LIST_HEAD(res_list, pool_entry);
387 struct i40e_res_pool_info {
388 uint32_t base; /* Resource start index */
389 uint32_t num_alloc; /* Allocated resource number */
390 uint32_t num_free; /* Total available resource number */
391 struct res_list alloc_list; /* Allocated resource list */
392 struct res_list free_list; /* Available resource list */
396 I40E_VF_INACTIVE = 0,
403 * Structure to store private data for PF host.
407 struct i40e_vsi *vsi;
408 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
409 uint16_t vf_idx; /* VF index in pf->vfs */
410 uint16_t lan_nb_qps; /* Actual queues allocated */
411 uint16_t reset_cnt; /* Total vf reset times */
412 struct ether_addr mac_addr; /* Default MAC address */
416 * Structure to store private data for flow control.
418 struct i40e_fc_conf {
419 uint16_t pause_time; /* Flow control pause timer */
420 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
421 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
422 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
423 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
427 * Structure to store private data for VMDQ instance
429 struct i40e_vmdq_info {
431 struct i40e_vsi *vsi;
434 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
435 #define I40E_MAX_FLX_SOURCE_OFF 480
436 #define NONUSE_FLX_PIT_DEST_OFF 63
437 #define NONUSE_FLX_PIT_FSIZE 1
438 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
439 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
440 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
441 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
442 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
443 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
444 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
445 NONUSE_FLX_PIT_DEST_OFF : \
446 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
447 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
448 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
449 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
450 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
453 * Structure to store flex pit for flow diretor.
455 struct i40e_fdir_flex_pit {
456 uint8_t src_offset; /* offset in words from the beginning of payload */
457 uint8_t size; /* size in words */
458 uint8_t dst_offset; /* offset in words of flexible payload */
461 struct i40e_fdir_flex_mask {
462 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
467 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
470 #define I40E_FILTER_PCTYPE_MAX 64
471 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
473 struct i40e_fdir_filter {
474 TAILQ_ENTRY(i40e_fdir_filter) rules;
475 struct rte_eth_fdir_filter fdir;
478 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
480 * A structure used to define fields of a FDIR related info.
482 struct i40e_fdir_info {
483 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
484 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
485 struct i40e_tx_queue *txq;
486 struct i40e_rx_queue *rxq;
487 void *prg_pkt; /* memory for fdir program packet */
488 uint64_t dma_addr; /* physic address of packet memory*/
489 /* input set bits for each pctype */
490 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
492 * the rule how bytes stream is extracted as flexible payload
493 * for each payload layer, the setting can up to three elements
495 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
496 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
498 struct i40e_fdir_filter_list fdir_list;
499 struct i40e_fdir_filter **hash_map;
500 struct rte_hash *hash_table;
502 /* Mark if flex pit and mask is set */
503 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
504 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
507 /* Ethertype filter number HW supports */
508 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
510 /* Ethertype filter struct */
511 struct i40e_ethertype_filter_input {
512 struct ether_addr mac_addr; /* Mac address to match */
513 uint16_t ether_type; /* Ether type to match */
516 struct i40e_ethertype_filter {
517 TAILQ_ENTRY(i40e_ethertype_filter) rules;
518 struct i40e_ethertype_filter_input input;
519 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
520 uint16_t queue; /* Queue assigned to when match */
523 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
525 struct i40e_ethertype_rule {
526 struct i40e_ethertype_filter_list ethertype_list;
527 struct i40e_ethertype_filter **hash_map;
528 struct rte_hash *hash_table;
531 /* Tunnel filter number HW supports */
532 #define I40E_MAX_TUNNEL_FILTER_NUM 400
534 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
535 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
536 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP 8
537 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE 9
538 #define I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ 0x10
539 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP 0x11
540 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE 0x12
541 #define I40E_AQC_ADD_L1_FILTER_TEID_MPLS 0x11
543 enum i40e_tunnel_iptype {
544 I40E_TUNNEL_IPTYPE_IPV4,
545 I40E_TUNNEL_IPTYPE_IPV6,
548 /* Tunnel filter struct */
549 struct i40e_tunnel_filter_input {
550 uint8_t outer_mac[6]; /* Outer mac address to match */
551 uint8_t inner_mac[6]; /* Inner mac address to match */
552 uint16_t inner_vlan; /* Inner vlan address to match */
553 enum i40e_tunnel_iptype ip_type;
554 uint16_t flags; /* Filter type flag */
555 uint32_t tenant_id; /* Tenant id to match */
556 uint16_t general_fields[32]; /* Big buffer */
559 struct i40e_tunnel_filter {
560 TAILQ_ENTRY(i40e_tunnel_filter) rules;
561 struct i40e_tunnel_filter_input input;
562 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
563 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
564 uint16_t queue; /* Queue assigned to when match */
567 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
569 struct i40e_tunnel_rule {
570 struct i40e_tunnel_filter_list tunnel_list;
571 struct i40e_tunnel_filter **hash_map;
572 struct rte_hash *hash_table;
578 enum i40e_tunnel_type {
579 I40E_TUNNEL_TYPE_NONE = 0,
580 I40E_TUNNEL_TYPE_VXLAN,
581 I40E_TUNNEL_TYPE_GENEVE,
582 I40E_TUNNEL_TYPE_TEREDO,
583 I40E_TUNNEL_TYPE_NVGRE,
584 I40E_TUNNEL_TYPE_IP_IN_GRE,
585 I40E_L2_TUNNEL_TYPE_E_TAG,
586 I40E_TUNNEL_TYPE_MPLSoUDP,
587 I40E_TUNNEL_TYPE_MPLSoGRE,
588 I40E_TUNNEL_TYPE_QINQ,
589 I40E_TUNNEL_TYPE_MAX,
593 * Tunneling Packet filter configuration.
595 struct i40e_tunnel_filter_conf {
596 struct ether_addr outer_mac; /**< Outer MAC address to match. */
597 struct ether_addr inner_mac; /**< Inner MAC address to match. */
598 uint16_t inner_vlan; /**< Inner VLAN to match. */
599 uint32_t outer_vlan; /**< Outer VLAN to match */
600 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
602 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
603 * is set in filter_type, or inner destination IP address to match
604 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
607 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
608 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
610 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
611 uint16_t filter_type;
612 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
613 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
614 uint16_t queue_id; /**< Queue assigned to if match. */
615 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
616 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
619 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
620 #define I40E_MAX_MIRROR_RULES 64
622 * Mirror rule structure
624 struct i40e_mirror_rule {
625 TAILQ_ENTRY(i40e_mirror_rule) rules;
627 uint16_t index; /* the sw index of mirror rule */
628 uint16_t id; /* the rule id assigned by firmware */
629 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
630 uint16_t num_entries;
631 /* the info stores depend on the rule type.
632 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
633 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
635 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
638 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
641 * Struct to store flow created.
644 TAILQ_ENTRY(rte_flow) node;
645 enum rte_filter_type filter_type;
649 TAILQ_HEAD(i40e_flow_list, rte_flow);
652 * Structure to store private data specific for PF instance.
655 struct i40e_adapter *adapter; /* The adapter this PF associate to */
656 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
657 uint16_t mac_seid; /* The seid of the MAC of this PF */
658 uint16_t main_vsi_seid; /* The seid of the main VSI */
659 uint16_t max_num_vsi;
660 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
661 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
663 struct i40e_hw_port_stats stats_offset;
664 struct i40e_hw_port_stats stats;
665 /* internal packet byte count, it should be excluded from the total */
666 uint64_t internal_rx_bytes;
667 uint64_t internal_tx_bytes;
668 uint64_t internal_rx_bytes_offset;
669 uint64_t internal_tx_bytes_offset;
672 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
673 struct ether_addr dev_addr; /* PF device mac address */
674 uint64_t flags; /* PF feature flags */
675 /* All kinds of queue pair setting for different VSIs */
676 struct i40e_pf_vf *vfs;
678 /* Each of below queue pairs should be power of 2 since it's the
679 precondition after TC configuration applied */
680 uint16_t lan_nb_qp_max;
681 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
682 uint16_t lan_qp_offset;
683 uint16_t vmdq_nb_qp_max;
684 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
685 uint16_t vmdq_qp_offset;
686 uint16_t vf_nb_qp_max;
687 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
688 uint16_t vf_qp_offset;
689 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
690 uint16_t fdir_qp_offset;
692 uint16_t hash_lut_size; /* The size of hash lookup table */
693 /* input set bits for each pctype */
694 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
695 /* store VXLAN UDP ports */
696 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
697 uint16_t vxlan_bitmap; /* Vxlan bit mask */
699 /* VMDQ related info */
700 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
701 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
702 struct i40e_vmdq_info *vmdq;
704 struct i40e_fdir_info fdir; /* flow director info */
705 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
706 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
707 struct i40e_fc_conf fc_conf; /* Flow control conf */
708 struct i40e_mirror_rule_list mirror_list;
709 uint16_t nb_mirror_rule; /* The number of mirror rules */
710 bool floating_veb; /* The flag to use the floating VEB */
711 /* The floating enable flag for the specific VF */
712 bool floating_veb_list[I40E_MAX_VF];
713 struct i40e_flow_list flow_list;
714 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
715 bool qinq_replace_flag; /* QINQ filter replace is done */
719 PFMSG_LINK_CHANGE = 0x1,
720 PFMSG_RESET_IMPENDING = 0x2,
721 PFMSG_DRIVER_CLOSE = 0x4,
724 struct i40e_vsi_vlan_pvid_info {
725 uint16_t on; /* Enable or disable pvid */
727 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
729 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
730 * while 'untagged' will reject untagged packets.
738 struct i40e_vf_rx_queues {
739 uint64_t rx_dma_addr;
740 uint32_t rx_ring_len;
744 struct i40e_vf_tx_queues {
745 uint64_t tx_dma_addr;
746 uint32_t tx_ring_len;
750 * Structure to store private data specific for VF instance.
753 struct i40e_adapter *adapter; /* The adapter this VF associate to */
754 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
755 uint16_t num_queue_pairs;
756 uint16_t max_pkt_len; /* Maximum packet length */
757 bool promisc_unicast_enabled;
758 bool promisc_multicast_enabled;
760 uint32_t version_major; /* Major version number */
761 uint32_t version_minor; /* Minor version number */
762 uint16_t promisc_flags; /* Promiscuous setting */
763 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
768 enum i40e_aq_link_speed link_speed;
770 volatile uint32_t pend_cmd; /* pending command not finished yet */
771 int32_t cmd_retval; /* return value of the cmd response from PF */
772 u16 pend_msg; /* flags indicates events from pf not handled yet */
773 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
776 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
777 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
782 #define I40E_MAX_PKT_TYPE 256
785 * Structure to store private data for each PF/VF instance.
787 struct i40e_adapter {
788 /* Common for both PF and VF */
790 struct rte_eth_dev *eth_dev;
792 /* Specific for PF or VF */
799 bool rx_bulk_alloc_allowed;
801 bool tx_simple_allowed;
805 struct rte_timecounter systime_tc;
806 struct rte_timecounter rx_tstamp_tc;
807 struct rte_timecounter tx_tstamp_tc;
809 /* ptype mapping table */
810 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
813 extern const struct rte_flow_ops i40e_flow_ops;
815 union i40e_filter_t {
816 struct rte_eth_ethertype_filter ethertype_filter;
817 struct rte_eth_fdir_filter fdir_filter;
818 struct rte_eth_tunnel_filter_conf tunnel_filter;
819 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
822 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
823 const struct rte_flow_attr *attr,
824 const struct rte_flow_item pattern[],
825 const struct rte_flow_action actions[],
826 struct rte_flow_error *error,
827 union i40e_filter_t *filter);
828 struct i40e_valid_pattern {
829 enum rte_flow_item_type *items;
830 parse_filter_t parse_filter;
833 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
834 int i40e_vsi_release(struct i40e_vsi *vsi);
835 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
836 enum i40e_vsi_type type,
837 struct i40e_vsi *uplink_vsi,
838 uint16_t user_param);
839 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
840 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
841 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
842 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
843 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
844 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
845 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
846 void i40e_pf_disable_irq0(struct i40e_hw *hw);
847 void i40e_pf_enable_irq0(struct i40e_hw *hw);
848 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
849 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
850 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
851 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
852 struct i40e_vsi_vlan_pvid_info *info);
853 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
854 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
855 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
856 uint64_t i40e_parse_hena(uint64_t flags);
857 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
858 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
859 int i40e_fdir_setup(struct i40e_pf *pf);
860 const struct rte_memzone *i40e_memzone_reserve(const char *name,
863 int i40e_fdir_configure(struct rte_eth_dev *dev);
864 void i40e_fdir_teardown(struct i40e_pf *pf);
865 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
866 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
867 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
868 enum rte_filter_op filter_op,
870 int i40e_select_filter_input_set(struct i40e_hw *hw,
871 struct rte_eth_input_set_conf *conf,
872 enum rte_filter_type filter);
873 void i40e_fdir_filter_restore(struct i40e_pf *pf);
874 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
875 struct rte_eth_input_set_conf *conf);
876 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
877 struct rte_eth_input_set_conf *conf);
878 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
879 uint32_t retval, uint8_t *msg,
881 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
882 struct rte_eth_rxq_info *qinfo);
883 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
884 struct rte_eth_txq_info *qinfo);
885 struct i40e_ethertype_filter *
886 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
887 const struct i40e_ethertype_filter_input *input);
888 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
889 struct i40e_ethertype_filter_input *input);
890 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
891 struct rte_eth_fdir_input *input);
892 struct i40e_tunnel_filter *
893 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
894 const struct i40e_tunnel_filter_input *input);
895 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
896 struct i40e_tunnel_filter_input *input);
897 uint64_t i40e_get_default_input_set(uint16_t pctype);
898 int i40e_ethertype_filter_set(struct i40e_pf *pf,
899 struct rte_eth_ethertype_filter *filter,
901 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
902 const struct rte_eth_fdir_filter *filter,
904 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
905 struct rte_eth_tunnel_filter_conf *tunnel_filter,
907 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
908 struct i40e_tunnel_filter_conf *tunnel_filter,
910 int i40e_fdir_flush(struct rte_eth_dev *dev);
911 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
912 struct i40e_macvlan_filter *mv_f,
913 int num, struct ether_addr *addr);
914 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
915 struct i40e_macvlan_filter *filter,
917 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
918 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
919 struct i40e_macvlan_filter *filter,
921 bool is_i40e_supported(struct rte_eth_dev *dev);
923 /* I40E_DEV_PRIVATE_TO */
924 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
925 (&((struct i40e_adapter *)adapter)->pf)
926 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
927 (&((struct i40e_adapter *)adapter)->hw)
928 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
929 ((struct i40e_adapter *)adapter)
931 /* I40EVF_DEV_PRIVATE_TO */
932 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
933 (&((struct i40e_adapter *)adapter)->vf)
935 static inline struct i40e_vsi *
936 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
943 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
944 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
945 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
952 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
953 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
956 #define I40E_VSI_TO_HW(vsi) \
957 (&(((struct i40e_vsi *)vsi)->adapter->hw))
958 #define I40E_VSI_TO_PF(vsi) \
959 (&(((struct i40e_vsi *)vsi)->adapter->pf))
960 #define I40E_VSI_TO_VF(vsi) \
961 (&(((struct i40e_vsi *)vsi)->adapter->vf))
962 #define I40E_VSI_TO_DEV_DATA(vsi) \
963 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
964 #define I40E_VSI_TO_ETH_DEV(vsi) \
965 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
968 #define I40E_PF_TO_HW(pf) \
969 (&(((struct i40e_pf *)pf)->adapter->hw))
970 #define I40E_PF_TO_ADAPTER(pf) \
971 ((struct i40e_adapter *)pf->adapter)
974 #define I40E_VF_TO_HW(vf) \
975 (&(((struct i40e_vf *)vf)->adapter->hw))
978 i40e_init_adminq_parameter(struct i40e_hw *hw)
980 hw->aq.num_arq_entries = I40E_AQ_LEN;
981 hw->aq.num_asq_entries = I40E_AQ_LEN;
982 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
983 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
987 i40e_align_floor(int n)
991 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
994 static inline uint16_t
995 i40e_calc_itr_interval(int16_t interval)
997 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
998 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1000 /* Convert to hardware count, as writing each 1 represents 2 us */
1001 return interval / 2;
1004 #define I40E_VALID_FLOW(flow_type) \
1005 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1006 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1007 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1008 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1009 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1010 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1011 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1012 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1013 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1014 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1015 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1017 #define I40E_VALID_PCTYPE_X722(pctype) \
1018 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1019 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1020 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1021 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1022 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1023 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1024 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1025 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1026 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1027 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1028 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1029 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1030 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1031 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1032 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1033 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1034 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1036 #define I40E_VALID_PCTYPE(pctype) \
1037 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1038 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1039 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1040 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1041 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1042 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1043 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1044 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1045 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1046 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1047 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1049 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1050 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1051 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1052 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1053 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1054 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1055 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1057 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1058 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1059 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1060 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1061 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1063 #endif /* _I40E_ETHDEV_H_ */