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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
42 #define I40E_VLAN_TAG_SIZE 4
44 #define I40E_AQ_LEN 32
45 #define I40E_AQ_BUF_SZ 4096
46 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
47 #define I40E_MAX_Q_PER_TC 64
48 #define I40E_NUM_DESC_DEFAULT 512
49 #define I40E_NUM_DESC_ALIGN 32
50 #define I40E_BUF_SIZE_MIN 1024
51 #define I40E_FRAME_SIZE_MAX 9728
52 #define I40E_QUEUE_BASE_ADDR_UNIT 128
53 /* number of VSIs and queue default setting */
54 #define I40E_MAX_QP_NUM_PER_VF 16
55 #define I40E_DEFAULT_QP_NUM_FDIR 1
56 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
57 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
58 /* Maximun number of MAC addresses */
59 #define I40E_NUM_MACADDR_MAX 64
60 /* Maximum number of VFs */
61 #define I40E_MAX_VF 128
64 * vlan_id is a 12 bit number.
65 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
66 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
67 * The higher 7 bit val specifies VFTA array index.
69 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
70 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
72 /* Default TC traffic in case DCB is not enabled */
73 #define I40E_DEFAULT_TCMAP 0x1
74 #define I40E_FDIR_QUEUE_ID 0
76 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
77 #define I40E_VMDQ_POOL_BASE 1
79 #define I40E_DEFAULT_RX_FREE_THRESH 32
80 #define I40E_DEFAULT_RX_PTHRESH 8
81 #define I40E_DEFAULT_RX_HTHRESH 8
82 #define I40E_DEFAULT_RX_WTHRESH 0
84 #define I40E_DEFAULT_TX_FREE_THRESH 32
85 #define I40E_DEFAULT_TX_PTHRESH 32
86 #define I40E_DEFAULT_TX_HTHRESH 0
87 #define I40E_DEFAULT_TX_WTHRESH 0
88 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
90 /* Bit shift and mask */
91 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
92 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
93 #define I40E_8_BIT_WIDTH CHAR_BIT
94 #define I40E_8_BIT_MASK UINT8_MAX
95 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
96 #define I40E_16_BIT_MASK UINT16_MAX
97 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
98 #define I40E_32_BIT_MASK UINT32_MAX
99 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
100 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
102 /* Linux PF host with virtchnl version 1.1 */
103 #define PF_IS_V11(vf) \
104 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
105 ((vf)->version_minor == 1))
107 /* index flex payload per layer */
108 enum i40e_flxpld_layer_idx {
109 I40E_FLXPLD_L2_IDX = 0,
110 I40E_FLXPLD_L3_IDX = 1,
111 I40E_FLXPLD_L4_IDX = 2,
112 I40E_MAX_FLXPLD_LAYER = 3,
114 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
115 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
116 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
117 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
118 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
121 #define I40E_FLAG_RSS (1ULL << 0)
122 #define I40E_FLAG_DCB (1ULL << 1)
123 #define I40E_FLAG_VMDQ (1ULL << 2)
124 #define I40E_FLAG_SRIOV (1ULL << 3)
125 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
126 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
127 #define I40E_FLAG_FDIR (1ULL << 6)
128 #define I40E_FLAG_VXLAN (1ULL << 7)
129 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
130 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
134 I40E_FLAG_HEADER_SPLIT_DISABLED | \
135 I40E_FLAG_HEADER_SPLIT_ENABLED | \
138 I40E_FLAG_RSS_AQ_CAPABLE)
140 #define I40E_RSS_OFFLOAD_ALL ( \
141 ETH_RSS_FRAG_IPV4 | \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
144 ETH_RSS_NONFRAG_IPV4_SCTP | \
145 ETH_RSS_NONFRAG_IPV4_OTHER | \
146 ETH_RSS_FRAG_IPV6 | \
147 ETH_RSS_NONFRAG_IPV6_TCP | \
148 ETH_RSS_NONFRAG_IPV6_UDP | \
149 ETH_RSS_NONFRAG_IPV6_SCTP | \
150 ETH_RSS_NONFRAG_IPV6_OTHER | \
153 /* All bits of RSS hash enable for X722*/
154 #define I40E_RSS_HENA_ALL_X722 ( \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
163 /* All bits of RSS hash enable */
164 #define I40E_RSS_HENA_ALL ( \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
169 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
174 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
175 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
177 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
178 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
180 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
181 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
183 /* Default queue interrupt throttling time in microseconds */
184 #define I40E_ITR_INDEX_DEFAULT 0
185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
188 /* Special FW support this floating VEB feature */
189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
195 * MAC filter structure
197 struct i40e_mac_filter_info {
198 enum rte_mac_filter_type filter_type;
199 struct ether_addr mac_addr;
202 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
204 /* MAC filter list structure */
205 struct i40e_mac_filter {
206 TAILQ_ENTRY(i40e_mac_filter) next;
207 struct i40e_mac_filter_info mac_info;
210 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
214 /* VSI list structure */
215 struct i40e_vsi_list {
216 TAILQ_ENTRY(i40e_vsi_list) list;
217 struct i40e_vsi *vsi;
220 struct i40e_rx_queue;
221 struct i40e_tx_queue;
223 /* Bandwidth limit information */
224 struct i40e_bw_info {
225 uint16_t bw_limit; /* BW Limit (0 = disabled) */
226 uint8_t bw_max; /* Max BW limit if enabled */
228 /* Relative credits within same TC with respect to other VSIs or Comps */
229 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
230 /* Bandwidth limit per TC */
231 uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
232 /* Max bandwidth limit per TC */
233 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
236 /* Structure that defines a VEB */
238 struct i40e_vsi_list_head head;
239 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
240 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
241 uint16_t seid; /* The seid of VEB itself */
242 uint16_t uplink_seid; /* The uplink seid of this VEB */
244 struct i40e_eth_stats stats;
245 uint8_t enabled_tc; /* The traffic class enabled */
246 struct i40e_bw_info bw_info; /* VEB bandwidth information */
249 /* i40e MACVLAN filter structure */
250 struct i40e_macvlan_filter {
251 struct ether_addr macaddr;
252 enum rte_mac_filter_type filter_type;
257 * Structure that defines a VSI, associated with a adapter.
260 struct i40e_adapter *adapter; /* Backreference to associated adapter */
261 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
263 struct i40e_eth_stats eth_stats_offset;
264 struct i40e_eth_stats eth_stats;
266 * When drivers loaded, only a default main VSI exists. In case new VSI
267 * needs to add, HW needs to know the layout that VSIs are organized.
268 * Besides that, VSI isan element and can't switch packets, which needs
269 * to add new component VEB to perform switching. So, a new VSI needs
270 * to specify the the uplink VSI (Parent VSI) before created. The
271 * uplink VSI will check whether it had a VEB to switch packets. If no,
272 * it will try to create one. Then, uplink VSI will move the new VSI
273 * into its' sib_vsi_list to manage all the downlink VSI.
274 * sib_vsi_list: the VSI list that shared the same uplink VSI.
275 * parent_vsi : the uplink VSI. It's NULL for main VSI.
276 * veb : the VEB associates with the VSI.
278 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
279 struct i40e_vsi *parent_vsi;
280 struct i40e_veb *veb; /* Associated veb, could be null */
281 struct i40e_veb *floating_veb; /* Associated floating veb */
283 enum i40e_vsi_type type; /* VSI types */
284 uint16_t vlan_num; /* Total VLAN number */
285 uint16_t mac_num; /* Total mac number */
286 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
287 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
288 /* specific VSI-defined parameters, SRIOV stored the vf_id */
290 uint16_t seid; /* The seid of VSI itself */
291 uint16_t uplink_seid; /* The uplink seid of this VSI */
292 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
293 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
294 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
295 uint16_t base_queue; /* The first queue index of this VSI */
297 * The offset to visit VSI related register, assigned by HW when
301 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
302 uint16_t nb_msix; /* The max number of msix vector */
303 uint8_t enabled_tc; /* The traffic class enabled */
304 struct i40e_bw_info bw_info; /* VSI bandwidth information */
308 LIST_ENTRY(pool_entry) next;
313 LIST_HEAD(res_list, pool_entry);
315 struct i40e_res_pool_info {
316 uint32_t base; /* Resource start index */
317 uint32_t num_alloc; /* Allocated resource number */
318 uint32_t num_free; /* Total available resource number */
319 struct res_list alloc_list; /* Allocated resource list */
320 struct res_list free_list; /* Available resource list */
324 I40E_VF_INACTIVE = 0,
331 * Structure to store private data for PF host.
335 struct i40e_vsi *vsi;
336 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
337 uint16_t vf_idx; /* VF index in pf->vfs */
338 uint16_t lan_nb_qps; /* Actual queues allocated */
339 uint16_t reset_cnt; /* Total vf reset times */
340 struct ether_addr mac_addr; /* Default MAC address */
344 * Structure to store private data for flow control.
346 struct i40e_fc_conf {
347 uint16_t pause_time; /* Flow control pause timer */
348 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
349 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
350 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
351 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
355 * Structure to store private data for VMDQ instance
357 struct i40e_vmdq_info {
359 struct i40e_vsi *vsi;
363 * Structure to store flex pit for flow diretor.
365 struct i40e_fdir_flex_pit {
366 uint8_t src_offset; /* offset in words from the beginning of payload */
367 uint8_t size; /* size in words */
368 uint8_t dst_offset; /* offset in words of flexible payload */
371 struct i40e_fdir_flex_mask {
372 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
376 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
379 #define I40E_FILTER_PCTYPE_MAX 64
380 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
382 struct i40e_fdir_filter {
383 TAILQ_ENTRY(i40e_fdir_filter) rules;
384 struct rte_eth_fdir_filter fdir;
387 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
389 * A structure used to define fields of a FDIR related info.
391 struct i40e_fdir_info {
392 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
393 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
394 struct i40e_tx_queue *txq;
395 struct i40e_rx_queue *rxq;
396 void *prg_pkt; /* memory for fdir program packet */
397 uint64_t dma_addr; /* physic address of packet memory*/
398 /* input set bits for each pctype */
399 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
401 * the rule how bytes stream is extracted as flexible payload
402 * for each payload layer, the setting can up to three elements
404 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
405 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
407 struct i40e_fdir_filter_list fdir_list;
408 struct i40e_fdir_filter **hash_map;
409 struct rte_hash *hash_table;
412 /* Ethertype filter number HW supports */
413 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
415 /* Ethertype filter struct */
416 struct i40e_ethertype_filter_input {
417 struct ether_addr mac_addr; /* Mac address to match */
418 uint16_t ether_type; /* Ether type to match */
421 struct i40e_ethertype_filter {
422 TAILQ_ENTRY(i40e_ethertype_filter) rules;
423 struct i40e_ethertype_filter_input input;
424 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
425 uint16_t queue; /* Queue assigned to when match */
428 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
430 struct i40e_ethertype_rule {
431 struct i40e_ethertype_filter_list ethertype_list;
432 struct i40e_ethertype_filter **hash_map;
433 struct rte_hash *hash_table;
436 /* Tunnel filter number HW supports */
437 #define I40E_MAX_TUNNEL_FILTER_NUM 400
439 /* Tunnel filter struct */
440 struct i40e_tunnel_filter_input {
441 uint8_t outer_mac[6]; /* Outer mac address to match */
442 uint8_t inner_mac[6]; /* Inner mac address to match */
443 uint16_t inner_vlan; /* Inner vlan address to match */
444 uint16_t flags; /* Filter type flag */
445 uint32_t tenant_id; /* Tenant id to match */
448 struct i40e_tunnel_filter {
449 TAILQ_ENTRY(i40e_tunnel_filter) rules;
450 struct i40e_tunnel_filter_input input;
451 uint16_t queue; /* Queue assigned to when match */
454 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
456 struct i40e_tunnel_rule {
457 struct i40e_tunnel_filter_list tunnel_list;
458 struct i40e_tunnel_filter **hash_map;
459 struct rte_hash *hash_table;
462 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
463 #define I40E_MAX_MIRROR_RULES 64
465 * Mirror rule structure
467 struct i40e_mirror_rule {
468 TAILQ_ENTRY(i40e_mirror_rule) rules;
470 uint16_t index; /* the sw index of mirror rule */
471 uint16_t id; /* the rule id assigned by firmware */
472 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
473 uint16_t num_entries;
474 /* the info stores depend on the rule type.
475 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
476 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
478 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
481 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
484 * Structure to store private data specific for PF instance.
487 struct i40e_adapter *adapter; /* The adapter this PF associate to */
488 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
489 uint16_t mac_seid; /* The seid of the MAC of this PF */
490 uint16_t main_vsi_seid; /* The seid of the main VSI */
491 uint16_t max_num_vsi;
492 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
493 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
495 struct i40e_hw_port_stats stats_offset;
496 struct i40e_hw_port_stats stats;
499 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
500 struct ether_addr dev_addr; /* PF device mac address */
501 uint64_t flags; /* PF feature flags */
502 /* All kinds of queue pair setting for different VSIs */
503 struct i40e_pf_vf *vfs;
505 /* Each of below queue pairs should be power of 2 since it's the
506 precondition after TC configuration applied */
507 uint16_t lan_nb_qp_max;
508 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
509 uint16_t lan_qp_offset;
510 uint16_t vmdq_nb_qp_max;
511 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
512 uint16_t vmdq_qp_offset;
513 uint16_t vf_nb_qp_max;
514 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
515 uint16_t vf_qp_offset;
516 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
517 uint16_t fdir_qp_offset;
519 uint16_t hash_lut_size; /* The size of hash lookup table */
520 /* input set bits for each pctype */
521 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
522 /* store VXLAN UDP ports */
523 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
524 uint16_t vxlan_bitmap; /* Vxlan bit mask */
526 /* VMDQ related info */
527 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
528 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
529 struct i40e_vmdq_info *vmdq;
531 struct i40e_fdir_info fdir; /* flow director info */
532 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
533 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
534 struct i40e_fc_conf fc_conf; /* Flow control conf */
535 struct i40e_mirror_rule_list mirror_list;
536 uint16_t nb_mirror_rule; /* The number of mirror rules */
537 bool floating_veb; /* The flag to use the floating VEB */
538 /* The floating enable flag for the specific VF */
539 bool floating_veb_list[I40E_MAX_VF];
543 PFMSG_LINK_CHANGE = 0x1,
544 PFMSG_RESET_IMPENDING = 0x2,
545 PFMSG_DRIVER_CLOSE = 0x4,
548 struct i40e_vsi_vlan_pvid_info {
549 uint16_t on; /* Enable or disable pvid */
551 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
553 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
554 * while 'untagged' will reject untagged packets.
562 struct i40e_vf_rx_queues {
563 uint64_t rx_dma_addr;
564 uint32_t rx_ring_len;
568 struct i40e_vf_tx_queues {
569 uint64_t tx_dma_addr;
570 uint32_t tx_ring_len;
574 * Structure to store private data specific for VF instance.
577 struct i40e_adapter *adapter; /* The adapter this VF associate to */
578 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
579 uint16_t num_queue_pairs;
580 uint16_t max_pkt_len; /* Maximum packet length */
581 bool promisc_unicast_enabled;
582 bool promisc_multicast_enabled;
584 uint32_t version_major; /* Major version number */
585 uint32_t version_minor; /* Minor version number */
586 uint16_t promisc_flags; /* Promiscuous setting */
587 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
592 enum i40e_aq_link_speed link_speed;
594 volatile uint32_t pend_cmd; /* pending command not finished yet */
595 int32_t cmd_retval; /* return value of the cmd response from PF */
596 u16 pend_msg; /* flags indicates events from pf not handled yet */
597 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
600 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
601 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
607 * Structure to store private data for each PF/VF instance.
609 struct i40e_adapter {
610 /* Common for both PF and VF */
612 struct rte_eth_dev *eth_dev;
614 /* Specific for PF or VF */
621 bool rx_bulk_alloc_allowed;
623 bool tx_simple_allowed;
627 struct rte_timecounter systime_tc;
628 struct rte_timecounter rx_tstamp_tc;
629 struct rte_timecounter tx_tstamp_tc;
632 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
633 int i40e_vsi_release(struct i40e_vsi *vsi);
634 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
635 enum i40e_vsi_type type,
636 struct i40e_vsi *uplink_vsi,
637 uint16_t user_param);
638 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
639 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
640 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
641 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
642 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
643 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
644 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
645 void i40e_pf_disable_irq0(struct i40e_hw *hw);
646 void i40e_pf_enable_irq0(struct i40e_hw *hw);
647 int i40e_dev_link_update(struct rte_eth_dev *dev,
648 __rte_unused int wait_to_complete);
649 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
650 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
651 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
652 struct i40e_vsi_vlan_pvid_info *info);
653 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
654 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
655 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
656 uint64_t i40e_parse_hena(uint64_t flags);
657 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
658 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
659 int i40e_fdir_setup(struct i40e_pf *pf);
660 const struct rte_memzone *i40e_memzone_reserve(const char *name,
663 int i40e_fdir_configure(struct rte_eth_dev *dev);
664 void i40e_fdir_teardown(struct i40e_pf *pf);
665 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
666 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
667 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
668 enum rte_filter_op filter_op,
670 int i40e_select_filter_input_set(struct i40e_hw *hw,
671 struct rte_eth_input_set_conf *conf,
672 enum rte_filter_type filter);
673 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
674 struct rte_eth_input_set_conf *conf);
675 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
676 struct rte_eth_input_set_conf *conf);
677 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
678 uint32_t retval, uint8_t *msg,
680 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
681 struct rte_eth_rxq_info *qinfo);
682 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
683 struct rte_eth_txq_info *qinfo);
684 struct i40e_ethertype_filter *
685 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
686 const struct i40e_ethertype_filter_input *input);
687 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
688 struct i40e_ethertype_filter_input *input);
689 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
690 struct rte_eth_fdir_input *input);
691 struct i40e_tunnel_filter *
692 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
693 const struct i40e_tunnel_filter_input *input);
694 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
695 struct i40e_tunnel_filter_input *input);
697 #define I40E_DEV_TO_PCI(eth_dev) \
698 RTE_DEV_TO_PCI((eth_dev)->device)
700 /* I40E_DEV_PRIVATE_TO */
701 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
702 (&((struct i40e_adapter *)adapter)->pf)
703 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
704 (&((struct i40e_adapter *)adapter)->hw)
705 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
706 ((struct i40e_adapter *)adapter)
708 /* I40EVF_DEV_PRIVATE_TO */
709 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
710 (&((struct i40e_adapter *)adapter)->vf)
712 static inline struct i40e_vsi *
713 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
720 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
721 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
722 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
725 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
729 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
730 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
733 #define I40E_VSI_TO_HW(vsi) \
734 (&(((struct i40e_vsi *)vsi)->adapter->hw))
735 #define I40E_VSI_TO_PF(vsi) \
736 (&(((struct i40e_vsi *)vsi)->adapter->pf))
737 #define I40E_VSI_TO_VF(vsi) \
738 (&(((struct i40e_vsi *)vsi)->adapter->vf))
739 #define I40E_VSI_TO_DEV_DATA(vsi) \
740 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
741 #define I40E_VSI_TO_ETH_DEV(vsi) \
742 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
745 #define I40E_PF_TO_HW(pf) \
746 (&(((struct i40e_pf *)pf)->adapter->hw))
747 #define I40E_PF_TO_ADAPTER(pf) \
748 ((struct i40e_adapter *)pf->adapter)
751 #define I40E_VF_TO_HW(vf) \
752 (&(((struct i40e_vf *)vf)->adapter->hw))
755 i40e_init_adminq_parameter(struct i40e_hw *hw)
757 hw->aq.num_arq_entries = I40E_AQ_LEN;
758 hw->aq.num_asq_entries = I40E_AQ_LEN;
759 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
760 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
764 i40e_align_floor(int n)
768 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
771 static inline uint16_t
772 i40e_calc_itr_interval(int16_t interval)
774 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
775 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
777 /* Convert to hardware count, as writing each 1 represents 2 us */
781 #define I40E_VALID_FLOW(flow_type) \
782 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
783 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
784 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
785 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
786 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
787 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
788 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
789 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
790 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
791 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
792 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
794 #define I40E_VALID_PCTYPE_X722(pctype) \
795 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
796 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
797 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
798 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
799 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
800 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
801 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
802 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
803 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
804 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
805 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
806 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
807 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
808 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
809 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
810 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
811 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
813 #define I40E_VALID_PCTYPE(pctype) \
814 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
815 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
816 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
817 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
818 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
819 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
820 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
821 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
822 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
823 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
824 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
826 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
827 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
828 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
829 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
830 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
831 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
832 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
834 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
835 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
836 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
837 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
838 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
840 #endif /* _I40E_ETHDEV_H_ */