1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
11 #include <rte_kvargs.h>
14 #include <rte_flow_driver.h>
15 #include <rte_tm_driver.h>
16 #include "rte_pmd_i40e.h"
18 #include "base/i40e_register.h"
20 #define I40E_VLAN_TAG_SIZE 4
22 #define I40E_AQ_LEN 32
23 #define I40E_AQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define I40E_MAX_Q_PER_TC 64
26 #define I40E_NUM_DESC_DEFAULT 512
27 #define I40E_NUM_DESC_ALIGN 32
28 #define I40E_BUF_SIZE_MIN 1024
29 #define I40E_FRAME_SIZE_MAX 9728
30 #define I40E_TSO_FRAME_SIZE_MAX 262144
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
90 struct rte_eth_dev *dev; \
91 ori_val = I40E_READ_REG((hw), (reg)); \
92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
95 if (ori_val != value) \
96 PMD_DRV_LOG(WARNING, \
97 "i40e device %s changed global " \
98 "register [0x%08x]. original: 0x%08x, " \
100 (dev->device->name), (reg), \
101 (ori_val), (value)); \
104 /* index flex payload per layer */
105 enum i40e_flxpld_layer_idx {
106 I40E_FLXPLD_L2_IDX = 0,
107 I40E_FLXPLD_L3_IDX = 1,
108 I40E_FLXPLD_L4_IDX = 2,
109 I40E_MAX_FLXPLD_LAYER = 3,
111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
118 #define I40E_FLAG_RSS (1ULL << 0)
119 #define I40E_FLAG_DCB (1ULL << 1)
120 #define I40E_FLAG_VMDQ (1ULL << 2)
121 #define I40E_FLAG_SRIOV (1ULL << 3)
122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
124 #define I40E_FLAG_FDIR (1ULL << 6)
125 #define I40E_FLAG_VXLAN (1ULL << 7)
126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
131 I40E_FLAG_HEADER_SPLIT_DISABLED | \
132 I40E_FLAG_HEADER_SPLIT_ENABLED | \
135 I40E_FLAG_RSS_AQ_CAPABLE)
137 #define I40E_RSS_OFFLOAD_ALL ( \
138 ETH_RSS_FRAG_IPV4 | \
139 ETH_RSS_NONFRAG_IPV4_TCP | \
140 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV4_SCTP | \
142 ETH_RSS_NONFRAG_IPV4_OTHER | \
143 ETH_RSS_FRAG_IPV6 | \
144 ETH_RSS_NONFRAG_IPV6_TCP | \
145 ETH_RSS_NONFRAG_IPV6_UDP | \
146 ETH_RSS_NONFRAG_IPV6_SCTP | \
147 ETH_RSS_NONFRAG_IPV6_OTHER | \
150 /* All bits of RSS hash enable for X722*/
151 #define I40E_RSS_HENA_ALL_X722 ( \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
160 /* All bits of RSS hash enable */
161 #define I40E_RSS_HENA_ALL ( \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
180 /* Default queue interrupt throttling time in microseconds */
181 #define I40E_ITR_INDEX_DEFAULT 0
182 #define I40E_ITR_INDEX_NONE 3
183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 /* Special FW support this floating VEB feature */
187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
195 #define I40E_INSET_NONE 0x00000000000000000ULL
198 #define I40E_INSET_DMAC 0x0000000000000001ULL
199 #define I40E_INSET_SMAC 0x0000000000000002ULL
200 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
201 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
202 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
205 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
206 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
207 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
208 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
209 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
210 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
211 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
213 /* bit 16 ~ bit 31 */
214 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
215 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
216 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
217 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
218 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
219 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
220 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
221 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
223 /* bit 32 ~ bit 47, tunnel fields */
224 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
225 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
226 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
227 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
228 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
229 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
231 /* bit 48 ~ bit 55 */
232 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
234 /* bit 56 ~ bit 63, Flex Payload */
235 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
236 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
237 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
238 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD \
244 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
245 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
246 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
247 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
249 /* The max bandwidth of i40e is 40Gbps. */
250 #define I40E_QOS_BW_MAX 40000
251 /* The bandwidth should be the multiple of 50Mbps. */
252 #define I40E_QOS_BW_GRANULARITY 50
253 /* The min bandwidth weight is 1. */
254 #define I40E_QOS_BW_WEIGHT_MIN 1
255 /* The max bandwidth weight is 127. */
256 #define I40E_QOS_BW_WEIGHT_MAX 127
257 /* The max queue region index is 7. */
258 #define I40E_REGION_MAX_INDEX 7
260 #define I40E_MAX_PERCENT 100
261 #define I40E_DEFAULT_DCB_APP_NUM 1
262 #define I40E_DEFAULT_DCB_APP_PRIO 3
265 * The overhead from MTU to max frame size.
266 * Considering QinQ packet, the VLAN tag needs to be counted twice.
268 #define I40E_ETH_OVERHEAD \
269 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
272 struct rte_pci_driver;
275 * MAC filter structure
277 struct i40e_mac_filter_info {
278 enum rte_mac_filter_type filter_type;
279 struct rte_ether_addr mac_addr;
282 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
284 /* MAC filter list structure */
285 struct i40e_mac_filter {
286 TAILQ_ENTRY(i40e_mac_filter) next;
287 struct i40e_mac_filter_info mac_info;
290 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
294 /* VSI list structure */
295 struct i40e_vsi_list {
296 TAILQ_ENTRY(i40e_vsi_list) list;
297 struct i40e_vsi *vsi;
300 struct i40e_rx_queue;
301 struct i40e_tx_queue;
303 /* Bandwidth limit information */
304 struct i40e_bw_info {
305 uint16_t bw_limit; /* BW Limit (0 = disabled) */
306 uint8_t bw_max; /* Max BW limit if enabled */
308 /* Relative credits within same TC with respect to other VSIs or Comps */
309 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
310 /* Bandwidth limit per TC */
311 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
312 /* Max bandwidth limit per TC */
313 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
316 /* Structure that defines a VEB */
318 struct i40e_vsi_list_head head;
319 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
320 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
321 uint16_t seid; /* The seid of VEB itself */
322 uint16_t uplink_seid; /* The uplink seid of this VEB */
324 struct i40e_eth_stats stats;
325 uint8_t enabled_tc; /* The traffic class enabled */
326 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
327 struct i40e_bw_info bw_info; /* VEB bandwidth information */
330 /* i40e MACVLAN filter structure */
331 struct i40e_macvlan_filter {
332 struct rte_ether_addr macaddr;
333 enum rte_mac_filter_type filter_type;
338 * Structure that defines a VSI, associated with a adapter.
341 struct i40e_adapter *adapter; /* Backreference to associated adapter */
342 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
344 struct i40e_eth_stats eth_stats_offset;
345 struct i40e_eth_stats eth_stats;
347 * When drivers loaded, only a default main VSI exists. In case new VSI
348 * needs to add, HW needs to know the layout that VSIs are organized.
349 * Besides that, VSI isan element and can't switch packets, which needs
350 * to add new component VEB to perform switching. So, a new VSI needs
351 * to specify the uplink VSI (Parent VSI) before created. The
352 * uplink VSI will check whether it had a VEB to switch packets. If no,
353 * it will try to create one. Then, uplink VSI will move the new VSI
354 * into its' sib_vsi_list to manage all the downlink VSI.
355 * sib_vsi_list: the VSI list that shared the same uplink VSI.
356 * parent_vsi : the uplink VSI. It's NULL for main VSI.
357 * veb : the VEB associates with the VSI.
359 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
360 struct i40e_vsi *parent_vsi;
361 struct i40e_veb *veb; /* Associated veb, could be null */
362 struct i40e_veb *floating_veb; /* Associated floating veb */
364 enum i40e_vsi_type type; /* VSI types */
365 uint16_t vlan_num; /* Total VLAN number */
366 uint16_t mac_num; /* Total mac number */
367 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
368 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
369 /* specific VSI-defined parameters, SRIOV stored the vf_id */
371 uint16_t seid; /* The seid of VSI itself */
372 uint16_t uplink_seid; /* The uplink seid of this VSI */
373 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
374 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
375 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
376 uint16_t base_queue; /* The first queue index of this VSI */
378 * The offset to visit VSI related register, assigned by HW when
382 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
383 uint16_t nb_msix; /* The max number of msix vector */
384 uint8_t enabled_tc; /* The traffic class enabled */
385 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
386 uint8_t vlan_filter_on; /* The VLAN filter enabled */
387 struct i40e_bw_info bw_info; /* VSI bandwidth information */
391 LIST_ENTRY(pool_entry) next;
396 LIST_HEAD(res_list, pool_entry);
398 struct i40e_res_pool_info {
399 uint32_t base; /* Resource start index */
400 uint32_t num_alloc; /* Allocated resource number */
401 uint32_t num_free; /* Total available resource number */
402 struct res_list alloc_list; /* Allocated resource list */
403 struct res_list free_list; /* Available resource list */
407 I40E_VF_INACTIVE = 0,
414 * Structure to store private data for PF host.
418 struct i40e_vsi *vsi;
419 enum I40E_VF_STATE state; /* The number of queue pairs available */
420 uint16_t vf_idx; /* VF index in pf->vfs */
421 uint16_t lan_nb_qps; /* Actual queues allocated */
422 uint16_t reset_cnt; /* Total vf reset times */
423 struct rte_ether_addr mac_addr; /* Default MAC address */
424 /* version of the virtchnl from VF */
425 struct virtchnl_version_info version;
426 uint32_t request_caps; /* offload caps requested from VF */
427 uint64_t num_mdd_events; /* num of mdd events detected */
430 * Variables for store the arrival timestamp of VF messages.
431 * If the timestamp of latest message stored at
432 * `msg_timestamps[index % max]` then the timestamp of
433 * earliest message stored at `msg_time[(index + 1) % max]`.
434 * When a new message come, the timestamp of this message
435 * will be stored at `msg_timestamps[(index + 1) % max]` and the
436 * earliest message timestamp is at
437 * `msg_timestamps[(index + 2) % max]` now...
440 uint64_t *msg_timestamps;
442 /* cycle of stop ignoring VF message */
443 uint64_t ignore_end_cycle;
447 * Structure to store private data for flow control.
449 struct i40e_fc_conf {
450 uint16_t pause_time; /* Flow control pause timer */
451 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
452 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
453 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
454 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
458 * Structure to store private data for VMDQ instance
460 struct i40e_vmdq_info {
462 struct i40e_vsi *vsi;
465 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
466 #define I40E_MAX_FLX_SOURCE_OFF 480
467 #define NONUSE_FLX_PIT_DEST_OFF 63
468 #define NONUSE_FLX_PIT_FSIZE 1
469 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
470 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
471 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
472 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
473 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
474 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
475 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
476 NONUSE_FLX_PIT_DEST_OFF : \
477 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
478 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
479 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
480 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
481 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
482 #define I40E_FDIR_IPv6_TC_OFFSET 20
484 /* A structure used to define the input for GTP flow */
485 struct i40e_gtp_flow {
486 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
487 uint8_t msg_type; /* Message type. */
488 uint32_t teid; /* TEID in big endian. */
491 /* A structure used to define the input for GTP IPV4 flow */
492 struct i40e_gtp_ipv4_flow {
493 struct i40e_gtp_flow gtp;
494 struct rte_eth_ipv4_flow ip4;
497 /* A structure used to define the input for GTP IPV6 flow */
498 struct i40e_gtp_ipv6_flow {
499 struct i40e_gtp_flow gtp;
500 struct rte_eth_ipv6_flow ip6;
503 /* A structure used to define the input for ESP IPV4 flow */
504 struct i40e_esp_ipv4_flow {
505 struct rte_eth_ipv4_flow ipv4;
506 uint32_t spi; /* SPI in big endian. */
509 /* A structure used to define the input for ESP IPV6 flow */
510 struct i40e_esp_ipv6_flow {
511 struct rte_eth_ipv6_flow ipv6;
512 uint32_t spi; /* SPI in big endian. */
514 /* A structure used to define the input for ESP IPV4 UDP flow */
515 struct i40e_esp_ipv4_udp_flow {
516 struct rte_eth_udpv4_flow udp;
517 uint32_t spi; /* SPI in big endian. */
520 /* A structure used to define the input for ESP IPV6 UDP flow */
521 struct i40e_esp_ipv6_udp_flow {
522 struct rte_eth_udpv6_flow udp;
523 uint32_t spi; /* SPI in big endian. */
526 /* A structure used to define the input for raw type flow */
527 struct i40e_raw_flow {
533 /* A structure used to define the input for L2TPv3 over IPv4 flow */
534 struct i40e_ipv4_l2tpv3oip_flow {
535 struct rte_eth_ipv4_flow ip4;
536 uint32_t session_id; /* Session ID in big endian. */
539 /* A structure used to define the input for L2TPv3 over IPv6 flow */
540 struct i40e_ipv6_l2tpv3oip_flow {
541 struct rte_eth_ipv6_flow ip6;
542 uint32_t session_id; /* Session ID in big endian. */
545 /* A structure used to define the input for l2 dst type flow */
546 struct i40e_l2_flow {
547 struct rte_ether_addr dst;
548 struct rte_ether_addr src;
549 uint16_t ether_type; /**< Ether type in big endian */
553 * A union contains the inputs for all types of flow
554 * items in flows need to be in big endian
556 union i40e_fdir_flow {
557 struct i40e_l2_flow l2_flow;
558 struct rte_eth_udpv4_flow udp4_flow;
559 struct rte_eth_tcpv4_flow tcp4_flow;
560 struct rte_eth_sctpv4_flow sctp4_flow;
561 struct rte_eth_ipv4_flow ip4_flow;
562 struct rte_eth_udpv6_flow udp6_flow;
563 struct rte_eth_tcpv6_flow tcp6_flow;
564 struct rte_eth_sctpv6_flow sctp6_flow;
565 struct rte_eth_ipv6_flow ipv6_flow;
566 struct i40e_gtp_flow gtp_flow;
567 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
568 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
569 struct i40e_raw_flow raw_flow;
570 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow;
571 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow;
572 struct i40e_esp_ipv4_flow esp_ipv4_flow;
573 struct i40e_esp_ipv6_flow esp_ipv6_flow;
574 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow;
575 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow;
578 enum i40e_fdir_ip_type {
579 I40E_FDIR_IPTYPE_IPV4,
580 I40E_FDIR_IPTYPE_IPV6,
583 /* A structure used to contain extend input of flow */
584 struct i40e_fdir_flow_ext {
586 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
587 /* It is filled by the flexible payload to match. */
588 uint8_t is_vf; /* 1 for VF, 0 for port dev */
589 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
590 bool inner_ip; /* If there is inner ip */
591 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
592 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */
593 bool customized_pctype; /* If customized pctype is used */
594 bool pkt_template; /* If raw packet template is used */
595 bool is_udp; /* ipv4|ipv6 udp flow */
598 /* A structure used to define the input for a flow director filter entry */
599 struct i40e_fdir_input {
600 enum i40e_filter_pctype pctype;
601 union i40e_fdir_flow flow;
602 /* Flow fields to match, dependent on flow_type */
603 struct i40e_fdir_flow_ext flow_ext;
604 /* Additional fields to match */
607 /* Behavior will be taken if FDIR match */
608 enum i40e_fdir_behavior {
609 I40E_FDIR_ACCEPT = 0,
614 /* Flow director report status
615 * It defines what will be reported if FDIR entry is matched.
617 enum i40e_fdir_status {
618 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
619 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
620 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
621 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
624 /* A structure used to define an action when match FDIR packet filter. */
625 struct i40e_fdir_action {
626 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
627 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
628 enum i40e_fdir_status report_status; /* Status report option */
629 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
630 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
631 * flex bytes start from in flexible payload.
636 /* A structure used to define the flow director filter entry by filter_ctrl API
637 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
638 * RTE_ETH_FILTER_DELETE operations.
640 struct i40e_fdir_filter_conf {
642 /* ID, an unique value is required when deal with FDIR entry */
643 struct i40e_fdir_input input; /* Input set */
644 struct i40e_fdir_action action; /* Action taken when match */
648 * Structure to store flex pit for flow diretor.
650 struct i40e_fdir_flex_pit {
651 uint8_t src_offset; /* offset in words from the beginning of payload */
652 uint8_t size; /* size in words */
653 uint8_t dst_offset; /* offset in words of flexible payload */
656 struct i40e_fdir_flex_mask {
657 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
662 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
665 #define I40E_FILTER_PCTYPE_INVALID 0
666 #define I40E_FILTER_PCTYPE_MAX 64
667 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
669 struct i40e_fdir_filter {
670 TAILQ_ENTRY(i40e_fdir_filter) rules;
671 struct i40e_fdir_filter_conf fdir;
674 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
676 * A structure used to define fields of a FDIR related info.
678 struct i40e_fdir_info {
679 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
680 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
681 struct i40e_tx_queue *txq;
682 struct i40e_rx_queue *rxq;
683 void *prg_pkt; /* memory for fdir program packet */
684 uint64_t dma_addr; /* physic address of packet memory*/
685 /* input set bits for each pctype */
686 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
688 * the rule how bytes stream is extracted as flexible payload
689 * for each payload layer, the setting can up to three elements
691 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
692 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
694 struct i40e_fdir_filter_list fdir_list;
695 struct i40e_fdir_filter **hash_map;
696 struct rte_hash *hash_table;
698 /* Mark if flex pit and mask is set */
699 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
700 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
702 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
705 /* Ethertype filter number HW supports */
706 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
708 /* Ethertype filter struct */
709 struct i40e_ethertype_filter_input {
710 struct rte_ether_addr mac_addr; /* Mac address to match */
711 uint16_t ether_type; /* Ether type to match */
714 struct i40e_ethertype_filter {
715 TAILQ_ENTRY(i40e_ethertype_filter) rules;
716 struct i40e_ethertype_filter_input input;
717 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
718 uint16_t queue; /* Queue assigned to when match */
721 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
723 struct i40e_ethertype_rule {
724 struct i40e_ethertype_filter_list ethertype_list;
725 struct i40e_ethertype_filter **hash_map;
726 struct rte_hash *hash_table;
729 /* queue region info */
730 struct i40e_queue_region_info {
731 /* the region id for this configuration */
733 /* the start queue index for this region */
734 uint8_t queue_start_index;
735 /* the total queue number of this queue region */
737 /* the total number of user priority for this region */
738 uint8_t user_priority_num;
739 /* the packet's user priority for this region */
740 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
741 /* the total number of flowtype for this region */
742 uint8_t flowtype_num;
744 * the pctype or hardware flowtype of packet,
745 * the specific index for each type has been defined
746 * in file i40e_type.h as enum i40e_filter_pctype.
748 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
751 struct i40e_queue_regions {
752 /* the total number of queue region for this port */
753 uint16_t queue_region_number;
754 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
757 /* Tunnel filter number HW supports */
758 #define I40E_MAX_TUNNEL_FILTER_NUM 400
760 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
761 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
762 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
763 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
764 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
765 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
766 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
767 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
768 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
769 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
770 #define I40E_AQC_NEW_TR_21 21
771 #define I40E_AQC_NEW_TR_22 22
773 enum i40e_tunnel_iptype {
774 I40E_TUNNEL_IPTYPE_IPV4,
775 I40E_TUNNEL_IPTYPE_IPV6,
778 /* Tunnel filter struct */
779 struct i40e_tunnel_filter_input {
780 uint8_t outer_mac[6]; /* Outer mac address to match */
781 uint8_t inner_mac[6]; /* Inner mac address to match */
782 uint16_t inner_vlan; /* Inner vlan address to match */
783 enum i40e_tunnel_iptype ip_type;
784 uint16_t flags; /* Filter type flag */
785 uint32_t tenant_id; /* Tenant id to match */
786 uint16_t general_fields[32]; /* Big buffer */
789 struct i40e_tunnel_filter {
790 TAILQ_ENTRY(i40e_tunnel_filter) rules;
791 struct i40e_tunnel_filter_input input;
792 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
793 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
794 uint16_t queue; /* Queue assigned to when match */
797 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
799 struct i40e_tunnel_rule {
800 struct i40e_tunnel_filter_list tunnel_list;
801 struct i40e_tunnel_filter **hash_map;
802 struct rte_hash *hash_table;
808 enum i40e_tunnel_type {
809 I40E_TUNNEL_TYPE_NONE = 0,
810 I40E_TUNNEL_TYPE_VXLAN,
811 I40E_TUNNEL_TYPE_GENEVE,
812 I40E_TUNNEL_TYPE_TEREDO,
813 I40E_TUNNEL_TYPE_NVGRE,
814 I40E_TUNNEL_TYPE_IP_IN_GRE,
815 I40E_L2_TUNNEL_TYPE_E_TAG,
816 I40E_TUNNEL_TYPE_MPLSoUDP,
817 I40E_TUNNEL_TYPE_MPLSoGRE,
818 I40E_TUNNEL_TYPE_QINQ,
819 I40E_TUNNEL_TYPE_GTPC,
820 I40E_TUNNEL_TYPE_GTPU,
821 I40E_TUNNEL_TYPE_ESPoUDP,
822 I40E_TUNNEL_TYPE_ESPoIP,
823 I40E_TUNNEL_TYPE_MAX,
827 * Tunneling Packet filter configuration.
829 struct i40e_tunnel_filter_conf {
830 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */
831 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */
832 uint16_t inner_vlan; /**< Inner VLAN to match. */
833 uint32_t outer_vlan; /**< Outer VLAN to match */
834 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
836 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
837 * is set in filter_type, or inner destination IP address to match
838 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
841 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
842 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
844 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
845 uint16_t filter_type;
846 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
847 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
848 uint16_t queue_id; /**< Queue assigned to if match. */
849 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
850 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
853 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
854 #define I40E_MAX_MIRROR_RULES 64
856 * Mirror rule structure
858 struct i40e_mirror_rule {
859 TAILQ_ENTRY(i40e_mirror_rule) rules;
861 uint16_t index; /* the sw index of mirror rule */
862 uint16_t id; /* the rule id assigned by firmware */
863 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
864 uint16_t num_entries;
865 /* the info stores depend on the rule type.
866 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
867 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
869 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
872 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
875 * Struct to store flow created.
878 TAILQ_ENTRY(rte_flow) node;
879 enum rte_filter_type filter_type;
883 TAILQ_HEAD(i40e_flow_list, rte_flow);
885 /* Struct to store Traffic Manager shaper profile. */
886 struct i40e_tm_shaper_profile {
887 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
888 uint32_t shaper_profile_id;
889 uint32_t reference_count;
890 struct rte_tm_shaper_params profile;
893 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
895 /* node type of Traffic Manager */
896 enum i40e_tm_node_type {
897 I40E_TM_NODE_TYPE_PORT,
898 I40E_TM_NODE_TYPE_TC,
899 I40E_TM_NODE_TYPE_QUEUE,
900 I40E_TM_NODE_TYPE_MAX,
903 /* Struct to store Traffic Manager node configuration. */
904 struct i40e_tm_node {
905 TAILQ_ENTRY(i40e_tm_node) node;
909 uint32_t reference_count;
910 struct i40e_tm_node *parent;
911 struct i40e_tm_shaper_profile *shaper_profile;
912 struct rte_tm_node_params params;
915 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
917 /* Struct to store all the Traffic Manager configuration. */
918 struct i40e_tm_conf {
919 struct i40e_shaper_profile_list shaper_profile_list;
920 struct i40e_tm_node *root; /* root node - port */
921 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
922 struct i40e_tm_node_list queue_list; /* node list for all the queues */
924 * The number of added TC nodes.
925 * It should be no more than the TC number of this port.
929 * The number of added queue nodes.
930 * It should be no more than the queue number of this port.
932 uint32_t nb_queue_node;
934 * This flag is used to check if APP can change the TM node
936 * When it's true, means the configuration is applied to HW,
937 * APP should not change the configuration.
938 * As we don't support on-the-fly configuration, when starting
939 * the port, APP should call the hierarchy_commit API to set this
940 * flag to true. When stopping the port, this flag should be set
946 enum i40e_new_pctype {
947 I40E_CUSTOMIZED_GTPC = 0,
948 I40E_CUSTOMIZED_GTPU_IPV4,
949 I40E_CUSTOMIZED_GTPU_IPV6,
950 I40E_CUSTOMIZED_GTPU,
951 I40E_CUSTOMIZED_IPV4_L2TPV3,
952 I40E_CUSTOMIZED_IPV6_L2TPV3,
953 I40E_CUSTOMIZED_ESP_IPV4,
954 I40E_CUSTOMIZED_ESP_IPV6,
955 I40E_CUSTOMIZED_ESP_IPV4_UDP,
956 I40E_CUSTOMIZED_ESP_IPV6_UDP,
957 I40E_CUSTOMIZED_AH_IPV4,
958 I40E_CUSTOMIZED_AH_IPV6,
962 #define I40E_FILTER_PCTYPE_INVALID 0
963 struct i40e_customized_pctype {
964 enum i40e_new_pctype index; /* Indicate which customized pctype */
965 uint8_t pctype; /* New pctype value */
966 bool valid; /* Check if it's valid */
969 struct i40e_rte_flow_rss_conf {
970 struct rte_flow_action_rss conf; /**< RSS parameters. */
971 uint16_t queue_region_conf; /**< Queue region config flag */
972 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
973 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
974 sizeof(uint32_t)]; /* Hash key. */
975 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
978 struct i40e_vf_msg_cfg {
979 /* maximal VF message during a statistic period */
982 /* statistic period, in second */
985 * If message statistics from a VF exceed the maximal limitation,
986 * the PF will ignore any new message from that VF for
987 * 'ignor_second' time.
989 uint32_t ignore_second;
993 * Structure to store private data specific for PF instance.
996 struct i40e_adapter *adapter; /* The adapter this PF associate to */
997 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
998 uint16_t mac_seid; /* The seid of the MAC of this PF */
999 uint16_t main_vsi_seid; /* The seid of the main VSI */
1000 uint16_t max_num_vsi;
1001 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
1002 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
1004 struct i40e_hw_port_stats stats_offset;
1005 struct i40e_hw_port_stats stats;
1006 /* internal packet statistics, it should be excluded from the total */
1007 struct i40e_eth_stats internal_stats_offset;
1008 struct i40e_eth_stats internal_stats;
1011 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1012 struct rte_ether_addr dev_addr; /* PF device mac address */
1013 uint64_t flags; /* PF feature flags */
1014 /* All kinds of queue pair setting for different VSIs */
1015 struct i40e_pf_vf *vfs;
1017 /* Each of below queue pairs should be power of 2 since it's the
1018 precondition after TC configuration applied */
1019 uint16_t lan_nb_qp_max;
1020 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
1021 uint16_t lan_qp_offset;
1022 uint16_t vmdq_nb_qp_max;
1023 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
1024 uint16_t vmdq_qp_offset;
1025 uint16_t vf_nb_qp_max;
1026 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
1027 uint16_t vf_qp_offset;
1028 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
1029 uint16_t fdir_qp_offset;
1031 uint16_t hash_lut_size; /* The size of hash lookup table */
1032 /* input set bits for each pctype */
1033 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
1034 /* store VXLAN UDP ports */
1035 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
1036 uint16_t vxlan_bitmap; /* Vxlan bit mask */
1038 /* VMDQ related info */
1039 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
1040 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
1041 struct i40e_vmdq_info *vmdq;
1043 struct i40e_fdir_info fdir; /* flow director info */
1044 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
1045 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
1046 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
1047 struct i40e_queue_regions queue_region; /* queue region info */
1048 struct i40e_fc_conf fc_conf; /* Flow control conf */
1049 struct i40e_mirror_rule_list mirror_list;
1050 uint16_t nb_mirror_rule; /* The number of mirror rules */
1051 bool floating_veb; /* The flag to use the floating VEB */
1052 /* The floating enable flag for the specific VF */
1053 bool floating_veb_list[I40E_MAX_VF];
1054 struct i40e_flow_list flow_list;
1055 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
1056 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
1057 bool qinq_replace_flag; /* QINQ filter replace is done */
1058 struct i40e_tm_conf tm_conf;
1059 bool support_multi_driver; /* 1 - support multiple driver */
1061 /* Dynamic Device Personalization */
1062 bool gtp_support; /* 1 - support GTP-C and GTP-U */
1063 bool esp_support; /* 1 - support ESP SPI */
1064 /* customer customized pctype */
1065 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
1066 /* Switch Domain Id */
1067 uint16_t switch_domain_id;
1069 struct i40e_vf_msg_cfg vf_msg_cfg;
1073 PFMSG_LINK_CHANGE = 0x1,
1074 PFMSG_RESET_IMPENDING = 0x2,
1075 PFMSG_DRIVER_CLOSE = 0x4,
1078 struct i40e_vsi_vlan_pvid_info {
1079 uint16_t on; /* Enable or disable pvid */
1081 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
1083 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
1084 * while 'untagged' will reject untagged packets.
1092 struct i40e_vf_rx_queues {
1093 uint64_t rx_dma_addr;
1094 uint32_t rx_ring_len;
1098 struct i40e_vf_tx_queues {
1099 uint64_t tx_dma_addr;
1100 uint32_t tx_ring_len;
1104 * Structure to store private data specific for VF instance.
1107 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1108 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1109 uint16_t num_queue_pairs;
1110 uint16_t max_pkt_len; /* Maximum packet length */
1111 bool promisc_unicast_enabled;
1112 bool promisc_multicast_enabled;
1114 uint32_t version_major; /* Major version number */
1115 uint32_t version_minor; /* Minor version number */
1116 uint16_t promisc_flags; /* Promiscuous setting */
1117 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1119 /* Multicast addrs */
1120 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX];
1121 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1126 enum virtchnl_link_speed link_speed;
1128 volatile uint32_t pend_cmd; /* pending command not finished yet */
1129 int32_t cmd_retval; /* return value of the cmd response from PF */
1130 u16 pend_msg; /* flags indicates events from pf not handled yet */
1131 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1134 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1135 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1136 struct i40e_vsi vsi;
1140 #define I40E_MAX_PKT_TYPE 256
1141 #define I40E_FLOW_TYPE_MAX 64
1144 * Structure to store private data for each PF/VF instance.
1146 struct i40e_adapter {
1147 /* Common for both PF and VF */
1149 struct rte_eth_dev *eth_dev;
1151 /* Specific for PF or VF */
1157 /* For vector PMD */
1158 bool rx_bulk_alloc_allowed;
1159 bool rx_vec_allowed;
1160 bool tx_simple_allowed;
1161 bool tx_vec_allowed;
1164 struct rte_timecounter systime_tc;
1165 struct rte_timecounter rx_tstamp_tc;
1166 struct rte_timecounter tx_tstamp_tc;
1168 /* ptype mapping table */
1169 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1170 /* flow type to pctype mapping table */
1171 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1172 uint64_t flow_types_mask;
1173 uint64_t pctypes_mask;
1176 uint8_t use_latest_vec;
1178 /* For RSS reta table update */
1179 uint8_t rss_reta_updated;
1183 * Strucute to store private data for each VF representor instance
1185 struct i40e_vf_representor {
1186 uint16_t switch_domain_id;
1187 /**< Virtual Function ID */
1189 /**< Virtual Function ID */
1190 struct i40e_adapter *adapter;
1191 /**< Private data store of assocaiated physical function */
1192 struct i40e_eth_stats stats_offset;
1193 /**< Zero-point of VF statistics*/
1196 extern const struct rte_flow_ops i40e_flow_ops;
1198 union i40e_filter_t {
1199 struct rte_eth_ethertype_filter ethertype_filter;
1200 struct i40e_fdir_filter_conf fdir_filter;
1201 struct rte_eth_tunnel_filter_conf tunnel_filter;
1202 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1203 struct i40e_rte_flow_rss_conf rss_conf;
1206 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1207 const struct rte_flow_attr *attr,
1208 const struct rte_flow_item pattern[],
1209 const struct rte_flow_action actions[],
1210 struct rte_flow_error *error,
1211 union i40e_filter_t *filter);
1212 struct i40e_valid_pattern {
1213 enum rte_flow_item_type *items;
1214 parse_filter_t parse_filter;
1217 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1218 int i40e_vsi_release(struct i40e_vsi *vsi);
1219 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1220 enum i40e_vsi_type type,
1221 struct i40e_vsi *uplink_vsi,
1222 uint16_t user_param);
1223 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1224 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1225 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1226 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1227 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1228 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr);
1229 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1230 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1231 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1232 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1233 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1234 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1235 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1236 struct i40e_vsi_vlan_pvid_info *info);
1237 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1238 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1239 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1240 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1241 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1242 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1243 int i40e_fdir_setup(struct i40e_pf *pf);
1244 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1247 int i40e_fdir_configure(struct rte_eth_dev *dev);
1248 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on);
1249 void i40e_fdir_teardown(struct i40e_pf *pf);
1250 enum i40e_filter_pctype
1251 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1252 uint16_t flow_type);
1253 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1254 enum i40e_filter_pctype pctype);
1255 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1256 enum rte_filter_op filter_op,
1258 int i40e_select_filter_input_set(struct i40e_hw *hw,
1259 struct rte_eth_input_set_conf *conf,
1260 enum rte_filter_type filter);
1261 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1262 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1263 struct rte_eth_input_set_conf *conf);
1264 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1265 struct rte_eth_input_set_conf *conf);
1266 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1267 uint32_t retval, uint8_t *msg,
1269 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1270 struct rte_eth_rxq_info *qinfo);
1271 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1272 struct rte_eth_txq_info *qinfo);
1273 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1274 struct rte_eth_burst_mode *mode);
1275 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1276 struct rte_eth_burst_mode *mode);
1277 struct i40e_ethertype_filter *
1278 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1279 const struct i40e_ethertype_filter_input *input);
1280 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1281 struct i40e_ethertype_filter_input *input);
1282 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1283 struct i40e_fdir_input *input);
1284 struct i40e_tunnel_filter *
1285 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1286 const struct i40e_tunnel_filter_input *input);
1287 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1288 struct i40e_tunnel_filter_input *input);
1289 uint64_t i40e_get_default_input_set(uint16_t pctype);
1290 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1291 struct rte_eth_ethertype_filter *filter,
1293 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1294 const struct rte_eth_fdir_filter *filter,
1296 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1297 const struct i40e_fdir_filter_conf *filter,
1299 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1300 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1302 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1303 struct i40e_tunnel_filter_conf *tunnel_filter,
1305 int i40e_fdir_flush(struct rte_eth_dev *dev);
1306 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1307 struct i40e_macvlan_filter *mv_f,
1308 int num, struct rte_ether_addr *addr);
1309 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1310 struct i40e_macvlan_filter *filter,
1312 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1313 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1314 struct i40e_macvlan_filter *filter,
1316 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv);
1317 bool is_i40e_supported(struct rte_eth_dev *dev);
1318 bool is_i40evf_supported(struct rte_eth_dev *dev);
1320 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1321 enum rte_filter_type filter, uint64_t inset);
1322 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1324 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1325 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1326 void i40e_check_write_global_reg(struct i40e_hw *hw,
1327 uint32_t addr, uint32_t val);
1329 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1330 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1331 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1332 struct i40e_customized_pctype*
1333 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1334 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1336 enum rte_pmd_i40e_package_op op);
1337 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1338 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1339 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1340 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1341 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1342 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1343 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1344 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1345 const struct rte_flow_action_rss *in);
1346 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1347 const struct rte_flow_action_rss *with);
1348 int i40e_config_rss_filter(struct i40e_pf *pf,
1349 struct i40e_rte_flow_rss_conf *conf, bool add);
1350 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1351 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1353 #define I40E_DEV_TO_PCI(eth_dev) \
1354 RTE_DEV_TO_PCI((eth_dev)->device)
1356 /* I40E_DEV_PRIVATE_TO */
1357 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1358 (&((struct i40e_adapter *)adapter)->pf)
1359 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1360 (&((struct i40e_adapter *)adapter)->hw)
1361 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1362 ((struct i40e_adapter *)adapter)
1364 /* I40EVF_DEV_PRIVATE_TO */
1365 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1366 (&((struct i40e_adapter *)adapter)->vf)
1368 static inline struct i40e_vsi *
1369 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1376 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1377 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1378 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1381 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1382 return pf->main_vsi;
1385 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1386 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1389 #define I40E_VSI_TO_HW(vsi) \
1390 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1391 #define I40E_VSI_TO_PF(vsi) \
1392 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1393 #define I40E_VSI_TO_VF(vsi) \
1394 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1395 #define I40E_VSI_TO_DEV_DATA(vsi) \
1396 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1397 #define I40E_VSI_TO_ETH_DEV(vsi) \
1398 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1401 #define I40E_PF_TO_HW(pf) \
1402 (&(((struct i40e_pf *)pf)->adapter->hw))
1403 #define I40E_PF_TO_ADAPTER(pf) \
1404 ((struct i40e_adapter *)pf->adapter)
1407 #define I40E_VF_TO_HW(vf) \
1408 (&(((struct i40e_vf *)vf)->adapter->hw))
1411 i40e_init_adminq_parameter(struct i40e_hw *hw)
1413 hw->aq.num_arq_entries = I40E_AQ_LEN;
1414 hw->aq.num_asq_entries = I40E_AQ_LEN;
1415 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1416 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1420 i40e_align_floor(int n)
1424 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1427 static inline uint16_t
1428 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
1430 uint16_t interval = 0;
1433 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1436 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1438 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1441 /* Convert to hardware count, as writing each 1 represents 2 us */
1442 return interval / 2;
1445 #define I40E_VALID_FLOW(flow_type) \
1446 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1447 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1448 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1449 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1450 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1451 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1452 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1453 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1454 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1455 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1456 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1458 #define I40E_VALID_PCTYPE_X722(pctype) \
1459 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1460 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1461 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1462 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1463 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1464 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1465 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1466 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1467 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1468 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1469 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1470 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1471 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1472 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1473 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1474 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1475 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1477 #define I40E_VALID_PCTYPE(pctype) \
1478 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1479 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1480 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1481 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1482 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1483 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1484 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1485 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1486 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1487 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1488 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1490 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1491 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1492 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1493 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1494 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1495 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1496 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1498 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1499 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1500 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1501 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1502 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
1503 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
1504 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
1506 #endif /* _I40E_ETHDEV_H_ */