1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
8 #include <rte_eth_ctrl.h>
10 #include <rte_kvargs.h>
12 #include <rte_flow_driver.h>
13 #include <rte_tm_driver.h>
15 #define I40E_VLAN_TAG_SIZE 4
17 #define I40E_AQ_LEN 32
18 #define I40E_AQ_BUF_SZ 4096
19 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
20 #define I40E_MAX_Q_PER_TC 64
21 #define I40E_NUM_DESC_DEFAULT 512
22 #define I40E_NUM_DESC_ALIGN 32
23 #define I40E_BUF_SIZE_MIN 1024
24 #define I40E_FRAME_SIZE_MAX 9728
25 #define I40E_QUEUE_BASE_ADDR_UNIT 128
26 /* number of VSIs and queue default setting */
27 #define I40E_MAX_QP_NUM_PER_VF 16
28 #define I40E_DEFAULT_QP_NUM_FDIR 1
29 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
30 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
31 /* Maximun number of MAC addresses */
32 #define I40E_NUM_MACADDR_MAX 64
33 /* Maximum number of VFs */
34 #define I40E_MAX_VF 128
35 /*flag of no loopback*/
36 #define I40E_AQ_LB_MODE_NONE 0x0
38 * vlan_id is a 12 bit number.
39 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
40 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
41 * The higher 7 bit val specifies VFTA array index.
43 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
44 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
46 /* Default TC traffic in case DCB is not enabled */
47 #define I40E_DEFAULT_TCMAP 0x1
48 #define I40E_FDIR_QUEUE_ID 0
50 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
51 #define I40E_VMDQ_POOL_BASE 1
53 #define I40E_DEFAULT_RX_FREE_THRESH 32
54 #define I40E_DEFAULT_RX_PTHRESH 8
55 #define I40E_DEFAULT_RX_HTHRESH 8
56 #define I40E_DEFAULT_RX_WTHRESH 0
58 #define I40E_DEFAULT_TX_FREE_THRESH 32
59 #define I40E_DEFAULT_TX_PTHRESH 32
60 #define I40E_DEFAULT_TX_HTHRESH 0
61 #define I40E_DEFAULT_TX_WTHRESH 0
62 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
64 /* Bit shift and mask */
65 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
66 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
67 #define I40E_8_BIT_WIDTH CHAR_BIT
68 #define I40E_8_BIT_MASK UINT8_MAX
69 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
70 #define I40E_16_BIT_MASK UINT16_MAX
71 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
72 #define I40E_32_BIT_MASK UINT32_MAX
73 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
74 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
76 /* Linux PF host with virtchnl version 1.1 */
77 #define PF_IS_V11(vf) \
78 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
79 ((vf)->version_minor == 1))
81 /* index flex payload per layer */
82 enum i40e_flxpld_layer_idx {
83 I40E_FLXPLD_L2_IDX = 0,
84 I40E_FLXPLD_L3_IDX = 1,
85 I40E_FLXPLD_L4_IDX = 2,
86 I40E_MAX_FLXPLD_LAYER = 3,
88 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
89 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
90 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
91 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
92 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
95 #define I40E_FLAG_RSS (1ULL << 0)
96 #define I40E_FLAG_DCB (1ULL << 1)
97 #define I40E_FLAG_VMDQ (1ULL << 2)
98 #define I40E_FLAG_SRIOV (1ULL << 3)
99 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
100 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
101 #define I40E_FLAG_FDIR (1ULL << 6)
102 #define I40E_FLAG_VXLAN (1ULL << 7)
103 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
104 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
105 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
109 I40E_FLAG_HEADER_SPLIT_DISABLED | \
110 I40E_FLAG_HEADER_SPLIT_ENABLED | \
113 I40E_FLAG_RSS_AQ_CAPABLE | \
114 I40E_FLAG_VF_MAC_BY_PF)
116 #define I40E_RSS_OFFLOAD_ALL ( \
117 ETH_RSS_FRAG_IPV4 | \
118 ETH_RSS_NONFRAG_IPV4_TCP | \
119 ETH_RSS_NONFRAG_IPV4_UDP | \
120 ETH_RSS_NONFRAG_IPV4_SCTP | \
121 ETH_RSS_NONFRAG_IPV4_OTHER | \
122 ETH_RSS_FRAG_IPV6 | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
125 ETH_RSS_NONFRAG_IPV6_SCTP | \
126 ETH_RSS_NONFRAG_IPV6_OTHER | \
129 /* All bits of RSS hash enable for X722*/
130 #define I40E_RSS_HENA_ALL_X722 ( \
131 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
132 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
133 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
134 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
135 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
136 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
139 /* All bits of RSS hash enable */
140 #define I40E_RSS_HENA_ALL ( \
141 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
143 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
144 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
145 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
150 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
151 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
152 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
153 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
154 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
156 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
157 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
159 /* Default queue interrupt throttling time in microseconds */
160 #define I40E_ITR_INDEX_DEFAULT 0
161 #define I40E_ITR_INDEX_NONE 3
162 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
163 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
164 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */
165 /* Special FW support this floating VEB feature */
166 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
167 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
169 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
170 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
171 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
172 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
174 #define I40E_INSET_NONE 0x00000000000000000ULL
177 #define I40E_INSET_DMAC 0x0000000000000001ULL
178 #define I40E_INSET_SMAC 0x0000000000000002ULL
179 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
180 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
181 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
184 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
185 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
186 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
187 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
188 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
189 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
190 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
192 /* bit 16 ~ bit 31 */
193 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
194 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
195 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
196 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
197 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
198 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
199 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
200 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
202 /* bit 32 ~ bit 47, tunnel fields */
203 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
204 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
205 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
206 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
207 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
208 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
210 /* bit 48 ~ bit 55 */
211 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
213 /* bit 56 ~ bit 63, Flex Payload */
214 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
215 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
216 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
217 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
218 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
219 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
220 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
221 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
222 #define I40E_INSET_FLEX_PAYLOAD \
223 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
224 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
225 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
226 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
228 /* The max bandwidth of i40e is 40Gbps. */
229 #define I40E_QOS_BW_MAX 40000
230 /* The bandwidth should be the multiple of 50Mbps. */
231 #define I40E_QOS_BW_GRANULARITY 50
232 /* The min bandwidth weight is 1. */
233 #define I40E_QOS_BW_WEIGHT_MIN 1
234 /* The max bandwidth weight is 127. */
235 #define I40E_QOS_BW_WEIGHT_MAX 127
236 /* The max queue region index is 7. */
237 #define I40E_REGION_MAX_INDEX 7
239 #define I40E_MAX_PERCENT 100
240 #define I40E_DEFAULT_DCB_APP_NUM 1
241 #define I40E_DEFAULT_DCB_APP_PRIO 3
244 * The overhead from MTU to max frame size.
245 * Considering QinQ packet, the VLAN tag needs to be counted twice.
247 #define I40E_ETH_OVERHEAD \
248 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
253 * MAC filter structure
255 struct i40e_mac_filter_info {
256 enum rte_mac_filter_type filter_type;
257 struct ether_addr mac_addr;
260 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
262 /* MAC filter list structure */
263 struct i40e_mac_filter {
264 TAILQ_ENTRY(i40e_mac_filter) next;
265 struct i40e_mac_filter_info mac_info;
268 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
272 /* VSI list structure */
273 struct i40e_vsi_list {
274 TAILQ_ENTRY(i40e_vsi_list) list;
275 struct i40e_vsi *vsi;
278 struct i40e_rx_queue;
279 struct i40e_tx_queue;
281 /* Bandwidth limit information */
282 struct i40e_bw_info {
283 uint16_t bw_limit; /* BW Limit (0 = disabled) */
284 uint8_t bw_max; /* Max BW limit if enabled */
286 /* Relative credits within same TC with respect to other VSIs or Comps */
287 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
288 /* Bandwidth limit per TC */
289 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
290 /* Max bandwidth limit per TC */
291 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
294 /* Structure that defines a VEB */
296 struct i40e_vsi_list_head head;
297 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
298 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
299 uint16_t seid; /* The seid of VEB itself */
300 uint16_t uplink_seid; /* The uplink seid of this VEB */
302 struct i40e_eth_stats stats;
303 uint8_t enabled_tc; /* The traffic class enabled */
304 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
305 struct i40e_bw_info bw_info; /* VEB bandwidth information */
308 /* i40e MACVLAN filter structure */
309 struct i40e_macvlan_filter {
310 struct ether_addr macaddr;
311 enum rte_mac_filter_type filter_type;
316 * Structure that defines a VSI, associated with a adapter.
319 struct i40e_adapter *adapter; /* Backreference to associated adapter */
320 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
322 struct i40e_eth_stats eth_stats_offset;
323 struct i40e_eth_stats eth_stats;
325 * When drivers loaded, only a default main VSI exists. In case new VSI
326 * needs to add, HW needs to know the layout that VSIs are organized.
327 * Besides that, VSI isan element and can't switch packets, which needs
328 * to add new component VEB to perform switching. So, a new VSI needs
329 * to specify the uplink VSI (Parent VSI) before created. The
330 * uplink VSI will check whether it had a VEB to switch packets. If no,
331 * it will try to create one. Then, uplink VSI will move the new VSI
332 * into its' sib_vsi_list to manage all the downlink VSI.
333 * sib_vsi_list: the VSI list that shared the same uplink VSI.
334 * parent_vsi : the uplink VSI. It's NULL for main VSI.
335 * veb : the VEB associates with the VSI.
337 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
338 struct i40e_vsi *parent_vsi;
339 struct i40e_veb *veb; /* Associated veb, could be null */
340 struct i40e_veb *floating_veb; /* Associated floating veb */
342 enum i40e_vsi_type type; /* VSI types */
343 uint16_t vlan_num; /* Total VLAN number */
344 uint16_t mac_num; /* Total mac number */
345 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
346 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
347 /* specific VSI-defined parameters, SRIOV stored the vf_id */
349 uint16_t seid; /* The seid of VSI itself */
350 uint16_t uplink_seid; /* The uplink seid of this VSI */
351 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
352 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
353 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
354 uint16_t base_queue; /* The first queue index of this VSI */
356 * The offset to visit VSI related register, assigned by HW when
360 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
361 uint16_t nb_msix; /* The max number of msix vector */
362 uint8_t enabled_tc; /* The traffic class enabled */
363 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
364 uint8_t vlan_filter_on; /* The VLAN filter enabled */
365 struct i40e_bw_info bw_info; /* VSI bandwidth information */
369 LIST_ENTRY(pool_entry) next;
374 LIST_HEAD(res_list, pool_entry);
376 struct i40e_res_pool_info {
377 uint32_t base; /* Resource start index */
378 uint32_t num_alloc; /* Allocated resource number */
379 uint32_t num_free; /* Total available resource number */
380 struct res_list alloc_list; /* Allocated resource list */
381 struct res_list free_list; /* Available resource list */
385 I40E_VF_INACTIVE = 0,
392 * Structure to store private data for PF host.
396 struct i40e_vsi *vsi;
397 enum I40E_VF_STATE state; /* The number of queue pairs available */
398 uint16_t vf_idx; /* VF index in pf->vfs */
399 uint16_t lan_nb_qps; /* Actual queues allocated */
400 uint16_t reset_cnt; /* Total vf reset times */
401 struct ether_addr mac_addr; /* Default MAC address */
402 /* version of the virtchnl from VF */
403 struct virtchnl_version_info version;
404 uint32_t request_caps; /* offload caps requested from VF */
408 * Structure to store private data for flow control.
410 struct i40e_fc_conf {
411 uint16_t pause_time; /* Flow control pause timer */
412 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
413 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
414 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
415 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
419 * Structure to store private data for VMDQ instance
421 struct i40e_vmdq_info {
423 struct i40e_vsi *vsi;
426 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
427 #define I40E_MAX_FLX_SOURCE_OFF 480
428 #define NONUSE_FLX_PIT_DEST_OFF 63
429 #define NONUSE_FLX_PIT_FSIZE 1
430 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
431 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
432 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
433 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
434 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
435 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
436 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
437 NONUSE_FLX_PIT_DEST_OFF : \
438 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
439 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
440 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
441 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
442 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
443 #define I40E_FDIR_IPv6_TC_OFFSET 20
445 /* A structure used to define the input for GTP flow */
446 struct i40e_gtp_flow {
447 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
448 uint8_t msg_type; /* Message type. */
449 uint32_t teid; /* TEID in big endian. */
452 /* A structure used to define the input for GTP IPV4 flow */
453 struct i40e_gtp_ipv4_flow {
454 struct i40e_gtp_flow gtp;
455 struct rte_eth_ipv4_flow ip4;
458 /* A structure used to define the input for GTP IPV6 flow */
459 struct i40e_gtp_ipv6_flow {
460 struct i40e_gtp_flow gtp;
461 struct rte_eth_ipv6_flow ip6;
464 /* A structure used to define the input for raw type flow */
465 struct i40e_raw_flow {
472 * A union contains the inputs for all types of flow
473 * items in flows need to be in big endian
475 union i40e_fdir_flow {
476 struct rte_eth_l2_flow l2_flow;
477 struct rte_eth_udpv4_flow udp4_flow;
478 struct rte_eth_tcpv4_flow tcp4_flow;
479 struct rte_eth_sctpv4_flow sctp4_flow;
480 struct rte_eth_ipv4_flow ip4_flow;
481 struct rte_eth_udpv6_flow udp6_flow;
482 struct rte_eth_tcpv6_flow tcp6_flow;
483 struct rte_eth_sctpv6_flow sctp6_flow;
484 struct rte_eth_ipv6_flow ipv6_flow;
485 struct i40e_gtp_flow gtp_flow;
486 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
487 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
488 struct i40e_raw_flow raw_flow;
491 enum i40e_fdir_ip_type {
492 I40E_FDIR_IPTYPE_IPV4,
493 I40E_FDIR_IPTYPE_IPV6,
496 /* A structure used to contain extend input of flow */
497 struct i40e_fdir_flow_ext {
499 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
500 /* It is filled by the flexible payload to match. */
501 uint8_t is_vf; /* 1 for VF, 0 for port dev */
502 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
503 bool inner_ip; /* If there is inner ip */
504 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
505 bool customized_pctype; /* If customized pctype is used */
506 bool pkt_template; /* If raw packet template is used */
509 /* A structure used to define the input for a flow director filter entry */
510 struct i40e_fdir_input {
511 enum i40e_filter_pctype pctype;
512 union i40e_fdir_flow flow;
513 /* Flow fields to match, dependent on flow_type */
514 struct i40e_fdir_flow_ext flow_ext;
515 /* Additional fields to match */
518 /* Behavior will be taken if FDIR match */
519 enum i40e_fdir_behavior {
520 I40E_FDIR_ACCEPT = 0,
525 /* Flow director report status
526 * It defines what will be reported if FDIR entry is matched.
528 enum i40e_fdir_status {
529 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
530 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
531 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
532 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
535 /* A structure used to define an action when match FDIR packet filter. */
536 struct i40e_fdir_action {
537 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
538 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
539 enum i40e_fdir_status report_status; /* Status report option */
540 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
541 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
542 * flex bytes start from in flexible payload.
547 /* A structure used to define the flow director filter entry by filter_ctrl API
548 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
549 * RTE_ETH_FILTER_DELETE operations.
551 struct i40e_fdir_filter_conf {
553 /* ID, an unique value is required when deal with FDIR entry */
554 struct i40e_fdir_input input; /* Input set */
555 struct i40e_fdir_action action; /* Action taken when match */
559 * Structure to store flex pit for flow diretor.
561 struct i40e_fdir_flex_pit {
562 uint8_t src_offset; /* offset in words from the beginning of payload */
563 uint8_t size; /* size in words */
564 uint8_t dst_offset; /* offset in words of flexible payload */
567 struct i40e_fdir_flex_mask {
568 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
573 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
576 #define I40E_FILTER_PCTYPE_INVALID 0
577 #define I40E_FILTER_PCTYPE_MAX 64
578 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
580 struct i40e_fdir_filter {
581 TAILQ_ENTRY(i40e_fdir_filter) rules;
582 struct i40e_fdir_filter_conf fdir;
585 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
587 * A structure used to define fields of a FDIR related info.
589 struct i40e_fdir_info {
590 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
591 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
592 struct i40e_tx_queue *txq;
593 struct i40e_rx_queue *rxq;
594 void *prg_pkt; /* memory for fdir program packet */
595 uint64_t dma_addr; /* physic address of packet memory*/
596 /* input set bits for each pctype */
597 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
599 * the rule how bytes stream is extracted as flexible payload
600 * for each payload layer, the setting can up to three elements
602 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
603 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
605 struct i40e_fdir_filter_list fdir_list;
606 struct i40e_fdir_filter **hash_map;
607 struct rte_hash *hash_table;
609 /* Mark if flex pit and mask is set */
610 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
611 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
613 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
616 /* Ethertype filter number HW supports */
617 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
619 /* Ethertype filter struct */
620 struct i40e_ethertype_filter_input {
621 struct ether_addr mac_addr; /* Mac address to match */
622 uint16_t ether_type; /* Ether type to match */
625 struct i40e_ethertype_filter {
626 TAILQ_ENTRY(i40e_ethertype_filter) rules;
627 struct i40e_ethertype_filter_input input;
628 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
629 uint16_t queue; /* Queue assigned to when match */
632 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
634 struct i40e_ethertype_rule {
635 struct i40e_ethertype_filter_list ethertype_list;
636 struct i40e_ethertype_filter **hash_map;
637 struct rte_hash *hash_table;
640 /* queue region info */
641 struct i40e_queue_region_info {
642 /* the region id for this configuration */
644 /* the start queue index for this region */
645 uint8_t queue_start_index;
646 /* the total queue number of this queue region */
648 /* the total number of user priority for this region */
649 uint8_t user_priority_num;
650 /* the packet's user priority for this region */
651 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
652 /* the total number of flowtype for this region */
653 uint8_t flowtype_num;
655 * the pctype or hardware flowtype of packet,
656 * the specific index for each type has been defined
657 * in file i40e_type.h as enum i40e_filter_pctype.
659 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
662 struct i40e_queue_regions {
663 /* the total number of queue region for this port */
664 uint16_t queue_region_number;
665 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
668 /* Tunnel filter number HW supports */
669 #define I40E_MAX_TUNNEL_FILTER_NUM 400
671 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
672 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
673 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
674 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
675 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
676 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
677 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
678 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
679 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
680 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
681 #define I40E_AQC_NEW_TR_21 21
682 #define I40E_AQC_NEW_TR_22 22
684 enum i40e_tunnel_iptype {
685 I40E_TUNNEL_IPTYPE_IPV4,
686 I40E_TUNNEL_IPTYPE_IPV6,
689 /* Tunnel filter struct */
690 struct i40e_tunnel_filter_input {
691 uint8_t outer_mac[6]; /* Outer mac address to match */
692 uint8_t inner_mac[6]; /* Inner mac address to match */
693 uint16_t inner_vlan; /* Inner vlan address to match */
694 enum i40e_tunnel_iptype ip_type;
695 uint16_t flags; /* Filter type flag */
696 uint32_t tenant_id; /* Tenant id to match */
697 uint16_t general_fields[32]; /* Big buffer */
700 struct i40e_tunnel_filter {
701 TAILQ_ENTRY(i40e_tunnel_filter) rules;
702 struct i40e_tunnel_filter_input input;
703 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
704 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
705 uint16_t queue; /* Queue assigned to when match */
708 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
710 struct i40e_tunnel_rule {
711 struct i40e_tunnel_filter_list tunnel_list;
712 struct i40e_tunnel_filter **hash_map;
713 struct rte_hash *hash_table;
719 enum i40e_tunnel_type {
720 I40E_TUNNEL_TYPE_NONE = 0,
721 I40E_TUNNEL_TYPE_VXLAN,
722 I40E_TUNNEL_TYPE_GENEVE,
723 I40E_TUNNEL_TYPE_TEREDO,
724 I40E_TUNNEL_TYPE_NVGRE,
725 I40E_TUNNEL_TYPE_IP_IN_GRE,
726 I40E_L2_TUNNEL_TYPE_E_TAG,
727 I40E_TUNNEL_TYPE_MPLSoUDP,
728 I40E_TUNNEL_TYPE_MPLSoGRE,
729 I40E_TUNNEL_TYPE_QINQ,
730 I40E_TUNNEL_TYPE_GTPC,
731 I40E_TUNNEL_TYPE_GTPU,
732 I40E_TUNNEL_TYPE_MAX,
736 * Tunneling Packet filter configuration.
738 struct i40e_tunnel_filter_conf {
739 struct ether_addr outer_mac; /**< Outer MAC address to match. */
740 struct ether_addr inner_mac; /**< Inner MAC address to match. */
741 uint16_t inner_vlan; /**< Inner VLAN to match. */
742 uint32_t outer_vlan; /**< Outer VLAN to match */
743 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
745 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
746 * is set in filter_type, or inner destination IP address to match
747 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
750 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
751 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
753 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
754 uint16_t filter_type;
755 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
756 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
757 uint16_t queue_id; /**< Queue assigned to if match. */
758 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
759 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
762 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
763 #define I40E_MAX_MIRROR_RULES 64
765 * Mirror rule structure
767 struct i40e_mirror_rule {
768 TAILQ_ENTRY(i40e_mirror_rule) rules;
770 uint16_t index; /* the sw index of mirror rule */
771 uint16_t id; /* the rule id assigned by firmware */
772 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
773 uint16_t num_entries;
774 /* the info stores depend on the rule type.
775 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
776 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
778 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
781 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
784 * Struct to store flow created.
787 TAILQ_ENTRY(rte_flow) node;
788 enum rte_filter_type filter_type;
792 TAILQ_HEAD(i40e_flow_list, rte_flow);
794 /* Struct to store Traffic Manager shaper profile. */
795 struct i40e_tm_shaper_profile {
796 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
797 uint32_t shaper_profile_id;
798 uint32_t reference_count;
799 struct rte_tm_shaper_params profile;
802 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
804 /* node type of Traffic Manager */
805 enum i40e_tm_node_type {
806 I40E_TM_NODE_TYPE_PORT,
807 I40E_TM_NODE_TYPE_TC,
808 I40E_TM_NODE_TYPE_QUEUE,
809 I40E_TM_NODE_TYPE_MAX,
812 /* Struct to store Traffic Manager node configuration. */
813 struct i40e_tm_node {
814 TAILQ_ENTRY(i40e_tm_node) node;
818 uint32_t reference_count;
819 struct i40e_tm_node *parent;
820 struct i40e_tm_shaper_profile *shaper_profile;
821 struct rte_tm_node_params params;
824 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
826 /* Struct to store all the Traffic Manager configuration. */
827 struct i40e_tm_conf {
828 struct i40e_shaper_profile_list shaper_profile_list;
829 struct i40e_tm_node *root; /* root node - port */
830 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
831 struct i40e_tm_node_list queue_list; /* node list for all the queues */
833 * The number of added TC nodes.
834 * It should be no more than the TC number of this port.
838 * The number of added queue nodes.
839 * It should be no more than the queue number of this port.
841 uint32_t nb_queue_node;
843 * This flag is used to check if APP can change the TM node
845 * When it's true, means the configuration is applied to HW,
846 * APP should not change the configuration.
847 * As we don't support on-the-fly configuration, when starting
848 * the port, APP should call the hierarchy_commit API to set this
849 * flag to true. When stopping the port, this flag should be set
855 enum i40e_new_pctype {
856 I40E_CUSTOMIZED_GTPC = 0,
857 I40E_CUSTOMIZED_GTPU_IPV4,
858 I40E_CUSTOMIZED_GTPU_IPV6,
859 I40E_CUSTOMIZED_GTPU,
863 #define I40E_FILTER_PCTYPE_INVALID 0
864 struct i40e_customized_pctype {
865 enum i40e_new_pctype index; /* Indicate which customized pctype */
866 uint8_t pctype; /* New pctype value */
867 bool valid; /* Check if it's valid */
870 struct i40e_rte_flow_rss_conf {
871 struct rte_eth_rss_conf rss_conf; /**< RSS parameters. */
872 uint16_t queue_region_conf; /**< Queue region config flag */
873 uint16_t num; /**< Number of entries in queue[]. */
874 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
878 * Structure to store private data specific for PF instance.
881 struct i40e_adapter *adapter; /* The adapter this PF associate to */
882 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
883 uint16_t mac_seid; /* The seid of the MAC of this PF */
884 uint16_t main_vsi_seid; /* The seid of the main VSI */
885 uint16_t max_num_vsi;
886 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
887 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
889 struct i40e_hw_port_stats stats_offset;
890 struct i40e_hw_port_stats stats;
891 /* internal packet statistics, it should be excluded from the total */
892 struct i40e_eth_stats internal_stats_offset;
893 struct i40e_eth_stats internal_stats;
896 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
897 struct ether_addr dev_addr; /* PF device mac address */
898 uint64_t flags; /* PF feature flags */
899 /* All kinds of queue pair setting for different VSIs */
900 struct i40e_pf_vf *vfs;
902 /* Each of below queue pairs should be power of 2 since it's the
903 precondition after TC configuration applied */
904 uint16_t lan_nb_qp_max;
905 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
906 uint16_t lan_qp_offset;
907 uint16_t vmdq_nb_qp_max;
908 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
909 uint16_t vmdq_qp_offset;
910 uint16_t vf_nb_qp_max;
911 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
912 uint16_t vf_qp_offset;
913 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
914 uint16_t fdir_qp_offset;
916 uint16_t hash_lut_size; /* The size of hash lookup table */
917 /* input set bits for each pctype */
918 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
919 /* store VXLAN UDP ports */
920 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
921 uint16_t vxlan_bitmap; /* Vxlan bit mask */
923 /* VMDQ related info */
924 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
925 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
926 struct i40e_vmdq_info *vmdq;
928 struct i40e_fdir_info fdir; /* flow director info */
929 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
930 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
931 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
932 struct i40e_queue_regions queue_region; /* queue region info */
933 struct i40e_fc_conf fc_conf; /* Flow control conf */
934 struct i40e_mirror_rule_list mirror_list;
935 uint16_t nb_mirror_rule; /* The number of mirror rules */
936 bool floating_veb; /* The flag to use the floating VEB */
937 /* The floating enable flag for the specific VF */
938 bool floating_veb_list[I40E_MAX_VF];
939 struct i40e_flow_list flow_list;
940 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
941 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
942 bool qinq_replace_flag; /* QINQ filter replace is done */
943 struct i40e_tm_conf tm_conf;
945 /* Dynamic Device Personalization */
946 bool gtp_support; /* 1 - support GTP-C and GTP-U */
947 /* customer customized pctype */
948 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
952 PFMSG_LINK_CHANGE = 0x1,
953 PFMSG_RESET_IMPENDING = 0x2,
954 PFMSG_DRIVER_CLOSE = 0x4,
957 struct i40e_vsi_vlan_pvid_info {
958 uint16_t on; /* Enable or disable pvid */
960 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
962 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
963 * while 'untagged' will reject untagged packets.
971 struct i40e_vf_rx_queues {
972 uint64_t rx_dma_addr;
973 uint32_t rx_ring_len;
977 struct i40e_vf_tx_queues {
978 uint64_t tx_dma_addr;
979 uint32_t tx_ring_len;
983 * Structure to store private data specific for VF instance.
986 struct i40e_adapter *adapter; /* The adapter this VF associate to */
987 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
988 uint16_t num_queue_pairs;
989 uint16_t max_pkt_len; /* Maximum packet length */
990 bool promisc_unicast_enabled;
991 bool promisc_multicast_enabled;
993 uint32_t version_major; /* Major version number */
994 uint32_t version_minor; /* Minor version number */
995 uint16_t promisc_flags; /* Promiscuous setting */
996 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1001 enum virtchnl_link_speed link_speed;
1003 volatile uint32_t pend_cmd; /* pending command not finished yet */
1004 int32_t cmd_retval; /* return value of the cmd response from PF */
1005 u16 pend_msg; /* flags indicates events from pf not handled yet */
1006 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1009 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1010 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1011 struct i40e_vsi vsi;
1015 #define I40E_MAX_PKT_TYPE 256
1016 #define I40E_FLOW_TYPE_MAX 64
1019 * Structure to store private data for each PF/VF instance.
1021 struct i40e_adapter {
1022 /* Common for both PF and VF */
1024 struct rte_eth_dev *eth_dev;
1026 /* Specific for PF or VF */
1032 /* For vector PMD */
1033 bool rx_bulk_alloc_allowed;
1034 bool rx_vec_allowed;
1035 bool tx_simple_allowed;
1036 bool tx_vec_allowed;
1039 struct rte_timecounter systime_tc;
1040 struct rte_timecounter rx_tstamp_tc;
1041 struct rte_timecounter tx_tstamp_tc;
1043 /* ptype mapping table */
1044 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1045 /* flow type to pctype mapping table */
1046 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1047 uint64_t flow_types_mask;
1048 uint64_t pctypes_mask;
1051 extern const struct rte_flow_ops i40e_flow_ops;
1053 union i40e_filter_t {
1054 struct rte_eth_ethertype_filter ethertype_filter;
1055 struct i40e_fdir_filter_conf fdir_filter;
1056 struct rte_eth_tunnel_filter_conf tunnel_filter;
1057 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1058 struct i40e_rte_flow_rss_conf rss_conf;
1061 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1062 const struct rte_flow_attr *attr,
1063 const struct rte_flow_item pattern[],
1064 const struct rte_flow_action actions[],
1065 struct rte_flow_error *error,
1066 union i40e_filter_t *filter);
1067 struct i40e_valid_pattern {
1068 enum rte_flow_item_type *items;
1069 parse_filter_t parse_filter;
1072 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1073 int i40e_vsi_release(struct i40e_vsi *vsi);
1074 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1075 enum i40e_vsi_type type,
1076 struct i40e_vsi *uplink_vsi,
1077 uint16_t user_param);
1078 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1079 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1080 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1081 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1082 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1083 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1084 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1085 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1086 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1087 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1088 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1089 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1090 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1091 struct i40e_vsi_vlan_pvid_info *info);
1092 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1093 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1094 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1095 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1096 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1097 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1098 int i40e_fdir_setup(struct i40e_pf *pf);
1099 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1102 int i40e_fdir_configure(struct rte_eth_dev *dev);
1103 void i40e_fdir_teardown(struct i40e_pf *pf);
1104 enum i40e_filter_pctype
1105 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1106 uint16_t flow_type);
1107 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1108 enum i40e_filter_pctype pctype);
1109 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1110 enum rte_filter_op filter_op,
1112 int i40e_select_filter_input_set(struct i40e_hw *hw,
1113 struct rte_eth_input_set_conf *conf,
1114 enum rte_filter_type filter);
1115 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1116 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1117 struct rte_eth_input_set_conf *conf);
1118 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1119 struct rte_eth_input_set_conf *conf);
1120 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1121 uint32_t retval, uint8_t *msg,
1123 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1124 struct rte_eth_rxq_info *qinfo);
1125 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1126 struct rte_eth_txq_info *qinfo);
1127 struct i40e_ethertype_filter *
1128 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1129 const struct i40e_ethertype_filter_input *input);
1130 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1131 struct i40e_ethertype_filter_input *input);
1132 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1133 struct i40e_fdir_input *input);
1134 struct i40e_tunnel_filter *
1135 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1136 const struct i40e_tunnel_filter_input *input);
1137 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1138 struct i40e_tunnel_filter_input *input);
1139 uint64_t i40e_get_default_input_set(uint16_t pctype);
1140 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1141 struct rte_eth_ethertype_filter *filter,
1143 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1144 const struct rte_eth_fdir_filter *filter,
1146 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1147 const struct i40e_fdir_filter_conf *filter,
1149 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1150 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1152 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1153 struct i40e_tunnel_filter_conf *tunnel_filter,
1155 int i40e_fdir_flush(struct rte_eth_dev *dev);
1156 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1157 struct i40e_macvlan_filter *mv_f,
1158 int num, struct ether_addr *addr);
1159 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1160 struct i40e_macvlan_filter *filter,
1162 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1163 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1164 struct i40e_macvlan_filter *filter,
1166 bool is_i40e_supported(struct rte_eth_dev *dev);
1168 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1169 enum rte_filter_type filter, uint64_t inset);
1170 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1172 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1173 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1175 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1176 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1177 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1178 struct i40e_customized_pctype*
1179 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1180 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1182 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1183 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1184 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1185 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1186 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1187 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1188 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1189 int i40e_config_rss_filter(struct i40e_pf *pf,
1190 struct i40e_rte_flow_rss_conf *conf, bool add);
1192 #define I40E_DEV_TO_PCI(eth_dev) \
1193 RTE_DEV_TO_PCI((eth_dev)->device)
1195 /* I40E_DEV_PRIVATE_TO */
1196 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1197 (&((struct i40e_adapter *)adapter)->pf)
1198 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1199 (&((struct i40e_adapter *)adapter)->hw)
1200 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1201 ((struct i40e_adapter *)adapter)
1203 /* I40EVF_DEV_PRIVATE_TO */
1204 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1205 (&((struct i40e_adapter *)adapter)->vf)
1207 static inline struct i40e_vsi *
1208 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1215 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1216 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1217 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1220 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1221 return pf->main_vsi;
1224 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1225 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1228 #define I40E_VSI_TO_HW(vsi) \
1229 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1230 #define I40E_VSI_TO_PF(vsi) \
1231 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1232 #define I40E_VSI_TO_VF(vsi) \
1233 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1234 #define I40E_VSI_TO_DEV_DATA(vsi) \
1235 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1236 #define I40E_VSI_TO_ETH_DEV(vsi) \
1237 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1240 #define I40E_PF_TO_HW(pf) \
1241 (&(((struct i40e_pf *)pf)->adapter->hw))
1242 #define I40E_PF_TO_ADAPTER(pf) \
1243 ((struct i40e_adapter *)pf->adapter)
1246 #define I40E_VF_TO_HW(vf) \
1247 (&(((struct i40e_vf *)vf)->adapter->hw))
1250 i40e_init_adminq_parameter(struct i40e_hw *hw)
1252 hw->aq.num_arq_entries = I40E_AQ_LEN;
1253 hw->aq.num_asq_entries = I40E_AQ_LEN;
1254 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1255 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1259 i40e_align_floor(int n)
1263 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1266 static inline uint16_t
1267 i40e_calc_itr_interval(int16_t interval, bool is_pf)
1269 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
1271 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1273 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1276 /* Convert to hardware count, as writing each 1 represents 2 us */
1277 return interval / 2;
1280 #define I40E_VALID_FLOW(flow_type) \
1281 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1282 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1283 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1284 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1285 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1286 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1287 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1288 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1289 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1290 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1291 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1293 #define I40E_VALID_PCTYPE_X722(pctype) \
1294 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1295 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1296 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1297 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1298 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1299 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1300 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1301 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1302 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1303 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1304 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1305 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1306 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1307 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1308 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1309 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1310 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1312 #define I40E_VALID_PCTYPE(pctype) \
1313 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1314 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1315 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1316 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1317 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1318 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1319 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1320 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1321 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1322 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1323 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1325 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1326 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1327 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1328 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1329 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1330 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1331 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1333 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1334 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1335 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1336 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1337 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1339 #endif /* _I40E_ETHDEV_H_ */