1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
8 #include <rte_eth_ctrl.h>
10 #include <rte_kvargs.h>
12 #include <rte_flow_driver.h>
13 #include <rte_tm_driver.h>
15 #define I40E_VLAN_TAG_SIZE 4
17 #define I40E_AQ_LEN 32
18 #define I40E_AQ_BUF_SZ 4096
19 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
20 #define I40E_MAX_Q_PER_TC 64
21 #define I40E_NUM_DESC_DEFAULT 512
22 #define I40E_NUM_DESC_ALIGN 32
23 #define I40E_BUF_SIZE_MIN 1024
24 #define I40E_FRAME_SIZE_MAX 9728
25 #define I40E_QUEUE_BASE_ADDR_UNIT 128
26 /* number of VSIs and queue default setting */
27 #define I40E_MAX_QP_NUM_PER_VF 16
28 #define I40E_DEFAULT_QP_NUM_FDIR 1
29 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
30 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
31 /* Maximun number of MAC addresses */
32 #define I40E_NUM_MACADDR_MAX 64
33 /* Maximum number of VFs */
34 #define I40E_MAX_VF 128
35 /*flag of no loopback*/
36 #define I40E_AQ_LB_MODE_NONE 0x0
38 * vlan_id is a 12 bit number.
39 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
40 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
41 * The higher 7 bit val specifies VFTA array index.
43 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
44 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
46 /* Default TC traffic in case DCB is not enabled */
47 #define I40E_DEFAULT_TCMAP 0x1
48 #define I40E_FDIR_QUEUE_ID 0
50 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
51 #define I40E_VMDQ_POOL_BASE 1
53 #define I40E_DEFAULT_RX_FREE_THRESH 32
54 #define I40E_DEFAULT_RX_PTHRESH 8
55 #define I40E_DEFAULT_RX_HTHRESH 8
56 #define I40E_DEFAULT_RX_WTHRESH 0
58 #define I40E_DEFAULT_TX_FREE_THRESH 32
59 #define I40E_DEFAULT_TX_PTHRESH 32
60 #define I40E_DEFAULT_TX_HTHRESH 0
61 #define I40E_DEFAULT_TX_WTHRESH 0
62 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
64 /* Bit shift and mask */
65 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
66 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
67 #define I40E_8_BIT_WIDTH CHAR_BIT
68 #define I40E_8_BIT_MASK UINT8_MAX
69 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
70 #define I40E_16_BIT_MASK UINT16_MAX
71 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
72 #define I40E_32_BIT_MASK UINT32_MAX
73 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
74 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
76 /* Linux PF host with virtchnl version 1.1 */
77 #define PF_IS_V11(vf) \
78 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
79 ((vf)->version_minor == 1))
81 #define I40E_WRITE_GLB_REG(hw, reg, value) \
83 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
85 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
86 "with value 0x%08x", \
90 /* index flex payload per layer */
91 enum i40e_flxpld_layer_idx {
92 I40E_FLXPLD_L2_IDX = 0,
93 I40E_FLXPLD_L3_IDX = 1,
94 I40E_FLXPLD_L4_IDX = 2,
95 I40E_MAX_FLXPLD_LAYER = 3,
97 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
98 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
99 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
100 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
101 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
104 #define I40E_FLAG_RSS (1ULL << 0)
105 #define I40E_FLAG_DCB (1ULL << 1)
106 #define I40E_FLAG_VMDQ (1ULL << 2)
107 #define I40E_FLAG_SRIOV (1ULL << 3)
108 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
109 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
110 #define I40E_FLAG_FDIR (1ULL << 6)
111 #define I40E_FLAG_VXLAN (1ULL << 7)
112 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
113 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
114 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
118 I40E_FLAG_HEADER_SPLIT_DISABLED | \
119 I40E_FLAG_HEADER_SPLIT_ENABLED | \
122 I40E_FLAG_RSS_AQ_CAPABLE | \
123 I40E_FLAG_VF_MAC_BY_PF)
125 #define I40E_RSS_OFFLOAD_ALL ( \
126 ETH_RSS_FRAG_IPV4 | \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
129 ETH_RSS_NONFRAG_IPV4_SCTP | \
130 ETH_RSS_NONFRAG_IPV4_OTHER | \
131 ETH_RSS_FRAG_IPV6 | \
132 ETH_RSS_NONFRAG_IPV6_TCP | \
133 ETH_RSS_NONFRAG_IPV6_UDP | \
134 ETH_RSS_NONFRAG_IPV6_SCTP | \
135 ETH_RSS_NONFRAG_IPV6_OTHER | \
138 /* All bits of RSS hash enable for X722*/
139 #define I40E_RSS_HENA_ALL_X722 ( \
140 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
141 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
143 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
144 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
148 /* All bits of RSS hash enable */
149 #define I40E_RSS_HENA_ALL ( \
150 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
154 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
159 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
160 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
161 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
162 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
163 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
165 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
166 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
168 /* Default queue interrupt throttling time in microseconds */
169 #define I40E_ITR_INDEX_DEFAULT 0
170 #define I40E_ITR_INDEX_NONE 3
171 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
172 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
173 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */
174 /* Special FW support this floating VEB feature */
175 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
176 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
178 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
179 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
180 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
181 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
183 #define I40E_INSET_NONE 0x00000000000000000ULL
186 #define I40E_INSET_DMAC 0x0000000000000001ULL
187 #define I40E_INSET_SMAC 0x0000000000000002ULL
188 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
189 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
190 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
193 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
194 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
195 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
196 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
197 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
198 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
199 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
201 /* bit 16 ~ bit 31 */
202 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
203 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
204 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
205 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
206 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
207 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
208 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
209 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
211 /* bit 32 ~ bit 47, tunnel fields */
212 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
213 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
214 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
215 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
216 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
217 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
219 /* bit 48 ~ bit 55 */
220 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
222 /* bit 56 ~ bit 63, Flex Payload */
223 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
224 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
225 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
226 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
227 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
228 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
229 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
230 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
231 #define I40E_INSET_FLEX_PAYLOAD \
232 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
233 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
234 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
235 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
237 /* The max bandwidth of i40e is 40Gbps. */
238 #define I40E_QOS_BW_MAX 40000
239 /* The bandwidth should be the multiple of 50Mbps. */
240 #define I40E_QOS_BW_GRANULARITY 50
241 /* The min bandwidth weight is 1. */
242 #define I40E_QOS_BW_WEIGHT_MIN 1
243 /* The max bandwidth weight is 127. */
244 #define I40E_QOS_BW_WEIGHT_MAX 127
245 /* The max queue region index is 7. */
246 #define I40E_REGION_MAX_INDEX 7
248 #define I40E_MAX_PERCENT 100
249 #define I40E_DEFAULT_DCB_APP_NUM 1
250 #define I40E_DEFAULT_DCB_APP_PRIO 3
253 * The overhead from MTU to max frame size.
254 * Considering QinQ packet, the VLAN tag needs to be counted twice.
256 #define I40E_ETH_OVERHEAD \
257 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
262 * MAC filter structure
264 struct i40e_mac_filter_info {
265 enum rte_mac_filter_type filter_type;
266 struct ether_addr mac_addr;
269 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
271 /* MAC filter list structure */
272 struct i40e_mac_filter {
273 TAILQ_ENTRY(i40e_mac_filter) next;
274 struct i40e_mac_filter_info mac_info;
277 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
281 /* VSI list structure */
282 struct i40e_vsi_list {
283 TAILQ_ENTRY(i40e_vsi_list) list;
284 struct i40e_vsi *vsi;
287 struct i40e_rx_queue;
288 struct i40e_tx_queue;
290 /* Bandwidth limit information */
291 struct i40e_bw_info {
292 uint16_t bw_limit; /* BW Limit (0 = disabled) */
293 uint8_t bw_max; /* Max BW limit if enabled */
295 /* Relative credits within same TC with respect to other VSIs or Comps */
296 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
297 /* Bandwidth limit per TC */
298 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
299 /* Max bandwidth limit per TC */
300 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
303 /* Structure that defines a VEB */
305 struct i40e_vsi_list_head head;
306 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
307 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
308 uint16_t seid; /* The seid of VEB itself */
309 uint16_t uplink_seid; /* The uplink seid of this VEB */
311 struct i40e_eth_stats stats;
312 uint8_t enabled_tc; /* The traffic class enabled */
313 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
314 struct i40e_bw_info bw_info; /* VEB bandwidth information */
317 /* i40e MACVLAN filter structure */
318 struct i40e_macvlan_filter {
319 struct ether_addr macaddr;
320 enum rte_mac_filter_type filter_type;
325 * Structure that defines a VSI, associated with a adapter.
328 struct i40e_adapter *adapter; /* Backreference to associated adapter */
329 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
331 struct i40e_eth_stats eth_stats_offset;
332 struct i40e_eth_stats eth_stats;
334 * When drivers loaded, only a default main VSI exists. In case new VSI
335 * needs to add, HW needs to know the layout that VSIs are organized.
336 * Besides that, VSI isan element and can't switch packets, which needs
337 * to add new component VEB to perform switching. So, a new VSI needs
338 * to specify the uplink VSI (Parent VSI) before created. The
339 * uplink VSI will check whether it had a VEB to switch packets. If no,
340 * it will try to create one. Then, uplink VSI will move the new VSI
341 * into its' sib_vsi_list to manage all the downlink VSI.
342 * sib_vsi_list: the VSI list that shared the same uplink VSI.
343 * parent_vsi : the uplink VSI. It's NULL for main VSI.
344 * veb : the VEB associates with the VSI.
346 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
347 struct i40e_vsi *parent_vsi;
348 struct i40e_veb *veb; /* Associated veb, could be null */
349 struct i40e_veb *floating_veb; /* Associated floating veb */
351 enum i40e_vsi_type type; /* VSI types */
352 uint16_t vlan_num; /* Total VLAN number */
353 uint16_t mac_num; /* Total mac number */
354 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
355 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
356 /* specific VSI-defined parameters, SRIOV stored the vf_id */
358 uint16_t seid; /* The seid of VSI itself */
359 uint16_t uplink_seid; /* The uplink seid of this VSI */
360 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
361 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
362 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
363 uint16_t base_queue; /* The first queue index of this VSI */
365 * The offset to visit VSI related register, assigned by HW when
369 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
370 uint16_t nb_msix; /* The max number of msix vector */
371 uint8_t enabled_tc; /* The traffic class enabled */
372 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
373 uint8_t vlan_filter_on; /* The VLAN filter enabled */
374 struct i40e_bw_info bw_info; /* VSI bandwidth information */
378 LIST_ENTRY(pool_entry) next;
383 LIST_HEAD(res_list, pool_entry);
385 struct i40e_res_pool_info {
386 uint32_t base; /* Resource start index */
387 uint32_t num_alloc; /* Allocated resource number */
388 uint32_t num_free; /* Total available resource number */
389 struct res_list alloc_list; /* Allocated resource list */
390 struct res_list free_list; /* Available resource list */
394 I40E_VF_INACTIVE = 0,
401 * Structure to store private data for PF host.
405 struct i40e_vsi *vsi;
406 enum I40E_VF_STATE state; /* The number of queue pairs available */
407 uint16_t vf_idx; /* VF index in pf->vfs */
408 uint16_t lan_nb_qps; /* Actual queues allocated */
409 uint16_t reset_cnt; /* Total vf reset times */
410 struct ether_addr mac_addr; /* Default MAC address */
411 /* version of the virtchnl from VF */
412 struct virtchnl_version_info version;
413 uint32_t request_caps; /* offload caps requested from VF */
417 * Structure to store private data for flow control.
419 struct i40e_fc_conf {
420 uint16_t pause_time; /* Flow control pause timer */
421 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
422 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
423 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
424 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
428 * Structure to store private data for VMDQ instance
430 struct i40e_vmdq_info {
432 struct i40e_vsi *vsi;
435 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
436 #define I40E_MAX_FLX_SOURCE_OFF 480
437 #define NONUSE_FLX_PIT_DEST_OFF 63
438 #define NONUSE_FLX_PIT_FSIZE 1
439 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
440 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
441 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
442 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
443 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
444 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
445 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
446 NONUSE_FLX_PIT_DEST_OFF : \
447 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
448 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
449 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
450 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
451 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
452 #define I40E_FDIR_IPv6_TC_OFFSET 20
454 /* A structure used to define the input for GTP flow */
455 struct i40e_gtp_flow {
456 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
457 uint8_t msg_type; /* Message type. */
458 uint32_t teid; /* TEID in big endian. */
461 /* A structure used to define the input for GTP IPV4 flow */
462 struct i40e_gtp_ipv4_flow {
463 struct i40e_gtp_flow gtp;
464 struct rte_eth_ipv4_flow ip4;
467 /* A structure used to define the input for GTP IPV6 flow */
468 struct i40e_gtp_ipv6_flow {
469 struct i40e_gtp_flow gtp;
470 struct rte_eth_ipv6_flow ip6;
473 /* A structure used to define the input for raw type flow */
474 struct i40e_raw_flow {
481 * A union contains the inputs for all types of flow
482 * items in flows need to be in big endian
484 union i40e_fdir_flow {
485 struct rte_eth_l2_flow l2_flow;
486 struct rte_eth_udpv4_flow udp4_flow;
487 struct rte_eth_tcpv4_flow tcp4_flow;
488 struct rte_eth_sctpv4_flow sctp4_flow;
489 struct rte_eth_ipv4_flow ip4_flow;
490 struct rte_eth_udpv6_flow udp6_flow;
491 struct rte_eth_tcpv6_flow tcp6_flow;
492 struct rte_eth_sctpv6_flow sctp6_flow;
493 struct rte_eth_ipv6_flow ipv6_flow;
494 struct i40e_gtp_flow gtp_flow;
495 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
496 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
497 struct i40e_raw_flow raw_flow;
500 enum i40e_fdir_ip_type {
501 I40E_FDIR_IPTYPE_IPV4,
502 I40E_FDIR_IPTYPE_IPV6,
505 /* A structure used to contain extend input of flow */
506 struct i40e_fdir_flow_ext {
508 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
509 /* It is filled by the flexible payload to match. */
510 uint8_t is_vf; /* 1 for VF, 0 for port dev */
511 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
512 bool inner_ip; /* If there is inner ip */
513 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
514 bool customized_pctype; /* If customized pctype is used */
515 bool pkt_template; /* If raw packet template is used */
518 /* A structure used to define the input for a flow director filter entry */
519 struct i40e_fdir_input {
520 enum i40e_filter_pctype pctype;
521 union i40e_fdir_flow flow;
522 /* Flow fields to match, dependent on flow_type */
523 struct i40e_fdir_flow_ext flow_ext;
524 /* Additional fields to match */
527 /* Behavior will be taken if FDIR match */
528 enum i40e_fdir_behavior {
529 I40E_FDIR_ACCEPT = 0,
534 /* Flow director report status
535 * It defines what will be reported if FDIR entry is matched.
537 enum i40e_fdir_status {
538 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
539 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
540 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
541 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
544 /* A structure used to define an action when match FDIR packet filter. */
545 struct i40e_fdir_action {
546 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
547 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
548 enum i40e_fdir_status report_status; /* Status report option */
549 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
550 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
551 * flex bytes start from in flexible payload.
556 /* A structure used to define the flow director filter entry by filter_ctrl API
557 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
558 * RTE_ETH_FILTER_DELETE operations.
560 struct i40e_fdir_filter_conf {
562 /* ID, an unique value is required when deal with FDIR entry */
563 struct i40e_fdir_input input; /* Input set */
564 struct i40e_fdir_action action; /* Action taken when match */
568 * Structure to store flex pit for flow diretor.
570 struct i40e_fdir_flex_pit {
571 uint8_t src_offset; /* offset in words from the beginning of payload */
572 uint8_t size; /* size in words */
573 uint8_t dst_offset; /* offset in words of flexible payload */
576 struct i40e_fdir_flex_mask {
577 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
582 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
585 #define I40E_FILTER_PCTYPE_INVALID 0
586 #define I40E_FILTER_PCTYPE_MAX 64
587 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
589 struct i40e_fdir_filter {
590 TAILQ_ENTRY(i40e_fdir_filter) rules;
591 struct i40e_fdir_filter_conf fdir;
594 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
596 * A structure used to define fields of a FDIR related info.
598 struct i40e_fdir_info {
599 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
600 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
601 struct i40e_tx_queue *txq;
602 struct i40e_rx_queue *rxq;
603 void *prg_pkt; /* memory for fdir program packet */
604 uint64_t dma_addr; /* physic address of packet memory*/
605 /* input set bits for each pctype */
606 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
608 * the rule how bytes stream is extracted as flexible payload
609 * for each payload layer, the setting can up to three elements
611 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
612 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
614 struct i40e_fdir_filter_list fdir_list;
615 struct i40e_fdir_filter **hash_map;
616 struct rte_hash *hash_table;
618 /* Mark if flex pit and mask is set */
619 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
620 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
622 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
625 /* Ethertype filter number HW supports */
626 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
628 /* Ethertype filter struct */
629 struct i40e_ethertype_filter_input {
630 struct ether_addr mac_addr; /* Mac address to match */
631 uint16_t ether_type; /* Ether type to match */
634 struct i40e_ethertype_filter {
635 TAILQ_ENTRY(i40e_ethertype_filter) rules;
636 struct i40e_ethertype_filter_input input;
637 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
638 uint16_t queue; /* Queue assigned to when match */
641 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
643 struct i40e_ethertype_rule {
644 struct i40e_ethertype_filter_list ethertype_list;
645 struct i40e_ethertype_filter **hash_map;
646 struct rte_hash *hash_table;
649 /* queue region info */
650 struct i40e_queue_region_info {
651 /* the region id for this configuration */
653 /* the start queue index for this region */
654 uint8_t queue_start_index;
655 /* the total queue number of this queue region */
657 /* the total number of user priority for this region */
658 uint8_t user_priority_num;
659 /* the packet's user priority for this region */
660 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
661 /* the total number of flowtype for this region */
662 uint8_t flowtype_num;
664 * the pctype or hardware flowtype of packet,
665 * the specific index for each type has been defined
666 * in file i40e_type.h as enum i40e_filter_pctype.
668 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
671 struct i40e_queue_regions {
672 /* the total number of queue region for this port */
673 uint16_t queue_region_number;
674 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
677 /* Tunnel filter number HW supports */
678 #define I40E_MAX_TUNNEL_FILTER_NUM 400
680 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
681 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
682 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
683 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
684 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
685 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
686 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
687 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
688 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
689 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
690 #define I40E_AQC_NEW_TR_21 21
691 #define I40E_AQC_NEW_TR_22 22
693 enum i40e_tunnel_iptype {
694 I40E_TUNNEL_IPTYPE_IPV4,
695 I40E_TUNNEL_IPTYPE_IPV6,
698 /* Tunnel filter struct */
699 struct i40e_tunnel_filter_input {
700 uint8_t outer_mac[6]; /* Outer mac address to match */
701 uint8_t inner_mac[6]; /* Inner mac address to match */
702 uint16_t inner_vlan; /* Inner vlan address to match */
703 enum i40e_tunnel_iptype ip_type;
704 uint16_t flags; /* Filter type flag */
705 uint32_t tenant_id; /* Tenant id to match */
706 uint16_t general_fields[32]; /* Big buffer */
709 struct i40e_tunnel_filter {
710 TAILQ_ENTRY(i40e_tunnel_filter) rules;
711 struct i40e_tunnel_filter_input input;
712 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
713 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
714 uint16_t queue; /* Queue assigned to when match */
717 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
719 struct i40e_tunnel_rule {
720 struct i40e_tunnel_filter_list tunnel_list;
721 struct i40e_tunnel_filter **hash_map;
722 struct rte_hash *hash_table;
728 enum i40e_tunnel_type {
729 I40E_TUNNEL_TYPE_NONE = 0,
730 I40E_TUNNEL_TYPE_VXLAN,
731 I40E_TUNNEL_TYPE_GENEVE,
732 I40E_TUNNEL_TYPE_TEREDO,
733 I40E_TUNNEL_TYPE_NVGRE,
734 I40E_TUNNEL_TYPE_IP_IN_GRE,
735 I40E_L2_TUNNEL_TYPE_E_TAG,
736 I40E_TUNNEL_TYPE_MPLSoUDP,
737 I40E_TUNNEL_TYPE_MPLSoGRE,
738 I40E_TUNNEL_TYPE_QINQ,
739 I40E_TUNNEL_TYPE_GTPC,
740 I40E_TUNNEL_TYPE_GTPU,
741 I40E_TUNNEL_TYPE_MAX,
745 * Tunneling Packet filter configuration.
747 struct i40e_tunnel_filter_conf {
748 struct ether_addr outer_mac; /**< Outer MAC address to match. */
749 struct ether_addr inner_mac; /**< Inner MAC address to match. */
750 uint16_t inner_vlan; /**< Inner VLAN to match. */
751 uint32_t outer_vlan; /**< Outer VLAN to match */
752 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
754 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
755 * is set in filter_type, or inner destination IP address to match
756 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
759 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
760 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
762 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
763 uint16_t filter_type;
764 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
765 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
766 uint16_t queue_id; /**< Queue assigned to if match. */
767 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
768 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
771 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
772 #define I40E_MAX_MIRROR_RULES 64
774 * Mirror rule structure
776 struct i40e_mirror_rule {
777 TAILQ_ENTRY(i40e_mirror_rule) rules;
779 uint16_t index; /* the sw index of mirror rule */
780 uint16_t id; /* the rule id assigned by firmware */
781 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
782 uint16_t num_entries;
783 /* the info stores depend on the rule type.
784 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
785 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
787 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
790 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
793 * Struct to store flow created.
796 TAILQ_ENTRY(rte_flow) node;
797 enum rte_filter_type filter_type;
801 TAILQ_HEAD(i40e_flow_list, rte_flow);
803 /* Struct to store Traffic Manager shaper profile. */
804 struct i40e_tm_shaper_profile {
805 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
806 uint32_t shaper_profile_id;
807 uint32_t reference_count;
808 struct rte_tm_shaper_params profile;
811 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
813 /* node type of Traffic Manager */
814 enum i40e_tm_node_type {
815 I40E_TM_NODE_TYPE_PORT,
816 I40E_TM_NODE_TYPE_TC,
817 I40E_TM_NODE_TYPE_QUEUE,
818 I40E_TM_NODE_TYPE_MAX,
821 /* Struct to store Traffic Manager node configuration. */
822 struct i40e_tm_node {
823 TAILQ_ENTRY(i40e_tm_node) node;
827 uint32_t reference_count;
828 struct i40e_tm_node *parent;
829 struct i40e_tm_shaper_profile *shaper_profile;
830 struct rte_tm_node_params params;
833 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
835 /* Struct to store all the Traffic Manager configuration. */
836 struct i40e_tm_conf {
837 struct i40e_shaper_profile_list shaper_profile_list;
838 struct i40e_tm_node *root; /* root node - port */
839 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
840 struct i40e_tm_node_list queue_list; /* node list for all the queues */
842 * The number of added TC nodes.
843 * It should be no more than the TC number of this port.
847 * The number of added queue nodes.
848 * It should be no more than the queue number of this port.
850 uint32_t nb_queue_node;
852 * This flag is used to check if APP can change the TM node
854 * When it's true, means the configuration is applied to HW,
855 * APP should not change the configuration.
856 * As we don't support on-the-fly configuration, when starting
857 * the port, APP should call the hierarchy_commit API to set this
858 * flag to true. When stopping the port, this flag should be set
864 enum i40e_new_pctype {
865 I40E_CUSTOMIZED_GTPC = 0,
866 I40E_CUSTOMIZED_GTPU_IPV4,
867 I40E_CUSTOMIZED_GTPU_IPV6,
868 I40E_CUSTOMIZED_GTPU,
872 #define I40E_FILTER_PCTYPE_INVALID 0
873 struct i40e_customized_pctype {
874 enum i40e_new_pctype index; /* Indicate which customized pctype */
875 uint8_t pctype; /* New pctype value */
876 bool valid; /* Check if it's valid */
879 struct i40e_rte_flow_rss_conf {
880 struct rte_eth_rss_conf rss_conf; /**< RSS parameters. */
881 uint16_t queue_region_conf; /**< Queue region config flag */
882 uint16_t num; /**< Number of entries in queue[]. */
883 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
887 * Structure to store private data specific for PF instance.
890 struct i40e_adapter *adapter; /* The adapter this PF associate to */
891 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
892 uint16_t mac_seid; /* The seid of the MAC of this PF */
893 uint16_t main_vsi_seid; /* The seid of the main VSI */
894 uint16_t max_num_vsi;
895 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
896 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
898 struct i40e_hw_port_stats stats_offset;
899 struct i40e_hw_port_stats stats;
900 /* internal packet statistics, it should be excluded from the total */
901 struct i40e_eth_stats internal_stats_offset;
902 struct i40e_eth_stats internal_stats;
905 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
906 struct ether_addr dev_addr; /* PF device mac address */
907 uint64_t flags; /* PF feature flags */
908 /* All kinds of queue pair setting for different VSIs */
909 struct i40e_pf_vf *vfs;
911 /* Each of below queue pairs should be power of 2 since it's the
912 precondition after TC configuration applied */
913 uint16_t lan_nb_qp_max;
914 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
915 uint16_t lan_qp_offset;
916 uint16_t vmdq_nb_qp_max;
917 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
918 uint16_t vmdq_qp_offset;
919 uint16_t vf_nb_qp_max;
920 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
921 uint16_t vf_qp_offset;
922 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
923 uint16_t fdir_qp_offset;
925 uint16_t hash_lut_size; /* The size of hash lookup table */
926 /* input set bits for each pctype */
927 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
928 /* store VXLAN UDP ports */
929 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
930 uint16_t vxlan_bitmap; /* Vxlan bit mask */
932 /* VMDQ related info */
933 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
934 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
935 struct i40e_vmdq_info *vmdq;
937 struct i40e_fdir_info fdir; /* flow director info */
938 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
939 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
940 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
941 struct i40e_queue_regions queue_region; /* queue region info */
942 struct i40e_fc_conf fc_conf; /* Flow control conf */
943 struct i40e_mirror_rule_list mirror_list;
944 uint16_t nb_mirror_rule; /* The number of mirror rules */
945 bool floating_veb; /* The flag to use the floating VEB */
946 /* The floating enable flag for the specific VF */
947 bool floating_veb_list[I40E_MAX_VF];
948 struct i40e_flow_list flow_list;
949 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
950 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
951 bool qinq_replace_flag; /* QINQ filter replace is done */
952 struct i40e_tm_conf tm_conf;
953 bool support_multi_driver; /* 1 - support multiple driver */
955 /* Dynamic Device Personalization */
956 bool gtp_support; /* 1 - support GTP-C and GTP-U */
957 /* customer customized pctype */
958 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
962 PFMSG_LINK_CHANGE = 0x1,
963 PFMSG_RESET_IMPENDING = 0x2,
964 PFMSG_DRIVER_CLOSE = 0x4,
967 struct i40e_vsi_vlan_pvid_info {
968 uint16_t on; /* Enable or disable pvid */
970 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
972 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
973 * while 'untagged' will reject untagged packets.
981 struct i40e_vf_rx_queues {
982 uint64_t rx_dma_addr;
983 uint32_t rx_ring_len;
987 struct i40e_vf_tx_queues {
988 uint64_t tx_dma_addr;
989 uint32_t tx_ring_len;
993 * Structure to store private data specific for VF instance.
996 struct i40e_adapter *adapter; /* The adapter this VF associate to */
997 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
998 uint16_t num_queue_pairs;
999 uint16_t max_pkt_len; /* Maximum packet length */
1000 bool promisc_unicast_enabled;
1001 bool promisc_multicast_enabled;
1003 uint32_t version_major; /* Major version number */
1004 uint32_t version_minor; /* Minor version number */
1005 uint16_t promisc_flags; /* Promiscuous setting */
1006 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1011 enum virtchnl_link_speed link_speed;
1013 volatile uint32_t pend_cmd; /* pending command not finished yet */
1014 int32_t cmd_retval; /* return value of the cmd response from PF */
1015 u16 pend_msg; /* flags indicates events from pf not handled yet */
1016 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1019 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1020 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1021 struct i40e_vsi vsi;
1025 #define I40E_MAX_PKT_TYPE 256
1026 #define I40E_FLOW_TYPE_MAX 64
1029 * Structure to store private data for each PF/VF instance.
1031 struct i40e_adapter {
1032 /* Common for both PF and VF */
1034 struct rte_eth_dev *eth_dev;
1036 /* Specific for PF or VF */
1042 /* For vector PMD */
1043 bool rx_bulk_alloc_allowed;
1044 bool rx_vec_allowed;
1045 bool tx_simple_allowed;
1046 bool tx_vec_allowed;
1049 struct rte_timecounter systime_tc;
1050 struct rte_timecounter rx_tstamp_tc;
1051 struct rte_timecounter tx_tstamp_tc;
1053 /* ptype mapping table */
1054 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1055 /* flow type to pctype mapping table */
1056 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1057 uint64_t flow_types_mask;
1058 uint64_t pctypes_mask;
1061 extern const struct rte_flow_ops i40e_flow_ops;
1063 union i40e_filter_t {
1064 struct rte_eth_ethertype_filter ethertype_filter;
1065 struct i40e_fdir_filter_conf fdir_filter;
1066 struct rte_eth_tunnel_filter_conf tunnel_filter;
1067 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1068 struct i40e_rte_flow_rss_conf rss_conf;
1071 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1072 const struct rte_flow_attr *attr,
1073 const struct rte_flow_item pattern[],
1074 const struct rte_flow_action actions[],
1075 struct rte_flow_error *error,
1076 union i40e_filter_t *filter);
1077 struct i40e_valid_pattern {
1078 enum rte_flow_item_type *items;
1079 parse_filter_t parse_filter;
1082 enum I40E_WARNING_IDX {
1083 I40E_WARNING_DIS_FLX_PLD,
1084 I40E_WARNING_ENA_FLX_PLD,
1085 I40E_WARNING_QINQ_PARSER,
1086 I40E_WARNING_QINQ_CLOUD_FILTER,
1088 I40E_WARNING_FLOW_CTL,
1089 I40E_WARNING_GRE_KEY_LEN,
1090 I40E_WARNING_QF_CTL,
1091 I40E_WARNING_HASH_INSET,
1093 I40E_WARNING_HASH_MSK,
1094 I40E_WARNING_FD_MSK,
1095 I40E_WARNING_RPL_CLD_FILTER,
1098 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1099 int i40e_vsi_release(struct i40e_vsi *vsi);
1100 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1101 enum i40e_vsi_type type,
1102 struct i40e_vsi *uplink_vsi,
1103 uint16_t user_param);
1104 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1105 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1106 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1107 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1108 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1109 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1110 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1111 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1112 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1113 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1114 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1115 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1116 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1117 struct i40e_vsi_vlan_pvid_info *info);
1118 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1119 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1120 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1121 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1122 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1123 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1124 int i40e_fdir_setup(struct i40e_pf *pf);
1125 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1128 int i40e_fdir_configure(struct rte_eth_dev *dev);
1129 void i40e_fdir_teardown(struct i40e_pf *pf);
1130 enum i40e_filter_pctype
1131 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1132 uint16_t flow_type);
1133 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1134 enum i40e_filter_pctype pctype);
1135 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1136 enum rte_filter_op filter_op,
1138 int i40e_select_filter_input_set(struct i40e_hw *hw,
1139 struct rte_eth_input_set_conf *conf,
1140 enum rte_filter_type filter);
1141 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1142 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1143 struct rte_eth_input_set_conf *conf);
1144 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1145 struct rte_eth_input_set_conf *conf);
1146 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1147 uint32_t retval, uint8_t *msg,
1149 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1150 struct rte_eth_rxq_info *qinfo);
1151 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1152 struct rte_eth_txq_info *qinfo);
1153 struct i40e_ethertype_filter *
1154 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1155 const struct i40e_ethertype_filter_input *input);
1156 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1157 struct i40e_ethertype_filter_input *input);
1158 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1159 struct i40e_fdir_input *input);
1160 struct i40e_tunnel_filter *
1161 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1162 const struct i40e_tunnel_filter_input *input);
1163 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1164 struct i40e_tunnel_filter_input *input);
1165 uint64_t i40e_get_default_input_set(uint16_t pctype);
1166 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1167 struct rte_eth_ethertype_filter *filter,
1169 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1170 const struct rte_eth_fdir_filter *filter,
1172 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1173 const struct i40e_fdir_filter_conf *filter,
1175 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1176 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1178 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1179 struct i40e_tunnel_filter_conf *tunnel_filter,
1181 int i40e_fdir_flush(struct rte_eth_dev *dev);
1182 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1183 struct i40e_macvlan_filter *mv_f,
1184 int num, struct ether_addr *addr);
1185 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1186 struct i40e_macvlan_filter *filter,
1188 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1189 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1190 struct i40e_macvlan_filter *filter,
1192 bool is_i40e_supported(struct rte_eth_dev *dev);
1194 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1195 enum rte_filter_type filter, uint64_t inset);
1196 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1198 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1199 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1200 void i40e_check_write_global_reg(struct i40e_hw *hw,
1201 uint32_t addr, uint32_t val);
1203 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1204 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1205 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1206 struct i40e_customized_pctype*
1207 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1208 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1210 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1211 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1212 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1213 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1214 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1215 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1216 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1217 int i40e_config_rss_filter(struct i40e_pf *pf,
1218 struct i40e_rte_flow_rss_conf *conf, bool add);
1220 #define I40E_DEV_TO_PCI(eth_dev) \
1221 RTE_DEV_TO_PCI((eth_dev)->device)
1223 /* I40E_DEV_PRIVATE_TO */
1224 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1225 (&((struct i40e_adapter *)adapter)->pf)
1226 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1227 (&((struct i40e_adapter *)adapter)->hw)
1228 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1229 ((struct i40e_adapter *)adapter)
1231 /* I40EVF_DEV_PRIVATE_TO */
1232 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1233 (&((struct i40e_adapter *)adapter)->vf)
1235 static inline struct i40e_vsi *
1236 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1243 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1244 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1245 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1248 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1249 return pf->main_vsi;
1252 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1253 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1256 #define I40E_VSI_TO_HW(vsi) \
1257 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1258 #define I40E_VSI_TO_PF(vsi) \
1259 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1260 #define I40E_VSI_TO_VF(vsi) \
1261 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1262 #define I40E_VSI_TO_DEV_DATA(vsi) \
1263 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1264 #define I40E_VSI_TO_ETH_DEV(vsi) \
1265 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1268 #define I40E_PF_TO_HW(pf) \
1269 (&(((struct i40e_pf *)pf)->adapter->hw))
1270 #define I40E_PF_TO_ADAPTER(pf) \
1271 ((struct i40e_adapter *)pf->adapter)
1274 #define I40E_VF_TO_HW(vf) \
1275 (&(((struct i40e_vf *)vf)->adapter->hw))
1278 i40e_init_adminq_parameter(struct i40e_hw *hw)
1280 hw->aq.num_arq_entries = I40E_AQ_LEN;
1281 hw->aq.num_asq_entries = I40E_AQ_LEN;
1282 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1283 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1287 i40e_align_floor(int n)
1291 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1294 static inline uint16_t
1295 i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
1297 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
1299 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1302 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1304 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1308 /* Convert to hardware count, as writing each 1 represents 2 us */
1309 return interval / 2;
1313 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
1315 const char *warning;
1316 static const char *const warning_list[] = {
1317 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
1318 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
1319 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
1320 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
1321 [I40E_WARNING_TPID] = "support TPID configuration",
1322 [I40E_WARNING_FLOW_CTL] = "configure water marker",
1323 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
1324 [I40E_WARNING_QF_CTL] = "support hash function setting",
1325 [I40E_WARNING_HASH_INSET] = "configure hash input set",
1326 [I40E_WARNING_HSYM] = "set symmetric hash",
1327 [I40E_WARNING_HASH_MSK] = "configure hash mask",
1328 [I40E_WARNING_FD_MSK] = "configure fdir mask",
1329 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
1332 warning = warning_list[idx];
1334 RTE_LOG(WARNING, PMD,
1335 "Global register is changed during %s\n",
1339 #define I40E_VALID_FLOW(flow_type) \
1340 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1341 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1342 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1343 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1344 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1345 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1346 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1347 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1348 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1349 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1350 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1352 #define I40E_VALID_PCTYPE_X722(pctype) \
1353 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1354 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1355 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1356 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1357 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1358 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1359 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1360 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1361 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1362 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1363 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1364 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1365 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1366 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1367 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1368 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1369 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1371 #define I40E_VALID_PCTYPE(pctype) \
1372 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1373 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1374 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1375 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1376 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1377 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1378 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1379 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1380 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1381 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1382 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1384 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1385 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1386 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1387 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1388 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1389 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1390 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1392 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1393 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1394 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1395 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1396 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1398 #endif /* _I40E_ETHDEV_H_ */