1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
10 #include <rte_eth_ctrl.h>
12 #include <rte_kvargs.h>
15 #include <rte_flow_driver.h>
16 #include <rte_tm_driver.h>
17 #include "rte_pmd_i40e.h"
19 #include "base/i40e_register.h"
21 #define I40E_VLAN_TAG_SIZE 4
23 #define I40E_AQ_LEN 32
24 #define I40E_AQ_BUF_SZ 4096
25 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
26 #define I40E_MAX_Q_PER_TC 64
27 #define I40E_NUM_DESC_DEFAULT 512
28 #define I40E_NUM_DESC_ALIGN 32
29 #define I40E_BUF_SIZE_MIN 1024
30 #define I40E_FRAME_SIZE_MAX 9728
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
89 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
91 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
92 "with value 0x%08x", \
96 /* index flex payload per layer */
97 enum i40e_flxpld_layer_idx {
98 I40E_FLXPLD_L2_IDX = 0,
99 I40E_FLXPLD_L3_IDX = 1,
100 I40E_FLXPLD_L4_IDX = 2,
101 I40E_MAX_FLXPLD_LAYER = 3,
103 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
104 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
105 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
106 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
107 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
110 #define I40E_FLAG_RSS (1ULL << 0)
111 #define I40E_FLAG_DCB (1ULL << 1)
112 #define I40E_FLAG_VMDQ (1ULL << 2)
113 #define I40E_FLAG_SRIOV (1ULL << 3)
114 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
115 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
116 #define I40E_FLAG_FDIR (1ULL << 6)
117 #define I40E_FLAG_VXLAN (1ULL << 7)
118 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
119 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
120 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
124 I40E_FLAG_HEADER_SPLIT_DISABLED | \
125 I40E_FLAG_HEADER_SPLIT_ENABLED | \
128 I40E_FLAG_RSS_AQ_CAPABLE | \
129 I40E_FLAG_VF_MAC_BY_PF)
131 #define I40E_RSS_OFFLOAD_ALL ( \
132 ETH_RSS_FRAG_IPV4 | \
133 ETH_RSS_NONFRAG_IPV4_TCP | \
134 ETH_RSS_NONFRAG_IPV4_UDP | \
135 ETH_RSS_NONFRAG_IPV4_SCTP | \
136 ETH_RSS_NONFRAG_IPV4_OTHER | \
137 ETH_RSS_FRAG_IPV6 | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP | \
140 ETH_RSS_NONFRAG_IPV6_SCTP | \
141 ETH_RSS_NONFRAG_IPV6_OTHER | \
144 /* All bits of RSS hash enable for X722*/
145 #define I40E_RSS_HENA_ALL_X722 ( \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
150 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
154 /* All bits of RSS hash enable */
155 #define I40E_RSS_HENA_ALL ( \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
160 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
165 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
166 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
167 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
168 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
169 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
171 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
172 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
174 /* Default queue interrupt throttling time in microseconds */
175 #define I40E_ITR_INDEX_DEFAULT 0
176 #define I40E_ITR_INDEX_NONE 3
177 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
178 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
179 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 8160 /* 8160 us */
180 /* Special FW support this floating VEB feature */
181 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
182 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
184 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
185 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
186 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
187 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
189 #define I40E_INSET_NONE 0x00000000000000000ULL
192 #define I40E_INSET_DMAC 0x0000000000000001ULL
193 #define I40E_INSET_SMAC 0x0000000000000002ULL
194 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
195 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
196 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
199 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
200 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
201 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
202 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
203 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
204 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
205 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
207 /* bit 16 ~ bit 31 */
208 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
209 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
210 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
211 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
212 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
213 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
214 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
215 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
217 /* bit 32 ~ bit 47, tunnel fields */
218 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
219 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
220 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
221 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
222 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
223 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
225 /* bit 48 ~ bit 55 */
226 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
228 /* bit 56 ~ bit 63, Flex Payload */
229 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
230 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
231 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
232 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
233 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
234 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
235 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
236 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
237 #define I40E_INSET_FLEX_PAYLOAD \
238 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
239 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
240 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
241 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
243 /* The max bandwidth of i40e is 40Gbps. */
244 #define I40E_QOS_BW_MAX 40000
245 /* The bandwidth should be the multiple of 50Mbps. */
246 #define I40E_QOS_BW_GRANULARITY 50
247 /* The min bandwidth weight is 1. */
248 #define I40E_QOS_BW_WEIGHT_MIN 1
249 /* The max bandwidth weight is 127. */
250 #define I40E_QOS_BW_WEIGHT_MAX 127
251 /* The max queue region index is 7. */
252 #define I40E_REGION_MAX_INDEX 7
254 #define I40E_MAX_PERCENT 100
255 #define I40E_DEFAULT_DCB_APP_NUM 1
256 #define I40E_DEFAULT_DCB_APP_PRIO 3
259 * The overhead from MTU to max frame size.
260 * Considering QinQ packet, the VLAN tag needs to be counted twice.
262 #define I40E_ETH_OVERHEAD \
263 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
268 * MAC filter structure
270 struct i40e_mac_filter_info {
271 enum rte_mac_filter_type filter_type;
272 struct ether_addr mac_addr;
275 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
277 /* MAC filter list structure */
278 struct i40e_mac_filter {
279 TAILQ_ENTRY(i40e_mac_filter) next;
280 struct i40e_mac_filter_info mac_info;
283 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
287 /* VSI list structure */
288 struct i40e_vsi_list {
289 TAILQ_ENTRY(i40e_vsi_list) list;
290 struct i40e_vsi *vsi;
293 struct i40e_rx_queue;
294 struct i40e_tx_queue;
296 /* Bandwidth limit information */
297 struct i40e_bw_info {
298 uint16_t bw_limit; /* BW Limit (0 = disabled) */
299 uint8_t bw_max; /* Max BW limit if enabled */
301 /* Relative credits within same TC with respect to other VSIs or Comps */
302 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
303 /* Bandwidth limit per TC */
304 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
305 /* Max bandwidth limit per TC */
306 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
309 /* Structure that defines a VEB */
311 struct i40e_vsi_list_head head;
312 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
313 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
314 uint16_t seid; /* The seid of VEB itself */
315 uint16_t uplink_seid; /* The uplink seid of this VEB */
317 struct i40e_eth_stats stats;
318 uint8_t enabled_tc; /* The traffic class enabled */
319 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
320 struct i40e_bw_info bw_info; /* VEB bandwidth information */
323 /* i40e MACVLAN filter structure */
324 struct i40e_macvlan_filter {
325 struct ether_addr macaddr;
326 enum rte_mac_filter_type filter_type;
331 * Structure that defines a VSI, associated with a adapter.
334 struct i40e_adapter *adapter; /* Backreference to associated adapter */
335 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
337 struct i40e_eth_stats eth_stats_offset;
338 struct i40e_eth_stats eth_stats;
340 * When drivers loaded, only a default main VSI exists. In case new VSI
341 * needs to add, HW needs to know the layout that VSIs are organized.
342 * Besides that, VSI isan element and can't switch packets, which needs
343 * to add new component VEB to perform switching. So, a new VSI needs
344 * to specify the uplink VSI (Parent VSI) before created. The
345 * uplink VSI will check whether it had a VEB to switch packets. If no,
346 * it will try to create one. Then, uplink VSI will move the new VSI
347 * into its' sib_vsi_list to manage all the downlink VSI.
348 * sib_vsi_list: the VSI list that shared the same uplink VSI.
349 * parent_vsi : the uplink VSI. It's NULL for main VSI.
350 * veb : the VEB associates with the VSI.
352 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
353 struct i40e_vsi *parent_vsi;
354 struct i40e_veb *veb; /* Associated veb, could be null */
355 struct i40e_veb *floating_veb; /* Associated floating veb */
357 enum i40e_vsi_type type; /* VSI types */
358 uint16_t vlan_num; /* Total VLAN number */
359 uint16_t mac_num; /* Total mac number */
360 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
361 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
362 /* specific VSI-defined parameters, SRIOV stored the vf_id */
364 uint16_t seid; /* The seid of VSI itself */
365 uint16_t uplink_seid; /* The uplink seid of this VSI */
366 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
367 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
368 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
369 uint16_t base_queue; /* The first queue index of this VSI */
371 * The offset to visit VSI related register, assigned by HW when
375 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
376 uint16_t nb_msix; /* The max number of msix vector */
377 uint8_t enabled_tc; /* The traffic class enabled */
378 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
379 uint8_t vlan_filter_on; /* The VLAN filter enabled */
380 struct i40e_bw_info bw_info; /* VSI bandwidth information */
384 LIST_ENTRY(pool_entry) next;
389 LIST_HEAD(res_list, pool_entry);
391 struct i40e_res_pool_info {
392 uint32_t base; /* Resource start index */
393 uint32_t num_alloc; /* Allocated resource number */
394 uint32_t num_free; /* Total available resource number */
395 struct res_list alloc_list; /* Allocated resource list */
396 struct res_list free_list; /* Available resource list */
400 I40E_VF_INACTIVE = 0,
407 * Structure to store private data for PF host.
411 struct i40e_vsi *vsi;
412 enum I40E_VF_STATE state; /* The number of queue pairs available */
413 uint16_t vf_idx; /* VF index in pf->vfs */
414 uint16_t lan_nb_qps; /* Actual queues allocated */
415 uint16_t reset_cnt; /* Total vf reset times */
416 struct ether_addr mac_addr; /* Default MAC address */
417 /* version of the virtchnl from VF */
418 struct virtchnl_version_info version;
419 uint32_t request_caps; /* offload caps requested from VF */
423 * Structure to store private data for flow control.
425 struct i40e_fc_conf {
426 uint16_t pause_time; /* Flow control pause timer */
427 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
428 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
429 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
430 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
434 * Structure to store private data for VMDQ instance
436 struct i40e_vmdq_info {
438 struct i40e_vsi *vsi;
441 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
442 #define I40E_MAX_FLX_SOURCE_OFF 480
443 #define NONUSE_FLX_PIT_DEST_OFF 63
444 #define NONUSE_FLX_PIT_FSIZE 1
445 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
446 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
447 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
448 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
449 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
450 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
451 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
452 NONUSE_FLX_PIT_DEST_OFF : \
453 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
454 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
455 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
456 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
457 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
458 #define I40E_FDIR_IPv6_TC_OFFSET 20
460 /* A structure used to define the input for GTP flow */
461 struct i40e_gtp_flow {
462 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
463 uint8_t msg_type; /* Message type. */
464 uint32_t teid; /* TEID in big endian. */
467 /* A structure used to define the input for GTP IPV4 flow */
468 struct i40e_gtp_ipv4_flow {
469 struct i40e_gtp_flow gtp;
470 struct rte_eth_ipv4_flow ip4;
473 /* A structure used to define the input for GTP IPV6 flow */
474 struct i40e_gtp_ipv6_flow {
475 struct i40e_gtp_flow gtp;
476 struct rte_eth_ipv6_flow ip6;
479 /* A structure used to define the input for raw type flow */
480 struct i40e_raw_flow {
487 * A union contains the inputs for all types of flow
488 * items in flows need to be in big endian
490 union i40e_fdir_flow {
491 struct rte_eth_l2_flow l2_flow;
492 struct rte_eth_udpv4_flow udp4_flow;
493 struct rte_eth_tcpv4_flow tcp4_flow;
494 struct rte_eth_sctpv4_flow sctp4_flow;
495 struct rte_eth_ipv4_flow ip4_flow;
496 struct rte_eth_udpv6_flow udp6_flow;
497 struct rte_eth_tcpv6_flow tcp6_flow;
498 struct rte_eth_sctpv6_flow sctp6_flow;
499 struct rte_eth_ipv6_flow ipv6_flow;
500 struct i40e_gtp_flow gtp_flow;
501 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
502 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
503 struct i40e_raw_flow raw_flow;
506 enum i40e_fdir_ip_type {
507 I40E_FDIR_IPTYPE_IPV4,
508 I40E_FDIR_IPTYPE_IPV6,
511 /* A structure used to contain extend input of flow */
512 struct i40e_fdir_flow_ext {
514 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
515 /* It is filled by the flexible payload to match. */
516 uint8_t is_vf; /* 1 for VF, 0 for port dev */
517 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
518 bool inner_ip; /* If there is inner ip */
519 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
520 bool customized_pctype; /* If customized pctype is used */
521 bool pkt_template; /* If raw packet template is used */
524 /* A structure used to define the input for a flow director filter entry */
525 struct i40e_fdir_input {
526 enum i40e_filter_pctype pctype;
527 union i40e_fdir_flow flow;
528 /* Flow fields to match, dependent on flow_type */
529 struct i40e_fdir_flow_ext flow_ext;
530 /* Additional fields to match */
533 /* Behavior will be taken if FDIR match */
534 enum i40e_fdir_behavior {
535 I40E_FDIR_ACCEPT = 0,
540 /* Flow director report status
541 * It defines what will be reported if FDIR entry is matched.
543 enum i40e_fdir_status {
544 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
545 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
546 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
547 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
550 /* A structure used to define an action when match FDIR packet filter. */
551 struct i40e_fdir_action {
552 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
553 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
554 enum i40e_fdir_status report_status; /* Status report option */
555 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
556 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
557 * flex bytes start from in flexible payload.
562 /* A structure used to define the flow director filter entry by filter_ctrl API
563 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
564 * RTE_ETH_FILTER_DELETE operations.
566 struct i40e_fdir_filter_conf {
568 /* ID, an unique value is required when deal with FDIR entry */
569 struct i40e_fdir_input input; /* Input set */
570 struct i40e_fdir_action action; /* Action taken when match */
574 * Structure to store flex pit for flow diretor.
576 struct i40e_fdir_flex_pit {
577 uint8_t src_offset; /* offset in words from the beginning of payload */
578 uint8_t size; /* size in words */
579 uint8_t dst_offset; /* offset in words of flexible payload */
582 struct i40e_fdir_flex_mask {
583 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
588 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
591 #define I40E_FILTER_PCTYPE_INVALID 0
592 #define I40E_FILTER_PCTYPE_MAX 64
593 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
595 struct i40e_fdir_filter {
596 TAILQ_ENTRY(i40e_fdir_filter) rules;
597 struct i40e_fdir_filter_conf fdir;
600 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
602 * A structure used to define fields of a FDIR related info.
604 struct i40e_fdir_info {
605 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
606 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
607 struct i40e_tx_queue *txq;
608 struct i40e_rx_queue *rxq;
609 void *prg_pkt; /* memory for fdir program packet */
610 uint64_t dma_addr; /* physic address of packet memory*/
611 /* input set bits for each pctype */
612 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
614 * the rule how bytes stream is extracted as flexible payload
615 * for each payload layer, the setting can up to three elements
617 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
618 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
620 struct i40e_fdir_filter_list fdir_list;
621 struct i40e_fdir_filter **hash_map;
622 struct rte_hash *hash_table;
624 /* Mark if flex pit and mask is set */
625 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
626 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
628 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
631 /* Ethertype filter number HW supports */
632 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
634 /* Ethertype filter struct */
635 struct i40e_ethertype_filter_input {
636 struct ether_addr mac_addr; /* Mac address to match */
637 uint16_t ether_type; /* Ether type to match */
640 struct i40e_ethertype_filter {
641 TAILQ_ENTRY(i40e_ethertype_filter) rules;
642 struct i40e_ethertype_filter_input input;
643 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
644 uint16_t queue; /* Queue assigned to when match */
647 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
649 struct i40e_ethertype_rule {
650 struct i40e_ethertype_filter_list ethertype_list;
651 struct i40e_ethertype_filter **hash_map;
652 struct rte_hash *hash_table;
655 /* queue region info */
656 struct i40e_queue_region_info {
657 /* the region id for this configuration */
659 /* the start queue index for this region */
660 uint8_t queue_start_index;
661 /* the total queue number of this queue region */
663 /* the total number of user priority for this region */
664 uint8_t user_priority_num;
665 /* the packet's user priority for this region */
666 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
667 /* the total number of flowtype for this region */
668 uint8_t flowtype_num;
670 * the pctype or hardware flowtype of packet,
671 * the specific index for each type has been defined
672 * in file i40e_type.h as enum i40e_filter_pctype.
674 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
677 struct i40e_queue_regions {
678 /* the total number of queue region for this port */
679 uint16_t queue_region_number;
680 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
683 /* Tunnel filter number HW supports */
684 #define I40E_MAX_TUNNEL_FILTER_NUM 400
686 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
687 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
688 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
689 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
690 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
691 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
692 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
693 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
694 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
695 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
696 #define I40E_AQC_NEW_TR_21 21
697 #define I40E_AQC_NEW_TR_22 22
699 enum i40e_tunnel_iptype {
700 I40E_TUNNEL_IPTYPE_IPV4,
701 I40E_TUNNEL_IPTYPE_IPV6,
704 /* Tunnel filter struct */
705 struct i40e_tunnel_filter_input {
706 uint8_t outer_mac[6]; /* Outer mac address to match */
707 uint8_t inner_mac[6]; /* Inner mac address to match */
708 uint16_t inner_vlan; /* Inner vlan address to match */
709 enum i40e_tunnel_iptype ip_type;
710 uint16_t flags; /* Filter type flag */
711 uint32_t tenant_id; /* Tenant id to match */
712 uint16_t general_fields[32]; /* Big buffer */
715 struct i40e_tunnel_filter {
716 TAILQ_ENTRY(i40e_tunnel_filter) rules;
717 struct i40e_tunnel_filter_input input;
718 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
719 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
720 uint16_t queue; /* Queue assigned to when match */
723 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
725 struct i40e_tunnel_rule {
726 struct i40e_tunnel_filter_list tunnel_list;
727 struct i40e_tunnel_filter **hash_map;
728 struct rte_hash *hash_table;
734 enum i40e_tunnel_type {
735 I40E_TUNNEL_TYPE_NONE = 0,
736 I40E_TUNNEL_TYPE_VXLAN,
737 I40E_TUNNEL_TYPE_GENEVE,
738 I40E_TUNNEL_TYPE_TEREDO,
739 I40E_TUNNEL_TYPE_NVGRE,
740 I40E_TUNNEL_TYPE_IP_IN_GRE,
741 I40E_L2_TUNNEL_TYPE_E_TAG,
742 I40E_TUNNEL_TYPE_MPLSoUDP,
743 I40E_TUNNEL_TYPE_MPLSoGRE,
744 I40E_TUNNEL_TYPE_QINQ,
745 I40E_TUNNEL_TYPE_GTPC,
746 I40E_TUNNEL_TYPE_GTPU,
747 I40E_TUNNEL_TYPE_MAX,
751 * Tunneling Packet filter configuration.
753 struct i40e_tunnel_filter_conf {
754 struct ether_addr outer_mac; /**< Outer MAC address to match. */
755 struct ether_addr inner_mac; /**< Inner MAC address to match. */
756 uint16_t inner_vlan; /**< Inner VLAN to match. */
757 uint32_t outer_vlan; /**< Outer VLAN to match */
758 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
760 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
761 * is set in filter_type, or inner destination IP address to match
762 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
765 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
766 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
768 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
769 uint16_t filter_type;
770 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
771 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
772 uint16_t queue_id; /**< Queue assigned to if match. */
773 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
774 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
777 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
778 #define I40E_MAX_MIRROR_RULES 64
780 * Mirror rule structure
782 struct i40e_mirror_rule {
783 TAILQ_ENTRY(i40e_mirror_rule) rules;
785 uint16_t index; /* the sw index of mirror rule */
786 uint16_t id; /* the rule id assigned by firmware */
787 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
788 uint16_t num_entries;
789 /* the info stores depend on the rule type.
790 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
791 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
793 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
796 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
799 * Struct to store flow created.
802 TAILQ_ENTRY(rte_flow) node;
803 enum rte_filter_type filter_type;
807 TAILQ_HEAD(i40e_flow_list, rte_flow);
809 /* Struct to store Traffic Manager shaper profile. */
810 struct i40e_tm_shaper_profile {
811 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
812 uint32_t shaper_profile_id;
813 uint32_t reference_count;
814 struct rte_tm_shaper_params profile;
817 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
819 /* node type of Traffic Manager */
820 enum i40e_tm_node_type {
821 I40E_TM_NODE_TYPE_PORT,
822 I40E_TM_NODE_TYPE_TC,
823 I40E_TM_NODE_TYPE_QUEUE,
824 I40E_TM_NODE_TYPE_MAX,
827 /* Struct to store Traffic Manager node configuration. */
828 struct i40e_tm_node {
829 TAILQ_ENTRY(i40e_tm_node) node;
833 uint32_t reference_count;
834 struct i40e_tm_node *parent;
835 struct i40e_tm_shaper_profile *shaper_profile;
836 struct rte_tm_node_params params;
839 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
841 /* Struct to store all the Traffic Manager configuration. */
842 struct i40e_tm_conf {
843 struct i40e_shaper_profile_list shaper_profile_list;
844 struct i40e_tm_node *root; /* root node - port */
845 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
846 struct i40e_tm_node_list queue_list; /* node list for all the queues */
848 * The number of added TC nodes.
849 * It should be no more than the TC number of this port.
853 * The number of added queue nodes.
854 * It should be no more than the queue number of this port.
856 uint32_t nb_queue_node;
858 * This flag is used to check if APP can change the TM node
860 * When it's true, means the configuration is applied to HW,
861 * APP should not change the configuration.
862 * As we don't support on-the-fly configuration, when starting
863 * the port, APP should call the hierarchy_commit API to set this
864 * flag to true. When stopping the port, this flag should be set
870 enum i40e_new_pctype {
871 I40E_CUSTOMIZED_GTPC = 0,
872 I40E_CUSTOMIZED_GTPU_IPV4,
873 I40E_CUSTOMIZED_GTPU_IPV6,
874 I40E_CUSTOMIZED_GTPU,
878 #define I40E_FILTER_PCTYPE_INVALID 0
879 struct i40e_customized_pctype {
880 enum i40e_new_pctype index; /* Indicate which customized pctype */
881 uint8_t pctype; /* New pctype value */
882 bool valid; /* Check if it's valid */
885 struct i40e_rte_flow_rss_conf {
886 struct rte_flow_action_rss conf; /**< RSS parameters. */
887 uint16_t queue_region_conf; /**< Queue region config flag */
888 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
889 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX) + 1 *
890 sizeof(uint32_t)]; /* Hash key. */
891 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
895 * Structure to store private data specific for PF instance.
898 struct i40e_adapter *adapter; /* The adapter this PF associate to */
899 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
900 uint16_t mac_seid; /* The seid of the MAC of this PF */
901 uint16_t main_vsi_seid; /* The seid of the main VSI */
902 uint16_t max_num_vsi;
903 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
904 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
906 struct i40e_hw_port_stats stats_offset;
907 struct i40e_hw_port_stats stats;
908 /* internal packet statistics, it should be excluded from the total */
909 struct i40e_eth_stats internal_stats_offset;
910 struct i40e_eth_stats internal_stats;
913 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
914 struct ether_addr dev_addr; /* PF device mac address */
915 uint64_t flags; /* PF feature flags */
916 /* All kinds of queue pair setting for different VSIs */
917 struct i40e_pf_vf *vfs;
919 /* Each of below queue pairs should be power of 2 since it's the
920 precondition after TC configuration applied */
921 uint16_t lan_nb_qp_max;
922 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
923 uint16_t lan_qp_offset;
924 uint16_t vmdq_nb_qp_max;
925 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
926 uint16_t vmdq_qp_offset;
927 uint16_t vf_nb_qp_max;
928 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
929 uint16_t vf_qp_offset;
930 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
931 uint16_t fdir_qp_offset;
933 uint16_t hash_lut_size; /* The size of hash lookup table */
934 /* input set bits for each pctype */
935 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
936 /* store VXLAN UDP ports */
937 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
938 uint16_t vxlan_bitmap; /* Vxlan bit mask */
940 /* VMDQ related info */
941 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
942 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
943 struct i40e_vmdq_info *vmdq;
945 struct i40e_fdir_info fdir; /* flow director info */
946 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
947 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
948 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
949 struct i40e_queue_regions queue_region; /* queue region info */
950 struct i40e_fc_conf fc_conf; /* Flow control conf */
951 struct i40e_mirror_rule_list mirror_list;
952 uint16_t nb_mirror_rule; /* The number of mirror rules */
953 bool floating_veb; /* The flag to use the floating VEB */
954 /* The floating enable flag for the specific VF */
955 bool floating_veb_list[I40E_MAX_VF];
956 struct i40e_flow_list flow_list;
957 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
958 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
959 bool qinq_replace_flag; /* QINQ filter replace is done */
960 struct i40e_tm_conf tm_conf;
961 bool support_multi_driver; /* 1 - support multiple driver */
963 /* Dynamic Device Personalization */
964 bool gtp_support; /* 1 - support GTP-C and GTP-U */
965 /* customer customized pctype */
966 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
970 PFMSG_LINK_CHANGE = 0x1,
971 PFMSG_RESET_IMPENDING = 0x2,
972 PFMSG_DRIVER_CLOSE = 0x4,
975 struct i40e_vsi_vlan_pvid_info {
976 uint16_t on; /* Enable or disable pvid */
978 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
980 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
981 * while 'untagged' will reject untagged packets.
989 struct i40e_vf_rx_queues {
990 uint64_t rx_dma_addr;
991 uint32_t rx_ring_len;
995 struct i40e_vf_tx_queues {
996 uint64_t tx_dma_addr;
997 uint32_t tx_ring_len;
1001 * Structure to store private data specific for VF instance.
1004 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1005 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1006 uint16_t num_queue_pairs;
1007 uint16_t max_pkt_len; /* Maximum packet length */
1008 bool promisc_unicast_enabled;
1009 bool promisc_multicast_enabled;
1011 uint32_t version_major; /* Major version number */
1012 uint32_t version_minor; /* Minor version number */
1013 uint16_t promisc_flags; /* Promiscuous setting */
1014 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1016 struct ether_addr mc_addrs[I40E_NUM_MACADDR_MAX]; /* Multicast addrs */
1017 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1022 enum virtchnl_link_speed link_speed;
1024 volatile uint32_t pend_cmd; /* pending command not finished yet */
1025 int32_t cmd_retval; /* return value of the cmd response from PF */
1026 u16 pend_msg; /* flags indicates events from pf not handled yet */
1027 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1030 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1031 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1032 struct i40e_vsi vsi;
1036 #define I40E_MAX_PKT_TYPE 256
1037 #define I40E_FLOW_TYPE_MAX 64
1040 * Structure to store private data for each PF/VF instance.
1042 struct i40e_adapter {
1043 /* Common for both PF and VF */
1045 struct rte_eth_dev *eth_dev;
1047 /* Specific for PF or VF */
1053 /* For vector PMD */
1054 bool rx_bulk_alloc_allowed;
1055 bool rx_vec_allowed;
1056 bool tx_simple_allowed;
1057 bool tx_vec_allowed;
1060 struct rte_timecounter systime_tc;
1061 struct rte_timecounter rx_tstamp_tc;
1062 struct rte_timecounter tx_tstamp_tc;
1064 /* ptype mapping table */
1065 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1066 /* flow type to pctype mapping table */
1067 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1068 uint64_t flow_types_mask;
1069 uint64_t pctypes_mask;
1072 extern const struct rte_flow_ops i40e_flow_ops;
1074 union i40e_filter_t {
1075 struct rte_eth_ethertype_filter ethertype_filter;
1076 struct i40e_fdir_filter_conf fdir_filter;
1077 struct rte_eth_tunnel_filter_conf tunnel_filter;
1078 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1079 struct i40e_rte_flow_rss_conf rss_conf;
1082 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1083 const struct rte_flow_attr *attr,
1084 const struct rte_flow_item pattern[],
1085 const struct rte_flow_action actions[],
1086 struct rte_flow_error *error,
1087 union i40e_filter_t *filter);
1088 struct i40e_valid_pattern {
1089 enum rte_flow_item_type *items;
1090 parse_filter_t parse_filter;
1093 enum I40E_WARNING_IDX {
1094 I40E_WARNING_DIS_FLX_PLD,
1095 I40E_WARNING_ENA_FLX_PLD,
1096 I40E_WARNING_QINQ_PARSER,
1097 I40E_WARNING_QINQ_CLOUD_FILTER,
1099 I40E_WARNING_FLOW_CTL,
1100 I40E_WARNING_GRE_KEY_LEN,
1101 I40E_WARNING_QF_CTL,
1102 I40E_WARNING_HASH_INSET,
1104 I40E_WARNING_HASH_MSK,
1105 I40E_WARNING_FD_MSK,
1106 I40E_WARNING_RPL_CLD_FILTER,
1109 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1110 int i40e_vsi_release(struct i40e_vsi *vsi);
1111 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1112 enum i40e_vsi_type type,
1113 struct i40e_vsi *uplink_vsi,
1114 uint16_t user_param);
1115 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1116 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1117 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1118 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1119 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1120 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1121 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1122 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1123 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1124 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1125 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1126 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1127 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1128 struct i40e_vsi_vlan_pvid_info *info);
1129 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1130 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1131 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1132 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1133 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1134 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1135 int i40e_fdir_setup(struct i40e_pf *pf);
1136 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1139 int i40e_fdir_configure(struct rte_eth_dev *dev);
1140 void i40e_fdir_teardown(struct i40e_pf *pf);
1141 enum i40e_filter_pctype
1142 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1143 uint16_t flow_type);
1144 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1145 enum i40e_filter_pctype pctype);
1146 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1147 enum rte_filter_op filter_op,
1149 int i40e_select_filter_input_set(struct i40e_hw *hw,
1150 struct rte_eth_input_set_conf *conf,
1151 enum rte_filter_type filter);
1152 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1153 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1154 struct rte_eth_input_set_conf *conf);
1155 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1156 struct rte_eth_input_set_conf *conf);
1157 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1158 uint32_t retval, uint8_t *msg,
1160 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1161 struct rte_eth_rxq_info *qinfo);
1162 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1163 struct rte_eth_txq_info *qinfo);
1164 struct i40e_ethertype_filter *
1165 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1166 const struct i40e_ethertype_filter_input *input);
1167 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1168 struct i40e_ethertype_filter_input *input);
1169 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1170 struct i40e_fdir_input *input);
1171 struct i40e_tunnel_filter *
1172 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1173 const struct i40e_tunnel_filter_input *input);
1174 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1175 struct i40e_tunnel_filter_input *input);
1176 uint64_t i40e_get_default_input_set(uint16_t pctype);
1177 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1178 struct rte_eth_ethertype_filter *filter,
1180 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1181 const struct rte_eth_fdir_filter *filter,
1183 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1184 const struct i40e_fdir_filter_conf *filter,
1186 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1187 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1189 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1190 struct i40e_tunnel_filter_conf *tunnel_filter,
1192 int i40e_fdir_flush(struct rte_eth_dev *dev);
1193 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1194 struct i40e_macvlan_filter *mv_f,
1195 int num, struct ether_addr *addr);
1196 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1197 struct i40e_macvlan_filter *filter,
1199 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1200 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1201 struct i40e_macvlan_filter *filter,
1203 bool is_i40e_supported(struct rte_eth_dev *dev);
1205 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1206 enum rte_filter_type filter, uint64_t inset);
1207 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1209 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1210 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1211 void i40e_check_write_global_reg(struct i40e_hw *hw,
1212 uint32_t addr, uint32_t val);
1214 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1215 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1216 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1217 struct i40e_customized_pctype*
1218 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1219 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1221 enum rte_pmd_i40e_package_op op);
1222 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1223 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1224 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1225 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1226 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1227 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1228 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1229 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1230 const struct rte_flow_action_rss *in);
1231 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1232 const struct rte_flow_action_rss *with);
1233 int i40e_config_rss_filter(struct i40e_pf *pf,
1234 struct i40e_rte_flow_rss_conf *conf, bool add);
1236 #define I40E_DEV_TO_PCI(eth_dev) \
1237 RTE_DEV_TO_PCI((eth_dev)->device)
1239 /* I40E_DEV_PRIVATE_TO */
1240 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1241 (&((struct i40e_adapter *)adapter)->pf)
1242 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1243 (&((struct i40e_adapter *)adapter)->hw)
1244 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1245 ((struct i40e_adapter *)adapter)
1247 /* I40EVF_DEV_PRIVATE_TO */
1248 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1249 (&((struct i40e_adapter *)adapter)->vf)
1251 static inline struct i40e_vsi *
1252 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1259 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1260 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1261 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1265 return pf->main_vsi;
1268 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1269 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1272 #define I40E_VSI_TO_HW(vsi) \
1273 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1274 #define I40E_VSI_TO_PF(vsi) \
1275 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1276 #define I40E_VSI_TO_VF(vsi) \
1277 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1278 #define I40E_VSI_TO_DEV_DATA(vsi) \
1279 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1280 #define I40E_VSI_TO_ETH_DEV(vsi) \
1281 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1284 #define I40E_PF_TO_HW(pf) \
1285 (&(((struct i40e_pf *)pf)->adapter->hw))
1286 #define I40E_PF_TO_ADAPTER(pf) \
1287 ((struct i40e_adapter *)pf->adapter)
1290 #define I40E_VF_TO_HW(vf) \
1291 (&(((struct i40e_vf *)vf)->adapter->hw))
1294 i40e_init_adminq_parameter(struct i40e_hw *hw)
1296 hw->aq.num_arq_entries = I40E_AQ_LEN;
1297 hw->aq.num_asq_entries = I40E_AQ_LEN;
1298 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1299 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1303 i40e_align_floor(int n)
1307 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1310 static inline uint16_t
1311 i40e_calc_itr_interval(int16_t interval, bool is_pf, bool is_multi_drv)
1313 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
1315 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1318 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1320 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1324 /* Convert to hardware count, as writing each 1 represents 2 us */
1325 return interval / 2;
1329 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
1331 const char *warning;
1332 static const char *const warning_list[] = {
1333 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
1334 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
1335 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
1336 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
1337 [I40E_WARNING_TPID] = "support TPID configuration",
1338 [I40E_WARNING_FLOW_CTL] = "configure water marker",
1339 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
1340 [I40E_WARNING_QF_CTL] = "support hash function setting",
1341 [I40E_WARNING_HASH_INSET] = "configure hash input set",
1342 [I40E_WARNING_HSYM] = "set symmetric hash",
1343 [I40E_WARNING_HASH_MSK] = "configure hash mask",
1344 [I40E_WARNING_FD_MSK] = "configure fdir mask",
1345 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
1348 warning = warning_list[idx];
1350 RTE_LOG(WARNING, PMD,
1351 "Global register is changed during %s\n",
1355 #define I40E_VALID_FLOW(flow_type) \
1356 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1357 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1358 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1359 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1360 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1361 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1362 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1363 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1364 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1365 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1366 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1368 #define I40E_VALID_PCTYPE_X722(pctype) \
1369 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1370 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1371 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1372 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1373 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1374 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1375 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1376 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1377 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1378 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1379 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1380 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1381 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1382 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1383 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1384 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1385 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1387 #define I40E_VALID_PCTYPE(pctype) \
1388 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1389 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1390 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1391 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1392 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1393 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1394 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1395 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1396 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1397 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1398 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1400 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1401 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1402 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1403 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1404 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1405 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1406 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1408 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1409 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1410 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1411 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1412 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1414 #endif /* _I40E_ETHDEV_H_ */