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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
42 #include <rte_tm_driver.h>
44 #define I40E_VLAN_TAG_SIZE 4
46 #define I40E_AQ_LEN 32
47 #define I40E_AQ_BUF_SZ 4096
48 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
49 #define I40E_MAX_Q_PER_TC 64
50 #define I40E_NUM_DESC_DEFAULT 512
51 #define I40E_NUM_DESC_ALIGN 32
52 #define I40E_BUF_SIZE_MIN 1024
53 #define I40E_FRAME_SIZE_MAX 9728
54 #define I40E_QUEUE_BASE_ADDR_UNIT 128
55 /* number of VSIs and queue default setting */
56 #define I40E_MAX_QP_NUM_PER_VF 16
57 #define I40E_DEFAULT_QP_NUM_FDIR 1
58 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
59 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
60 /* Maximun number of MAC addresses */
61 #define I40E_NUM_MACADDR_MAX 64
62 /* Maximum number of VFs */
63 #define I40E_MAX_VF 128
66 * vlan_id is a 12 bit number.
67 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
68 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
69 * The higher 7 bit val specifies VFTA array index.
71 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
72 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
74 /* Default TC traffic in case DCB is not enabled */
75 #define I40E_DEFAULT_TCMAP 0x1
76 #define I40E_FDIR_QUEUE_ID 0
78 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
79 #define I40E_VMDQ_POOL_BASE 1
81 #define I40E_DEFAULT_RX_FREE_THRESH 32
82 #define I40E_DEFAULT_RX_PTHRESH 8
83 #define I40E_DEFAULT_RX_HTHRESH 8
84 #define I40E_DEFAULT_RX_WTHRESH 0
86 #define I40E_DEFAULT_TX_FREE_THRESH 32
87 #define I40E_DEFAULT_TX_PTHRESH 32
88 #define I40E_DEFAULT_TX_HTHRESH 0
89 #define I40E_DEFAULT_TX_WTHRESH 0
90 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
95 #define I40E_8_BIT_WIDTH CHAR_BIT
96 #define I40E_8_BIT_MASK UINT8_MAX
97 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
98 #define I40E_16_BIT_MASK UINT16_MAX
99 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
100 #define I40E_32_BIT_MASK UINT32_MAX
101 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
102 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
104 /* Linux PF host with virtchnl version 1.1 */
105 #define PF_IS_V11(vf) \
106 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
107 ((vf)->version_minor == 1))
109 /* index flex payload per layer */
110 enum i40e_flxpld_layer_idx {
111 I40E_FLXPLD_L2_IDX = 0,
112 I40E_FLXPLD_L3_IDX = 1,
113 I40E_FLXPLD_L4_IDX = 2,
114 I40E_MAX_FLXPLD_LAYER = 3,
116 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
117 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
118 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
119 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
120 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
123 #define I40E_FLAG_RSS (1ULL << 0)
124 #define I40E_FLAG_DCB (1ULL << 1)
125 #define I40E_FLAG_VMDQ (1ULL << 2)
126 #define I40E_FLAG_SRIOV (1ULL << 3)
127 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
128 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
129 #define I40E_FLAG_FDIR (1ULL << 6)
130 #define I40E_FLAG_VXLAN (1ULL << 7)
131 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
132 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
133 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
137 I40E_FLAG_HEADER_SPLIT_DISABLED | \
138 I40E_FLAG_HEADER_SPLIT_ENABLED | \
141 I40E_FLAG_RSS_AQ_CAPABLE | \
142 I40E_FLAG_VF_MAC_BY_PF)
144 #define I40E_RSS_OFFLOAD_ALL ( \
145 ETH_RSS_FRAG_IPV4 | \
146 ETH_RSS_NONFRAG_IPV4_TCP | \
147 ETH_RSS_NONFRAG_IPV4_UDP | \
148 ETH_RSS_NONFRAG_IPV4_SCTP | \
149 ETH_RSS_NONFRAG_IPV4_OTHER | \
150 ETH_RSS_FRAG_IPV6 | \
151 ETH_RSS_NONFRAG_IPV6_TCP | \
152 ETH_RSS_NONFRAG_IPV6_UDP | \
153 ETH_RSS_NONFRAG_IPV6_SCTP | \
154 ETH_RSS_NONFRAG_IPV6_OTHER | \
157 /* All bits of RSS hash enable for X722*/
158 #define I40E_RSS_HENA_ALL_X722 ( \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
167 /* All bits of RSS hash enable */
168 #define I40E_RSS_HENA_ALL ( \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
176 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
178 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
179 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
180 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
181 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
182 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
184 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
185 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
187 /* Default queue interrupt throttling time in microseconds */
188 #define I40E_ITR_INDEX_DEFAULT 0
189 #define I40E_ITR_INDEX_NONE 3
190 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
191 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
192 /* Special FW support this floating VEB feature */
193 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
194 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
196 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
197 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
198 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
199 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
201 #define I40E_INSET_NONE 0x00000000000000000ULL
204 #define I40E_INSET_DMAC 0x0000000000000001ULL
205 #define I40E_INSET_SMAC 0x0000000000000002ULL
206 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
207 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
208 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
211 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
212 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
213 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
214 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
215 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
216 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
217 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
219 /* bit 16 ~ bit 31 */
220 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
221 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
222 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
223 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
224 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
225 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
226 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
227 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
229 /* bit 32 ~ bit 47, tunnel fields */
230 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
231 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
232 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
233 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
234 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
235 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
237 /* bit 48 ~ bit 55 */
238 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
240 /* bit 56 ~ bit 63, Flex Payload */
241 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
247 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
248 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
249 #define I40E_INSET_FLEX_PAYLOAD \
250 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
251 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
252 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
253 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
255 /* The max bandwidth of i40e is 40Gbps. */
256 #define I40E_QOS_BW_MAX 40000
257 /* The bandwidth should be the multiple of 50Mbps. */
258 #define I40E_QOS_BW_GRANULARITY 50
259 /* The min bandwidth weight is 1. */
260 #define I40E_QOS_BW_WEIGHT_MIN 1
261 /* The max bandwidth weight is 127. */
262 #define I40E_QOS_BW_WEIGHT_MAX 127
265 * The overhead from MTU to max frame size.
266 * Considering QinQ packet, the VLAN tag needs to be counted twice.
268 #define I40E_ETH_OVERHEAD \
269 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
274 * MAC filter structure
276 struct i40e_mac_filter_info {
277 enum rte_mac_filter_type filter_type;
278 struct ether_addr mac_addr;
281 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
283 /* MAC filter list structure */
284 struct i40e_mac_filter {
285 TAILQ_ENTRY(i40e_mac_filter) next;
286 struct i40e_mac_filter_info mac_info;
289 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
293 /* VSI list structure */
294 struct i40e_vsi_list {
295 TAILQ_ENTRY(i40e_vsi_list) list;
296 struct i40e_vsi *vsi;
299 struct i40e_rx_queue;
300 struct i40e_tx_queue;
302 /* Bandwidth limit information */
303 struct i40e_bw_info {
304 uint16_t bw_limit; /* BW Limit (0 = disabled) */
305 uint8_t bw_max; /* Max BW limit if enabled */
307 /* Relative credits within same TC with respect to other VSIs or Comps */
308 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
309 /* Bandwidth limit per TC */
310 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
311 /* Max bandwidth limit per TC */
312 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
315 /* Structure that defines a VEB */
317 struct i40e_vsi_list_head head;
318 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
319 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
320 uint16_t seid; /* The seid of VEB itself */
321 uint16_t uplink_seid; /* The uplink seid of this VEB */
323 struct i40e_eth_stats stats;
324 uint8_t enabled_tc; /* The traffic class enabled */
325 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
326 struct i40e_bw_info bw_info; /* VEB bandwidth information */
329 /* i40e MACVLAN filter structure */
330 struct i40e_macvlan_filter {
331 struct ether_addr macaddr;
332 enum rte_mac_filter_type filter_type;
337 * Structure that defines a VSI, associated with a adapter.
340 struct i40e_adapter *adapter; /* Backreference to associated adapter */
341 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
343 struct i40e_eth_stats eth_stats_offset;
344 struct i40e_eth_stats eth_stats;
346 * When drivers loaded, only a default main VSI exists. In case new VSI
347 * needs to add, HW needs to know the layout that VSIs are organized.
348 * Besides that, VSI isan element and can't switch packets, which needs
349 * to add new component VEB to perform switching. So, a new VSI needs
350 * to specify the the uplink VSI (Parent VSI) before created. The
351 * uplink VSI will check whether it had a VEB to switch packets. If no,
352 * it will try to create one. Then, uplink VSI will move the new VSI
353 * into its' sib_vsi_list to manage all the downlink VSI.
354 * sib_vsi_list: the VSI list that shared the same uplink VSI.
355 * parent_vsi : the uplink VSI. It's NULL for main VSI.
356 * veb : the VEB associates with the VSI.
358 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
359 struct i40e_vsi *parent_vsi;
360 struct i40e_veb *veb; /* Associated veb, could be null */
361 struct i40e_veb *floating_veb; /* Associated floating veb */
363 enum i40e_vsi_type type; /* VSI types */
364 uint16_t vlan_num; /* Total VLAN number */
365 uint16_t mac_num; /* Total mac number */
366 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
367 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
368 /* specific VSI-defined parameters, SRIOV stored the vf_id */
370 uint16_t seid; /* The seid of VSI itself */
371 uint16_t uplink_seid; /* The uplink seid of this VSI */
372 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
373 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
374 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
375 uint16_t base_queue; /* The first queue index of this VSI */
377 * The offset to visit VSI related register, assigned by HW when
381 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
382 uint16_t nb_msix; /* The max number of msix vector */
383 uint8_t enabled_tc; /* The traffic class enabled */
384 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
385 uint8_t vlan_filter_on; /* The VLAN filter enabled */
386 struct i40e_bw_info bw_info; /* VSI bandwidth information */
390 LIST_ENTRY(pool_entry) next;
395 LIST_HEAD(res_list, pool_entry);
397 struct i40e_res_pool_info {
398 uint32_t base; /* Resource start index */
399 uint32_t num_alloc; /* Allocated resource number */
400 uint32_t num_free; /* Total available resource number */
401 struct res_list alloc_list; /* Allocated resource list */
402 struct res_list free_list; /* Available resource list */
406 I40E_VF_INACTIVE = 0,
413 * Structure to store private data for PF host.
417 struct i40e_vsi *vsi;
418 enum I40E_VF_STATE state; /* The number of queue pairs available */
419 uint16_t vf_idx; /* VF index in pf->vfs */
420 uint16_t lan_nb_qps; /* Actual queues allocated */
421 uint16_t reset_cnt; /* Total vf reset times */
422 struct ether_addr mac_addr; /* Default MAC address */
426 * Structure to store private data for flow control.
428 struct i40e_fc_conf {
429 uint16_t pause_time; /* Flow control pause timer */
430 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
431 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
432 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
433 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
437 * Structure to store private data for VMDQ instance
439 struct i40e_vmdq_info {
441 struct i40e_vsi *vsi;
444 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
445 #define I40E_MAX_FLX_SOURCE_OFF 480
446 #define NONUSE_FLX_PIT_DEST_OFF 63
447 #define NONUSE_FLX_PIT_FSIZE 1
448 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
449 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
450 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
451 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
452 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
453 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
454 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
455 NONUSE_FLX_PIT_DEST_OFF : \
456 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
457 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
458 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
459 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
460 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
461 #define I40E_FDIR_IPv6_TC_OFFSET 20
464 * Structure to store flex pit for flow diretor.
466 struct i40e_fdir_flex_pit {
467 uint8_t src_offset; /* offset in words from the beginning of payload */
468 uint8_t size; /* size in words */
469 uint8_t dst_offset; /* offset in words of flexible payload */
472 struct i40e_fdir_flex_mask {
473 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
478 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
481 #define I40E_FILTER_PCTYPE_MAX 64
482 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
484 struct i40e_fdir_filter {
485 TAILQ_ENTRY(i40e_fdir_filter) rules;
486 struct rte_eth_fdir_filter fdir;
489 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
491 * A structure used to define fields of a FDIR related info.
493 struct i40e_fdir_info {
494 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
495 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
496 struct i40e_tx_queue *txq;
497 struct i40e_rx_queue *rxq;
498 void *prg_pkt; /* memory for fdir program packet */
499 uint64_t dma_addr; /* physic address of packet memory*/
500 /* input set bits for each pctype */
501 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
503 * the rule how bytes stream is extracted as flexible payload
504 * for each payload layer, the setting can up to three elements
506 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
507 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
509 struct i40e_fdir_filter_list fdir_list;
510 struct i40e_fdir_filter **hash_map;
511 struct rte_hash *hash_table;
513 /* Mark if flex pit and mask is set */
514 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
515 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
517 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
520 /* Ethertype filter number HW supports */
521 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
523 /* Ethertype filter struct */
524 struct i40e_ethertype_filter_input {
525 struct ether_addr mac_addr; /* Mac address to match */
526 uint16_t ether_type; /* Ether type to match */
529 struct i40e_ethertype_filter {
530 TAILQ_ENTRY(i40e_ethertype_filter) rules;
531 struct i40e_ethertype_filter_input input;
532 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
533 uint16_t queue; /* Queue assigned to when match */
536 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
538 struct i40e_ethertype_rule {
539 struct i40e_ethertype_filter_list ethertype_list;
540 struct i40e_ethertype_filter **hash_map;
541 struct rte_hash *hash_table;
544 /* Tunnel filter number HW supports */
545 #define I40E_MAX_TUNNEL_FILTER_NUM 400
547 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
548 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
549 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP 8
550 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE 9
551 #define I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ 0x10
552 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP 0x11
553 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE 0x12
554 #define I40E_AQC_ADD_L1_FILTER_TEID_MPLS 0x11
556 enum i40e_tunnel_iptype {
557 I40E_TUNNEL_IPTYPE_IPV4,
558 I40E_TUNNEL_IPTYPE_IPV6,
561 /* Tunnel filter struct */
562 struct i40e_tunnel_filter_input {
563 uint8_t outer_mac[6]; /* Outer mac address to match */
564 uint8_t inner_mac[6]; /* Inner mac address to match */
565 uint16_t inner_vlan; /* Inner vlan address to match */
566 enum i40e_tunnel_iptype ip_type;
567 uint16_t flags; /* Filter type flag */
568 uint32_t tenant_id; /* Tenant id to match */
569 uint16_t general_fields[32]; /* Big buffer */
572 struct i40e_tunnel_filter {
573 TAILQ_ENTRY(i40e_tunnel_filter) rules;
574 struct i40e_tunnel_filter_input input;
575 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
576 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
577 uint16_t queue; /* Queue assigned to when match */
580 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
582 struct i40e_tunnel_rule {
583 struct i40e_tunnel_filter_list tunnel_list;
584 struct i40e_tunnel_filter **hash_map;
585 struct rte_hash *hash_table;
591 enum i40e_tunnel_type {
592 I40E_TUNNEL_TYPE_NONE = 0,
593 I40E_TUNNEL_TYPE_VXLAN,
594 I40E_TUNNEL_TYPE_GENEVE,
595 I40E_TUNNEL_TYPE_TEREDO,
596 I40E_TUNNEL_TYPE_NVGRE,
597 I40E_TUNNEL_TYPE_IP_IN_GRE,
598 I40E_L2_TUNNEL_TYPE_E_TAG,
599 I40E_TUNNEL_TYPE_MPLSoUDP,
600 I40E_TUNNEL_TYPE_MPLSoGRE,
601 I40E_TUNNEL_TYPE_QINQ,
602 I40E_TUNNEL_TYPE_MAX,
606 * Tunneling Packet filter configuration.
608 struct i40e_tunnel_filter_conf {
609 struct ether_addr outer_mac; /**< Outer MAC address to match. */
610 struct ether_addr inner_mac; /**< Inner MAC address to match. */
611 uint16_t inner_vlan; /**< Inner VLAN to match. */
612 uint32_t outer_vlan; /**< Outer VLAN to match */
613 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
615 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
616 * is set in filter_type, or inner destination IP address to match
617 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
620 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
621 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
623 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
624 uint16_t filter_type;
625 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
626 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
627 uint16_t queue_id; /**< Queue assigned to if match. */
628 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
629 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
632 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
633 #define I40E_MAX_MIRROR_RULES 64
635 * Mirror rule structure
637 struct i40e_mirror_rule {
638 TAILQ_ENTRY(i40e_mirror_rule) rules;
640 uint16_t index; /* the sw index of mirror rule */
641 uint16_t id; /* the rule id assigned by firmware */
642 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
643 uint16_t num_entries;
644 /* the info stores depend on the rule type.
645 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
646 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
648 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
651 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
654 * Struct to store flow created.
657 TAILQ_ENTRY(rte_flow) node;
658 enum rte_filter_type filter_type;
662 TAILQ_HEAD(i40e_flow_list, rte_flow);
664 /* Struct to store Traffic Manager shaper profile. */
665 struct i40e_tm_shaper_profile {
666 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
667 uint32_t shaper_profile_id;
668 uint32_t reference_count;
669 struct rte_tm_shaper_params profile;
672 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
674 /* node type of Traffic Manager */
675 enum i40e_tm_node_type {
676 I40E_TM_NODE_TYPE_PORT,
677 I40E_TM_NODE_TYPE_TC,
678 I40E_TM_NODE_TYPE_QUEUE,
679 I40E_TM_NODE_TYPE_MAX,
682 /* Struct to store Traffic Manager node configuration. */
683 struct i40e_tm_node {
684 TAILQ_ENTRY(i40e_tm_node) node;
688 uint32_t reference_count;
689 struct i40e_tm_node *parent;
690 struct i40e_tm_shaper_profile *shaper_profile;
691 struct rte_tm_node_params params;
694 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
696 /* Struct to store all the Traffic Manager configuration. */
697 struct i40e_tm_conf {
698 struct i40e_shaper_profile_list shaper_profile_list;
699 struct i40e_tm_node *root; /* root node - port */
700 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
701 struct i40e_tm_node_list queue_list; /* node list for all the queues */
703 * The number of added TC nodes.
704 * It should be no more than the TC number of this port.
708 * The number of added queue nodes.
709 * It should be no more than the queue number of this port.
711 uint32_t nb_queue_node;
713 * This flag is used to check if APP can change the TM node
715 * When it's true, means the configuration is applied to HW,
716 * APP should not change the configuration.
717 * As we don't support on-the-fly configuration, when starting
718 * the port, APP should call the hierarchy_commit API to set this
719 * flag to true. When stopping the port, this flag should be set
726 * Structure to store private data specific for PF instance.
729 struct i40e_adapter *adapter; /* The adapter this PF associate to */
730 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
731 uint16_t mac_seid; /* The seid of the MAC of this PF */
732 uint16_t main_vsi_seid; /* The seid of the main VSI */
733 uint16_t max_num_vsi;
734 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
735 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
737 struct i40e_hw_port_stats stats_offset;
738 struct i40e_hw_port_stats stats;
739 /* internal packet statistics, it should be excluded from the total */
740 struct i40e_eth_stats internal_stats_offset;
741 struct i40e_eth_stats internal_stats;
744 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
745 struct ether_addr dev_addr; /* PF device mac address */
746 uint64_t flags; /* PF feature flags */
747 /* All kinds of queue pair setting for different VSIs */
748 struct i40e_pf_vf *vfs;
750 /* Each of below queue pairs should be power of 2 since it's the
751 precondition after TC configuration applied */
752 uint16_t lan_nb_qp_max;
753 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
754 uint16_t lan_qp_offset;
755 uint16_t vmdq_nb_qp_max;
756 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
757 uint16_t vmdq_qp_offset;
758 uint16_t vf_nb_qp_max;
759 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
760 uint16_t vf_qp_offset;
761 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
762 uint16_t fdir_qp_offset;
764 uint16_t hash_lut_size; /* The size of hash lookup table */
765 /* input set bits for each pctype */
766 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
767 /* store VXLAN UDP ports */
768 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
769 uint16_t vxlan_bitmap; /* Vxlan bit mask */
771 /* VMDQ related info */
772 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
773 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
774 struct i40e_vmdq_info *vmdq;
776 struct i40e_fdir_info fdir; /* flow director info */
777 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
778 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
779 struct i40e_fc_conf fc_conf; /* Flow control conf */
780 struct i40e_mirror_rule_list mirror_list;
781 uint16_t nb_mirror_rule; /* The number of mirror rules */
782 bool floating_veb; /* The flag to use the floating VEB */
783 /* The floating enable flag for the specific VF */
784 bool floating_veb_list[I40E_MAX_VF];
785 struct i40e_flow_list flow_list;
786 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
787 bool qinq_replace_flag; /* QINQ filter replace is done */
788 struct i40e_tm_conf tm_conf;
792 PFMSG_LINK_CHANGE = 0x1,
793 PFMSG_RESET_IMPENDING = 0x2,
794 PFMSG_DRIVER_CLOSE = 0x4,
797 struct i40e_vsi_vlan_pvid_info {
798 uint16_t on; /* Enable or disable pvid */
800 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
802 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
803 * while 'untagged' will reject untagged packets.
811 struct i40e_vf_rx_queues {
812 uint64_t rx_dma_addr;
813 uint32_t rx_ring_len;
817 struct i40e_vf_tx_queues {
818 uint64_t tx_dma_addr;
819 uint32_t tx_ring_len;
823 * Structure to store private data specific for VF instance.
826 struct i40e_adapter *adapter; /* The adapter this VF associate to */
827 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
828 uint16_t num_queue_pairs;
829 uint16_t max_pkt_len; /* Maximum packet length */
830 bool promisc_unicast_enabled;
831 bool promisc_multicast_enabled;
833 uint32_t version_major; /* Major version number */
834 uint32_t version_minor; /* Minor version number */
835 uint16_t promisc_flags; /* Promiscuous setting */
836 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
841 enum virtchnl_link_speed link_speed;
843 volatile uint32_t pend_cmd; /* pending command not finished yet */
844 int32_t cmd_retval; /* return value of the cmd response from PF */
845 u16 pend_msg; /* flags indicates events from pf not handled yet */
846 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
849 struct virtchnl_vf_resource *vf_res; /* All VSIs */
850 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
855 #define I40E_MAX_PKT_TYPE 256
858 * Structure to store private data for each PF/VF instance.
860 struct i40e_adapter {
861 /* Common for both PF and VF */
863 struct rte_eth_dev *eth_dev;
865 /* Specific for PF or VF */
872 bool rx_bulk_alloc_allowed;
874 bool tx_simple_allowed;
878 struct rte_timecounter systime_tc;
879 struct rte_timecounter rx_tstamp_tc;
880 struct rte_timecounter tx_tstamp_tc;
882 /* ptype mapping table */
883 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
886 extern const struct rte_flow_ops i40e_flow_ops;
888 union i40e_filter_t {
889 struct rte_eth_ethertype_filter ethertype_filter;
890 struct rte_eth_fdir_filter fdir_filter;
891 struct rte_eth_tunnel_filter_conf tunnel_filter;
892 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
895 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
896 const struct rte_flow_attr *attr,
897 const struct rte_flow_item pattern[],
898 const struct rte_flow_action actions[],
899 struct rte_flow_error *error,
900 union i40e_filter_t *filter);
901 struct i40e_valid_pattern {
902 enum rte_flow_item_type *items;
903 parse_filter_t parse_filter;
906 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
907 int i40e_vsi_release(struct i40e_vsi *vsi);
908 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
909 enum i40e_vsi_type type,
910 struct i40e_vsi *uplink_vsi,
911 uint16_t user_param);
912 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
913 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
914 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
915 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
916 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
917 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
918 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
919 void i40e_pf_disable_irq0(struct i40e_hw *hw);
920 void i40e_pf_enable_irq0(struct i40e_hw *hw);
921 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
922 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
923 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
924 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
925 struct i40e_vsi_vlan_pvid_info *info);
926 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
927 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
928 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
929 uint64_t i40e_parse_hena(uint64_t flags);
930 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
931 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
932 int i40e_fdir_setup(struct i40e_pf *pf);
933 const struct rte_memzone *i40e_memzone_reserve(const char *name,
936 int i40e_fdir_configure(struct rte_eth_dev *dev);
937 void i40e_fdir_teardown(struct i40e_pf *pf);
938 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
939 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
940 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
941 enum rte_filter_op filter_op,
943 int i40e_select_filter_input_set(struct i40e_hw *hw,
944 struct rte_eth_input_set_conf *conf,
945 enum rte_filter_type filter);
946 void i40e_fdir_filter_restore(struct i40e_pf *pf);
947 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
948 struct rte_eth_input_set_conf *conf);
949 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
950 struct rte_eth_input_set_conf *conf);
951 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
952 uint32_t retval, uint8_t *msg,
954 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
955 struct rte_eth_rxq_info *qinfo);
956 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
957 struct rte_eth_txq_info *qinfo);
958 struct i40e_ethertype_filter *
959 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
960 const struct i40e_ethertype_filter_input *input);
961 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
962 struct i40e_ethertype_filter_input *input);
963 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
964 struct rte_eth_fdir_input *input);
965 struct i40e_tunnel_filter *
966 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
967 const struct i40e_tunnel_filter_input *input);
968 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
969 struct i40e_tunnel_filter_input *input);
970 uint64_t i40e_get_default_input_set(uint16_t pctype);
971 int i40e_ethertype_filter_set(struct i40e_pf *pf,
972 struct rte_eth_ethertype_filter *filter,
974 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
975 const struct rte_eth_fdir_filter *filter,
977 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
978 struct rte_eth_tunnel_filter_conf *tunnel_filter,
980 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
981 struct i40e_tunnel_filter_conf *tunnel_filter,
983 int i40e_fdir_flush(struct rte_eth_dev *dev);
984 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
985 struct i40e_macvlan_filter *mv_f,
986 int num, struct ether_addr *addr);
987 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
988 struct i40e_macvlan_filter *filter,
990 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
991 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
992 struct i40e_macvlan_filter *filter,
994 bool is_i40e_supported(struct rte_eth_dev *dev);
996 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
997 enum rte_filter_type filter, uint64_t inset);
998 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1000 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1001 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1003 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1004 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1005 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1007 #define I40E_DEV_TO_PCI(eth_dev) \
1008 RTE_DEV_TO_PCI((eth_dev)->device)
1010 /* I40E_DEV_PRIVATE_TO */
1011 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1012 (&((struct i40e_adapter *)adapter)->pf)
1013 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1014 (&((struct i40e_adapter *)adapter)->hw)
1015 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1016 ((struct i40e_adapter *)adapter)
1018 /* I40EVF_DEV_PRIVATE_TO */
1019 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1020 (&((struct i40e_adapter *)adapter)->vf)
1022 static inline struct i40e_vsi *
1023 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1030 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1031 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1032 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1036 return pf->main_vsi;
1039 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1040 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1043 #define I40E_VSI_TO_HW(vsi) \
1044 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1045 #define I40E_VSI_TO_PF(vsi) \
1046 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1047 #define I40E_VSI_TO_VF(vsi) \
1048 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1049 #define I40E_VSI_TO_DEV_DATA(vsi) \
1050 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1051 #define I40E_VSI_TO_ETH_DEV(vsi) \
1052 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1055 #define I40E_PF_TO_HW(pf) \
1056 (&(((struct i40e_pf *)pf)->adapter->hw))
1057 #define I40E_PF_TO_ADAPTER(pf) \
1058 ((struct i40e_adapter *)pf->adapter)
1061 #define I40E_VF_TO_HW(vf) \
1062 (&(((struct i40e_vf *)vf)->adapter->hw))
1065 i40e_init_adminq_parameter(struct i40e_hw *hw)
1067 hw->aq.num_arq_entries = I40E_AQ_LEN;
1068 hw->aq.num_asq_entries = I40E_AQ_LEN;
1069 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1070 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1074 i40e_align_floor(int n)
1078 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1081 static inline uint16_t
1082 i40e_calc_itr_interval(int16_t interval)
1084 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1085 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1087 /* Convert to hardware count, as writing each 1 represents 2 us */
1088 return interval / 2;
1091 #define I40E_VALID_FLOW(flow_type) \
1092 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1093 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1094 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1095 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1096 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1097 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1098 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1099 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1100 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1101 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1102 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1104 #define I40E_VALID_PCTYPE_X722(pctype) \
1105 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1106 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1107 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1108 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1109 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1110 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1111 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1112 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1113 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1114 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1115 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1116 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1117 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1118 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1119 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1120 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1121 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1123 #define I40E_VALID_PCTYPE(pctype) \
1124 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1125 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1126 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1127 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1128 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1129 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1130 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1131 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1132 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1133 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1134 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1136 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1137 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1138 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1139 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1140 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1141 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1142 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1144 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1145 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1146 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1147 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1148 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1150 #endif /* _I40E_ETHDEV_H_ */