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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
43 #define I40E_VLAN_TAG_SIZE 4
45 #define I40E_AQ_LEN 32
46 #define I40E_AQ_BUF_SZ 4096
47 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
48 #define I40E_MAX_Q_PER_TC 64
49 #define I40E_NUM_DESC_DEFAULT 512
50 #define I40E_NUM_DESC_ALIGN 32
51 #define I40E_BUF_SIZE_MIN 1024
52 #define I40E_FRAME_SIZE_MAX 9728
53 #define I40E_QUEUE_BASE_ADDR_UNIT 128
54 /* number of VSIs and queue default setting */
55 #define I40E_MAX_QP_NUM_PER_VF 16
56 #define I40E_DEFAULT_QP_NUM_FDIR 1
57 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
58 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
59 /* Maximun number of MAC addresses */
60 #define I40E_NUM_MACADDR_MAX 64
61 /* Maximum number of VFs */
62 #define I40E_MAX_VF 128
65 * vlan_id is a 12 bit number.
66 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
67 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
68 * The higher 7 bit val specifies VFTA array index.
70 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
71 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
73 /* Default TC traffic in case DCB is not enabled */
74 #define I40E_DEFAULT_TCMAP 0x1
75 #define I40E_FDIR_QUEUE_ID 0
77 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
78 #define I40E_VMDQ_POOL_BASE 1
80 #define I40E_DEFAULT_RX_FREE_THRESH 32
81 #define I40E_DEFAULT_RX_PTHRESH 8
82 #define I40E_DEFAULT_RX_HTHRESH 8
83 #define I40E_DEFAULT_RX_WTHRESH 0
85 #define I40E_DEFAULT_TX_FREE_THRESH 32
86 #define I40E_DEFAULT_TX_PTHRESH 32
87 #define I40E_DEFAULT_TX_HTHRESH 0
88 #define I40E_DEFAULT_TX_WTHRESH 0
89 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
91 /* Bit shift and mask */
92 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
93 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
94 #define I40E_8_BIT_WIDTH CHAR_BIT
95 #define I40E_8_BIT_MASK UINT8_MAX
96 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
97 #define I40E_16_BIT_MASK UINT16_MAX
98 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
99 #define I40E_32_BIT_MASK UINT32_MAX
100 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
101 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
103 /* Linux PF host with virtchnl version 1.1 */
104 #define PF_IS_V11(vf) \
105 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
106 ((vf)->version_minor == 1))
108 /* index flex payload per layer */
109 enum i40e_flxpld_layer_idx {
110 I40E_FLXPLD_L2_IDX = 0,
111 I40E_FLXPLD_L3_IDX = 1,
112 I40E_FLXPLD_L4_IDX = 2,
113 I40E_MAX_FLXPLD_LAYER = 3,
115 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
116 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
117 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
118 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
119 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
122 #define I40E_FLAG_RSS (1ULL << 0)
123 #define I40E_FLAG_DCB (1ULL << 1)
124 #define I40E_FLAG_VMDQ (1ULL << 2)
125 #define I40E_FLAG_SRIOV (1ULL << 3)
126 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
127 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
128 #define I40E_FLAG_FDIR (1ULL << 6)
129 #define I40E_FLAG_VXLAN (1ULL << 7)
130 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
131 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
132 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
136 I40E_FLAG_HEADER_SPLIT_DISABLED | \
137 I40E_FLAG_HEADER_SPLIT_ENABLED | \
140 I40E_FLAG_RSS_AQ_CAPABLE | \
141 I40E_FLAG_VF_MAC_BY_PF)
143 #define I40E_RSS_OFFLOAD_ALL ( \
144 ETH_RSS_FRAG_IPV4 | \
145 ETH_RSS_NONFRAG_IPV4_TCP | \
146 ETH_RSS_NONFRAG_IPV4_UDP | \
147 ETH_RSS_NONFRAG_IPV4_SCTP | \
148 ETH_RSS_NONFRAG_IPV4_OTHER | \
149 ETH_RSS_FRAG_IPV6 | \
150 ETH_RSS_NONFRAG_IPV6_TCP | \
151 ETH_RSS_NONFRAG_IPV6_UDP | \
152 ETH_RSS_NONFRAG_IPV6_SCTP | \
153 ETH_RSS_NONFRAG_IPV6_OTHER | \
156 /* All bits of RSS hash enable for X722*/
157 #define I40E_RSS_HENA_ALL_X722 ( \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
166 /* All bits of RSS hash enable */
167 #define I40E_RSS_HENA_ALL ( \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
172 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
176 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
177 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
178 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
179 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
180 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
181 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
183 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
184 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
186 /* Default queue interrupt throttling time in microseconds */
187 #define I40E_ITR_INDEX_DEFAULT 0
188 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
189 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
191 /* Special FW support this floating VEB feature */
192 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
193 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
195 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
196 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
197 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
198 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
200 #define I40E_INSET_NONE 0x00000000000000000ULL
203 #define I40E_INSET_DMAC 0x0000000000000001ULL
204 #define I40E_INSET_SMAC 0x0000000000000002ULL
205 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
206 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
207 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
210 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
211 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
212 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
213 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
214 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
215 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
216 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
218 /* bit 16 ~ bit 31 */
219 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
220 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
221 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
222 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
223 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
224 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
225 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
226 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
228 /* bit 32 ~ bit 47, tunnel fields */
229 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
230 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
231 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
232 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
233 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
234 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
236 /* bit 48 ~ bit 55 */
237 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
239 /* bit 56 ~ bit 63, Flex Payload */
240 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
247 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
248 #define I40E_INSET_FLEX_PAYLOAD \
249 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
250 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
251 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
252 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
257 * MAC filter structure
259 struct i40e_mac_filter_info {
260 enum rte_mac_filter_type filter_type;
261 struct ether_addr mac_addr;
264 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
266 /* MAC filter list structure */
267 struct i40e_mac_filter {
268 TAILQ_ENTRY(i40e_mac_filter) next;
269 struct i40e_mac_filter_info mac_info;
272 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
276 /* VSI list structure */
277 struct i40e_vsi_list {
278 TAILQ_ENTRY(i40e_vsi_list) list;
279 struct i40e_vsi *vsi;
282 struct i40e_rx_queue;
283 struct i40e_tx_queue;
285 /* Bandwidth limit information */
286 struct i40e_bw_info {
287 uint16_t bw_limit; /* BW Limit (0 = disabled) */
288 uint8_t bw_max; /* Max BW limit if enabled */
290 /* Relative credits within same TC with respect to other VSIs or Comps */
291 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
292 /* Bandwidth limit per TC */
293 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
294 /* Max bandwidth limit per TC */
295 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
298 /* Structure that defines a VEB */
300 struct i40e_vsi_list_head head;
301 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
302 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
303 uint16_t seid; /* The seid of VEB itself */
304 uint16_t uplink_seid; /* The uplink seid of this VEB */
306 struct i40e_eth_stats stats;
307 uint8_t enabled_tc; /* The traffic class enabled */
308 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
309 struct i40e_bw_info bw_info; /* VEB bandwidth information */
312 /* i40e MACVLAN filter structure */
313 struct i40e_macvlan_filter {
314 struct ether_addr macaddr;
315 enum rte_mac_filter_type filter_type;
320 * Structure that defines a VSI, associated with a adapter.
323 struct i40e_adapter *adapter; /* Backreference to associated adapter */
324 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
326 struct i40e_eth_stats eth_stats_offset;
327 struct i40e_eth_stats eth_stats;
329 * When drivers loaded, only a default main VSI exists. In case new VSI
330 * needs to add, HW needs to know the layout that VSIs are organized.
331 * Besides that, VSI isan element and can't switch packets, which needs
332 * to add new component VEB to perform switching. So, a new VSI needs
333 * to specify the the uplink VSI (Parent VSI) before created. The
334 * uplink VSI will check whether it had a VEB to switch packets. If no,
335 * it will try to create one. Then, uplink VSI will move the new VSI
336 * into its' sib_vsi_list to manage all the downlink VSI.
337 * sib_vsi_list: the VSI list that shared the same uplink VSI.
338 * parent_vsi : the uplink VSI. It's NULL for main VSI.
339 * veb : the VEB associates with the VSI.
341 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
342 struct i40e_vsi *parent_vsi;
343 struct i40e_veb *veb; /* Associated veb, could be null */
344 struct i40e_veb *floating_veb; /* Associated floating veb */
346 enum i40e_vsi_type type; /* VSI types */
347 uint16_t vlan_num; /* Total VLAN number */
348 uint16_t mac_num; /* Total mac number */
349 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
350 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
351 /* specific VSI-defined parameters, SRIOV stored the vf_id */
353 uint16_t seid; /* The seid of VSI itself */
354 uint16_t uplink_seid; /* The uplink seid of this VSI */
355 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
356 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
357 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
358 uint16_t base_queue; /* The first queue index of this VSI */
360 * The offset to visit VSI related register, assigned by HW when
364 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
365 uint16_t nb_msix; /* The max number of msix vector */
366 uint8_t enabled_tc; /* The traffic class enabled */
367 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
368 uint8_t vlan_filter_on; /* The VLAN filter enabled */
369 struct i40e_bw_info bw_info; /* VSI bandwidth information */
373 LIST_ENTRY(pool_entry) next;
378 LIST_HEAD(res_list, pool_entry);
380 struct i40e_res_pool_info {
381 uint32_t base; /* Resource start index */
382 uint32_t num_alloc; /* Allocated resource number */
383 uint32_t num_free; /* Total available resource number */
384 struct res_list alloc_list; /* Allocated resource list */
385 struct res_list free_list; /* Available resource list */
389 I40E_VF_INACTIVE = 0,
396 * Structure to store private data for PF host.
400 struct i40e_vsi *vsi;
401 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
402 uint16_t vf_idx; /* VF index in pf->vfs */
403 uint16_t lan_nb_qps; /* Actual queues allocated */
404 uint16_t reset_cnt; /* Total vf reset times */
405 struct ether_addr mac_addr; /* Default MAC address */
409 * Structure to store private data for flow control.
411 struct i40e_fc_conf {
412 uint16_t pause_time; /* Flow control pause timer */
413 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
414 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
415 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
416 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
420 * Structure to store private data for VMDQ instance
422 struct i40e_vmdq_info {
424 struct i40e_vsi *vsi;
428 * Structure to store flex pit for flow diretor.
430 struct i40e_fdir_flex_pit {
431 uint8_t src_offset; /* offset in words from the beginning of payload */
432 uint8_t size; /* size in words */
433 uint8_t dst_offset; /* offset in words of flexible payload */
436 struct i40e_fdir_flex_mask {
437 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
441 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
444 #define I40E_FILTER_PCTYPE_MAX 64
445 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
447 struct i40e_fdir_filter {
448 TAILQ_ENTRY(i40e_fdir_filter) rules;
449 struct rte_eth_fdir_filter fdir;
452 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
454 * A structure used to define fields of a FDIR related info.
456 struct i40e_fdir_info {
457 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
458 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
459 struct i40e_tx_queue *txq;
460 struct i40e_rx_queue *rxq;
461 void *prg_pkt; /* memory for fdir program packet */
462 uint64_t dma_addr; /* physic address of packet memory*/
463 /* input set bits for each pctype */
464 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
466 * the rule how bytes stream is extracted as flexible payload
467 * for each payload layer, the setting can up to three elements
469 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
470 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
472 struct i40e_fdir_filter_list fdir_list;
473 struct i40e_fdir_filter **hash_map;
474 struct rte_hash *hash_table;
477 /* Ethertype filter number HW supports */
478 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
480 /* Ethertype filter struct */
481 struct i40e_ethertype_filter_input {
482 struct ether_addr mac_addr; /* Mac address to match */
483 uint16_t ether_type; /* Ether type to match */
486 struct i40e_ethertype_filter {
487 TAILQ_ENTRY(i40e_ethertype_filter) rules;
488 struct i40e_ethertype_filter_input input;
489 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
490 uint16_t queue; /* Queue assigned to when match */
493 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
495 struct i40e_ethertype_rule {
496 struct i40e_ethertype_filter_list ethertype_list;
497 struct i40e_ethertype_filter **hash_map;
498 struct rte_hash *hash_table;
501 /* Tunnel filter number HW supports */
502 #define I40E_MAX_TUNNEL_FILTER_NUM 400
504 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
505 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
506 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP 8
507 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE 9
508 #define I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ 0x10
509 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP 0x11
510 #define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE 0x12
511 #define I40E_AQC_ADD_L1_FILTER_TEID_MPLS 0x11
513 enum i40e_tunnel_iptype {
514 I40E_TUNNEL_IPTYPE_IPV4,
515 I40E_TUNNEL_IPTYPE_IPV6,
518 /* Tunnel filter struct */
519 struct i40e_tunnel_filter_input {
520 uint8_t outer_mac[6]; /* Outer mac address to match */
521 uint8_t inner_mac[6]; /* Inner mac address to match */
522 uint16_t inner_vlan; /* Inner vlan address to match */
523 enum i40e_tunnel_iptype ip_type;
524 uint16_t flags; /* Filter type flag */
525 uint32_t tenant_id; /* Tenant id to match */
526 uint16_t general_fields[32]; /* Big buffer */
529 struct i40e_tunnel_filter {
530 TAILQ_ENTRY(i40e_tunnel_filter) rules;
531 struct i40e_tunnel_filter_input input;
532 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
533 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
534 uint16_t queue; /* Queue assigned to when match */
537 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
539 struct i40e_tunnel_rule {
540 struct i40e_tunnel_filter_list tunnel_list;
541 struct i40e_tunnel_filter **hash_map;
542 struct rte_hash *hash_table;
548 enum i40e_tunnel_type {
549 I40E_TUNNEL_TYPE_NONE = 0,
550 I40E_TUNNEL_TYPE_VXLAN,
551 I40E_TUNNEL_TYPE_GENEVE,
552 I40E_TUNNEL_TYPE_TEREDO,
553 I40E_TUNNEL_TYPE_NVGRE,
554 I40E_TUNNEL_TYPE_IP_IN_GRE,
555 I40E_L2_TUNNEL_TYPE_E_TAG,
556 I40E_TUNNEL_TYPE_MPLSoUDP,
557 I40E_TUNNEL_TYPE_MPLSoGRE,
558 I40E_TUNNEL_TYPE_QINQ,
559 I40E_TUNNEL_TYPE_MAX,
563 * Tunneling Packet filter configuration.
565 struct i40e_tunnel_filter_conf {
566 struct ether_addr outer_mac; /**< Outer MAC address to match. */
567 struct ether_addr inner_mac; /**< Inner MAC address to match. */
568 uint16_t inner_vlan; /**< Inner VLAN to match. */
569 uint32_t outer_vlan; /**< Outer VLAN to match */
570 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
572 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
573 * is set in filter_type, or inner destination IP address to match
574 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
577 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
578 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
580 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
581 uint16_t filter_type;
582 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
583 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
584 uint16_t queue_id; /**< Queue assigned to if match. */
585 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
586 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
589 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
590 #define I40E_MAX_MIRROR_RULES 64
592 * Mirror rule structure
594 struct i40e_mirror_rule {
595 TAILQ_ENTRY(i40e_mirror_rule) rules;
597 uint16_t index; /* the sw index of mirror rule */
598 uint16_t id; /* the rule id assigned by firmware */
599 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
600 uint16_t num_entries;
601 /* the info stores depend on the rule type.
602 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
603 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
605 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
608 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
611 * Struct to store flow created.
614 TAILQ_ENTRY(rte_flow) node;
615 enum rte_filter_type filter_type;
619 TAILQ_HEAD(i40e_flow_list, rte_flow);
622 * Structure to store private data specific for PF instance.
625 struct i40e_adapter *adapter; /* The adapter this PF associate to */
626 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
627 uint16_t mac_seid; /* The seid of the MAC of this PF */
628 uint16_t main_vsi_seid; /* The seid of the main VSI */
629 uint16_t max_num_vsi;
630 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
631 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
633 struct i40e_hw_port_stats stats_offset;
634 struct i40e_hw_port_stats stats;
637 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
638 struct ether_addr dev_addr; /* PF device mac address */
639 uint64_t flags; /* PF feature flags */
640 /* All kinds of queue pair setting for different VSIs */
641 struct i40e_pf_vf *vfs;
643 /* Each of below queue pairs should be power of 2 since it's the
644 precondition after TC configuration applied */
645 uint16_t lan_nb_qp_max;
646 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
647 uint16_t lan_qp_offset;
648 uint16_t vmdq_nb_qp_max;
649 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
650 uint16_t vmdq_qp_offset;
651 uint16_t vf_nb_qp_max;
652 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
653 uint16_t vf_qp_offset;
654 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
655 uint16_t fdir_qp_offset;
657 uint16_t hash_lut_size; /* The size of hash lookup table */
658 /* input set bits for each pctype */
659 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
660 /* store VXLAN UDP ports */
661 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
662 uint16_t vxlan_bitmap; /* Vxlan bit mask */
664 /* VMDQ related info */
665 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
666 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
667 struct i40e_vmdq_info *vmdq;
669 struct i40e_fdir_info fdir; /* flow director info */
670 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
671 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
672 struct i40e_fc_conf fc_conf; /* Flow control conf */
673 struct i40e_mirror_rule_list mirror_list;
674 uint16_t nb_mirror_rule; /* The number of mirror rules */
675 bool floating_veb; /* The flag to use the floating VEB */
676 /* The floating enable flag for the specific VF */
677 bool floating_veb_list[I40E_MAX_VF];
678 struct i40e_flow_list flow_list;
679 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
680 bool qinq_replace_flag; /* QINQ filter replace is done */
684 PFMSG_LINK_CHANGE = 0x1,
685 PFMSG_RESET_IMPENDING = 0x2,
686 PFMSG_DRIVER_CLOSE = 0x4,
689 struct i40e_vsi_vlan_pvid_info {
690 uint16_t on; /* Enable or disable pvid */
692 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
694 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
695 * while 'untagged' will reject untagged packets.
703 struct i40e_vf_rx_queues {
704 uint64_t rx_dma_addr;
705 uint32_t rx_ring_len;
709 struct i40e_vf_tx_queues {
710 uint64_t tx_dma_addr;
711 uint32_t tx_ring_len;
715 * Structure to store private data specific for VF instance.
718 struct i40e_adapter *adapter; /* The adapter this VF associate to */
719 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
720 uint16_t num_queue_pairs;
721 uint16_t max_pkt_len; /* Maximum packet length */
722 bool promisc_unicast_enabled;
723 bool promisc_multicast_enabled;
725 uint32_t version_major; /* Major version number */
726 uint32_t version_minor; /* Minor version number */
727 uint16_t promisc_flags; /* Promiscuous setting */
728 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
733 enum i40e_aq_link_speed link_speed;
735 volatile uint32_t pend_cmd; /* pending command not finished yet */
736 int32_t cmd_retval; /* return value of the cmd response from PF */
737 u16 pend_msg; /* flags indicates events from pf not handled yet */
738 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
741 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
742 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
748 * Structure to store private data for each PF/VF instance.
750 struct i40e_adapter {
751 /* Common for both PF and VF */
753 struct rte_eth_dev *eth_dev;
755 /* Specific for PF or VF */
762 bool rx_bulk_alloc_allowed;
764 bool tx_simple_allowed;
768 struct rte_timecounter systime_tc;
769 struct rte_timecounter rx_tstamp_tc;
770 struct rte_timecounter tx_tstamp_tc;
773 extern const struct rte_flow_ops i40e_flow_ops;
775 union i40e_filter_t {
776 struct rte_eth_ethertype_filter ethertype_filter;
777 struct rte_eth_fdir_filter fdir_filter;
778 struct rte_eth_tunnel_filter_conf tunnel_filter;
779 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
782 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
783 const struct rte_flow_attr *attr,
784 const struct rte_flow_item pattern[],
785 const struct rte_flow_action actions[],
786 struct rte_flow_error *error,
787 union i40e_filter_t *filter);
788 struct i40e_valid_pattern {
789 enum rte_flow_item_type *items;
790 parse_filter_t parse_filter;
793 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
794 int i40e_vsi_release(struct i40e_vsi *vsi);
795 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
796 enum i40e_vsi_type type,
797 struct i40e_vsi *uplink_vsi,
798 uint16_t user_param);
799 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
800 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
801 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
802 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
803 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
804 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
805 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
806 void i40e_pf_disable_irq0(struct i40e_hw *hw);
807 void i40e_pf_enable_irq0(struct i40e_hw *hw);
808 int i40e_dev_link_update(struct rte_eth_dev *dev,
809 __rte_unused int wait_to_complete);
810 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
811 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
812 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
813 struct i40e_vsi_vlan_pvid_info *info);
814 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
815 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
816 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
817 uint64_t i40e_parse_hena(uint64_t flags);
818 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
819 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
820 int i40e_fdir_setup(struct i40e_pf *pf);
821 const struct rte_memzone *i40e_memzone_reserve(const char *name,
824 int i40e_fdir_configure(struct rte_eth_dev *dev);
825 void i40e_fdir_teardown(struct i40e_pf *pf);
826 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
827 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
828 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
829 enum rte_filter_op filter_op,
831 int i40e_select_filter_input_set(struct i40e_hw *hw,
832 struct rte_eth_input_set_conf *conf,
833 enum rte_filter_type filter);
834 void i40e_fdir_filter_restore(struct i40e_pf *pf);
835 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
836 struct rte_eth_input_set_conf *conf);
837 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
838 struct rte_eth_input_set_conf *conf);
839 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
840 uint32_t retval, uint8_t *msg,
842 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
843 struct rte_eth_rxq_info *qinfo);
844 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
845 struct rte_eth_txq_info *qinfo);
846 struct i40e_ethertype_filter *
847 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
848 const struct i40e_ethertype_filter_input *input);
849 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
850 struct i40e_ethertype_filter_input *input);
851 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
852 struct rte_eth_fdir_input *input);
853 struct i40e_tunnel_filter *
854 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
855 const struct i40e_tunnel_filter_input *input);
856 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
857 struct i40e_tunnel_filter_input *input);
858 uint64_t i40e_get_default_input_set(uint16_t pctype);
859 int i40e_ethertype_filter_set(struct i40e_pf *pf,
860 struct rte_eth_ethertype_filter *filter,
862 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
863 const struct rte_eth_fdir_filter *filter,
865 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
866 struct rte_eth_tunnel_filter_conf *tunnel_filter,
868 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
869 struct i40e_tunnel_filter_conf *tunnel_filter,
871 int i40e_fdir_flush(struct rte_eth_dev *dev);
872 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
873 struct i40e_macvlan_filter *mv_f,
874 int num, struct ether_addr *addr);
875 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
876 struct i40e_macvlan_filter *filter,
878 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
879 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
880 struct i40e_macvlan_filter *filter,
882 bool is_i40e_supported(struct rte_eth_dev *dev);
884 #define I40E_DEV_TO_PCI(eth_dev) \
885 RTE_DEV_TO_PCI((eth_dev)->device)
887 /* I40E_DEV_PRIVATE_TO */
888 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
889 (&((struct i40e_adapter *)adapter)->pf)
890 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
891 (&((struct i40e_adapter *)adapter)->hw)
892 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
893 ((struct i40e_adapter *)adapter)
895 /* I40EVF_DEV_PRIVATE_TO */
896 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
897 (&((struct i40e_adapter *)adapter)->vf)
899 static inline struct i40e_vsi *
900 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
907 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
908 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
909 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
916 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
917 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
920 #define I40E_VSI_TO_HW(vsi) \
921 (&(((struct i40e_vsi *)vsi)->adapter->hw))
922 #define I40E_VSI_TO_PF(vsi) \
923 (&(((struct i40e_vsi *)vsi)->adapter->pf))
924 #define I40E_VSI_TO_VF(vsi) \
925 (&(((struct i40e_vsi *)vsi)->adapter->vf))
926 #define I40E_VSI_TO_DEV_DATA(vsi) \
927 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
928 #define I40E_VSI_TO_ETH_DEV(vsi) \
929 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
932 #define I40E_PF_TO_HW(pf) \
933 (&(((struct i40e_pf *)pf)->adapter->hw))
934 #define I40E_PF_TO_ADAPTER(pf) \
935 ((struct i40e_adapter *)pf->adapter)
938 #define I40E_VF_TO_HW(vf) \
939 (&(((struct i40e_vf *)vf)->adapter->hw))
942 i40e_init_adminq_parameter(struct i40e_hw *hw)
944 hw->aq.num_arq_entries = I40E_AQ_LEN;
945 hw->aq.num_asq_entries = I40E_AQ_LEN;
946 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
947 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
951 i40e_align_floor(int n)
955 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
958 static inline uint16_t
959 i40e_calc_itr_interval(int16_t interval)
961 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
962 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
964 /* Convert to hardware count, as writing each 1 represents 2 us */
968 #define I40E_VALID_FLOW(flow_type) \
969 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
970 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
971 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
972 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
973 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
974 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
975 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
976 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
977 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
978 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
979 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
981 #define I40E_VALID_PCTYPE_X722(pctype) \
982 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
983 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
984 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
985 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
986 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
987 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
988 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
989 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
990 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
991 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
992 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
993 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
994 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
995 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
996 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
997 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
998 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1000 #define I40E_VALID_PCTYPE(pctype) \
1001 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1002 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1003 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1004 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1005 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1006 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1007 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1008 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1009 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1010 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1011 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1013 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1014 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1015 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1016 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1017 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1018 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1019 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1021 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1022 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1023 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1024 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1025 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1027 #endif /* _I40E_ETHDEV_H_ */