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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_VLAN_TAG_SIZE 4
41 #define I40E_AQ_LEN 32
42 #define I40E_AQ_BUF_SZ 4096
43 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
44 #define I40E_MAX_Q_PER_TC 64
45 #define I40E_NUM_DESC_DEFAULT 512
46 #define I40E_NUM_DESC_ALIGN 32
47 #define I40E_BUF_SIZE_MIN 1024
48 #define I40E_FRAME_SIZE_MAX 9728
49 #define I40E_QUEUE_BASE_ADDR_UNIT 128
50 /* number of VSIs and queue default setting */
51 #define I40E_MAX_QP_NUM_PER_VF 16
52 #define I40E_DEFAULT_QP_NUM_FDIR 1
53 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
54 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
56 * vlan_id is a 12 bit number.
57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
59 * The higher 7 bit val specifies VFTA array index.
61 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
62 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
64 /* Default TC traffic in case DCB is not enabled */
65 #define I40E_DEFAULT_TCMAP 0x1
66 #define I40E_FDIR_QUEUE_ID 0
68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
69 #define I40E_VMDQ_POOL_BASE 1
71 #define I40E_DEFAULT_RX_FREE_THRESH 32
72 #define I40E_DEFAULT_RX_PTHRESH 8
73 #define I40E_DEFAULT_RX_HTHRESH 8
74 #define I40E_DEFAULT_RX_WTHRESH 0
76 #define I40E_DEFAULT_TX_FREE_THRESH 32
77 #define I40E_DEFAULT_TX_PTHRESH 32
78 #define I40E_DEFAULT_TX_HTHRESH 0
79 #define I40E_DEFAULT_TX_WTHRESH 0
80 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
82 /* Bit shift and mask */
83 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
84 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
85 #define I40E_8_BIT_WIDTH CHAR_BIT
86 #define I40E_8_BIT_MASK UINT8_MAX
87 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
88 #define I40E_16_BIT_MASK UINT16_MAX
89 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
90 #define I40E_32_BIT_MASK UINT32_MAX
91 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
92 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
94 /* Linux PF host with virtchnl version 1.1 */
95 #define PF_IS_V11(vf) \
96 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
97 ((vf)->version_minor == 1))
99 /* index flex payload per layer */
100 enum i40e_flxpld_layer_idx {
101 I40E_FLXPLD_L2_IDX = 0,
102 I40E_FLXPLD_L3_IDX = 1,
103 I40E_FLXPLD_L4_IDX = 2,
104 I40E_MAX_FLXPLD_LAYER = 3,
106 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
107 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
108 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
109 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
112 #define I40E_FLAG_RSS (1ULL << 0)
113 #define I40E_FLAG_DCB (1ULL << 1)
114 #define I40E_FLAG_VMDQ (1ULL << 2)
115 #define I40E_FLAG_SRIOV (1ULL << 3)
116 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
117 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
118 #define I40E_FLAG_FDIR (1ULL << 6)
119 #define I40E_FLAG_VXLAN (1ULL << 7)
120 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
124 I40E_FLAG_HEADER_SPLIT_DISABLED | \
125 I40E_FLAG_HEADER_SPLIT_ENABLED | \
129 #define I40E_RSS_OFFLOAD_ALL ( \
130 ETH_RSS_FRAG_IPV4 | \
131 ETH_RSS_NONFRAG_IPV4_TCP | \
132 ETH_RSS_NONFRAG_IPV4_UDP | \
133 ETH_RSS_NONFRAG_IPV4_SCTP | \
134 ETH_RSS_NONFRAG_IPV4_OTHER | \
135 ETH_RSS_FRAG_IPV6 | \
136 ETH_RSS_NONFRAG_IPV6_TCP | \
137 ETH_RSS_NONFRAG_IPV6_UDP | \
138 ETH_RSS_NONFRAG_IPV6_SCTP | \
139 ETH_RSS_NONFRAG_IPV6_OTHER | \
142 /* All bits of RSS hash enable */
143 #define I40E_RSS_HENA_ALL ( \
144 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
148 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
150 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
153 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
154 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
155 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
156 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
157 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
162 * MAC filter structure
164 struct i40e_mac_filter_info {
165 enum rte_mac_filter_type filter_type;
166 struct ether_addr mac_addr;
169 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
171 /* MAC filter list structure */
172 struct i40e_mac_filter {
173 TAILQ_ENTRY(i40e_mac_filter) next;
174 struct i40e_mac_filter_info mac_info;
177 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
181 /* VSI list structure */
182 struct i40e_vsi_list {
183 TAILQ_ENTRY(i40e_vsi_list) list;
184 struct i40e_vsi *vsi;
187 struct i40e_rx_queue;
188 struct i40e_tx_queue;
190 /* Structure that defines a VEB */
192 struct i40e_vsi_list_head head;
193 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
194 uint16_t seid; /* The seid of VEB itself */
195 uint16_t uplink_seid; /* The uplink seid of this VEB */
197 struct i40e_eth_stats stats;
200 /* i40e MACVLAN filter structure */
201 struct i40e_macvlan_filter {
202 struct ether_addr macaddr;
203 enum rte_mac_filter_type filter_type;
208 * Structure that defines a VSI, associated with a adapter.
211 struct i40e_adapter *adapter; /* Backreference to associated adapter */
212 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
214 struct i40e_eth_stats eth_stats_offset;
215 struct i40e_eth_stats eth_stats;
217 * When drivers loaded, only a default main VSI exists. In case new VSI
218 * needs to add, HW needs to know the layout that VSIs are organized.
219 * Besides that, VSI isan element and can't switch packets, which needs
220 * to add new component VEB to perform switching. So, a new VSI needs
221 * to specify the the uplink VSI (Parent VSI) before created. The
222 * uplink VSI will check whether it had a VEB to switch packets. If no,
223 * it will try to create one. Then, uplink VSI will move the new VSI
224 * into its' sib_vsi_list to manage all the downlink VSI.
225 * sib_vsi_list: the VSI list that shared the same uplink VSI.
226 * parent_vsi : the uplink VSI. It's NULL for main VSI.
227 * veb : the VEB associates with the VSI.
229 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
230 struct i40e_vsi *parent_vsi;
231 struct i40e_veb *veb; /* Associated veb, could be null */
233 enum i40e_vsi_type type; /* VSI types */
234 uint16_t vlan_num; /* Total VLAN number */
235 uint16_t mac_num; /* Total mac number */
236 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
237 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
238 /* specific VSI-defined parameters, SRIOV stored the vf_id */
240 uint16_t seid; /* The seid of VSI itself */
241 uint16_t uplink_seid; /* The uplink seid of this VSI */
242 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
243 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
244 uint16_t base_queue; /* The first queue index of this VSI */
246 * The offset to visit VSI related register, assigned by HW when
250 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
251 uint8_t enabled_tc; /* The traffic class enabled */
255 LIST_ENTRY(pool_entry) next;
260 LIST_HEAD(res_list, pool_entry);
262 struct i40e_res_pool_info {
263 uint32_t base; /* Resource start index */
264 uint32_t num_alloc; /* Allocated resource number */
265 uint32_t num_free; /* Total available resource number */
266 struct res_list alloc_list; /* Allocated resource list */
267 struct res_list free_list; /* Available resource list */
271 I40E_VF_INACTIVE = 0,
278 * Structure to store private data for PF host.
282 struct i40e_vsi *vsi;
283 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
284 uint16_t vf_idx; /* VF index in pf->vfs */
285 uint16_t lan_nb_qps; /* Actual queues allocated */
286 uint16_t reset_cnt; /* Total vf reset times */
290 * Structure to store private data for VMDQ instance
292 struct i40e_vmdq_info {
294 struct i40e_vsi *vsi;
298 * Structure to store flex pit for flow diretor.
300 struct i40e_fdir_flex_pit {
301 uint8_t src_offset; /* offset in words from the beginning of payload */
302 uint8_t size; /* size in words */
303 uint8_t dst_offset; /* offset in words of flexible payload */
306 struct i40e_fdir_flex_mask {
307 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
311 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
314 #define I40E_FILTER_PCTYPE_MAX 64
316 * A structure used to define fields of a FDIR related info.
318 struct i40e_fdir_info {
319 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
320 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
321 struct i40e_tx_queue *txq;
322 struct i40e_rx_queue *rxq;
323 void *prg_pkt; /* memory for fdir program packet */
324 uint64_t dma_addr; /* physic address of packet memory*/
326 * the rule how bytes stream is extracted as flexible payload
327 * for each payload layer, the setting can up to three elements
329 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
330 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
333 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
334 #define I40E_MAX_MIRROR_RULES 64
336 * Mirror rule structure
338 struct i40e_mirror_rule {
339 TAILQ_ENTRY(i40e_mirror_rule) rules;
341 uint16_t index; /* the sw index of mirror rule */
342 uint16_t id; /* the rule id assigned by firmware */
343 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
344 uint16_t num_entries;
345 /* the info stores depend on the rule type.
346 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
347 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
349 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
352 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
355 * Structure to store private data specific for PF instance.
358 struct i40e_adapter *adapter; /* The adapter this PF associate to */
359 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
360 uint16_t mac_seid; /* The seid of the MAC of this PF */
361 uint16_t main_vsi_seid; /* The seid of the main VSI */
362 uint16_t max_num_vsi;
363 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
364 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
366 struct i40e_hw_port_stats stats_offset;
367 struct i40e_hw_port_stats stats;
370 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
371 struct ether_addr dev_addr; /* PF device mac address */
372 uint64_t flags; /* PF featuer flags */
373 /* All kinds of queue pair setting for different VSIs */
374 struct i40e_pf_vf *vfs;
376 /* Each of below queue pairs should be power of 2 since it's the
377 precondition after TC configuration applied */
378 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
379 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
380 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
381 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
382 uint16_t hash_lut_size; /* The size of hash lookup table */
383 /* store VXLAN UDP ports */
384 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
385 uint16_t vxlan_bitmap; /* Vxlan bit mask */
387 /* VMDQ related info */
388 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
389 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
390 struct i40e_vmdq_info *vmdq;
392 struct i40e_fdir_info fdir; /* flow director info */
393 struct i40e_mirror_rule_list mirror_list;
394 uint16_t nb_mirror_rule; /* The number of mirror rules */
398 PFMSG_LINK_CHANGE = 0x1,
399 PFMSG_RESET_IMPENDING = 0x2,
400 PFMSG_DRIVER_CLOSE = 0x4,
403 struct i40e_vsi_vlan_pvid_info {
404 uint16_t on; /* Enable or disable pvid */
406 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
408 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
409 * while 'untagged' will reject untagged packets.
417 struct i40e_vf_rx_queues {
418 uint64_t rx_dma_addr;
419 uint32_t rx_ring_len;
423 struct i40e_vf_tx_queues {
424 uint64_t tx_dma_addr;
425 uint32_t tx_ring_len;
429 * Structure to store private data specific for VF instance.
432 struct i40e_adapter *adapter; /* The adapter this VF associate to */
433 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
434 uint16_t num_queue_pairs;
435 uint16_t max_pkt_len; /* Maximum packet length */
436 bool promisc_unicast_enabled;
437 bool promisc_multicast_enabled;
439 uint32_t version_major; /* Major version number */
440 uint32_t version_minor; /* Minor version number */
441 uint16_t promisc_flags; /* Promiscuous setting */
442 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
448 volatile uint32_t pend_cmd; /* pending command not finished yet */
449 u16 pend_msg; /* flags indicates events from pf not handled yet */
452 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
453 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
458 * Structure to store private data for each PF/VF instance.
460 struct i40e_adapter {
461 /* Common for both PF and VF */
463 struct rte_eth_dev *eth_dev;
465 /* Specific for PF or VF */
472 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
473 int i40e_vsi_release(struct i40e_vsi *vsi);
474 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
475 enum i40e_vsi_type type,
476 struct i40e_vsi *uplink_vsi,
477 uint16_t user_param);
478 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
479 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
480 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
481 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
482 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
483 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
484 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
485 void i40e_pf_disable_irq0(struct i40e_hw *hw);
486 void i40e_pf_enable_irq0(struct i40e_hw *hw);
487 int i40e_dev_link_update(struct rte_eth_dev *dev,
488 __rte_unused int wait_to_complete);
489 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
490 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
491 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
492 struct i40e_vsi_vlan_pvid_info *info);
493 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
494 uint64_t i40e_config_hena(uint64_t flags);
495 uint64_t i40e_parse_hena(uint64_t flags);
496 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
497 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
498 int i40e_fdir_setup(struct i40e_pf *pf);
499 const struct rte_memzone *i40e_memzone_reserve(const char *name,
502 int i40e_fdir_configure(struct rte_eth_dev *dev);
503 void i40e_fdir_teardown(struct i40e_pf *pf);
504 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
505 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
506 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
507 enum rte_filter_op filter_op,
510 /* I40E_DEV_PRIVATE_TO */
511 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
512 (&((struct i40e_adapter *)adapter)->pf)
513 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
514 (&((struct i40e_adapter *)adapter)->hw)
515 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
516 ((struct i40e_adapter *)adapter)
518 /* I40EVF_DEV_PRIVATE_TO */
519 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
520 (&((struct i40e_adapter *)adapter)->vf)
522 static inline struct i40e_vsi *
523 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
530 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
531 if (hw->mac.type == I40E_MAC_VF) {
532 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
539 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
540 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
543 #define I40E_VSI_TO_HW(vsi) \
544 (&(((struct i40e_vsi *)vsi)->adapter->hw))
545 #define I40E_VSI_TO_PF(vsi) \
546 (&(((struct i40e_vsi *)vsi)->adapter->pf))
547 #define I40E_VSI_TO_DEV_DATA(vsi) \
548 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
549 #define I40E_VSI_TO_ETH_DEV(vsi) \
550 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
553 #define I40E_PF_TO_HW(pf) \
554 (&(((struct i40e_pf *)pf)->adapter->hw))
555 #define I40E_PF_TO_ADAPTER(pf) \
556 ((struct i40e_adapter *)pf->adapter)
559 #define I40E_VF_TO_HW(vf) \
560 (&(((struct i40e_vf *)vf)->adapter->hw))
563 i40e_init_adminq_parameter(struct i40e_hw *hw)
565 hw->aq.num_arq_entries = I40E_AQ_LEN;
566 hw->aq.num_asq_entries = I40E_AQ_LEN;
567 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
568 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
572 i40e_align_floor(int n)
576 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
579 #define I40E_VALID_FLOW(flow_type) \
580 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
581 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
582 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
583 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
584 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
585 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
586 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
587 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
588 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
589 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
590 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
592 #define I40E_VALID_PCTYPE(pctype) \
593 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
594 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
595 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
596 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
597 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
598 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
599 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
600 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
601 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
602 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
603 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
605 #endif /* _I40E_ETHDEV_H_ */