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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_VLAN_TAG_SIZE 4
41 #define I40E_AQ_LEN 32
42 #define I40E_AQ_BUF_SZ 4096
43 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
44 #define I40E_MAX_Q_PER_TC 64
45 #define I40E_NUM_DESC_DEFAULT 512
46 #define I40E_NUM_DESC_ALIGN 32
47 #define I40E_BUF_SIZE_MIN 1024
48 #define I40E_FRAME_SIZE_MAX 9728
49 #define I40E_QUEUE_BASE_ADDR_UNIT 128
50 /* number of VSIs and queue default setting */
51 #define I40E_MAX_QP_NUM_PER_VF 16
52 #define I40E_DEFAULT_QP_NUM_FDIR 1
53 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
54 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
56 * vlan_id is a 12 bit number.
57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
59 * The higher 7 bit val specifies VFTA array index.
61 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
62 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
64 /* Default TC traffic in case DCB is not enabled */
65 #define I40E_DEFAULT_TCMAP 0x1
66 #define I40E_FDIR_QUEUE_ID 0
68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
69 #define I40E_VMDQ_POOL_BASE 1
71 #define I40E_DEFAULT_RX_FREE_THRESH 32
72 #define I40E_DEFAULT_RX_PTHRESH 8
73 #define I40E_DEFAULT_RX_HTHRESH 8
74 #define I40E_DEFAULT_RX_WTHRESH 0
76 #define I40E_DEFAULT_TX_FREE_THRESH 32
77 #define I40E_DEFAULT_TX_PTHRESH 32
78 #define I40E_DEFAULT_TX_HTHRESH 0
79 #define I40E_DEFAULT_TX_WTHRESH 0
80 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
82 /* Bit shift and mask */
83 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
84 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
85 #define I40E_8_BIT_WIDTH CHAR_BIT
86 #define I40E_8_BIT_MASK UINT8_MAX
87 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
88 #define I40E_16_BIT_MASK UINT16_MAX
89 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
90 #define I40E_32_BIT_MASK UINT32_MAX
91 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
92 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
94 /* Linux PF host with virtchnl version 1.1 */
95 #define PF_IS_V11(vf) \
96 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
97 ((vf)->version_minor == 1))
99 /* index flex payload per layer */
100 enum i40e_flxpld_layer_idx {
101 I40E_FLXPLD_L2_IDX = 0,
102 I40E_FLXPLD_L3_IDX = 1,
103 I40E_FLXPLD_L4_IDX = 2,
104 I40E_MAX_FLXPLD_LAYER = 3,
106 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
107 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
108 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
109 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
112 #define I40E_FLAG_RSS (1ULL << 0)
113 #define I40E_FLAG_DCB (1ULL << 1)
114 #define I40E_FLAG_VMDQ (1ULL << 2)
115 #define I40E_FLAG_SRIOV (1ULL << 3)
116 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
117 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
118 #define I40E_FLAG_FDIR (1ULL << 6)
119 #define I40E_FLAG_VXLAN (1ULL << 7)
120 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
121 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
125 I40E_FLAG_HEADER_SPLIT_DISABLED | \
126 I40E_FLAG_HEADER_SPLIT_ENABLED | \
129 I40E_FLAG_RSS_AQ_CAPABLE)
131 #define I40E_RSS_OFFLOAD_ALL ( \
132 ETH_RSS_FRAG_IPV4 | \
133 ETH_RSS_NONFRAG_IPV4_TCP | \
134 ETH_RSS_NONFRAG_IPV4_UDP | \
135 ETH_RSS_NONFRAG_IPV4_SCTP | \
136 ETH_RSS_NONFRAG_IPV4_OTHER | \
137 ETH_RSS_FRAG_IPV6 | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP | \
140 ETH_RSS_NONFRAG_IPV6_SCTP | \
141 ETH_RSS_NONFRAG_IPV6_OTHER | \
144 /* All bits of RSS hash enable */
145 #define I40E_RSS_HENA_ALL ( \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
150 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
151 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
155 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
156 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
157 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
158 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
159 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
164 * MAC filter structure
166 struct i40e_mac_filter_info {
167 enum rte_mac_filter_type filter_type;
168 struct ether_addr mac_addr;
171 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
173 /* MAC filter list structure */
174 struct i40e_mac_filter {
175 TAILQ_ENTRY(i40e_mac_filter) next;
176 struct i40e_mac_filter_info mac_info;
179 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
183 /* VSI list structure */
184 struct i40e_vsi_list {
185 TAILQ_ENTRY(i40e_vsi_list) list;
186 struct i40e_vsi *vsi;
189 struct i40e_rx_queue;
190 struct i40e_tx_queue;
192 /* Structure that defines a VEB */
194 struct i40e_vsi_list_head head;
195 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
196 uint16_t seid; /* The seid of VEB itself */
197 uint16_t uplink_seid; /* The uplink seid of this VEB */
199 struct i40e_eth_stats stats;
202 /* i40e MACVLAN filter structure */
203 struct i40e_macvlan_filter {
204 struct ether_addr macaddr;
205 enum rte_mac_filter_type filter_type;
209 /* Bandwidth limit information */
210 struct i40e_bw_info {
211 uint16_t bw_limit; /* BW Limit (0 = disabled) */
212 uint8_t bw_max_quanta; /* Max Quanta when BW limit is enabled */
214 /* Relative TC credits across VSIs */
215 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
216 /* TC BW limit credits within VSI */
217 uint8_t bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
218 /* TC BW limit max quanta within VSI */
219 uint8_t bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
223 * Structure that defines a VSI, associated with a adapter.
226 struct i40e_adapter *adapter; /* Backreference to associated adapter */
227 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
229 struct i40e_eth_stats eth_stats_offset;
230 struct i40e_eth_stats eth_stats;
232 * When drivers loaded, only a default main VSI exists. In case new VSI
233 * needs to add, HW needs to know the layout that VSIs are organized.
234 * Besides that, VSI isan element and can't switch packets, which needs
235 * to add new component VEB to perform switching. So, a new VSI needs
236 * to specify the the uplink VSI (Parent VSI) before created. The
237 * uplink VSI will check whether it had a VEB to switch packets. If no,
238 * it will try to create one. Then, uplink VSI will move the new VSI
239 * into its' sib_vsi_list to manage all the downlink VSI.
240 * sib_vsi_list: the VSI list that shared the same uplink VSI.
241 * parent_vsi : the uplink VSI. It's NULL for main VSI.
242 * veb : the VEB associates with the VSI.
244 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
245 struct i40e_vsi *parent_vsi;
246 struct i40e_veb *veb; /* Associated veb, could be null */
248 enum i40e_vsi_type type; /* VSI types */
249 uint16_t vlan_num; /* Total VLAN number */
250 uint16_t mac_num; /* Total mac number */
251 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
252 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
253 /* specific VSI-defined parameters, SRIOV stored the vf_id */
255 uint16_t seid; /* The seid of VSI itself */
256 uint16_t uplink_seid; /* The uplink seid of this VSI */
257 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
258 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
259 uint16_t base_queue; /* The first queue index of this VSI */
261 * The offset to visit VSI related register, assigned by HW when
265 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
266 uint8_t enabled_tc; /* The traffic class enabled */
267 struct i40e_bw_info bw_info; /* VSI bandwidth information */
271 LIST_ENTRY(pool_entry) next;
276 LIST_HEAD(res_list, pool_entry);
278 struct i40e_res_pool_info {
279 uint32_t base; /* Resource start index */
280 uint32_t num_alloc; /* Allocated resource number */
281 uint32_t num_free; /* Total available resource number */
282 struct res_list alloc_list; /* Allocated resource list */
283 struct res_list free_list; /* Available resource list */
287 I40E_VF_INACTIVE = 0,
294 * Structure to store private data for PF host.
298 struct i40e_vsi *vsi;
299 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
300 uint16_t vf_idx; /* VF index in pf->vfs */
301 uint16_t lan_nb_qps; /* Actual queues allocated */
302 uint16_t reset_cnt; /* Total vf reset times */
306 * Structure to store private data for flow control.
308 struct i40e_fc_conf {
309 uint16_t pause_time; /* Flow control pause timer */
310 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
311 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
312 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
313 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
317 * Structure to store private data for VMDQ instance
319 struct i40e_vmdq_info {
321 struct i40e_vsi *vsi;
325 * Structure to store flex pit for flow diretor.
327 struct i40e_fdir_flex_pit {
328 uint8_t src_offset; /* offset in words from the beginning of payload */
329 uint8_t size; /* size in words */
330 uint8_t dst_offset; /* offset in words of flexible payload */
333 struct i40e_fdir_flex_mask {
334 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
338 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
341 #define I40E_FILTER_PCTYPE_MAX 64
343 * A structure used to define fields of a FDIR related info.
345 struct i40e_fdir_info {
346 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
347 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
348 struct i40e_tx_queue *txq;
349 struct i40e_rx_queue *rxq;
350 void *prg_pkt; /* memory for fdir program packet */
351 uint64_t dma_addr; /* physic address of packet memory*/
353 * the rule how bytes stream is extracted as flexible payload
354 * for each payload layer, the setting can up to three elements
356 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
357 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
360 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
361 #define I40E_MAX_MIRROR_RULES 64
363 * Mirror rule structure
365 struct i40e_mirror_rule {
366 TAILQ_ENTRY(i40e_mirror_rule) rules;
368 uint16_t index; /* the sw index of mirror rule */
369 uint16_t id; /* the rule id assigned by firmware */
370 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
371 uint16_t num_entries;
372 /* the info stores depend on the rule type.
373 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
374 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
376 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
379 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
382 * Structure to store private data specific for PF instance.
385 struct i40e_adapter *adapter; /* The adapter this PF associate to */
386 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
387 uint16_t mac_seid; /* The seid of the MAC of this PF */
388 uint16_t main_vsi_seid; /* The seid of the main VSI */
389 uint16_t max_num_vsi;
390 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
391 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
393 struct i40e_hw_port_stats stats_offset;
394 struct i40e_hw_port_stats stats;
397 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
398 struct ether_addr dev_addr; /* PF device mac address */
399 uint64_t flags; /* PF featuer flags */
400 /* All kinds of queue pair setting for different VSIs */
401 struct i40e_pf_vf *vfs;
403 /* Each of below queue pairs should be power of 2 since it's the
404 precondition after TC configuration applied */
405 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
406 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
407 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
408 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
409 uint16_t hash_lut_size; /* The size of hash lookup table */
410 /* store VXLAN UDP ports */
411 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
412 uint16_t vxlan_bitmap; /* Vxlan bit mask */
414 /* VMDQ related info */
415 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
416 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
417 struct i40e_vmdq_info *vmdq;
419 struct i40e_fdir_info fdir; /* flow director info */
420 struct i40e_fc_conf fc_conf; /* Flow control conf */
421 struct i40e_mirror_rule_list mirror_list;
422 uint16_t nb_mirror_rule; /* The number of mirror rules */
426 PFMSG_LINK_CHANGE = 0x1,
427 PFMSG_RESET_IMPENDING = 0x2,
428 PFMSG_DRIVER_CLOSE = 0x4,
431 struct i40e_vsi_vlan_pvid_info {
432 uint16_t on; /* Enable or disable pvid */
434 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
436 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
437 * while 'untagged' will reject untagged packets.
445 struct i40e_vf_rx_queues {
446 uint64_t rx_dma_addr;
447 uint32_t rx_ring_len;
451 struct i40e_vf_tx_queues {
452 uint64_t tx_dma_addr;
453 uint32_t tx_ring_len;
457 * Structure to store private data specific for VF instance.
460 struct i40e_adapter *adapter; /* The adapter this VF associate to */
461 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
462 uint16_t num_queue_pairs;
463 uint16_t max_pkt_len; /* Maximum packet length */
464 bool promisc_unicast_enabled;
465 bool promisc_multicast_enabled;
467 uint32_t version_major; /* Major version number */
468 uint32_t version_minor; /* Minor version number */
469 uint16_t promisc_flags; /* Promiscuous setting */
470 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
476 volatile uint32_t pend_cmd; /* pending command not finished yet */
477 u16 pend_msg; /* flags indicates events from pf not handled yet */
480 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
481 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
487 * Structure to store private data for each PF/VF instance.
489 struct i40e_adapter {
490 /* Common for both PF and VF */
492 struct rte_eth_dev *eth_dev;
494 /* Specific for PF or VF */
501 bool rx_bulk_alloc_allowed;
503 bool tx_simple_allowed;
507 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
508 int i40e_vsi_release(struct i40e_vsi *vsi);
509 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
510 enum i40e_vsi_type type,
511 struct i40e_vsi *uplink_vsi,
512 uint16_t user_param);
513 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
514 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
515 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
516 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
517 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
518 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
519 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
520 void i40e_pf_disable_irq0(struct i40e_hw *hw);
521 void i40e_pf_enable_irq0(struct i40e_hw *hw);
522 int i40e_dev_link_update(struct rte_eth_dev *dev,
523 __rte_unused int wait_to_complete);
524 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
525 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
526 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
527 struct i40e_vsi_vlan_pvid_info *info);
528 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
529 uint64_t i40e_config_hena(uint64_t flags);
530 uint64_t i40e_parse_hena(uint64_t flags);
531 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
532 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
533 int i40e_fdir_setup(struct i40e_pf *pf);
534 const struct rte_memzone *i40e_memzone_reserve(const char *name,
537 int i40e_fdir_configure(struct rte_eth_dev *dev);
538 void i40e_fdir_teardown(struct i40e_pf *pf);
539 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
540 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
541 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
542 enum rte_filter_op filter_op,
545 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
546 struct rte_eth_rxq_info *qinfo);
547 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
548 struct rte_eth_txq_info *qinfo);
550 /* I40E_DEV_PRIVATE_TO */
551 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
552 (&((struct i40e_adapter *)adapter)->pf)
553 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
554 (&((struct i40e_adapter *)adapter)->hw)
555 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
556 ((struct i40e_adapter *)adapter)
558 /* I40EVF_DEV_PRIVATE_TO */
559 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
560 (&((struct i40e_adapter *)adapter)->vf)
562 static inline struct i40e_vsi *
563 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
570 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
571 if (hw->mac.type == I40E_MAC_VF) {
572 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
575 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
579 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
580 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
583 #define I40E_VSI_TO_HW(vsi) \
584 (&(((struct i40e_vsi *)vsi)->adapter->hw))
585 #define I40E_VSI_TO_PF(vsi) \
586 (&(((struct i40e_vsi *)vsi)->adapter->pf))
587 #define I40E_VSI_TO_VF(vsi) \
588 (&(((struct i40e_vsi *)vsi)->adapter->vf))
589 #define I40E_VSI_TO_DEV_DATA(vsi) \
590 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
591 #define I40E_VSI_TO_ETH_DEV(vsi) \
592 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
595 #define I40E_PF_TO_HW(pf) \
596 (&(((struct i40e_pf *)pf)->adapter->hw))
597 #define I40E_PF_TO_ADAPTER(pf) \
598 ((struct i40e_adapter *)pf->adapter)
601 #define I40E_VF_TO_HW(vf) \
602 (&(((struct i40e_vf *)vf)->adapter->hw))
605 i40e_init_adminq_parameter(struct i40e_hw *hw)
607 hw->aq.num_arq_entries = I40E_AQ_LEN;
608 hw->aq.num_asq_entries = I40E_AQ_LEN;
609 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
610 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
614 i40e_align_floor(int n)
618 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
621 #define I40E_VALID_FLOW(flow_type) \
622 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
623 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
624 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
625 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
626 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
627 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
628 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
629 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
630 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
631 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
632 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
634 #define I40E_VALID_PCTYPE(pctype) \
635 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
636 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
637 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
638 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
639 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
640 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
641 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
642 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
643 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
644 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
645 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
647 #endif /* _I40E_ETHDEV_H_ */