1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
11 #include <rte_kvargs.h>
14 #include <rte_flow_driver.h>
15 #include <rte_tm_driver.h>
16 #include "rte_pmd_i40e.h"
18 #include "base/i40e_register.h"
20 #define I40E_VLAN_TAG_SIZE 4
22 #define I40E_AQ_LEN 32
23 #define I40E_AQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define I40E_MAX_Q_PER_TC 64
26 #define I40E_NUM_DESC_DEFAULT 512
27 #define I40E_NUM_DESC_ALIGN 32
28 #define I40E_BUF_SIZE_MIN 1024
29 #define I40E_FRAME_SIZE_MAX 9728
30 #define I40E_TSO_FRAME_SIZE_MAX 262144
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
90 struct rte_eth_dev *dev; \
91 ori_val = I40E_READ_REG((hw), (reg)); \
92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
95 if (ori_val != value) \
96 PMD_DRV_LOG(WARNING, \
97 "i40e device %s changed global " \
98 "register [0x%08x]. original: 0x%08x, " \
100 (dev->device->name), (reg), \
101 (ori_val), (value)); \
104 /* index flex payload per layer */
105 enum i40e_flxpld_layer_idx {
106 I40E_FLXPLD_L2_IDX = 0,
107 I40E_FLXPLD_L3_IDX = 1,
108 I40E_FLXPLD_L4_IDX = 2,
109 I40E_MAX_FLXPLD_LAYER = 3,
111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
118 #define I40E_FLAG_RSS (1ULL << 0)
119 #define I40E_FLAG_DCB (1ULL << 1)
120 #define I40E_FLAG_VMDQ (1ULL << 2)
121 #define I40E_FLAG_SRIOV (1ULL << 3)
122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
124 #define I40E_FLAG_FDIR (1ULL << 6)
125 #define I40E_FLAG_VXLAN (1ULL << 7)
126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
127 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
131 I40E_FLAG_HEADER_SPLIT_DISABLED | \
132 I40E_FLAG_HEADER_SPLIT_ENABLED | \
135 I40E_FLAG_RSS_AQ_CAPABLE)
137 #define I40E_RSS_OFFLOAD_ALL ( \
138 ETH_RSS_FRAG_IPV4 | \
139 ETH_RSS_NONFRAG_IPV4_TCP | \
140 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV4_SCTP | \
142 ETH_RSS_NONFRAG_IPV4_OTHER | \
143 ETH_RSS_FRAG_IPV6 | \
144 ETH_RSS_NONFRAG_IPV6_TCP | \
145 ETH_RSS_NONFRAG_IPV6_UDP | \
146 ETH_RSS_NONFRAG_IPV6_SCTP | \
147 ETH_RSS_NONFRAG_IPV6_OTHER | \
150 /* All bits of RSS hash enable for X722*/
151 #define I40E_RSS_HENA_ALL_X722 ( \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
160 /* All bits of RSS hash enable */
161 #define I40E_RSS_HENA_ALL ( \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
166 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
171 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
172 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
173 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
175 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
177 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
178 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
180 /* Default queue interrupt throttling time in microseconds */
181 #define I40E_ITR_INDEX_DEFAULT 0
182 #define I40E_ITR_INDEX_NONE 3
183 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
184 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
185 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 /* Special FW support this floating VEB feature */
187 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
188 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
190 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
191 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
192 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
193 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
195 #define I40E_RSS_TYPE_NONE 0ULL
196 #define I40E_RSS_TYPE_INVALID 1ULL
198 #define I40E_INSET_NONE 0x00000000000000000ULL
201 #define I40E_INSET_DMAC 0x0000000000000001ULL
202 #define I40E_INSET_SMAC 0x0000000000000002ULL
203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
216 /* bit 16 ~ bit 31 */
217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
226 /* bit 32 ~ bit 47, tunnel fields */
227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
234 /* bit 48 ~ bit 55 */
235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
237 /* bit 56 ~ bit 63, Flex Payload */
238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD \
247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
252 /* The max bandwidth of i40e is 40Gbps. */
253 #define I40E_QOS_BW_MAX 40000
254 /* The bandwidth should be the multiple of 50Mbps. */
255 #define I40E_QOS_BW_GRANULARITY 50
256 /* The min bandwidth weight is 1. */
257 #define I40E_QOS_BW_WEIGHT_MIN 1
258 /* The max bandwidth weight is 127. */
259 #define I40E_QOS_BW_WEIGHT_MAX 127
260 /* The max queue region index is 7. */
261 #define I40E_REGION_MAX_INDEX 7
263 #define I40E_MAX_PERCENT 100
264 #define I40E_DEFAULT_DCB_APP_NUM 1
265 #define I40E_DEFAULT_DCB_APP_PRIO 3
268 * Struct to store flow created.
271 TAILQ_ENTRY(rte_flow) node;
272 enum rte_filter_type filter_type;
277 * The overhead from MTU to max frame size.
278 * Considering QinQ packet, the VLAN tag needs to be counted twice.
280 #define I40E_ETH_OVERHEAD \
281 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
284 struct rte_pci_driver;
287 * MAC filter structure
289 struct i40e_mac_filter_info {
290 enum rte_mac_filter_type filter_type;
291 struct rte_ether_addr mac_addr;
294 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
296 /* MAC filter list structure */
297 struct i40e_mac_filter {
298 TAILQ_ENTRY(i40e_mac_filter) next;
299 struct i40e_mac_filter_info mac_info;
302 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
306 /* VSI list structure */
307 struct i40e_vsi_list {
308 TAILQ_ENTRY(i40e_vsi_list) list;
309 struct i40e_vsi *vsi;
312 struct i40e_rx_queue;
313 struct i40e_tx_queue;
315 /* Bandwidth limit information */
316 struct i40e_bw_info {
317 uint16_t bw_limit; /* BW Limit (0 = disabled) */
318 uint8_t bw_max; /* Max BW limit if enabled */
320 /* Relative credits within same TC with respect to other VSIs or Comps */
321 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
322 /* Bandwidth limit per TC */
323 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
324 /* Max bandwidth limit per TC */
325 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
328 /* Structure that defines a VEB */
330 struct i40e_vsi_list_head head;
331 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
332 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
333 uint16_t seid; /* The seid of VEB itself */
334 uint16_t uplink_seid; /* The uplink seid of this VEB */
336 struct i40e_eth_stats stats;
337 uint8_t enabled_tc; /* The traffic class enabled */
338 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
339 struct i40e_bw_info bw_info; /* VEB bandwidth information */
342 /* i40e MACVLAN filter structure */
343 struct i40e_macvlan_filter {
344 struct rte_ether_addr macaddr;
345 enum rte_mac_filter_type filter_type;
350 * Structure that defines a VSI, associated with a adapter.
353 struct i40e_adapter *adapter; /* Backreference to associated adapter */
354 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
356 struct i40e_eth_stats eth_stats_offset;
357 struct i40e_eth_stats eth_stats;
359 * When drivers loaded, only a default main VSI exists. In case new VSI
360 * needs to add, HW needs to know the layout that VSIs are organized.
361 * Besides that, VSI isan element and can't switch packets, which needs
362 * to add new component VEB to perform switching. So, a new VSI needs
363 * to specify the uplink VSI (Parent VSI) before created. The
364 * uplink VSI will check whether it had a VEB to switch packets. If no,
365 * it will try to create one. Then, uplink VSI will move the new VSI
366 * into its' sib_vsi_list to manage all the downlink VSI.
367 * sib_vsi_list: the VSI list that shared the same uplink VSI.
368 * parent_vsi : the uplink VSI. It's NULL for main VSI.
369 * veb : the VEB associates with the VSI.
371 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
372 struct i40e_vsi *parent_vsi;
373 struct i40e_veb *veb; /* Associated veb, could be null */
374 struct i40e_veb *floating_veb; /* Associated floating veb */
376 enum i40e_vsi_type type; /* VSI types */
377 uint16_t vlan_num; /* Total VLAN number */
378 uint16_t mac_num; /* Total mac number */
379 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
380 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
381 /* specific VSI-defined parameters, SRIOV stored the vf_id */
383 uint16_t seid; /* The seid of VSI itself */
384 uint16_t uplink_seid; /* The uplink seid of this VSI */
385 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
386 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
387 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
388 uint16_t base_queue; /* The first queue index of this VSI */
390 * The offset to visit VSI related register, assigned by HW when
394 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
395 uint16_t nb_msix; /* The max number of msix vector */
396 uint8_t enabled_tc; /* The traffic class enabled */
397 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
398 uint8_t vlan_filter_on; /* The VLAN filter enabled */
399 struct i40e_bw_info bw_info; /* VSI bandwidth information */
403 LIST_ENTRY(pool_entry) next;
408 LIST_HEAD(res_list, pool_entry);
410 struct i40e_res_pool_info {
411 uint32_t base; /* Resource start index */
412 uint32_t num_alloc; /* Allocated resource number */
413 uint32_t num_free; /* Total available resource number */
414 struct res_list alloc_list; /* Allocated resource list */
415 struct res_list free_list; /* Available resource list */
419 I40E_VF_INACTIVE = 0,
426 * Structure to store private data for PF host.
430 struct i40e_vsi *vsi;
431 enum I40E_VF_STATE state; /* The number of queue pairs available */
432 uint16_t vf_idx; /* VF index in pf->vfs */
433 uint16_t lan_nb_qps; /* Actual queues allocated */
434 uint16_t reset_cnt; /* Total vf reset times */
435 struct rte_ether_addr mac_addr; /* Default MAC address */
436 /* version of the virtchnl from VF */
437 struct virtchnl_version_info version;
438 uint32_t request_caps; /* offload caps requested from VF */
439 uint64_t num_mdd_events; /* num of mdd events detected */
442 * Variables for store the arrival timestamp of VF messages.
443 * If the timestamp of latest message stored at
444 * `msg_timestamps[index % max]` then the timestamp of
445 * earliest message stored at `msg_time[(index + 1) % max]`.
446 * When a new message come, the timestamp of this message
447 * will be stored at `msg_timestamps[(index + 1) % max]` and the
448 * earliest message timestamp is at
449 * `msg_timestamps[(index + 2) % max]` now...
452 uint64_t *msg_timestamps;
454 /* cycle of stop ignoring VF message */
455 uint64_t ignore_end_cycle;
459 * Structure to store private data for flow control.
461 struct i40e_fc_conf {
462 uint16_t pause_time; /* Flow control pause timer */
463 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
464 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
465 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
466 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
470 * Structure to store private data for VMDQ instance
472 struct i40e_vmdq_info {
474 struct i40e_vsi *vsi;
477 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
478 #define I40E_MAX_FLX_SOURCE_OFF 480
479 #define NONUSE_FLX_PIT_DEST_OFF 63
480 #define NONUSE_FLX_PIT_FSIZE 1
481 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
482 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
483 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
484 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
485 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
486 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
487 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
488 NONUSE_FLX_PIT_DEST_OFF : \
489 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
490 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
491 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
492 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
493 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
494 #define I40E_FDIR_IPv6_TC_OFFSET 20
496 /* A structure used to define the input for GTP flow */
497 struct i40e_gtp_flow {
498 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
499 uint8_t msg_type; /* Message type. */
500 uint32_t teid; /* TEID in big endian. */
503 /* A structure used to define the input for GTP IPV4 flow */
504 struct i40e_gtp_ipv4_flow {
505 struct i40e_gtp_flow gtp;
506 struct rte_eth_ipv4_flow ip4;
509 /* A structure used to define the input for GTP IPV6 flow */
510 struct i40e_gtp_ipv6_flow {
511 struct i40e_gtp_flow gtp;
512 struct rte_eth_ipv6_flow ip6;
515 /* A structure used to define the input for ESP IPV4 flow */
516 struct i40e_esp_ipv4_flow {
517 struct rte_eth_ipv4_flow ipv4;
518 uint32_t spi; /* SPI in big endian. */
521 /* A structure used to define the input for ESP IPV6 flow */
522 struct i40e_esp_ipv6_flow {
523 struct rte_eth_ipv6_flow ipv6;
524 uint32_t spi; /* SPI in big endian. */
526 /* A structure used to define the input for ESP IPV4 UDP flow */
527 struct i40e_esp_ipv4_udp_flow {
528 struct rte_eth_udpv4_flow udp;
529 uint32_t spi; /* SPI in big endian. */
532 /* A structure used to define the input for ESP IPV6 UDP flow */
533 struct i40e_esp_ipv6_udp_flow {
534 struct rte_eth_udpv6_flow udp;
535 uint32_t spi; /* SPI in big endian. */
538 /* A structure used to define the input for raw type flow */
539 struct i40e_raw_flow {
545 /* A structure used to define the input for L2TPv3 over IPv4 flow */
546 struct i40e_ipv4_l2tpv3oip_flow {
547 struct rte_eth_ipv4_flow ip4;
548 uint32_t session_id; /* Session ID in big endian. */
551 /* A structure used to define the input for L2TPv3 over IPv6 flow */
552 struct i40e_ipv6_l2tpv3oip_flow {
553 struct rte_eth_ipv6_flow ip6;
554 uint32_t session_id; /* Session ID in big endian. */
557 /* A structure used to define the input for l2 dst type flow */
558 struct i40e_l2_flow {
559 struct rte_ether_addr dst;
560 struct rte_ether_addr src;
561 uint16_t ether_type; /**< Ether type in big endian */
565 * A union contains the inputs for all types of flow
566 * items in flows need to be in big endian
568 union i40e_fdir_flow {
569 struct i40e_l2_flow l2_flow;
570 struct rte_eth_udpv4_flow udp4_flow;
571 struct rte_eth_tcpv4_flow tcp4_flow;
572 struct rte_eth_sctpv4_flow sctp4_flow;
573 struct rte_eth_ipv4_flow ip4_flow;
574 struct rte_eth_udpv6_flow udp6_flow;
575 struct rte_eth_tcpv6_flow tcp6_flow;
576 struct rte_eth_sctpv6_flow sctp6_flow;
577 struct rte_eth_ipv6_flow ipv6_flow;
578 struct i40e_gtp_flow gtp_flow;
579 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
580 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
581 struct i40e_raw_flow raw_flow;
582 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow;
583 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow;
584 struct i40e_esp_ipv4_flow esp_ipv4_flow;
585 struct i40e_esp_ipv6_flow esp_ipv6_flow;
586 struct i40e_esp_ipv4_udp_flow esp_ipv4_udp_flow;
587 struct i40e_esp_ipv6_udp_flow esp_ipv6_udp_flow;
590 enum i40e_fdir_ip_type {
591 I40E_FDIR_IPTYPE_IPV4,
592 I40E_FDIR_IPTYPE_IPV6,
595 /* A structure used to contain extend input of flow */
596 struct i40e_fdir_flow_ext {
598 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
599 /* It is filled by the flexible payload to match. */
600 uint8_t is_vf; /* 1 for VF, 0 for port dev */
601 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
602 bool inner_ip; /* If there is inner ip */
603 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
604 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */
605 bool customized_pctype; /* If customized pctype is used */
606 bool pkt_template; /* If raw packet template is used */
607 bool is_udp; /* ipv4|ipv6 udp flow */
610 /* A structure used to define the input for a flow director filter entry */
611 struct i40e_fdir_input {
612 enum i40e_filter_pctype pctype;
613 union i40e_fdir_flow flow;
614 /* Flow fields to match, dependent on flow_type */
615 struct i40e_fdir_flow_ext flow_ext;
616 /* Additional fields to match */
619 /* Behavior will be taken if FDIR match */
620 enum i40e_fdir_behavior {
621 I40E_FDIR_ACCEPT = 0,
626 /* Flow director report status
627 * It defines what will be reported if FDIR entry is matched.
629 enum i40e_fdir_status {
630 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
631 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
632 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
633 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
636 /* A structure used to define an action when match FDIR packet filter. */
637 struct i40e_fdir_action {
638 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
639 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
640 enum i40e_fdir_status report_status; /* Status report option */
641 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
642 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
643 * flex bytes start from in flexible payload.
648 /* A structure used to define the flow director filter entry by filter_ctrl API
649 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
650 * RTE_ETH_FILTER_DELETE operations.
652 struct i40e_fdir_filter_conf {
654 /* ID, an unique value is required when deal with FDIR entry */
655 struct i40e_fdir_input input; /* Input set */
656 struct i40e_fdir_action action; /* Action taken when match */
660 * Structure to store flex pit for flow diretor.
662 struct i40e_fdir_flex_pit {
663 uint8_t src_offset; /* offset in words from the beginning of payload */
664 uint8_t size; /* size in words */
665 uint8_t dst_offset; /* offset in words of flexible payload */
668 struct i40e_fdir_flex_mask {
669 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
674 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
677 #define I40E_FILTER_PCTYPE_INVALID 0
678 #define I40E_FILTER_PCTYPE_MAX 64
679 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
681 struct i40e_fdir_filter {
682 TAILQ_ENTRY(i40e_fdir_filter) rules;
683 struct i40e_fdir_filter_conf fdir;
686 /* fdir memory pool entry */
687 struct i40e_fdir_entry {
688 struct rte_flow flow;
692 /* pre-allocated fdir memory pool */
693 struct i40e_fdir_flow_pool {
694 /* a bitmap to manage the fdir pool */
695 struct rte_bitmap *bitmap;
696 /* the size the pool is pf->fdir->fdir_space_size */
697 struct i40e_fdir_entry *pool;
700 #define FLOW_TO_FLOW_BITMAP(f) \
701 container_of((f), struct i40e_fdir_entry, flow)
703 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
705 * A structure used to define fields of a FDIR related info.
707 struct i40e_fdir_info {
708 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
709 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
710 struct i40e_tx_queue *txq;
711 struct i40e_rx_queue *rxq;
712 void *prg_pkt; /* memory for fdir program packet */
713 uint64_t dma_addr; /* physic address of packet memory*/
714 /* input set bits for each pctype */
715 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
717 * the rule how bytes stream is extracted as flexible payload
718 * for each payload layer, the setting can up to three elements
720 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
721 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
723 struct i40e_fdir_filter_list fdir_list;
724 struct i40e_fdir_filter **hash_map;
725 struct rte_hash *hash_table;
726 /* An array to store the inserted rules input */
727 struct i40e_fdir_filter *fdir_filter_array;
730 * Priority ordering at filter invalidation(destroying a flow) between
731 * "best effort" space and "guaranteed" space.
733 * 0 = At filter invalidation, the hardware first tries to increment the
734 * "best effort" space. The "guaranteed" space is incremented only when
735 * the global "best effort" space is at it max value or the "best effort"
736 * space of the PF is at its max value.
737 * 1 = At filter invalidation, the hardware first tries to increment its
738 * "guaranteed" space. The "best effort" space is incremented only when
739 * it is already at its max value.
741 uint32_t fdir_invalprio;
742 /* the total size of the fdir, this number is the sum of the guaranteed +
745 uint32_t fdir_space_size;
746 /* the actual number of the fdir rules in hardware, initialized as 0 */
747 uint32_t fdir_actual_cnt;
748 /* the free guaranteed space of the fdir */
749 uint32_t fdir_guarantee_free_space;
750 /* the fdir total guaranteed space */
751 uint32_t fdir_guarantee_total_space;
752 /* the pre-allocated pool of the rte_flow */
753 struct i40e_fdir_flow_pool fdir_flow_pool;
755 /* Mark if flex pit and mask is set */
756 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
757 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
759 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
762 /* Ethertype filter number HW supports */
763 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
765 /* Ethertype filter struct */
766 struct i40e_ethertype_filter_input {
767 struct rte_ether_addr mac_addr; /* Mac address to match */
768 uint16_t ether_type; /* Ether type to match */
771 struct i40e_ethertype_filter {
772 TAILQ_ENTRY(i40e_ethertype_filter) rules;
773 struct i40e_ethertype_filter_input input;
774 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
775 uint16_t queue; /* Queue assigned to when match */
778 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
780 struct i40e_ethertype_rule {
781 struct i40e_ethertype_filter_list ethertype_list;
782 struct i40e_ethertype_filter **hash_map;
783 struct rte_hash *hash_table;
786 /* queue region info */
787 struct i40e_queue_region_info {
788 /* the region id for this configuration */
790 /* the start queue index for this region */
791 uint8_t queue_start_index;
792 /* the total queue number of this queue region */
794 /* the total number of user priority for this region */
795 uint8_t user_priority_num;
796 /* the packet's user priority for this region */
797 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
798 /* the total number of flowtype for this region */
799 uint8_t flowtype_num;
801 * the pctype or hardware flowtype of packet,
802 * the specific index for each type has been defined
803 * in file i40e_type.h as enum i40e_filter_pctype.
805 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
808 struct i40e_queue_regions {
809 /* the total number of queue region for this port */
810 uint16_t queue_region_number;
811 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
814 struct i40e_rss_pattern_info {
819 /* Tunnel filter number HW supports */
820 #define I40E_MAX_TUNNEL_FILTER_NUM 400
822 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
823 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
824 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT 29
825 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT 30
826 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
827 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
828 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
829 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
830 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
831 #define I40E_AQC_ADD_L1_FILTER_0X10 0x10
832 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
833 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
834 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
835 #define I40E_AQC_NEW_TR_21 21
836 #define I40E_AQC_NEW_TR_22 22
838 enum i40e_tunnel_iptype {
839 I40E_TUNNEL_IPTYPE_IPV4,
840 I40E_TUNNEL_IPTYPE_IPV6,
843 /* Tunnel filter struct */
844 struct i40e_tunnel_filter_input {
845 uint8_t outer_mac[6]; /* Outer mac address to match */
846 uint8_t inner_mac[6]; /* Inner mac address to match */
847 uint16_t inner_vlan; /* Inner vlan address to match */
848 enum i40e_tunnel_iptype ip_type;
849 uint16_t flags; /* Filter type flag */
850 uint32_t tenant_id; /* Tenant id to match */
851 uint16_t general_fields[32]; /* Big buffer */
854 struct i40e_tunnel_filter {
855 TAILQ_ENTRY(i40e_tunnel_filter) rules;
856 struct i40e_tunnel_filter_input input;
857 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
858 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
859 uint16_t queue; /* Queue assigned to when match */
862 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
864 struct i40e_tunnel_rule {
865 struct i40e_tunnel_filter_list tunnel_list;
866 struct i40e_tunnel_filter **hash_map;
867 struct rte_hash *hash_table;
873 enum i40e_tunnel_type {
874 I40E_TUNNEL_TYPE_NONE = 0,
875 I40E_TUNNEL_TYPE_VXLAN,
876 I40E_TUNNEL_TYPE_GENEVE,
877 I40E_TUNNEL_TYPE_TEREDO,
878 I40E_TUNNEL_TYPE_NVGRE,
879 I40E_TUNNEL_TYPE_IP_IN_GRE,
880 I40E_L2_TUNNEL_TYPE_E_TAG,
881 I40E_TUNNEL_TYPE_MPLSoUDP,
882 I40E_TUNNEL_TYPE_MPLSoGRE,
883 I40E_TUNNEL_TYPE_QINQ,
884 I40E_TUNNEL_TYPE_GTPC,
885 I40E_TUNNEL_TYPE_GTPU,
886 I40E_TUNNEL_TYPE_ESPoUDP,
887 I40E_TUNNEL_TYPE_ESPoIP,
890 I40E_CLOUD_TYPE_SCTP,
891 I40E_TUNNEL_TYPE_MAX,
897 enum i40e_l4_port_type {
898 I40E_L4_PORT_TYPE_SRC = 0,
899 I40E_L4_PORT_TYPE_DST,
903 * Tunneling Packet filter configuration.
905 struct i40e_tunnel_filter_conf {
906 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */
907 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */
908 uint16_t inner_vlan; /**< Inner VLAN to match. */
909 uint32_t outer_vlan; /**< Outer VLAN to match */
910 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
912 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
913 * is set in filter_type, or inner destination IP address to match
914 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
917 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
918 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
920 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
921 uint16_t filter_type;
922 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
923 enum i40e_l4_port_type l4_port_type; /**< L4 Port Type. */
924 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
925 uint16_t queue_id; /**< Queue assigned to if match. */
926 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
927 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
930 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
931 #define I40E_MAX_MIRROR_RULES 64
933 * Mirror rule structure
935 struct i40e_mirror_rule {
936 TAILQ_ENTRY(i40e_mirror_rule) rules;
938 uint16_t index; /* the sw index of mirror rule */
939 uint16_t id; /* the rule id assigned by firmware */
940 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
941 uint16_t num_entries;
942 /* the info stores depend on the rule type.
943 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
944 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
946 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
949 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
951 TAILQ_HEAD(i40e_flow_list, rte_flow);
953 /* Struct to store Traffic Manager shaper profile. */
954 struct i40e_tm_shaper_profile {
955 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
956 uint32_t shaper_profile_id;
957 uint32_t reference_count;
958 struct rte_tm_shaper_params profile;
961 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
963 /* node type of Traffic Manager */
964 enum i40e_tm_node_type {
965 I40E_TM_NODE_TYPE_PORT,
966 I40E_TM_NODE_TYPE_TC,
967 I40E_TM_NODE_TYPE_QUEUE,
968 I40E_TM_NODE_TYPE_MAX,
971 /* Struct to store Traffic Manager node configuration. */
972 struct i40e_tm_node {
973 TAILQ_ENTRY(i40e_tm_node) node;
977 uint32_t reference_count;
978 struct i40e_tm_node *parent;
979 struct i40e_tm_shaper_profile *shaper_profile;
980 struct rte_tm_node_params params;
983 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
985 /* Struct to store all the Traffic Manager configuration. */
986 struct i40e_tm_conf {
987 struct i40e_shaper_profile_list shaper_profile_list;
988 struct i40e_tm_node *root; /* root node - port */
989 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
990 struct i40e_tm_node_list queue_list; /* node list for all the queues */
992 * The number of added TC nodes.
993 * It should be no more than the TC number of this port.
997 * The number of added queue nodes.
998 * It should be no more than the queue number of this port.
1000 uint32_t nb_queue_node;
1002 * This flag is used to check if APP can change the TM node
1004 * When it's true, means the configuration is applied to HW,
1005 * APP should not change the configuration.
1006 * As we don't support on-the-fly configuration, when starting
1007 * the port, APP should call the hierarchy_commit API to set this
1008 * flag to true. When stopping the port, this flag should be set
1014 enum i40e_new_pctype {
1015 I40E_CUSTOMIZED_GTPC = 0,
1016 I40E_CUSTOMIZED_GTPU_IPV4,
1017 I40E_CUSTOMIZED_GTPU_IPV6,
1018 I40E_CUSTOMIZED_GTPU,
1019 I40E_CUSTOMIZED_IPV4_L2TPV3,
1020 I40E_CUSTOMIZED_IPV6_L2TPV3,
1021 I40E_CUSTOMIZED_ESP_IPV4,
1022 I40E_CUSTOMIZED_ESP_IPV6,
1023 I40E_CUSTOMIZED_ESP_IPV4_UDP,
1024 I40E_CUSTOMIZED_ESP_IPV6_UDP,
1025 I40E_CUSTOMIZED_AH_IPV4,
1026 I40E_CUSTOMIZED_AH_IPV6,
1027 I40E_CUSTOMIZED_MAX,
1030 #define I40E_FILTER_PCTYPE_INVALID 0
1031 struct i40e_customized_pctype {
1032 enum i40e_new_pctype index; /* Indicate which customized pctype */
1033 uint8_t pctype; /* New pctype value */
1034 bool valid; /* Check if it's valid */
1037 struct i40e_rte_flow_rss_conf {
1038 struct rte_flow_action_rss conf; /**< RSS parameters. */
1039 uint16_t queue_region_conf; /**< Queue region config flag */
1040 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
1041 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
1042 sizeof(uint32_t)]; /* Hash key. */
1043 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
1044 bool valid; /* Check if it's valid */
1047 TAILQ_HEAD(i40e_rss_conf_list, i40e_rss_filter);
1049 /* RSS filter list structure */
1050 struct i40e_rss_filter {
1051 TAILQ_ENTRY(i40e_rss_filter) next;
1052 struct i40e_rte_flow_rss_conf rss_filter_info;
1055 struct i40e_vf_msg_cfg {
1056 /* maximal VF message during a statistic period */
1059 /* statistic period, in second */
1062 * If message statistics from a VF exceed the maximal limitation,
1063 * the PF will ignore any new message from that VF for
1064 * 'ignor_second' time.
1066 uint32_t ignore_second;
1070 * Structure to store private data specific for PF instance.
1073 struct i40e_adapter *adapter; /* The adapter this PF associate to */
1074 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
1075 uint16_t mac_seid; /* The seid of the MAC of this PF */
1076 uint16_t main_vsi_seid; /* The seid of the main VSI */
1077 uint16_t max_num_vsi;
1078 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
1079 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
1081 struct i40e_hw_port_stats stats_offset;
1082 struct i40e_hw_port_stats stats;
1083 /* internal packet statistics, it should be excluded from the total */
1084 struct i40e_eth_stats internal_stats_offset;
1085 struct i40e_eth_stats internal_stats;
1088 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1089 struct rte_ether_addr dev_addr; /* PF device mac address */
1090 uint64_t flags; /* PF feature flags */
1091 /* All kinds of queue pair setting for different VSIs */
1092 struct i40e_pf_vf *vfs;
1094 /* Each of below queue pairs should be power of 2 since it's the
1095 precondition after TC configuration applied */
1096 uint16_t lan_nb_qp_max;
1097 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
1098 uint16_t lan_qp_offset;
1099 uint16_t vmdq_nb_qp_max;
1100 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
1101 uint16_t vmdq_qp_offset;
1102 uint16_t vf_nb_qp_max;
1103 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
1104 uint16_t vf_qp_offset;
1105 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
1106 uint16_t fdir_qp_offset;
1108 uint16_t hash_lut_size; /* The size of hash lookup table */
1109 /* input set bits for each pctype */
1110 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
1111 /* store VXLAN UDP ports */
1112 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
1113 uint16_t vxlan_bitmap; /* Vxlan bit mask */
1115 /* VMDQ related info */
1116 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
1117 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
1118 struct i40e_vmdq_info *vmdq;
1120 struct i40e_fdir_info fdir; /* flow director info */
1121 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
1122 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
1123 struct i40e_rte_flow_rss_conf rss_info; /* RSS info */
1124 struct i40e_rss_conf_list rss_config_list; /* RSS rule list */
1125 struct i40e_queue_regions queue_region; /* queue region info */
1126 struct i40e_fc_conf fc_conf; /* Flow control conf */
1127 struct i40e_mirror_rule_list mirror_list;
1128 uint16_t nb_mirror_rule; /* The number of mirror rules */
1129 bool floating_veb; /* The flag to use the floating VEB */
1130 /* The floating enable flag for the specific VF */
1131 bool floating_veb_list[I40E_MAX_VF];
1132 struct i40e_flow_list flow_list;
1133 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
1134 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
1135 bool qinq_replace_flag; /* QINQ filter replace is done */
1137 bool sport_replace_flag; /* Source port replace is done */
1138 bool dport_replace_flag; /* Destination port replace is done */
1139 struct i40e_tm_conf tm_conf;
1140 bool support_multi_driver; /* 1 - support multiple driver */
1142 /* Dynamic Device Personalization */
1143 bool gtp_support; /* 1 - support GTP-C and GTP-U */
1144 bool esp_support; /* 1 - support ESP SPI */
1145 /* customer customized pctype */
1146 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
1147 /* Switch Domain Id */
1148 uint16_t switch_domain_id;
1150 struct i40e_vf_msg_cfg vf_msg_cfg;
1154 PFMSG_LINK_CHANGE = 0x1,
1155 PFMSG_RESET_IMPENDING = 0x2,
1156 PFMSG_DRIVER_CLOSE = 0x4,
1159 struct i40e_vsi_vlan_pvid_info {
1160 uint16_t on; /* Enable or disable pvid */
1162 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
1164 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
1165 * while 'untagged' will reject untagged packets.
1173 struct i40e_vf_rx_queues {
1174 uint64_t rx_dma_addr;
1175 uint32_t rx_ring_len;
1179 struct i40e_vf_tx_queues {
1180 uint64_t tx_dma_addr;
1181 uint32_t tx_ring_len;
1185 * Structure to store private data specific for VF instance.
1188 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1189 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1190 uint16_t num_queue_pairs;
1191 uint16_t max_pkt_len; /* Maximum packet length */
1192 bool promisc_unicast_enabled;
1193 bool promisc_multicast_enabled;
1195 uint32_t version_major; /* Major version number */
1196 uint32_t version_minor; /* Minor version number */
1197 uint16_t promisc_flags; /* Promiscuous setting */
1198 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1200 /* Multicast addrs */
1201 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX];
1202 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1207 enum virtchnl_link_speed link_speed;
1209 volatile uint32_t pend_cmd; /* pending command not finished yet */
1210 int32_t cmd_retval; /* return value of the cmd response from PF */
1211 u16 pend_msg; /* flags indicates events from pf not handled yet */
1212 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1215 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1216 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1217 struct i40e_vsi vsi;
1221 #define I40E_MAX_PKT_TYPE 256
1222 #define I40E_FLOW_TYPE_MAX 64
1225 * Structure to store private data for each PF/VF instance.
1227 struct i40e_adapter {
1228 /* Common for both PF and VF */
1230 struct rte_eth_dev *eth_dev;
1232 /* Specific for PF or VF */
1238 /* For vector PMD */
1239 bool rx_bulk_alloc_allowed;
1240 bool rx_vec_allowed;
1241 bool tx_simple_allowed;
1242 bool tx_vec_allowed;
1245 struct rte_timecounter systime_tc;
1246 struct rte_timecounter rx_tstamp_tc;
1247 struct rte_timecounter tx_tstamp_tc;
1249 /* ptype mapping table */
1250 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1251 /* flow type to pctype mapping table */
1252 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1253 uint64_t flow_types_mask;
1254 uint64_t pctypes_mask;
1257 uint8_t use_latest_vec;
1259 /* For RSS reta table update */
1260 uint8_t rss_reta_updated;
1264 * Strucute to store private data for each VF representor instance
1266 struct i40e_vf_representor {
1267 uint16_t switch_domain_id;
1268 /**< Virtual Function ID */
1270 /**< Virtual Function ID */
1271 struct i40e_adapter *adapter;
1272 /**< Private data store of assocaiated physical function */
1273 struct i40e_eth_stats stats_offset;
1274 /**< Zero-point of VF statistics*/
1277 extern const struct rte_flow_ops i40e_flow_ops;
1279 union i40e_filter_t {
1280 struct rte_eth_ethertype_filter ethertype_filter;
1281 struct i40e_fdir_filter_conf fdir_filter;
1282 struct rte_eth_tunnel_filter_conf tunnel_filter;
1283 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1284 struct i40e_rte_flow_rss_conf rss_conf;
1287 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1288 const struct rte_flow_attr *attr,
1289 const struct rte_flow_item pattern[],
1290 const struct rte_flow_action actions[],
1291 struct rte_flow_error *error,
1292 union i40e_filter_t *filter);
1293 struct i40e_valid_pattern {
1294 enum rte_flow_item_type *items;
1295 parse_filter_t parse_filter;
1298 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1299 int i40e_vsi_release(struct i40e_vsi *vsi);
1300 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1301 enum i40e_vsi_type type,
1302 struct i40e_vsi *uplink_vsi,
1303 uint16_t user_param);
1304 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1305 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1306 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1307 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1308 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1309 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr);
1310 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1311 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1312 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1313 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1314 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1315 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1316 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1317 struct i40e_vsi_vlan_pvid_info *info);
1318 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1319 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1320 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1321 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1322 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1323 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1324 int i40e_fdir_setup(struct i40e_pf *pf);
1325 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1328 int i40e_fdir_configure(struct rte_eth_dev *dev);
1329 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on);
1330 void i40e_fdir_teardown(struct i40e_pf *pf);
1331 enum i40e_filter_pctype
1332 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1333 uint16_t flow_type);
1334 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1335 enum i40e_filter_pctype pctype);
1336 int i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len);
1337 void i40e_fdir_info_get(struct rte_eth_dev *dev,
1338 struct rte_eth_fdir_info *fdir);
1339 void i40e_fdir_stats_get(struct rte_eth_dev *dev,
1340 struct rte_eth_fdir_stats *stat);
1341 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1342 enum rte_filter_op filter_op,
1344 int i40e_select_filter_input_set(struct i40e_hw *hw,
1345 struct rte_eth_input_set_conf *conf,
1346 enum rte_filter_type filter);
1347 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1348 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1349 struct rte_eth_input_set_conf *conf);
1350 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1351 struct rte_eth_input_set_conf *conf);
1352 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1353 uint32_t retval, uint8_t *msg,
1355 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1356 struct rte_eth_rxq_info *qinfo);
1357 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1358 struct rte_eth_txq_info *qinfo);
1359 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1360 struct rte_eth_burst_mode *mode);
1361 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1362 struct rte_eth_burst_mode *mode);
1363 struct i40e_ethertype_filter *
1364 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1365 const struct i40e_ethertype_filter_input *input);
1366 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1367 struct i40e_ethertype_filter_input *input);
1368 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1369 struct i40e_fdir_input *input);
1370 struct i40e_tunnel_filter *
1371 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1372 const struct i40e_tunnel_filter_input *input);
1373 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1374 struct i40e_tunnel_filter_input *input);
1375 uint64_t i40e_get_default_input_set(uint16_t pctype);
1376 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1377 struct rte_eth_ethertype_filter *filter,
1379 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1380 const struct rte_eth_fdir_filter *filter,
1383 i40e_fdir_entry_pool_get(struct i40e_fdir_info *fdir_info);
1384 void i40e_fdir_entry_pool_put(struct i40e_fdir_info *fdir_info,
1385 struct rte_flow *flow);
1386 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1387 const struct i40e_fdir_filter_conf *filter,
1389 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1390 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1392 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1393 struct i40e_tunnel_filter_conf *tunnel_filter,
1395 int i40e_fdir_flush(struct rte_eth_dev *dev);
1396 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1397 struct i40e_macvlan_filter *mv_f,
1398 int num, struct rte_ether_addr *addr);
1399 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1400 struct i40e_macvlan_filter *filter,
1402 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1403 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1404 struct i40e_macvlan_filter *filter,
1406 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv);
1407 bool is_i40e_supported(struct rte_eth_dev *dev);
1408 bool is_i40evf_supported(struct rte_eth_dev *dev);
1410 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1411 enum rte_filter_type filter, uint64_t inset);
1412 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1414 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1415 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1416 void i40e_check_write_global_reg(struct i40e_hw *hw,
1417 uint32_t addr, uint32_t val);
1419 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1420 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1421 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1422 struct i40e_customized_pctype*
1423 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1424 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1426 enum rte_pmd_i40e_package_op op);
1427 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1428 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1429 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1430 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1431 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1432 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1433 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1434 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1435 const struct rte_flow_action_rss *in);
1436 int i40e_config_rss_filter(struct i40e_pf *pf,
1437 struct i40e_rte_flow_rss_conf *conf, bool add);
1438 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1439 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1441 #define I40E_DEV_TO_PCI(eth_dev) \
1442 RTE_DEV_TO_PCI((eth_dev)->device)
1444 /* I40E_DEV_PRIVATE_TO */
1445 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1446 (&((struct i40e_adapter *)adapter)->pf)
1447 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1448 (&((struct i40e_adapter *)adapter)->hw)
1449 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1450 ((struct i40e_adapter *)adapter)
1452 /* I40EVF_DEV_PRIVATE_TO */
1453 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1454 (&((struct i40e_adapter *)adapter)->vf)
1456 static inline struct i40e_vsi *
1457 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1464 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1465 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1466 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1469 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1470 return pf->main_vsi;
1473 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1474 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1477 #define I40E_VSI_TO_HW(vsi) \
1478 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1479 #define I40E_VSI_TO_PF(vsi) \
1480 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1481 #define I40E_VSI_TO_VF(vsi) \
1482 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1483 #define I40E_VSI_TO_DEV_DATA(vsi) \
1484 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1485 #define I40E_VSI_TO_ETH_DEV(vsi) \
1486 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1489 #define I40E_PF_TO_HW(pf) \
1490 (&(((struct i40e_pf *)pf)->adapter->hw))
1491 #define I40E_PF_TO_ADAPTER(pf) \
1492 ((struct i40e_adapter *)pf->adapter)
1495 #define I40E_VF_TO_HW(vf) \
1496 (&(((struct i40e_vf *)vf)->adapter->hw))
1499 i40e_init_adminq_parameter(struct i40e_hw *hw)
1501 hw->aq.num_arq_entries = I40E_AQ_LEN;
1502 hw->aq.num_asq_entries = I40E_AQ_LEN;
1503 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1504 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1508 i40e_align_floor(int n)
1512 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1515 static inline uint16_t
1516 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
1518 uint16_t interval = 0;
1521 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1524 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1526 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1529 /* Convert to hardware count, as writing each 1 represents 2 us */
1530 return interval / 2;
1533 #define I40E_VALID_FLOW(flow_type) \
1534 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1535 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1536 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1537 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1538 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1539 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1540 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1541 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1542 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1543 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1544 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1546 #define I40E_VALID_PCTYPE_X722(pctype) \
1547 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1548 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1549 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1550 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1551 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1552 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1553 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1554 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1555 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1556 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1557 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1558 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1559 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1560 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1561 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1562 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1563 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1565 #define I40E_VALID_PCTYPE(pctype) \
1566 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1567 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1568 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1569 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1570 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1571 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1572 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1573 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1574 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1575 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1576 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1578 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1579 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1580 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1581 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1582 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1583 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1584 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1586 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1587 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1588 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1589 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1590 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
1591 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
1592 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
1594 #endif /* _I40E_ETHDEV_H_ */