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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_ethdev_pci.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static void i40evf_dev_close(struct rte_eth_dev *dev);
123 static int i40evf_dev_reset(struct rte_eth_dev *dev);
124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
155 struct ether_addr *mac_addr);
157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
164 /* Default hash key buffer for RSS */
165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
167 struct rte_i40evf_xstats_name_off {
168 char name[RTE_ETH_XSTATS_NAME_SIZE];
172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
173 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
174 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
175 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
176 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
177 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
178 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
179 rx_unknown_protocol)},
180 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
182 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
183 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
184 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
185 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
189 sizeof(rte_i40evf_stats_strings[0]))
191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
192 .dev_configure = i40evf_dev_configure,
193 .dev_start = i40evf_dev_start,
194 .dev_stop = i40evf_dev_stop,
195 .promiscuous_enable = i40evf_dev_promiscuous_enable,
196 .promiscuous_disable = i40evf_dev_promiscuous_disable,
197 .allmulticast_enable = i40evf_dev_allmulticast_enable,
198 .allmulticast_disable = i40evf_dev_allmulticast_disable,
199 .link_update = i40evf_dev_link_update,
200 .stats_get = i40evf_dev_stats_get,
201 .stats_reset = i40evf_dev_xstats_reset,
202 .xstats_get = i40evf_dev_xstats_get,
203 .xstats_get_names = i40evf_dev_xstats_get_names,
204 .xstats_reset = i40evf_dev_xstats_reset,
205 .dev_close = i40evf_dev_close,
206 .dev_reset = i40evf_dev_reset,
207 .dev_infos_get = i40evf_dev_info_get,
208 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
209 .vlan_filter_set = i40evf_vlan_filter_set,
210 .vlan_offload_set = i40evf_vlan_offload_set,
211 .rx_queue_start = i40evf_dev_rx_queue_start,
212 .rx_queue_stop = i40evf_dev_rx_queue_stop,
213 .tx_queue_start = i40evf_dev_tx_queue_start,
214 .tx_queue_stop = i40evf_dev_tx_queue_stop,
215 .rx_queue_setup = i40e_dev_rx_queue_setup,
216 .rx_queue_release = i40e_dev_rx_queue_release,
217 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
218 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
219 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
220 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
221 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
222 .tx_queue_setup = i40e_dev_tx_queue_setup,
223 .tx_queue_release = i40e_dev_tx_queue_release,
224 .rx_queue_count = i40e_dev_rx_queue_count,
225 .rxq_info_get = i40e_rxq_info_get,
226 .txq_info_get = i40e_txq_info_get,
227 .mac_addr_add = i40evf_add_mac_addr,
228 .mac_addr_remove = i40evf_del_mac_addr,
229 .reta_update = i40evf_dev_rss_reta_update,
230 .reta_query = i40evf_dev_rss_reta_query,
231 .rss_hash_update = i40evf_dev_rss_hash_update,
232 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
233 .mtu_set = i40evf_dev_mtu_set,
234 .mac_addr_set = i40evf_set_default_mac_addr,
238 * Read data in admin queue to get msg from pf driver
240 static enum i40evf_aq_result
241 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
244 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
245 struct i40e_arq_event_info event;
246 enum virtchnl_ops opcode;
247 enum i40e_status_code retval;
249 enum i40evf_aq_result result = I40EVF_MSG_NON;
251 event.buf_len = data->buf_len;
252 event.msg_buf = data->msg;
253 ret = i40e_clean_arq_element(hw, &event, NULL);
254 /* Can't read any msg from adminQ */
256 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
257 result = I40EVF_MSG_ERR;
261 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
262 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
264 if (opcode == VIRTCHNL_OP_EVENT) {
265 struct virtchnl_pf_event *vpe =
266 (struct virtchnl_pf_event *)event.msg_buf;
268 result = I40EVF_MSG_SYS;
269 switch (vpe->event) {
270 case VIRTCHNL_EVENT_LINK_CHANGE:
272 vpe->event_data.link_event.link_status;
274 vpe->event_data.link_event.link_speed;
275 vf->pend_msg |= PFMSG_LINK_CHANGE;
276 PMD_DRV_LOG(INFO, "Link status update:%s",
277 vf->link_up ? "up" : "down");
279 case VIRTCHNL_EVENT_RESET_IMPENDING:
281 vf->pend_msg |= PFMSG_RESET_IMPENDING;
282 PMD_DRV_LOG(INFO, "vf is reseting");
284 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
285 vf->dev_closed = true;
286 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
287 PMD_DRV_LOG(INFO, "PF driver closed");
290 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
291 __func__, vpe->event);
294 /* async reply msg on command issued by vf previously */
295 result = I40EVF_MSG_CMD;
296 /* Actual data length read from PF */
297 data->msg_len = event.msg_len;
300 data->result = retval;
307 * clear current command. Only call in case execute
308 * _atomic_set_cmd successfully.
311 _clear_cmd(struct i40e_vf *vf)
314 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
318 * Check there is pending cmd in execution. If none, set new command.
321 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
323 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
324 VIRTCHNL_OP_UNKNOWN, ops);
327 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
332 #define MAX_TRY_TIMES 200
333 #define ASQ_DELAY_MS 10
336 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
339 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
340 struct i40evf_arq_msg_info info;
341 enum i40evf_aq_result ret;
344 if (_atomic_set_cmd(vf, args->ops))
347 info.msg = args->out_buffer;
348 info.buf_len = args->out_size;
349 info.ops = VIRTCHNL_OP_UNKNOWN;
350 info.result = I40E_SUCCESS;
352 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
353 args->in_args, args->in_args_size, NULL);
355 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
361 case VIRTCHNL_OP_RESET_VF:
362 /*no need to process in this function */
365 case VIRTCHNL_OP_VERSION:
366 case VIRTCHNL_OP_GET_VF_RESOURCES:
367 /* for init adminq commands, need to poll the response */
370 ret = i40evf_read_pfmsg(dev, &info);
371 vf->cmd_retval = info.result;
372 if (ret == I40EVF_MSG_CMD) {
375 } else if (ret == I40EVF_MSG_ERR)
377 rte_delay_ms(ASQ_DELAY_MS);
378 /* If don't read msg or read sys event, continue */
379 } while (i++ < MAX_TRY_TIMES);
384 /* for other adminq in running time, waiting the cmd done flag */
387 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
391 rte_delay_ms(ASQ_DELAY_MS);
392 /* If don't read msg or read sys event, continue */
393 } while (i++ < MAX_TRY_TIMES);
394 /* If there's no response is received, clear command */
395 if (i >= MAX_TRY_TIMES) {
396 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
402 return err | vf->cmd_retval;
406 * Check API version with sync wait until version read or fail from admin queue
409 i40evf_check_api_version(struct rte_eth_dev *dev)
411 struct virtchnl_version_info version, *pver;
413 struct vf_cmd_info args;
414 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
416 version.major = VIRTCHNL_VERSION_MAJOR;
417 version.minor = VIRTCHNL_VERSION_MINOR;
419 args.ops = VIRTCHNL_OP_VERSION;
420 args.in_args = (uint8_t *)&version;
421 args.in_args_size = sizeof(version);
422 args.out_buffer = vf->aq_resp;
423 args.out_size = I40E_AQ_BUF_SZ;
425 err = i40evf_execute_vf_cmd(dev, &args);
427 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
431 pver = (struct virtchnl_version_info *)args.out_buffer;
432 vf->version_major = pver->major;
433 vf->version_minor = pver->minor;
434 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
435 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
436 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
438 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
439 vf->version_major, vf->version_minor,
440 VIRTCHNL_VERSION_MAJOR,
441 VIRTCHNL_VERSION_MINOR);
449 i40evf_get_vf_resource(struct rte_eth_dev *dev)
451 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
454 struct vf_cmd_info args;
457 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
458 args.out_buffer = vf->aq_resp;
459 args.out_size = I40E_AQ_BUF_SZ;
461 caps = VIRTCHNL_VF_OFFLOAD_L2 |
462 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
463 VIRTCHNL_VF_OFFLOAD_RSS_REG |
464 VIRTCHNL_VF_OFFLOAD_VLAN |
465 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
466 args.in_args = (uint8_t *)∩︀
467 args.in_args_size = sizeof(caps);
470 args.in_args_size = 0;
472 err = i40evf_execute_vf_cmd(dev, &args);
475 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
479 len = sizeof(struct virtchnl_vf_resource) +
480 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
482 rte_memcpy(vf->vf_res, args.out_buffer,
483 RTE_MIN(args.out_size, len));
484 i40e_vf_parse_hw_config(hw, vf->vf_res);
490 i40evf_config_promisc(struct rte_eth_dev *dev,
492 bool enable_multicast)
494 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
496 struct vf_cmd_info args;
497 struct virtchnl_promisc_info promisc;
500 promisc.vsi_id = vf->vsi_res->vsi_id;
503 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
505 if (enable_multicast)
506 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
508 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
509 args.in_args = (uint8_t *)&promisc;
510 args.in_args_size = sizeof(promisc);
511 args.out_buffer = vf->aq_resp;
512 args.out_size = I40E_AQ_BUF_SZ;
514 err = i40evf_execute_vf_cmd(dev, &args);
517 PMD_DRV_LOG(ERR, "fail to execute command "
518 "CONFIG_PROMISCUOUS_MODE");
523 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
525 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
526 struct vf_cmd_info args;
529 memset(&args, 0, sizeof(args));
530 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
532 args.in_args_size = 0;
533 args.out_buffer = vf->aq_resp;
534 args.out_size = I40E_AQ_BUF_SZ;
535 ret = i40evf_execute_vf_cmd(dev, &args);
537 PMD_DRV_LOG(ERR, "Failed to execute command of "
538 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
544 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
546 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
547 struct vf_cmd_info args;
550 memset(&args, 0, sizeof(args));
551 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
553 args.in_args_size = 0;
554 args.out_buffer = vf->aq_resp;
555 args.out_size = I40E_AQ_BUF_SZ;
556 ret = i40evf_execute_vf_cmd(dev, &args);
558 PMD_DRV_LOG(ERR, "Failed to execute command of "
559 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
565 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
569 struct i40e_tx_queue *txq)
571 txq_info->vsi_id = vsi_id;
572 txq_info->queue_id = queue_id;
573 if (queue_id < nb_txq) {
574 txq_info->ring_len = txq->nb_tx_desc;
575 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
580 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
584 uint32_t max_pkt_size,
585 struct i40e_rx_queue *rxq)
587 rxq_info->vsi_id = vsi_id;
588 rxq_info->queue_id = queue_id;
589 rxq_info->max_pkt_size = max_pkt_size;
590 if (queue_id < nb_rxq) {
591 rxq_info->ring_len = rxq->nb_rx_desc;
592 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
593 rxq_info->databuffer_size =
594 (rte_pktmbuf_data_room_size(rxq->mp) -
595 RTE_PKTMBUF_HEADROOM);
600 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
602 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
603 struct i40e_rx_queue **rxq =
604 (struct i40e_rx_queue **)dev->data->rx_queues;
605 struct i40e_tx_queue **txq =
606 (struct i40e_tx_queue **)dev->data->tx_queues;
607 struct virtchnl_vsi_queue_config_info *vc_vqci;
608 struct virtchnl_queue_pair_info *vc_qpi;
609 struct vf_cmd_info args;
610 uint16_t i, nb_qp = vf->num_queue_pairs;
611 const uint32_t size =
612 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
616 memset(buff, 0, sizeof(buff));
617 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
618 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
619 vc_vqci->num_queue_pairs = nb_qp;
621 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
622 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
623 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
624 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
625 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
626 vf->max_pkt_len, rxq[i]);
628 memset(&args, 0, sizeof(args));
629 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
630 args.in_args = (uint8_t *)vc_vqci;
631 args.in_args_size = size;
632 args.out_buffer = vf->aq_resp;
633 args.out_size = I40E_AQ_BUF_SZ;
634 ret = i40evf_execute_vf_cmd(dev, &args);
636 PMD_DRV_LOG(ERR, "Failed to execute command of "
637 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
643 i40evf_config_irq_map(struct rte_eth_dev *dev)
645 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
646 struct vf_cmd_info args;
647 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
648 sizeof(struct virtchnl_vector_map)];
649 struct virtchnl_irq_map_info *map_info;
650 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
651 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
655 if (rte_intr_allow_others(intr_handle))
656 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
658 vector_id = I40E_MISC_VEC_ID;
660 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
661 map_info->num_vectors = 1;
662 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
663 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
664 /* Alway use default dynamic MSIX interrupt */
665 map_info->vecmap[0].vector_id = vector_id;
666 /* Don't map any tx queue */
667 map_info->vecmap[0].txq_map = 0;
668 map_info->vecmap[0].rxq_map = 0;
669 for (i = 0; i < dev->data->nb_rx_queues; i++) {
670 map_info->vecmap[0].rxq_map |= 1 << i;
671 if (rte_intr_dp_is_en(intr_handle))
672 intr_handle->intr_vec[i] = vector_id;
675 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
676 args.in_args = (u8 *)cmd_buffer;
677 args.in_args_size = sizeof(cmd_buffer);
678 args.out_buffer = vf->aq_resp;
679 args.out_size = I40E_AQ_BUF_SZ;
680 err = i40evf_execute_vf_cmd(dev, &args);
682 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
688 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
691 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
692 struct virtchnl_queue_select queue_select;
694 struct vf_cmd_info args;
695 memset(&queue_select, 0, sizeof(queue_select));
696 queue_select.vsi_id = vf->vsi_res->vsi_id;
699 queue_select.rx_queues |= 1 << qid;
701 queue_select.tx_queues |= 1 << qid;
704 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
706 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
707 args.in_args = (u8 *)&queue_select;
708 args.in_args_size = sizeof(queue_select);
709 args.out_buffer = vf->aq_resp;
710 args.out_size = I40E_AQ_BUF_SZ;
711 err = i40evf_execute_vf_cmd(dev, &args);
713 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
714 isrx ? "RX" : "TX", qid, on ? "on" : "off");
720 i40evf_start_queues(struct rte_eth_dev *dev)
722 struct rte_eth_dev_data *dev_data = dev->data;
724 struct i40e_rx_queue *rxq;
725 struct i40e_tx_queue *txq;
727 for (i = 0; i < dev->data->nb_rx_queues; i++) {
728 rxq = dev_data->rx_queues[i];
729 if (rxq->rx_deferred_start)
731 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
732 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
737 for (i = 0; i < dev->data->nb_tx_queues; i++) {
738 txq = dev_data->tx_queues[i];
739 if (txq->tx_deferred_start)
741 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
742 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
751 i40evf_stop_queues(struct rte_eth_dev *dev)
755 /* Stop TX queues first */
756 for (i = 0; i < dev->data->nb_tx_queues; i++) {
757 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
758 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
763 /* Then stop RX queues */
764 for (i = 0; i < dev->data->nb_rx_queues; i++) {
765 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
766 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
775 i40evf_add_mac_addr(struct rte_eth_dev *dev,
776 struct ether_addr *addr,
777 __rte_unused uint32_t index,
778 __rte_unused uint32_t pool)
780 struct virtchnl_ether_addr_list *list;
781 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
782 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
783 sizeof(struct virtchnl_ether_addr)];
785 struct vf_cmd_info args;
787 if (is_zero_ether_addr(addr)) {
788 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
789 addr->addr_bytes[0], addr->addr_bytes[1],
790 addr->addr_bytes[2], addr->addr_bytes[3],
791 addr->addr_bytes[4], addr->addr_bytes[5]);
792 return I40E_ERR_INVALID_MAC_ADDR;
795 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
796 list->vsi_id = vf->vsi_res->vsi_id;
797 list->num_elements = 1;
798 rte_memcpy(list->list[0].addr, addr->addr_bytes,
799 sizeof(addr->addr_bytes));
801 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
802 args.in_args = cmd_buffer;
803 args.in_args_size = sizeof(cmd_buffer);
804 args.out_buffer = vf->aq_resp;
805 args.out_size = I40E_AQ_BUF_SZ;
806 err = i40evf_execute_vf_cmd(dev, &args);
808 PMD_DRV_LOG(ERR, "fail to execute command "
809 "OP_ADD_ETHER_ADDRESS");
817 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
818 struct ether_addr *addr)
820 struct virtchnl_ether_addr_list *list;
821 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
822 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
823 sizeof(struct virtchnl_ether_addr)];
825 struct vf_cmd_info args;
827 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
828 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
829 addr->addr_bytes[0], addr->addr_bytes[1],
830 addr->addr_bytes[2], addr->addr_bytes[3],
831 addr->addr_bytes[4], addr->addr_bytes[5]);
835 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
836 list->vsi_id = vf->vsi_res->vsi_id;
837 list->num_elements = 1;
838 rte_memcpy(list->list[0].addr, addr->addr_bytes,
839 sizeof(addr->addr_bytes));
841 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
842 args.in_args = cmd_buffer;
843 args.in_args_size = sizeof(cmd_buffer);
844 args.out_buffer = vf->aq_resp;
845 args.out_size = I40E_AQ_BUF_SZ;
846 err = i40evf_execute_vf_cmd(dev, &args);
848 PMD_DRV_LOG(ERR, "fail to execute command "
849 "OP_DEL_ETHER_ADDRESS");
856 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
858 struct rte_eth_dev_data *data = dev->data;
859 struct ether_addr *addr;
861 addr = &data->mac_addrs[index];
863 i40evf_del_mac_addr_by_addr(dev, addr);
867 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
869 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
870 struct virtchnl_queue_select q_stats;
872 struct vf_cmd_info args;
874 memset(&q_stats, 0, sizeof(q_stats));
875 q_stats.vsi_id = vf->vsi_res->vsi_id;
876 args.ops = VIRTCHNL_OP_GET_STATS;
877 args.in_args = (u8 *)&q_stats;
878 args.in_args_size = sizeof(q_stats);
879 args.out_buffer = vf->aq_resp;
880 args.out_size = I40E_AQ_BUF_SZ;
882 err = i40evf_execute_vf_cmd(dev, &args);
884 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
888 *pstats = (struct i40e_eth_stats *)args.out_buffer;
893 i40evf_stat_update_48(uint64_t *offset,
896 if (*stat >= *offset)
897 *stat = *stat - *offset;
899 *stat = (uint64_t)((*stat +
900 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
902 *stat &= I40E_48_BIT_MASK;
906 i40evf_stat_update_32(uint64_t *offset,
909 if (*stat >= *offset)
910 *stat = (uint64_t)(*stat - *offset);
912 *stat = (uint64_t)((*stat +
913 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
917 i40evf_update_stats(struct i40e_vsi *vsi,
918 struct i40e_eth_stats *nes)
920 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
922 i40evf_stat_update_48(&oes->rx_bytes,
924 i40evf_stat_update_48(&oes->rx_unicast,
926 i40evf_stat_update_48(&oes->rx_multicast,
928 i40evf_stat_update_48(&oes->rx_broadcast,
930 i40evf_stat_update_32(&oes->rx_discards,
932 i40evf_stat_update_32(&oes->rx_unknown_protocol,
933 &nes->rx_unknown_protocol);
934 i40evf_stat_update_48(&oes->tx_bytes,
936 i40evf_stat_update_48(&oes->tx_unicast,
938 i40evf_stat_update_48(&oes->tx_multicast,
940 i40evf_stat_update_48(&oes->tx_broadcast,
942 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
943 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
947 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
949 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
950 struct i40e_eth_stats *pstats = NULL;
952 /* read stat values to clear hardware registers */
953 i40evf_query_stats(dev, &pstats);
955 /* set stats offset base on current values */
956 vf->vsi.eth_stats_offset = *pstats;
959 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
960 struct rte_eth_xstat_name *xstats_names,
961 __rte_unused unsigned limit)
965 if (xstats_names != NULL)
966 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
967 snprintf(xstats_names[i].name,
968 sizeof(xstats_names[i].name),
969 "%s", rte_i40evf_stats_strings[i].name);
971 return I40EVF_NB_XSTATS;
974 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
975 struct rte_eth_xstat *xstats, unsigned n)
979 struct i40e_eth_stats *pstats = NULL;
980 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
981 struct i40e_vsi *vsi = &vf->vsi;
983 if (n < I40EVF_NB_XSTATS)
984 return I40EVF_NB_XSTATS;
986 ret = i40evf_query_stats(dev, &pstats);
993 i40evf_update_stats(vsi, pstats);
995 /* loop over xstats array and values from pstats */
996 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
998 xstats[i].value = *(uint64_t *)(((char *)pstats) +
999 rte_i40evf_stats_strings[i].offset);
1002 return I40EVF_NB_XSTATS;
1006 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1008 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1009 struct virtchnl_vlan_filter_list *vlan_list;
1010 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1013 struct vf_cmd_info args;
1015 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1016 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1017 vlan_list->num_elements = 1;
1018 vlan_list->vlan_id[0] = vlanid;
1020 args.ops = VIRTCHNL_OP_ADD_VLAN;
1021 args.in_args = (u8 *)&cmd_buffer;
1022 args.in_args_size = sizeof(cmd_buffer);
1023 args.out_buffer = vf->aq_resp;
1024 args.out_size = I40E_AQ_BUF_SZ;
1025 err = i40evf_execute_vf_cmd(dev, &args);
1027 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1033 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1035 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1036 struct virtchnl_vlan_filter_list *vlan_list;
1037 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1040 struct vf_cmd_info args;
1042 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1043 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1044 vlan_list->num_elements = 1;
1045 vlan_list->vlan_id[0] = vlanid;
1047 args.ops = VIRTCHNL_OP_DEL_VLAN;
1048 args.in_args = (u8 *)&cmd_buffer;
1049 args.in_args_size = sizeof(cmd_buffer);
1050 args.out_buffer = vf->aq_resp;
1051 args.out_size = I40E_AQ_BUF_SZ;
1052 err = i40evf_execute_vf_cmd(dev, &args);
1054 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1059 static const struct rte_pci_id pci_id_i40evf_map[] = {
1060 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1061 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1062 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1063 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1064 { .vendor_id = 0, /* sentinel */ },
1068 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1069 struct rte_eth_link *link)
1071 struct rte_eth_link *dst = &(dev->data->dev_link);
1072 struct rte_eth_link *src = link;
1074 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1075 *(uint64_t *)src) == 0)
1083 i40evf_disable_irq0(struct i40e_hw *hw)
1085 /* Disable all interrupt types */
1086 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1087 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1088 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1089 I40EVF_WRITE_FLUSH(hw);
1094 i40evf_enable_irq0(struct i40e_hw *hw)
1096 /* Enable admin queue interrupt trigger */
1099 i40evf_disable_irq0(hw);
1100 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1101 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1102 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1103 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1105 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1106 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1107 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1108 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1110 I40EVF_WRITE_FLUSH(hw);
1114 i40evf_reset_vf(struct i40e_hw *hw)
1118 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1119 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1123 * After issuing vf reset command to pf, pf won't necessarily
1124 * reset vf, it depends on what state it exactly is. If it's not
1125 * initialized yet, it won't have vf reset since it's in a certain
1126 * state. If not, it will try to reset. Even vf is reset, pf will
1127 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1128 * it to ACTIVE. In this duration, vf may not catch the moment that
1129 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1133 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1134 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1135 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1136 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1137 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1143 if (i >= MAX_RESET_WAIT_CNT) {
1144 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1152 i40evf_init_vf(struct rte_eth_dev *dev)
1155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1158 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1160 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1161 vf->dev_data = dev->data;
1162 err = i40e_set_mac_type(hw);
1164 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1168 i40e_init_adminq_parameter(hw);
1169 err = i40e_init_adminq(hw);
1171 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1175 /* Reset VF and wait until it's complete */
1176 if (i40evf_reset_vf(hw)) {
1177 PMD_INIT_LOG(ERR, "reset NIC failed");
1181 /* VF reset, shutdown admin queue and initialize again */
1182 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1183 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1187 i40e_init_adminq_parameter(hw);
1188 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "init_adminq failed");
1192 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1194 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1197 if (i40evf_check_api_version(dev) != 0) {
1198 PMD_INIT_LOG(ERR, "check_api version failed");
1201 bufsz = sizeof(struct virtchnl_vf_resource) +
1202 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1203 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1205 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1209 if (i40evf_get_vf_resource(dev) != 0) {
1210 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1214 /* got VF config message back from PF, now we can parse it */
1215 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1216 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1217 vf->vsi_res = &vf->vf_res->vsi_res[i];
1221 PMD_INIT_LOG(ERR, "no LAN VSI found");
1225 if (hw->mac.type == I40E_MAC_X722_VF)
1226 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1227 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1229 switch (vf->vsi_res->vsi_type) {
1230 case VIRTCHNL_VSI_SRIOV:
1231 vf->vsi.type = I40E_VSI_SRIOV;
1234 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1237 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1238 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1240 /* Store the MAC address configured by host, or generate random one */
1241 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1242 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1244 eth_random_addr(hw->mac.addr); /* Generate a random one */
1246 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1247 (I40E_ITR_INDEX_DEFAULT <<
1248 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1250 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1251 I40EVF_WRITE_FLUSH(hw);
1256 rte_free(vf->vf_res);
1259 rte_free(vf->aq_resp);
1261 i40e_shutdown_adminq(hw); /* ignore error */
1267 i40evf_uninit_vf(struct rte_eth_dev *dev)
1269 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272 PMD_INIT_FUNC_TRACE();
1274 if (hw->adapter_stopped == 0)
1275 i40evf_dev_close(dev);
1276 rte_free(vf->vf_res);
1278 rte_free(vf->aq_resp);
1285 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1286 __rte_unused uint16_t msglen)
1288 struct virtchnl_pf_event *pf_msg =
1289 (struct virtchnl_pf_event *)msg;
1290 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1292 switch (pf_msg->event) {
1293 case VIRTCHNL_EVENT_RESET_IMPENDING:
1294 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1295 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1298 case VIRTCHNL_EVENT_LINK_CHANGE:
1299 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1300 vf->link_up = pf_msg->event_data.link_event.link_status;
1301 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1303 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1304 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1307 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1313 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1317 struct i40e_arq_event_info info;
1318 uint16_t pending, aq_opc;
1319 enum virtchnl_ops msg_opc;
1320 enum i40e_status_code msg_ret;
1323 info.buf_len = I40E_AQ_BUF_SZ;
1325 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1328 info.msg_buf = vf->aq_resp;
1332 ret = i40e_clean_arq_element(hw, &info, &pending);
1334 if (ret != I40E_SUCCESS) {
1335 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1339 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1340 /* For the message sent from pf to vf, opcode is stored in
1341 * cookie_high of struct i40e_aq_desc, while return error code
1342 * are stored in cookie_low, Which is done by
1343 * i40e_aq_send_msg_to_vf in PF driver.*/
1344 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1345 info.desc.cookie_high);
1346 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1347 info.desc.cookie_low);
1349 case i40e_aqc_opc_send_msg_to_vf:
1350 if (msg_opc == VIRTCHNL_OP_EVENT)
1352 i40evf_handle_pf_event(dev, info.msg_buf,
1355 /* read message and it's expected one */
1356 if (msg_opc == vf->pend_cmd) {
1357 vf->cmd_retval = msg_ret;
1358 /* prevent compiler reordering */
1359 rte_compiler_barrier();
1362 PMD_DRV_LOG(ERR, "command mismatch,"
1363 "expect %u, get %u",
1364 vf->pend_cmd, msg_opc);
1365 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1366 " opcode = %d", msg_opc);
1370 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1378 * Interrupt handler triggered by NIC for handling
1379 * specific interrupt. Only adminq interrupt is processed in VF.
1382 * Pointer to interrupt handle.
1384 * The address of parameter (struct rte_eth_dev *) regsitered before.
1390 i40evf_dev_interrupt_handler(void *param)
1392 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1393 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396 i40evf_disable_irq0(hw);
1398 /* read out interrupt causes */
1399 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1401 /* No interrupt event indicated */
1402 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1403 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1407 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1408 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1409 i40evf_handle_aq_msg(dev);
1412 /* Link Status Change interrupt */
1413 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1414 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1418 i40evf_enable_irq0(hw);
1419 rte_intr_enable(dev->intr_handle);
1423 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1426 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1427 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1429 PMD_INIT_FUNC_TRACE();
1431 /* assign ops func pointer */
1432 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1433 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1434 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1437 * For secondary processes, we don't initialise any further as primary
1438 * has already done this work.
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1441 i40e_set_rx_function(eth_dev);
1442 i40e_set_tx_function(eth_dev);
1445 i40e_set_default_ptype_table(eth_dev);
1446 i40e_set_default_pctype_table(eth_dev);
1447 rte_eth_copy_pci_info(eth_dev, pci_dev);
1448 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1450 hw->vendor_id = pci_dev->id.vendor_id;
1451 hw->device_id = pci_dev->id.device_id;
1452 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1453 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1454 hw->bus.device = pci_dev->addr.devid;
1455 hw->bus.func = pci_dev->addr.function;
1456 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1457 hw->adapter_stopped = 0;
1459 if(i40evf_init_vf(eth_dev) != 0) {
1460 PMD_INIT_LOG(ERR, "Init vf failed");
1464 /* register callback func to eal lib */
1465 rte_intr_callback_register(&pci_dev->intr_handle,
1466 i40evf_dev_interrupt_handler, (void *)eth_dev);
1468 /* enable uio intr after callback register */
1469 rte_intr_enable(&pci_dev->intr_handle);
1471 /* configure and enable device interrupt */
1472 i40evf_enable_irq0(hw);
1475 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1476 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1478 if (eth_dev->data->mac_addrs == NULL) {
1479 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1480 " store MAC addresses",
1481 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1484 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1485 ð_dev->data->mac_addrs[0]);
1491 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1493 PMD_INIT_FUNC_TRACE();
1495 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1498 eth_dev->dev_ops = NULL;
1499 eth_dev->rx_pkt_burst = NULL;
1500 eth_dev->tx_pkt_burst = NULL;
1502 if (i40evf_uninit_vf(eth_dev) != 0) {
1503 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1507 rte_free(eth_dev->data->mac_addrs);
1508 eth_dev->data->mac_addrs = NULL;
1513 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1514 struct rte_pci_device *pci_dev)
1516 return rte_eth_dev_pci_generic_probe(pci_dev,
1517 sizeof(struct i40e_adapter), i40evf_dev_init);
1520 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1522 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1526 * virtual function driver struct
1528 static struct rte_pci_driver rte_i40evf_pmd = {
1529 .id_table = pci_id_i40evf_map,
1530 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1531 .probe = eth_i40evf_pci_probe,
1532 .remove = eth_i40evf_pci_remove,
1535 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1536 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1537 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1540 i40evf_dev_configure(struct rte_eth_dev *dev)
1542 struct i40e_adapter *ad =
1543 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1544 struct rte_eth_conf *conf = &dev->data->dev_conf;
1547 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1548 * allocation or vector Rx preconditions we will reset it.
1550 ad->rx_bulk_alloc_allowed = true;
1551 ad->rx_vec_allowed = true;
1552 ad->tx_simple_allowed = true;
1553 ad->tx_vec_allowed = true;
1555 /* For non-DPDK PF drivers, VF has no ability to disable HW
1556 * CRC strip, and is implicitly enabled by the PF.
1558 if (!conf->rxmode.hw_strip_crc) {
1559 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1560 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1561 (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1562 /* Peer is running non-DPDK PF driver. */
1563 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1568 return i40evf_init_vlan(dev);
1572 i40evf_init_vlan(struct rte_eth_dev *dev)
1574 /* Apply vlan offload setting */
1575 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1577 return I40E_SUCCESS;
1581 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1583 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1585 /* Vlan stripping setting */
1586 if (mask & ETH_VLAN_STRIP_MASK) {
1587 /* Enable or disable VLAN stripping */
1588 if (dev_conf->rxmode.hw_vlan_strip)
1589 i40evf_enable_vlan_strip(dev);
1591 i40evf_disable_vlan_strip(dev);
1596 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1598 struct i40e_rx_queue *rxq;
1600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602 PMD_INIT_FUNC_TRACE();
1604 if (rx_queue_id < dev->data->nb_rx_queues) {
1605 rxq = dev->data->rx_queues[rx_queue_id];
1607 err = i40e_alloc_rx_queue_mbufs(rxq);
1609 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1615 /* Init the RX tail register. */
1616 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1617 I40EVF_WRITE_FLUSH(hw);
1619 /* Ready to switch the queue on */
1620 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1623 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1626 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1633 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1635 struct i40e_rx_queue *rxq;
1638 if (rx_queue_id < dev->data->nb_rx_queues) {
1639 rxq = dev->data->rx_queues[rx_queue_id];
1641 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1644 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1649 i40e_rx_queue_release_mbufs(rxq);
1650 i40e_reset_rx_queue(rxq);
1651 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1658 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1662 PMD_INIT_FUNC_TRACE();
1664 if (tx_queue_id < dev->data->nb_tx_queues) {
1666 /* Ready to switch the queue on */
1667 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1670 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1673 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1680 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1682 struct i40e_tx_queue *txq;
1685 if (tx_queue_id < dev->data->nb_tx_queues) {
1686 txq = dev->data->tx_queues[tx_queue_id];
1688 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1691 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1696 i40e_tx_queue_release_mbufs(txq);
1697 i40e_reset_tx_queue(txq);
1698 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1705 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1710 ret = i40evf_add_vlan(dev, vlan_id);
1712 ret = i40evf_del_vlan(dev,vlan_id);
1718 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721 struct rte_eth_dev_data *dev_data = dev->data;
1722 struct rte_pktmbuf_pool_private *mbp_priv;
1723 uint16_t buf_size, len;
1725 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1726 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1727 I40EVF_WRITE_FLUSH(hw);
1729 /* Calculate the maximum packet length allowed */
1730 mbp_priv = rte_mempool_get_priv(rxq->mp);
1731 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1732 RTE_PKTMBUF_HEADROOM);
1733 rxq->hs_mode = i40e_header_split_none;
1734 rxq->rx_hdr_len = 0;
1735 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1736 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1737 rxq->max_pkt_len = RTE_MIN(len,
1738 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1741 * Check if the jumbo frame and maximum packet length are set correctly
1743 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1744 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1745 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1746 PMD_DRV_LOG(ERR, "maximum packet length must be "
1747 "larger than %u and smaller than %u, as jumbo "
1748 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1749 (uint32_t)I40E_FRAME_SIZE_MAX);
1750 return I40E_ERR_CONFIG;
1753 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1754 rxq->max_pkt_len > ETHER_MAX_LEN) {
1755 PMD_DRV_LOG(ERR, "maximum packet length must be "
1756 "larger than %u and smaller than %u, as jumbo "
1757 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1758 (uint32_t)ETHER_MAX_LEN);
1759 return I40E_ERR_CONFIG;
1763 if (dev_data->dev_conf.rxmode.enable_scatter ||
1764 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1765 dev_data->scattered_rx = 1;
1772 i40evf_rx_init(struct rte_eth_dev *dev)
1774 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1776 int ret = I40E_SUCCESS;
1777 struct i40e_rx_queue **rxq =
1778 (struct i40e_rx_queue **)dev->data->rx_queues;
1780 i40evf_config_rss(vf);
1781 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1782 if (!rxq[i] || !rxq[i]->q_set)
1784 ret = i40evf_rxq_init(dev, rxq[i]);
1785 if (ret != I40E_SUCCESS)
1788 if (ret == I40E_SUCCESS)
1789 i40e_set_rx_function(dev);
1795 i40evf_tx_init(struct rte_eth_dev *dev)
1798 struct i40e_tx_queue **txq =
1799 (struct i40e_tx_queue **)dev->data->tx_queues;
1800 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802 for (i = 0; i < dev->data->nb_tx_queues; i++)
1803 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1805 i40e_set_tx_function(dev);
1809 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1813 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1815 if (!rte_intr_allow_others(intr_handle)) {
1817 I40E_VFINT_DYN_CTL01,
1818 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1819 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1820 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1821 I40EVF_WRITE_FLUSH(hw);
1825 I40EVF_WRITE_FLUSH(hw);
1829 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1833 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1835 if (!rte_intr_allow_others(intr_handle)) {
1836 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1837 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1838 I40EVF_WRITE_FLUSH(hw);
1842 I40EVF_WRITE_FLUSH(hw);
1846 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1849 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1855 msix_intr = intr_handle->intr_vec[queue_id];
1856 if (msix_intr == I40E_MISC_VEC_ID)
1857 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1858 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1859 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1860 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1862 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1865 I40E_VFINT_DYN_CTLN1(msix_intr -
1867 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1868 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1869 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1871 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1873 I40EVF_WRITE_FLUSH(hw);
1875 rte_intr_enable(&pci_dev->intr_handle);
1881 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1883 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1884 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 msix_intr = intr_handle->intr_vec[queue_id];
1889 if (msix_intr == I40E_MISC_VEC_ID)
1890 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1893 I40E_VFINT_DYN_CTLN1(msix_intr -
1897 I40EVF_WRITE_FLUSH(hw);
1903 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1905 struct virtchnl_ether_addr_list *list;
1906 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1911 struct ether_addr *addr;
1912 struct vf_cmd_info args;
1916 len = sizeof(struct virtchnl_ether_addr_list);
1917 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1918 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1920 len += sizeof(struct virtchnl_ether_addr);
1921 if (len >= I40E_AQ_BUF_SZ) {
1927 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1929 PMD_DRV_LOG(ERR, "fail to allocate memory");
1933 for (i = begin; i < next_begin; i++) {
1934 addr = &dev->data->mac_addrs[i];
1935 if (is_zero_ether_addr(addr))
1937 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1938 sizeof(addr->addr_bytes));
1939 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1940 addr->addr_bytes[0], addr->addr_bytes[1],
1941 addr->addr_bytes[2], addr->addr_bytes[3],
1942 addr->addr_bytes[4], addr->addr_bytes[5]);
1945 list->vsi_id = vf->vsi_res->vsi_id;
1946 list->num_elements = j;
1947 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1948 VIRTCHNL_OP_DEL_ETH_ADDR;
1949 args.in_args = (uint8_t *)list;
1950 args.in_args_size = len;
1951 args.out_buffer = vf->aq_resp;
1952 args.out_size = I40E_AQ_BUF_SZ;
1953 err = i40evf_execute_vf_cmd(dev, &args);
1955 PMD_DRV_LOG(ERR, "fail to execute command %s",
1956 add ? "OP_ADD_ETHER_ADDRESS" :
1957 "OP_DEL_ETHER_ADDRESS");
1966 } while (begin < I40E_NUM_MACADDR_MAX);
1970 i40evf_dev_start(struct rte_eth_dev *dev)
1972 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1975 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1976 uint32_t intr_vector = 0;
1978 PMD_INIT_FUNC_TRACE();
1980 hw->adapter_stopped = 0;
1982 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1983 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1984 dev->data->nb_tx_queues);
1986 /* check and configure queue intr-vector mapping */
1987 if (dev->data->dev_conf.intr_conf.rxq != 0) {
1988 intr_vector = dev->data->nb_rx_queues;
1989 if (rte_intr_efd_enable(intr_handle, intr_vector))
1993 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1994 intr_handle->intr_vec =
1995 rte_zmalloc("intr_vec",
1996 dev->data->nb_rx_queues * sizeof(int), 0);
1997 if (!intr_handle->intr_vec) {
1998 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1999 " intr_vec", dev->data->nb_rx_queues);
2004 if (i40evf_rx_init(dev) != 0){
2005 PMD_DRV_LOG(ERR, "failed to do RX init");
2009 i40evf_tx_init(dev);
2011 if (i40evf_configure_vsi_queues(dev) != 0) {
2012 PMD_DRV_LOG(ERR, "configure queues failed");
2015 if (i40evf_config_irq_map(dev)) {
2016 PMD_DRV_LOG(ERR, "config_irq_map failed");
2020 /* Set all mac addrs */
2021 i40evf_add_del_all_mac_addr(dev, TRUE);
2023 if (i40evf_start_queues(dev) != 0) {
2024 PMD_DRV_LOG(ERR, "enable queues failed");
2028 i40evf_enable_queues_intr(dev);
2032 i40evf_add_del_all_mac_addr(dev, FALSE);
2038 i40evf_dev_stop(struct rte_eth_dev *dev)
2040 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2041 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2044 PMD_INIT_FUNC_TRACE();
2046 if (hw->adapter_stopped == 1)
2048 i40evf_stop_queues(dev);
2049 i40evf_disable_queues_intr(dev);
2050 i40e_dev_clear_queues(dev);
2052 /* Clean datapath event and queue/vec mapping */
2053 rte_intr_efd_disable(intr_handle);
2054 if (intr_handle->intr_vec) {
2055 rte_free(intr_handle->intr_vec);
2056 intr_handle->intr_vec = NULL;
2058 /* remove all mac addrs */
2059 i40evf_add_del_all_mac_addr(dev, FALSE);
2060 hw->adapter_stopped = 1;
2065 i40evf_dev_link_update(struct rte_eth_dev *dev,
2066 __rte_unused int wait_to_complete)
2068 struct rte_eth_link new_link;
2069 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2071 * DPDK pf host provide interfacet to acquire link status
2072 * while Linux driver does not
2075 /* Linux driver PF host */
2076 switch (vf->link_speed) {
2077 case I40E_LINK_SPEED_100MB:
2078 new_link.link_speed = ETH_SPEED_NUM_100M;
2080 case I40E_LINK_SPEED_1GB:
2081 new_link.link_speed = ETH_SPEED_NUM_1G;
2083 case I40E_LINK_SPEED_10GB:
2084 new_link.link_speed = ETH_SPEED_NUM_10G;
2086 case I40E_LINK_SPEED_20GB:
2087 new_link.link_speed = ETH_SPEED_NUM_20G;
2089 case I40E_LINK_SPEED_25GB:
2090 new_link.link_speed = ETH_SPEED_NUM_25G;
2092 case I40E_LINK_SPEED_40GB:
2093 new_link.link_speed = ETH_SPEED_NUM_40G;
2096 new_link.link_speed = ETH_SPEED_NUM_100M;
2099 /* full duplex only */
2100 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2101 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2104 i40evf_dev_atomic_write_link_status(dev, &new_link);
2110 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2112 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2115 /* If enabled, just return */
2116 if (vf->promisc_unicast_enabled)
2119 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2121 vf->promisc_unicast_enabled = TRUE;
2125 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2127 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2130 /* If disabled, just return */
2131 if (!vf->promisc_unicast_enabled)
2134 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2136 vf->promisc_unicast_enabled = FALSE;
2140 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2142 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2145 /* If enabled, just return */
2146 if (vf->promisc_multicast_enabled)
2149 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2151 vf->promisc_multicast_enabled = TRUE;
2155 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2157 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2160 /* If enabled, just return */
2161 if (!vf->promisc_multicast_enabled)
2164 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2166 vf->promisc_multicast_enabled = FALSE;
2170 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2172 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2174 memset(dev_info, 0, sizeof(*dev_info));
2175 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2176 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2177 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2178 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2179 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2180 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2181 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2182 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2183 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2184 dev_info->rx_offload_capa =
2185 DEV_RX_OFFLOAD_VLAN_STRIP |
2186 DEV_RX_OFFLOAD_QINQ_STRIP |
2187 DEV_RX_OFFLOAD_IPV4_CKSUM |
2188 DEV_RX_OFFLOAD_UDP_CKSUM |
2189 DEV_RX_OFFLOAD_TCP_CKSUM;
2190 dev_info->tx_offload_capa =
2191 DEV_TX_OFFLOAD_VLAN_INSERT |
2192 DEV_TX_OFFLOAD_QINQ_INSERT |
2193 DEV_TX_OFFLOAD_IPV4_CKSUM |
2194 DEV_TX_OFFLOAD_UDP_CKSUM |
2195 DEV_TX_OFFLOAD_TCP_CKSUM |
2196 DEV_TX_OFFLOAD_SCTP_CKSUM;
2198 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2200 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2201 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2202 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2204 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2208 dev_info->default_txconf = (struct rte_eth_txconf) {
2210 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2211 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2212 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2214 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2215 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2216 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2217 ETH_TXQ_FLAGS_NOOFFLOADS,
2220 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2221 .nb_max = I40E_MAX_RING_DESC,
2222 .nb_min = I40E_MIN_RING_DESC,
2223 .nb_align = I40E_ALIGN_RING_DESC,
2226 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2227 .nb_max = I40E_MAX_RING_DESC,
2228 .nb_min = I40E_MIN_RING_DESC,
2229 .nb_align = I40E_ALIGN_RING_DESC,
2234 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2237 struct i40e_eth_stats *pstats = NULL;
2238 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2239 struct i40e_vsi *vsi = &vf->vsi;
2241 ret = i40evf_query_stats(dev, &pstats);
2243 i40evf_update_stats(vsi, pstats);
2245 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2246 pstats->rx_broadcast;
2247 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2249 stats->imissed = pstats->rx_discards;
2250 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2251 stats->ibytes = pstats->rx_bytes;
2252 stats->obytes = pstats->tx_bytes;
2254 PMD_DRV_LOG(ERR, "Get statistics failed");
2259 i40evf_dev_close(struct rte_eth_dev *dev)
2261 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2263 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2265 i40evf_dev_stop(dev);
2266 i40e_dev_free_queues(dev);
2267 i40evf_reset_vf(hw);
2268 i40e_shutdown_adminq(hw);
2269 /* disable uio intr before callback unregister */
2270 rte_intr_disable(intr_handle);
2272 /* unregister callback func from eal lib */
2273 rte_intr_callback_unregister(intr_handle,
2274 i40evf_dev_interrupt_handler, dev);
2275 i40evf_disable_irq0(hw);
2279 * Reset VF device only to re-initialize resources in PMD layer
2282 i40evf_dev_reset(struct rte_eth_dev *dev)
2286 ret = i40evf_dev_uninit(dev);
2290 ret = i40evf_dev_init(dev);
2296 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2298 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2299 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2305 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2306 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2309 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2313 uint32_t *lut_dw = (uint32_t *)lut;
2314 uint16_t i, lut_size_dw = lut_size / 4;
2316 for (i = 0; i < lut_size_dw; i++)
2317 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2324 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2333 vf = I40E_VSI_TO_VF(vsi);
2334 hw = I40E_VSI_TO_HW(vsi);
2336 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2337 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2340 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2344 uint32_t *lut_dw = (uint32_t *)lut;
2345 uint16_t i, lut_size_dw = lut_size / 4;
2347 for (i = 0; i < lut_size_dw; i++)
2348 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2349 I40EVF_WRITE_FLUSH(hw);
2356 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2357 struct rte_eth_rss_reta_entry64 *reta_conf,
2360 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2362 uint16_t i, idx, shift;
2365 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2366 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2367 "(%d) doesn't match the number of hardware can "
2368 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2372 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2374 PMD_DRV_LOG(ERR, "No memory can be allocated");
2377 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2380 for (i = 0; i < reta_size; i++) {
2381 idx = i / RTE_RETA_GROUP_SIZE;
2382 shift = i % RTE_RETA_GROUP_SIZE;
2383 if (reta_conf[idx].mask & (1ULL << shift))
2384 lut[i] = reta_conf[idx].reta[shift];
2386 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2395 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2396 struct rte_eth_rss_reta_entry64 *reta_conf,
2399 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2400 uint16_t i, idx, shift;
2404 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2405 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2406 "(%d) doesn't match the number of hardware can "
2407 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2411 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2413 PMD_DRV_LOG(ERR, "No memory can be allocated");
2417 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2420 for (i = 0; i < reta_size; i++) {
2421 idx = i / RTE_RETA_GROUP_SIZE;
2422 shift = i % RTE_RETA_GROUP_SIZE;
2423 if (reta_conf[idx].mask & (1ULL << shift))
2424 reta_conf[idx].reta[shift] = lut[i];
2434 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2436 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2437 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2440 if (!key || key_len == 0) {
2441 PMD_DRV_LOG(DEBUG, "No key to be configured");
2443 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2445 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2449 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2450 struct i40e_aqc_get_set_rss_key_data *key_dw =
2451 (struct i40e_aqc_get_set_rss_key_data *)key;
2453 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2455 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2458 uint32_t *hash_key = (uint32_t *)key;
2461 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2462 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2463 I40EVF_WRITE_FLUSH(hw);
2470 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2472 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2473 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2476 if (!key || !key_len)
2479 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2480 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2481 (struct i40e_aqc_get_set_rss_key_data *)key);
2483 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2487 uint32_t *key_dw = (uint32_t *)key;
2490 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2491 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2493 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2499 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2501 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2505 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2506 rss_conf->rss_key_len);
2510 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2511 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2512 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2513 I40EVF_WRITE_FLUSH(hw);
2519 i40evf_disable_rss(struct i40e_vf *vf)
2521 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2523 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2524 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2525 I40EVF_WRITE_FLUSH(hw);
2529 i40evf_config_rss(struct i40e_vf *vf)
2531 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2532 struct rte_eth_rss_conf rss_conf;
2533 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2536 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2537 i40evf_disable_rss(vf);
2538 PMD_DRV_LOG(DEBUG, "RSS not configured");
2542 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2543 /* Fill out the look up table */
2544 for (i = 0, j = 0; i < nb_q; i++, j++) {
2547 lut = (lut << 8) | j;
2549 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2552 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2553 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2554 i40evf_disable_rss(vf);
2555 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2559 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2560 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2561 /* Calculate the default hash key */
2562 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2563 rss_key_default[i] = (uint32_t)rte_rand();
2564 rss_conf.rss_key = (uint8_t *)rss_key_default;
2565 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2569 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2573 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2574 struct rte_eth_rss_conf *rss_conf)
2576 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2581 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2582 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2584 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2585 if (rss_hf != 0) /* Enable RSS */
2591 if (rss_hf == 0) /* Disable RSS */
2594 return i40evf_hw_rss_hash_set(vf, rss_conf);
2598 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2599 struct rte_eth_rss_conf *rss_conf)
2601 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2606 &rss_conf->rss_key_len);
2608 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2609 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2610 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2616 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2618 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2619 struct rte_eth_dev_data *dev_data = vf->dev_data;
2620 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2623 /* check if mtu is within the allowed range */
2624 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2627 /* mtu setting is forbidden if port is start */
2628 if (dev_data->dev_started) {
2629 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2634 if (frame_size > ETHER_MAX_LEN)
2635 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2637 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2639 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2645 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2646 struct ether_addr *mac_addr)
2648 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2650 if (!is_valid_assigned_ether_addr(mac_addr)) {
2651 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2655 if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2658 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2661 i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2663 i40evf_add_mac_addr(dev, mac_addr, 0, 0);