4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstats *xstats, unsigned n);
115 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
116 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
119 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
121 static void i40evf_dev_close(struct rte_eth_dev *dev);
122 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40evf_get_link_status(struct rte_eth_dev *dev,
127 struct rte_eth_link *link);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
157 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
161 /* Default hash key buffer for RSS */
162 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
164 struct rte_i40evf_xstats_name_off {
165 char name[RTE_ETH_XSTATS_NAME_SIZE];
169 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
170 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
171 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
172 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
173 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
174 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
175 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
176 rx_unknown_protocol)},
177 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
178 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
179 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
180 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
185 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
186 sizeof(rte_i40evf_stats_strings[0]))
188 static const struct eth_dev_ops i40evf_eth_dev_ops = {
189 .dev_configure = i40evf_dev_configure,
190 .dev_start = i40evf_dev_start,
191 .dev_stop = i40evf_dev_stop,
192 .promiscuous_enable = i40evf_dev_promiscuous_enable,
193 .promiscuous_disable = i40evf_dev_promiscuous_disable,
194 .allmulticast_enable = i40evf_dev_allmulticast_enable,
195 .allmulticast_disable = i40evf_dev_allmulticast_disable,
196 .link_update = i40evf_dev_link_update,
197 .stats_get = i40evf_dev_stats_get,
198 .xstats_get = i40evf_dev_xstats_get,
199 .xstats_reset = i40evf_dev_xstats_reset,
200 .dev_close = i40evf_dev_close,
201 .dev_infos_get = i40evf_dev_info_get,
202 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
203 .vlan_filter_set = i40evf_vlan_filter_set,
204 .vlan_offload_set = i40evf_vlan_offload_set,
205 .vlan_pvid_set = i40evf_vlan_pvid_set,
206 .rx_queue_start = i40evf_dev_rx_queue_start,
207 .rx_queue_stop = i40evf_dev_rx_queue_stop,
208 .tx_queue_start = i40evf_dev_tx_queue_start,
209 .tx_queue_stop = i40evf_dev_tx_queue_stop,
210 .rx_queue_setup = i40e_dev_rx_queue_setup,
211 .rx_queue_release = i40e_dev_rx_queue_release,
212 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
213 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
214 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
215 .tx_queue_setup = i40e_dev_tx_queue_setup,
216 .tx_queue_release = i40e_dev_tx_queue_release,
217 .mac_addr_add = i40evf_add_mac_addr,
218 .mac_addr_remove = i40evf_del_mac_addr,
219 .reta_update = i40evf_dev_rss_reta_update,
220 .reta_query = i40evf_dev_rss_reta_query,
221 .rss_hash_update = i40evf_dev_rss_hash_update,
222 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
226 * Read data in admin queue to get msg from pf driver
228 static enum i40evf_aq_result
229 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
232 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
233 struct i40e_arq_event_info event;
234 enum i40e_virtchnl_ops opcode;
235 enum i40e_status_code retval;
237 enum i40evf_aq_result result = I40EVF_MSG_NON;
239 event.buf_len = data->buf_len;
240 event.msg_buf = data->msg;
241 ret = i40e_clean_arq_element(hw, &event, NULL);
242 /* Can't read any msg from adminQ */
244 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
245 result = I40EVF_MSG_ERR;
249 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
250 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
252 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
253 struct i40e_virtchnl_pf_event *vpe =
254 (struct i40e_virtchnl_pf_event *)event.msg_buf;
256 result = I40EVF_MSG_SYS;
257 switch (vpe->event) {
258 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
260 vpe->event_data.link_event.link_status;
262 vpe->event_data.link_event.link_speed;
263 vf->pend_msg |= PFMSG_LINK_CHANGE;
264 PMD_DRV_LOG(INFO, "Link status update:%s",
265 vf->link_up ? "up" : "down");
267 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
269 vf->pend_msg |= PFMSG_RESET_IMPENDING;
270 PMD_DRV_LOG(INFO, "vf is reseting");
272 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
273 vf->dev_closed = true;
274 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
275 PMD_DRV_LOG(INFO, "PF driver closed");
278 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
279 __func__, vpe->event);
282 /* async reply msg on command issued by vf previously */
283 result = I40EVF_MSG_CMD;
284 /* Actual data length read from PF */
285 data->msg_len = event.msg_len;
288 data->result = retval;
295 * clear current command. Only call in case execute
296 * _atomic_set_cmd successfully.
299 _clear_cmd(struct i40e_vf *vf)
302 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
306 * Check there is pending cmd in execution. If none, set new command.
309 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
311 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
312 I40E_VIRTCHNL_OP_UNKNOWN, ops);
315 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
320 #define MAX_TRY_TIMES 200
321 #define ASQ_DELAY_MS 10
324 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
326 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
327 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
328 struct i40evf_arq_msg_info info;
329 enum i40evf_aq_result ret;
333 if (_atomic_set_cmd(vf, args->ops))
336 info.msg = args->out_buffer;
337 info.buf_len = args->out_size;
338 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
339 info.result = I40E_SUCCESS;
341 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
342 args->in_args, args->in_args_size, NULL);
344 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
350 case I40E_VIRTCHNL_OP_RESET_VF:
351 /*no need to process in this function */
353 case I40E_VIRTCHNL_OP_VERSION:
354 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
355 /* for init adminq commands, need to poll the response */
357 ret = i40evf_read_pfmsg(dev, &info);
358 if (ret == I40EVF_MSG_CMD) {
361 } else if (ret == I40EVF_MSG_ERR) {
365 rte_delay_ms(ASQ_DELAY_MS);
366 /* If don't read msg or read sys event, continue */
367 } while (i++ < MAX_TRY_TIMES);
372 /* for other adminq in running time, waiting the cmd done flag */
374 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
378 rte_delay_ms(ASQ_DELAY_MS);
379 /* If don't read msg or read sys event, continue */
380 } while (i++ < MAX_TRY_TIMES);
384 return err | vf->cmd_retval;
388 * Check API version with sync wait until version read or fail from admin queue
391 i40evf_check_api_version(struct rte_eth_dev *dev)
393 struct i40e_virtchnl_version_info version, *pver;
395 struct vf_cmd_info args;
396 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
398 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
399 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
401 args.ops = I40E_VIRTCHNL_OP_VERSION;
402 args.in_args = (uint8_t *)&version;
403 args.in_args_size = sizeof(version);
404 args.out_buffer = vf->aq_resp;
405 args.out_size = I40E_AQ_BUF_SZ;
407 err = i40evf_execute_vf_cmd(dev, &args);
409 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
413 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
414 vf->version_major = pver->major;
415 vf->version_minor = pver->minor;
416 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
417 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
418 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
419 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
420 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
422 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
423 vf->version_major, vf->version_minor,
424 I40E_VIRTCHNL_VERSION_MAJOR,
425 I40E_VIRTCHNL_VERSION_MINOR);
433 i40evf_get_vf_resource(struct rte_eth_dev *dev)
435 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
436 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
438 struct vf_cmd_info args;
441 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
442 args.out_buffer = vf->aq_resp;
443 args.out_size = I40E_AQ_BUF_SZ;
445 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
446 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
447 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
448 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
449 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
450 args.in_args = (uint8_t *)∩︀
451 args.in_args_size = sizeof(caps);
454 args.in_args_size = 0;
456 err = i40evf_execute_vf_cmd(dev, &args);
459 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
463 len = sizeof(struct i40e_virtchnl_vf_resource) +
464 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
466 (void)rte_memcpy(vf->vf_res, args.out_buffer,
467 RTE_MIN(args.out_size, len));
468 i40e_vf_parse_hw_config(hw, vf->vf_res);
474 i40evf_config_promisc(struct rte_eth_dev *dev,
476 bool enable_multicast)
478 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
480 struct vf_cmd_info args;
481 struct i40e_virtchnl_promisc_info promisc;
484 promisc.vsi_id = vf->vsi_res->vsi_id;
487 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
489 if (enable_multicast)
490 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
492 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
493 args.in_args = (uint8_t *)&promisc;
494 args.in_args_size = sizeof(promisc);
495 args.out_buffer = vf->aq_resp;
496 args.out_size = I40E_AQ_BUF_SZ;
498 err = i40evf_execute_vf_cmd(dev, &args);
501 PMD_DRV_LOG(ERR, "fail to execute command "
502 "CONFIG_PROMISCUOUS_MODE");
506 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
508 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
509 bool enable_vlan_strip)
511 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
513 struct vf_cmd_info args;
514 struct i40e_virtchnl_vlan_offload_info offload;
516 offload.vsi_id = vf->vsi_res->vsi_id;
517 offload.enable_vlan_strip = enable_vlan_strip;
519 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
520 args.in_args = (uint8_t *)&offload;
521 args.in_args_size = sizeof(offload);
522 args.out_buffer = vf->aq_resp;
523 args.out_size = I40E_AQ_BUF_SZ;
525 err = i40evf_execute_vf_cmd(dev, &args);
527 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
533 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
534 struct i40e_vsi_vlan_pvid_info *info)
536 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
538 struct vf_cmd_info args;
539 struct i40e_virtchnl_pvid_info tpid_info;
542 PMD_DRV_LOG(ERR, "invalid parameters");
543 return I40E_ERR_PARAM;
546 memset(&tpid_info, 0, sizeof(tpid_info));
547 tpid_info.vsi_id = vf->vsi_res->vsi_id;
548 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
550 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
551 args.in_args = (uint8_t *)&tpid_info;
552 args.in_args_size = sizeof(tpid_info);
553 args.out_buffer = vf->aq_resp;
554 args.out_size = I40E_AQ_BUF_SZ;
556 err = i40evf_execute_vf_cmd(dev, &args);
558 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
564 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
568 struct i40e_tx_queue *txq)
570 txq_info->vsi_id = vsi_id;
571 txq_info->queue_id = queue_id;
572 if (queue_id < nb_txq) {
573 txq_info->ring_len = txq->nb_tx_desc;
574 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
579 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
583 uint32_t max_pkt_size,
584 struct i40e_rx_queue *rxq)
586 rxq_info->vsi_id = vsi_id;
587 rxq_info->queue_id = queue_id;
588 rxq_info->max_pkt_size = max_pkt_size;
589 if (queue_id < nb_rxq) {
590 rxq_info->ring_len = rxq->nb_rx_desc;
591 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
592 rxq_info->databuffer_size =
593 (rte_pktmbuf_data_room_size(rxq->mp) -
594 RTE_PKTMBUF_HEADROOM);
598 /* It configures VSI queues to co-work with Linux PF host */
600 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
602 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
603 struct i40e_rx_queue **rxq =
604 (struct i40e_rx_queue **)dev->data->rx_queues;
605 struct i40e_tx_queue **txq =
606 (struct i40e_tx_queue **)dev->data->tx_queues;
607 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
608 struct i40e_virtchnl_queue_pair_info *vc_qpi;
609 struct vf_cmd_info args;
610 uint16_t i, nb_qp = vf->num_queue_pairs;
611 const uint32_t size =
612 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
616 memset(buff, 0, sizeof(buff));
617 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
618 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
619 vc_vqci->num_queue_pairs = nb_qp;
621 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
622 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
623 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
624 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
625 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
626 vf->max_pkt_len, rxq[i]);
628 memset(&args, 0, sizeof(args));
629 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
630 args.in_args = (uint8_t *)vc_vqci;
631 args.in_args_size = size;
632 args.out_buffer = vf->aq_resp;
633 args.out_size = I40E_AQ_BUF_SZ;
634 ret = i40evf_execute_vf_cmd(dev, &args);
636 PMD_DRV_LOG(ERR, "Failed to execute command of "
637 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
642 /* It configures VSI queues to co-work with DPDK PF host */
644 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
646 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
647 struct i40e_rx_queue **rxq =
648 (struct i40e_rx_queue **)dev->data->rx_queues;
649 struct i40e_tx_queue **txq =
650 (struct i40e_tx_queue **)dev->data->tx_queues;
651 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
652 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
653 struct vf_cmd_info args;
654 uint16_t i, nb_qp = vf->num_queue_pairs;
655 const uint32_t size =
656 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
660 memset(buff, 0, sizeof(buff));
661 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
662 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
663 vc_vqcei->num_queue_pairs = nb_qp;
664 vc_qpei = vc_vqcei->qpair;
665 for (i = 0; i < nb_qp; i++, vc_qpei++) {
666 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
667 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
668 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
669 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
670 vf->max_pkt_len, rxq[i]);
671 if (i < dev->data->nb_rx_queues)
673 * It adds extra info for configuring VSI queues, which
674 * is needed to enable the configurable crc stripping
677 vc_qpei->rxq_ext.crcstrip =
678 dev->data->dev_conf.rxmode.hw_strip_crc;
680 memset(&args, 0, sizeof(args));
682 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
683 args.in_args = (uint8_t *)vc_vqcei;
684 args.in_args_size = size;
685 args.out_buffer = vf->aq_resp;
686 args.out_size = I40E_AQ_BUF_SZ;
687 ret = i40evf_execute_vf_cmd(dev, &args);
689 PMD_DRV_LOG(ERR, "Failed to execute command of "
690 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
696 i40evf_configure_queues(struct rte_eth_dev *dev)
698 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
700 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
701 /* To support DPDK PF host */
702 return i40evf_configure_vsi_queues_ext(dev);
704 /* To support Linux PF host */
705 return i40evf_configure_vsi_queues(dev);
709 i40evf_config_irq_map(struct rte_eth_dev *dev)
711 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
712 struct vf_cmd_info args;
713 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
714 sizeof(struct i40e_virtchnl_vector_map)];
715 struct i40e_virtchnl_irq_map_info *map_info;
716 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
720 if (rte_intr_allow_others(intr_handle)) {
721 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
722 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
724 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
726 vector_id = I40E_MISC_VEC_ID;
729 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
730 map_info->num_vectors = 1;
731 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
732 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
733 /* Alway use default dynamic MSIX interrupt */
734 map_info->vecmap[0].vector_id = vector_id;
735 /* Don't map any tx queue */
736 map_info->vecmap[0].txq_map = 0;
737 map_info->vecmap[0].rxq_map = 0;
738 for (i = 0; i < dev->data->nb_rx_queues; i++) {
739 map_info->vecmap[0].rxq_map |= 1 << i;
740 if (rte_intr_dp_is_en(intr_handle))
741 intr_handle->intr_vec[i] = vector_id;
744 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
745 args.in_args = (u8 *)cmd_buffer;
746 args.in_args_size = sizeof(cmd_buffer);
747 args.out_buffer = vf->aq_resp;
748 args.out_size = I40E_AQ_BUF_SZ;
749 err = i40evf_execute_vf_cmd(dev, &args);
751 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
757 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
760 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
761 struct i40e_virtchnl_queue_select queue_select;
763 struct vf_cmd_info args;
764 memset(&queue_select, 0, sizeof(queue_select));
765 queue_select.vsi_id = vf->vsi_res->vsi_id;
768 queue_select.rx_queues |= 1 << qid;
770 queue_select.tx_queues |= 1 << qid;
773 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
775 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
776 args.in_args = (u8 *)&queue_select;
777 args.in_args_size = sizeof(queue_select);
778 args.out_buffer = vf->aq_resp;
779 args.out_size = I40E_AQ_BUF_SZ;
780 err = i40evf_execute_vf_cmd(dev, &args);
782 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
783 isrx ? "RX" : "TX", qid, on ? "on" : "off");
789 i40evf_start_queues(struct rte_eth_dev *dev)
791 struct rte_eth_dev_data *dev_data = dev->data;
793 struct i40e_rx_queue *rxq;
794 struct i40e_tx_queue *txq;
796 for (i = 0; i < dev->data->nb_rx_queues; i++) {
797 rxq = dev_data->rx_queues[i];
798 if (rxq->rx_deferred_start)
800 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
801 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
806 for (i = 0; i < dev->data->nb_tx_queues; i++) {
807 txq = dev_data->tx_queues[i];
808 if (txq->tx_deferred_start)
810 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
811 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
820 i40evf_stop_queues(struct rte_eth_dev *dev)
824 /* Stop TX queues first */
825 for (i = 0; i < dev->data->nb_tx_queues; i++) {
826 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
827 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
832 /* Then stop RX queues */
833 for (i = 0; i < dev->data->nb_rx_queues; i++) {
834 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
835 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
844 i40evf_add_mac_addr(struct rte_eth_dev *dev,
845 struct ether_addr *addr,
846 __rte_unused uint32_t index,
847 __rte_unused uint32_t pool)
849 struct i40e_virtchnl_ether_addr_list *list;
850 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
851 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
852 sizeof(struct i40e_virtchnl_ether_addr)];
854 struct vf_cmd_info args;
856 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
857 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
858 addr->addr_bytes[0], addr->addr_bytes[1],
859 addr->addr_bytes[2], addr->addr_bytes[3],
860 addr->addr_bytes[4], addr->addr_bytes[5]);
864 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
865 list->vsi_id = vf->vsi_res->vsi_id;
866 list->num_elements = 1;
867 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
868 sizeof(addr->addr_bytes));
870 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
871 args.in_args = cmd_buffer;
872 args.in_args_size = sizeof(cmd_buffer);
873 args.out_buffer = vf->aq_resp;
874 args.out_size = I40E_AQ_BUF_SZ;
875 err = i40evf_execute_vf_cmd(dev, &args);
877 PMD_DRV_LOG(ERR, "fail to execute command "
878 "OP_ADD_ETHER_ADDRESS");
884 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
886 struct i40e_virtchnl_ether_addr_list *list;
887 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
888 struct rte_eth_dev_data *data = dev->data;
889 struct ether_addr *addr;
890 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
891 sizeof(struct i40e_virtchnl_ether_addr)];
893 struct vf_cmd_info args;
895 addr = &(data->mac_addrs[index]);
897 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
898 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
899 addr->addr_bytes[0], addr->addr_bytes[1],
900 addr->addr_bytes[2], addr->addr_bytes[3],
901 addr->addr_bytes[4], addr->addr_bytes[5]);
905 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
906 list->vsi_id = vf->vsi_res->vsi_id;
907 list->num_elements = 1;
908 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
909 sizeof(addr->addr_bytes));
911 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
912 args.in_args = cmd_buffer;
913 args.in_args_size = sizeof(cmd_buffer);
914 args.out_buffer = vf->aq_resp;
915 args.out_size = I40E_AQ_BUF_SZ;
916 err = i40evf_execute_vf_cmd(dev, &args);
918 PMD_DRV_LOG(ERR, "fail to execute command "
919 "OP_DEL_ETHER_ADDRESS");
924 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
926 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
927 struct i40e_virtchnl_queue_select q_stats;
929 struct vf_cmd_info args;
931 memset(&q_stats, 0, sizeof(q_stats));
932 q_stats.vsi_id = vf->vsi_res->vsi_id;
933 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
934 args.in_args = (u8 *)&q_stats;
935 args.in_args_size = sizeof(q_stats);
936 args.out_buffer = vf->aq_resp;
937 args.out_size = I40E_AQ_BUF_SZ;
939 err = i40evf_execute_vf_cmd(dev, &args);
941 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
945 *pstats = (struct i40e_eth_stats *)args.out_buffer;
950 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
953 struct i40e_eth_stats *pstats = NULL;
955 ret = i40evf_update_stats(dev, &pstats);
959 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
960 pstats->rx_broadcast;
961 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
963 stats->ierrors = pstats->rx_discards;
964 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
965 stats->ibytes = pstats->rx_bytes;
966 stats->obytes = pstats->tx_bytes;
972 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
974 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
975 struct i40e_eth_stats *pstats = NULL;
977 /* read stat values to clear hardware registers */
978 i40evf_update_stats(dev, &pstats);
980 /* set stats offset base on current values */
981 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
984 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
985 struct rte_eth_xstats *xstats, unsigned n)
989 struct i40e_eth_stats *pstats = NULL;
991 if (n < I40EVF_NB_XSTATS)
992 return I40EVF_NB_XSTATS;
994 ret = i40evf_update_stats(dev, &pstats);
1001 /* loop over xstats array and values from pstats */
1002 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1003 snprintf(xstats[i].name, sizeof(xstats[i].name),
1004 "%s", rte_i40evf_stats_strings[i].name);
1005 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1006 rte_i40evf_stats_strings[i].offset);
1009 return I40EVF_NB_XSTATS;
1013 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1015 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1016 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1017 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1020 struct vf_cmd_info args;
1022 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1023 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1024 vlan_list->num_elements = 1;
1025 vlan_list->vlan_id[0] = vlanid;
1027 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1028 args.in_args = (u8 *)&cmd_buffer;
1029 args.in_args_size = sizeof(cmd_buffer);
1030 args.out_buffer = vf->aq_resp;
1031 args.out_size = I40E_AQ_BUF_SZ;
1032 err = i40evf_execute_vf_cmd(dev, &args);
1034 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1040 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1042 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1043 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1044 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1047 struct vf_cmd_info args;
1049 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1050 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1051 vlan_list->num_elements = 1;
1052 vlan_list->vlan_id[0] = vlanid;
1054 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1055 args.in_args = (u8 *)&cmd_buffer;
1056 args.in_args_size = sizeof(cmd_buffer);
1057 args.out_buffer = vf->aq_resp;
1058 args.out_size = I40E_AQ_BUF_SZ;
1059 err = i40evf_execute_vf_cmd(dev, &args);
1061 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1067 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1069 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1071 struct vf_cmd_info args;
1072 struct rte_eth_link *new_link;
1074 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1075 args.in_args = NULL;
1076 args.in_args_size = 0;
1077 args.out_buffer = vf->aq_resp;
1078 args.out_size = I40E_AQ_BUF_SZ;
1079 err = i40evf_execute_vf_cmd(dev, &args);
1081 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1085 new_link = (struct rte_eth_link *)args.out_buffer;
1086 (void)rte_memcpy(link, new_link, sizeof(*link));
1091 static const struct rte_pci_id pci_id_i40evf_map[] = {
1092 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1093 #include "rte_pci_dev_ids.h"
1094 { .vendor_id = 0, /* sentinel */ },
1098 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1099 struct rte_eth_link *link)
1101 struct rte_eth_link *dst = &(dev->data->dev_link);
1102 struct rte_eth_link *src = link;
1104 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1105 *(uint64_t *)src) == 0)
1113 i40evf_disable_irq0(struct i40e_hw *hw)
1115 /* Disable all interrupt types */
1116 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1117 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1118 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1119 I40EVF_WRITE_FLUSH(hw);
1124 i40evf_enable_irq0(struct i40e_hw *hw)
1126 /* Enable admin queue interrupt trigger */
1129 i40evf_disable_irq0(hw);
1130 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1131 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1132 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1133 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1135 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1136 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1137 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1138 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1140 I40EVF_WRITE_FLUSH(hw);
1144 i40evf_reset_vf(struct i40e_hw *hw)
1148 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1149 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1153 * After issuing vf reset command to pf, pf won't necessarily
1154 * reset vf, it depends on what state it exactly is. If it's not
1155 * initialized yet, it won't have vf reset since it's in a certain
1156 * state. If not, it will try to reset. Even vf is reset, pf will
1157 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1158 * it to ACTIVE. In this duration, vf may not catch the moment that
1159 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1163 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1164 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1165 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1166 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1167 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1173 if (i >= MAX_RESET_WAIT_CNT) {
1174 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1182 i40evf_init_vf(struct rte_eth_dev *dev)
1185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1187 struct ether_addr *p_mac_addr;
1189 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1191 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1192 vf->dev_data = dev->data;
1193 err = i40e_set_mac_type(hw);
1195 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1199 i40e_init_adminq_parameter(hw);
1200 err = i40e_init_adminq(hw);
1202 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1206 /* Reset VF and wait until it's complete */
1207 if (i40evf_reset_vf(hw)) {
1208 PMD_INIT_LOG(ERR, "reset NIC failed");
1212 /* VF reset, shutdown admin queue and initialize again */
1213 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1214 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1218 i40e_init_adminq_parameter(hw);
1219 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1220 PMD_INIT_LOG(ERR, "init_adminq failed");
1223 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1225 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1228 if (i40evf_check_api_version(dev) != 0) {
1229 PMD_INIT_LOG(ERR, "check_api version failed");
1232 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1233 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1234 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1236 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1240 if (i40evf_get_vf_resource(dev) != 0) {
1241 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1245 /* got VF config message back from PF, now we can parse it */
1246 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1247 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1248 vf->vsi_res = &vf->vf_res->vsi_res[i];
1252 PMD_INIT_LOG(ERR, "no LAN VSI found");
1256 if (hw->mac.type == I40E_MAC_X722_VF)
1257 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1258 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1259 vf->vsi.type = vf->vsi_res->vsi_type;
1260 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1261 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1263 /* Store the MAC address configured by host, or generate random one */
1264 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1265 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1266 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1268 eth_random_addr(hw->mac.addr); /* Generate a random one */
1270 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1271 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1272 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1273 (I40E_ITR_INDEX_DEFAULT <<
1274 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1276 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1277 I40EVF_WRITE_FLUSH(hw);
1283 rte_free(vf->vf_res);
1285 i40e_shutdown_adminq(hw); /* ignore error */
1291 i40evf_uninit_vf(struct rte_eth_dev *dev)
1293 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1296 PMD_INIT_FUNC_TRACE();
1298 if (hw->adapter_stopped == 0)
1299 i40evf_dev_close(dev);
1300 rte_free(vf->vf_res);
1302 rte_free(vf->aq_resp);
1309 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1311 __rte_unused uint16_t msglen)
1313 struct i40e_virtchnl_pf_event *pf_msg =
1314 (struct i40e_virtchnl_pf_event *)msg;
1315 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1317 switch (pf_msg->event) {
1318 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1319 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1320 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
1322 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1323 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1324 vf->link_up = pf_msg->event_data.link_event.link_status;
1325 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1327 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1328 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1331 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1337 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1341 struct i40e_arq_event_info info;
1342 struct i40e_virtchnl_msg *v_msg;
1343 uint16_t pending, opcode;
1346 info.buf_len = I40E_AQ_BUF_SZ;
1348 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1351 info.msg_buf = vf->aq_resp;
1352 v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1356 ret = i40e_clean_arq_element(hw, &info, &pending);
1358 if (ret != I40E_SUCCESS) {
1359 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1363 opcode = rte_le_to_cpu_16(info.desc.opcode);
1366 case i40e_aqc_opc_send_msg_to_vf:
1367 if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1369 i40evf_handle_pf_event(dev, info.msg_buf,
1372 /* read message and it's expected one */
1373 if (v_msg->v_opcode == vf->pend_cmd) {
1374 vf->cmd_retval = v_msg->v_retval;
1375 /* prevent compiler reordering */
1376 rte_compiler_barrier();
1379 PMD_DRV_LOG(ERR, "command mismatch,"
1380 "expect %u, get %u",
1381 vf->pend_cmd, v_msg->v_opcode);
1382 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1383 " opcode = %d\n", v_msg->v_opcode);
1387 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1395 * Interrupt handler triggered by NIC for handling
1396 * specific interrupt. Only adminq interrupt is processed in VF.
1399 * Pointer to interrupt handle.
1401 * The address of parameter (struct rte_eth_dev *) regsitered before.
1407 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1410 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1411 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414 i40evf_disable_irq0(hw);
1416 /* read out interrupt causes */
1417 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1419 /* No interrupt event indicated */
1420 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1421 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1425 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1426 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1427 i40evf_handle_aq_msg(dev);
1430 /* Link Status Change interrupt */
1431 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1432 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1436 i40evf_enable_irq0(hw);
1437 rte_intr_enable(&dev->pci_dev->intr_handle);
1441 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1443 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1444 eth_dev->data->dev_private);
1445 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1447 PMD_INIT_FUNC_TRACE();
1449 /* assign ops func pointer */
1450 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1451 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1452 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1455 * For secondary processes, we don't initialise any further as primary
1456 * has already done this work.
1458 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459 i40e_set_rx_function(eth_dev);
1460 i40e_set_tx_function(eth_dev);
1464 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1466 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1467 hw->device_id = eth_dev->pci_dev->id.device_id;
1468 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1469 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1470 hw->bus.device = eth_dev->pci_dev->addr.devid;
1471 hw->bus.func = eth_dev->pci_dev->addr.function;
1472 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1473 hw->adapter_stopped = 0;
1475 if(i40evf_init_vf(eth_dev) != 0) {
1476 PMD_INIT_LOG(ERR, "Init vf failed");
1480 /* register callback func to eal lib */
1481 rte_intr_callback_register(&pci_dev->intr_handle,
1482 i40evf_dev_interrupt_handler, (void *)eth_dev);
1484 /* enable uio intr after callback register */
1485 rte_intr_enable(&pci_dev->intr_handle);
1487 /* configure and enable device interrupt */
1488 i40evf_enable_irq0(hw);
1491 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1492 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1494 if (eth_dev->data->mac_addrs == NULL) {
1495 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1496 " store MAC addresses",
1497 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1500 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1501 ð_dev->data->mac_addrs[0]);
1507 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1509 PMD_INIT_FUNC_TRACE();
1511 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1514 eth_dev->dev_ops = NULL;
1515 eth_dev->rx_pkt_burst = NULL;
1516 eth_dev->tx_pkt_burst = NULL;
1518 if (i40evf_uninit_vf(eth_dev) != 0) {
1519 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1523 rte_free(eth_dev->data->mac_addrs);
1524 eth_dev->data->mac_addrs = NULL;
1529 * virtual function driver struct
1531 static struct eth_driver rte_i40evf_pmd = {
1533 .name = "rte_i40evf_pmd",
1534 .id_table = pci_id_i40evf_map,
1535 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1537 .eth_dev_init = i40evf_dev_init,
1538 .eth_dev_uninit = i40evf_dev_uninit,
1539 .dev_private_size = sizeof(struct i40e_adapter),
1543 * VF Driver initialization routine.
1544 * Invoked one at EAL init time.
1545 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1548 rte_i40evf_pmd_init(const char *name __rte_unused,
1549 const char *params __rte_unused)
1551 PMD_INIT_FUNC_TRACE();
1553 rte_eth_driver_register(&rte_i40evf_pmd);
1558 static struct rte_driver rte_i40evf_driver = {
1560 .init = rte_i40evf_pmd_init,
1563 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1566 i40evf_dev_configure(struct rte_eth_dev *dev)
1568 struct i40e_adapter *ad =
1569 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1571 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1572 * allocation or vector Rx preconditions we will reset it.
1574 ad->rx_bulk_alloc_allowed = true;
1575 ad->rx_vec_allowed = true;
1576 ad->tx_simple_allowed = true;
1577 ad->tx_vec_allowed = true;
1579 return i40evf_init_vlan(dev);
1583 i40evf_init_vlan(struct rte_eth_dev *dev)
1585 struct rte_eth_dev_data *data = dev->data;
1588 /* Apply vlan offload setting */
1589 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1591 /* Apply pvid setting */
1592 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1593 data->dev_conf.txmode.hw_vlan_insert_pvid);
1598 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1600 bool enable_vlan_strip = 0;
1601 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1602 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1604 /* Linux pf host doesn't support vlan offload yet */
1605 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1606 /* Vlan stripping setting */
1607 if (mask & ETH_VLAN_STRIP_MASK) {
1608 /* Enable or disable VLAN stripping */
1609 if (dev_conf->rxmode.hw_vlan_strip)
1610 enable_vlan_strip = 1;
1612 enable_vlan_strip = 0;
1614 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1620 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1622 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1623 struct i40e_vsi_vlan_pvid_info info;
1624 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1626 memset(&info, 0, sizeof(info));
1629 /* Linux pf host don't support vlan offload yet */
1630 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1632 info.config.pvid = pvid;
1634 info.config.reject.tagged =
1635 dev_conf->txmode.hw_vlan_reject_tagged;
1636 info.config.reject.untagged =
1637 dev_conf->txmode.hw_vlan_reject_untagged;
1639 return i40evf_config_vlan_pvid(dev, &info);
1646 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1648 struct i40e_rx_queue *rxq;
1650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652 PMD_INIT_FUNC_TRACE();
1654 if (rx_queue_id < dev->data->nb_rx_queues) {
1655 rxq = dev->data->rx_queues[rx_queue_id];
1657 err = i40e_alloc_rx_queue_mbufs(rxq);
1659 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1665 /* Init the RX tail register. */
1666 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1667 I40EVF_WRITE_FLUSH(hw);
1669 /* Ready to switch the queue on */
1670 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1673 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1676 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1683 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1685 struct i40e_rx_queue *rxq;
1688 if (rx_queue_id < dev->data->nb_rx_queues) {
1689 rxq = dev->data->rx_queues[rx_queue_id];
1691 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1694 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1699 i40e_rx_queue_release_mbufs(rxq);
1700 i40e_reset_rx_queue(rxq);
1701 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1708 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1712 PMD_INIT_FUNC_TRACE();
1714 if (tx_queue_id < dev->data->nb_tx_queues) {
1716 /* Ready to switch the queue on */
1717 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1720 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1723 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1730 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1732 struct i40e_tx_queue *txq;
1735 if (tx_queue_id < dev->data->nb_tx_queues) {
1736 txq = dev->data->tx_queues[tx_queue_id];
1738 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1741 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1746 i40e_tx_queue_release_mbufs(txq);
1747 i40e_reset_tx_queue(txq);
1748 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1755 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1760 ret = i40evf_add_vlan(dev, vlan_id);
1762 ret = i40evf_del_vlan(dev,vlan_id);
1768 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771 struct rte_eth_dev_data *dev_data = dev->data;
1772 struct rte_pktmbuf_pool_private *mbp_priv;
1773 uint16_t buf_size, len;
1775 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1776 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1777 I40EVF_WRITE_FLUSH(hw);
1779 /* Calculate the maximum packet length allowed */
1780 mbp_priv = rte_mempool_get_priv(rxq->mp);
1781 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1782 RTE_PKTMBUF_HEADROOM);
1783 rxq->hs_mode = i40e_header_split_none;
1784 rxq->rx_hdr_len = 0;
1785 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1786 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1787 rxq->max_pkt_len = RTE_MIN(len,
1788 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1791 * Check if the jumbo frame and maximum packet length are set correctly
1793 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1794 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1795 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1796 PMD_DRV_LOG(ERR, "maximum packet length must be "
1797 "larger than %u and smaller than %u, as jumbo "
1798 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1799 (uint32_t)I40E_FRAME_SIZE_MAX);
1800 return I40E_ERR_CONFIG;
1803 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1804 rxq->max_pkt_len > ETHER_MAX_LEN) {
1805 PMD_DRV_LOG(ERR, "maximum packet length must be "
1806 "larger than %u and smaller than %u, as jumbo "
1807 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1808 (uint32_t)ETHER_MAX_LEN);
1809 return I40E_ERR_CONFIG;
1813 if (dev_data->dev_conf.rxmode.enable_scatter ||
1814 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1815 dev_data->scattered_rx = 1;
1822 i40evf_rx_init(struct rte_eth_dev *dev)
1824 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1826 int ret = I40E_SUCCESS;
1827 struct i40e_rx_queue **rxq =
1828 (struct i40e_rx_queue **)dev->data->rx_queues;
1830 i40evf_config_rss(vf);
1831 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1832 if (!rxq[i] || !rxq[i]->q_set)
1834 ret = i40evf_rxq_init(dev, rxq[i]);
1835 if (ret != I40E_SUCCESS)
1838 if (ret == I40E_SUCCESS)
1839 i40e_set_rx_function(dev);
1845 i40evf_tx_init(struct rte_eth_dev *dev)
1848 struct i40e_tx_queue **txq =
1849 (struct i40e_tx_queue **)dev->data->tx_queues;
1850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852 for (i = 0; i < dev->data->nb_tx_queues; i++)
1853 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1855 i40e_set_tx_function(dev);
1859 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1861 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1862 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1865 if (!rte_intr_allow_others(intr_handle)) {
1867 I40E_VFINT_DYN_CTL01,
1868 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1869 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1870 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1871 I40EVF_WRITE_FLUSH(hw);
1875 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1876 /* To support DPDK PF host */
1878 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1879 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1880 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1881 /* If host driver is kernel driver, do nothing.
1882 * Interrupt 0 is used for rx packets, but don't set
1883 * I40E_VFINT_DYN_CTL01,
1884 * because it is already done in i40evf_enable_irq0.
1887 I40EVF_WRITE_FLUSH(hw);
1891 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1893 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1897 if (!rte_intr_allow_others(intr_handle)) {
1898 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1899 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1900 I40EVF_WRITE_FLUSH(hw);
1904 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1906 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1909 /* If host driver is kernel driver, do nothing.
1910 * Interrupt 0 is used for rx packets, but don't zero
1911 * I40E_VFINT_DYN_CTL01,
1912 * because interrupt 0 is also used for adminq processing.
1915 I40EVF_WRITE_FLUSH(hw);
1919 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1921 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1927 msix_intr = intr_handle->intr_vec[queue_id];
1928 if (msix_intr == I40E_MISC_VEC_ID)
1929 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1930 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1931 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1932 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1934 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1937 I40E_VFINT_DYN_CTLN1(msix_intr -
1939 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1940 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1941 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1943 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1945 I40EVF_WRITE_FLUSH(hw);
1947 rte_intr_enable(&dev->pci_dev->intr_handle);
1953 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1955 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 msix_intr = intr_handle->intr_vec[queue_id];
1960 if (msix_intr == I40E_MISC_VEC_ID)
1961 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1964 I40E_VFINT_DYN_CTLN1(msix_intr -
1968 I40EVF_WRITE_FLUSH(hw);
1974 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1976 struct i40e_virtchnl_ether_addr_list *list;
1977 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1982 struct ether_addr *addr;
1983 struct vf_cmd_info args;
1987 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1988 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1989 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1991 len += sizeof(struct i40e_virtchnl_ether_addr);
1992 if (len >= I40E_AQ_BUF_SZ) {
1998 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2000 for (i = begin; i < next_begin; i++) {
2001 addr = &dev->data->mac_addrs[i];
2002 if (is_zero_ether_addr(addr))
2004 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2005 sizeof(addr->addr_bytes));
2006 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2007 addr->addr_bytes[0], addr->addr_bytes[1],
2008 addr->addr_bytes[2], addr->addr_bytes[3],
2009 addr->addr_bytes[4], addr->addr_bytes[5]);
2012 list->vsi_id = vf->vsi_res->vsi_id;
2013 list->num_elements = j;
2014 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2015 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2016 args.in_args = (uint8_t *)list;
2017 args.in_args_size = len;
2018 args.out_buffer = vf->aq_resp;
2019 args.out_size = I40E_AQ_BUF_SZ;
2020 err = i40evf_execute_vf_cmd(dev, &args);
2022 PMD_DRV_LOG(ERR, "fail to execute command %s",
2023 add ? "OP_ADD_ETHER_ADDRESS" :
2024 "OP_DEL_ETHER_ADDRESS");
2027 } while (begin < I40E_NUM_MACADDR_MAX);
2031 i40evf_dev_start(struct rte_eth_dev *dev)
2033 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2034 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2036 uint32_t intr_vector = 0;
2038 PMD_INIT_FUNC_TRACE();
2040 hw->adapter_stopped = 0;
2042 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2043 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2044 dev->data->nb_tx_queues);
2046 /* check and configure queue intr-vector mapping */
2047 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2048 intr_vector = dev->data->nb_rx_queues;
2049 if (rte_intr_efd_enable(intr_handle, intr_vector))
2053 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2054 intr_handle->intr_vec =
2055 rte_zmalloc("intr_vec",
2056 dev->data->nb_rx_queues * sizeof(int), 0);
2057 if (!intr_handle->intr_vec) {
2058 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2059 " intr_vec\n", dev->data->nb_rx_queues);
2064 if (i40evf_rx_init(dev) != 0){
2065 PMD_DRV_LOG(ERR, "failed to do RX init");
2069 i40evf_tx_init(dev);
2071 if (i40evf_configure_queues(dev) != 0) {
2072 PMD_DRV_LOG(ERR, "configure queues failed");
2075 if (i40evf_config_irq_map(dev)) {
2076 PMD_DRV_LOG(ERR, "config_irq_map failed");
2080 /* Set all mac addrs */
2081 i40evf_add_del_all_mac_addr(dev, TRUE);
2083 if (i40evf_start_queues(dev) != 0) {
2084 PMD_DRV_LOG(ERR, "enable queues failed");
2088 i40evf_enable_queues_intr(dev);
2092 i40evf_add_del_all_mac_addr(dev, FALSE);
2098 i40evf_dev_stop(struct rte_eth_dev *dev)
2100 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2102 PMD_INIT_FUNC_TRACE();
2104 i40evf_stop_queues(dev);
2105 i40evf_disable_queues_intr(dev);
2106 i40e_dev_clear_queues(dev);
2108 /* Clean datapath event and queue/vec mapping */
2109 rte_intr_efd_disable(intr_handle);
2110 if (intr_handle->intr_vec) {
2111 rte_free(intr_handle->intr_vec);
2112 intr_handle->intr_vec = NULL;
2114 /* remove all mac addrs */
2115 i40evf_add_del_all_mac_addr(dev, FALSE);
2120 i40evf_dev_link_update(struct rte_eth_dev *dev,
2121 __rte_unused int wait_to_complete)
2123 struct rte_eth_link new_link;
2124 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2126 * DPDK pf host provide interfacet to acquire link status
2127 * while Linux driver does not
2129 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
2130 i40evf_get_link_status(dev, &new_link);
2132 /* Linux driver PF host */
2133 switch (vf->link_speed) {
2134 case I40E_LINK_SPEED_100MB:
2135 new_link.link_speed = ETH_SPEED_NUM_100M;
2137 case I40E_LINK_SPEED_1GB:
2138 new_link.link_speed = ETH_SPEED_NUM_1G;
2140 case I40E_LINK_SPEED_10GB:
2141 new_link.link_speed = ETH_SPEED_NUM_10G;
2143 case I40E_LINK_SPEED_20GB:
2144 new_link.link_speed = ETH_SPEED_NUM_20G;
2146 case I40E_LINK_SPEED_40GB:
2147 new_link.link_speed = ETH_SPEED_NUM_40G;
2150 new_link.link_speed = ETH_SPEED_NUM_100M;
2153 /* full duplex only */
2154 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2155 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2158 i40evf_dev_atomic_write_link_status(dev, &new_link);
2164 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2166 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2169 /* If enabled, just return */
2170 if (vf->promisc_unicast_enabled)
2173 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2175 vf->promisc_unicast_enabled = TRUE;
2179 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2181 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2184 /* If disabled, just return */
2185 if (!vf->promisc_unicast_enabled)
2188 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2190 vf->promisc_unicast_enabled = FALSE;
2194 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2196 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2199 /* If enabled, just return */
2200 if (vf->promisc_multicast_enabled)
2203 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2205 vf->promisc_multicast_enabled = TRUE;
2209 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2211 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2214 /* If enabled, just return */
2215 if (!vf->promisc_multicast_enabled)
2218 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2220 vf->promisc_multicast_enabled = FALSE;
2224 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2226 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2228 memset(dev_info, 0, sizeof(*dev_info));
2229 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2230 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2231 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2232 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2233 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2234 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2235 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2236 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2237 dev_info->rx_offload_capa =
2238 DEV_RX_OFFLOAD_VLAN_STRIP |
2239 DEV_RX_OFFLOAD_QINQ_STRIP |
2240 DEV_RX_OFFLOAD_IPV4_CKSUM |
2241 DEV_RX_OFFLOAD_UDP_CKSUM |
2242 DEV_RX_OFFLOAD_TCP_CKSUM;
2243 dev_info->tx_offload_capa =
2244 DEV_TX_OFFLOAD_VLAN_INSERT |
2245 DEV_TX_OFFLOAD_QINQ_INSERT |
2246 DEV_TX_OFFLOAD_IPV4_CKSUM |
2247 DEV_TX_OFFLOAD_UDP_CKSUM |
2248 DEV_TX_OFFLOAD_TCP_CKSUM |
2249 DEV_TX_OFFLOAD_SCTP_CKSUM;
2251 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2253 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2254 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2255 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2257 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2261 dev_info->default_txconf = (struct rte_eth_txconf) {
2263 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2264 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2265 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2267 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2268 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2269 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2270 ETH_TXQ_FLAGS_NOOFFLOADS,
2273 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2274 .nb_max = I40E_MAX_RING_DESC,
2275 .nb_min = I40E_MIN_RING_DESC,
2276 .nb_align = I40E_ALIGN_RING_DESC,
2279 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2280 .nb_max = I40E_MAX_RING_DESC,
2281 .nb_min = I40E_MIN_RING_DESC,
2282 .nb_align = I40E_ALIGN_RING_DESC,
2287 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2289 if (i40evf_get_statics(dev, stats))
2290 PMD_DRV_LOG(ERR, "Get statics failed");
2294 i40evf_dev_close(struct rte_eth_dev *dev)
2296 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297 struct rte_pci_device *pci_dev = dev->pci_dev;
2299 i40evf_dev_stop(dev);
2300 hw->adapter_stopped = 1;
2301 i40e_dev_free_queues(dev);
2302 i40evf_reset_vf(hw);
2303 i40e_shutdown_adminq(hw);
2304 /* disable uio intr before callback unregister */
2305 rte_intr_disable(&pci_dev->intr_handle);
2307 /* unregister callback func from eal lib */
2308 rte_intr_callback_unregister(&pci_dev->intr_handle,
2309 i40evf_dev_interrupt_handler, (void *)dev);
2310 i40evf_disable_irq0(hw);
2314 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2316 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2323 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2324 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2327 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2331 uint32_t *lut_dw = (uint32_t *)lut;
2332 uint16_t i, lut_size_dw = lut_size / 4;
2334 for (i = 0; i < lut_size_dw; i++)
2335 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2342 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2344 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2345 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2351 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2352 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2355 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2359 uint32_t *lut_dw = (uint32_t *)lut;
2360 uint16_t i, lut_size_dw = lut_size / 4;
2362 for (i = 0; i < lut_size_dw; i++)
2363 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2364 I40EVF_WRITE_FLUSH(hw);
2371 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2372 struct rte_eth_rss_reta_entry64 *reta_conf,
2375 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2377 uint16_t i, idx, shift;
2380 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2381 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2382 "(%d) doesn't match the number of hardware can "
2383 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2387 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2389 PMD_DRV_LOG(ERR, "No memory can be allocated");
2392 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2395 for (i = 0; i < reta_size; i++) {
2396 idx = i / RTE_RETA_GROUP_SIZE;
2397 shift = i % RTE_RETA_GROUP_SIZE;
2398 if (reta_conf[idx].mask & (1ULL << shift))
2399 lut[i] = reta_conf[idx].reta[shift];
2401 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2410 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2411 struct rte_eth_rss_reta_entry64 *reta_conf,
2414 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2415 uint16_t i, idx, shift;
2419 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2420 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2421 "(%d) doesn't match the number of hardware can "
2422 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2426 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2428 PMD_DRV_LOG(ERR, "No memory can be allocated");
2432 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2435 for (i = 0; i < reta_size; i++) {
2436 idx = i / RTE_RETA_GROUP_SIZE;
2437 shift = i % RTE_RETA_GROUP_SIZE;
2438 if (reta_conf[idx].mask & (1ULL << shift))
2439 reta_conf[idx].reta[shift] = lut[i];
2449 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2451 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2452 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2455 if (!key || key_len == 0) {
2456 PMD_DRV_LOG(DEBUG, "No key to be configured");
2458 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2460 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2464 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2465 struct i40e_aqc_get_set_rss_key_data *key_dw =
2466 (struct i40e_aqc_get_set_rss_key_data *)key;
2468 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2470 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2473 uint32_t *hash_key = (uint32_t *)key;
2476 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2477 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2478 I40EVF_WRITE_FLUSH(hw);
2485 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2487 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2488 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2491 if (!key || !key_len)
2494 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2495 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2496 (struct i40e_aqc_get_set_rss_key_data *)key);
2498 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2502 uint32_t *key_dw = (uint32_t *)key;
2505 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2506 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2508 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2514 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2516 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2517 uint64_t rss_hf, hena;
2520 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2521 rss_conf->rss_key_len);
2525 rss_hf = rss_conf->rss_hf;
2526 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2527 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2528 hena &= ~I40E_RSS_HENA_ALL;
2529 hena |= i40e_config_hena(rss_hf);
2530 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2531 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2532 I40EVF_WRITE_FLUSH(hw);
2538 i40evf_disable_rss(struct i40e_vf *vf)
2540 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2543 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2544 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2545 hena &= ~I40E_RSS_HENA_ALL;
2546 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2547 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2548 I40EVF_WRITE_FLUSH(hw);
2552 i40evf_config_rss(struct i40e_vf *vf)
2554 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2555 struct rte_eth_rss_conf rss_conf;
2556 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2559 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2560 i40evf_disable_rss(vf);
2561 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2565 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2566 /* Fill out the look up table */
2567 for (i = 0, j = 0; i < nb_q; i++, j++) {
2570 lut = (lut << 8) | j;
2572 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2575 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2576 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2577 i40evf_disable_rss(vf);
2578 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2582 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2583 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2584 /* Calculate the default hash key */
2585 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2586 rss_key_default[i] = (uint32_t)rte_rand();
2587 rss_conf.rss_key = (uint8_t *)rss_key_default;
2588 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2592 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2596 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2597 struct rte_eth_rss_conf *rss_conf)
2599 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2604 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2605 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2606 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2607 if (rss_hf != 0) /* Enable RSS */
2613 if (rss_hf == 0) /* Disable RSS */
2616 return i40evf_hw_rss_hash_set(vf, rss_conf);
2620 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2621 struct rte_eth_rss_conf *rss_conf)
2623 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2624 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2628 &rss_conf->rss_key_len);
2630 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2631 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2632 rss_conf->rss_hf = i40e_parse_hena(hena);