1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <ethdev_driver.h>
29 #include <ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static int i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static int i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int i40evf_init_vlan(struct rte_eth_dev *dev);
101 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
102 uint16_t rx_queue_id);
103 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
104 uint16_t rx_queue_id);
105 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
106 uint16_t tx_queue_id);
107 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
108 uint16_t tx_queue_id);
109 static int i40evf_add_del_eth_addr(struct rte_eth_dev *dev,
110 struct rte_ether_addr *addr,
111 bool add, uint8_t type);
112 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
113 struct rte_ether_addr *addr,
116 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
117 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
118 struct rte_eth_rss_reta_entry64 *reta_conf,
120 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
121 struct rte_eth_rss_reta_entry64 *reta_conf,
123 static int i40evf_config_rss(struct i40e_vf *vf);
124 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
125 struct rte_eth_rss_conf *rss_conf);
126 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
127 struct rte_eth_rss_conf *rss_conf);
128 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
129 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
130 struct rte_ether_addr *mac_addr);
132 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
134 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
135 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
140 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr, bool add);
144 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
145 struct rte_ether_addr *mc_addr_set,
146 uint32_t nb_mc_addr);
148 i40evf_dev_alarm_handler(void *param);
150 /* Default hash key buffer for RSS */
151 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
153 struct rte_i40evf_xstats_name_off {
154 char name[RTE_ETH_XSTATS_NAME_SIZE];
158 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
159 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
160 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
161 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
162 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
163 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
164 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
165 rx_unknown_protocol)},
166 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
167 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
168 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
169 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
170 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
171 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
174 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
175 sizeof(rte_i40evf_stats_strings[0]))
177 static const struct eth_dev_ops i40evf_eth_dev_ops = {
178 .dev_configure = i40evf_dev_configure,
179 .dev_start = i40evf_dev_start,
180 .dev_stop = i40evf_dev_stop,
181 .promiscuous_enable = i40evf_dev_promiscuous_enable,
182 .promiscuous_disable = i40evf_dev_promiscuous_disable,
183 .allmulticast_enable = i40evf_dev_allmulticast_enable,
184 .allmulticast_disable = i40evf_dev_allmulticast_disable,
185 .link_update = i40evf_dev_link_update,
186 .stats_get = i40evf_dev_stats_get,
187 .stats_reset = i40evf_dev_xstats_reset,
188 .xstats_get = i40evf_dev_xstats_get,
189 .xstats_get_names = i40evf_dev_xstats_get_names,
190 .xstats_reset = i40evf_dev_xstats_reset,
191 .dev_close = i40evf_dev_close,
192 .dev_reset = i40evf_dev_reset,
193 .dev_infos_get = i40evf_dev_info_get,
194 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
195 .vlan_filter_set = i40evf_vlan_filter_set,
196 .vlan_offload_set = i40evf_vlan_offload_set,
197 .rx_queue_start = i40evf_dev_rx_queue_start,
198 .rx_queue_stop = i40evf_dev_rx_queue_stop,
199 .tx_queue_start = i40evf_dev_tx_queue_start,
200 .tx_queue_stop = i40evf_dev_tx_queue_stop,
201 .rx_queue_setup = i40e_dev_rx_queue_setup,
202 .rx_queue_release = i40e_dev_rx_queue_release,
203 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
204 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
205 .tx_queue_setup = i40e_dev_tx_queue_setup,
206 .tx_queue_release = i40e_dev_tx_queue_release,
207 .rxq_info_get = i40e_rxq_info_get,
208 .txq_info_get = i40e_txq_info_get,
209 .mac_addr_add = i40evf_add_mac_addr,
210 .mac_addr_remove = i40evf_del_mac_addr,
211 .set_mc_addr_list = i40evf_set_mc_addr_list,
212 .reta_update = i40evf_dev_rss_reta_update,
213 .reta_query = i40evf_dev_rss_reta_query,
214 .rss_hash_update = i40evf_dev_rss_hash_update,
215 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
216 .mtu_set = i40evf_dev_mtu_set,
217 .mac_addr_set = i40evf_set_default_mac_addr,
218 .tx_done_cleanup = i40e_tx_done_cleanup,
222 * Read data in admin queue to get msg from pf driver
224 static enum i40evf_aq_result
225 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
228 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
229 struct i40e_arq_event_info event;
230 enum virtchnl_ops opcode;
231 enum i40e_status_code retval;
233 enum i40evf_aq_result result = I40EVF_MSG_NON;
235 event.buf_len = data->buf_len;
236 event.msg_buf = data->msg;
237 ret = i40e_clean_arq_element(hw, &event, NULL);
238 /* Can't read any msg from adminQ */
240 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
241 result = I40EVF_MSG_ERR;
245 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
246 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
248 if (opcode == VIRTCHNL_OP_EVENT) {
249 struct virtchnl_pf_event *vpe =
250 (struct virtchnl_pf_event *)event.msg_buf;
252 result = I40EVF_MSG_SYS;
253 switch (vpe->event) {
254 case VIRTCHNL_EVENT_LINK_CHANGE:
256 vpe->event_data.link_event.link_status;
258 vpe->event_data.link_event.link_speed;
259 vf->pend_msg |= PFMSG_LINK_CHANGE;
260 PMD_DRV_LOG(INFO, "Link status update:%s",
261 vf->link_up ? "up" : "down");
263 case VIRTCHNL_EVENT_RESET_IMPENDING:
265 vf->pend_msg |= PFMSG_RESET_IMPENDING;
266 PMD_DRV_LOG(INFO, "VF is resetting");
268 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
269 vf->dev_closed = true;
270 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
271 PMD_DRV_LOG(INFO, "PF driver closed");
274 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
275 __func__, vpe->event);
278 /* async reply msg on command issued by vf previously */
279 result = I40EVF_MSG_CMD;
280 /* Actual data length read from PF */
281 data->msg_len = event.msg_len;
284 data->result = retval;
291 * clear current command. Only call in case execute
292 * _atomic_set_cmd successfully.
295 _clear_cmd(struct i40e_vf *vf)
298 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
302 * Check there is pending cmd in execution. If none, set new command.
305 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
307 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
308 VIRTCHNL_OP_UNKNOWN, ops);
311 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
316 #define MAX_TRY_TIMES 200
317 #define ASQ_DELAY_MS 10
320 _i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
323 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
324 struct i40evf_arq_msg_info info;
325 enum i40evf_aq_result ret;
328 if (_atomic_set_cmd(vf, args->ops))
331 info.msg = args->out_buffer;
332 info.buf_len = args->out_size;
333 info.ops = VIRTCHNL_OP_UNKNOWN;
334 info.result = I40E_SUCCESS;
336 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
337 args->in_args, args->in_args_size, NULL);
339 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
345 case VIRTCHNL_OP_RESET_VF:
346 /*no need to process in this function */
349 case VIRTCHNL_OP_VERSION:
350 case VIRTCHNL_OP_GET_VF_RESOURCES:
351 /* for init adminq commands, need to poll the response */
354 ret = i40evf_read_pfmsg(dev, &info);
355 vf->cmd_retval = info.result;
356 if (ret == I40EVF_MSG_CMD) {
359 } else if (ret == I40EVF_MSG_ERR)
361 rte_delay_ms(ASQ_DELAY_MS);
362 /* If don't read msg or read sys event, continue */
363 } while (i++ < MAX_TRY_TIMES);
366 case VIRTCHNL_OP_REQUEST_QUEUES:
368 * ignore async reply, only wait for system message,
369 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
370 * if not, means request queues failed.
374 ret = i40evf_read_pfmsg(dev, &info);
375 vf->cmd_retval = info.result;
376 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
379 } else if (ret == I40EVF_MSG_ERR ||
380 ret == I40EVF_MSG_CMD) {
383 rte_delay_ms(ASQ_DELAY_MS);
384 /* If don't read msg or read sys event, continue */
385 } while (i++ < MAX_TRY_TIMES);
390 /* for other adminq in running time, waiting the cmd done flag */
393 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
397 rte_delay_ms(ASQ_DELAY_MS);
398 /* If don't read msg or read sys event, continue */
399 } while (i++ < MAX_TRY_TIMES);
400 /* If there's no response is received, clear command */
401 if (i >= MAX_TRY_TIMES) {
402 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
408 return err | vf->cmd_retval;
412 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
414 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
417 while (!rte_spinlock_trylock(&vf->cmd_send_lock))
418 rte_delay_us_sleep(50);
419 err = _i40evf_execute_vf_cmd(dev, args);
420 rte_spinlock_unlock(&vf->cmd_send_lock);
425 * Check API version with sync wait until version read or fail from admin queue
428 i40evf_check_api_version(struct rte_eth_dev *dev)
430 struct virtchnl_version_info version, *pver;
432 struct vf_cmd_info args;
433 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
435 version.major = VIRTCHNL_VERSION_MAJOR;
436 version.minor = VIRTCHNL_VERSION_MINOR;
438 args.ops = VIRTCHNL_OP_VERSION;
439 args.in_args = (uint8_t *)&version;
440 args.in_args_size = sizeof(version);
441 args.out_buffer = vf->aq_resp;
442 args.out_size = I40E_AQ_BUF_SZ;
444 err = i40evf_execute_vf_cmd(dev, &args);
446 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
450 pver = (struct virtchnl_version_info *)args.out_buffer;
451 vf->version_major = pver->major;
452 vf->version_minor = pver->minor;
453 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
454 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
455 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
457 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
458 vf->version_major, vf->version_minor,
459 VIRTCHNL_VERSION_MAJOR,
460 VIRTCHNL_VERSION_MINOR);
468 i40evf_get_vf_resource(struct rte_eth_dev *dev)
470 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
471 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
473 struct vf_cmd_info args;
476 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
477 args.out_buffer = vf->aq_resp;
478 args.out_size = I40E_AQ_BUF_SZ;
480 caps = VIRTCHNL_VF_OFFLOAD_L2 |
481 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
482 VIRTCHNL_VF_OFFLOAD_RSS_REG |
483 VIRTCHNL_VF_OFFLOAD_VLAN |
484 VIRTCHNL_VF_OFFLOAD_RX_POLLING |
485 VIRTCHNL_VF_CAP_ADV_LINK_SPEED;
486 args.in_args = (uint8_t *)∩︀
487 args.in_args_size = sizeof(caps);
490 args.in_args_size = 0;
492 err = i40evf_execute_vf_cmd(dev, &args);
495 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
499 len = sizeof(struct virtchnl_vf_resource) +
500 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
502 rte_memcpy(vf->vf_res, args.out_buffer,
503 RTE_MIN(args.out_size, len));
504 i40e_vf_parse_hw_config(hw, vf->vf_res);
510 i40evf_config_promisc(struct rte_eth_dev *dev,
512 bool enable_multicast)
514 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
516 struct vf_cmd_info args;
517 struct virtchnl_promisc_info promisc;
520 promisc.vsi_id = vf->vsi_res->vsi_id;
523 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
525 if (enable_multicast)
526 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
528 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
529 args.in_args = (uint8_t *)&promisc;
530 args.in_args_size = sizeof(promisc);
531 args.out_buffer = vf->aq_resp;
532 args.out_size = I40E_AQ_BUF_SZ;
534 err = i40evf_execute_vf_cmd(dev, &args);
537 PMD_DRV_LOG(ERR, "fail to execute command "
538 "CONFIG_PROMISCUOUS_MODE");
540 if (err == I40E_NOT_SUPPORTED)
546 vf->promisc_unicast_enabled = enable_unicast;
547 vf->promisc_multicast_enabled = enable_multicast;
552 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
554 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
555 struct vf_cmd_info args;
558 memset(&args, 0, sizeof(args));
559 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
561 args.in_args_size = 0;
562 args.out_buffer = vf->aq_resp;
563 args.out_size = I40E_AQ_BUF_SZ;
564 ret = i40evf_execute_vf_cmd(dev, &args);
566 PMD_DRV_LOG(ERR, "Failed to execute command of "
567 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
573 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
575 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
576 struct vf_cmd_info args;
579 memset(&args, 0, sizeof(args));
580 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
582 args.in_args_size = 0;
583 args.out_buffer = vf->aq_resp;
584 args.out_size = I40E_AQ_BUF_SZ;
585 ret = i40evf_execute_vf_cmd(dev, &args);
587 PMD_DRV_LOG(ERR, "Failed to execute command of "
588 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
594 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
598 struct i40e_tx_queue *txq)
600 txq_info->vsi_id = vsi_id;
601 txq_info->queue_id = queue_id;
602 if (queue_id < nb_txq && txq) {
603 txq_info->ring_len = txq->nb_tx_desc;
604 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
609 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
613 uint32_t max_pkt_size,
614 struct i40e_rx_queue *rxq)
616 rxq_info->vsi_id = vsi_id;
617 rxq_info->queue_id = queue_id;
618 rxq_info->max_pkt_size = max_pkt_size;
619 if (queue_id < nb_rxq && rxq) {
620 rxq_info->ring_len = rxq->nb_rx_desc;
621 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
622 rxq_info->databuffer_size =
623 (rte_pktmbuf_data_room_size(rxq->mp) -
624 RTE_PKTMBUF_HEADROOM);
629 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
631 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
632 struct i40e_rx_queue **rxq =
633 (struct i40e_rx_queue **)dev->data->rx_queues;
634 struct i40e_tx_queue **txq =
635 (struct i40e_tx_queue **)dev->data->tx_queues;
636 struct virtchnl_vsi_queue_config_info *vc_vqci;
637 struct virtchnl_queue_pair_info *vc_qpi;
638 struct vf_cmd_info args;
639 uint16_t i, nb_qp = vf->num_queue_pairs;
640 const uint32_t size =
641 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
645 memset(buff, 0, sizeof(buff));
646 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
647 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
648 vc_vqci->num_queue_pairs = nb_qp;
650 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
651 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
652 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
653 txq ? txq[i] : NULL);
654 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
655 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
656 vf->max_pkt_len, rxq ? rxq[i] : NULL);
658 memset(&args, 0, sizeof(args));
659 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
660 args.in_args = (uint8_t *)vc_vqci;
661 args.in_args_size = size;
662 args.out_buffer = vf->aq_resp;
663 args.out_size = I40E_AQ_BUF_SZ;
664 ret = i40evf_execute_vf_cmd(dev, &args);
666 PMD_DRV_LOG(ERR, "Failed to execute command of "
667 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
673 i40evf_config_irq_map(struct rte_eth_dev *dev)
675 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
676 struct vf_cmd_info args;
677 uint8_t *cmd_buffer = NULL;
678 struct virtchnl_irq_map_info *map_info;
679 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
680 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
681 uint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;
682 uint16_t rxq_map[vf->vf_res->max_vectors];
685 memset(rxq_map, 0, sizeof(rxq_map));
686 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
687 rte_intr_allow_others(intr_handle)) {
688 msix_base = I40E_RX_VEC_START;
689 /* For interrupt mode, available vector id is from 1. */
690 max_vectors = vf->vf_res->max_vectors - 1;
691 nb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);
694 for (i = 0; i < dev->data->nb_rx_queues; i++) {
695 rxq_map[vec] |= 1 << i;
696 intr_handle->intr_vec[i] = vec++;
697 if (vec >= vf->vf_res->max_vectors)
701 msix_base = I40E_MISC_VEC_ID;
704 for (i = 0; i < dev->data->nb_rx_queues; i++) {
705 rxq_map[msix_base] |= 1 << i;
706 if (rte_intr_dp_is_en(intr_handle))
707 intr_handle->intr_vec[i] = msix_base;
711 cmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +
712 sizeof(struct virtchnl_vector_map) * nb_msix;
713 cmd_buffer = rte_zmalloc("i40e", cmd_buffer_size, 0);
715 PMD_DRV_LOG(ERR, "Failed to allocate memory");
716 return I40E_ERR_NO_MEMORY;
719 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
720 map_info->num_vectors = nb_msix;
721 for (i = 0; i < nb_msix; i++) {
722 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
723 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
724 map_info->vecmap[i].vector_id = msix_base + i;
725 map_info->vecmap[i].txq_map = 0;
726 map_info->vecmap[i].rxq_map = rxq_map[msix_base + i];
729 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
730 args.in_args = (u8 *)cmd_buffer;
731 args.in_args_size = cmd_buffer_size;
732 args.out_buffer = vf->aq_resp;
733 args.out_size = I40E_AQ_BUF_SZ;
734 err = i40evf_execute_vf_cmd(dev, &args);
736 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
738 rte_free(cmd_buffer);
744 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
747 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
748 struct virtchnl_queue_select queue_select;
750 struct vf_cmd_info args;
751 memset(&queue_select, 0, sizeof(queue_select));
752 queue_select.vsi_id = vf->vsi_res->vsi_id;
755 queue_select.rx_queues |= 1 << qid;
757 queue_select.tx_queues |= 1 << qid;
760 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
762 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
763 args.in_args = (u8 *)&queue_select;
764 args.in_args_size = sizeof(queue_select);
765 args.out_buffer = vf->aq_resp;
766 args.out_size = I40E_AQ_BUF_SZ;
767 err = i40evf_execute_vf_cmd(dev, &args);
769 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
770 isrx ? "RX" : "TX", qid, on ? "on" : "off");
776 i40evf_start_queues(struct rte_eth_dev *dev)
778 struct rte_eth_dev_data *dev_data = dev->data;
780 struct i40e_rx_queue *rxq;
781 struct i40e_tx_queue *txq;
783 for (i = 0; i < dev->data->nb_rx_queues; i++) {
784 rxq = dev_data->rx_queues[i];
785 if (rxq->rx_deferred_start)
787 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
788 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
793 for (i = 0; i < dev->data->nb_tx_queues; i++) {
794 txq = dev_data->tx_queues[i];
795 if (txq->tx_deferred_start)
797 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
798 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
807 i40evf_stop_queues(struct rte_eth_dev *dev)
811 /* Stop TX queues first */
812 for (i = 0; i < dev->data->nb_tx_queues; i++) {
813 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
814 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
818 /* Then stop RX queues */
819 for (i = 0; i < dev->data->nb_rx_queues; i++) {
820 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
821 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
829 i40evf_add_del_eth_addr(struct rte_eth_dev *dev,
830 struct rte_ether_addr *addr,
831 bool add, uint8_t type)
833 struct virtchnl_ether_addr_list *list;
834 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
835 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
836 sizeof(struct virtchnl_ether_addr)];
838 struct vf_cmd_info args;
840 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
841 list->vsi_id = vf->vsi_res->vsi_id;
842 list->num_elements = 1;
843 list->list[0].type = type;
844 rte_memcpy(list->list[0].addr, addr->addr_bytes,
845 sizeof(addr->addr_bytes));
847 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
848 args.in_args = cmd_buffer;
849 args.in_args_size = sizeof(cmd_buffer);
850 args.out_buffer = vf->aq_resp;
851 args.out_size = I40E_AQ_BUF_SZ;
852 err = i40evf_execute_vf_cmd(dev, &args);
854 PMD_DRV_LOG(ERR, "fail to execute command %s",
855 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
860 i40evf_add_mac_addr(struct rte_eth_dev *dev,
861 struct rte_ether_addr *addr,
862 __rte_unused uint32_t index,
863 __rte_unused uint32_t pool)
865 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
868 if (rte_is_zero_ether_addr(addr)) {
869 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
870 addr->addr_bytes[0], addr->addr_bytes[1],
871 addr->addr_bytes[2], addr->addr_bytes[3],
872 addr->addr_bytes[4], addr->addr_bytes[5]);
873 return I40E_ERR_INVALID_MAC_ADDR;
876 err = i40evf_add_del_eth_addr(dev, addr, TRUE, VIRTCHNL_ETHER_ADDR_EXTRA);
879 PMD_DRV_LOG(ERR, "fail to add MAC address");
887 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
889 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
890 struct rte_eth_dev_data *data = dev->data;
891 struct rte_ether_addr *addr;
894 addr = &data->mac_addrs[index];
896 err = i40evf_add_del_eth_addr(dev, addr, FALSE, VIRTCHNL_ETHER_ADDR_EXTRA);
899 PMD_DRV_LOG(ERR, "fail to delete MAC address");
907 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
909 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
910 struct virtchnl_queue_select q_stats;
912 struct vf_cmd_info args;
914 memset(&q_stats, 0, sizeof(q_stats));
915 q_stats.vsi_id = vf->vsi_res->vsi_id;
916 args.ops = VIRTCHNL_OP_GET_STATS;
917 args.in_args = (u8 *)&q_stats;
918 args.in_args_size = sizeof(q_stats);
919 args.out_buffer = vf->aq_resp;
920 args.out_size = I40E_AQ_BUF_SZ;
922 err = i40evf_execute_vf_cmd(dev, &args);
924 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
928 *pstats = (struct i40e_eth_stats *)args.out_buffer;
933 i40evf_stat_update_48(uint64_t *offset,
936 if (*stat >= *offset)
937 *stat = *stat - *offset;
939 *stat = (uint64_t)((*stat +
940 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
942 *stat &= I40E_48_BIT_MASK;
946 i40evf_stat_update_32(uint64_t *offset,
949 if (*stat >= *offset)
950 *stat = (uint64_t)(*stat - *offset);
952 *stat = (uint64_t)((*stat +
953 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
957 i40evf_update_stats(struct i40e_vsi *vsi,
958 struct i40e_eth_stats *nes)
960 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
962 i40evf_stat_update_48(&oes->rx_bytes,
964 i40evf_stat_update_48(&oes->rx_unicast,
966 i40evf_stat_update_48(&oes->rx_multicast,
968 i40evf_stat_update_48(&oes->rx_broadcast,
970 i40evf_stat_update_32(&oes->rx_discards,
972 i40evf_stat_update_32(&oes->rx_unknown_protocol,
973 &nes->rx_unknown_protocol);
974 i40evf_stat_update_48(&oes->tx_bytes,
976 i40evf_stat_update_48(&oes->tx_unicast,
978 i40evf_stat_update_48(&oes->tx_multicast,
980 i40evf_stat_update_48(&oes->tx_broadcast,
982 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
983 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
987 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
990 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
991 struct i40e_eth_stats *pstats = NULL;
993 /* read stat values to clear hardware registers */
994 ret = i40evf_query_stats(dev, &pstats);
996 /* set stats offset base on current values */
998 vf->vsi.eth_stats_offset = *pstats;
1003 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1004 struct rte_eth_xstat_name *xstats_names,
1005 __rte_unused unsigned limit)
1009 if (xstats_names != NULL)
1010 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1011 snprintf(xstats_names[i].name,
1012 sizeof(xstats_names[i].name),
1013 "%s", rte_i40evf_stats_strings[i].name);
1015 return I40EVF_NB_XSTATS;
1018 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1019 struct rte_eth_xstat *xstats, unsigned n)
1023 struct i40e_eth_stats *pstats = NULL;
1024 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1025 struct i40e_vsi *vsi = &vf->vsi;
1027 if (n < I40EVF_NB_XSTATS)
1028 return I40EVF_NB_XSTATS;
1030 ret = i40evf_query_stats(dev, &pstats);
1037 i40evf_update_stats(vsi, pstats);
1039 /* loop over xstats array and values from pstats */
1040 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1042 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1043 rte_i40evf_stats_strings[i].offset);
1046 return I40EVF_NB_XSTATS;
1050 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1052 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1053 struct virtchnl_vlan_filter_list *vlan_list;
1054 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1057 struct vf_cmd_info args;
1059 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1060 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1061 vlan_list->num_elements = 1;
1062 vlan_list->vlan_id[0] = vlanid;
1064 args.ops = VIRTCHNL_OP_ADD_VLAN;
1065 args.in_args = (u8 *)&cmd_buffer;
1066 args.in_args_size = sizeof(cmd_buffer);
1067 args.out_buffer = vf->aq_resp;
1068 args.out_size = I40E_AQ_BUF_SZ;
1069 err = i40evf_execute_vf_cmd(dev, &args);
1071 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1075 * In linux kernel driver on receiving ADD_VLAN it enables
1076 * VLAN_STRIP by default. So reconfigure the vlan_offload
1077 * as it was done by the app earlier.
1079 err = i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1081 PMD_DRV_LOG(ERR, "fail to set vlan_strip");
1087 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1089 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1090 struct virtchnl_vf_res_request vfres;
1091 struct vf_cmd_info args;
1094 vfres.num_queue_pairs = num;
1096 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1097 args.in_args = (u8 *)&vfres;
1098 args.in_args_size = sizeof(vfres);
1099 args.out_buffer = vf->aq_resp;
1100 args.out_size = I40E_AQ_BUF_SZ;
1102 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1104 err = i40evf_execute_vf_cmd(dev, &args);
1106 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);
1108 if (err != I40E_SUCCESS) {
1109 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1113 /* The PF will issue a reset to the VF when change the number of
1114 * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then
1115 * wait 10ms and set it to ACTIVE. In this duration, vf may not catch
1116 * the moment that COMPLETE is set. So, for vf, we'll try to wait a
1121 err = i40evf_check_vf_reset_done(dev);
1123 PMD_DRV_LOG(ERR, "VF is still resetting");
1129 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1131 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1132 struct virtchnl_vlan_filter_list *vlan_list;
1133 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1136 struct vf_cmd_info args;
1138 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1139 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1140 vlan_list->num_elements = 1;
1141 vlan_list->vlan_id[0] = vlanid;
1143 args.ops = VIRTCHNL_OP_DEL_VLAN;
1144 args.in_args = (u8 *)&cmd_buffer;
1145 args.in_args_size = sizeof(cmd_buffer);
1146 args.out_buffer = vf->aq_resp;
1147 args.out_size = I40E_AQ_BUF_SZ;
1148 err = i40evf_execute_vf_cmd(dev, &args);
1150 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1155 static const struct rte_pci_id pci_id_i40evf_map[] = {
1156 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1157 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1158 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1159 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1160 { .vendor_id = 0, /* sentinel */ },
1165 i40evf_disable_irq0(struct i40e_hw *hw)
1167 /* Disable all interrupt types */
1168 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1169 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1170 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1171 I40EVF_WRITE_FLUSH(hw);
1176 i40evf_enable_irq0(struct i40e_hw *hw)
1178 /* Enable admin queue interrupt trigger */
1181 i40evf_disable_irq0(hw);
1182 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1183 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1184 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1185 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1187 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1188 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1189 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1190 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1192 I40EVF_WRITE_FLUSH(hw);
1196 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1199 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1202 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1203 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1204 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1205 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1206 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1207 reset == VIRTCHNL_VFR_COMPLETED)
1212 if (i >= MAX_RESET_WAIT_CNT)
1215 vf->vf_reset = false;
1216 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1221 i40evf_reset_vf(struct rte_eth_dev *dev)
1224 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1227 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1231 * After issuing vf reset command to pf, pf won't necessarily
1232 * reset vf, it depends on what state it exactly is. If it's not
1233 * initialized yet, it won't have vf reset since it's in a certain
1234 * state. If not, it will try to reset. Even vf is reset, pf will
1235 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1236 * it to ACTIVE. In this duration, vf may not catch the moment that
1237 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1241 ret = i40evf_check_vf_reset_done(dev);
1243 PMD_INIT_LOG(ERR, "VF is still resetting");
1251 i40evf_init_vf(struct rte_eth_dev *dev)
1254 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1255 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1257 i40e_calc_itr_interval(0, 0);
1259 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1260 vf->dev_data = dev->data;
1261 rte_spinlock_init(&vf->cmd_send_lock);
1262 err = i40e_set_mac_type(hw);
1264 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1268 err = i40evf_check_vf_reset_done(dev);
1272 i40e_init_adminq_parameter(hw);
1273 err = i40e_init_adminq(hw);
1275 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1279 /* Reset VF and wait until it's complete */
1280 if (i40evf_reset_vf(dev)) {
1281 PMD_INIT_LOG(ERR, "reset NIC failed");
1285 /* VF reset, shutdown admin queue and initialize again */
1286 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1287 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1291 i40e_init_adminq_parameter(hw);
1292 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1293 PMD_INIT_LOG(ERR, "init_adminq failed");
1297 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1299 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1302 if (i40evf_check_api_version(dev) != 0) {
1303 PMD_INIT_LOG(ERR, "check_api version failed");
1306 bufsz = sizeof(struct virtchnl_vf_resource) +
1307 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1308 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1310 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1314 if (i40evf_get_vf_resource(dev) != 0) {
1315 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1319 /* got VF config message back from PF, now we can parse it */
1320 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1321 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1322 vf->vsi_res = &vf->vf_res->vsi_res[i];
1326 PMD_INIT_LOG(ERR, "no LAN VSI found");
1330 if (hw->mac.type == I40E_MAC_X722_VF)
1331 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1332 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1334 switch (vf->vsi_res->vsi_type) {
1335 case VIRTCHNL_VSI_SRIOV:
1336 vf->vsi.type = I40E_VSI_SRIOV;
1339 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1342 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1343 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1345 /* Store the MAC address configured by host, or generate random one */
1346 if (!rte_is_valid_assigned_ether_addr(
1347 (struct rte_ether_addr *)hw->mac.addr))
1348 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1350 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1351 (I40E_ITR_INDEX_DEFAULT <<
1352 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1354 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1355 I40EVF_WRITE_FLUSH(hw);
1360 rte_free(vf->vf_res);
1363 rte_free(vf->aq_resp);
1365 i40e_shutdown_adminq(hw); /* ignore error */
1371 i40evf_uninit_vf(struct rte_eth_dev *dev)
1373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375 PMD_INIT_FUNC_TRACE();
1377 if (hw->adapter_closed == 0)
1378 i40evf_dev_close(dev);
1384 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1385 __rte_unused uint16_t msglen)
1387 struct virtchnl_pf_event *pf_msg =
1388 (struct virtchnl_pf_event *)msg;
1389 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1391 switch (pf_msg->event) {
1392 case VIRTCHNL_EVENT_RESET_IMPENDING:
1393 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1394 rte_eth_dev_callback_process(dev,
1395 RTE_ETH_EVENT_INTR_RESET, NULL);
1397 case VIRTCHNL_EVENT_LINK_CHANGE:
1398 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1400 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {
1402 pf_msg->event_data.link_event_adv.link_status;
1404 switch (pf_msg->event_data.link_event_adv.link_speed) {
1405 case ETH_SPEED_NUM_100M:
1406 vf->link_speed = VIRTCHNL_LINK_SPEED_100MB;
1408 case ETH_SPEED_NUM_1G:
1409 vf->link_speed = VIRTCHNL_LINK_SPEED_1GB;
1411 case ETH_SPEED_NUM_2_5G:
1412 vf->link_speed = VIRTCHNL_LINK_SPEED_2_5GB;
1414 case ETH_SPEED_NUM_5G:
1415 vf->link_speed = VIRTCHNL_LINK_SPEED_5GB;
1417 case ETH_SPEED_NUM_10G:
1418 vf->link_speed = VIRTCHNL_LINK_SPEED_10GB;
1420 case ETH_SPEED_NUM_20G:
1421 vf->link_speed = VIRTCHNL_LINK_SPEED_20GB;
1423 case ETH_SPEED_NUM_25G:
1424 vf->link_speed = VIRTCHNL_LINK_SPEED_25GB;
1426 case ETH_SPEED_NUM_40G:
1427 vf->link_speed = VIRTCHNL_LINK_SPEED_40GB;
1430 vf->link_speed = VIRTCHNL_LINK_SPEED_UNKNOWN;
1435 pf_msg->event_data.link_event.link_status;
1437 pf_msg->event_data.link_event.link_speed;
1440 i40evf_dev_link_update(dev, 0);
1441 rte_eth_dev_callback_process(dev,
1442 RTE_ETH_EVENT_INTR_LSC, NULL);
1444 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1445 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1448 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1454 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1456 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1458 struct i40e_arq_event_info info;
1459 uint16_t pending, aq_opc;
1460 enum virtchnl_ops msg_opc;
1461 enum i40e_status_code msg_ret;
1464 info.buf_len = I40E_AQ_BUF_SZ;
1466 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1469 info.msg_buf = vf->aq_resp;
1473 ret = i40e_clean_arq_element(hw, &info, &pending);
1475 if (ret != I40E_SUCCESS) {
1476 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1480 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1481 /* For the message sent from pf to vf, opcode is stored in
1482 * cookie_high of struct i40e_aq_desc, while return error code
1483 * are stored in cookie_low, Which is done by
1484 * i40e_aq_send_msg_to_vf in PF driver.*/
1485 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1486 info.desc.cookie_high);
1487 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1488 info.desc.cookie_low);
1490 case i40e_aqc_opc_send_msg_to_vf:
1491 if (msg_opc == VIRTCHNL_OP_EVENT)
1493 i40evf_handle_pf_event(dev, info.msg_buf,
1496 /* read message and it's expected one */
1497 if ((volatile uint32_t)msg_opc ==
1499 vf->cmd_retval = msg_ret;
1500 /* prevent compiler reordering */
1501 rte_compiler_barrier();
1504 PMD_DRV_LOG(ERR, "command mismatch,"
1505 "expect %u, get %u",
1506 vf->pend_cmd, msg_opc);
1507 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1508 " opcode = %d", msg_opc);
1512 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1520 * Interrupt handler triggered by NIC for handling
1521 * specific interrupt. Only adminq interrupt is processed in VF.
1524 * Pointer to interrupt handle.
1526 * The address of parameter (struct rte_eth_dev *) regsitered before.
1532 i40evf_dev_alarm_handler(void *param)
1534 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538 i40evf_disable_irq0(hw);
1540 /* read out interrupt causes */
1541 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1543 /* No interrupt event indicated */
1544 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1547 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1548 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1549 i40evf_handle_aq_msg(dev);
1552 /* Link Status Change interrupt */
1553 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1554 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1558 i40evf_enable_irq0(hw);
1559 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1560 i40evf_dev_alarm_handler, dev);
1564 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1567 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1568 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1570 PMD_INIT_FUNC_TRACE();
1572 /* assign ops func pointer */
1573 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1574 eth_dev->rx_queue_count = i40e_dev_rx_queue_count;
1575 eth_dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1576 eth_dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1577 eth_dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1578 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1579 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1582 * For secondary processes, we don't initialise any further as primary
1583 * has already done this work.
1585 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1586 i40e_set_rx_function(eth_dev);
1587 i40e_set_tx_function(eth_dev);
1590 i40e_set_default_ptype_table(eth_dev);
1591 rte_eth_copy_pci_info(eth_dev, pci_dev);
1592 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1594 hw->vendor_id = pci_dev->id.vendor_id;
1595 hw->device_id = pci_dev->id.device_id;
1596 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1597 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1598 hw->bus.device = pci_dev->addr.devid;
1599 hw->bus.func = pci_dev->addr.function;
1600 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1601 hw->adapter_stopped = 1;
1602 hw->adapter_closed = 0;
1604 if(i40evf_init_vf(eth_dev) != 0) {
1605 PMD_INIT_LOG(ERR, "Init vf failed");
1609 i40e_set_default_pctype_table(eth_dev);
1610 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1611 i40evf_dev_alarm_handler, eth_dev);
1613 /* configure and enable device interrupt */
1614 i40evf_enable_irq0(hw);
1617 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1618 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1620 if (eth_dev->data->mac_addrs == NULL) {
1621 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1622 " store MAC addresses",
1623 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1626 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1627 ð_dev->data->mac_addrs[0]);
1633 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1635 PMD_INIT_FUNC_TRACE();
1637 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1640 if (i40evf_uninit_vf(eth_dev) != 0) {
1641 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1649 i40evf_check_driver_handler(__rte_unused const char *key,
1650 const char *value, __rte_unused void *opaque)
1652 if (strcmp(value, "i40evf"))
1659 i40evf_driver_selected(struct rte_devargs *devargs)
1661 struct rte_kvargs *kvlist;
1662 const char *key = "driver";
1665 if (devargs == NULL)
1668 kvlist = rte_kvargs_parse(devargs->args, NULL);
1672 if (!rte_kvargs_count(kvlist, key))
1675 /* i40evf driver selected when there's a key-value pair:
1678 if (rte_kvargs_process(kvlist, key,
1679 i40evf_check_driver_handler, NULL) < 0)
1685 rte_kvargs_free(kvlist);
1689 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1690 struct rte_pci_device *pci_dev)
1692 if (!i40evf_driver_selected(pci_dev->device.devargs))
1695 return rte_eth_dev_pci_generic_probe(pci_dev,
1696 sizeof(struct i40e_adapter), i40evf_dev_init);
1699 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1701 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1705 * virtual function driver struct
1707 static struct rte_pci_driver rte_i40evf_pmd = {
1708 .id_table = pci_id_i40evf_map,
1709 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1710 .probe = eth_i40evf_pci_probe,
1711 .remove = eth_i40evf_pci_remove,
1714 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1715 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1716 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1717 RTE_PMD_REGISTER_PARAM_STRING(net_i40e_vf, "driver=i40evf");
1720 i40evf_dev_configure(struct rte_eth_dev *dev)
1722 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1723 struct i40e_adapter *ad =
1724 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1725 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1726 dev->data->nb_tx_queues);
1728 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1729 * allocation or vector Rx preconditions we will reset it.
1731 ad->rx_bulk_alloc_allowed = true;
1732 ad->rx_vec_allowed = true;
1733 ad->tx_simple_allowed = true;
1734 ad->tx_vec_allowed = true;
1736 dev->data->dev_conf.intr_conf.lsc =
1737 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);
1739 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1743 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1745 "For secondary processes, change queue pairs is not supported!");
1749 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750 if (!hw->adapter_stopped) {
1751 PMD_DRV_LOG(ERR, "Device must be stopped first!");
1755 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1756 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1757 ret = i40evf_request_queues(dev, num_queue_pairs);
1761 ret = i40evf_dev_reset(dev);
1766 return i40evf_init_vlan(dev);
1770 i40evf_init_vlan(struct rte_eth_dev *dev)
1772 /* Apply vlan offload setting */
1773 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1779 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1781 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1782 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1784 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1787 /* Vlan stripping setting */
1788 if (mask & ETH_VLAN_STRIP_MASK) {
1789 /* Enable or disable VLAN stripping */
1790 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1791 i40evf_enable_vlan_strip(dev);
1793 i40evf_disable_vlan_strip(dev);
1800 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1802 struct i40e_rx_queue *rxq;
1804 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 PMD_INIT_FUNC_TRACE();
1808 rxq = dev->data->rx_queues[rx_queue_id];
1810 err = i40e_alloc_rx_queue_mbufs(rxq);
1812 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1818 /* Init the RX tail register. */
1819 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1820 I40EVF_WRITE_FLUSH(hw);
1822 /* Ready to switch the queue on */
1823 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1825 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1829 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1835 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1837 struct i40e_rx_queue *rxq;
1840 rxq = dev->data->rx_queues[rx_queue_id];
1842 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1844 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1849 i40e_rx_queue_release_mbufs(rxq);
1850 i40e_reset_rx_queue(rxq);
1851 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1857 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1861 PMD_INIT_FUNC_TRACE();
1863 /* Ready to switch the queue on */
1864 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1866 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1870 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1876 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1878 struct i40e_tx_queue *txq;
1881 txq = dev->data->tx_queues[tx_queue_id];
1883 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1885 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1890 i40e_tx_queue_release_mbufs(txq);
1891 i40e_reset_tx_queue(txq);
1892 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1898 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1903 ret = i40evf_add_vlan(dev, vlan_id);
1905 ret = i40evf_del_vlan(dev,vlan_id);
1911 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914 struct rte_eth_dev_data *dev_data = dev->data;
1915 struct rte_pktmbuf_pool_private *mbp_priv;
1916 uint16_t buf_size, len;
1918 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1919 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1920 I40EVF_WRITE_FLUSH(hw);
1922 /* Calculate the maximum packet length allowed */
1923 mbp_priv = rte_mempool_get_priv(rxq->mp);
1924 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1925 RTE_PKTMBUF_HEADROOM);
1926 rxq->hs_mode = i40e_header_split_none;
1927 rxq->rx_hdr_len = 0;
1928 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1929 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1930 rxq->max_pkt_len = RTE_MIN(len,
1931 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1934 * Check if the jumbo frame and maximum packet length are set correctly
1936 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1937 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
1938 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1939 PMD_DRV_LOG(ERR, "maximum packet length must be "
1940 "larger than %u and smaller than %u, as jumbo "
1941 "frame is enabled", (uint32_t)I40E_ETH_MAX_LEN,
1942 (uint32_t)I40E_FRAME_SIZE_MAX);
1943 return I40E_ERR_CONFIG;
1946 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1947 rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
1948 PMD_DRV_LOG(ERR, "maximum packet length must be "
1949 "larger than %u and smaller than %u, as jumbo "
1950 "frame is disabled",
1951 (uint32_t)RTE_ETHER_MIN_LEN,
1952 (uint32_t)I40E_ETH_MAX_LEN);
1953 return I40E_ERR_CONFIG;
1957 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1958 rxq->max_pkt_len > buf_size)
1959 dev_data->scattered_rx = 1;
1965 i40evf_rx_init(struct rte_eth_dev *dev)
1967 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1969 int ret = I40E_SUCCESS;
1970 struct i40e_rx_queue **rxq =
1971 (struct i40e_rx_queue **)dev->data->rx_queues;
1973 i40evf_config_rss(vf);
1974 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1975 if (!rxq[i] || !rxq[i]->q_set)
1977 ret = i40evf_rxq_init(dev, rxq[i]);
1978 if (ret != I40E_SUCCESS)
1981 if (ret == I40E_SUCCESS)
1982 i40e_set_rx_function(dev);
1988 i40evf_tx_init(struct rte_eth_dev *dev)
1991 struct i40e_tx_queue **txq =
1992 (struct i40e_tx_queue **)dev->data->tx_queues;
1993 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995 for (i = 0; i < dev->data->nb_tx_queues; i++)
1996 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1998 i40e_set_tx_function(dev);
2002 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
2004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2008 if (!rte_intr_allow_others(intr_handle)) {
2010 I40E_VFINT_DYN_CTL01,
2011 I40E_VFINT_DYN_CTL01_INTENA_MASK |
2012 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
2013 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
2014 I40EVF_WRITE_FLUSH(hw);
2018 I40EVF_WRITE_FLUSH(hw);
2022 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
2024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2026 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2028 if (!rte_intr_allow_others(intr_handle)) {
2029 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
2030 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
2031 I40EVF_WRITE_FLUSH(hw);
2035 I40EVF_WRITE_FLUSH(hw);
2039 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2041 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2042 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2043 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045 i40e_calc_itr_interval(0, 0);
2048 msix_intr = intr_handle->intr_vec[queue_id];
2049 if (msix_intr == I40E_MISC_VEC_ID)
2050 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
2051 I40E_VFINT_DYN_CTL01_INTENA_MASK |
2052 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
2053 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
2055 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
2058 I40E_VFINT_DYN_CTLN1(msix_intr -
2060 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2061 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2062 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2064 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2066 I40EVF_WRITE_FLUSH(hw);
2072 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2075 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 msix_intr = intr_handle->intr_vec[queue_id];
2080 if (msix_intr == I40E_MISC_VEC_ID)
2081 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2084 I40E_VFINT_DYN_CTLN1(msix_intr -
2088 I40EVF_WRITE_FLUSH(hw);
2094 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2096 struct virtchnl_ether_addr_list *list;
2097 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2102 struct rte_ether_addr *addr;
2103 struct vf_cmd_info args;
2107 len = sizeof(struct virtchnl_ether_addr_list);
2108 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2109 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
2111 len += sizeof(struct virtchnl_ether_addr);
2112 if (len >= I40E_AQ_BUF_SZ) {
2118 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2120 PMD_DRV_LOG(ERR, "fail to allocate memory");
2124 for (i = begin; i < next_begin; i++) {
2125 addr = &dev->data->mac_addrs[i];
2126 if (rte_is_zero_ether_addr(addr))
2128 rte_memcpy(list->list[j].addr, addr->addr_bytes,
2129 sizeof(addr->addr_bytes));
2130 list->list[j].type = VIRTCHNL_ETHER_ADDR_EXTRA;
2131 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2132 addr->addr_bytes[0], addr->addr_bytes[1],
2133 addr->addr_bytes[2], addr->addr_bytes[3],
2134 addr->addr_bytes[4], addr->addr_bytes[5]);
2137 list->vsi_id = vf->vsi_res->vsi_id;
2138 list->num_elements = j;
2139 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2140 VIRTCHNL_OP_DEL_ETH_ADDR;
2141 args.in_args = (uint8_t *)list;
2142 args.in_args_size = len;
2143 args.out_buffer = vf->aq_resp;
2144 args.out_size = I40E_AQ_BUF_SZ;
2145 err = i40evf_execute_vf_cmd(dev, &args);
2147 PMD_DRV_LOG(ERR, "fail to execute command %s",
2148 add ? "OP_ADD_ETHER_ADDRESS" :
2149 "OP_DEL_ETHER_ADDRESS");
2158 } while (begin < I40E_NUM_MACADDR_MAX);
2162 i40evf_dev_start(struct rte_eth_dev *dev)
2164 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2167 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2168 uint32_t intr_vector = 0;
2170 PMD_INIT_FUNC_TRACE();
2172 hw->adapter_stopped = 0;
2174 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2175 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2176 dev->data->nb_tx_queues);
2178 /* check and configure queue intr-vector mapping */
2179 if (rte_intr_cap_multiple(intr_handle) &&
2180 dev->data->dev_conf.intr_conf.rxq) {
2181 intr_vector = dev->data->nb_rx_queues;
2182 if (rte_intr_efd_enable(intr_handle, intr_vector))
2186 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2187 intr_handle->intr_vec =
2188 rte_zmalloc("intr_vec",
2189 dev->data->nb_rx_queues * sizeof(int), 0);
2190 if (!intr_handle->intr_vec) {
2191 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2192 " intr_vec", dev->data->nb_rx_queues);
2197 if (i40evf_rx_init(dev) != 0){
2198 PMD_DRV_LOG(ERR, "failed to do RX init");
2202 i40evf_tx_init(dev);
2204 if (i40evf_configure_vsi_queues(dev) != 0) {
2205 PMD_DRV_LOG(ERR, "configure queues failed");
2208 if (i40evf_config_irq_map(dev)) {
2209 PMD_DRV_LOG(ERR, "config_irq_map failed");
2213 /* Set all mac addrs */
2214 i40evf_add_del_all_mac_addr(dev, TRUE);
2215 /* Set all multicast addresses */
2216 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2219 if (i40evf_start_queues(dev) != 0) {
2220 PMD_DRV_LOG(ERR, "enable queues failed");
2224 /* only enable interrupt in rx interrupt mode */
2225 if (dev->data->dev_conf.intr_conf.rxq != 0)
2226 rte_intr_enable(intr_handle);
2228 i40evf_enable_queues_intr(dev);
2233 i40evf_add_del_all_mac_addr(dev, FALSE);
2234 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2241 i40evf_dev_stop(struct rte_eth_dev *dev)
2243 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2244 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2248 PMD_INIT_FUNC_TRACE();
2250 if (dev->data->dev_conf.intr_conf.rxq != 0)
2251 rte_intr_disable(intr_handle);
2253 if (hw->adapter_stopped == 1)
2255 i40evf_stop_queues(dev);
2256 i40evf_disable_queues_intr(dev);
2257 i40e_dev_clear_queues(dev);
2259 /* Clean datapath event and queue/vec mapping */
2260 rte_intr_efd_disable(intr_handle);
2261 if (intr_handle->intr_vec) {
2262 rte_free(intr_handle->intr_vec);
2263 intr_handle->intr_vec = NULL;
2265 /* remove all mac addrs */
2266 i40evf_add_del_all_mac_addr(dev, FALSE);
2267 /* remove all multicast addresses */
2268 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2270 hw->adapter_stopped = 1;
2271 dev->data->dev_started = 0;
2277 i40evf_dev_link_update(struct rte_eth_dev *dev,
2278 __rte_unused int wait_to_complete)
2280 struct rte_eth_link new_link;
2281 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2283 * DPDK pf host provide interfacet to acquire link status
2284 * while Linux driver does not
2287 memset(&new_link, 0, sizeof(new_link));
2288 /* Linux driver PF host */
2289 switch (vf->link_speed) {
2290 case I40E_LINK_SPEED_100MB:
2291 new_link.link_speed = ETH_SPEED_NUM_100M;
2293 case I40E_LINK_SPEED_1GB:
2294 new_link.link_speed = ETH_SPEED_NUM_1G;
2296 case I40E_LINK_SPEED_10GB:
2297 new_link.link_speed = ETH_SPEED_NUM_10G;
2299 case I40E_LINK_SPEED_20GB:
2300 new_link.link_speed = ETH_SPEED_NUM_20G;
2302 case I40E_LINK_SPEED_25GB:
2303 new_link.link_speed = ETH_SPEED_NUM_25G;
2305 case I40E_LINK_SPEED_40GB:
2306 new_link.link_speed = ETH_SPEED_NUM_40G;
2310 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2312 new_link.link_speed = ETH_SPEED_NUM_NONE;
2315 /* full duplex only */
2316 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2317 new_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
2318 new_link.link_autoneg =
2319 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2321 return rte_eth_linkstatus_set(dev, &new_link);
2325 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2327 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2329 return i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);
2333 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2335 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2337 return i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);
2341 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2343 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2345 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);
2349 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2351 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2353 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);
2357 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2359 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2361 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2362 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2363 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2364 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2365 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2366 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2367 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2368 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2369 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2370 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2371 dev_info->rx_queue_offload_capa = 0;
2372 dev_info->rx_offload_capa =
2373 DEV_RX_OFFLOAD_VLAN_STRIP |
2374 DEV_RX_OFFLOAD_QINQ_STRIP |
2375 DEV_RX_OFFLOAD_IPV4_CKSUM |
2376 DEV_RX_OFFLOAD_UDP_CKSUM |
2377 DEV_RX_OFFLOAD_TCP_CKSUM |
2378 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2379 DEV_RX_OFFLOAD_SCATTER |
2380 DEV_RX_OFFLOAD_JUMBO_FRAME |
2381 DEV_RX_OFFLOAD_VLAN_FILTER;
2383 dev_info->tx_queue_offload_capa = 0;
2384 dev_info->tx_offload_capa =
2385 DEV_TX_OFFLOAD_VLAN_INSERT |
2386 DEV_TX_OFFLOAD_QINQ_INSERT |
2387 DEV_TX_OFFLOAD_IPV4_CKSUM |
2388 DEV_TX_OFFLOAD_UDP_CKSUM |
2389 DEV_TX_OFFLOAD_TCP_CKSUM |
2390 DEV_TX_OFFLOAD_SCTP_CKSUM |
2391 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2392 DEV_TX_OFFLOAD_TCP_TSO |
2393 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2394 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2395 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2396 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2397 DEV_TX_OFFLOAD_MULTI_SEGS;
2399 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2401 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2402 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2403 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2405 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2410 dev_info->default_txconf = (struct rte_eth_txconf) {
2412 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2413 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2414 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2416 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2417 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2421 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2422 .nb_max = I40E_MAX_RING_DESC,
2423 .nb_min = I40E_MIN_RING_DESC,
2424 .nb_align = I40E_ALIGN_RING_DESC,
2427 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2428 .nb_max = I40E_MAX_RING_DESC,
2429 .nb_min = I40E_MIN_RING_DESC,
2430 .nb_align = I40E_ALIGN_RING_DESC,
2437 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2440 struct i40e_eth_stats *pstats = NULL;
2441 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2442 struct i40e_vsi *vsi = &vf->vsi;
2444 ret = i40evf_query_stats(dev, &pstats);
2446 i40evf_update_stats(vsi, pstats);
2448 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2449 pstats->rx_broadcast;
2450 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2452 stats->imissed = pstats->rx_discards;
2453 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2454 stats->ibytes = pstats->rx_bytes;
2455 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
2456 stats->obytes = pstats->tx_bytes;
2458 PMD_DRV_LOG(ERR, "Get statistics failed");
2464 i40evf_dev_close(struct rte_eth_dev *dev)
2466 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2470 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2473 ret = i40evf_dev_stop(dev);
2475 i40e_dev_free_queues(dev);
2477 * disable promiscuous mode before reset vf
2478 * it is a workaround solution when work with kernel driver
2479 * and it is not the normal way
2481 if (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)
2482 i40evf_config_promisc(dev, false, false);
2484 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2486 i40evf_reset_vf(dev);
2487 i40e_shutdown_adminq(hw);
2488 i40evf_disable_irq0(hw);
2490 rte_free(vf->vf_res);
2492 rte_free(vf->aq_resp);
2495 hw->adapter_closed = 1;
2500 * Reset VF device only to re-initialize resources in PMD layer
2503 i40evf_dev_reset(struct rte_eth_dev *dev)
2507 ret = i40evf_dev_uninit(dev);
2511 ret = i40evf_dev_init(dev);
2517 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2519 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2520 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2526 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2527 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2530 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2534 uint32_t *lut_dw = (uint32_t *)lut;
2535 uint16_t i, lut_size_dw = lut_size / 4;
2537 for (i = 0; i < lut_size_dw; i++)
2538 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2545 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2554 vf = I40E_VSI_TO_VF(vsi);
2555 hw = I40E_VSI_TO_HW(vsi);
2557 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2558 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2561 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2565 uint32_t *lut_dw = (uint32_t *)lut;
2566 uint16_t i, lut_size_dw = lut_size / 4;
2568 for (i = 0; i < lut_size_dw; i++)
2569 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2570 I40EVF_WRITE_FLUSH(hw);
2577 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2578 struct rte_eth_rss_reta_entry64 *reta_conf,
2581 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2583 uint16_t i, idx, shift;
2586 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2587 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2588 "(%d) doesn't match the number of hardware can "
2589 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2593 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2595 PMD_DRV_LOG(ERR, "No memory can be allocated");
2598 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2601 for (i = 0; i < reta_size; i++) {
2602 idx = i / RTE_RETA_GROUP_SIZE;
2603 shift = i % RTE_RETA_GROUP_SIZE;
2604 if (reta_conf[idx].mask & (1ULL << shift))
2605 lut[i] = reta_conf[idx].reta[shift];
2607 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2616 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2617 struct rte_eth_rss_reta_entry64 *reta_conf,
2620 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2621 uint16_t i, idx, shift;
2625 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2626 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2627 "(%d) doesn't match the number of hardware can "
2628 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2632 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2634 PMD_DRV_LOG(ERR, "No memory can be allocated");
2638 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2641 for (i = 0; i < reta_size; i++) {
2642 idx = i / RTE_RETA_GROUP_SIZE;
2643 shift = i % RTE_RETA_GROUP_SIZE;
2644 if (reta_conf[idx].mask & (1ULL << shift))
2645 reta_conf[idx].reta[shift] = lut[i];
2655 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2657 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2658 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2661 if (!key || key_len == 0) {
2662 PMD_DRV_LOG(DEBUG, "No key to be configured");
2664 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2666 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2670 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2671 struct i40e_aqc_get_set_rss_key_data *key_dw =
2672 (struct i40e_aqc_get_set_rss_key_data *)key;
2674 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2676 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2679 uint32_t *hash_key = (uint32_t *)key;
2682 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2683 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2684 I40EVF_WRITE_FLUSH(hw);
2691 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2693 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2694 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2697 if (!key || !key_len)
2700 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2701 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2702 (struct i40e_aqc_get_set_rss_key_data *)key);
2704 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2708 uint32_t *key_dw = (uint32_t *)key;
2711 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2712 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2714 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2720 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2722 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2726 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2727 rss_conf->rss_key_len);
2731 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2732 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2733 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2734 I40EVF_WRITE_FLUSH(hw);
2740 i40evf_disable_rss(struct i40e_vf *vf)
2742 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2744 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2745 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2746 I40EVF_WRITE_FLUSH(hw);
2750 i40evf_config_rss(struct i40e_vf *vf)
2752 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2753 struct rte_eth_rss_conf rss_conf;
2754 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2755 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2760 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2761 i40evf_disable_rss(vf);
2762 PMD_DRV_LOG(DEBUG, "RSS not configured");
2766 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2767 /* Fill out the look up table */
2768 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2769 for (i = 0, j = 0; i < nb_q; i++, j++) {
2772 lut = (lut << 8) | j;
2774 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2777 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2779 PMD_DRV_LOG(ERR, "No memory can be allocated");
2783 for (i = 0; i < rss_lut_size; i++)
2784 lut_info[i] = i % num;
2786 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2793 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2794 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2795 i40evf_disable_rss(vf);
2796 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2800 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2801 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2802 /* Calculate the default hash key */
2803 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2804 rss_key_default[i] = (uint32_t)rte_rand();
2805 rss_conf.rss_key = (uint8_t *)rss_key_default;
2806 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2810 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2814 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2815 struct rte_eth_rss_conf *rss_conf)
2817 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2822 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2823 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2825 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2826 if (rss_hf != 0) /* Enable RSS */
2832 if (rss_hf == 0) /* Disable RSS */
2835 return i40evf_hw_rss_hash_set(vf, rss_conf);
2839 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2840 struct rte_eth_rss_conf *rss_conf)
2842 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2847 &rss_conf->rss_key_len);
2849 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2850 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2851 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2857 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2859 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2860 struct rte_eth_dev_data *dev_data = vf->dev_data;
2861 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2864 /* check if mtu is within the allowed range */
2865 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2868 /* mtu setting is forbidden if port is start */
2869 if (dev_data->dev_started) {
2870 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2875 if (frame_size > I40E_ETH_MAX_LEN)
2876 dev_data->dev_conf.rxmode.offloads |=
2877 DEV_RX_OFFLOAD_JUMBO_FRAME;
2879 dev_data->dev_conf.rxmode.offloads &=
2880 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2881 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2887 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2888 struct rte_ether_addr *mac_addr)
2890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891 struct rte_ether_addr *old_addr;
2894 old_addr = (struct rte_ether_addr *)hw->mac.addr;
2896 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2897 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2901 if (rte_is_same_ether_addr(old_addr, mac_addr))
2904 i40evf_add_del_eth_addr(dev, old_addr, FALSE, VIRTCHNL_ETHER_ADDR_PRIMARY);
2906 ret = i40evf_add_del_eth_addr(dev, mac_addr, TRUE, VIRTCHNL_ETHER_ADDR_PRIMARY);
2910 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2915 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2916 struct rte_ether_addr *mc_addrs,
2917 uint32_t mc_addrs_num, bool add)
2919 struct virtchnl_ether_addr_list *list;
2920 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2921 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2922 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2925 struct vf_cmd_info args;
2927 if (mc_addrs == NULL || mc_addrs_num == 0)
2930 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2933 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2934 list->vsi_id = vf->vsi_res->vsi_id;
2935 list->num_elements = mc_addrs_num;
2937 for (i = 0; i < mc_addrs_num; i++) {
2938 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2939 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2940 mc_addrs[i].addr_bytes[0],
2941 mc_addrs[i].addr_bytes[1],
2942 mc_addrs[i].addr_bytes[2],
2943 mc_addrs[i].addr_bytes[3],
2944 mc_addrs[i].addr_bytes[4],
2945 mc_addrs[i].addr_bytes[5]);
2949 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2950 sizeof(list->list[i].addr));
2951 list->list[i].type = VIRTCHNL_ETHER_ADDR_EXTRA;
2954 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2955 args.in_args = cmd_buffer;
2956 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2957 i * sizeof(struct virtchnl_ether_addr);
2958 args.out_buffer = vf->aq_resp;
2959 args.out_size = I40E_AQ_BUF_SZ;
2960 err = i40evf_execute_vf_cmd(dev, &args);
2962 PMD_DRV_LOG(ERR, "fail to execute command %s",
2963 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2971 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2972 struct rte_ether_addr *mc_addrs,
2973 uint32_t mc_addrs_num)
2975 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2978 /* flush previous addresses */
2979 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2984 vf->mc_addrs_num = 0;
2987 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2992 vf->mc_addrs_num = mc_addrs_num;
2993 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2999 is_i40evf_supported(struct rte_eth_dev *dev)
3001 return is_device_supported(dev, &rte_i40evf_pmd);