1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct rte_ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct rte_ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct rte_ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr);
144 /* Default hash key buffer for RSS */
145 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
147 struct rte_i40evf_xstats_name_off {
148 char name[RTE_ETH_XSTATS_NAME_SIZE];
152 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
153 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
154 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
155 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
156 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
157 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
158 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
159 rx_unknown_protocol)},
160 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
161 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
162 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
163 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
164 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
165 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
168 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
169 sizeof(rte_i40evf_stats_strings[0]))
171 static const struct eth_dev_ops i40evf_eth_dev_ops = {
172 .dev_configure = i40evf_dev_configure,
173 .dev_start = i40evf_dev_start,
174 .dev_stop = i40evf_dev_stop,
175 .promiscuous_enable = i40evf_dev_promiscuous_enable,
176 .promiscuous_disable = i40evf_dev_promiscuous_disable,
177 .allmulticast_enable = i40evf_dev_allmulticast_enable,
178 .allmulticast_disable = i40evf_dev_allmulticast_disable,
179 .link_update = i40evf_dev_link_update,
180 .stats_get = i40evf_dev_stats_get,
181 .stats_reset = i40evf_dev_xstats_reset,
182 .xstats_get = i40evf_dev_xstats_get,
183 .xstats_get_names = i40evf_dev_xstats_get_names,
184 .xstats_reset = i40evf_dev_xstats_reset,
185 .dev_close = i40evf_dev_close,
186 .dev_reset = i40evf_dev_reset,
187 .dev_infos_get = i40evf_dev_info_get,
188 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
189 .vlan_filter_set = i40evf_vlan_filter_set,
190 .vlan_offload_set = i40evf_vlan_offload_set,
191 .rx_queue_start = i40evf_dev_rx_queue_start,
192 .rx_queue_stop = i40evf_dev_rx_queue_stop,
193 .tx_queue_start = i40evf_dev_tx_queue_start,
194 .tx_queue_stop = i40evf_dev_tx_queue_stop,
195 .rx_queue_setup = i40e_dev_rx_queue_setup,
196 .rx_queue_release = i40e_dev_rx_queue_release,
197 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
198 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
199 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
200 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
201 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
202 .tx_queue_setup = i40e_dev_tx_queue_setup,
203 .tx_queue_release = i40e_dev_tx_queue_release,
204 .rx_queue_count = i40e_dev_rx_queue_count,
205 .rxq_info_get = i40e_rxq_info_get,
206 .txq_info_get = i40e_txq_info_get,
207 .mac_addr_add = i40evf_add_mac_addr,
208 .mac_addr_remove = i40evf_del_mac_addr,
209 .set_mc_addr_list = i40evf_set_mc_addr_list,
210 .reta_update = i40evf_dev_rss_reta_update,
211 .reta_query = i40evf_dev_rss_reta_query,
212 .rss_hash_update = i40evf_dev_rss_hash_update,
213 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
214 .mtu_set = i40evf_dev_mtu_set,
215 .mac_addr_set = i40evf_set_default_mac_addr,
219 * Read data in admin queue to get msg from pf driver
221 static enum i40evf_aq_result
222 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
224 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
225 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
226 struct i40e_arq_event_info event;
227 enum virtchnl_ops opcode;
228 enum i40e_status_code retval;
230 enum i40evf_aq_result result = I40EVF_MSG_NON;
232 event.buf_len = data->buf_len;
233 event.msg_buf = data->msg;
234 ret = i40e_clean_arq_element(hw, &event, NULL);
235 /* Can't read any msg from adminQ */
237 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
238 result = I40EVF_MSG_ERR;
242 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
243 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
245 if (opcode == VIRTCHNL_OP_EVENT) {
246 struct virtchnl_pf_event *vpe =
247 (struct virtchnl_pf_event *)event.msg_buf;
249 result = I40EVF_MSG_SYS;
250 switch (vpe->event) {
251 case VIRTCHNL_EVENT_LINK_CHANGE:
253 vpe->event_data.link_event.link_status;
255 vpe->event_data.link_event.link_speed;
256 vf->pend_msg |= PFMSG_LINK_CHANGE;
257 PMD_DRV_LOG(INFO, "Link status update:%s",
258 vf->link_up ? "up" : "down");
260 case VIRTCHNL_EVENT_RESET_IMPENDING:
262 vf->pend_msg |= PFMSG_RESET_IMPENDING;
263 PMD_DRV_LOG(INFO, "vf is reseting");
265 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
266 vf->dev_closed = true;
267 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
268 PMD_DRV_LOG(INFO, "PF driver closed");
271 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
272 __func__, vpe->event);
275 /* async reply msg on command issued by vf previously */
276 result = I40EVF_MSG_CMD;
277 /* Actual data length read from PF */
278 data->msg_len = event.msg_len;
281 data->result = retval;
288 * clear current command. Only call in case execute
289 * _atomic_set_cmd successfully.
292 _clear_cmd(struct i40e_vf *vf)
295 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
299 * Check there is pending cmd in execution. If none, set new command.
302 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
304 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
305 VIRTCHNL_OP_UNKNOWN, ops);
308 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
313 #define MAX_TRY_TIMES 200
314 #define ASQ_DELAY_MS 10
317 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
320 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
321 struct i40evf_arq_msg_info info;
322 enum i40evf_aq_result ret;
325 if (_atomic_set_cmd(vf, args->ops))
328 info.msg = args->out_buffer;
329 info.buf_len = args->out_size;
330 info.ops = VIRTCHNL_OP_UNKNOWN;
331 info.result = I40E_SUCCESS;
333 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
334 args->in_args, args->in_args_size, NULL);
336 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
342 case VIRTCHNL_OP_RESET_VF:
343 /*no need to process in this function */
346 case VIRTCHNL_OP_VERSION:
347 case VIRTCHNL_OP_GET_VF_RESOURCES:
348 /* for init adminq commands, need to poll the response */
351 ret = i40evf_read_pfmsg(dev, &info);
352 vf->cmd_retval = info.result;
353 if (ret == I40EVF_MSG_CMD) {
356 } else if (ret == I40EVF_MSG_ERR)
358 rte_delay_ms(ASQ_DELAY_MS);
359 /* If don't read msg or read sys event, continue */
360 } while (i++ < MAX_TRY_TIMES);
363 case VIRTCHNL_OP_REQUEST_QUEUES:
365 * ignore async reply, only wait for system message,
366 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
367 * if not, means request queues failed.
371 ret = i40evf_read_pfmsg(dev, &info);
372 vf->cmd_retval = info.result;
373 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
376 } else if (ret == I40EVF_MSG_ERR ||
377 ret == I40EVF_MSG_CMD) {
380 rte_delay_ms(ASQ_DELAY_MS);
381 /* If don't read msg or read sys event, continue */
382 } while (i++ < MAX_TRY_TIMES);
387 /* for other adminq in running time, waiting the cmd done flag */
390 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
394 rte_delay_ms(ASQ_DELAY_MS);
395 /* If don't read msg or read sys event, continue */
396 } while (i++ < MAX_TRY_TIMES);
397 /* If there's no response is received, clear command */
398 if (i >= MAX_TRY_TIMES) {
399 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
405 return err | vf->cmd_retval;
409 * Check API version with sync wait until version read or fail from admin queue
412 i40evf_check_api_version(struct rte_eth_dev *dev)
414 struct virtchnl_version_info version, *pver;
416 struct vf_cmd_info args;
417 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
419 version.major = VIRTCHNL_VERSION_MAJOR;
420 version.minor = VIRTCHNL_VERSION_MINOR;
422 args.ops = VIRTCHNL_OP_VERSION;
423 args.in_args = (uint8_t *)&version;
424 args.in_args_size = sizeof(version);
425 args.out_buffer = vf->aq_resp;
426 args.out_size = I40E_AQ_BUF_SZ;
428 err = i40evf_execute_vf_cmd(dev, &args);
430 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
434 pver = (struct virtchnl_version_info *)args.out_buffer;
435 vf->version_major = pver->major;
436 vf->version_minor = pver->minor;
437 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
438 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
439 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
441 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
442 vf->version_major, vf->version_minor,
443 VIRTCHNL_VERSION_MAJOR,
444 VIRTCHNL_VERSION_MINOR);
452 i40evf_get_vf_resource(struct rte_eth_dev *dev)
454 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
455 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
457 struct vf_cmd_info args;
460 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
461 args.out_buffer = vf->aq_resp;
462 args.out_size = I40E_AQ_BUF_SZ;
464 caps = VIRTCHNL_VF_OFFLOAD_L2 |
465 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
466 VIRTCHNL_VF_OFFLOAD_RSS_REG |
467 VIRTCHNL_VF_OFFLOAD_VLAN |
468 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
469 args.in_args = (uint8_t *)∩︀
470 args.in_args_size = sizeof(caps);
473 args.in_args_size = 0;
475 err = i40evf_execute_vf_cmd(dev, &args);
478 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
482 len = sizeof(struct virtchnl_vf_resource) +
483 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
485 rte_memcpy(vf->vf_res, args.out_buffer,
486 RTE_MIN(args.out_size, len));
487 i40e_vf_parse_hw_config(hw, vf->vf_res);
493 i40evf_config_promisc(struct rte_eth_dev *dev,
495 bool enable_multicast)
497 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
499 struct vf_cmd_info args;
500 struct virtchnl_promisc_info promisc;
503 promisc.vsi_id = vf->vsi_res->vsi_id;
506 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
508 if (enable_multicast)
509 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
511 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
512 args.in_args = (uint8_t *)&promisc;
513 args.in_args_size = sizeof(promisc);
514 args.out_buffer = vf->aq_resp;
515 args.out_size = I40E_AQ_BUF_SZ;
517 err = i40evf_execute_vf_cmd(dev, &args);
520 PMD_DRV_LOG(ERR, "fail to execute command "
521 "CONFIG_PROMISCUOUS_MODE");
526 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
528 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
529 struct vf_cmd_info args;
532 memset(&args, 0, sizeof(args));
533 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
535 args.in_args_size = 0;
536 args.out_buffer = vf->aq_resp;
537 args.out_size = I40E_AQ_BUF_SZ;
538 ret = i40evf_execute_vf_cmd(dev, &args);
540 PMD_DRV_LOG(ERR, "Failed to execute command of "
541 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
547 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
549 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
550 struct vf_cmd_info args;
553 memset(&args, 0, sizeof(args));
554 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
556 args.in_args_size = 0;
557 args.out_buffer = vf->aq_resp;
558 args.out_size = I40E_AQ_BUF_SZ;
559 ret = i40evf_execute_vf_cmd(dev, &args);
561 PMD_DRV_LOG(ERR, "Failed to execute command of "
562 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
568 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
572 struct i40e_tx_queue *txq)
574 txq_info->vsi_id = vsi_id;
575 txq_info->queue_id = queue_id;
576 if (queue_id < nb_txq && txq) {
577 txq_info->ring_len = txq->nb_tx_desc;
578 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
583 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
587 uint32_t max_pkt_size,
588 struct i40e_rx_queue *rxq)
590 rxq_info->vsi_id = vsi_id;
591 rxq_info->queue_id = queue_id;
592 rxq_info->max_pkt_size = max_pkt_size;
593 if (queue_id < nb_rxq && rxq) {
594 rxq_info->ring_len = rxq->nb_rx_desc;
595 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
596 rxq_info->databuffer_size =
597 (rte_pktmbuf_data_room_size(rxq->mp) -
598 RTE_PKTMBUF_HEADROOM);
603 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
605 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
606 struct i40e_rx_queue **rxq =
607 (struct i40e_rx_queue **)dev->data->rx_queues;
608 struct i40e_tx_queue **txq =
609 (struct i40e_tx_queue **)dev->data->tx_queues;
610 struct virtchnl_vsi_queue_config_info *vc_vqci;
611 struct virtchnl_queue_pair_info *vc_qpi;
612 struct vf_cmd_info args;
613 uint16_t i, nb_qp = vf->num_queue_pairs;
614 const uint32_t size =
615 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
619 memset(buff, 0, sizeof(buff));
620 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
621 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
622 vc_vqci->num_queue_pairs = nb_qp;
624 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
625 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
626 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
627 txq ? txq[i] : NULL);
628 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
629 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
630 vf->max_pkt_len, rxq ? rxq[i] : NULL);
632 memset(&args, 0, sizeof(args));
633 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
634 args.in_args = (uint8_t *)vc_vqci;
635 args.in_args_size = size;
636 args.out_buffer = vf->aq_resp;
637 args.out_size = I40E_AQ_BUF_SZ;
638 ret = i40evf_execute_vf_cmd(dev, &args);
640 PMD_DRV_LOG(ERR, "Failed to execute command of "
641 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
647 i40evf_config_irq_map(struct rte_eth_dev *dev)
649 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
650 struct vf_cmd_info args;
651 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
652 sizeof(struct virtchnl_vector_map)];
653 struct virtchnl_irq_map_info *map_info;
654 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
655 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
659 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
660 rte_intr_allow_others(intr_handle))
661 vector_id = I40E_RX_VEC_START;
663 vector_id = I40E_MISC_VEC_ID;
665 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
666 map_info->num_vectors = 1;
667 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
668 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
669 /* Alway use default dynamic MSIX interrupt */
670 map_info->vecmap[0].vector_id = vector_id;
671 /* Don't map any tx queue */
672 map_info->vecmap[0].txq_map = 0;
673 map_info->vecmap[0].rxq_map = 0;
674 for (i = 0; i < dev->data->nb_rx_queues; i++) {
675 map_info->vecmap[0].rxq_map |= 1 << i;
676 if (rte_intr_dp_is_en(intr_handle))
677 intr_handle->intr_vec[i] = vector_id;
680 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
681 args.in_args = (u8 *)cmd_buffer;
682 args.in_args_size = sizeof(cmd_buffer);
683 args.out_buffer = vf->aq_resp;
684 args.out_size = I40E_AQ_BUF_SZ;
685 err = i40evf_execute_vf_cmd(dev, &args);
687 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
693 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
696 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
697 struct virtchnl_queue_select queue_select;
699 struct vf_cmd_info args;
700 memset(&queue_select, 0, sizeof(queue_select));
701 queue_select.vsi_id = vf->vsi_res->vsi_id;
704 queue_select.rx_queues |= 1 << qid;
706 queue_select.tx_queues |= 1 << qid;
709 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
711 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
712 args.in_args = (u8 *)&queue_select;
713 args.in_args_size = sizeof(queue_select);
714 args.out_buffer = vf->aq_resp;
715 args.out_size = I40E_AQ_BUF_SZ;
716 err = i40evf_execute_vf_cmd(dev, &args);
718 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
719 isrx ? "RX" : "TX", qid, on ? "on" : "off");
725 i40evf_start_queues(struct rte_eth_dev *dev)
727 struct rte_eth_dev_data *dev_data = dev->data;
729 struct i40e_rx_queue *rxq;
730 struct i40e_tx_queue *txq;
732 for (i = 0; i < dev->data->nb_rx_queues; i++) {
733 rxq = dev_data->rx_queues[i];
734 if (rxq->rx_deferred_start)
736 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
737 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
742 for (i = 0; i < dev->data->nb_tx_queues; i++) {
743 txq = dev_data->tx_queues[i];
744 if (txq->tx_deferred_start)
746 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
747 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
756 i40evf_stop_queues(struct rte_eth_dev *dev)
760 /* Stop TX queues first */
761 for (i = 0; i < dev->data->nb_tx_queues; i++) {
762 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
763 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
768 /* Then stop RX queues */
769 for (i = 0; i < dev->data->nb_rx_queues; i++) {
770 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
771 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
780 i40evf_add_mac_addr(struct rte_eth_dev *dev,
781 struct rte_ether_addr *addr,
782 __rte_unused uint32_t index,
783 __rte_unused uint32_t pool)
785 struct virtchnl_ether_addr_list *list;
786 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
787 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
788 sizeof(struct virtchnl_ether_addr)];
790 struct vf_cmd_info args;
792 if (rte_is_zero_ether_addr(addr)) {
793 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
794 addr->addr_bytes[0], addr->addr_bytes[1],
795 addr->addr_bytes[2], addr->addr_bytes[3],
796 addr->addr_bytes[4], addr->addr_bytes[5]);
797 return I40E_ERR_INVALID_MAC_ADDR;
800 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
801 list->vsi_id = vf->vsi_res->vsi_id;
802 list->num_elements = 1;
803 rte_memcpy(list->list[0].addr, addr->addr_bytes,
804 sizeof(addr->addr_bytes));
806 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
807 args.in_args = cmd_buffer;
808 args.in_args_size = sizeof(cmd_buffer);
809 args.out_buffer = vf->aq_resp;
810 args.out_size = I40E_AQ_BUF_SZ;
811 err = i40evf_execute_vf_cmd(dev, &args);
813 PMD_DRV_LOG(ERR, "fail to execute command "
814 "OP_ADD_ETHER_ADDRESS");
822 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
823 struct rte_ether_addr *addr)
825 struct virtchnl_ether_addr_list *list;
826 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
827 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
828 sizeof(struct virtchnl_ether_addr)];
830 struct vf_cmd_info args;
832 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
833 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
834 addr->addr_bytes[0], addr->addr_bytes[1],
835 addr->addr_bytes[2], addr->addr_bytes[3],
836 addr->addr_bytes[4], addr->addr_bytes[5]);
840 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
841 list->vsi_id = vf->vsi_res->vsi_id;
842 list->num_elements = 1;
843 rte_memcpy(list->list[0].addr, addr->addr_bytes,
844 sizeof(addr->addr_bytes));
846 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
847 args.in_args = cmd_buffer;
848 args.in_args_size = sizeof(cmd_buffer);
849 args.out_buffer = vf->aq_resp;
850 args.out_size = I40E_AQ_BUF_SZ;
851 err = i40evf_execute_vf_cmd(dev, &args);
853 PMD_DRV_LOG(ERR, "fail to execute command "
854 "OP_DEL_ETHER_ADDRESS");
861 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
863 struct rte_eth_dev_data *data = dev->data;
864 struct rte_ether_addr *addr;
866 addr = &data->mac_addrs[index];
868 i40evf_del_mac_addr_by_addr(dev, addr);
872 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
874 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
875 struct virtchnl_queue_select q_stats;
877 struct vf_cmd_info args;
879 memset(&q_stats, 0, sizeof(q_stats));
880 q_stats.vsi_id = vf->vsi_res->vsi_id;
881 args.ops = VIRTCHNL_OP_GET_STATS;
882 args.in_args = (u8 *)&q_stats;
883 args.in_args_size = sizeof(q_stats);
884 args.out_buffer = vf->aq_resp;
885 args.out_size = I40E_AQ_BUF_SZ;
887 err = i40evf_execute_vf_cmd(dev, &args);
889 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
893 *pstats = (struct i40e_eth_stats *)args.out_buffer;
898 i40evf_stat_update_48(uint64_t *offset,
901 if (*stat >= *offset)
902 *stat = *stat - *offset;
904 *stat = (uint64_t)((*stat +
905 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
907 *stat &= I40E_48_BIT_MASK;
911 i40evf_stat_update_32(uint64_t *offset,
914 if (*stat >= *offset)
915 *stat = (uint64_t)(*stat - *offset);
917 *stat = (uint64_t)((*stat +
918 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
922 i40evf_update_stats(struct i40e_vsi *vsi,
923 struct i40e_eth_stats *nes)
925 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
927 i40evf_stat_update_48(&oes->rx_bytes,
929 i40evf_stat_update_48(&oes->rx_unicast,
931 i40evf_stat_update_48(&oes->rx_multicast,
933 i40evf_stat_update_48(&oes->rx_broadcast,
935 i40evf_stat_update_32(&oes->rx_discards,
937 i40evf_stat_update_32(&oes->rx_unknown_protocol,
938 &nes->rx_unknown_protocol);
939 i40evf_stat_update_48(&oes->tx_bytes,
941 i40evf_stat_update_48(&oes->tx_unicast,
943 i40evf_stat_update_48(&oes->tx_multicast,
945 i40evf_stat_update_48(&oes->tx_broadcast,
947 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
948 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
952 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
955 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
956 struct i40e_eth_stats *pstats = NULL;
958 /* read stat values to clear hardware registers */
959 ret = i40evf_query_stats(dev, &pstats);
961 /* set stats offset base on current values */
963 vf->vsi.eth_stats_offset = *pstats;
966 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
967 struct rte_eth_xstat_name *xstats_names,
968 __rte_unused unsigned limit)
972 if (xstats_names != NULL)
973 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
974 snprintf(xstats_names[i].name,
975 sizeof(xstats_names[i].name),
976 "%s", rte_i40evf_stats_strings[i].name);
978 return I40EVF_NB_XSTATS;
981 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
982 struct rte_eth_xstat *xstats, unsigned n)
986 struct i40e_eth_stats *pstats = NULL;
987 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
988 struct i40e_vsi *vsi = &vf->vsi;
990 if (n < I40EVF_NB_XSTATS)
991 return I40EVF_NB_XSTATS;
993 ret = i40evf_query_stats(dev, &pstats);
1000 i40evf_update_stats(vsi, pstats);
1002 /* loop over xstats array and values from pstats */
1003 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1005 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1006 rte_i40evf_stats_strings[i].offset);
1009 return I40EVF_NB_XSTATS;
1013 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1015 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1016 struct virtchnl_vlan_filter_list *vlan_list;
1017 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1020 struct vf_cmd_info args;
1022 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1023 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1024 vlan_list->num_elements = 1;
1025 vlan_list->vlan_id[0] = vlanid;
1027 args.ops = VIRTCHNL_OP_ADD_VLAN;
1028 args.in_args = (u8 *)&cmd_buffer;
1029 args.in_args_size = sizeof(cmd_buffer);
1030 args.out_buffer = vf->aq_resp;
1031 args.out_size = I40E_AQ_BUF_SZ;
1032 err = i40evf_execute_vf_cmd(dev, &args);
1034 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1040 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1042 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1043 struct virtchnl_vf_res_request vfres;
1044 struct vf_cmd_info args;
1047 vfres.num_queue_pairs = num;
1049 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1050 args.in_args = (u8 *)&vfres;
1051 args.in_args_size = sizeof(vfres);
1052 args.out_buffer = vf->aq_resp;
1053 args.out_size = I40E_AQ_BUF_SZ;
1054 err = i40evf_execute_vf_cmd(dev, &args);
1056 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1062 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1064 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1065 struct virtchnl_vlan_filter_list *vlan_list;
1066 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1069 struct vf_cmd_info args;
1071 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1072 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1073 vlan_list->num_elements = 1;
1074 vlan_list->vlan_id[0] = vlanid;
1076 args.ops = VIRTCHNL_OP_DEL_VLAN;
1077 args.in_args = (u8 *)&cmd_buffer;
1078 args.in_args_size = sizeof(cmd_buffer);
1079 args.out_buffer = vf->aq_resp;
1080 args.out_size = I40E_AQ_BUF_SZ;
1081 err = i40evf_execute_vf_cmd(dev, &args);
1083 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1088 static const struct rte_pci_id pci_id_i40evf_map[] = {
1089 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1090 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1091 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1092 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1093 { .vendor_id = 0, /* sentinel */ },
1098 i40evf_disable_irq0(struct i40e_hw *hw)
1100 /* Disable all interrupt types */
1101 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1102 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1103 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1104 I40EVF_WRITE_FLUSH(hw);
1109 i40evf_enable_irq0(struct i40e_hw *hw)
1111 /* Enable admin queue interrupt trigger */
1114 i40evf_disable_irq0(hw);
1115 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1116 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1117 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1118 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1120 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1121 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1122 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1123 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1125 I40EVF_WRITE_FLUSH(hw);
1129 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1133 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1135 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1136 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1137 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1138 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1139 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1140 reset == VIRTCHNL_VFR_COMPLETED)
1145 if (i >= MAX_RESET_WAIT_CNT)
1148 vf->vf_reset = false;
1149 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1154 i40evf_reset_vf(struct rte_eth_dev *dev)
1157 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1164 * After issuing vf reset command to pf, pf won't necessarily
1165 * reset vf, it depends on what state it exactly is. If it's not
1166 * initialized yet, it won't have vf reset since it's in a certain
1167 * state. If not, it will try to reset. Even vf is reset, pf will
1168 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1169 * it to ACTIVE. In this duration, vf may not catch the moment that
1170 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1174 ret = i40evf_check_vf_reset_done(dev);
1176 PMD_INIT_LOG(ERR, "VF is still resetting");
1184 i40evf_init_vf(struct rte_eth_dev *dev)
1187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1190 i40e_calc_itr_interval(0, 0);
1192 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1193 vf->dev_data = dev->data;
1194 err = i40e_set_mac_type(hw);
1196 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1200 err = i40evf_check_vf_reset_done(dev);
1204 i40e_init_adminq_parameter(hw);
1205 err = i40e_init_adminq(hw);
1207 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1211 /* Reset VF and wait until it's complete */
1212 if (i40evf_reset_vf(dev)) {
1213 PMD_INIT_LOG(ERR, "reset NIC failed");
1217 /* VF reset, shutdown admin queue and initialize again */
1218 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1219 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1223 i40e_init_adminq_parameter(hw);
1224 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1225 PMD_INIT_LOG(ERR, "init_adminq failed");
1229 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1231 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1234 if (i40evf_check_api_version(dev) != 0) {
1235 PMD_INIT_LOG(ERR, "check_api version failed");
1238 bufsz = sizeof(struct virtchnl_vf_resource) +
1239 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1240 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1242 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1246 if (i40evf_get_vf_resource(dev) != 0) {
1247 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1251 /* got VF config message back from PF, now we can parse it */
1252 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1253 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1254 vf->vsi_res = &vf->vf_res->vsi_res[i];
1258 PMD_INIT_LOG(ERR, "no LAN VSI found");
1262 if (hw->mac.type == I40E_MAC_X722_VF)
1263 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1264 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1266 switch (vf->vsi_res->vsi_type) {
1267 case VIRTCHNL_VSI_SRIOV:
1268 vf->vsi.type = I40E_VSI_SRIOV;
1271 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1274 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1275 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1277 /* Store the MAC address configured by host, or generate random one */
1278 if (rte_is_valid_assigned_ether_addr(
1279 (struct rte_ether_addr *)hw->mac.addr))
1280 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1282 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1284 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1285 (I40E_ITR_INDEX_DEFAULT <<
1286 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1288 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1289 I40EVF_WRITE_FLUSH(hw);
1294 rte_free(vf->vf_res);
1297 rte_free(vf->aq_resp);
1299 i40e_shutdown_adminq(hw); /* ignore error */
1305 i40evf_uninit_vf(struct rte_eth_dev *dev)
1307 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1308 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310 PMD_INIT_FUNC_TRACE();
1312 if (hw->adapter_closed == 0)
1313 i40evf_dev_close(dev);
1314 rte_free(vf->vf_res);
1316 rte_free(vf->aq_resp);
1323 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1324 __rte_unused uint16_t msglen)
1326 struct virtchnl_pf_event *pf_msg =
1327 (struct virtchnl_pf_event *)msg;
1328 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1330 switch (pf_msg->event) {
1331 case VIRTCHNL_EVENT_RESET_IMPENDING:
1332 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1333 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1336 case VIRTCHNL_EVENT_LINK_CHANGE:
1337 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1338 vf->link_up = pf_msg->event_data.link_event.link_status;
1339 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1341 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1342 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1345 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1351 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1355 struct i40e_arq_event_info info;
1356 uint16_t pending, aq_opc;
1357 enum virtchnl_ops msg_opc;
1358 enum i40e_status_code msg_ret;
1361 info.buf_len = I40E_AQ_BUF_SZ;
1363 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1366 info.msg_buf = vf->aq_resp;
1370 ret = i40e_clean_arq_element(hw, &info, &pending);
1372 if (ret != I40E_SUCCESS) {
1373 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1377 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1378 /* For the message sent from pf to vf, opcode is stored in
1379 * cookie_high of struct i40e_aq_desc, while return error code
1380 * are stored in cookie_low, Which is done by
1381 * i40e_aq_send_msg_to_vf in PF driver.*/
1382 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1383 info.desc.cookie_high);
1384 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1385 info.desc.cookie_low);
1387 case i40e_aqc_opc_send_msg_to_vf:
1388 if (msg_opc == VIRTCHNL_OP_EVENT)
1390 i40evf_handle_pf_event(dev, info.msg_buf,
1393 /* read message and it's expected one */
1394 if (msg_opc == vf->pend_cmd) {
1395 vf->cmd_retval = msg_ret;
1396 /* prevent compiler reordering */
1397 rte_compiler_barrier();
1400 PMD_DRV_LOG(ERR, "command mismatch,"
1401 "expect %u, get %u",
1402 vf->pend_cmd, msg_opc);
1403 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1404 " opcode = %d", msg_opc);
1408 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1416 * Interrupt handler triggered by NIC for handling
1417 * specific interrupt. Only adminq interrupt is processed in VF.
1420 * Pointer to interrupt handle.
1422 * The address of parameter (struct rte_eth_dev *) regsitered before.
1428 i40evf_dev_alarm_handler(void *param)
1430 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1434 i40evf_disable_irq0(hw);
1436 /* read out interrupt causes */
1437 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1439 /* No interrupt event indicated */
1440 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1443 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1444 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1445 i40evf_handle_aq_msg(dev);
1448 /* Link Status Change interrupt */
1449 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1450 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1454 i40evf_enable_irq0(hw);
1455 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1456 i40evf_dev_alarm_handler, dev);
1460 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1463 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1466 PMD_INIT_FUNC_TRACE();
1468 /* assign ops func pointer */
1469 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1470 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1471 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1474 * For secondary processes, we don't initialise any further as primary
1475 * has already done this work.
1477 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1478 i40e_set_rx_function(eth_dev);
1479 i40e_set_tx_function(eth_dev);
1482 i40e_set_default_ptype_table(eth_dev);
1483 i40e_set_default_pctype_table(eth_dev);
1484 rte_eth_copy_pci_info(eth_dev, pci_dev);
1486 hw->vendor_id = pci_dev->id.vendor_id;
1487 hw->device_id = pci_dev->id.device_id;
1488 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1489 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1490 hw->bus.device = pci_dev->addr.devid;
1491 hw->bus.func = pci_dev->addr.function;
1492 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1493 hw->adapter_stopped = 0;
1494 hw->adapter_closed = 0;
1496 if(i40evf_init_vf(eth_dev) != 0) {
1497 PMD_INIT_LOG(ERR, "Init vf failed");
1501 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1502 i40evf_dev_alarm_handler, eth_dev);
1504 /* configure and enable device interrupt */
1505 i40evf_enable_irq0(hw);
1508 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1509 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1511 if (eth_dev->data->mac_addrs == NULL) {
1512 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1513 " store MAC addresses",
1514 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1517 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1518 ð_dev->data->mac_addrs[0]);
1524 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1526 PMD_INIT_FUNC_TRACE();
1528 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1531 eth_dev->dev_ops = NULL;
1532 eth_dev->rx_pkt_burst = NULL;
1533 eth_dev->tx_pkt_burst = NULL;
1535 if (i40evf_uninit_vf(eth_dev) != 0) {
1536 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1543 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1544 struct rte_pci_device *pci_dev)
1546 return rte_eth_dev_pci_generic_probe(pci_dev,
1547 sizeof(struct i40e_adapter), i40evf_dev_init);
1550 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1552 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1556 * virtual function driver struct
1558 static struct rte_pci_driver rte_i40evf_pmd = {
1559 .id_table = pci_id_i40evf_map,
1560 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1561 .probe = eth_i40evf_pci_probe,
1562 .remove = eth_i40evf_pci_remove,
1565 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1566 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1567 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1570 i40evf_dev_configure(struct rte_eth_dev *dev)
1572 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1573 struct i40e_adapter *ad =
1574 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1575 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1576 dev->data->nb_tx_queues);
1578 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1579 * allocation or vector Rx preconditions we will reset it.
1581 ad->rx_bulk_alloc_allowed = true;
1582 ad->rx_vec_allowed = true;
1583 ad->tx_simple_allowed = true;
1584 ad->tx_vec_allowed = true;
1586 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1589 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1590 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1591 ret = i40evf_request_queues(dev, num_queue_pairs);
1595 ret = i40evf_dev_reset(dev);
1600 return i40evf_init_vlan(dev);
1604 i40evf_init_vlan(struct rte_eth_dev *dev)
1606 /* Apply vlan offload setting */
1607 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1613 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1615 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1616 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1618 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1621 /* Vlan stripping setting */
1622 if (mask & ETH_VLAN_STRIP_MASK) {
1623 /* Enable or disable VLAN stripping */
1624 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1625 i40evf_enable_vlan_strip(dev);
1627 i40evf_disable_vlan_strip(dev);
1634 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1636 struct i40e_rx_queue *rxq;
1638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640 PMD_INIT_FUNC_TRACE();
1642 rxq = dev->data->rx_queues[rx_queue_id];
1644 err = i40e_alloc_rx_queue_mbufs(rxq);
1646 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1652 /* Init the RX tail register. */
1653 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1654 I40EVF_WRITE_FLUSH(hw);
1656 /* Ready to switch the queue on */
1657 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1659 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1663 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1669 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1671 struct i40e_rx_queue *rxq;
1674 rxq = dev->data->rx_queues[rx_queue_id];
1676 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1678 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1683 i40e_rx_queue_release_mbufs(rxq);
1684 i40e_reset_rx_queue(rxq);
1685 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1691 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1695 PMD_INIT_FUNC_TRACE();
1697 /* Ready to switch the queue on */
1698 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1700 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1704 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1710 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1712 struct i40e_tx_queue *txq;
1715 txq = dev->data->tx_queues[tx_queue_id];
1717 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1719 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1724 i40e_tx_queue_release_mbufs(txq);
1725 i40e_reset_tx_queue(txq);
1726 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1732 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1737 ret = i40evf_add_vlan(dev, vlan_id);
1739 ret = i40evf_del_vlan(dev,vlan_id);
1745 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1747 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 struct rte_eth_dev_data *dev_data = dev->data;
1749 struct rte_pktmbuf_pool_private *mbp_priv;
1750 uint16_t buf_size, len;
1752 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1753 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1754 I40EVF_WRITE_FLUSH(hw);
1756 /* Calculate the maximum packet length allowed */
1757 mbp_priv = rte_mempool_get_priv(rxq->mp);
1758 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1759 RTE_PKTMBUF_HEADROOM);
1760 rxq->hs_mode = i40e_header_split_none;
1761 rxq->rx_hdr_len = 0;
1762 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1763 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1764 rxq->max_pkt_len = RTE_MIN(len,
1765 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1768 * Check if the jumbo frame and maximum packet length are set correctly
1770 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1771 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1772 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1773 PMD_DRV_LOG(ERR, "maximum packet length must be "
1774 "larger than %u and smaller than %u, as jumbo "
1775 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1776 (uint32_t)I40E_FRAME_SIZE_MAX);
1777 return I40E_ERR_CONFIG;
1780 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1781 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1782 PMD_DRV_LOG(ERR, "maximum packet length must be "
1783 "larger than %u and smaller than %u, as jumbo "
1784 "frame is disabled",
1785 (uint32_t)RTE_ETHER_MIN_LEN,
1786 (uint32_t)RTE_ETHER_MAX_LEN);
1787 return I40E_ERR_CONFIG;
1791 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1792 rxq->max_pkt_len > buf_size)
1793 dev_data->scattered_rx = 1;
1799 i40evf_rx_init(struct rte_eth_dev *dev)
1801 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1803 int ret = I40E_SUCCESS;
1804 struct i40e_rx_queue **rxq =
1805 (struct i40e_rx_queue **)dev->data->rx_queues;
1807 i40evf_config_rss(vf);
1808 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1809 if (!rxq[i] || !rxq[i]->q_set)
1811 ret = i40evf_rxq_init(dev, rxq[i]);
1812 if (ret != I40E_SUCCESS)
1815 if (ret == I40E_SUCCESS)
1816 i40e_set_rx_function(dev);
1822 i40evf_tx_init(struct rte_eth_dev *dev)
1825 struct i40e_tx_queue **txq =
1826 (struct i40e_tx_queue **)dev->data->tx_queues;
1827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829 for (i = 0; i < dev->data->nb_tx_queues; i++)
1830 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1832 i40e_set_tx_function(dev);
1836 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1840 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1842 if (!rte_intr_allow_others(intr_handle)) {
1844 I40E_VFINT_DYN_CTL01,
1845 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1846 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1847 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1848 I40EVF_WRITE_FLUSH(hw);
1852 I40EVF_WRITE_FLUSH(hw);
1856 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1860 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1862 if (!rte_intr_allow_others(intr_handle)) {
1863 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1864 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1865 I40EVF_WRITE_FLUSH(hw);
1869 I40EVF_WRITE_FLUSH(hw);
1873 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1875 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1876 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1877 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879 i40e_calc_itr_interval(0, 0);
1882 msix_intr = intr_handle->intr_vec[queue_id];
1883 if (msix_intr == I40E_MISC_VEC_ID)
1884 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1885 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1886 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1887 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1889 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1892 I40E_VFINT_DYN_CTLN1(msix_intr -
1894 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1895 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1896 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1898 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1900 I40EVF_WRITE_FLUSH(hw);
1906 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1908 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1909 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 msix_intr = intr_handle->intr_vec[queue_id];
1914 if (msix_intr == I40E_MISC_VEC_ID)
1915 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1918 I40E_VFINT_DYN_CTLN1(msix_intr -
1922 I40EVF_WRITE_FLUSH(hw);
1928 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1930 struct virtchnl_ether_addr_list *list;
1931 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1936 struct rte_ether_addr *addr;
1937 struct vf_cmd_info args;
1941 len = sizeof(struct virtchnl_ether_addr_list);
1942 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1943 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
1945 len += sizeof(struct virtchnl_ether_addr);
1946 if (len >= I40E_AQ_BUF_SZ) {
1952 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1954 PMD_DRV_LOG(ERR, "fail to allocate memory");
1958 for (i = begin; i < next_begin; i++) {
1959 addr = &dev->data->mac_addrs[i];
1960 if (rte_is_zero_ether_addr(addr))
1962 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1963 sizeof(addr->addr_bytes));
1964 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1965 addr->addr_bytes[0], addr->addr_bytes[1],
1966 addr->addr_bytes[2], addr->addr_bytes[3],
1967 addr->addr_bytes[4], addr->addr_bytes[5]);
1970 list->vsi_id = vf->vsi_res->vsi_id;
1971 list->num_elements = j;
1972 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1973 VIRTCHNL_OP_DEL_ETH_ADDR;
1974 args.in_args = (uint8_t *)list;
1975 args.in_args_size = len;
1976 args.out_buffer = vf->aq_resp;
1977 args.out_size = I40E_AQ_BUF_SZ;
1978 err = i40evf_execute_vf_cmd(dev, &args);
1980 PMD_DRV_LOG(ERR, "fail to execute command %s",
1981 add ? "OP_ADD_ETHER_ADDRESS" :
1982 "OP_DEL_ETHER_ADDRESS");
1991 } while (begin < I40E_NUM_MACADDR_MAX);
1995 i40evf_dev_start(struct rte_eth_dev *dev)
1997 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2000 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2001 uint32_t intr_vector = 0;
2003 PMD_INIT_FUNC_TRACE();
2005 hw->adapter_stopped = 0;
2007 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2008 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2009 dev->data->nb_tx_queues);
2011 /* check and configure queue intr-vector mapping */
2012 if (rte_intr_cap_multiple(intr_handle) &&
2013 dev->data->dev_conf.intr_conf.rxq) {
2014 intr_vector = dev->data->nb_rx_queues;
2015 if (rte_intr_efd_enable(intr_handle, intr_vector))
2019 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2020 intr_handle->intr_vec =
2021 rte_zmalloc("intr_vec",
2022 dev->data->nb_rx_queues * sizeof(int), 0);
2023 if (!intr_handle->intr_vec) {
2024 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2025 " intr_vec", dev->data->nb_rx_queues);
2030 if (i40evf_rx_init(dev) != 0){
2031 PMD_DRV_LOG(ERR, "failed to do RX init");
2035 i40evf_tx_init(dev);
2037 if (i40evf_configure_vsi_queues(dev) != 0) {
2038 PMD_DRV_LOG(ERR, "configure queues failed");
2041 if (i40evf_config_irq_map(dev)) {
2042 PMD_DRV_LOG(ERR, "config_irq_map failed");
2046 /* Set all mac addrs */
2047 i40evf_add_del_all_mac_addr(dev, TRUE);
2048 /* Set all multicast addresses */
2049 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2052 if (i40evf_start_queues(dev) != 0) {
2053 PMD_DRV_LOG(ERR, "enable queues failed");
2057 /* only enable interrupt in rx interrupt mode */
2058 if (dev->data->dev_conf.intr_conf.rxq != 0)
2059 rte_intr_enable(intr_handle);
2061 i40evf_enable_queues_intr(dev);
2066 i40evf_add_del_all_mac_addr(dev, FALSE);
2067 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2074 i40evf_dev_stop(struct rte_eth_dev *dev)
2076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2077 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2081 PMD_INIT_FUNC_TRACE();
2083 if (dev->data->dev_conf.intr_conf.rxq != 0)
2084 rte_intr_disable(intr_handle);
2086 if (hw->adapter_stopped == 1)
2088 i40evf_stop_queues(dev);
2089 i40evf_disable_queues_intr(dev);
2090 i40e_dev_clear_queues(dev);
2092 /* Clean datapath event and queue/vec mapping */
2093 rte_intr_efd_disable(intr_handle);
2094 if (intr_handle->intr_vec) {
2095 rte_free(intr_handle->intr_vec);
2096 intr_handle->intr_vec = NULL;
2098 /* remove all mac addrs */
2099 i40evf_add_del_all_mac_addr(dev, FALSE);
2100 /* remove all multicast addresses */
2101 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2103 hw->adapter_stopped = 1;
2108 i40evf_dev_link_update(struct rte_eth_dev *dev,
2109 __rte_unused int wait_to_complete)
2111 struct rte_eth_link new_link;
2112 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2114 * DPDK pf host provide interfacet to acquire link status
2115 * while Linux driver does not
2118 memset(&new_link, 0, sizeof(new_link));
2119 /* Linux driver PF host */
2120 switch (vf->link_speed) {
2121 case I40E_LINK_SPEED_100MB:
2122 new_link.link_speed = ETH_SPEED_NUM_100M;
2124 case I40E_LINK_SPEED_1GB:
2125 new_link.link_speed = ETH_SPEED_NUM_1G;
2127 case I40E_LINK_SPEED_10GB:
2128 new_link.link_speed = ETH_SPEED_NUM_10G;
2130 case I40E_LINK_SPEED_20GB:
2131 new_link.link_speed = ETH_SPEED_NUM_20G;
2133 case I40E_LINK_SPEED_25GB:
2134 new_link.link_speed = ETH_SPEED_NUM_25G;
2136 case I40E_LINK_SPEED_40GB:
2137 new_link.link_speed = ETH_SPEED_NUM_40G;
2140 new_link.link_speed = ETH_SPEED_NUM_100M;
2143 /* full duplex only */
2144 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2145 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2147 new_link.link_autoneg =
2148 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2150 return rte_eth_linkstatus_set(dev, &new_link);
2154 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2156 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2159 /* If enabled, just return */
2160 if (vf->promisc_unicast_enabled)
2163 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2165 vf->promisc_unicast_enabled = TRUE;
2169 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2171 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2174 /* If disabled, just return */
2175 if (!vf->promisc_unicast_enabled)
2178 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2180 vf->promisc_unicast_enabled = FALSE;
2184 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2186 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2189 /* If enabled, just return */
2190 if (vf->promisc_multicast_enabled)
2193 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2195 vf->promisc_multicast_enabled = TRUE;
2199 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2201 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2204 /* If enabled, just return */
2205 if (!vf->promisc_multicast_enabled)
2208 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2210 vf->promisc_multicast_enabled = FALSE;
2214 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2216 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2218 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2219 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2220 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2221 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2222 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2223 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2224 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2225 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2226 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2227 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2228 dev_info->rx_queue_offload_capa = 0;
2229 dev_info->rx_offload_capa =
2230 DEV_RX_OFFLOAD_VLAN_STRIP |
2231 DEV_RX_OFFLOAD_QINQ_STRIP |
2232 DEV_RX_OFFLOAD_IPV4_CKSUM |
2233 DEV_RX_OFFLOAD_UDP_CKSUM |
2234 DEV_RX_OFFLOAD_TCP_CKSUM |
2235 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2236 DEV_RX_OFFLOAD_SCATTER |
2237 DEV_RX_OFFLOAD_JUMBO_FRAME |
2238 DEV_RX_OFFLOAD_VLAN_FILTER;
2240 dev_info->tx_queue_offload_capa = 0;
2241 dev_info->tx_offload_capa =
2242 DEV_TX_OFFLOAD_VLAN_INSERT |
2243 DEV_TX_OFFLOAD_QINQ_INSERT |
2244 DEV_TX_OFFLOAD_IPV4_CKSUM |
2245 DEV_TX_OFFLOAD_UDP_CKSUM |
2246 DEV_TX_OFFLOAD_TCP_CKSUM |
2247 DEV_TX_OFFLOAD_SCTP_CKSUM |
2248 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2249 DEV_TX_OFFLOAD_TCP_TSO |
2250 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2251 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2252 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2253 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2254 DEV_TX_OFFLOAD_MULTI_SEGS;
2256 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2258 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2259 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2260 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2262 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2267 dev_info->default_txconf = (struct rte_eth_txconf) {
2269 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2270 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2271 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2273 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2274 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2278 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2279 .nb_max = I40E_MAX_RING_DESC,
2280 .nb_min = I40E_MIN_RING_DESC,
2281 .nb_align = I40E_ALIGN_RING_DESC,
2284 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2285 .nb_max = I40E_MAX_RING_DESC,
2286 .nb_min = I40E_MIN_RING_DESC,
2287 .nb_align = I40E_ALIGN_RING_DESC,
2292 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2295 struct i40e_eth_stats *pstats = NULL;
2296 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2297 struct i40e_vsi *vsi = &vf->vsi;
2299 ret = i40evf_query_stats(dev, &pstats);
2301 i40evf_update_stats(vsi, pstats);
2303 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2304 pstats->rx_broadcast;
2305 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2307 stats->imissed = pstats->rx_discards;
2308 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2309 stats->ibytes = pstats->rx_bytes;
2310 stats->obytes = pstats->tx_bytes;
2312 PMD_DRV_LOG(ERR, "Get statistics failed");
2318 i40evf_dev_close(struct rte_eth_dev *dev)
2320 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 i40evf_dev_stop(dev);
2323 i40e_dev_free_queues(dev);
2325 * disable promiscuous mode before reset vf
2326 * it is a workaround solution when work with kernel driver
2327 * and it is not the normal way
2329 i40evf_dev_promiscuous_disable(dev);
2330 i40evf_dev_allmulticast_disable(dev);
2331 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2333 i40evf_reset_vf(dev);
2334 i40e_shutdown_adminq(hw);
2335 i40evf_disable_irq0(hw);
2336 hw->adapter_closed = 1;
2340 * Reset VF device only to re-initialize resources in PMD layer
2343 i40evf_dev_reset(struct rte_eth_dev *dev)
2347 ret = i40evf_dev_uninit(dev);
2351 ret = i40evf_dev_init(dev);
2357 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2359 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2360 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2366 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2367 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2370 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2374 uint32_t *lut_dw = (uint32_t *)lut;
2375 uint16_t i, lut_size_dw = lut_size / 4;
2377 for (i = 0; i < lut_size_dw; i++)
2378 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2385 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2394 vf = I40E_VSI_TO_VF(vsi);
2395 hw = I40E_VSI_TO_HW(vsi);
2397 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2398 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2401 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2405 uint32_t *lut_dw = (uint32_t *)lut;
2406 uint16_t i, lut_size_dw = lut_size / 4;
2408 for (i = 0; i < lut_size_dw; i++)
2409 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2410 I40EVF_WRITE_FLUSH(hw);
2417 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2418 struct rte_eth_rss_reta_entry64 *reta_conf,
2421 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2423 uint16_t i, idx, shift;
2426 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2427 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2428 "(%d) doesn't match the number of hardware can "
2429 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2433 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2435 PMD_DRV_LOG(ERR, "No memory can be allocated");
2438 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2441 for (i = 0; i < reta_size; i++) {
2442 idx = i / RTE_RETA_GROUP_SIZE;
2443 shift = i % RTE_RETA_GROUP_SIZE;
2444 if (reta_conf[idx].mask & (1ULL << shift))
2445 lut[i] = reta_conf[idx].reta[shift];
2447 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2456 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2457 struct rte_eth_rss_reta_entry64 *reta_conf,
2460 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2461 uint16_t i, idx, shift;
2465 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2466 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2467 "(%d) doesn't match the number of hardware can "
2468 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2472 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2474 PMD_DRV_LOG(ERR, "No memory can be allocated");
2478 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2481 for (i = 0; i < reta_size; i++) {
2482 idx = i / RTE_RETA_GROUP_SIZE;
2483 shift = i % RTE_RETA_GROUP_SIZE;
2484 if (reta_conf[idx].mask & (1ULL << shift))
2485 reta_conf[idx].reta[shift] = lut[i];
2495 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2497 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2498 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2501 if (!key || key_len == 0) {
2502 PMD_DRV_LOG(DEBUG, "No key to be configured");
2504 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2506 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2510 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2511 struct i40e_aqc_get_set_rss_key_data *key_dw =
2512 (struct i40e_aqc_get_set_rss_key_data *)key;
2514 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2516 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2519 uint32_t *hash_key = (uint32_t *)key;
2522 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2523 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2524 I40EVF_WRITE_FLUSH(hw);
2531 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2533 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2534 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2537 if (!key || !key_len)
2540 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2541 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2542 (struct i40e_aqc_get_set_rss_key_data *)key);
2544 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2548 uint32_t *key_dw = (uint32_t *)key;
2551 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2552 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2554 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2560 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2562 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2566 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2567 rss_conf->rss_key_len);
2571 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2572 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2573 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2574 I40EVF_WRITE_FLUSH(hw);
2580 i40evf_disable_rss(struct i40e_vf *vf)
2582 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2584 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2585 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2586 I40EVF_WRITE_FLUSH(hw);
2590 i40evf_config_rss(struct i40e_vf *vf)
2592 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2593 struct rte_eth_rss_conf rss_conf;
2594 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2597 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2598 i40evf_disable_rss(vf);
2599 PMD_DRV_LOG(DEBUG, "RSS not configured");
2603 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2604 /* Fill out the look up table */
2605 for (i = 0, j = 0; i < nb_q; i++, j++) {
2608 lut = (lut << 8) | j;
2610 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2613 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2614 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2615 i40evf_disable_rss(vf);
2616 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2620 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2621 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2622 /* Calculate the default hash key */
2623 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2624 rss_key_default[i] = (uint32_t)rte_rand();
2625 rss_conf.rss_key = (uint8_t *)rss_key_default;
2626 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2630 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2634 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2635 struct rte_eth_rss_conf *rss_conf)
2637 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2642 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2643 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2645 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2646 if (rss_hf != 0) /* Enable RSS */
2652 if (rss_hf == 0) /* Disable RSS */
2655 return i40evf_hw_rss_hash_set(vf, rss_conf);
2659 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2660 struct rte_eth_rss_conf *rss_conf)
2662 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2667 &rss_conf->rss_key_len);
2669 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2670 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2671 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2677 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2679 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2680 struct rte_eth_dev_data *dev_data = vf->dev_data;
2681 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2684 /* check if mtu is within the allowed range */
2685 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2688 /* mtu setting is forbidden if port is start */
2689 if (dev_data->dev_started) {
2690 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2695 if (frame_size > RTE_ETHER_MAX_LEN)
2696 dev_data->dev_conf.rxmode.offloads |=
2697 DEV_RX_OFFLOAD_JUMBO_FRAME;
2699 dev_data->dev_conf.rxmode.offloads &=
2700 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2701 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2707 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2708 struct rte_ether_addr *mac_addr)
2710 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2714 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2718 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2721 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2723 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2726 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2731 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2732 struct rte_ether_addr *mc_addrs,
2733 uint32_t mc_addrs_num, bool add)
2735 struct virtchnl_ether_addr_list *list;
2736 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2737 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2738 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2741 struct vf_cmd_info args;
2743 if (mc_addrs == NULL || mc_addrs_num == 0)
2746 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2749 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2750 list->vsi_id = vf->vsi_res->vsi_id;
2751 list->num_elements = mc_addrs_num;
2753 for (i = 0; i < mc_addrs_num; i++) {
2754 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2755 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2756 mc_addrs[i].addr_bytes[0],
2757 mc_addrs[i].addr_bytes[1],
2758 mc_addrs[i].addr_bytes[2],
2759 mc_addrs[i].addr_bytes[3],
2760 mc_addrs[i].addr_bytes[4],
2761 mc_addrs[i].addr_bytes[5]);
2765 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2766 sizeof(list->list[i].addr));
2769 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2770 args.in_args = cmd_buffer;
2771 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2772 i * sizeof(struct virtchnl_ether_addr);
2773 args.out_buffer = vf->aq_resp;
2774 args.out_size = I40E_AQ_BUF_SZ;
2775 err = i40evf_execute_vf_cmd(dev, &args);
2777 PMD_DRV_LOG(ERR, "fail to execute command %s",
2778 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2786 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2787 struct rte_ether_addr *mc_addrs,
2788 uint32_t mc_addrs_num)
2790 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2793 /* flush previous addresses */
2794 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2799 vf->mc_addrs_num = 0;
2802 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2807 vf->mc_addrs_num = mc_addrs_num;
2808 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2814 is_i40evf_supported(struct rte_eth_dev *dev)
2816 return is_device_supported(dev, &rte_i40evf_pmd);