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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_ethdev_pci.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static void i40evf_dev_close(struct rte_eth_dev *dev);
123 static int i40evf_dev_reset(struct rte_eth_dev *dev);
124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
155 struct ether_addr *mac_addr);
157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
164 /* Default hash key buffer for RSS */
165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
167 struct rte_i40evf_xstats_name_off {
168 char name[RTE_ETH_XSTATS_NAME_SIZE];
172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
173 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
174 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
175 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
176 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
177 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
178 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
179 rx_unknown_protocol)},
180 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
182 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
183 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
184 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
185 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
189 sizeof(rte_i40evf_stats_strings[0]))
191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
192 .dev_configure = i40evf_dev_configure,
193 .dev_start = i40evf_dev_start,
194 .dev_stop = i40evf_dev_stop,
195 .promiscuous_enable = i40evf_dev_promiscuous_enable,
196 .promiscuous_disable = i40evf_dev_promiscuous_disable,
197 .allmulticast_enable = i40evf_dev_allmulticast_enable,
198 .allmulticast_disable = i40evf_dev_allmulticast_disable,
199 .link_update = i40evf_dev_link_update,
200 .stats_get = i40evf_dev_stats_get,
201 .xstats_get = i40evf_dev_xstats_get,
202 .xstats_get_names = i40evf_dev_xstats_get_names,
203 .xstats_reset = i40evf_dev_xstats_reset,
204 .dev_close = i40evf_dev_close,
205 .dev_reset = i40evf_dev_reset,
206 .dev_infos_get = i40evf_dev_info_get,
207 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
208 .vlan_filter_set = i40evf_vlan_filter_set,
209 .vlan_offload_set = i40evf_vlan_offload_set,
210 .rx_queue_start = i40evf_dev_rx_queue_start,
211 .rx_queue_stop = i40evf_dev_rx_queue_stop,
212 .tx_queue_start = i40evf_dev_tx_queue_start,
213 .tx_queue_stop = i40evf_dev_tx_queue_stop,
214 .rx_queue_setup = i40e_dev_rx_queue_setup,
215 .rx_queue_release = i40e_dev_rx_queue_release,
216 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
217 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
218 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
219 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
220 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
221 .tx_queue_setup = i40e_dev_tx_queue_setup,
222 .tx_queue_release = i40e_dev_tx_queue_release,
223 .rx_queue_count = i40e_dev_rx_queue_count,
224 .rxq_info_get = i40e_rxq_info_get,
225 .txq_info_get = i40e_txq_info_get,
226 .mac_addr_add = i40evf_add_mac_addr,
227 .mac_addr_remove = i40evf_del_mac_addr,
228 .reta_update = i40evf_dev_rss_reta_update,
229 .reta_query = i40evf_dev_rss_reta_query,
230 .rss_hash_update = i40evf_dev_rss_hash_update,
231 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
232 .mtu_set = i40evf_dev_mtu_set,
233 .mac_addr_set = i40evf_set_default_mac_addr,
237 * Read data in admin queue to get msg from pf driver
239 static enum i40evf_aq_result
240 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
243 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
244 struct i40e_arq_event_info event;
245 enum virtchnl_ops opcode;
246 enum i40e_status_code retval;
248 enum i40evf_aq_result result = I40EVF_MSG_NON;
250 event.buf_len = data->buf_len;
251 event.msg_buf = data->msg;
252 ret = i40e_clean_arq_element(hw, &event, NULL);
253 /* Can't read any msg from adminQ */
255 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
256 result = I40EVF_MSG_ERR;
260 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
261 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
263 if (opcode == VIRTCHNL_OP_EVENT) {
264 struct virtchnl_pf_event *vpe =
265 (struct virtchnl_pf_event *)event.msg_buf;
267 result = I40EVF_MSG_SYS;
268 switch (vpe->event) {
269 case VIRTCHNL_EVENT_LINK_CHANGE:
271 vpe->event_data.link_event.link_status;
273 vpe->event_data.link_event.link_speed;
274 vf->pend_msg |= PFMSG_LINK_CHANGE;
275 PMD_DRV_LOG(INFO, "Link status update:%s",
276 vf->link_up ? "up" : "down");
278 case VIRTCHNL_EVENT_RESET_IMPENDING:
280 vf->pend_msg |= PFMSG_RESET_IMPENDING;
281 PMD_DRV_LOG(INFO, "vf is reseting");
283 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
284 vf->dev_closed = true;
285 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
286 PMD_DRV_LOG(INFO, "PF driver closed");
289 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
290 __func__, vpe->event);
293 /* async reply msg on command issued by vf previously */
294 result = I40EVF_MSG_CMD;
295 /* Actual data length read from PF */
296 data->msg_len = event.msg_len;
299 data->result = retval;
306 * clear current command. Only call in case execute
307 * _atomic_set_cmd successfully.
310 _clear_cmd(struct i40e_vf *vf)
313 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
317 * Check there is pending cmd in execution. If none, set new command.
320 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
322 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
323 VIRTCHNL_OP_UNKNOWN, ops);
326 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
331 #define MAX_TRY_TIMES 200
332 #define ASQ_DELAY_MS 10
335 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
337 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
338 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
339 struct i40evf_arq_msg_info info;
340 enum i40evf_aq_result ret;
343 if (_atomic_set_cmd(vf, args->ops))
346 info.msg = args->out_buffer;
347 info.buf_len = args->out_size;
348 info.ops = VIRTCHNL_OP_UNKNOWN;
349 info.result = I40E_SUCCESS;
351 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
352 args->in_args, args->in_args_size, NULL);
354 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
360 case VIRTCHNL_OP_RESET_VF:
361 /*no need to process in this function */
364 case VIRTCHNL_OP_VERSION:
365 case VIRTCHNL_OP_GET_VF_RESOURCES:
366 /* for init adminq commands, need to poll the response */
369 ret = i40evf_read_pfmsg(dev, &info);
370 vf->cmd_retval = info.result;
371 if (ret == I40EVF_MSG_CMD) {
374 } else if (ret == I40EVF_MSG_ERR)
376 rte_delay_ms(ASQ_DELAY_MS);
377 /* If don't read msg or read sys event, continue */
378 } while (i++ < MAX_TRY_TIMES);
383 /* for other adminq in running time, waiting the cmd done flag */
386 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
390 rte_delay_ms(ASQ_DELAY_MS);
391 /* If don't read msg or read sys event, continue */
392 } while (i++ < MAX_TRY_TIMES);
393 /* If there's no response is received, clear command */
394 if (i >= MAX_TRY_TIMES) {
395 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
401 return err | vf->cmd_retval;
405 * Check API version with sync wait until version read or fail from admin queue
408 i40evf_check_api_version(struct rte_eth_dev *dev)
410 struct virtchnl_version_info version, *pver;
412 struct vf_cmd_info args;
413 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
415 version.major = VIRTCHNL_VERSION_MAJOR;
416 version.minor = VIRTCHNL_VERSION_MINOR;
418 args.ops = VIRTCHNL_OP_VERSION;
419 args.in_args = (uint8_t *)&version;
420 args.in_args_size = sizeof(version);
421 args.out_buffer = vf->aq_resp;
422 args.out_size = I40E_AQ_BUF_SZ;
424 err = i40evf_execute_vf_cmd(dev, &args);
426 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
430 pver = (struct virtchnl_version_info *)args.out_buffer;
431 vf->version_major = pver->major;
432 vf->version_minor = pver->minor;
433 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
434 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
435 else if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
436 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
437 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
439 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
440 vf->version_major, vf->version_minor,
441 VIRTCHNL_VERSION_MAJOR,
442 VIRTCHNL_VERSION_MINOR);
450 i40evf_get_vf_resource(struct rte_eth_dev *dev)
452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
453 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
455 struct vf_cmd_info args;
458 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
459 args.out_buffer = vf->aq_resp;
460 args.out_size = I40E_AQ_BUF_SZ;
462 caps = VIRTCHNL_VF_OFFLOAD_L2 |
463 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
464 VIRTCHNL_VF_OFFLOAD_RSS_REG |
465 VIRTCHNL_VF_OFFLOAD_VLAN |
466 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
467 args.in_args = (uint8_t *)∩︀
468 args.in_args_size = sizeof(caps);
471 args.in_args_size = 0;
473 err = i40evf_execute_vf_cmd(dev, &args);
476 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
480 len = sizeof(struct virtchnl_vf_resource) +
481 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
483 (void)rte_memcpy(vf->vf_res, args.out_buffer,
484 RTE_MIN(args.out_size, len));
485 i40e_vf_parse_hw_config(hw, vf->vf_res);
491 i40evf_config_promisc(struct rte_eth_dev *dev,
493 bool enable_multicast)
495 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
497 struct vf_cmd_info args;
498 struct virtchnl_promisc_info promisc;
501 promisc.vsi_id = vf->vsi_res->vsi_id;
504 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
506 if (enable_multicast)
507 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
509 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
510 args.in_args = (uint8_t *)&promisc;
511 args.in_args_size = sizeof(promisc);
512 args.out_buffer = vf->aq_resp;
513 args.out_size = I40E_AQ_BUF_SZ;
515 err = i40evf_execute_vf_cmd(dev, &args);
518 PMD_DRV_LOG(ERR, "fail to execute command "
519 "CONFIG_PROMISCUOUS_MODE");
524 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
526 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
527 struct vf_cmd_info args;
530 memset(&args, 0, sizeof(args));
531 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
533 args.in_args_size = 0;
534 args.out_buffer = vf->aq_resp;
535 args.out_size = I40E_AQ_BUF_SZ;
536 ret = i40evf_execute_vf_cmd(dev, &args);
538 PMD_DRV_LOG(ERR, "Failed to execute command of "
539 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
545 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
547 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
548 struct vf_cmd_info args;
551 memset(&args, 0, sizeof(args));
552 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
554 args.in_args_size = 0;
555 args.out_buffer = vf->aq_resp;
556 args.out_size = I40E_AQ_BUF_SZ;
557 ret = i40evf_execute_vf_cmd(dev, &args);
559 PMD_DRV_LOG(ERR, "Failed to execute command of "
560 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
566 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
570 struct i40e_tx_queue *txq)
572 txq_info->vsi_id = vsi_id;
573 txq_info->queue_id = queue_id;
574 if (queue_id < nb_txq) {
575 txq_info->ring_len = txq->nb_tx_desc;
576 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
581 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
585 uint32_t max_pkt_size,
586 struct i40e_rx_queue *rxq)
588 rxq_info->vsi_id = vsi_id;
589 rxq_info->queue_id = queue_id;
590 rxq_info->max_pkt_size = max_pkt_size;
591 if (queue_id < nb_rxq) {
592 rxq_info->ring_len = rxq->nb_rx_desc;
593 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
594 rxq_info->databuffer_size =
595 (rte_pktmbuf_data_room_size(rxq->mp) -
596 RTE_PKTMBUF_HEADROOM);
600 /* It configures VSI queues to co-work with Linux PF host */
602 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
604 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
605 struct i40e_rx_queue **rxq =
606 (struct i40e_rx_queue **)dev->data->rx_queues;
607 struct i40e_tx_queue **txq =
608 (struct i40e_tx_queue **)dev->data->tx_queues;
609 struct virtchnl_vsi_queue_config_info *vc_vqci;
610 struct virtchnl_queue_pair_info *vc_qpi;
611 struct vf_cmd_info args;
612 uint16_t i, nb_qp = vf->num_queue_pairs;
613 const uint32_t size =
614 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
618 memset(buff, 0, sizeof(buff));
619 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
620 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
621 vc_vqci->num_queue_pairs = nb_qp;
623 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
624 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
625 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
626 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
627 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
628 vf->max_pkt_len, rxq[i]);
630 memset(&args, 0, sizeof(args));
631 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
632 args.in_args = (uint8_t *)vc_vqci;
633 args.in_args_size = size;
634 args.out_buffer = vf->aq_resp;
635 args.out_size = I40E_AQ_BUF_SZ;
636 ret = i40evf_execute_vf_cmd(dev, &args);
638 PMD_DRV_LOG(ERR, "Failed to execute command of "
639 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
644 /* It configures VSI queues to co-work with DPDK PF host */
646 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
648 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
649 struct i40e_rx_queue **rxq =
650 (struct i40e_rx_queue **)dev->data->rx_queues;
651 struct i40e_tx_queue **txq =
652 (struct i40e_tx_queue **)dev->data->tx_queues;
653 struct virtchnl_vsi_queue_config_ext_info *vc_vqcei;
654 struct virtchnl_queue_pair_ext_info *vc_qpei;
655 struct vf_cmd_info args;
656 uint16_t i, nb_qp = vf->num_queue_pairs;
657 const uint32_t size =
658 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
662 memset(buff, 0, sizeof(buff));
663 vc_vqcei = (struct virtchnl_vsi_queue_config_ext_info *)buff;
664 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
665 vc_vqcei->num_queue_pairs = nb_qp;
666 vc_qpei = vc_vqcei->qpair;
667 for (i = 0; i < nb_qp; i++, vc_qpei++) {
668 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
669 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
670 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
671 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
672 vf->max_pkt_len, rxq[i]);
673 if (i < dev->data->nb_rx_queues)
675 * It adds extra info for configuring VSI queues, which
676 * is needed to enable the configurable crc stripping
679 vc_qpei->rxq_ext.crcstrip =
680 dev->data->dev_conf.rxmode.hw_strip_crc;
682 memset(&args, 0, sizeof(args));
684 (enum virtchnl_ops)VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
685 args.in_args = (uint8_t *)vc_vqcei;
686 args.in_args_size = size;
687 args.out_buffer = vf->aq_resp;
688 args.out_size = I40E_AQ_BUF_SZ;
689 ret = i40evf_execute_vf_cmd(dev, &args);
691 PMD_DRV_LOG(ERR, "Failed to execute command of "
692 "VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT");
698 i40evf_configure_queues(struct rte_eth_dev *dev)
700 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
702 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
703 /* To support DPDK PF host */
704 return i40evf_configure_vsi_queues_ext(dev);
706 /* To support Linux PF host */
707 return i40evf_configure_vsi_queues(dev);
711 i40evf_config_irq_map(struct rte_eth_dev *dev)
713 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
714 struct vf_cmd_info args;
715 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
716 sizeof(struct virtchnl_vector_map)];
717 struct virtchnl_irq_map_info *map_info;
718 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
723 if (rte_intr_allow_others(intr_handle)) {
724 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
725 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
727 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
729 vector_id = I40E_MISC_VEC_ID;
732 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
733 map_info->num_vectors = 1;
734 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
735 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
736 /* Alway use default dynamic MSIX interrupt */
737 map_info->vecmap[0].vector_id = vector_id;
738 /* Don't map any tx queue */
739 map_info->vecmap[0].txq_map = 0;
740 map_info->vecmap[0].rxq_map = 0;
741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
742 map_info->vecmap[0].rxq_map |= 1 << i;
743 if (rte_intr_dp_is_en(intr_handle))
744 intr_handle->intr_vec[i] = vector_id;
747 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
748 args.in_args = (u8 *)cmd_buffer;
749 args.in_args_size = sizeof(cmd_buffer);
750 args.out_buffer = vf->aq_resp;
751 args.out_size = I40E_AQ_BUF_SZ;
752 err = i40evf_execute_vf_cmd(dev, &args);
754 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
760 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
763 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
764 struct virtchnl_queue_select queue_select;
766 struct vf_cmd_info args;
767 memset(&queue_select, 0, sizeof(queue_select));
768 queue_select.vsi_id = vf->vsi_res->vsi_id;
771 queue_select.rx_queues |= 1 << qid;
773 queue_select.tx_queues |= 1 << qid;
776 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
778 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
779 args.in_args = (u8 *)&queue_select;
780 args.in_args_size = sizeof(queue_select);
781 args.out_buffer = vf->aq_resp;
782 args.out_size = I40E_AQ_BUF_SZ;
783 err = i40evf_execute_vf_cmd(dev, &args);
785 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
786 isrx ? "RX" : "TX", qid, on ? "on" : "off");
792 i40evf_start_queues(struct rte_eth_dev *dev)
794 struct rte_eth_dev_data *dev_data = dev->data;
796 struct i40e_rx_queue *rxq;
797 struct i40e_tx_queue *txq;
799 for (i = 0; i < dev->data->nb_rx_queues; i++) {
800 rxq = dev_data->rx_queues[i];
801 if (rxq->rx_deferred_start)
803 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
804 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
809 for (i = 0; i < dev->data->nb_tx_queues; i++) {
810 txq = dev_data->tx_queues[i];
811 if (txq->tx_deferred_start)
813 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
814 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
823 i40evf_stop_queues(struct rte_eth_dev *dev)
827 /* Stop TX queues first */
828 for (i = 0; i < dev->data->nb_tx_queues; i++) {
829 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
830 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
835 /* Then stop RX queues */
836 for (i = 0; i < dev->data->nb_rx_queues; i++) {
837 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
838 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
847 i40evf_add_mac_addr(struct rte_eth_dev *dev,
848 struct ether_addr *addr,
849 __rte_unused uint32_t index,
850 __rte_unused uint32_t pool)
852 struct virtchnl_ether_addr_list *list;
853 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
854 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
855 sizeof(struct virtchnl_ether_addr)];
857 struct vf_cmd_info args;
859 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
860 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
861 addr->addr_bytes[0], addr->addr_bytes[1],
862 addr->addr_bytes[2], addr->addr_bytes[3],
863 addr->addr_bytes[4], addr->addr_bytes[5]);
864 return I40E_ERR_INVALID_MAC_ADDR;
867 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
868 list->vsi_id = vf->vsi_res->vsi_id;
869 list->num_elements = 1;
870 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
871 sizeof(addr->addr_bytes));
873 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
874 args.in_args = cmd_buffer;
875 args.in_args_size = sizeof(cmd_buffer);
876 args.out_buffer = vf->aq_resp;
877 args.out_size = I40E_AQ_BUF_SZ;
878 err = i40evf_execute_vf_cmd(dev, &args);
880 PMD_DRV_LOG(ERR, "fail to execute command "
881 "OP_ADD_ETHER_ADDRESS");
889 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
890 struct ether_addr *addr)
892 struct virtchnl_ether_addr_list *list;
893 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
894 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
895 sizeof(struct virtchnl_ether_addr)];
897 struct vf_cmd_info args;
899 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
900 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
901 addr->addr_bytes[0], addr->addr_bytes[1],
902 addr->addr_bytes[2], addr->addr_bytes[3],
903 addr->addr_bytes[4], addr->addr_bytes[5]);
907 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
908 list->vsi_id = vf->vsi_res->vsi_id;
909 list->num_elements = 1;
910 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
911 sizeof(addr->addr_bytes));
913 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
914 args.in_args = cmd_buffer;
915 args.in_args_size = sizeof(cmd_buffer);
916 args.out_buffer = vf->aq_resp;
917 args.out_size = I40E_AQ_BUF_SZ;
918 err = i40evf_execute_vf_cmd(dev, &args);
920 PMD_DRV_LOG(ERR, "fail to execute command "
921 "OP_DEL_ETHER_ADDRESS");
928 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
930 struct rte_eth_dev_data *data = dev->data;
931 struct ether_addr *addr;
933 addr = &data->mac_addrs[index];
935 i40evf_del_mac_addr_by_addr(dev, addr);
939 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
941 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
942 struct virtchnl_queue_select q_stats;
944 struct vf_cmd_info args;
946 memset(&q_stats, 0, sizeof(q_stats));
947 q_stats.vsi_id = vf->vsi_res->vsi_id;
948 args.ops = VIRTCHNL_OP_GET_STATS;
949 args.in_args = (u8 *)&q_stats;
950 args.in_args_size = sizeof(q_stats);
951 args.out_buffer = vf->aq_resp;
952 args.out_size = I40E_AQ_BUF_SZ;
954 err = i40evf_execute_vf_cmd(dev, &args);
956 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
960 *pstats = (struct i40e_eth_stats *)args.out_buffer;
965 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
968 struct i40e_eth_stats *pstats = NULL;
970 ret = i40evf_update_stats(dev, &pstats);
974 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
975 pstats->rx_broadcast;
976 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
978 stats->imissed = pstats->rx_discards;
979 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
980 stats->ibytes = pstats->rx_bytes;
981 stats->obytes = pstats->tx_bytes;
987 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
989 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
990 struct i40e_eth_stats *pstats = NULL;
992 /* read stat values to clear hardware registers */
993 i40evf_update_stats(dev, &pstats);
995 /* set stats offset base on current values */
996 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
999 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1000 struct rte_eth_xstat_name *xstats_names,
1001 __rte_unused unsigned limit)
1005 if (xstats_names != NULL)
1006 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1007 snprintf(xstats_names[i].name,
1008 sizeof(xstats_names[i].name),
1009 "%s", rte_i40evf_stats_strings[i].name);
1011 return I40EVF_NB_XSTATS;
1014 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1015 struct rte_eth_xstat *xstats, unsigned n)
1019 struct i40e_eth_stats *pstats = NULL;
1021 if (n < I40EVF_NB_XSTATS)
1022 return I40EVF_NB_XSTATS;
1024 ret = i40evf_update_stats(dev, &pstats);
1031 /* loop over xstats array and values from pstats */
1032 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1034 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1035 rte_i40evf_stats_strings[i].offset);
1038 return I40EVF_NB_XSTATS;
1042 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1044 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1045 struct virtchnl_vlan_filter_list *vlan_list;
1046 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1049 struct vf_cmd_info args;
1051 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1052 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1053 vlan_list->num_elements = 1;
1054 vlan_list->vlan_id[0] = vlanid;
1056 args.ops = VIRTCHNL_OP_ADD_VLAN;
1057 args.in_args = (u8 *)&cmd_buffer;
1058 args.in_args_size = sizeof(cmd_buffer);
1059 args.out_buffer = vf->aq_resp;
1060 args.out_size = I40E_AQ_BUF_SZ;
1061 err = i40evf_execute_vf_cmd(dev, &args);
1063 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1069 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1071 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1072 struct virtchnl_vlan_filter_list *vlan_list;
1073 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1076 struct vf_cmd_info args;
1078 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1079 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1080 vlan_list->num_elements = 1;
1081 vlan_list->vlan_id[0] = vlanid;
1083 args.ops = VIRTCHNL_OP_DEL_VLAN;
1084 args.in_args = (u8 *)&cmd_buffer;
1085 args.in_args_size = sizeof(cmd_buffer);
1086 args.out_buffer = vf->aq_resp;
1087 args.out_size = I40E_AQ_BUF_SZ;
1088 err = i40evf_execute_vf_cmd(dev, &args);
1090 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1095 static const struct rte_pci_id pci_id_i40evf_map[] = {
1096 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1097 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1098 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1099 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1100 { .vendor_id = 0, /* sentinel */ },
1104 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1105 struct rte_eth_link *link)
1107 struct rte_eth_link *dst = &(dev->data->dev_link);
1108 struct rte_eth_link *src = link;
1110 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1111 *(uint64_t *)src) == 0)
1119 i40evf_disable_irq0(struct i40e_hw *hw)
1121 /* Disable all interrupt types */
1122 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1123 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1124 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1125 I40EVF_WRITE_FLUSH(hw);
1130 i40evf_enable_irq0(struct i40e_hw *hw)
1132 /* Enable admin queue interrupt trigger */
1135 i40evf_disable_irq0(hw);
1136 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1137 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1138 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1139 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1141 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1142 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1143 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1144 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1146 I40EVF_WRITE_FLUSH(hw);
1150 i40evf_reset_vf(struct i40e_hw *hw)
1154 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1155 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1159 * After issuing vf reset command to pf, pf won't necessarily
1160 * reset vf, it depends on what state it exactly is. If it's not
1161 * initialized yet, it won't have vf reset since it's in a certain
1162 * state. If not, it will try to reset. Even vf is reset, pf will
1163 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1164 * it to ACTIVE. In this duration, vf may not catch the moment that
1165 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1169 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1170 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1171 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1172 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1173 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1179 if (i >= MAX_RESET_WAIT_CNT) {
1180 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1188 i40evf_init_vf(struct rte_eth_dev *dev)
1191 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1194 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1196 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1197 vf->dev_data = dev->data;
1198 err = i40e_set_mac_type(hw);
1200 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1204 i40e_init_adminq_parameter(hw);
1205 err = i40e_init_adminq(hw);
1207 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1211 /* Reset VF and wait until it's complete */
1212 if (i40evf_reset_vf(hw)) {
1213 PMD_INIT_LOG(ERR, "reset NIC failed");
1217 /* VF reset, shutdown admin queue and initialize again */
1218 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1219 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1223 i40e_init_adminq_parameter(hw);
1224 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1225 PMD_INIT_LOG(ERR, "init_adminq failed");
1228 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1230 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1233 if (i40evf_check_api_version(dev) != 0) {
1234 PMD_INIT_LOG(ERR, "check_api version failed");
1237 bufsz = sizeof(struct virtchnl_vf_resource) +
1238 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1239 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1241 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1245 if (i40evf_get_vf_resource(dev) != 0) {
1246 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1250 /* got VF config message back from PF, now we can parse it */
1251 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1252 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1253 vf->vsi_res = &vf->vf_res->vsi_res[i];
1257 PMD_INIT_LOG(ERR, "no LAN VSI found");
1261 if (hw->mac.type == I40E_MAC_X722_VF)
1262 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1263 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1264 vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1265 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1266 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1268 /* Store the MAC address configured by host, or generate random one */
1269 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1270 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1272 eth_random_addr(hw->mac.addr); /* Generate a random one */
1274 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1275 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1276 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1277 (I40E_ITR_INDEX_DEFAULT <<
1278 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1280 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1281 I40EVF_WRITE_FLUSH(hw);
1287 rte_free(vf->vf_res);
1289 i40e_shutdown_adminq(hw); /* ignore error */
1295 i40evf_uninit_vf(struct rte_eth_dev *dev)
1297 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1298 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300 PMD_INIT_FUNC_TRACE();
1302 if (hw->adapter_stopped == 0)
1303 i40evf_dev_close(dev);
1304 rte_free(vf->vf_res);
1306 rte_free(vf->aq_resp);
1313 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1314 __rte_unused uint16_t msglen)
1316 struct virtchnl_pf_event *pf_msg =
1317 (struct virtchnl_pf_event *)msg;
1318 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1320 switch (pf_msg->event) {
1321 case VIRTCHNL_EVENT_RESET_IMPENDING:
1322 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1323 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1326 case VIRTCHNL_EVENT_LINK_CHANGE:
1327 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1328 vf->link_up = pf_msg->event_data.link_event.link_status;
1329 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1331 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1332 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1335 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1341 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1344 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1345 struct i40e_arq_event_info info;
1346 uint16_t pending, aq_opc;
1347 enum virtchnl_ops msg_opc;
1348 enum i40e_status_code msg_ret;
1351 info.buf_len = I40E_AQ_BUF_SZ;
1353 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1356 info.msg_buf = vf->aq_resp;
1360 ret = i40e_clean_arq_element(hw, &info, &pending);
1362 if (ret != I40E_SUCCESS) {
1363 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1367 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1368 /* For the message sent from pf to vf, opcode is stored in
1369 * cookie_high of struct i40e_aq_desc, while return error code
1370 * are stored in cookie_low, Which is done by
1371 * i40e_aq_send_msg_to_vf in PF driver.*/
1372 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1373 info.desc.cookie_high);
1374 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1375 info.desc.cookie_low);
1377 case i40e_aqc_opc_send_msg_to_vf:
1378 if (msg_opc == VIRTCHNL_OP_EVENT)
1380 i40evf_handle_pf_event(dev, info.msg_buf,
1383 /* read message and it's expected one */
1384 if (msg_opc == vf->pend_cmd) {
1385 vf->cmd_retval = msg_ret;
1386 /* prevent compiler reordering */
1387 rte_compiler_barrier();
1390 PMD_DRV_LOG(ERR, "command mismatch,"
1391 "expect %u, get %u",
1392 vf->pend_cmd, msg_opc);
1393 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1394 " opcode = %d", msg_opc);
1398 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1406 * Interrupt handler triggered by NIC for handling
1407 * specific interrupt. Only adminq interrupt is processed in VF.
1410 * Pointer to interrupt handle.
1412 * The address of parameter (struct rte_eth_dev *) regsitered before.
1418 i40evf_dev_interrupt_handler(void *param)
1420 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1421 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424 i40evf_disable_irq0(hw);
1426 /* read out interrupt causes */
1427 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1429 /* No interrupt event indicated */
1430 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1431 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1435 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1436 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1437 i40evf_handle_aq_msg(dev);
1440 /* Link Status Change interrupt */
1441 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1442 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1446 i40evf_enable_irq0(hw);
1447 rte_intr_enable(dev->intr_handle);
1451 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1454 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1455 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1457 PMD_INIT_FUNC_TRACE();
1459 /* assign ops func pointer */
1460 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1461 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1462 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1465 * For secondary processes, we don't initialise any further as primary
1466 * has already done this work.
1468 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1469 i40e_set_rx_function(eth_dev);
1470 i40e_set_tx_function(eth_dev);
1473 i40e_set_default_ptype_table(eth_dev);
1474 rte_eth_copy_pci_info(eth_dev, pci_dev);
1475 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1477 hw->vendor_id = pci_dev->id.vendor_id;
1478 hw->device_id = pci_dev->id.device_id;
1479 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1480 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1481 hw->bus.device = pci_dev->addr.devid;
1482 hw->bus.func = pci_dev->addr.function;
1483 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1484 hw->adapter_stopped = 0;
1486 if(i40evf_init_vf(eth_dev) != 0) {
1487 PMD_INIT_LOG(ERR, "Init vf failed");
1491 /* register callback func to eal lib */
1492 rte_intr_callback_register(&pci_dev->intr_handle,
1493 i40evf_dev_interrupt_handler, (void *)eth_dev);
1495 /* enable uio intr after callback register */
1496 rte_intr_enable(&pci_dev->intr_handle);
1498 /* configure and enable device interrupt */
1499 i40evf_enable_irq0(hw);
1502 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1503 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1505 if (eth_dev->data->mac_addrs == NULL) {
1506 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1507 " store MAC addresses",
1508 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1511 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1512 ð_dev->data->mac_addrs[0]);
1518 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1520 PMD_INIT_FUNC_TRACE();
1522 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1525 eth_dev->dev_ops = NULL;
1526 eth_dev->rx_pkt_burst = NULL;
1527 eth_dev->tx_pkt_burst = NULL;
1529 if (i40evf_uninit_vf(eth_dev) != 0) {
1530 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1534 rte_free(eth_dev->data->mac_addrs);
1535 eth_dev->data->mac_addrs = NULL;
1540 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1541 struct rte_pci_device *pci_dev)
1543 return rte_eth_dev_pci_generic_probe(pci_dev,
1544 sizeof(struct i40e_adapter), i40evf_dev_init);
1547 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1549 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1553 * virtual function driver struct
1555 static struct rte_pci_driver rte_i40evf_pmd = {
1556 .id_table = pci_id_i40evf_map,
1557 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1558 .probe = eth_i40evf_pci_probe,
1559 .remove = eth_i40evf_pci_remove,
1562 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1563 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1564 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1567 i40evf_dev_configure(struct rte_eth_dev *dev)
1569 struct i40e_adapter *ad =
1570 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1571 struct rte_eth_conf *conf = &dev->data->dev_conf;
1574 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1575 * allocation or vector Rx preconditions we will reset it.
1577 ad->rx_bulk_alloc_allowed = true;
1578 ad->rx_vec_allowed = true;
1579 ad->tx_simple_allowed = true;
1580 ad->tx_vec_allowed = true;
1582 /* For non-DPDK PF drivers, VF has no ability to disable HW
1583 * CRC strip, and is implicitly enabled by the PF.
1585 if (!conf->rxmode.hw_strip_crc) {
1586 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1587 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1588 (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1589 /* Peer is running non-DPDK PF driver. */
1590 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1595 return i40evf_init_vlan(dev);
1599 i40evf_init_vlan(struct rte_eth_dev *dev)
1601 /* Apply vlan offload setting */
1602 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1604 return I40E_SUCCESS;
1608 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1610 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1612 /* Vlan stripping setting */
1613 if (mask & ETH_VLAN_STRIP_MASK) {
1614 /* Enable or disable VLAN stripping */
1615 if (dev_conf->rxmode.hw_vlan_strip)
1616 i40evf_enable_vlan_strip(dev);
1618 i40evf_disable_vlan_strip(dev);
1623 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1625 struct i40e_rx_queue *rxq;
1627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629 PMD_INIT_FUNC_TRACE();
1631 if (rx_queue_id < dev->data->nb_rx_queues) {
1632 rxq = dev->data->rx_queues[rx_queue_id];
1634 err = i40e_alloc_rx_queue_mbufs(rxq);
1636 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1642 /* Init the RX tail register. */
1643 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1644 I40EVF_WRITE_FLUSH(hw);
1646 /* Ready to switch the queue on */
1647 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1650 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1653 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1660 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1662 struct i40e_rx_queue *rxq;
1665 if (rx_queue_id < dev->data->nb_rx_queues) {
1666 rxq = dev->data->rx_queues[rx_queue_id];
1668 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1671 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1676 i40e_rx_queue_release_mbufs(rxq);
1677 i40e_reset_rx_queue(rxq);
1678 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1685 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1689 PMD_INIT_FUNC_TRACE();
1691 if (tx_queue_id < dev->data->nb_tx_queues) {
1693 /* Ready to switch the queue on */
1694 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1697 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1700 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1707 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1709 struct i40e_tx_queue *txq;
1712 if (tx_queue_id < dev->data->nb_tx_queues) {
1713 txq = dev->data->tx_queues[tx_queue_id];
1715 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1718 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1723 i40e_tx_queue_release_mbufs(txq);
1724 i40e_reset_tx_queue(txq);
1725 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1732 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1737 ret = i40evf_add_vlan(dev, vlan_id);
1739 ret = i40evf_del_vlan(dev,vlan_id);
1745 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1747 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 struct rte_eth_dev_data *dev_data = dev->data;
1749 struct rte_pktmbuf_pool_private *mbp_priv;
1750 uint16_t buf_size, len;
1752 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1753 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1754 I40EVF_WRITE_FLUSH(hw);
1756 /* Calculate the maximum packet length allowed */
1757 mbp_priv = rte_mempool_get_priv(rxq->mp);
1758 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1759 RTE_PKTMBUF_HEADROOM);
1760 rxq->hs_mode = i40e_header_split_none;
1761 rxq->rx_hdr_len = 0;
1762 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1763 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1764 rxq->max_pkt_len = RTE_MIN(len,
1765 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1768 * Check if the jumbo frame and maximum packet length are set correctly
1770 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1771 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1772 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1773 PMD_DRV_LOG(ERR, "maximum packet length must be "
1774 "larger than %u and smaller than %u, as jumbo "
1775 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1776 (uint32_t)I40E_FRAME_SIZE_MAX);
1777 return I40E_ERR_CONFIG;
1780 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1781 rxq->max_pkt_len > ETHER_MAX_LEN) {
1782 PMD_DRV_LOG(ERR, "maximum packet length must be "
1783 "larger than %u and smaller than %u, as jumbo "
1784 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1785 (uint32_t)ETHER_MAX_LEN);
1786 return I40E_ERR_CONFIG;
1790 if (dev_data->dev_conf.rxmode.enable_scatter ||
1791 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1792 dev_data->scattered_rx = 1;
1799 i40evf_rx_init(struct rte_eth_dev *dev)
1801 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1803 int ret = I40E_SUCCESS;
1804 struct i40e_rx_queue **rxq =
1805 (struct i40e_rx_queue **)dev->data->rx_queues;
1807 i40evf_config_rss(vf);
1808 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1809 if (!rxq[i] || !rxq[i]->q_set)
1811 ret = i40evf_rxq_init(dev, rxq[i]);
1812 if (ret != I40E_SUCCESS)
1815 if (ret == I40E_SUCCESS)
1816 i40e_set_rx_function(dev);
1822 i40evf_tx_init(struct rte_eth_dev *dev)
1825 struct i40e_tx_queue **txq =
1826 (struct i40e_tx_queue **)dev->data->tx_queues;
1827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829 for (i = 0; i < dev->data->nb_tx_queues; i++)
1830 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1832 i40e_set_tx_function(dev);
1836 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1838 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1841 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1843 if (!rte_intr_allow_others(intr_handle)) {
1845 I40E_VFINT_DYN_CTL01,
1846 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1847 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1848 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1849 I40EVF_WRITE_FLUSH(hw);
1853 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1854 /* To support DPDK PF host */
1856 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1857 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1858 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1859 /* If host driver is kernel driver, do nothing.
1860 * Interrupt 0 is used for rx packets, but don't set
1861 * I40E_VFINT_DYN_CTL01,
1862 * because it is already done in i40evf_enable_irq0.
1865 I40EVF_WRITE_FLUSH(hw);
1869 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1871 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1872 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1876 if (!rte_intr_allow_others(intr_handle)) {
1877 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1878 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1879 I40EVF_WRITE_FLUSH(hw);
1883 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1885 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1888 /* If host driver is kernel driver, do nothing.
1889 * Interrupt 0 is used for rx packets, but don't zero
1890 * I40E_VFINT_DYN_CTL01,
1891 * because interrupt 0 is also used for adminq processing.
1894 I40EVF_WRITE_FLUSH(hw);
1898 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1900 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1901 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1902 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1907 msix_intr = intr_handle->intr_vec[queue_id];
1908 if (msix_intr == I40E_MISC_VEC_ID)
1909 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1910 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1911 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1912 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1914 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1917 I40E_VFINT_DYN_CTLN1(msix_intr -
1919 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1920 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1921 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1923 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1925 I40EVF_WRITE_FLUSH(hw);
1927 rte_intr_enable(&pci_dev->intr_handle);
1933 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1935 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1936 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 msix_intr = intr_handle->intr_vec[queue_id];
1941 if (msix_intr == I40E_MISC_VEC_ID)
1942 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1945 I40E_VFINT_DYN_CTLN1(msix_intr -
1949 I40EVF_WRITE_FLUSH(hw);
1955 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1957 struct virtchnl_ether_addr_list *list;
1958 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1963 struct ether_addr *addr;
1964 struct vf_cmd_info args;
1968 len = sizeof(struct virtchnl_ether_addr_list);
1969 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1970 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1972 len += sizeof(struct virtchnl_ether_addr);
1973 if (len >= I40E_AQ_BUF_SZ) {
1979 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1981 PMD_DRV_LOG(ERR, "fail to allocate memory");
1985 for (i = begin; i < next_begin; i++) {
1986 addr = &dev->data->mac_addrs[i];
1987 if (is_zero_ether_addr(addr))
1989 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
1990 sizeof(addr->addr_bytes));
1991 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1992 addr->addr_bytes[0], addr->addr_bytes[1],
1993 addr->addr_bytes[2], addr->addr_bytes[3],
1994 addr->addr_bytes[4], addr->addr_bytes[5]);
1997 list->vsi_id = vf->vsi_res->vsi_id;
1998 list->num_elements = j;
1999 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2000 VIRTCHNL_OP_DEL_ETH_ADDR;
2001 args.in_args = (uint8_t *)list;
2002 args.in_args_size = len;
2003 args.out_buffer = vf->aq_resp;
2004 args.out_size = I40E_AQ_BUF_SZ;
2005 err = i40evf_execute_vf_cmd(dev, &args);
2007 PMD_DRV_LOG(ERR, "fail to execute command %s",
2008 add ? "OP_ADD_ETHER_ADDRESS" :
2009 "OP_DEL_ETHER_ADDRESS");
2018 } while (begin < I40E_NUM_MACADDR_MAX);
2022 i40evf_dev_start(struct rte_eth_dev *dev)
2024 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2025 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2027 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2028 uint32_t intr_vector = 0;
2030 PMD_INIT_FUNC_TRACE();
2032 hw->adapter_stopped = 0;
2034 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2035 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2036 dev->data->nb_tx_queues);
2038 /* check and configure queue intr-vector mapping */
2039 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2040 intr_vector = dev->data->nb_rx_queues;
2041 if (rte_intr_efd_enable(intr_handle, intr_vector))
2045 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2046 intr_handle->intr_vec =
2047 rte_zmalloc("intr_vec",
2048 dev->data->nb_rx_queues * sizeof(int), 0);
2049 if (!intr_handle->intr_vec) {
2050 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2051 " intr_vec", dev->data->nb_rx_queues);
2056 if (i40evf_rx_init(dev) != 0){
2057 PMD_DRV_LOG(ERR, "failed to do RX init");
2061 i40evf_tx_init(dev);
2063 if (i40evf_configure_queues(dev) != 0) {
2064 PMD_DRV_LOG(ERR, "configure queues failed");
2067 if (i40evf_config_irq_map(dev)) {
2068 PMD_DRV_LOG(ERR, "config_irq_map failed");
2072 /* Set all mac addrs */
2073 i40evf_add_del_all_mac_addr(dev, TRUE);
2075 if (i40evf_start_queues(dev) != 0) {
2076 PMD_DRV_LOG(ERR, "enable queues failed");
2080 i40evf_enable_queues_intr(dev);
2084 i40evf_add_del_all_mac_addr(dev, FALSE);
2090 i40evf_dev_stop(struct rte_eth_dev *dev)
2092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2093 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev);
2096 PMD_INIT_FUNC_TRACE();
2098 if (hw->adapter_stopped == 1)
2100 i40evf_stop_queues(dev);
2101 i40evf_disable_queues_intr(dev);
2102 i40e_dev_clear_queues(dev);
2104 /* Clean datapath event and queue/vec mapping */
2105 rte_intr_efd_disable(intr_handle);
2106 if (intr_handle->intr_vec) {
2107 rte_free(intr_handle->intr_vec);
2108 intr_handle->intr_vec = NULL;
2110 /* remove all mac addrs */
2111 i40evf_add_del_all_mac_addr(dev, FALSE);
2112 hw->adapter_stopped = 1;
2117 i40evf_dev_link_update(struct rte_eth_dev *dev,
2118 __rte_unused int wait_to_complete)
2120 struct rte_eth_link new_link;
2121 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2123 * DPDK pf host provide interfacet to acquire link status
2124 * while Linux driver does not
2127 /* Linux driver PF host */
2128 switch (vf->link_speed) {
2129 case I40E_LINK_SPEED_100MB:
2130 new_link.link_speed = ETH_SPEED_NUM_100M;
2132 case I40E_LINK_SPEED_1GB:
2133 new_link.link_speed = ETH_SPEED_NUM_1G;
2135 case I40E_LINK_SPEED_10GB:
2136 new_link.link_speed = ETH_SPEED_NUM_10G;
2138 case I40E_LINK_SPEED_20GB:
2139 new_link.link_speed = ETH_SPEED_NUM_20G;
2141 case I40E_LINK_SPEED_25GB:
2142 new_link.link_speed = ETH_SPEED_NUM_25G;
2144 case I40E_LINK_SPEED_40GB:
2145 new_link.link_speed = ETH_SPEED_NUM_40G;
2148 new_link.link_speed = ETH_SPEED_NUM_100M;
2151 /* full duplex only */
2152 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2153 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2156 i40evf_dev_atomic_write_link_status(dev, &new_link);
2162 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2164 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2167 /* If enabled, just return */
2168 if (vf->promisc_unicast_enabled)
2171 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2173 vf->promisc_unicast_enabled = TRUE;
2177 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2179 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2182 /* If disabled, just return */
2183 if (!vf->promisc_unicast_enabled)
2186 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2188 vf->promisc_unicast_enabled = FALSE;
2192 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2194 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2197 /* If enabled, just return */
2198 if (vf->promisc_multicast_enabled)
2201 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2203 vf->promisc_multicast_enabled = TRUE;
2207 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2209 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2212 /* If enabled, just return */
2213 if (!vf->promisc_multicast_enabled)
2216 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2218 vf->promisc_multicast_enabled = FALSE;
2222 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2224 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2226 memset(dev_info, 0, sizeof(*dev_info));
2227 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2229 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2230 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2231 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2232 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2233 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2234 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2235 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2236 dev_info->rx_offload_capa =
2237 DEV_RX_OFFLOAD_VLAN_STRIP |
2238 DEV_RX_OFFLOAD_QINQ_STRIP |
2239 DEV_RX_OFFLOAD_IPV4_CKSUM |
2240 DEV_RX_OFFLOAD_UDP_CKSUM |
2241 DEV_RX_OFFLOAD_TCP_CKSUM;
2242 dev_info->tx_offload_capa =
2243 DEV_TX_OFFLOAD_VLAN_INSERT |
2244 DEV_TX_OFFLOAD_QINQ_INSERT |
2245 DEV_TX_OFFLOAD_IPV4_CKSUM |
2246 DEV_TX_OFFLOAD_UDP_CKSUM |
2247 DEV_TX_OFFLOAD_TCP_CKSUM |
2248 DEV_TX_OFFLOAD_SCTP_CKSUM;
2250 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2252 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2253 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2254 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2256 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2260 dev_info->default_txconf = (struct rte_eth_txconf) {
2262 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2263 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2264 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2266 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2267 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2268 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2269 ETH_TXQ_FLAGS_NOOFFLOADS,
2272 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2273 .nb_max = I40E_MAX_RING_DESC,
2274 .nb_min = I40E_MIN_RING_DESC,
2275 .nb_align = I40E_ALIGN_RING_DESC,
2278 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2279 .nb_max = I40E_MAX_RING_DESC,
2280 .nb_min = I40E_MIN_RING_DESC,
2281 .nb_align = I40E_ALIGN_RING_DESC,
2286 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2288 if (i40evf_get_statistics(dev, stats))
2289 PMD_DRV_LOG(ERR, "Get statistics failed");
2293 i40evf_dev_close(struct rte_eth_dev *dev)
2295 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2297 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2299 i40evf_dev_stop(dev);
2300 i40e_dev_free_queues(dev);
2301 i40evf_reset_vf(hw);
2302 i40e_shutdown_adminq(hw);
2303 /* disable uio intr before callback unregister */
2304 rte_intr_disable(intr_handle);
2306 /* unregister callback func from eal lib */
2307 rte_intr_callback_unregister(intr_handle,
2308 i40evf_dev_interrupt_handler, dev);
2309 i40evf_disable_irq0(hw);
2313 * Reset VF device only to re-initialize resources in PMD layer
2316 i40evf_dev_reset(struct rte_eth_dev *dev)
2320 ret = i40evf_dev_uninit(dev);
2324 ret = i40evf_dev_init(dev);
2330 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2332 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2333 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2339 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2340 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2343 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2347 uint32_t *lut_dw = (uint32_t *)lut;
2348 uint16_t i, lut_size_dw = lut_size / 4;
2350 for (i = 0; i < lut_size_dw; i++)
2351 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2358 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2367 vf = I40E_VSI_TO_VF(vsi);
2368 hw = I40E_VSI_TO_HW(vsi);
2370 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2371 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2374 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2378 uint32_t *lut_dw = (uint32_t *)lut;
2379 uint16_t i, lut_size_dw = lut_size / 4;
2381 for (i = 0; i < lut_size_dw; i++)
2382 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2383 I40EVF_WRITE_FLUSH(hw);
2390 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2391 struct rte_eth_rss_reta_entry64 *reta_conf,
2394 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2396 uint16_t i, idx, shift;
2399 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2400 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2401 "(%d) doesn't match the number of hardware can "
2402 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2406 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2408 PMD_DRV_LOG(ERR, "No memory can be allocated");
2411 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2414 for (i = 0; i < reta_size; i++) {
2415 idx = i / RTE_RETA_GROUP_SIZE;
2416 shift = i % RTE_RETA_GROUP_SIZE;
2417 if (reta_conf[idx].mask & (1ULL << shift))
2418 lut[i] = reta_conf[idx].reta[shift];
2420 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2429 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2430 struct rte_eth_rss_reta_entry64 *reta_conf,
2433 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2434 uint16_t i, idx, shift;
2438 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2439 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2440 "(%d) doesn't match the number of hardware can "
2441 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2445 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2447 PMD_DRV_LOG(ERR, "No memory can be allocated");
2451 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2454 for (i = 0; i < reta_size; i++) {
2455 idx = i / RTE_RETA_GROUP_SIZE;
2456 shift = i % RTE_RETA_GROUP_SIZE;
2457 if (reta_conf[idx].mask & (1ULL << shift))
2458 reta_conf[idx].reta[shift] = lut[i];
2468 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2470 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2471 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2474 if (!key || key_len == 0) {
2475 PMD_DRV_LOG(DEBUG, "No key to be configured");
2477 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2479 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2483 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2484 struct i40e_aqc_get_set_rss_key_data *key_dw =
2485 (struct i40e_aqc_get_set_rss_key_data *)key;
2487 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2489 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2492 uint32_t *hash_key = (uint32_t *)key;
2495 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2496 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2497 I40EVF_WRITE_FLUSH(hw);
2504 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2506 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2507 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2510 if (!key || !key_len)
2513 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2514 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2515 (struct i40e_aqc_get_set_rss_key_data *)key);
2517 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2521 uint32_t *key_dw = (uint32_t *)key;
2524 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2525 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2527 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2533 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2535 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2536 uint64_t rss_hf, hena;
2539 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2540 rss_conf->rss_key_len);
2544 rss_hf = rss_conf->rss_hf;
2545 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2546 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2547 if (hw->mac.type == I40E_MAC_X722)
2548 hena &= ~I40E_RSS_HENA_ALL_X722;
2550 hena &= ~I40E_RSS_HENA_ALL;
2551 hena |= i40e_config_hena(rss_hf, hw->mac.type);
2552 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2553 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2554 I40EVF_WRITE_FLUSH(hw);
2560 i40evf_disable_rss(struct i40e_vf *vf)
2562 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2565 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2566 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2567 if (hw->mac.type == I40E_MAC_X722)
2568 hena &= ~I40E_RSS_HENA_ALL_X722;
2570 hena &= ~I40E_RSS_HENA_ALL;
2571 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2572 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2573 I40EVF_WRITE_FLUSH(hw);
2577 i40evf_config_rss(struct i40e_vf *vf)
2579 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2580 struct rte_eth_rss_conf rss_conf;
2581 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2584 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2585 i40evf_disable_rss(vf);
2586 PMD_DRV_LOG(DEBUG, "RSS not configured");
2590 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2591 /* Fill out the look up table */
2592 for (i = 0, j = 0; i < nb_q; i++, j++) {
2595 lut = (lut << 8) | j;
2597 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2600 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2601 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2602 i40evf_disable_rss(vf);
2603 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2607 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2608 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2609 /* Calculate the default hash key */
2610 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2611 rss_key_default[i] = (uint32_t)rte_rand();
2612 rss_conf.rss_key = (uint8_t *)rss_key_default;
2613 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2617 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2621 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2622 struct rte_eth_rss_conf *rss_conf)
2624 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2629 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2630 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2631 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2632 ? I40E_RSS_HENA_ALL_X722
2633 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2634 if (rss_hf != 0) /* Enable RSS */
2640 if (rss_hf == 0) /* Disable RSS */
2643 return i40evf_hw_rss_hash_set(vf, rss_conf);
2647 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2648 struct rte_eth_rss_conf *rss_conf)
2650 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2655 &rss_conf->rss_key_len);
2657 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2658 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2659 rss_conf->rss_hf = i40e_parse_hena(hena);
2665 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2667 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2668 struct rte_eth_dev_data *dev_data = vf->dev_data;
2669 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2672 /* check if mtu is within the allowed range */
2673 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2676 /* mtu setting is forbidden if port is start */
2677 if (dev_data->dev_started) {
2678 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2683 if (frame_size > ETHER_MAX_LEN)
2684 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2686 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2688 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2694 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2695 struct ether_addr *mac_addr)
2697 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2699 if (!is_valid_assigned_ether_addr(mac_addr)) {
2700 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2704 if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2707 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2710 i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2712 i40evf_add_mac_addr(dev, mac_addr, 0, 0);