4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
77 /*ITR index for NOITR*/
78 #define I40E_QINT_RQCTL_MSIX_INDX_NOITR 3
80 struct i40evf_arq_msg_info {
81 enum i40e_virtchnl_ops ops;
82 enum i40e_status_code result;
89 enum i40e_virtchnl_ops ops;
91 uint32_t in_args_size;
93 /* Input & output type. pass in buffer size and pass out
94 * actual return result
99 enum i40evf_aq_result {
100 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
101 I40EVF_MSG_NON, /* Read nothing from admin queue */
102 I40EVF_MSG_SYS, /* Read system msg from admin queue */
103 I40EVF_MSG_CMD, /* Read async command result */
106 /* A share buffer to store the command result from PF driver */
107 static uint8_t cmd_result_buffer[I40E_AQ_BUF_SZ];
109 static int i40evf_dev_configure(struct rte_eth_dev *dev);
110 static int i40evf_dev_start(struct rte_eth_dev *dev);
111 static void i40evf_dev_stop(struct rte_eth_dev *dev);
112 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
113 struct rte_eth_dev_info *dev_info);
114 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
115 __rte_unused int wait_to_complete);
116 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
117 struct rte_eth_stats *stats);
118 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
119 struct rte_eth_xstats *xstats, unsigned n);
120 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
121 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
122 uint16_t vlan_id, int on);
123 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
126 static void i40evf_dev_close(struct rte_eth_dev *dev);
127 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
129 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
130 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
131 static int i40evf_get_link_status(struct rte_eth_dev *dev,
132 struct rte_eth_link *link);
133 static int i40evf_init_vlan(struct rte_eth_dev *dev);
134 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
135 uint16_t rx_queue_id);
136 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
137 uint16_t rx_queue_id);
138 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
139 uint16_t tx_queue_id);
140 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
141 uint16_t tx_queue_id);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
158 /* Default hash key buffer for RSS */
159 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
161 struct rte_i40evf_xstats_name_off {
162 char name[RTE_ETH_XSTATS_NAME_SIZE];
166 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
167 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
168 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
169 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
170 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
171 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
172 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
173 rx_unknown_protocol)},
174 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
175 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
176 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
177 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
178 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
179 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
183 sizeof(rte_i40evf_stats_strings[0]))
185 static const struct eth_dev_ops i40evf_eth_dev_ops = {
186 .dev_configure = i40evf_dev_configure,
187 .dev_start = i40evf_dev_start,
188 .dev_stop = i40evf_dev_stop,
189 .promiscuous_enable = i40evf_dev_promiscuous_enable,
190 .promiscuous_disable = i40evf_dev_promiscuous_disable,
191 .allmulticast_enable = i40evf_dev_allmulticast_enable,
192 .allmulticast_disable = i40evf_dev_allmulticast_disable,
193 .link_update = i40evf_dev_link_update,
194 .stats_get = i40evf_dev_stats_get,
195 .xstats_get = i40evf_dev_xstats_get,
196 .xstats_reset = i40evf_dev_xstats_reset,
197 .dev_close = i40evf_dev_close,
198 .dev_infos_get = i40evf_dev_info_get,
199 .vlan_filter_set = i40evf_vlan_filter_set,
200 .vlan_offload_set = i40evf_vlan_offload_set,
201 .vlan_pvid_set = i40evf_vlan_pvid_set,
202 .rx_queue_start = i40evf_dev_rx_queue_start,
203 .rx_queue_stop = i40evf_dev_rx_queue_stop,
204 .tx_queue_start = i40evf_dev_tx_queue_start,
205 .tx_queue_stop = i40evf_dev_tx_queue_stop,
206 .rx_queue_setup = i40e_dev_rx_queue_setup,
207 .rx_queue_release = i40e_dev_rx_queue_release,
208 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
209 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
210 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
211 .tx_queue_setup = i40e_dev_tx_queue_setup,
212 .tx_queue_release = i40e_dev_tx_queue_release,
213 .reta_update = i40evf_dev_rss_reta_update,
214 .reta_query = i40evf_dev_rss_reta_query,
215 .rss_hash_update = i40evf_dev_rss_hash_update,
216 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
220 * Parse admin queue message.
225 * > 0: read cmd result
227 static enum i40evf_aq_result
228 i40evf_parse_pfmsg(struct i40e_vf *vf,
229 struct i40e_arq_event_info *event,
230 struct i40evf_arq_msg_info *data)
232 enum i40e_virtchnl_ops opcode = (enum i40e_virtchnl_ops)\
233 rte_le_to_cpu_32(event->desc.cookie_high);
234 enum i40e_status_code retval = (enum i40e_status_code)\
235 rte_le_to_cpu_32(event->desc.cookie_low);
236 enum i40evf_aq_result ret = I40EVF_MSG_CMD;
239 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
240 struct i40e_virtchnl_pf_event *vpe =
241 (struct i40e_virtchnl_pf_event *)event->msg_buf;
243 /* Initialize ret to sys event */
244 ret = I40EVF_MSG_SYS;
245 switch (vpe->event) {
246 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
248 vpe->event_data.link_event.link_status;
249 vf->pend_msg |= PFMSG_LINK_CHANGE;
250 PMD_DRV_LOG(INFO, "Link status update:%s",
251 vf->link_up ? "up" : "down");
253 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
255 vf->pend_msg |= PFMSG_RESET_IMPENDING;
256 PMD_DRV_LOG(INFO, "vf is reseting");
258 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
259 vf->dev_closed = true;
260 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
261 PMD_DRV_LOG(INFO, "PF driver closed");
264 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
265 __func__, vpe->event);
268 /* async reply msg on command issued by vf previously */
269 ret = I40EVF_MSG_CMD;
270 /* Actual data length read from PF */
271 data->msg_len = event->msg_len;
273 /* fill the ops and result to notify VF */
274 data->result = retval;
281 * Read data in admin queue to get msg from pf driver
283 static enum i40evf_aq_result
284 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
287 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
288 struct i40e_arq_event_info event;
290 enum i40evf_aq_result result = I40EVF_MSG_NON;
292 event.buf_len = data->buf_len;
293 event.msg_buf = data->msg;
294 ret = i40e_clean_arq_element(hw, &event, NULL);
295 /* Can't read any msg from adminQ */
297 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
298 result = I40EVF_MSG_NON;
300 result = I40EVF_MSG_ERR;
304 /* Parse the event */
305 result = i40evf_parse_pfmsg(vf, &event, data);
311 * Polling read until command result return from pf driver or meet error.
314 i40evf_wait_cmd_done(struct rte_eth_dev *dev,
315 struct i40evf_arq_msg_info *data)
318 enum i40evf_aq_result ret;
320 #define MAX_TRY_TIMES 20
321 #define ASQ_DELAY_MS 100
323 /* Delay some time first */
324 rte_delay_ms(ASQ_DELAY_MS);
325 ret = i40evf_read_pfmsg(dev, data);
326 if (ret == I40EVF_MSG_CMD)
328 else if (ret == I40EVF_MSG_ERR)
331 /* If don't read msg or read sys event, continue */
332 } while(i++ < MAX_TRY_TIMES);
338 * clear current command. Only call in case execute
339 * _atomic_set_cmd successfully.
342 _clear_cmd(struct i40e_vf *vf)
345 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
349 * Check there is pending cmd in execution. If none, set new command.
352 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
354 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
355 I40E_VIRTCHNL_OP_UNKNOWN, ops);
358 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
364 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
366 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
367 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
369 struct i40evf_arq_msg_info info;
371 if (_atomic_set_cmd(vf, args->ops))
374 info.msg = args->out_buffer;
375 info.buf_len = args->out_size;
376 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
377 info.result = I40E_SUCCESS;
379 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
380 args->in_args, args->in_args_size, NULL);
382 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
387 err = i40evf_wait_cmd_done(dev, &info);
388 /* read message and it's expected one */
389 if (!err && args->ops == info.ops)
392 PMD_DRV_LOG(ERR, "Failed to read message from AdminQ");
395 else if (args->ops != info.ops)
396 PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u",
397 args->ops, info.ops);
399 return err | info.result;
403 * Check API version with sync wait until version read or fail from admin queue
406 i40evf_check_api_version(struct rte_eth_dev *dev)
408 struct i40e_virtchnl_version_info version, *pver;
410 struct vf_cmd_info args;
411 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
413 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
414 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
416 args.ops = I40E_VIRTCHNL_OP_VERSION;
417 args.in_args = (uint8_t *)&version;
418 args.in_args_size = sizeof(version);
419 args.out_buffer = cmd_result_buffer;
420 args.out_size = I40E_AQ_BUF_SZ;
422 err = i40evf_execute_vf_cmd(dev, &args);
424 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
428 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
429 vf->version_major = pver->major;
430 vf->version_minor = pver->minor;
431 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
432 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
433 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
434 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
435 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
437 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
438 vf->version_major, vf->version_minor,
439 I40E_VIRTCHNL_VERSION_MAJOR,
440 I40E_VIRTCHNL_VERSION_MINOR);
448 i40evf_get_vf_resource(struct rte_eth_dev *dev)
450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
451 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
453 struct vf_cmd_info args;
456 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
457 args.out_buffer = cmd_result_buffer;
458 args.out_size = I40E_AQ_BUF_SZ;
460 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
461 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
462 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
463 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
464 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
465 args.in_args = (uint8_t *)∩︀
466 args.in_args_size = sizeof(caps);
469 args.in_args_size = 0;
471 err = i40evf_execute_vf_cmd(dev, &args);
474 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
478 len = sizeof(struct i40e_virtchnl_vf_resource) +
479 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
481 (void)rte_memcpy(vf->vf_res, args.out_buffer,
482 RTE_MIN(args.out_size, len));
483 i40e_vf_parse_hw_config(hw, vf->vf_res);
489 i40evf_config_promisc(struct rte_eth_dev *dev,
491 bool enable_multicast)
493 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
495 struct vf_cmd_info args;
496 struct i40e_virtchnl_promisc_info promisc;
499 promisc.vsi_id = vf->vsi_res->vsi_id;
502 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
504 if (enable_multicast)
505 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
507 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
508 args.in_args = (uint8_t *)&promisc;
509 args.in_args_size = sizeof(promisc);
510 args.out_buffer = cmd_result_buffer;
511 args.out_size = I40E_AQ_BUF_SZ;
513 err = i40evf_execute_vf_cmd(dev, &args);
516 PMD_DRV_LOG(ERR, "fail to execute command "
517 "CONFIG_PROMISCUOUS_MODE");
521 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
523 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
524 bool enable_vlan_strip)
526 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
528 struct vf_cmd_info args;
529 struct i40e_virtchnl_vlan_offload_info offload;
531 offload.vsi_id = vf->vsi_res->vsi_id;
532 offload.enable_vlan_strip = enable_vlan_strip;
534 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
535 args.in_args = (uint8_t *)&offload;
536 args.in_args_size = sizeof(offload);
537 args.out_buffer = cmd_result_buffer;
538 args.out_size = I40E_AQ_BUF_SZ;
540 err = i40evf_execute_vf_cmd(dev, &args);
542 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
548 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
549 struct i40e_vsi_vlan_pvid_info *info)
551 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
553 struct vf_cmd_info args;
554 struct i40e_virtchnl_pvid_info tpid_info;
556 if (dev == NULL || info == NULL) {
557 PMD_DRV_LOG(ERR, "invalid parameters");
558 return I40E_ERR_PARAM;
561 memset(&tpid_info, 0, sizeof(tpid_info));
562 tpid_info.vsi_id = vf->vsi_res->vsi_id;
563 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
565 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
566 args.in_args = (uint8_t *)&tpid_info;
567 args.in_args_size = sizeof(tpid_info);
568 args.out_buffer = cmd_result_buffer;
569 args.out_size = I40E_AQ_BUF_SZ;
571 err = i40evf_execute_vf_cmd(dev, &args);
573 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
579 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
583 struct i40e_tx_queue *txq)
585 txq_info->vsi_id = vsi_id;
586 txq_info->queue_id = queue_id;
587 if (queue_id < nb_txq) {
588 txq_info->ring_len = txq->nb_tx_desc;
589 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
594 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
598 uint32_t max_pkt_size,
599 struct i40e_rx_queue *rxq)
601 rxq_info->vsi_id = vsi_id;
602 rxq_info->queue_id = queue_id;
603 rxq_info->max_pkt_size = max_pkt_size;
604 if (queue_id < nb_rxq) {
605 rxq_info->ring_len = rxq->nb_rx_desc;
606 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
607 rxq_info->databuffer_size =
608 (rte_pktmbuf_data_room_size(rxq->mp) -
609 RTE_PKTMBUF_HEADROOM);
613 /* It configures VSI queues to co-work with Linux PF host */
615 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
617 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
618 struct i40e_rx_queue **rxq =
619 (struct i40e_rx_queue **)dev->data->rx_queues;
620 struct i40e_tx_queue **txq =
621 (struct i40e_tx_queue **)dev->data->tx_queues;
622 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
623 struct i40e_virtchnl_queue_pair_info *vc_qpi;
624 struct vf_cmd_info args;
625 uint16_t i, nb_qp = vf->num_queue_pairs;
626 const uint32_t size =
627 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
631 memset(buff, 0, sizeof(buff));
632 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
633 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
634 vc_vqci->num_queue_pairs = nb_qp;
636 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
637 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
638 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
639 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
640 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
641 vf->max_pkt_len, rxq[i]);
643 memset(&args, 0, sizeof(args));
644 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
645 args.in_args = (uint8_t *)vc_vqci;
646 args.in_args_size = size;
647 args.out_buffer = cmd_result_buffer;
648 args.out_size = I40E_AQ_BUF_SZ;
649 ret = i40evf_execute_vf_cmd(dev, &args);
651 PMD_DRV_LOG(ERR, "Failed to execute command of "
652 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
657 /* It configures VSI queues to co-work with DPDK PF host */
659 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
661 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
662 struct i40e_rx_queue **rxq =
663 (struct i40e_rx_queue **)dev->data->rx_queues;
664 struct i40e_tx_queue **txq =
665 (struct i40e_tx_queue **)dev->data->tx_queues;
666 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
667 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
668 struct vf_cmd_info args;
669 uint16_t i, nb_qp = vf->num_queue_pairs;
670 const uint32_t size =
671 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
675 memset(buff, 0, sizeof(buff));
676 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
677 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
678 vc_vqcei->num_queue_pairs = nb_qp;
679 vc_qpei = vc_vqcei->qpair;
680 for (i = 0; i < nb_qp; i++, vc_qpei++) {
681 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
682 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
683 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
684 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
685 vf->max_pkt_len, rxq[i]);
686 if (i < dev->data->nb_rx_queues)
688 * It adds extra info for configuring VSI queues, which
689 * is needed to enable the configurable crc stripping
692 vc_qpei->rxq_ext.crcstrip =
693 dev->data->dev_conf.rxmode.hw_strip_crc;
695 memset(&args, 0, sizeof(args));
697 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
698 args.in_args = (uint8_t *)vc_vqcei;
699 args.in_args_size = size;
700 args.out_buffer = cmd_result_buffer;
701 args.out_size = I40E_AQ_BUF_SZ;
702 ret = i40evf_execute_vf_cmd(dev, &args);
704 PMD_DRV_LOG(ERR, "Failed to execute command of "
705 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
711 i40evf_configure_queues(struct rte_eth_dev *dev)
713 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
715 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
716 /* To support DPDK PF host */
717 return i40evf_configure_vsi_queues_ext(dev);
719 /* To support Linux PF host */
720 return i40evf_configure_vsi_queues(dev);
724 i40evf_config_irq_map(struct rte_eth_dev *dev)
726 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
727 struct vf_cmd_info args;
728 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
729 sizeof(struct i40e_virtchnl_vector_map)];
730 struct i40e_virtchnl_irq_map_info *map_info;
731 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
735 if (rte_intr_allow_others(intr_handle)) {
736 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
737 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
739 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
741 vector_id = I40E_MISC_VEC_ID;
744 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
745 map_info->num_vectors = 1;
746 map_info->vecmap[0].rxitr_idx = I40E_QINT_RQCTL_MSIX_INDX_NOITR;
747 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
748 /* Alway use default dynamic MSIX interrupt */
749 map_info->vecmap[0].vector_id = vector_id;
750 /* Don't map any tx queue */
751 map_info->vecmap[0].txq_map = 0;
752 map_info->vecmap[0].rxq_map = 0;
753 for (i = 0; i < dev->data->nb_rx_queues; i++) {
754 map_info->vecmap[0].rxq_map |= 1 << i;
755 if (rte_intr_dp_is_en(intr_handle))
756 intr_handle->intr_vec[i] = vector_id;
759 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
760 args.in_args = (u8 *)cmd_buffer;
761 args.in_args_size = sizeof(cmd_buffer);
762 args.out_buffer = cmd_result_buffer;
763 args.out_size = I40E_AQ_BUF_SZ;
764 err = i40evf_execute_vf_cmd(dev, &args);
766 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
772 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
775 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
776 struct i40e_virtchnl_queue_select queue_select;
778 struct vf_cmd_info args;
779 memset(&queue_select, 0, sizeof(queue_select));
780 queue_select.vsi_id = vf->vsi_res->vsi_id;
783 queue_select.rx_queues |= 1 << qid;
785 queue_select.tx_queues |= 1 << qid;
788 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
790 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
791 args.in_args = (u8 *)&queue_select;
792 args.in_args_size = sizeof(queue_select);
793 args.out_buffer = cmd_result_buffer;
794 args.out_size = I40E_AQ_BUF_SZ;
795 err = i40evf_execute_vf_cmd(dev, &args);
797 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
798 isrx ? "RX" : "TX", qid, on ? "on" : "off");
804 i40evf_start_queues(struct rte_eth_dev *dev)
806 struct rte_eth_dev_data *dev_data = dev->data;
808 struct i40e_rx_queue *rxq;
809 struct i40e_tx_queue *txq;
811 for (i = 0; i < dev->data->nb_rx_queues; i++) {
812 rxq = dev_data->rx_queues[i];
813 if (rxq->rx_deferred_start)
815 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
816 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
821 for (i = 0; i < dev->data->nb_tx_queues; i++) {
822 txq = dev_data->tx_queues[i];
823 if (txq->tx_deferred_start)
825 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
826 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
835 i40evf_stop_queues(struct rte_eth_dev *dev)
839 /* Stop TX queues first */
840 for (i = 0; i < dev->data->nb_tx_queues; i++) {
841 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
842 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
847 /* Then stop RX queues */
848 for (i = 0; i < dev->data->nb_rx_queues; i++) {
849 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
850 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
859 i40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
861 struct i40e_virtchnl_ether_addr_list *list;
862 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
863 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
864 sizeof(struct i40e_virtchnl_ether_addr)];
866 struct vf_cmd_info args;
868 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
869 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
870 addr->addr_bytes[0], addr->addr_bytes[1],
871 addr->addr_bytes[2], addr->addr_bytes[3],
872 addr->addr_bytes[4], addr->addr_bytes[5]);
876 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
877 list->vsi_id = vf->vsi_res->vsi_id;
878 list->num_elements = 1;
879 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
880 sizeof(addr->addr_bytes));
882 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
883 args.in_args = cmd_buffer;
884 args.in_args_size = sizeof(cmd_buffer);
885 args.out_buffer = cmd_result_buffer;
886 args.out_size = I40E_AQ_BUF_SZ;
887 err = i40evf_execute_vf_cmd(dev, &args);
889 PMD_DRV_LOG(ERR, "fail to execute command "
890 "OP_ADD_ETHER_ADDRESS");
896 i40evf_del_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
898 struct i40e_virtchnl_ether_addr_list *list;
899 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
900 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
901 sizeof(struct i40e_virtchnl_ether_addr)];
903 struct vf_cmd_info args;
905 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
906 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
907 addr->addr_bytes[0], addr->addr_bytes[1],
908 addr->addr_bytes[2], addr->addr_bytes[3],
909 addr->addr_bytes[4], addr->addr_bytes[5]);
913 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
914 list->vsi_id = vf->vsi_res->vsi_id;
915 list->num_elements = 1;
916 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
917 sizeof(addr->addr_bytes));
919 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
920 args.in_args = cmd_buffer;
921 args.in_args_size = sizeof(cmd_buffer);
922 args.out_buffer = cmd_result_buffer;
923 args.out_size = I40E_AQ_BUF_SZ;
924 err = i40evf_execute_vf_cmd(dev, &args);
926 PMD_DRV_LOG(ERR, "fail to execute command "
927 "OP_DEL_ETHER_ADDRESS");
933 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
935 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
936 struct i40e_virtchnl_queue_select q_stats;
938 struct vf_cmd_info args;
940 memset(&q_stats, 0, sizeof(q_stats));
941 q_stats.vsi_id = vf->vsi_res->vsi_id;
942 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
943 args.in_args = (u8 *)&q_stats;
944 args.in_args_size = sizeof(q_stats);
945 args.out_buffer = cmd_result_buffer;
946 args.out_size = I40E_AQ_BUF_SZ;
948 err = i40evf_execute_vf_cmd(dev, &args);
950 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
954 *pstats = (struct i40e_eth_stats *)args.out_buffer;
959 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
962 struct i40e_eth_stats *pstats = NULL;
964 ret = i40evf_update_stats(dev, &pstats);
968 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
969 pstats->rx_broadcast;
970 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
972 stats->ierrors = pstats->rx_discards;
973 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
974 stats->ibytes = pstats->rx_bytes;
975 stats->obytes = pstats->tx_bytes;
981 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
983 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
984 struct i40e_eth_stats *pstats = NULL;
986 /* read stat values to clear hardware registers */
987 i40evf_update_stats(dev, &pstats);
989 /* set stats offset base on current values */
990 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
993 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
994 struct rte_eth_xstats *xstats, unsigned n)
998 struct i40e_eth_stats *pstats = NULL;
1000 if (n < I40EVF_NB_XSTATS)
1001 return I40EVF_NB_XSTATS;
1003 ret = i40evf_update_stats(dev, &pstats);
1010 /* loop over xstats array and values from pstats */
1011 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1012 snprintf(xstats[i].name, sizeof(xstats[i].name),
1013 "%s", rte_i40evf_stats_strings[i].name);
1014 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1015 rte_i40evf_stats_strings[i].offset);
1018 return I40EVF_NB_XSTATS;
1022 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1024 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1025 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1026 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1029 struct vf_cmd_info args;
1031 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1032 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1033 vlan_list->num_elements = 1;
1034 vlan_list->vlan_id[0] = vlanid;
1036 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1037 args.in_args = (u8 *)&cmd_buffer;
1038 args.in_args_size = sizeof(cmd_buffer);
1039 args.out_buffer = cmd_result_buffer;
1040 args.out_size = I40E_AQ_BUF_SZ;
1041 err = i40evf_execute_vf_cmd(dev, &args);
1043 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1049 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1051 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1052 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1053 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1056 struct vf_cmd_info args;
1058 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1059 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1060 vlan_list->num_elements = 1;
1061 vlan_list->vlan_id[0] = vlanid;
1063 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1064 args.in_args = (u8 *)&cmd_buffer;
1065 args.in_args_size = sizeof(cmd_buffer);
1066 args.out_buffer = cmd_result_buffer;
1067 args.out_size = I40E_AQ_BUF_SZ;
1068 err = i40evf_execute_vf_cmd(dev, &args);
1070 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1076 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1079 struct vf_cmd_info args;
1080 struct rte_eth_link *new_link;
1082 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1083 args.in_args = NULL;
1084 args.in_args_size = 0;
1085 args.out_buffer = cmd_result_buffer;
1086 args.out_size = I40E_AQ_BUF_SZ;
1087 err = i40evf_execute_vf_cmd(dev, &args);
1089 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1093 new_link = (struct rte_eth_link *)args.out_buffer;
1094 (void)rte_memcpy(link, new_link, sizeof(*link));
1099 static const struct rte_pci_id pci_id_i40evf_map[] = {
1100 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1101 #include "rte_pci_dev_ids.h"
1102 { .vendor_id = 0, /* sentinel */ },
1106 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1107 struct rte_eth_link *link)
1109 struct rte_eth_link *dst = &(dev->data->dev_link);
1110 struct rte_eth_link *src = link;
1112 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1113 *(uint64_t *)src) == 0)
1120 i40evf_reset_vf(struct i40e_hw *hw)
1124 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1129 * After issuing vf reset command to pf, pf won't necessarily
1130 * reset vf, it depends on what state it exactly is. If it's not
1131 * initialized yet, it won't have vf reset since it's in a certain
1132 * state. If not, it will try to reset. Even vf is reset, pf will
1133 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1134 * it to ACTIVE. In this duration, vf may not catch the moment that
1135 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1139 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1140 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1141 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1142 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1143 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1149 if (i >= MAX_RESET_WAIT_CNT) {
1150 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1158 i40evf_init_vf(struct rte_eth_dev *dev)
1161 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1162 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1163 struct ether_addr *p_mac_addr;
1165 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1166 vf->dev_data = dev->data;
1167 err = i40e_set_mac_type(hw);
1169 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1173 i40e_init_adminq_parameter(hw);
1174 err = i40e_init_adminq(hw);
1176 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1181 /* Reset VF and wait until it's complete */
1182 if (i40evf_reset_vf(hw)) {
1183 PMD_INIT_LOG(ERR, "reset NIC failed");
1187 /* VF reset, shutdown admin queue and initialize again */
1188 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1193 i40e_init_adminq_parameter(hw);
1194 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "init_adminq failed");
1198 if (i40evf_check_api_version(dev) != 0) {
1199 PMD_INIT_LOG(ERR, "check_api version failed");
1202 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1203 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1204 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1206 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1210 if (i40evf_get_vf_resource(dev) != 0) {
1211 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1215 /* got VF config message back from PF, now we can parse it */
1216 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1217 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1218 vf->vsi_res = &vf->vf_res->vsi_res[i];
1222 PMD_INIT_LOG(ERR, "no LAN VSI found");
1226 if (hw->mac.type == I40E_MAC_X722_VF)
1227 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1228 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1229 vf->vsi.type = vf->vsi_res->vsi_type;
1230 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1231 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1233 /* Store the MAC address configured by host, or generate random one */
1234 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1235 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1236 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1238 eth_random_addr(hw->mac.addr); /* Generate a random one */
1243 rte_free(vf->vf_res);
1245 i40e_shutdown_adminq(hw); /* ignore error */
1251 i40evf_uninit_vf(struct rte_eth_dev *dev)
1253 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1254 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1256 PMD_INIT_FUNC_TRACE();
1258 if (hw->adapter_stopped == 0)
1259 i40evf_dev_close(dev);
1260 rte_free(vf->vf_res);
1267 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1269 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1270 eth_dev->data->dev_private);
1272 PMD_INIT_FUNC_TRACE();
1274 /* assign ops func pointer */
1275 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1276 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1277 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1280 * For secondary processes, we don't initialise any further as primary
1281 * has already done this work.
1283 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1284 i40e_set_rx_function(eth_dev);
1285 i40e_set_tx_function(eth_dev);
1289 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1291 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1292 hw->device_id = eth_dev->pci_dev->id.device_id;
1293 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1294 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1295 hw->bus.device = eth_dev->pci_dev->addr.devid;
1296 hw->bus.func = eth_dev->pci_dev->addr.function;
1297 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1298 hw->adapter_stopped = 0;
1300 if(i40evf_init_vf(eth_dev) != 0) {
1301 PMD_INIT_LOG(ERR, "Init vf failed");
1306 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1308 if (eth_dev->data->mac_addrs == NULL) {
1309 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
1310 "store MAC addresses", ETHER_ADDR_LEN);
1313 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1314 (struct ether_addr *)eth_dev->data->mac_addrs);
1320 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1322 PMD_INIT_FUNC_TRACE();
1324 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1327 eth_dev->dev_ops = NULL;
1328 eth_dev->rx_pkt_burst = NULL;
1329 eth_dev->tx_pkt_burst = NULL;
1331 if (i40evf_uninit_vf(eth_dev) != 0) {
1332 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1336 rte_free(eth_dev->data->mac_addrs);
1337 eth_dev->data->mac_addrs = NULL;
1342 * virtual function driver struct
1344 static struct eth_driver rte_i40evf_pmd = {
1346 .name = "rte_i40evf_pmd",
1347 .id_table = pci_id_i40evf_map,
1348 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1350 .eth_dev_init = i40evf_dev_init,
1351 .eth_dev_uninit = i40evf_dev_uninit,
1352 .dev_private_size = sizeof(struct i40e_adapter),
1356 * VF Driver initialization routine.
1357 * Invoked one at EAL init time.
1358 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1361 rte_i40evf_pmd_init(const char *name __rte_unused,
1362 const char *params __rte_unused)
1364 PMD_INIT_FUNC_TRACE();
1366 rte_eth_driver_register(&rte_i40evf_pmd);
1371 static struct rte_driver rte_i40evf_driver = {
1373 .init = rte_i40evf_pmd_init,
1376 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1379 i40evf_dev_configure(struct rte_eth_dev *dev)
1381 struct i40e_adapter *ad =
1382 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1384 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1385 * allocation or vector Rx preconditions we will reset it.
1387 ad->rx_bulk_alloc_allowed = true;
1388 ad->rx_vec_allowed = true;
1389 ad->tx_simple_allowed = true;
1390 ad->tx_vec_allowed = true;
1392 return i40evf_init_vlan(dev);
1396 i40evf_init_vlan(struct rte_eth_dev *dev)
1398 struct rte_eth_dev_data *data = dev->data;
1401 /* Apply vlan offload setting */
1402 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1404 /* Apply pvid setting */
1405 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1406 data->dev_conf.txmode.hw_vlan_insert_pvid);
1411 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1413 bool enable_vlan_strip = 0;
1414 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1415 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1417 /* Linux pf host doesn't support vlan offload yet */
1418 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1419 /* Vlan stripping setting */
1420 if (mask & ETH_VLAN_STRIP_MASK) {
1421 /* Enable or disable VLAN stripping */
1422 if (dev_conf->rxmode.hw_vlan_strip)
1423 enable_vlan_strip = 1;
1425 enable_vlan_strip = 0;
1427 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1433 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1435 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1436 struct i40e_vsi_vlan_pvid_info info;
1437 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1439 memset(&info, 0, sizeof(info));
1442 /* Linux pf host don't support vlan offload yet */
1443 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1445 info.config.pvid = pvid;
1447 info.config.reject.tagged =
1448 dev_conf->txmode.hw_vlan_reject_tagged;
1449 info.config.reject.untagged =
1450 dev_conf->txmode.hw_vlan_reject_untagged;
1452 return i40evf_config_vlan_pvid(dev, &info);
1459 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1461 struct i40e_rx_queue *rxq;
1463 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1465 PMD_INIT_FUNC_TRACE();
1467 if (rx_queue_id < dev->data->nb_rx_queues) {
1468 rxq = dev->data->rx_queues[rx_queue_id];
1470 err = i40e_alloc_rx_queue_mbufs(rxq);
1472 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1478 /* Init the RX tail register. */
1479 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1480 I40EVF_WRITE_FLUSH(hw);
1482 /* Ready to switch the queue on */
1483 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1486 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1489 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1496 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1498 struct i40e_rx_queue *rxq;
1501 if (rx_queue_id < dev->data->nb_rx_queues) {
1502 rxq = dev->data->rx_queues[rx_queue_id];
1504 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1507 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1512 i40e_rx_queue_release_mbufs(rxq);
1513 i40e_reset_rx_queue(rxq);
1514 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1521 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1525 PMD_INIT_FUNC_TRACE();
1527 if (tx_queue_id < dev->data->nb_tx_queues) {
1529 /* Ready to switch the queue on */
1530 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1533 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1536 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1543 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1545 struct i40e_tx_queue *txq;
1548 if (tx_queue_id < dev->data->nb_tx_queues) {
1549 txq = dev->data->tx_queues[tx_queue_id];
1551 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1554 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1559 i40e_tx_queue_release_mbufs(txq);
1560 i40e_reset_tx_queue(txq);
1561 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1568 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1573 ret = i40evf_add_vlan(dev, vlan_id);
1575 ret = i40evf_del_vlan(dev,vlan_id);
1581 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1583 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584 struct rte_eth_dev_data *dev_data = dev->data;
1585 struct rte_pktmbuf_pool_private *mbp_priv;
1586 uint16_t buf_size, len;
1588 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1589 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1590 I40EVF_WRITE_FLUSH(hw);
1592 /* Calculate the maximum packet length allowed */
1593 mbp_priv = rte_mempool_get_priv(rxq->mp);
1594 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1595 RTE_PKTMBUF_HEADROOM);
1596 rxq->hs_mode = i40e_header_split_none;
1597 rxq->rx_hdr_len = 0;
1598 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1599 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1600 rxq->max_pkt_len = RTE_MIN(len,
1601 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1604 * Check if the jumbo frame and maximum packet length are set correctly
1606 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1607 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1608 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1609 PMD_DRV_LOG(ERR, "maximum packet length must be "
1610 "larger than %u and smaller than %u, as jumbo "
1611 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1612 (uint32_t)I40E_FRAME_SIZE_MAX);
1613 return I40E_ERR_CONFIG;
1616 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1617 rxq->max_pkt_len > ETHER_MAX_LEN) {
1618 PMD_DRV_LOG(ERR, "maximum packet length must be "
1619 "larger than %u and smaller than %u, as jumbo "
1620 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1621 (uint32_t)ETHER_MAX_LEN);
1622 return I40E_ERR_CONFIG;
1626 if (dev_data->dev_conf.rxmode.enable_scatter ||
1627 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1628 dev_data->scattered_rx = 1;
1635 i40evf_rx_init(struct rte_eth_dev *dev)
1637 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1639 int ret = I40E_SUCCESS;
1640 struct i40e_rx_queue **rxq =
1641 (struct i40e_rx_queue **)dev->data->rx_queues;
1643 i40evf_config_rss(vf);
1644 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1645 if (!rxq[i] || !rxq[i]->q_set)
1647 ret = i40evf_rxq_init(dev, rxq[i]);
1648 if (ret != I40E_SUCCESS)
1651 if (ret == I40E_SUCCESS)
1652 i40e_set_rx_function(dev);
1658 i40evf_tx_init(struct rte_eth_dev *dev)
1661 struct i40e_tx_queue **txq =
1662 (struct i40e_tx_queue **)dev->data->tx_queues;
1663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665 for (i = 0; i < dev->data->nb_tx_queues; i++)
1666 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1668 i40e_set_tx_function(dev);
1672 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1674 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1678 if (!rte_intr_allow_others(intr_handle)) {
1680 I40E_VFINT_DYN_CTL01,
1681 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1682 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
1683 I40EVF_WRITE_FLUSH(hw);
1687 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1688 /* To support DPDK PF host */
1690 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1691 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1692 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1694 /* To support Linux PF host */
1695 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1696 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1697 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
1699 I40EVF_WRITE_FLUSH(hw);
1703 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1705 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1709 if (!rte_intr_allow_others(intr_handle)) {
1710 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1711 I40EVF_WRITE_FLUSH(hw);
1715 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1717 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1721 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1723 I40EVF_WRITE_FLUSH(hw);
1727 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1729 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1735 msix_intr = intr_handle->intr_vec[queue_id];
1736 if (msix_intr == I40E_MISC_VEC_ID)
1737 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1738 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1739 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1740 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1742 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1745 I40E_VFINT_DYN_CTLN1(msix_intr -
1747 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1748 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1749 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1751 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1753 I40EVF_WRITE_FLUSH(hw);
1755 rte_intr_enable(&dev->pci_dev->intr_handle);
1761 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1763 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1764 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767 msix_intr = intr_handle->intr_vec[queue_id];
1768 if (msix_intr == I40E_MISC_VEC_ID)
1769 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1772 I40E_VFINT_DYN_CTLN1(msix_intr -
1776 I40EVF_WRITE_FLUSH(hw);
1782 i40evf_dev_start(struct rte_eth_dev *dev)
1784 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1785 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1787 struct ether_addr mac_addr;
1788 uint32_t intr_vector = 0;
1790 PMD_INIT_FUNC_TRACE();
1792 hw->adapter_stopped = 0;
1794 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1795 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1796 dev->data->nb_tx_queues);
1798 /* check and configure queue intr-vector mapping */
1799 if (dev->data->dev_conf.intr_conf.rxq != 0) {
1800 intr_vector = dev->data->nb_rx_queues;
1801 if (rte_intr_efd_enable(intr_handle, intr_vector))
1805 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1806 intr_handle->intr_vec =
1807 rte_zmalloc("intr_vec",
1808 dev->data->nb_rx_queues * sizeof(int), 0);
1809 if (!intr_handle->intr_vec) {
1810 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1811 " intr_vec\n", dev->data->nb_rx_queues);
1816 if (i40evf_rx_init(dev) != 0){
1817 PMD_DRV_LOG(ERR, "failed to do RX init");
1821 i40evf_tx_init(dev);
1823 if (i40evf_configure_queues(dev) != 0) {
1824 PMD_DRV_LOG(ERR, "configure queues failed");
1827 if (i40evf_config_irq_map(dev)) {
1828 PMD_DRV_LOG(ERR, "config_irq_map failed");
1833 (void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr,
1834 sizeof(mac_addr.addr_bytes));
1835 if (i40evf_add_mac_addr(dev, &mac_addr)) {
1836 PMD_DRV_LOG(ERR, "Failed to add mac addr");
1840 if (i40evf_start_queues(dev) != 0) {
1841 PMD_DRV_LOG(ERR, "enable queues failed");
1845 /* vf don't allow intr except for rxq intr */
1846 if (dev->data->dev_conf.intr_conf.rxq != 0)
1847 rte_intr_enable(intr_handle);
1849 i40evf_enable_queues_intr(dev);
1853 i40evf_del_mac_addr(dev, &mac_addr);
1859 i40evf_dev_stop(struct rte_eth_dev *dev)
1861 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1863 struct ether_addr mac_addr;
1865 PMD_INIT_FUNC_TRACE();
1867 i40evf_stop_queues(dev);
1868 i40evf_disable_queues_intr(dev);
1869 i40e_dev_clear_queues(dev);
1871 /* Clean datapath event and queue/vec mapping */
1872 rte_intr_efd_disable(intr_handle);
1873 if (intr_handle->intr_vec) {
1874 rte_free(intr_handle->intr_vec);
1875 intr_handle->intr_vec = NULL;
1878 (void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr,
1879 sizeof(mac_addr.addr_bytes));
1880 /* Delete mac addr of this vf */
1881 i40evf_del_mac_addr(dev, &mac_addr);
1885 i40evf_dev_link_update(struct rte_eth_dev *dev,
1886 __rte_unused int wait_to_complete)
1888 struct rte_eth_link new_link;
1889 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1891 * DPDK pf host provide interfacet to acquire link status
1892 * while Linux driver does not
1894 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1895 i40evf_get_link_status(dev, &new_link);
1897 /* Always assume it's up, for Linux driver PF host */
1898 new_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;
1899 new_link.link_speed = ETH_LINK_SPEED_10000;
1900 new_link.link_status = 1;
1902 i40evf_dev_atomic_write_link_status(dev, &new_link);
1908 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
1910 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1913 /* If enabled, just return */
1914 if (vf->promisc_unicast_enabled)
1917 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
1919 vf->promisc_unicast_enabled = TRUE;
1923 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
1925 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1928 /* If disabled, just return */
1929 if (!vf->promisc_unicast_enabled)
1932 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
1934 vf->promisc_unicast_enabled = FALSE;
1938 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
1940 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1943 /* If enabled, just return */
1944 if (vf->promisc_multicast_enabled)
1947 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
1949 vf->promisc_multicast_enabled = TRUE;
1953 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
1955 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1958 /* If enabled, just return */
1959 if (!vf->promisc_multicast_enabled)
1962 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
1964 vf->promisc_multicast_enabled = FALSE;
1968 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1970 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1972 memset(dev_info, 0, sizeof(*dev_info));
1973 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
1974 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
1975 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1976 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1977 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1978 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
1979 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1980 dev_info->rx_offload_capa =
1981 DEV_RX_OFFLOAD_VLAN_STRIP |
1982 DEV_RX_OFFLOAD_QINQ_STRIP |
1983 DEV_RX_OFFLOAD_IPV4_CKSUM |
1984 DEV_RX_OFFLOAD_UDP_CKSUM |
1985 DEV_RX_OFFLOAD_TCP_CKSUM;
1986 dev_info->tx_offload_capa =
1987 DEV_TX_OFFLOAD_VLAN_INSERT |
1988 DEV_TX_OFFLOAD_QINQ_INSERT |
1989 DEV_TX_OFFLOAD_IPV4_CKSUM |
1990 DEV_TX_OFFLOAD_UDP_CKSUM |
1991 DEV_TX_OFFLOAD_TCP_CKSUM |
1992 DEV_TX_OFFLOAD_SCTP_CKSUM;
1994 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1996 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1997 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1998 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2000 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2004 dev_info->default_txconf = (struct rte_eth_txconf) {
2006 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2007 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2008 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2010 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2011 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2012 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2013 ETH_TXQ_FLAGS_NOOFFLOADS,
2016 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2017 .nb_max = I40E_MAX_RING_DESC,
2018 .nb_min = I40E_MIN_RING_DESC,
2019 .nb_align = I40E_ALIGN_RING_DESC,
2022 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2023 .nb_max = I40E_MAX_RING_DESC,
2024 .nb_min = I40E_MIN_RING_DESC,
2025 .nb_align = I40E_ALIGN_RING_DESC,
2030 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2032 if (i40evf_get_statics(dev, stats))
2033 PMD_DRV_LOG(ERR, "Get statics failed");
2037 i40evf_dev_close(struct rte_eth_dev *dev)
2039 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041 i40evf_dev_stop(dev);
2042 hw->adapter_stopped = 1;
2043 i40e_dev_free_queues(dev);
2044 i40evf_reset_vf(hw);
2045 i40e_shutdown_adminq(hw);
2049 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2051 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2058 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2059 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2062 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2066 uint32_t *lut_dw = (uint32_t *)lut;
2067 uint16_t i, lut_size_dw = lut_size / 4;
2069 for (i = 0; i < lut_size_dw; i++)
2070 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2077 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2079 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2080 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2086 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2087 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2090 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2094 uint32_t *lut_dw = (uint32_t *)lut;
2095 uint16_t i, lut_size_dw = lut_size / 4;
2097 for (i = 0; i < lut_size_dw; i++)
2098 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2099 I40EVF_WRITE_FLUSH(hw);
2106 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2107 struct rte_eth_rss_reta_entry64 *reta_conf,
2110 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2112 uint16_t i, idx, shift;
2115 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2116 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2117 "(%d) doesn't match the number of hardware can "
2118 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2122 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2124 PMD_DRV_LOG(ERR, "No memory can be allocated");
2127 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2130 for (i = 0; i < reta_size; i++) {
2131 idx = i / RTE_RETA_GROUP_SIZE;
2132 shift = i % RTE_RETA_GROUP_SIZE;
2133 if (reta_conf[idx].mask & (1ULL << shift))
2134 lut[i] = reta_conf[idx].reta[shift];
2136 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2145 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2146 struct rte_eth_rss_reta_entry64 *reta_conf,
2149 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2150 uint16_t i, idx, shift;
2154 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2155 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2156 "(%d) doesn't match the number of hardware can "
2157 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2161 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2163 PMD_DRV_LOG(ERR, "No memory can be allocated");
2167 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2170 for (i = 0; i < reta_size; i++) {
2171 idx = i / RTE_RETA_GROUP_SIZE;
2172 shift = i % RTE_RETA_GROUP_SIZE;
2173 if (reta_conf[idx].mask & (1ULL << shift))
2174 reta_conf[idx].reta[shift] = lut[i];
2184 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2186 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2187 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2190 if (!key || key_len == 0) {
2191 PMD_DRV_LOG(DEBUG, "No key to be configured");
2193 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2195 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2199 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2200 struct i40e_aqc_get_set_rss_key_data *key_dw =
2201 (struct i40e_aqc_get_set_rss_key_data *)key;
2203 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2205 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2208 uint32_t *hash_key = (uint32_t *)key;
2211 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2212 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2213 I40EVF_WRITE_FLUSH(hw);
2220 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2222 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2223 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2226 if (!key || !key_len)
2229 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2230 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2231 (struct i40e_aqc_get_set_rss_key_data *)key);
2233 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2237 uint32_t *key_dw = (uint32_t *)key;
2240 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2241 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2243 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2249 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2251 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2252 uint64_t rss_hf, hena;
2255 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2256 rss_conf->rss_key_len);
2260 rss_hf = rss_conf->rss_hf;
2261 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2262 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2263 hena &= ~I40E_RSS_HENA_ALL;
2264 hena |= i40e_config_hena(rss_hf);
2265 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2266 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2267 I40EVF_WRITE_FLUSH(hw);
2273 i40evf_disable_rss(struct i40e_vf *vf)
2275 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2278 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2279 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2280 hena &= ~I40E_RSS_HENA_ALL;
2281 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2282 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2283 I40EVF_WRITE_FLUSH(hw);
2287 i40evf_config_rss(struct i40e_vf *vf)
2289 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2290 struct rte_eth_rss_conf rss_conf;
2291 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2294 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2295 i40evf_disable_rss(vf);
2296 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2300 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2301 /* Fill out the look up table */
2302 for (i = 0, j = 0; i < nb_q; i++, j++) {
2305 lut = (lut << 8) | j;
2307 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2310 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2311 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2312 i40evf_disable_rss(vf);
2313 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2317 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2318 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2319 /* Calculate the default hash key */
2320 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2321 rss_key_default[i] = (uint32_t)rte_rand();
2322 rss_conf.rss_key = (uint8_t *)rss_key_default;
2323 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2327 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2331 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2332 struct rte_eth_rss_conf *rss_conf)
2334 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2335 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2339 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2340 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2341 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2342 if (rss_hf != 0) /* Enable RSS */
2348 if (rss_hf == 0) /* Disable RSS */
2351 return i40evf_hw_rss_hash_set(vf, rss_conf);
2355 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2356 struct rte_eth_rss_conf *rss_conf)
2358 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2363 &rss_conf->rss_key_len);
2365 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2366 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2367 rss_conf->rss_hf = i40e_parse_hena(hena);