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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
77 /*ITR index for NOITR*/
78 #define I40E_QINT_RQCTL_MSIX_INDX_NOITR 3
80 struct i40evf_arq_msg_info {
81 enum i40e_virtchnl_ops ops;
82 enum i40e_status_code result;
89 enum i40e_virtchnl_ops ops;
91 uint32_t in_args_size;
93 /* Input & output type. pass in buffer size and pass out
94 * actual return result
99 enum i40evf_aq_result {
100 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
101 I40EVF_MSG_NON, /* Read nothing from admin queue */
102 I40EVF_MSG_SYS, /* Read system msg from admin queue */
103 I40EVF_MSG_CMD, /* Read async command result */
106 /* A share buffer to store the command result from PF driver */
107 static uint8_t cmd_result_buffer[I40E_AQ_BUF_SZ];
109 static int i40evf_dev_configure(struct rte_eth_dev *dev);
110 static int i40evf_dev_start(struct rte_eth_dev *dev);
111 static void i40evf_dev_stop(struct rte_eth_dev *dev);
112 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
113 struct rte_eth_dev_info *dev_info);
114 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
115 __rte_unused int wait_to_complete);
116 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
117 struct rte_eth_stats *stats);
118 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
119 struct rte_eth_xstats *xstats, unsigned n);
120 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
121 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
122 uint16_t vlan_id, int on);
123 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
126 static void i40evf_dev_close(struct rte_eth_dev *dev);
127 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
129 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
130 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
131 static int i40evf_get_link_status(struct rte_eth_dev *dev,
132 struct rte_eth_link *link);
133 static int i40evf_init_vlan(struct rte_eth_dev *dev);
134 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
135 uint16_t rx_queue_id);
136 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
137 uint16_t rx_queue_id);
138 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
139 uint16_t tx_queue_id);
140 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
141 uint16_t tx_queue_id);
142 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
143 struct ether_addr *addr,
146 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
147 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
148 struct rte_eth_rss_reta_entry64 *reta_conf,
150 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
151 struct rte_eth_rss_reta_entry64 *reta_conf,
153 static int i40evf_config_rss(struct i40e_vf *vf);
154 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
155 struct rte_eth_rss_conf *rss_conf);
156 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
157 struct rte_eth_rss_conf *rss_conf);
159 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
161 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
163 /* Default hash key buffer for RSS */
164 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
166 struct rte_i40evf_xstats_name_off {
167 char name[RTE_ETH_XSTATS_NAME_SIZE];
171 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
172 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
173 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
174 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
175 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
176 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
177 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
178 rx_unknown_protocol)},
179 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
180 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
183 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
184 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
187 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
188 sizeof(rte_i40evf_stats_strings[0]))
190 static const struct eth_dev_ops i40evf_eth_dev_ops = {
191 .dev_configure = i40evf_dev_configure,
192 .dev_start = i40evf_dev_start,
193 .dev_stop = i40evf_dev_stop,
194 .promiscuous_enable = i40evf_dev_promiscuous_enable,
195 .promiscuous_disable = i40evf_dev_promiscuous_disable,
196 .allmulticast_enable = i40evf_dev_allmulticast_enable,
197 .allmulticast_disable = i40evf_dev_allmulticast_disable,
198 .link_update = i40evf_dev_link_update,
199 .stats_get = i40evf_dev_stats_get,
200 .xstats_get = i40evf_dev_xstats_get,
201 .xstats_reset = i40evf_dev_xstats_reset,
202 .dev_close = i40evf_dev_close,
203 .dev_infos_get = i40evf_dev_info_get,
204 .vlan_filter_set = i40evf_vlan_filter_set,
205 .vlan_offload_set = i40evf_vlan_offload_set,
206 .vlan_pvid_set = i40evf_vlan_pvid_set,
207 .rx_queue_start = i40evf_dev_rx_queue_start,
208 .rx_queue_stop = i40evf_dev_rx_queue_stop,
209 .tx_queue_start = i40evf_dev_tx_queue_start,
210 .tx_queue_stop = i40evf_dev_tx_queue_stop,
211 .rx_queue_setup = i40e_dev_rx_queue_setup,
212 .rx_queue_release = i40e_dev_rx_queue_release,
213 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
214 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
215 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
216 .tx_queue_setup = i40e_dev_tx_queue_setup,
217 .tx_queue_release = i40e_dev_tx_queue_release,
218 .mac_addr_add = i40evf_add_mac_addr,
219 .mac_addr_remove = i40evf_del_mac_addr,
220 .reta_update = i40evf_dev_rss_reta_update,
221 .reta_query = i40evf_dev_rss_reta_query,
222 .rss_hash_update = i40evf_dev_rss_hash_update,
223 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
227 * Parse admin queue message.
232 * > 0: read cmd result
234 static enum i40evf_aq_result
235 i40evf_parse_pfmsg(struct i40e_vf *vf,
236 struct i40e_arq_event_info *event,
237 struct i40evf_arq_msg_info *data)
239 enum i40e_virtchnl_ops opcode = (enum i40e_virtchnl_ops)\
240 rte_le_to_cpu_32(event->desc.cookie_high);
241 enum i40e_status_code retval = (enum i40e_status_code)\
242 rte_le_to_cpu_32(event->desc.cookie_low);
243 enum i40evf_aq_result ret = I40EVF_MSG_CMD;
246 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
247 struct i40e_virtchnl_pf_event *vpe =
248 (struct i40e_virtchnl_pf_event *)event->msg_buf;
250 /* Initialize ret to sys event */
251 ret = I40EVF_MSG_SYS;
252 switch (vpe->event) {
253 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
255 vpe->event_data.link_event.link_status;
256 vf->pend_msg |= PFMSG_LINK_CHANGE;
257 PMD_DRV_LOG(INFO, "Link status update:%s",
258 vf->link_up ? "up" : "down");
260 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
262 vf->pend_msg |= PFMSG_RESET_IMPENDING;
263 PMD_DRV_LOG(INFO, "vf is reseting");
265 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
266 vf->dev_closed = true;
267 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
268 PMD_DRV_LOG(INFO, "PF driver closed");
271 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
272 __func__, vpe->event);
275 /* async reply msg on command issued by vf previously */
276 ret = I40EVF_MSG_CMD;
277 /* Actual data length read from PF */
278 data->msg_len = event->msg_len;
280 /* fill the ops and result to notify VF */
281 data->result = retval;
288 * Read data in admin queue to get msg from pf driver
290 static enum i40evf_aq_result
291 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
294 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
295 struct i40e_arq_event_info event;
297 enum i40evf_aq_result result = I40EVF_MSG_NON;
299 event.buf_len = data->buf_len;
300 event.msg_buf = data->msg;
301 ret = i40e_clean_arq_element(hw, &event, NULL);
302 /* Can't read any msg from adminQ */
304 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
305 result = I40EVF_MSG_NON;
307 result = I40EVF_MSG_ERR;
311 /* Parse the event */
312 result = i40evf_parse_pfmsg(vf, &event, data);
318 * Polling read until command result return from pf driver or meet error.
321 i40evf_wait_cmd_done(struct rte_eth_dev *dev,
322 struct i40evf_arq_msg_info *data)
325 enum i40evf_aq_result ret;
327 #define MAX_TRY_TIMES 20
328 #define ASQ_DELAY_MS 100
330 /* Delay some time first */
331 rte_delay_ms(ASQ_DELAY_MS);
332 ret = i40evf_read_pfmsg(dev, data);
333 if (ret == I40EVF_MSG_CMD)
335 else if (ret == I40EVF_MSG_ERR)
338 /* If don't read msg or read sys event, continue */
339 } while(i++ < MAX_TRY_TIMES);
345 * clear current command. Only call in case execute
346 * _atomic_set_cmd successfully.
349 _clear_cmd(struct i40e_vf *vf)
352 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
356 * Check there is pending cmd in execution. If none, set new command.
359 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
361 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
362 I40E_VIRTCHNL_OP_UNKNOWN, ops);
365 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
371 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
374 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
376 struct i40evf_arq_msg_info info;
378 if (_atomic_set_cmd(vf, args->ops))
381 info.msg = args->out_buffer;
382 info.buf_len = args->out_size;
383 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
384 info.result = I40E_SUCCESS;
386 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
387 args->in_args, args->in_args_size, NULL);
389 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
394 err = i40evf_wait_cmd_done(dev, &info);
395 /* read message and it's expected one */
396 if (!err && args->ops == info.ops)
399 PMD_DRV_LOG(ERR, "Failed to read message from AdminQ");
402 else if (args->ops != info.ops)
403 PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u",
404 args->ops, info.ops);
406 return err | info.result;
410 * Check API version with sync wait until version read or fail from admin queue
413 i40evf_check_api_version(struct rte_eth_dev *dev)
415 struct i40e_virtchnl_version_info version, *pver;
417 struct vf_cmd_info args;
418 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
420 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
421 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
423 args.ops = I40E_VIRTCHNL_OP_VERSION;
424 args.in_args = (uint8_t *)&version;
425 args.in_args_size = sizeof(version);
426 args.out_buffer = cmd_result_buffer;
427 args.out_size = I40E_AQ_BUF_SZ;
429 err = i40evf_execute_vf_cmd(dev, &args);
431 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
435 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
436 vf->version_major = pver->major;
437 vf->version_minor = pver->minor;
438 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
439 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
440 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
441 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
442 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
444 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
445 vf->version_major, vf->version_minor,
446 I40E_VIRTCHNL_VERSION_MAJOR,
447 I40E_VIRTCHNL_VERSION_MINOR);
455 i40evf_get_vf_resource(struct rte_eth_dev *dev)
457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
458 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
460 struct vf_cmd_info args;
463 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
464 args.out_buffer = cmd_result_buffer;
465 args.out_size = I40E_AQ_BUF_SZ;
467 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
468 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
469 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
470 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
471 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
472 args.in_args = (uint8_t *)∩︀
473 args.in_args_size = sizeof(caps);
476 args.in_args_size = 0;
478 err = i40evf_execute_vf_cmd(dev, &args);
481 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
485 len = sizeof(struct i40e_virtchnl_vf_resource) +
486 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
488 (void)rte_memcpy(vf->vf_res, args.out_buffer,
489 RTE_MIN(args.out_size, len));
490 i40e_vf_parse_hw_config(hw, vf->vf_res);
496 i40evf_config_promisc(struct rte_eth_dev *dev,
498 bool enable_multicast)
500 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
502 struct vf_cmd_info args;
503 struct i40e_virtchnl_promisc_info promisc;
506 promisc.vsi_id = vf->vsi_res->vsi_id;
509 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
511 if (enable_multicast)
512 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
514 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
515 args.in_args = (uint8_t *)&promisc;
516 args.in_args_size = sizeof(promisc);
517 args.out_buffer = cmd_result_buffer;
518 args.out_size = I40E_AQ_BUF_SZ;
520 err = i40evf_execute_vf_cmd(dev, &args);
523 PMD_DRV_LOG(ERR, "fail to execute command "
524 "CONFIG_PROMISCUOUS_MODE");
528 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
530 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
531 bool enable_vlan_strip)
533 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
535 struct vf_cmd_info args;
536 struct i40e_virtchnl_vlan_offload_info offload;
538 offload.vsi_id = vf->vsi_res->vsi_id;
539 offload.enable_vlan_strip = enable_vlan_strip;
541 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
542 args.in_args = (uint8_t *)&offload;
543 args.in_args_size = sizeof(offload);
544 args.out_buffer = cmd_result_buffer;
545 args.out_size = I40E_AQ_BUF_SZ;
547 err = i40evf_execute_vf_cmd(dev, &args);
549 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
555 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
556 struct i40e_vsi_vlan_pvid_info *info)
558 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
560 struct vf_cmd_info args;
561 struct i40e_virtchnl_pvid_info tpid_info;
563 if (dev == NULL || info == NULL) {
564 PMD_DRV_LOG(ERR, "invalid parameters");
565 return I40E_ERR_PARAM;
568 memset(&tpid_info, 0, sizeof(tpid_info));
569 tpid_info.vsi_id = vf->vsi_res->vsi_id;
570 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
572 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
573 args.in_args = (uint8_t *)&tpid_info;
574 args.in_args_size = sizeof(tpid_info);
575 args.out_buffer = cmd_result_buffer;
576 args.out_size = I40E_AQ_BUF_SZ;
578 err = i40evf_execute_vf_cmd(dev, &args);
580 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
586 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
590 struct i40e_tx_queue *txq)
592 txq_info->vsi_id = vsi_id;
593 txq_info->queue_id = queue_id;
594 if (queue_id < nb_txq) {
595 txq_info->ring_len = txq->nb_tx_desc;
596 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
601 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
605 uint32_t max_pkt_size,
606 struct i40e_rx_queue *rxq)
608 rxq_info->vsi_id = vsi_id;
609 rxq_info->queue_id = queue_id;
610 rxq_info->max_pkt_size = max_pkt_size;
611 if (queue_id < nb_rxq) {
612 rxq_info->ring_len = rxq->nb_rx_desc;
613 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
614 rxq_info->databuffer_size =
615 (rte_pktmbuf_data_room_size(rxq->mp) -
616 RTE_PKTMBUF_HEADROOM);
620 /* It configures VSI queues to co-work with Linux PF host */
622 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
624 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
625 struct i40e_rx_queue **rxq =
626 (struct i40e_rx_queue **)dev->data->rx_queues;
627 struct i40e_tx_queue **txq =
628 (struct i40e_tx_queue **)dev->data->tx_queues;
629 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
630 struct i40e_virtchnl_queue_pair_info *vc_qpi;
631 struct vf_cmd_info args;
632 uint16_t i, nb_qp = vf->num_queue_pairs;
633 const uint32_t size =
634 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
638 memset(buff, 0, sizeof(buff));
639 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
640 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
641 vc_vqci->num_queue_pairs = nb_qp;
643 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
644 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
645 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
646 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
647 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
648 vf->max_pkt_len, rxq[i]);
650 memset(&args, 0, sizeof(args));
651 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
652 args.in_args = (uint8_t *)vc_vqci;
653 args.in_args_size = size;
654 args.out_buffer = cmd_result_buffer;
655 args.out_size = I40E_AQ_BUF_SZ;
656 ret = i40evf_execute_vf_cmd(dev, &args);
658 PMD_DRV_LOG(ERR, "Failed to execute command of "
659 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
664 /* It configures VSI queues to co-work with DPDK PF host */
666 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
668 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
669 struct i40e_rx_queue **rxq =
670 (struct i40e_rx_queue **)dev->data->rx_queues;
671 struct i40e_tx_queue **txq =
672 (struct i40e_tx_queue **)dev->data->tx_queues;
673 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
674 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
675 struct vf_cmd_info args;
676 uint16_t i, nb_qp = vf->num_queue_pairs;
677 const uint32_t size =
678 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
682 memset(buff, 0, sizeof(buff));
683 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
684 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
685 vc_vqcei->num_queue_pairs = nb_qp;
686 vc_qpei = vc_vqcei->qpair;
687 for (i = 0; i < nb_qp; i++, vc_qpei++) {
688 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
689 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
690 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
691 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
692 vf->max_pkt_len, rxq[i]);
693 if (i < dev->data->nb_rx_queues)
695 * It adds extra info for configuring VSI queues, which
696 * is needed to enable the configurable crc stripping
699 vc_qpei->rxq_ext.crcstrip =
700 dev->data->dev_conf.rxmode.hw_strip_crc;
702 memset(&args, 0, sizeof(args));
704 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
705 args.in_args = (uint8_t *)vc_vqcei;
706 args.in_args_size = size;
707 args.out_buffer = cmd_result_buffer;
708 args.out_size = I40E_AQ_BUF_SZ;
709 ret = i40evf_execute_vf_cmd(dev, &args);
711 PMD_DRV_LOG(ERR, "Failed to execute command of "
712 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
718 i40evf_configure_queues(struct rte_eth_dev *dev)
720 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
722 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
723 /* To support DPDK PF host */
724 return i40evf_configure_vsi_queues_ext(dev);
726 /* To support Linux PF host */
727 return i40evf_configure_vsi_queues(dev);
731 i40evf_config_irq_map(struct rte_eth_dev *dev)
733 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
734 struct vf_cmd_info args;
735 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
736 sizeof(struct i40e_virtchnl_vector_map)];
737 struct i40e_virtchnl_irq_map_info *map_info;
738 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
742 if (rte_intr_allow_others(intr_handle)) {
743 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
744 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
746 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
748 vector_id = I40E_MISC_VEC_ID;
751 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
752 map_info->num_vectors = 1;
753 map_info->vecmap[0].rxitr_idx = I40E_QINT_RQCTL_MSIX_INDX_NOITR;
754 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
755 /* Alway use default dynamic MSIX interrupt */
756 map_info->vecmap[0].vector_id = vector_id;
757 /* Don't map any tx queue */
758 map_info->vecmap[0].txq_map = 0;
759 map_info->vecmap[0].rxq_map = 0;
760 for (i = 0; i < dev->data->nb_rx_queues; i++) {
761 map_info->vecmap[0].rxq_map |= 1 << i;
762 if (rte_intr_dp_is_en(intr_handle))
763 intr_handle->intr_vec[i] = vector_id;
766 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
767 args.in_args = (u8 *)cmd_buffer;
768 args.in_args_size = sizeof(cmd_buffer);
769 args.out_buffer = cmd_result_buffer;
770 args.out_size = I40E_AQ_BUF_SZ;
771 err = i40evf_execute_vf_cmd(dev, &args);
773 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
779 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
782 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
783 struct i40e_virtchnl_queue_select queue_select;
785 struct vf_cmd_info args;
786 memset(&queue_select, 0, sizeof(queue_select));
787 queue_select.vsi_id = vf->vsi_res->vsi_id;
790 queue_select.rx_queues |= 1 << qid;
792 queue_select.tx_queues |= 1 << qid;
795 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
797 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
798 args.in_args = (u8 *)&queue_select;
799 args.in_args_size = sizeof(queue_select);
800 args.out_buffer = cmd_result_buffer;
801 args.out_size = I40E_AQ_BUF_SZ;
802 err = i40evf_execute_vf_cmd(dev, &args);
804 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
805 isrx ? "RX" : "TX", qid, on ? "on" : "off");
811 i40evf_start_queues(struct rte_eth_dev *dev)
813 struct rte_eth_dev_data *dev_data = dev->data;
815 struct i40e_rx_queue *rxq;
816 struct i40e_tx_queue *txq;
818 for (i = 0; i < dev->data->nb_rx_queues; i++) {
819 rxq = dev_data->rx_queues[i];
820 if (rxq->rx_deferred_start)
822 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
823 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
828 for (i = 0; i < dev->data->nb_tx_queues; i++) {
829 txq = dev_data->tx_queues[i];
830 if (txq->tx_deferred_start)
832 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
833 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
842 i40evf_stop_queues(struct rte_eth_dev *dev)
846 /* Stop TX queues first */
847 for (i = 0; i < dev->data->nb_tx_queues; i++) {
848 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
849 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
854 /* Then stop RX queues */
855 for (i = 0; i < dev->data->nb_rx_queues; i++) {
856 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
857 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
866 i40evf_add_mac_addr(struct rte_eth_dev *dev,
867 struct ether_addr *addr,
868 __rte_unused uint32_t index,
869 __rte_unused uint32_t pool)
871 struct i40e_virtchnl_ether_addr_list *list;
872 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
873 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
874 sizeof(struct i40e_virtchnl_ether_addr)];
876 struct vf_cmd_info args;
878 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
879 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
880 addr->addr_bytes[0], addr->addr_bytes[1],
881 addr->addr_bytes[2], addr->addr_bytes[3],
882 addr->addr_bytes[4], addr->addr_bytes[5]);
886 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
887 list->vsi_id = vf->vsi_res->vsi_id;
888 list->num_elements = 1;
889 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
890 sizeof(addr->addr_bytes));
892 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
893 args.in_args = cmd_buffer;
894 args.in_args_size = sizeof(cmd_buffer);
895 args.out_buffer = cmd_result_buffer;
896 args.out_size = I40E_AQ_BUF_SZ;
897 err = i40evf_execute_vf_cmd(dev, &args);
899 PMD_DRV_LOG(ERR, "fail to execute command "
900 "OP_ADD_ETHER_ADDRESS");
906 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
908 struct i40e_virtchnl_ether_addr_list *list;
909 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
910 struct rte_eth_dev_data *data = dev->data;
911 struct ether_addr *addr;
912 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
913 sizeof(struct i40e_virtchnl_ether_addr)];
915 struct vf_cmd_info args;
917 addr = &(data->mac_addrs[index]);
919 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
920 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
921 addr->addr_bytes[0], addr->addr_bytes[1],
922 addr->addr_bytes[2], addr->addr_bytes[3],
923 addr->addr_bytes[4], addr->addr_bytes[5]);
927 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
928 list->vsi_id = vf->vsi_res->vsi_id;
929 list->num_elements = 1;
930 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
931 sizeof(addr->addr_bytes));
933 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
934 args.in_args = cmd_buffer;
935 args.in_args_size = sizeof(cmd_buffer);
936 args.out_buffer = cmd_result_buffer;
937 args.out_size = I40E_AQ_BUF_SZ;
938 err = i40evf_execute_vf_cmd(dev, &args);
940 PMD_DRV_LOG(ERR, "fail to execute command "
941 "OP_DEL_ETHER_ADDRESS");
946 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
948 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
949 struct i40e_virtchnl_queue_select q_stats;
951 struct vf_cmd_info args;
953 memset(&q_stats, 0, sizeof(q_stats));
954 q_stats.vsi_id = vf->vsi_res->vsi_id;
955 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
956 args.in_args = (u8 *)&q_stats;
957 args.in_args_size = sizeof(q_stats);
958 args.out_buffer = cmd_result_buffer;
959 args.out_size = I40E_AQ_BUF_SZ;
961 err = i40evf_execute_vf_cmd(dev, &args);
963 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
967 *pstats = (struct i40e_eth_stats *)args.out_buffer;
972 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
975 struct i40e_eth_stats *pstats = NULL;
977 ret = i40evf_update_stats(dev, &pstats);
981 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
982 pstats->rx_broadcast;
983 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
985 stats->ierrors = pstats->rx_discards;
986 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
987 stats->ibytes = pstats->rx_bytes;
988 stats->obytes = pstats->tx_bytes;
994 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
996 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
997 struct i40e_eth_stats *pstats = NULL;
999 /* read stat values to clear hardware registers */
1000 i40evf_update_stats(dev, &pstats);
1002 /* set stats offset base on current values */
1003 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
1006 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1007 struct rte_eth_xstats *xstats, unsigned n)
1011 struct i40e_eth_stats *pstats = NULL;
1013 if (n < I40EVF_NB_XSTATS)
1014 return I40EVF_NB_XSTATS;
1016 ret = i40evf_update_stats(dev, &pstats);
1023 /* loop over xstats array and values from pstats */
1024 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1025 snprintf(xstats[i].name, sizeof(xstats[i].name),
1026 "%s", rte_i40evf_stats_strings[i].name);
1027 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1028 rte_i40evf_stats_strings[i].offset);
1031 return I40EVF_NB_XSTATS;
1035 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1037 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1038 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1039 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1042 struct vf_cmd_info args;
1044 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1045 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1046 vlan_list->num_elements = 1;
1047 vlan_list->vlan_id[0] = vlanid;
1049 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1050 args.in_args = (u8 *)&cmd_buffer;
1051 args.in_args_size = sizeof(cmd_buffer);
1052 args.out_buffer = cmd_result_buffer;
1053 args.out_size = I40E_AQ_BUF_SZ;
1054 err = i40evf_execute_vf_cmd(dev, &args);
1056 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1062 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1064 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1065 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1066 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1069 struct vf_cmd_info args;
1071 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1072 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1073 vlan_list->num_elements = 1;
1074 vlan_list->vlan_id[0] = vlanid;
1076 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1077 args.in_args = (u8 *)&cmd_buffer;
1078 args.in_args_size = sizeof(cmd_buffer);
1079 args.out_buffer = cmd_result_buffer;
1080 args.out_size = I40E_AQ_BUF_SZ;
1081 err = i40evf_execute_vf_cmd(dev, &args);
1083 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1089 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1092 struct vf_cmd_info args;
1093 struct rte_eth_link *new_link;
1095 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1096 args.in_args = NULL;
1097 args.in_args_size = 0;
1098 args.out_buffer = cmd_result_buffer;
1099 args.out_size = I40E_AQ_BUF_SZ;
1100 err = i40evf_execute_vf_cmd(dev, &args);
1102 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1106 new_link = (struct rte_eth_link *)args.out_buffer;
1107 (void)rte_memcpy(link, new_link, sizeof(*link));
1112 static const struct rte_pci_id pci_id_i40evf_map[] = {
1113 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1114 #include "rte_pci_dev_ids.h"
1115 { .vendor_id = 0, /* sentinel */ },
1119 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1120 struct rte_eth_link *link)
1122 struct rte_eth_link *dst = &(dev->data->dev_link);
1123 struct rte_eth_link *src = link;
1125 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1126 *(uint64_t *)src) == 0)
1133 i40evf_reset_vf(struct i40e_hw *hw)
1137 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1138 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1142 * After issuing vf reset command to pf, pf won't necessarily
1143 * reset vf, it depends on what state it exactly is. If it's not
1144 * initialized yet, it won't have vf reset since it's in a certain
1145 * state. If not, it will try to reset. Even vf is reset, pf will
1146 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1147 * it to ACTIVE. In this duration, vf may not catch the moment that
1148 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1152 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1153 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1154 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1155 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1156 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1162 if (i >= MAX_RESET_WAIT_CNT) {
1163 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1171 i40evf_init_vf(struct rte_eth_dev *dev)
1174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1176 struct ether_addr *p_mac_addr;
1178 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1179 vf->dev_data = dev->data;
1180 err = i40e_set_mac_type(hw);
1182 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1186 i40e_init_adminq_parameter(hw);
1187 err = i40e_init_adminq(hw);
1189 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1194 /* Reset VF and wait until it's complete */
1195 if (i40evf_reset_vf(hw)) {
1196 PMD_INIT_LOG(ERR, "reset NIC failed");
1200 /* VF reset, shutdown admin queue and initialize again */
1201 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1202 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1206 i40e_init_adminq_parameter(hw);
1207 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1208 PMD_INIT_LOG(ERR, "init_adminq failed");
1211 if (i40evf_check_api_version(dev) != 0) {
1212 PMD_INIT_LOG(ERR, "check_api version failed");
1215 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1216 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1217 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1219 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1223 if (i40evf_get_vf_resource(dev) != 0) {
1224 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1228 /* got VF config message back from PF, now we can parse it */
1229 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1230 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1231 vf->vsi_res = &vf->vf_res->vsi_res[i];
1235 PMD_INIT_LOG(ERR, "no LAN VSI found");
1239 if (hw->mac.type == I40E_MAC_X722_VF)
1240 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1241 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1242 vf->vsi.type = vf->vsi_res->vsi_type;
1243 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1244 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1246 /* Store the MAC address configured by host, or generate random one */
1247 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1248 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1249 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1251 eth_random_addr(hw->mac.addr); /* Generate a random one */
1256 rte_free(vf->vf_res);
1258 i40e_shutdown_adminq(hw); /* ignore error */
1264 i40evf_uninit_vf(struct rte_eth_dev *dev)
1266 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269 PMD_INIT_FUNC_TRACE();
1271 if (hw->adapter_stopped == 0)
1272 i40evf_dev_close(dev);
1273 rte_free(vf->vf_res);
1280 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1283 eth_dev->data->dev_private);
1285 PMD_INIT_FUNC_TRACE();
1287 /* assign ops func pointer */
1288 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1289 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1290 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1293 * For secondary processes, we don't initialise any further as primary
1294 * has already done this work.
1296 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1297 i40e_set_rx_function(eth_dev);
1298 i40e_set_tx_function(eth_dev);
1302 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1304 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1305 hw->device_id = eth_dev->pci_dev->id.device_id;
1306 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1307 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1308 hw->bus.device = eth_dev->pci_dev->addr.devid;
1309 hw->bus.func = eth_dev->pci_dev->addr.function;
1310 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1311 hw->adapter_stopped = 0;
1313 if(i40evf_init_vf(eth_dev) != 0) {
1314 PMD_INIT_LOG(ERR, "Init vf failed");
1318 /* allocate memory for mac addr storage */
1319 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1320 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1322 if (eth_dev->data->mac_addrs == NULL) {
1323 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1324 " store MAC addresses",
1325 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1328 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1329 ð_dev->data->mac_addrs[0]);
1335 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1337 PMD_INIT_FUNC_TRACE();
1339 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1342 eth_dev->dev_ops = NULL;
1343 eth_dev->rx_pkt_burst = NULL;
1344 eth_dev->tx_pkt_burst = NULL;
1346 if (i40evf_uninit_vf(eth_dev) != 0) {
1347 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1351 rte_free(eth_dev->data->mac_addrs);
1352 eth_dev->data->mac_addrs = NULL;
1357 * virtual function driver struct
1359 static struct eth_driver rte_i40evf_pmd = {
1361 .name = "rte_i40evf_pmd",
1362 .id_table = pci_id_i40evf_map,
1363 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1365 .eth_dev_init = i40evf_dev_init,
1366 .eth_dev_uninit = i40evf_dev_uninit,
1367 .dev_private_size = sizeof(struct i40e_adapter),
1371 * VF Driver initialization routine.
1372 * Invoked one at EAL init time.
1373 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1376 rte_i40evf_pmd_init(const char *name __rte_unused,
1377 const char *params __rte_unused)
1379 PMD_INIT_FUNC_TRACE();
1381 rte_eth_driver_register(&rte_i40evf_pmd);
1386 static struct rte_driver rte_i40evf_driver = {
1388 .init = rte_i40evf_pmd_init,
1391 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1394 i40evf_dev_configure(struct rte_eth_dev *dev)
1396 struct i40e_adapter *ad =
1397 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1399 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1400 * allocation or vector Rx preconditions we will reset it.
1402 ad->rx_bulk_alloc_allowed = true;
1403 ad->rx_vec_allowed = true;
1404 ad->tx_simple_allowed = true;
1405 ad->tx_vec_allowed = true;
1407 return i40evf_init_vlan(dev);
1411 i40evf_init_vlan(struct rte_eth_dev *dev)
1413 struct rte_eth_dev_data *data = dev->data;
1416 /* Apply vlan offload setting */
1417 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1419 /* Apply pvid setting */
1420 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1421 data->dev_conf.txmode.hw_vlan_insert_pvid);
1426 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1428 bool enable_vlan_strip = 0;
1429 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1430 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1432 /* Linux pf host doesn't support vlan offload yet */
1433 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1434 /* Vlan stripping setting */
1435 if (mask & ETH_VLAN_STRIP_MASK) {
1436 /* Enable or disable VLAN stripping */
1437 if (dev_conf->rxmode.hw_vlan_strip)
1438 enable_vlan_strip = 1;
1440 enable_vlan_strip = 0;
1442 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1448 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1450 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1451 struct i40e_vsi_vlan_pvid_info info;
1452 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1454 memset(&info, 0, sizeof(info));
1457 /* Linux pf host don't support vlan offload yet */
1458 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1460 info.config.pvid = pvid;
1462 info.config.reject.tagged =
1463 dev_conf->txmode.hw_vlan_reject_tagged;
1464 info.config.reject.untagged =
1465 dev_conf->txmode.hw_vlan_reject_untagged;
1467 return i40evf_config_vlan_pvid(dev, &info);
1474 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1476 struct i40e_rx_queue *rxq;
1478 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480 PMD_INIT_FUNC_TRACE();
1482 if (rx_queue_id < dev->data->nb_rx_queues) {
1483 rxq = dev->data->rx_queues[rx_queue_id];
1485 err = i40e_alloc_rx_queue_mbufs(rxq);
1487 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1493 /* Init the RX tail register. */
1494 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1495 I40EVF_WRITE_FLUSH(hw);
1497 /* Ready to switch the queue on */
1498 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1501 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1504 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1511 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1513 struct i40e_rx_queue *rxq;
1516 if (rx_queue_id < dev->data->nb_rx_queues) {
1517 rxq = dev->data->rx_queues[rx_queue_id];
1519 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1522 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1527 i40e_rx_queue_release_mbufs(rxq);
1528 i40e_reset_rx_queue(rxq);
1529 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1536 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1540 PMD_INIT_FUNC_TRACE();
1542 if (tx_queue_id < dev->data->nb_tx_queues) {
1544 /* Ready to switch the queue on */
1545 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1548 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1551 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1558 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1560 struct i40e_tx_queue *txq;
1563 if (tx_queue_id < dev->data->nb_tx_queues) {
1564 txq = dev->data->tx_queues[tx_queue_id];
1566 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1569 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1574 i40e_tx_queue_release_mbufs(txq);
1575 i40e_reset_tx_queue(txq);
1576 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1583 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1588 ret = i40evf_add_vlan(dev, vlan_id);
1590 ret = i40evf_del_vlan(dev,vlan_id);
1596 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 struct rte_eth_dev_data *dev_data = dev->data;
1600 struct rte_pktmbuf_pool_private *mbp_priv;
1601 uint16_t buf_size, len;
1603 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1604 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1605 I40EVF_WRITE_FLUSH(hw);
1607 /* Calculate the maximum packet length allowed */
1608 mbp_priv = rte_mempool_get_priv(rxq->mp);
1609 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1610 RTE_PKTMBUF_HEADROOM);
1611 rxq->hs_mode = i40e_header_split_none;
1612 rxq->rx_hdr_len = 0;
1613 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1614 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1615 rxq->max_pkt_len = RTE_MIN(len,
1616 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1619 * Check if the jumbo frame and maximum packet length are set correctly
1621 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1622 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1623 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1624 PMD_DRV_LOG(ERR, "maximum packet length must be "
1625 "larger than %u and smaller than %u, as jumbo "
1626 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1627 (uint32_t)I40E_FRAME_SIZE_MAX);
1628 return I40E_ERR_CONFIG;
1631 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1632 rxq->max_pkt_len > ETHER_MAX_LEN) {
1633 PMD_DRV_LOG(ERR, "maximum packet length must be "
1634 "larger than %u and smaller than %u, as jumbo "
1635 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1636 (uint32_t)ETHER_MAX_LEN);
1637 return I40E_ERR_CONFIG;
1641 if (dev_data->dev_conf.rxmode.enable_scatter ||
1642 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1643 dev_data->scattered_rx = 1;
1650 i40evf_rx_init(struct rte_eth_dev *dev)
1652 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1654 int ret = I40E_SUCCESS;
1655 struct i40e_rx_queue **rxq =
1656 (struct i40e_rx_queue **)dev->data->rx_queues;
1658 i40evf_config_rss(vf);
1659 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1660 if (!rxq[i] || !rxq[i]->q_set)
1662 ret = i40evf_rxq_init(dev, rxq[i]);
1663 if (ret != I40E_SUCCESS)
1666 if (ret == I40E_SUCCESS)
1667 i40e_set_rx_function(dev);
1673 i40evf_tx_init(struct rte_eth_dev *dev)
1676 struct i40e_tx_queue **txq =
1677 (struct i40e_tx_queue **)dev->data->tx_queues;
1678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 for (i = 0; i < dev->data->nb_tx_queues; i++)
1681 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1683 i40e_set_tx_function(dev);
1687 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1689 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1690 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1693 if (!rte_intr_allow_others(intr_handle)) {
1695 I40E_VFINT_DYN_CTL01,
1696 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1697 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
1698 I40EVF_WRITE_FLUSH(hw);
1702 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1703 /* To support DPDK PF host */
1705 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1706 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1707 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1709 /* To support Linux PF host */
1710 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1711 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1712 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK);
1714 I40EVF_WRITE_FLUSH(hw);
1718 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1720 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1724 if (!rte_intr_allow_others(intr_handle)) {
1725 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1726 I40EVF_WRITE_FLUSH(hw);
1730 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1732 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1736 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1738 I40EVF_WRITE_FLUSH(hw);
1742 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1744 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1750 msix_intr = intr_handle->intr_vec[queue_id];
1751 if (msix_intr == I40E_MISC_VEC_ID)
1752 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1753 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1754 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1755 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1757 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1760 I40E_VFINT_DYN_CTLN1(msix_intr -
1762 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1763 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1764 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1766 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1768 I40EVF_WRITE_FLUSH(hw);
1770 rte_intr_enable(&dev->pci_dev->intr_handle);
1776 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1778 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1779 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782 msix_intr = intr_handle->intr_vec[queue_id];
1783 if (msix_intr == I40E_MISC_VEC_ID)
1784 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1787 I40E_VFINT_DYN_CTLN1(msix_intr -
1791 I40EVF_WRITE_FLUSH(hw);
1797 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1799 struct i40e_virtchnl_ether_addr_list *list;
1800 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1805 struct ether_addr *addr;
1806 struct vf_cmd_info args;
1810 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1811 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1812 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1814 len += sizeof(struct i40e_virtchnl_ether_addr);
1815 if (len >= I40E_AQ_BUF_SZ) {
1821 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1823 for (i = begin; i < next_begin; i++) {
1824 addr = &dev->data->mac_addrs[i];
1825 if (is_zero_ether_addr(addr))
1827 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
1828 sizeof(addr->addr_bytes));
1829 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1830 addr->addr_bytes[0], addr->addr_bytes[1],
1831 addr->addr_bytes[2], addr->addr_bytes[3],
1832 addr->addr_bytes[4], addr->addr_bytes[5]);
1835 list->vsi_id = vf->vsi_res->vsi_id;
1836 list->num_elements = j;
1837 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
1838 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
1839 args.in_args = (uint8_t *)list;
1840 args.in_args_size = len;
1841 args.out_buffer = cmd_result_buffer;
1842 args.out_size = I40E_AQ_BUF_SZ;
1843 err = i40evf_execute_vf_cmd(dev, &args);
1845 PMD_DRV_LOG(ERR, "fail to execute command %s",
1846 add ? "OP_ADD_ETHER_ADDRESS" :
1847 "OP_DEL_ETHER_ADDRESS");
1850 } while (begin < I40E_NUM_MACADDR_MAX);
1854 i40evf_dev_start(struct rte_eth_dev *dev)
1856 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1859 uint32_t intr_vector = 0;
1861 PMD_INIT_FUNC_TRACE();
1863 hw->adapter_stopped = 0;
1865 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1866 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1867 dev->data->nb_tx_queues);
1869 /* check and configure queue intr-vector mapping */
1870 if (dev->data->dev_conf.intr_conf.rxq != 0) {
1871 intr_vector = dev->data->nb_rx_queues;
1872 if (rte_intr_efd_enable(intr_handle, intr_vector))
1876 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1877 intr_handle->intr_vec =
1878 rte_zmalloc("intr_vec",
1879 dev->data->nb_rx_queues * sizeof(int), 0);
1880 if (!intr_handle->intr_vec) {
1881 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1882 " intr_vec\n", dev->data->nb_rx_queues);
1887 if (i40evf_rx_init(dev) != 0){
1888 PMD_DRV_LOG(ERR, "failed to do RX init");
1892 i40evf_tx_init(dev);
1894 if (i40evf_configure_queues(dev) != 0) {
1895 PMD_DRV_LOG(ERR, "configure queues failed");
1898 if (i40evf_config_irq_map(dev)) {
1899 PMD_DRV_LOG(ERR, "config_irq_map failed");
1903 /* Set all mac addrs */
1904 i40evf_add_del_all_mac_addr(dev, TRUE);
1906 if (i40evf_start_queues(dev) != 0) {
1907 PMD_DRV_LOG(ERR, "enable queues failed");
1911 /* vf don't allow intr except for rxq intr */
1912 if (dev->data->dev_conf.intr_conf.rxq != 0)
1913 rte_intr_enable(intr_handle);
1915 i40evf_enable_queues_intr(dev);
1919 i40evf_add_del_all_mac_addr(dev, FALSE);
1925 i40evf_dev_stop(struct rte_eth_dev *dev)
1927 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1929 PMD_INIT_FUNC_TRACE();
1931 i40evf_stop_queues(dev);
1932 i40evf_disable_queues_intr(dev);
1933 i40e_dev_clear_queues(dev);
1935 /* Clean datapath event and queue/vec mapping */
1936 rte_intr_efd_disable(intr_handle);
1937 if (intr_handle->intr_vec) {
1938 rte_free(intr_handle->intr_vec);
1939 intr_handle->intr_vec = NULL;
1941 /* remove all mac addrs */
1942 i40evf_add_del_all_mac_addr(dev, FALSE);
1947 i40evf_dev_link_update(struct rte_eth_dev *dev,
1948 __rte_unused int wait_to_complete)
1950 struct rte_eth_link new_link;
1951 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1953 * DPDK pf host provide interfacet to acquire link status
1954 * while Linux driver does not
1956 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1957 i40evf_get_link_status(dev, &new_link);
1959 /* Always assume it's up, for Linux driver PF host */
1960 new_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;
1961 new_link.link_speed = ETH_LINK_SPEED_10000;
1962 new_link.link_status = 1;
1964 i40evf_dev_atomic_write_link_status(dev, &new_link);
1970 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
1972 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1975 /* If enabled, just return */
1976 if (vf->promisc_unicast_enabled)
1979 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
1981 vf->promisc_unicast_enabled = TRUE;
1985 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
1987 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1990 /* If disabled, just return */
1991 if (!vf->promisc_unicast_enabled)
1994 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
1996 vf->promisc_unicast_enabled = FALSE;
2000 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2002 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2005 /* If enabled, just return */
2006 if (vf->promisc_multicast_enabled)
2009 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2011 vf->promisc_multicast_enabled = TRUE;
2015 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2017 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2020 /* If enabled, just return */
2021 if (!vf->promisc_multicast_enabled)
2024 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2026 vf->promisc_multicast_enabled = FALSE;
2030 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2032 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2034 memset(dev_info, 0, sizeof(*dev_info));
2035 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2036 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2037 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2038 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2039 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2040 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2041 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2042 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2043 dev_info->rx_offload_capa =
2044 DEV_RX_OFFLOAD_VLAN_STRIP |
2045 DEV_RX_OFFLOAD_QINQ_STRIP |
2046 DEV_RX_OFFLOAD_IPV4_CKSUM |
2047 DEV_RX_OFFLOAD_UDP_CKSUM |
2048 DEV_RX_OFFLOAD_TCP_CKSUM;
2049 dev_info->tx_offload_capa =
2050 DEV_TX_OFFLOAD_VLAN_INSERT |
2051 DEV_TX_OFFLOAD_QINQ_INSERT |
2052 DEV_TX_OFFLOAD_IPV4_CKSUM |
2053 DEV_TX_OFFLOAD_UDP_CKSUM |
2054 DEV_TX_OFFLOAD_TCP_CKSUM |
2055 DEV_TX_OFFLOAD_SCTP_CKSUM;
2057 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2059 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2060 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2061 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2063 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2067 dev_info->default_txconf = (struct rte_eth_txconf) {
2069 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2070 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2071 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2073 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2074 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2075 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2076 ETH_TXQ_FLAGS_NOOFFLOADS,
2079 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2080 .nb_max = I40E_MAX_RING_DESC,
2081 .nb_min = I40E_MIN_RING_DESC,
2082 .nb_align = I40E_ALIGN_RING_DESC,
2085 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2086 .nb_max = I40E_MAX_RING_DESC,
2087 .nb_min = I40E_MIN_RING_DESC,
2088 .nb_align = I40E_ALIGN_RING_DESC,
2093 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2095 if (i40evf_get_statics(dev, stats))
2096 PMD_DRV_LOG(ERR, "Get statics failed");
2100 i40evf_dev_close(struct rte_eth_dev *dev)
2102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104 i40evf_dev_stop(dev);
2105 hw->adapter_stopped = 1;
2106 i40e_dev_free_queues(dev);
2107 i40evf_reset_vf(hw);
2108 i40e_shutdown_adminq(hw);
2112 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2114 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2115 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2121 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2122 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2125 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2129 uint32_t *lut_dw = (uint32_t *)lut;
2130 uint16_t i, lut_size_dw = lut_size / 4;
2132 for (i = 0; i < lut_size_dw; i++)
2133 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2140 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2142 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2143 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2149 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2150 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2153 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2157 uint32_t *lut_dw = (uint32_t *)lut;
2158 uint16_t i, lut_size_dw = lut_size / 4;
2160 for (i = 0; i < lut_size_dw; i++)
2161 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2162 I40EVF_WRITE_FLUSH(hw);
2169 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2170 struct rte_eth_rss_reta_entry64 *reta_conf,
2173 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2175 uint16_t i, idx, shift;
2178 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2179 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2180 "(%d) doesn't match the number of hardware can "
2181 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2185 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2187 PMD_DRV_LOG(ERR, "No memory can be allocated");
2190 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2193 for (i = 0; i < reta_size; i++) {
2194 idx = i / RTE_RETA_GROUP_SIZE;
2195 shift = i % RTE_RETA_GROUP_SIZE;
2196 if (reta_conf[idx].mask & (1ULL << shift))
2197 lut[i] = reta_conf[idx].reta[shift];
2199 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2208 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2209 struct rte_eth_rss_reta_entry64 *reta_conf,
2212 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2213 uint16_t i, idx, shift;
2217 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2218 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2219 "(%d) doesn't match the number of hardware can "
2220 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2224 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2226 PMD_DRV_LOG(ERR, "No memory can be allocated");
2230 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2233 for (i = 0; i < reta_size; i++) {
2234 idx = i / RTE_RETA_GROUP_SIZE;
2235 shift = i % RTE_RETA_GROUP_SIZE;
2236 if (reta_conf[idx].mask & (1ULL << shift))
2237 reta_conf[idx].reta[shift] = lut[i];
2247 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2249 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2250 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2253 if (!key || key_len == 0) {
2254 PMD_DRV_LOG(DEBUG, "No key to be configured");
2256 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2258 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2262 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2263 struct i40e_aqc_get_set_rss_key_data *key_dw =
2264 (struct i40e_aqc_get_set_rss_key_data *)key;
2266 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2268 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2271 uint32_t *hash_key = (uint32_t *)key;
2274 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2275 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2276 I40EVF_WRITE_FLUSH(hw);
2283 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2285 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2286 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2289 if (!key || !key_len)
2292 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2293 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2294 (struct i40e_aqc_get_set_rss_key_data *)key);
2296 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2300 uint32_t *key_dw = (uint32_t *)key;
2303 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2304 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2306 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2312 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2314 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2315 uint64_t rss_hf, hena;
2318 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2319 rss_conf->rss_key_len);
2323 rss_hf = rss_conf->rss_hf;
2324 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2325 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2326 hena &= ~I40E_RSS_HENA_ALL;
2327 hena |= i40e_config_hena(rss_hf);
2328 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2329 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2330 I40EVF_WRITE_FLUSH(hw);
2336 i40evf_disable_rss(struct i40e_vf *vf)
2338 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2341 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2342 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2343 hena &= ~I40E_RSS_HENA_ALL;
2344 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2345 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2346 I40EVF_WRITE_FLUSH(hw);
2350 i40evf_config_rss(struct i40e_vf *vf)
2352 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2353 struct rte_eth_rss_conf rss_conf;
2354 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2357 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2358 i40evf_disable_rss(vf);
2359 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2363 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2364 /* Fill out the look up table */
2365 for (i = 0, j = 0; i < nb_q; i++, j++) {
2368 lut = (lut << 8) | j;
2370 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2373 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2374 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2375 i40evf_disable_rss(vf);
2376 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2380 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2381 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2382 /* Calculate the default hash key */
2383 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2384 rss_key_default[i] = (uint32_t)rte_rand();
2385 rss_conf.rss_key = (uint8_t *)rss_key_default;
2386 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2390 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2394 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2395 struct rte_eth_rss_conf *rss_conf)
2397 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2398 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2402 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2403 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2404 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2405 if (rss_hf != 0) /* Enable RSS */
2411 if (rss_hf == 0) /* Disable RSS */
2414 return i40evf_hw_rss_hash_set(vf, rss_conf);
2418 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2419 struct rte_eth_rss_conf *rss_conf)
2421 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2422 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2426 &rss_conf->rss_key_len);
2428 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2429 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2430 rss_conf->rss_hf = i40e_parse_hena(hena);