1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static int i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static int i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int i40evf_init_vlan(struct rte_eth_dev *dev);
101 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
102 uint16_t rx_queue_id);
103 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
104 uint16_t rx_queue_id);
105 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
106 uint16_t tx_queue_id);
107 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
108 uint16_t tx_queue_id);
109 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
110 struct rte_ether_addr *addr,
113 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
114 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
115 struct rte_eth_rss_reta_entry64 *reta_conf,
117 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
118 struct rte_eth_rss_reta_entry64 *reta_conf,
120 static int i40evf_config_rss(struct i40e_vf *vf);
121 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
122 struct rte_eth_rss_conf *rss_conf);
123 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
124 struct rte_eth_rss_conf *rss_conf);
125 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr);
129 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
131 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
132 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
137 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
138 struct rte_ether_addr *mc_addr_set,
139 uint32_t nb_mc_addr, bool add);
141 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
142 struct rte_ether_addr *mc_addr_set,
143 uint32_t nb_mc_addr);
145 i40evf_dev_alarm_handler(void *param);
147 /* Default hash key buffer for RSS */
148 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
150 struct rte_i40evf_xstats_name_off {
151 char name[RTE_ETH_XSTATS_NAME_SIZE];
155 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
156 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
157 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
158 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
159 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
160 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
161 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
162 rx_unknown_protocol)},
163 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
164 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
165 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
166 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
167 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
168 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
171 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
172 sizeof(rte_i40evf_stats_strings[0]))
174 static const struct eth_dev_ops i40evf_eth_dev_ops = {
175 .dev_configure = i40evf_dev_configure,
176 .dev_start = i40evf_dev_start,
177 .dev_stop = i40evf_dev_stop,
178 .promiscuous_enable = i40evf_dev_promiscuous_enable,
179 .promiscuous_disable = i40evf_dev_promiscuous_disable,
180 .allmulticast_enable = i40evf_dev_allmulticast_enable,
181 .allmulticast_disable = i40evf_dev_allmulticast_disable,
182 .link_update = i40evf_dev_link_update,
183 .stats_get = i40evf_dev_stats_get,
184 .stats_reset = i40evf_dev_xstats_reset,
185 .xstats_get = i40evf_dev_xstats_get,
186 .xstats_get_names = i40evf_dev_xstats_get_names,
187 .xstats_reset = i40evf_dev_xstats_reset,
188 .dev_close = i40evf_dev_close,
189 .dev_reset = i40evf_dev_reset,
190 .dev_infos_get = i40evf_dev_info_get,
191 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
192 .vlan_filter_set = i40evf_vlan_filter_set,
193 .vlan_offload_set = i40evf_vlan_offload_set,
194 .rx_queue_start = i40evf_dev_rx_queue_start,
195 .rx_queue_stop = i40evf_dev_rx_queue_stop,
196 .tx_queue_start = i40evf_dev_tx_queue_start,
197 .tx_queue_stop = i40evf_dev_tx_queue_stop,
198 .rx_queue_setup = i40e_dev_rx_queue_setup,
199 .rx_queue_release = i40e_dev_rx_queue_release,
200 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
201 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
202 .tx_queue_setup = i40e_dev_tx_queue_setup,
203 .tx_queue_release = i40e_dev_tx_queue_release,
204 .rxq_info_get = i40e_rxq_info_get,
205 .txq_info_get = i40e_txq_info_get,
206 .mac_addr_add = i40evf_add_mac_addr,
207 .mac_addr_remove = i40evf_del_mac_addr,
208 .set_mc_addr_list = i40evf_set_mc_addr_list,
209 .reta_update = i40evf_dev_rss_reta_update,
210 .reta_query = i40evf_dev_rss_reta_query,
211 .rss_hash_update = i40evf_dev_rss_hash_update,
212 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
213 .mtu_set = i40evf_dev_mtu_set,
214 .mac_addr_set = i40evf_set_default_mac_addr,
215 .tx_done_cleanup = i40e_tx_done_cleanup,
219 * Read data in admin queue to get msg from pf driver
221 static enum i40evf_aq_result
222 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
224 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
225 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
226 struct i40e_arq_event_info event;
227 enum virtchnl_ops opcode;
228 enum i40e_status_code retval;
230 enum i40evf_aq_result result = I40EVF_MSG_NON;
232 event.buf_len = data->buf_len;
233 event.msg_buf = data->msg;
234 ret = i40e_clean_arq_element(hw, &event, NULL);
235 /* Can't read any msg from adminQ */
237 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
238 result = I40EVF_MSG_ERR;
242 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
243 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
245 if (opcode == VIRTCHNL_OP_EVENT) {
246 struct virtchnl_pf_event *vpe =
247 (struct virtchnl_pf_event *)event.msg_buf;
249 result = I40EVF_MSG_SYS;
250 switch (vpe->event) {
251 case VIRTCHNL_EVENT_LINK_CHANGE:
253 vpe->event_data.link_event.link_status;
255 vpe->event_data.link_event.link_speed;
256 vf->pend_msg |= PFMSG_LINK_CHANGE;
257 PMD_DRV_LOG(INFO, "Link status update:%s",
258 vf->link_up ? "up" : "down");
260 case VIRTCHNL_EVENT_RESET_IMPENDING:
262 vf->pend_msg |= PFMSG_RESET_IMPENDING;
263 PMD_DRV_LOG(INFO, "vf is reseting");
265 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
266 vf->dev_closed = true;
267 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
268 PMD_DRV_LOG(INFO, "PF driver closed");
271 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
272 __func__, vpe->event);
275 /* async reply msg on command issued by vf previously */
276 result = I40EVF_MSG_CMD;
277 /* Actual data length read from PF */
278 data->msg_len = event.msg_len;
281 data->result = retval;
288 * clear current command. Only call in case execute
289 * _atomic_set_cmd successfully.
292 _clear_cmd(struct i40e_vf *vf)
295 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
299 * Check there is pending cmd in execution. If none, set new command.
302 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
304 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
305 VIRTCHNL_OP_UNKNOWN, ops);
308 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
313 #define MAX_TRY_TIMES 200
314 #define ASQ_DELAY_MS 10
317 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
320 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
321 struct i40evf_arq_msg_info info;
322 enum i40evf_aq_result ret;
325 if (_atomic_set_cmd(vf, args->ops))
328 info.msg = args->out_buffer;
329 info.buf_len = args->out_size;
330 info.ops = VIRTCHNL_OP_UNKNOWN;
331 info.result = I40E_SUCCESS;
333 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
334 args->in_args, args->in_args_size, NULL);
336 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
342 case VIRTCHNL_OP_RESET_VF:
343 /*no need to process in this function */
346 case VIRTCHNL_OP_VERSION:
347 case VIRTCHNL_OP_GET_VF_RESOURCES:
348 /* for init adminq commands, need to poll the response */
351 ret = i40evf_read_pfmsg(dev, &info);
352 vf->cmd_retval = info.result;
353 if (ret == I40EVF_MSG_CMD) {
356 } else if (ret == I40EVF_MSG_ERR)
358 rte_delay_ms(ASQ_DELAY_MS);
359 /* If don't read msg or read sys event, continue */
360 } while (i++ < MAX_TRY_TIMES);
363 case VIRTCHNL_OP_REQUEST_QUEUES:
365 * ignore async reply, only wait for system message,
366 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
367 * if not, means request queues failed.
371 ret = i40evf_read_pfmsg(dev, &info);
372 vf->cmd_retval = info.result;
373 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
376 } else if (ret == I40EVF_MSG_ERR ||
377 ret == I40EVF_MSG_CMD) {
380 rte_delay_ms(ASQ_DELAY_MS);
381 /* If don't read msg or read sys event, continue */
382 } while (i++ < MAX_TRY_TIMES);
387 /* for other adminq in running time, waiting the cmd done flag */
390 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
394 rte_delay_ms(ASQ_DELAY_MS);
395 /* If don't read msg or read sys event, continue */
396 } while (i++ < MAX_TRY_TIMES);
397 /* If there's no response is received, clear command */
398 if (i >= MAX_TRY_TIMES) {
399 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
405 return err | vf->cmd_retval;
409 * Check API version with sync wait until version read or fail from admin queue
412 i40evf_check_api_version(struct rte_eth_dev *dev)
414 struct virtchnl_version_info version, *pver;
416 struct vf_cmd_info args;
417 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
419 version.major = VIRTCHNL_VERSION_MAJOR;
420 version.minor = VIRTCHNL_VERSION_MINOR;
422 args.ops = VIRTCHNL_OP_VERSION;
423 args.in_args = (uint8_t *)&version;
424 args.in_args_size = sizeof(version);
425 args.out_buffer = vf->aq_resp;
426 args.out_size = I40E_AQ_BUF_SZ;
428 err = i40evf_execute_vf_cmd(dev, &args);
430 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
434 pver = (struct virtchnl_version_info *)args.out_buffer;
435 vf->version_major = pver->major;
436 vf->version_minor = pver->minor;
437 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
438 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
439 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
441 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
442 vf->version_major, vf->version_minor,
443 VIRTCHNL_VERSION_MAJOR,
444 VIRTCHNL_VERSION_MINOR);
452 i40evf_get_vf_resource(struct rte_eth_dev *dev)
454 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
455 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
457 struct vf_cmd_info args;
460 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
461 args.out_buffer = vf->aq_resp;
462 args.out_size = I40E_AQ_BUF_SZ;
464 caps = VIRTCHNL_VF_OFFLOAD_L2 |
465 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
466 VIRTCHNL_VF_OFFLOAD_RSS_REG |
467 VIRTCHNL_VF_OFFLOAD_VLAN |
468 VIRTCHNL_VF_OFFLOAD_RX_POLLING |
469 VIRTCHNL_VF_CAP_ADV_LINK_SPEED;
470 args.in_args = (uint8_t *)∩︀
471 args.in_args_size = sizeof(caps);
474 args.in_args_size = 0;
476 err = i40evf_execute_vf_cmd(dev, &args);
479 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
483 len = sizeof(struct virtchnl_vf_resource) +
484 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
486 rte_memcpy(vf->vf_res, args.out_buffer,
487 RTE_MIN(args.out_size, len));
488 i40e_vf_parse_hw_config(hw, vf->vf_res);
494 i40evf_config_promisc(struct rte_eth_dev *dev,
496 bool enable_multicast)
498 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
500 struct vf_cmd_info args;
501 struct virtchnl_promisc_info promisc;
504 promisc.vsi_id = vf->vsi_res->vsi_id;
507 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
509 if (enable_multicast)
510 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
512 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
513 args.in_args = (uint8_t *)&promisc;
514 args.in_args_size = sizeof(promisc);
515 args.out_buffer = vf->aq_resp;
516 args.out_size = I40E_AQ_BUF_SZ;
518 err = i40evf_execute_vf_cmd(dev, &args);
521 PMD_DRV_LOG(ERR, "fail to execute command "
522 "CONFIG_PROMISCUOUS_MODE");
524 if (err == I40E_NOT_SUPPORTED)
530 vf->promisc_unicast_enabled = enable_unicast;
531 vf->promisc_multicast_enabled = enable_multicast;
536 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
538 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
539 struct vf_cmd_info args;
542 memset(&args, 0, sizeof(args));
543 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
545 args.in_args_size = 0;
546 args.out_buffer = vf->aq_resp;
547 args.out_size = I40E_AQ_BUF_SZ;
548 ret = i40evf_execute_vf_cmd(dev, &args);
550 PMD_DRV_LOG(ERR, "Failed to execute command of "
551 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
557 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
559 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
560 struct vf_cmd_info args;
563 memset(&args, 0, sizeof(args));
564 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
566 args.in_args_size = 0;
567 args.out_buffer = vf->aq_resp;
568 args.out_size = I40E_AQ_BUF_SZ;
569 ret = i40evf_execute_vf_cmd(dev, &args);
571 PMD_DRV_LOG(ERR, "Failed to execute command of "
572 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
578 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
582 struct i40e_tx_queue *txq)
584 txq_info->vsi_id = vsi_id;
585 txq_info->queue_id = queue_id;
586 if (queue_id < nb_txq && txq) {
587 txq_info->ring_len = txq->nb_tx_desc;
588 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
593 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
597 uint32_t max_pkt_size,
598 struct i40e_rx_queue *rxq)
600 rxq_info->vsi_id = vsi_id;
601 rxq_info->queue_id = queue_id;
602 rxq_info->max_pkt_size = max_pkt_size;
603 if (queue_id < nb_rxq && rxq) {
604 rxq_info->ring_len = rxq->nb_rx_desc;
605 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
606 rxq_info->databuffer_size =
607 (rte_pktmbuf_data_room_size(rxq->mp) -
608 RTE_PKTMBUF_HEADROOM);
613 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
615 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
616 struct i40e_rx_queue **rxq =
617 (struct i40e_rx_queue **)dev->data->rx_queues;
618 struct i40e_tx_queue **txq =
619 (struct i40e_tx_queue **)dev->data->tx_queues;
620 struct virtchnl_vsi_queue_config_info *vc_vqci;
621 struct virtchnl_queue_pair_info *vc_qpi;
622 struct vf_cmd_info args;
623 uint16_t i, nb_qp = vf->num_queue_pairs;
624 const uint32_t size =
625 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
629 memset(buff, 0, sizeof(buff));
630 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
631 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
632 vc_vqci->num_queue_pairs = nb_qp;
634 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
635 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
636 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
637 txq ? txq[i] : NULL);
638 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
639 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
640 vf->max_pkt_len, rxq ? rxq[i] : NULL);
642 memset(&args, 0, sizeof(args));
643 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
644 args.in_args = (uint8_t *)vc_vqci;
645 args.in_args_size = size;
646 args.out_buffer = vf->aq_resp;
647 args.out_size = I40E_AQ_BUF_SZ;
648 ret = i40evf_execute_vf_cmd(dev, &args);
650 PMD_DRV_LOG(ERR, "Failed to execute command of "
651 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
657 i40evf_config_irq_map(struct rte_eth_dev *dev)
659 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
660 struct vf_cmd_info args;
661 uint8_t *cmd_buffer = NULL;
662 struct virtchnl_irq_map_info *map_info;
663 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
664 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
665 uint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;
666 uint16_t rxq_map[vf->vf_res->max_vectors];
669 memset(rxq_map, 0, sizeof(rxq_map));
670 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
671 rte_intr_allow_others(intr_handle)) {
672 msix_base = I40E_RX_VEC_START;
673 /* For interrupt mode, available vector id is from 1. */
674 max_vectors = vf->vf_res->max_vectors - 1;
675 nb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);
678 for (i = 0; i < dev->data->nb_rx_queues; i++) {
679 rxq_map[vec] |= 1 << i;
680 intr_handle->intr_vec[i] = vec++;
681 if (vec >= vf->vf_res->max_vectors)
685 msix_base = I40E_MISC_VEC_ID;
688 for (i = 0; i < dev->data->nb_rx_queues; i++) {
689 rxq_map[msix_base] |= 1 << i;
690 if (rte_intr_dp_is_en(intr_handle))
691 intr_handle->intr_vec[i] = msix_base;
695 cmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +
696 sizeof(struct virtchnl_vector_map) * nb_msix;
697 cmd_buffer = rte_zmalloc("i40e", cmd_buffer_size, 0);
699 PMD_DRV_LOG(ERR, "Failed to allocate memory");
700 return I40E_ERR_NO_MEMORY;
703 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
704 map_info->num_vectors = nb_msix;
705 for (i = 0; i < nb_msix; i++) {
706 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
707 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
708 map_info->vecmap[i].vector_id = msix_base + i;
709 map_info->vecmap[i].txq_map = 0;
710 map_info->vecmap[i].rxq_map = rxq_map[msix_base + i];
713 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
714 args.in_args = (u8 *)cmd_buffer;
715 args.in_args_size = cmd_buffer_size;
716 args.out_buffer = vf->aq_resp;
717 args.out_size = I40E_AQ_BUF_SZ;
718 err = i40evf_execute_vf_cmd(dev, &args);
720 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
722 rte_free(cmd_buffer);
728 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
731 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
732 struct virtchnl_queue_select queue_select;
734 struct vf_cmd_info args;
735 memset(&queue_select, 0, sizeof(queue_select));
736 queue_select.vsi_id = vf->vsi_res->vsi_id;
739 queue_select.rx_queues |= 1 << qid;
741 queue_select.tx_queues |= 1 << qid;
744 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
746 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
747 args.in_args = (u8 *)&queue_select;
748 args.in_args_size = sizeof(queue_select);
749 args.out_buffer = vf->aq_resp;
750 args.out_size = I40E_AQ_BUF_SZ;
751 err = i40evf_execute_vf_cmd(dev, &args);
753 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
754 isrx ? "RX" : "TX", qid, on ? "on" : "off");
760 i40evf_start_queues(struct rte_eth_dev *dev)
762 struct rte_eth_dev_data *dev_data = dev->data;
764 struct i40e_rx_queue *rxq;
765 struct i40e_tx_queue *txq;
767 for (i = 0; i < dev->data->nb_rx_queues; i++) {
768 rxq = dev_data->rx_queues[i];
769 if (rxq->rx_deferred_start)
771 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
772 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
777 for (i = 0; i < dev->data->nb_tx_queues; i++) {
778 txq = dev_data->tx_queues[i];
779 if (txq->tx_deferred_start)
781 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
782 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
791 i40evf_stop_queues(struct rte_eth_dev *dev)
795 /* Stop TX queues first */
796 for (i = 0; i < dev->data->nb_tx_queues; i++) {
797 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
798 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
802 /* Then stop RX queues */
803 for (i = 0; i < dev->data->nb_rx_queues; i++) {
804 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
805 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
813 i40evf_add_mac_addr(struct rte_eth_dev *dev,
814 struct rte_ether_addr *addr,
815 __rte_unused uint32_t index,
816 __rte_unused uint32_t pool)
818 struct virtchnl_ether_addr_list *list;
819 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
820 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
821 sizeof(struct virtchnl_ether_addr)];
823 struct vf_cmd_info args;
825 if (rte_is_zero_ether_addr(addr)) {
826 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
827 addr->addr_bytes[0], addr->addr_bytes[1],
828 addr->addr_bytes[2], addr->addr_bytes[3],
829 addr->addr_bytes[4], addr->addr_bytes[5]);
830 return I40E_ERR_INVALID_MAC_ADDR;
833 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
834 list->vsi_id = vf->vsi_res->vsi_id;
835 list->num_elements = 1;
836 rte_memcpy(list->list[0].addr, addr->addr_bytes,
837 sizeof(addr->addr_bytes));
839 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
840 args.in_args = cmd_buffer;
841 args.in_args_size = sizeof(cmd_buffer);
842 args.out_buffer = vf->aq_resp;
843 args.out_size = I40E_AQ_BUF_SZ;
844 err = i40evf_execute_vf_cmd(dev, &args);
846 PMD_DRV_LOG(ERR, "fail to execute command "
847 "OP_ADD_ETHER_ADDRESS");
855 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
856 struct rte_ether_addr *addr)
858 struct virtchnl_ether_addr_list *list;
859 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
860 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
861 sizeof(struct virtchnl_ether_addr)];
863 struct vf_cmd_info args;
865 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
866 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
867 addr->addr_bytes[0], addr->addr_bytes[1],
868 addr->addr_bytes[2], addr->addr_bytes[3],
869 addr->addr_bytes[4], addr->addr_bytes[5]);
873 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
874 list->vsi_id = vf->vsi_res->vsi_id;
875 list->num_elements = 1;
876 rte_memcpy(list->list[0].addr, addr->addr_bytes,
877 sizeof(addr->addr_bytes));
879 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
880 args.in_args = cmd_buffer;
881 args.in_args_size = sizeof(cmd_buffer);
882 args.out_buffer = vf->aq_resp;
883 args.out_size = I40E_AQ_BUF_SZ;
884 err = i40evf_execute_vf_cmd(dev, &args);
886 PMD_DRV_LOG(ERR, "fail to execute command "
887 "OP_DEL_ETHER_ADDRESS");
894 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
896 struct rte_eth_dev_data *data = dev->data;
897 struct rte_ether_addr *addr;
899 addr = &data->mac_addrs[index];
901 i40evf_del_mac_addr_by_addr(dev, addr);
905 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
907 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
908 struct virtchnl_queue_select q_stats;
910 struct vf_cmd_info args;
912 memset(&q_stats, 0, sizeof(q_stats));
913 q_stats.vsi_id = vf->vsi_res->vsi_id;
914 args.ops = VIRTCHNL_OP_GET_STATS;
915 args.in_args = (u8 *)&q_stats;
916 args.in_args_size = sizeof(q_stats);
917 args.out_buffer = vf->aq_resp;
918 args.out_size = I40E_AQ_BUF_SZ;
920 err = i40evf_execute_vf_cmd(dev, &args);
922 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
926 *pstats = (struct i40e_eth_stats *)args.out_buffer;
931 i40evf_stat_update_48(uint64_t *offset,
934 if (*stat >= *offset)
935 *stat = *stat - *offset;
937 *stat = (uint64_t)((*stat +
938 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
940 *stat &= I40E_48_BIT_MASK;
944 i40evf_stat_update_32(uint64_t *offset,
947 if (*stat >= *offset)
948 *stat = (uint64_t)(*stat - *offset);
950 *stat = (uint64_t)((*stat +
951 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
955 i40evf_update_stats(struct i40e_vsi *vsi,
956 struct i40e_eth_stats *nes)
958 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
960 i40evf_stat_update_48(&oes->rx_bytes,
962 i40evf_stat_update_48(&oes->rx_unicast,
964 i40evf_stat_update_48(&oes->rx_multicast,
966 i40evf_stat_update_48(&oes->rx_broadcast,
968 i40evf_stat_update_32(&oes->rx_discards,
970 i40evf_stat_update_32(&oes->rx_unknown_protocol,
971 &nes->rx_unknown_protocol);
972 i40evf_stat_update_48(&oes->tx_bytes,
974 i40evf_stat_update_48(&oes->tx_unicast,
976 i40evf_stat_update_48(&oes->tx_multicast,
978 i40evf_stat_update_48(&oes->tx_broadcast,
980 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
981 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
985 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
988 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
989 struct i40e_eth_stats *pstats = NULL;
991 /* read stat values to clear hardware registers */
992 ret = i40evf_query_stats(dev, &pstats);
994 /* set stats offset base on current values */
996 vf->vsi.eth_stats_offset = *pstats;
1001 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1002 struct rte_eth_xstat_name *xstats_names,
1003 __rte_unused unsigned limit)
1007 if (xstats_names != NULL)
1008 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1009 snprintf(xstats_names[i].name,
1010 sizeof(xstats_names[i].name),
1011 "%s", rte_i40evf_stats_strings[i].name);
1013 return I40EVF_NB_XSTATS;
1016 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1017 struct rte_eth_xstat *xstats, unsigned n)
1021 struct i40e_eth_stats *pstats = NULL;
1022 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1023 struct i40e_vsi *vsi = &vf->vsi;
1025 if (n < I40EVF_NB_XSTATS)
1026 return I40EVF_NB_XSTATS;
1028 ret = i40evf_query_stats(dev, &pstats);
1035 i40evf_update_stats(vsi, pstats);
1037 /* loop over xstats array and values from pstats */
1038 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1040 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1041 rte_i40evf_stats_strings[i].offset);
1044 return I40EVF_NB_XSTATS;
1048 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1050 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1051 struct virtchnl_vlan_filter_list *vlan_list;
1052 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1055 struct vf_cmd_info args;
1057 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1058 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1059 vlan_list->num_elements = 1;
1060 vlan_list->vlan_id[0] = vlanid;
1062 args.ops = VIRTCHNL_OP_ADD_VLAN;
1063 args.in_args = (u8 *)&cmd_buffer;
1064 args.in_args_size = sizeof(cmd_buffer);
1065 args.out_buffer = vf->aq_resp;
1066 args.out_size = I40E_AQ_BUF_SZ;
1067 err = i40evf_execute_vf_cmd(dev, &args);
1069 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1075 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1077 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1078 struct virtchnl_vf_res_request vfres;
1079 struct vf_cmd_info args;
1082 vfres.num_queue_pairs = num;
1084 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1085 args.in_args = (u8 *)&vfres;
1086 args.in_args_size = sizeof(vfres);
1087 args.out_buffer = vf->aq_resp;
1088 args.out_size = I40E_AQ_BUF_SZ;
1090 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1092 err = i40evf_execute_vf_cmd(dev, &args);
1094 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);
1096 if (err != I40E_SUCCESS) {
1097 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1101 /* The PF will issue a reset to the VF when change the number of
1102 * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then
1103 * wait 10ms and set it to ACTIVE. In this duration, vf may not catch
1104 * the moment that COMPLETE is set. So, for vf, we'll try to wait a
1109 err = i40evf_check_vf_reset_done(dev);
1111 PMD_DRV_LOG(ERR, "VF is still resetting");
1117 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1119 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1120 struct virtchnl_vlan_filter_list *vlan_list;
1121 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1124 struct vf_cmd_info args;
1126 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1127 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1128 vlan_list->num_elements = 1;
1129 vlan_list->vlan_id[0] = vlanid;
1131 args.ops = VIRTCHNL_OP_DEL_VLAN;
1132 args.in_args = (u8 *)&cmd_buffer;
1133 args.in_args_size = sizeof(cmd_buffer);
1134 args.out_buffer = vf->aq_resp;
1135 args.out_size = I40E_AQ_BUF_SZ;
1136 err = i40evf_execute_vf_cmd(dev, &args);
1138 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1143 static const struct rte_pci_id pci_id_i40evf_map[] = {
1144 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1145 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1146 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1147 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1148 { .vendor_id = 0, /* sentinel */ },
1153 i40evf_disable_irq0(struct i40e_hw *hw)
1155 /* Disable all interrupt types */
1156 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1157 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1158 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1159 I40EVF_WRITE_FLUSH(hw);
1164 i40evf_enable_irq0(struct i40e_hw *hw)
1166 /* Enable admin queue interrupt trigger */
1169 i40evf_disable_irq0(hw);
1170 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1171 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1172 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1173 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1175 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1176 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1177 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1178 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1180 I40EVF_WRITE_FLUSH(hw);
1184 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1190 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1191 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1192 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1193 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1194 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1195 reset == VIRTCHNL_VFR_COMPLETED)
1200 if (i >= MAX_RESET_WAIT_CNT)
1203 vf->vf_reset = false;
1204 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1209 i40evf_reset_vf(struct rte_eth_dev *dev)
1212 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1215 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1219 * After issuing vf reset command to pf, pf won't necessarily
1220 * reset vf, it depends on what state it exactly is. If it's not
1221 * initialized yet, it won't have vf reset since it's in a certain
1222 * state. If not, it will try to reset. Even vf is reset, pf will
1223 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1224 * it to ACTIVE. In this duration, vf may not catch the moment that
1225 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1229 ret = i40evf_check_vf_reset_done(dev);
1231 PMD_INIT_LOG(ERR, "VF is still resetting");
1239 i40evf_init_vf(struct rte_eth_dev *dev)
1242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1245 i40e_calc_itr_interval(0, 0);
1247 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1248 vf->dev_data = dev->data;
1249 err = i40e_set_mac_type(hw);
1251 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1255 err = i40evf_check_vf_reset_done(dev);
1259 i40e_init_adminq_parameter(hw);
1260 err = i40e_init_adminq(hw);
1262 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1266 /* Reset VF and wait until it's complete */
1267 if (i40evf_reset_vf(dev)) {
1268 PMD_INIT_LOG(ERR, "reset NIC failed");
1272 /* VF reset, shutdown admin queue and initialize again */
1273 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1274 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1278 i40e_init_adminq_parameter(hw);
1279 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1280 PMD_INIT_LOG(ERR, "init_adminq failed");
1284 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1286 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1289 if (i40evf_check_api_version(dev) != 0) {
1290 PMD_INIT_LOG(ERR, "check_api version failed");
1293 bufsz = sizeof(struct virtchnl_vf_resource) +
1294 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1295 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1297 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1301 if (i40evf_get_vf_resource(dev) != 0) {
1302 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1306 /* got VF config message back from PF, now we can parse it */
1307 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1308 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1309 vf->vsi_res = &vf->vf_res->vsi_res[i];
1313 PMD_INIT_LOG(ERR, "no LAN VSI found");
1317 if (hw->mac.type == I40E_MAC_X722_VF)
1318 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1319 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1321 switch (vf->vsi_res->vsi_type) {
1322 case VIRTCHNL_VSI_SRIOV:
1323 vf->vsi.type = I40E_VSI_SRIOV;
1326 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1329 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1330 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1332 /* Store the MAC address configured by host, or generate random one */
1333 if (!rte_is_valid_assigned_ether_addr(
1334 (struct rte_ether_addr *)hw->mac.addr))
1335 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1337 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1338 (I40E_ITR_INDEX_DEFAULT <<
1339 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1341 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1342 I40EVF_WRITE_FLUSH(hw);
1347 rte_free(vf->vf_res);
1350 rte_free(vf->aq_resp);
1352 i40e_shutdown_adminq(hw); /* ignore error */
1358 i40evf_uninit_vf(struct rte_eth_dev *dev)
1360 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 PMD_INIT_FUNC_TRACE();
1364 if (hw->adapter_closed == 0)
1365 i40evf_dev_close(dev);
1371 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1372 __rte_unused uint16_t msglen)
1374 struct virtchnl_pf_event *pf_msg =
1375 (struct virtchnl_pf_event *)msg;
1376 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1378 switch (pf_msg->event) {
1379 case VIRTCHNL_EVENT_RESET_IMPENDING:
1380 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1381 rte_eth_dev_callback_process(dev,
1382 RTE_ETH_EVENT_INTR_RESET, NULL);
1384 case VIRTCHNL_EVENT_LINK_CHANGE:
1385 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1387 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {
1389 pf_msg->event_data.link_event_adv.link_status;
1391 switch (pf_msg->event_data.link_event_adv.link_speed) {
1392 case ETH_SPEED_NUM_100M:
1393 vf->link_speed = VIRTCHNL_LINK_SPEED_100MB;
1395 case ETH_SPEED_NUM_1G:
1396 vf->link_speed = VIRTCHNL_LINK_SPEED_1GB;
1398 case ETH_SPEED_NUM_2_5G:
1399 vf->link_speed = VIRTCHNL_LINK_SPEED_2_5GB;
1401 case ETH_SPEED_NUM_5G:
1402 vf->link_speed = VIRTCHNL_LINK_SPEED_5GB;
1404 case ETH_SPEED_NUM_10G:
1405 vf->link_speed = VIRTCHNL_LINK_SPEED_10GB;
1407 case ETH_SPEED_NUM_20G:
1408 vf->link_speed = VIRTCHNL_LINK_SPEED_20GB;
1410 case ETH_SPEED_NUM_25G:
1411 vf->link_speed = VIRTCHNL_LINK_SPEED_25GB;
1413 case ETH_SPEED_NUM_40G:
1414 vf->link_speed = VIRTCHNL_LINK_SPEED_40GB;
1417 vf->link_speed = VIRTCHNL_LINK_SPEED_UNKNOWN;
1422 pf_msg->event_data.link_event.link_status;
1424 pf_msg->event_data.link_event.link_speed;
1427 i40evf_dev_link_update(dev, 0);
1428 rte_eth_dev_callback_process(dev,
1429 RTE_ETH_EVENT_INTR_LSC, NULL);
1431 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1432 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1435 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1441 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1443 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1444 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1445 struct i40e_arq_event_info info;
1446 uint16_t pending, aq_opc;
1447 enum virtchnl_ops msg_opc;
1448 enum i40e_status_code msg_ret;
1451 info.buf_len = I40E_AQ_BUF_SZ;
1453 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1456 info.msg_buf = vf->aq_resp;
1460 ret = i40e_clean_arq_element(hw, &info, &pending);
1462 if (ret != I40E_SUCCESS) {
1463 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1467 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1468 /* For the message sent from pf to vf, opcode is stored in
1469 * cookie_high of struct i40e_aq_desc, while return error code
1470 * are stored in cookie_low, Which is done by
1471 * i40e_aq_send_msg_to_vf in PF driver.*/
1472 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1473 info.desc.cookie_high);
1474 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1475 info.desc.cookie_low);
1477 case i40e_aqc_opc_send_msg_to_vf:
1478 if (msg_opc == VIRTCHNL_OP_EVENT)
1480 i40evf_handle_pf_event(dev, info.msg_buf,
1483 /* read message and it's expected one */
1484 if (msg_opc == vf->pend_cmd) {
1485 vf->cmd_retval = msg_ret;
1486 /* prevent compiler reordering */
1487 rte_compiler_barrier();
1490 PMD_DRV_LOG(ERR, "command mismatch,"
1491 "expect %u, get %u",
1492 vf->pend_cmd, msg_opc);
1493 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1494 " opcode = %d", msg_opc);
1498 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1506 * Interrupt handler triggered by NIC for handling
1507 * specific interrupt. Only adminq interrupt is processed in VF.
1510 * Pointer to interrupt handle.
1512 * The address of parameter (struct rte_eth_dev *) regsitered before.
1518 i40evf_dev_alarm_handler(void *param)
1520 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1521 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 i40evf_disable_irq0(hw);
1526 /* read out interrupt causes */
1527 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1529 /* No interrupt event indicated */
1530 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1533 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1534 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1535 i40evf_handle_aq_msg(dev);
1538 /* Link Status Change interrupt */
1539 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1540 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1544 i40evf_enable_irq0(hw);
1545 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1546 i40evf_dev_alarm_handler, dev);
1550 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1553 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1554 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1556 PMD_INIT_FUNC_TRACE();
1558 /* assign ops func pointer */
1559 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1560 eth_dev->rx_queue_count = i40e_dev_rx_queue_count;
1561 eth_dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1562 eth_dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1563 eth_dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1564 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1565 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1568 * For secondary processes, we don't initialise any further as primary
1569 * has already done this work.
1571 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1572 i40e_set_rx_function(eth_dev);
1573 i40e_set_tx_function(eth_dev);
1576 i40e_set_default_ptype_table(eth_dev);
1577 rte_eth_copy_pci_info(eth_dev, pci_dev);
1579 hw->vendor_id = pci_dev->id.vendor_id;
1580 hw->device_id = pci_dev->id.device_id;
1581 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1582 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1583 hw->bus.device = pci_dev->addr.devid;
1584 hw->bus.func = pci_dev->addr.function;
1585 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1586 hw->adapter_stopped = 1;
1587 hw->adapter_closed = 0;
1589 if(i40evf_init_vf(eth_dev) != 0) {
1590 PMD_INIT_LOG(ERR, "Init vf failed");
1594 i40e_set_default_pctype_table(eth_dev);
1595 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1596 i40evf_dev_alarm_handler, eth_dev);
1598 /* configure and enable device interrupt */
1599 i40evf_enable_irq0(hw);
1602 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1603 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1605 if (eth_dev->data->mac_addrs == NULL) {
1606 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1607 " store MAC addresses",
1608 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1611 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1612 ð_dev->data->mac_addrs[0]);
1618 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1620 PMD_INIT_FUNC_TRACE();
1622 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1625 if (i40evf_uninit_vf(eth_dev) != 0) {
1626 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1633 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1634 struct rte_pci_device *pci_dev)
1636 return rte_eth_dev_pci_generic_probe(pci_dev,
1637 sizeof(struct i40e_adapter), i40evf_dev_init);
1640 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1642 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1646 * virtual function driver struct
1648 static struct rte_pci_driver rte_i40evf_pmd = {
1649 .id_table = pci_id_i40evf_map,
1650 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1651 .probe = eth_i40evf_pci_probe,
1652 .remove = eth_i40evf_pci_remove,
1655 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1656 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1657 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1660 i40evf_dev_configure(struct rte_eth_dev *dev)
1662 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1663 struct i40e_adapter *ad =
1664 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1665 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1666 dev->data->nb_tx_queues);
1668 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1669 * allocation or vector Rx preconditions we will reset it.
1671 ad->rx_bulk_alloc_allowed = true;
1672 ad->rx_vec_allowed = true;
1673 ad->tx_simple_allowed = true;
1674 ad->tx_vec_allowed = true;
1676 dev->data->dev_conf.intr_conf.lsc =
1677 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);
1679 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1683 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1685 "For secondary processes, change queue pairs is not supported!");
1689 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 if (!hw->adapter_stopped) {
1691 PMD_DRV_LOG(ERR, "Device must be stopped first!");
1695 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1696 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1697 ret = i40evf_request_queues(dev, num_queue_pairs);
1701 ret = i40evf_dev_reset(dev);
1706 return i40evf_init_vlan(dev);
1710 i40evf_init_vlan(struct rte_eth_dev *dev)
1712 /* Apply vlan offload setting */
1713 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1719 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1721 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1722 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1724 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1727 /* Vlan stripping setting */
1728 if (mask & ETH_VLAN_STRIP_MASK) {
1729 /* Enable or disable VLAN stripping */
1730 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1731 i40evf_enable_vlan_strip(dev);
1733 i40evf_disable_vlan_strip(dev);
1740 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1742 struct i40e_rx_queue *rxq;
1744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746 PMD_INIT_FUNC_TRACE();
1748 rxq = dev->data->rx_queues[rx_queue_id];
1750 err = i40e_alloc_rx_queue_mbufs(rxq);
1752 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1758 /* Init the RX tail register. */
1759 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1760 I40EVF_WRITE_FLUSH(hw);
1762 /* Ready to switch the queue on */
1763 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1765 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1769 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1775 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1777 struct i40e_rx_queue *rxq;
1780 rxq = dev->data->rx_queues[rx_queue_id];
1782 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1784 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1789 i40e_rx_queue_release_mbufs(rxq);
1790 i40e_reset_rx_queue(rxq);
1791 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1797 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1801 PMD_INIT_FUNC_TRACE();
1803 /* Ready to switch the queue on */
1804 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1806 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1810 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1816 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1818 struct i40e_tx_queue *txq;
1821 txq = dev->data->tx_queues[tx_queue_id];
1823 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1825 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1830 i40e_tx_queue_release_mbufs(txq);
1831 i40e_reset_tx_queue(txq);
1832 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1838 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1843 ret = i40evf_add_vlan(dev, vlan_id);
1845 ret = i40evf_del_vlan(dev,vlan_id);
1851 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1853 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854 struct rte_eth_dev_data *dev_data = dev->data;
1855 struct rte_pktmbuf_pool_private *mbp_priv;
1856 uint16_t buf_size, len;
1858 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1859 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1860 I40EVF_WRITE_FLUSH(hw);
1862 /* Calculate the maximum packet length allowed */
1863 mbp_priv = rte_mempool_get_priv(rxq->mp);
1864 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1865 RTE_PKTMBUF_HEADROOM);
1866 rxq->hs_mode = i40e_header_split_none;
1867 rxq->rx_hdr_len = 0;
1868 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1869 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1870 rxq->max_pkt_len = RTE_MIN(len,
1871 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1874 * Check if the jumbo frame and maximum packet length are set correctly
1876 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1877 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1878 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1879 PMD_DRV_LOG(ERR, "maximum packet length must be "
1880 "larger than %u and smaller than %u, as jumbo "
1881 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1882 (uint32_t)I40E_FRAME_SIZE_MAX);
1883 return I40E_ERR_CONFIG;
1886 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1887 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1888 PMD_DRV_LOG(ERR, "maximum packet length must be "
1889 "larger than %u and smaller than %u, as jumbo "
1890 "frame is disabled",
1891 (uint32_t)RTE_ETHER_MIN_LEN,
1892 (uint32_t)RTE_ETHER_MAX_LEN);
1893 return I40E_ERR_CONFIG;
1897 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1898 rxq->max_pkt_len > buf_size)
1899 dev_data->scattered_rx = 1;
1905 i40evf_rx_init(struct rte_eth_dev *dev)
1907 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1909 int ret = I40E_SUCCESS;
1910 struct i40e_rx_queue **rxq =
1911 (struct i40e_rx_queue **)dev->data->rx_queues;
1913 i40evf_config_rss(vf);
1914 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1915 if (!rxq[i] || !rxq[i]->q_set)
1917 ret = i40evf_rxq_init(dev, rxq[i]);
1918 if (ret != I40E_SUCCESS)
1921 if (ret == I40E_SUCCESS)
1922 i40e_set_rx_function(dev);
1928 i40evf_tx_init(struct rte_eth_dev *dev)
1931 struct i40e_tx_queue **txq =
1932 (struct i40e_tx_queue **)dev->data->tx_queues;
1933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935 for (i = 0; i < dev->data->nb_tx_queues; i++)
1936 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1938 i40e_set_tx_function(dev);
1942 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1944 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1948 if (!rte_intr_allow_others(intr_handle)) {
1950 I40E_VFINT_DYN_CTL01,
1951 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1952 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1953 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1954 I40EVF_WRITE_FLUSH(hw);
1958 I40EVF_WRITE_FLUSH(hw);
1962 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1966 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1968 if (!rte_intr_allow_others(intr_handle)) {
1969 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1970 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1971 I40EVF_WRITE_FLUSH(hw);
1975 I40EVF_WRITE_FLUSH(hw);
1979 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1981 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1982 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1983 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 i40e_calc_itr_interval(0, 0);
1988 msix_intr = intr_handle->intr_vec[queue_id];
1989 if (msix_intr == I40E_MISC_VEC_ID)
1990 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1991 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1992 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1993 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1995 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1998 I40E_VFINT_DYN_CTLN1(msix_intr -
2000 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2001 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2002 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2004 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2006 I40EVF_WRITE_FLUSH(hw);
2012 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2014 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2015 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019 msix_intr = intr_handle->intr_vec[queue_id];
2020 if (msix_intr == I40E_MISC_VEC_ID)
2021 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2024 I40E_VFINT_DYN_CTLN1(msix_intr -
2028 I40EVF_WRITE_FLUSH(hw);
2034 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2036 struct virtchnl_ether_addr_list *list;
2037 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2042 struct rte_ether_addr *addr;
2043 struct vf_cmd_info args;
2047 len = sizeof(struct virtchnl_ether_addr_list);
2048 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2049 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
2051 len += sizeof(struct virtchnl_ether_addr);
2052 if (len >= I40E_AQ_BUF_SZ) {
2058 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2060 PMD_DRV_LOG(ERR, "fail to allocate memory");
2064 for (i = begin; i < next_begin; i++) {
2065 addr = &dev->data->mac_addrs[i];
2066 if (rte_is_zero_ether_addr(addr))
2068 rte_memcpy(list->list[j].addr, addr->addr_bytes,
2069 sizeof(addr->addr_bytes));
2070 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2071 addr->addr_bytes[0], addr->addr_bytes[1],
2072 addr->addr_bytes[2], addr->addr_bytes[3],
2073 addr->addr_bytes[4], addr->addr_bytes[5]);
2076 list->vsi_id = vf->vsi_res->vsi_id;
2077 list->num_elements = j;
2078 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2079 VIRTCHNL_OP_DEL_ETH_ADDR;
2080 args.in_args = (uint8_t *)list;
2081 args.in_args_size = len;
2082 args.out_buffer = vf->aq_resp;
2083 args.out_size = I40E_AQ_BUF_SZ;
2084 err = i40evf_execute_vf_cmd(dev, &args);
2086 PMD_DRV_LOG(ERR, "fail to execute command %s",
2087 add ? "OP_ADD_ETHER_ADDRESS" :
2088 "OP_DEL_ETHER_ADDRESS");
2097 } while (begin < I40E_NUM_MACADDR_MAX);
2101 i40evf_dev_start(struct rte_eth_dev *dev)
2103 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2106 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2107 uint32_t intr_vector = 0;
2109 PMD_INIT_FUNC_TRACE();
2111 hw->adapter_stopped = 0;
2113 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2114 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2115 dev->data->nb_tx_queues);
2117 /* check and configure queue intr-vector mapping */
2118 if (rte_intr_cap_multiple(intr_handle) &&
2119 dev->data->dev_conf.intr_conf.rxq) {
2120 intr_vector = dev->data->nb_rx_queues;
2121 if (rte_intr_efd_enable(intr_handle, intr_vector))
2125 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2126 intr_handle->intr_vec =
2127 rte_zmalloc("intr_vec",
2128 dev->data->nb_rx_queues * sizeof(int), 0);
2129 if (!intr_handle->intr_vec) {
2130 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2131 " intr_vec", dev->data->nb_rx_queues);
2136 if (i40evf_rx_init(dev) != 0){
2137 PMD_DRV_LOG(ERR, "failed to do RX init");
2141 i40evf_tx_init(dev);
2143 if (i40evf_configure_vsi_queues(dev) != 0) {
2144 PMD_DRV_LOG(ERR, "configure queues failed");
2147 if (i40evf_config_irq_map(dev)) {
2148 PMD_DRV_LOG(ERR, "config_irq_map failed");
2152 /* Set all mac addrs */
2153 i40evf_add_del_all_mac_addr(dev, TRUE);
2154 /* Set all multicast addresses */
2155 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2158 if (i40evf_start_queues(dev) != 0) {
2159 PMD_DRV_LOG(ERR, "enable queues failed");
2163 /* only enable interrupt in rx interrupt mode */
2164 if (dev->data->dev_conf.intr_conf.rxq != 0)
2165 rte_intr_enable(intr_handle);
2167 i40evf_enable_queues_intr(dev);
2172 i40evf_add_del_all_mac_addr(dev, FALSE);
2173 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2180 i40evf_dev_stop(struct rte_eth_dev *dev)
2182 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2183 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2187 PMD_INIT_FUNC_TRACE();
2189 if (dev->data->dev_conf.intr_conf.rxq != 0)
2190 rte_intr_disable(intr_handle);
2192 if (hw->adapter_stopped == 1)
2194 i40evf_stop_queues(dev);
2195 i40evf_disable_queues_intr(dev);
2196 i40e_dev_clear_queues(dev);
2198 /* Clean datapath event and queue/vec mapping */
2199 rte_intr_efd_disable(intr_handle);
2200 if (intr_handle->intr_vec) {
2201 rte_free(intr_handle->intr_vec);
2202 intr_handle->intr_vec = NULL;
2204 /* remove all mac addrs */
2205 i40evf_add_del_all_mac_addr(dev, FALSE);
2206 /* remove all multicast addresses */
2207 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2209 hw->adapter_stopped = 1;
2210 dev->data->dev_started = 0;
2216 i40evf_dev_link_update(struct rte_eth_dev *dev,
2217 __rte_unused int wait_to_complete)
2219 struct rte_eth_link new_link;
2220 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2222 * DPDK pf host provide interfacet to acquire link status
2223 * while Linux driver does not
2226 memset(&new_link, 0, sizeof(new_link));
2227 /* Linux driver PF host */
2228 switch (vf->link_speed) {
2229 case I40E_LINK_SPEED_100MB:
2230 new_link.link_speed = ETH_SPEED_NUM_100M;
2232 case I40E_LINK_SPEED_1GB:
2233 new_link.link_speed = ETH_SPEED_NUM_1G;
2235 case I40E_LINK_SPEED_10GB:
2236 new_link.link_speed = ETH_SPEED_NUM_10G;
2238 case I40E_LINK_SPEED_20GB:
2239 new_link.link_speed = ETH_SPEED_NUM_20G;
2241 case I40E_LINK_SPEED_25GB:
2242 new_link.link_speed = ETH_SPEED_NUM_25G;
2244 case I40E_LINK_SPEED_40GB:
2245 new_link.link_speed = ETH_SPEED_NUM_40G;
2249 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2251 new_link.link_speed = ETH_SPEED_NUM_NONE;
2254 /* full duplex only */
2255 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256 new_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
2257 new_link.link_autoneg =
2258 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2260 return rte_eth_linkstatus_set(dev, &new_link);
2264 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2266 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2268 return i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);
2272 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2274 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2276 return i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);
2280 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2282 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2284 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);
2288 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2290 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2292 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);
2296 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2298 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2300 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2301 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2302 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2303 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2304 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2305 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2306 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2307 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2308 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2309 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2310 dev_info->rx_queue_offload_capa = 0;
2311 dev_info->rx_offload_capa =
2312 DEV_RX_OFFLOAD_VLAN_STRIP |
2313 DEV_RX_OFFLOAD_QINQ_STRIP |
2314 DEV_RX_OFFLOAD_IPV4_CKSUM |
2315 DEV_RX_OFFLOAD_UDP_CKSUM |
2316 DEV_RX_OFFLOAD_TCP_CKSUM |
2317 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2318 DEV_RX_OFFLOAD_SCATTER |
2319 DEV_RX_OFFLOAD_JUMBO_FRAME |
2320 DEV_RX_OFFLOAD_VLAN_FILTER;
2322 dev_info->tx_queue_offload_capa = 0;
2323 dev_info->tx_offload_capa =
2324 DEV_TX_OFFLOAD_VLAN_INSERT |
2325 DEV_TX_OFFLOAD_QINQ_INSERT |
2326 DEV_TX_OFFLOAD_IPV4_CKSUM |
2327 DEV_TX_OFFLOAD_UDP_CKSUM |
2328 DEV_TX_OFFLOAD_TCP_CKSUM |
2329 DEV_TX_OFFLOAD_SCTP_CKSUM |
2330 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2331 DEV_TX_OFFLOAD_TCP_TSO |
2332 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2333 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2334 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2335 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2336 DEV_TX_OFFLOAD_MULTI_SEGS;
2338 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2340 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2341 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2342 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2344 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2349 dev_info->default_txconf = (struct rte_eth_txconf) {
2351 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2352 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2353 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2355 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2356 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2360 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2361 .nb_max = I40E_MAX_RING_DESC,
2362 .nb_min = I40E_MIN_RING_DESC,
2363 .nb_align = I40E_ALIGN_RING_DESC,
2366 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2367 .nb_max = I40E_MAX_RING_DESC,
2368 .nb_min = I40E_MIN_RING_DESC,
2369 .nb_align = I40E_ALIGN_RING_DESC,
2376 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2379 struct i40e_eth_stats *pstats = NULL;
2380 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2381 struct i40e_vsi *vsi = &vf->vsi;
2383 ret = i40evf_query_stats(dev, &pstats);
2385 i40evf_update_stats(vsi, pstats);
2387 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2388 pstats->rx_broadcast;
2389 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2391 stats->imissed = pstats->rx_discards;
2392 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2393 stats->ibytes = pstats->rx_bytes;
2394 stats->obytes = pstats->tx_bytes;
2396 PMD_DRV_LOG(ERR, "Get statistics failed");
2402 i40evf_dev_close(struct rte_eth_dev *dev)
2404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2408 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2411 ret = i40evf_dev_stop(dev);
2413 i40e_dev_free_queues(dev);
2415 * disable promiscuous mode before reset vf
2416 * it is a workaround solution when work with kernel driver
2417 * and it is not the normal way
2419 if (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)
2420 i40evf_config_promisc(dev, false, false);
2422 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2424 i40evf_reset_vf(dev);
2425 i40e_shutdown_adminq(hw);
2426 i40evf_disable_irq0(hw);
2428 rte_free(vf->vf_res);
2430 rte_free(vf->aq_resp);
2433 hw->adapter_closed = 1;
2438 * Reset VF device only to re-initialize resources in PMD layer
2441 i40evf_dev_reset(struct rte_eth_dev *dev)
2445 ret = i40evf_dev_uninit(dev);
2449 ret = i40evf_dev_init(dev);
2455 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2457 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2458 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2464 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2465 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2468 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2472 uint32_t *lut_dw = (uint32_t *)lut;
2473 uint16_t i, lut_size_dw = lut_size / 4;
2475 for (i = 0; i < lut_size_dw; i++)
2476 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2483 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2492 vf = I40E_VSI_TO_VF(vsi);
2493 hw = I40E_VSI_TO_HW(vsi);
2495 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2496 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2499 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2503 uint32_t *lut_dw = (uint32_t *)lut;
2504 uint16_t i, lut_size_dw = lut_size / 4;
2506 for (i = 0; i < lut_size_dw; i++)
2507 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2508 I40EVF_WRITE_FLUSH(hw);
2515 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2516 struct rte_eth_rss_reta_entry64 *reta_conf,
2519 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2521 uint16_t i, idx, shift;
2524 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2525 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2526 "(%d) doesn't match the number of hardware can "
2527 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2531 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2533 PMD_DRV_LOG(ERR, "No memory can be allocated");
2536 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2539 for (i = 0; i < reta_size; i++) {
2540 idx = i / RTE_RETA_GROUP_SIZE;
2541 shift = i % RTE_RETA_GROUP_SIZE;
2542 if (reta_conf[idx].mask & (1ULL << shift))
2543 lut[i] = reta_conf[idx].reta[shift];
2545 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2554 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2555 struct rte_eth_rss_reta_entry64 *reta_conf,
2558 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2559 uint16_t i, idx, shift;
2563 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2564 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2565 "(%d) doesn't match the number of hardware can "
2566 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2570 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2572 PMD_DRV_LOG(ERR, "No memory can be allocated");
2576 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2579 for (i = 0; i < reta_size; i++) {
2580 idx = i / RTE_RETA_GROUP_SIZE;
2581 shift = i % RTE_RETA_GROUP_SIZE;
2582 if (reta_conf[idx].mask & (1ULL << shift))
2583 reta_conf[idx].reta[shift] = lut[i];
2593 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2595 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2596 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2599 if (!key || key_len == 0) {
2600 PMD_DRV_LOG(DEBUG, "No key to be configured");
2602 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2604 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2608 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2609 struct i40e_aqc_get_set_rss_key_data *key_dw =
2610 (struct i40e_aqc_get_set_rss_key_data *)key;
2612 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2614 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2617 uint32_t *hash_key = (uint32_t *)key;
2620 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2621 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2622 I40EVF_WRITE_FLUSH(hw);
2629 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2631 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2632 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2635 if (!key || !key_len)
2638 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2639 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2640 (struct i40e_aqc_get_set_rss_key_data *)key);
2642 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2646 uint32_t *key_dw = (uint32_t *)key;
2649 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2650 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2652 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2658 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2660 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2664 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2665 rss_conf->rss_key_len);
2669 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2670 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2671 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2672 I40EVF_WRITE_FLUSH(hw);
2678 i40evf_disable_rss(struct i40e_vf *vf)
2680 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2682 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2683 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2684 I40EVF_WRITE_FLUSH(hw);
2688 i40evf_config_rss(struct i40e_vf *vf)
2690 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2691 struct rte_eth_rss_conf rss_conf;
2692 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2693 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2698 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2699 i40evf_disable_rss(vf);
2700 PMD_DRV_LOG(DEBUG, "RSS not configured");
2704 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2705 /* Fill out the look up table */
2706 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2707 for (i = 0, j = 0; i < nb_q; i++, j++) {
2710 lut = (lut << 8) | j;
2712 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2715 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2717 PMD_DRV_LOG(ERR, "No memory can be allocated");
2721 for (i = 0; i < rss_lut_size; i++)
2722 lut_info[i] = i % vf->num_queue_pairs;
2724 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2731 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2732 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2733 i40evf_disable_rss(vf);
2734 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2738 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2739 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2740 /* Calculate the default hash key */
2741 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2742 rss_key_default[i] = (uint32_t)rte_rand();
2743 rss_conf.rss_key = (uint8_t *)rss_key_default;
2744 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2748 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2752 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2753 struct rte_eth_rss_conf *rss_conf)
2755 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2760 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2761 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2763 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2764 if (rss_hf != 0) /* Enable RSS */
2770 if (rss_hf == 0) /* Disable RSS */
2773 return i40evf_hw_rss_hash_set(vf, rss_conf);
2777 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2778 struct rte_eth_rss_conf *rss_conf)
2780 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2785 &rss_conf->rss_key_len);
2787 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2788 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2789 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2795 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2797 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2798 struct rte_eth_dev_data *dev_data = vf->dev_data;
2799 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2802 /* check if mtu is within the allowed range */
2803 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2806 /* mtu setting is forbidden if port is start */
2807 if (dev_data->dev_started) {
2808 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2813 if (frame_size > RTE_ETHER_MAX_LEN)
2814 dev_data->dev_conf.rxmode.offloads |=
2815 DEV_RX_OFFLOAD_JUMBO_FRAME;
2817 dev_data->dev_conf.rxmode.offloads &=
2818 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2819 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2825 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2826 struct rte_ether_addr *mac_addr)
2828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2831 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2835 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2837 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2840 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2845 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2846 struct rte_ether_addr *mc_addrs,
2847 uint32_t mc_addrs_num, bool add)
2849 struct virtchnl_ether_addr_list *list;
2850 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2851 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2852 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2855 struct vf_cmd_info args;
2857 if (mc_addrs == NULL || mc_addrs_num == 0)
2860 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2863 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2864 list->vsi_id = vf->vsi_res->vsi_id;
2865 list->num_elements = mc_addrs_num;
2867 for (i = 0; i < mc_addrs_num; i++) {
2868 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2869 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2870 mc_addrs[i].addr_bytes[0],
2871 mc_addrs[i].addr_bytes[1],
2872 mc_addrs[i].addr_bytes[2],
2873 mc_addrs[i].addr_bytes[3],
2874 mc_addrs[i].addr_bytes[4],
2875 mc_addrs[i].addr_bytes[5]);
2879 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2880 sizeof(list->list[i].addr));
2883 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2884 args.in_args = cmd_buffer;
2885 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2886 i * sizeof(struct virtchnl_ether_addr);
2887 args.out_buffer = vf->aq_resp;
2888 args.out_size = I40E_AQ_BUF_SZ;
2889 err = i40evf_execute_vf_cmd(dev, &args);
2891 PMD_DRV_LOG(ERR, "fail to execute command %s",
2892 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2900 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2901 struct rte_ether_addr *mc_addrs,
2902 uint32_t mc_addrs_num)
2904 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2907 /* flush previous addresses */
2908 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2913 vf->mc_addrs_num = 0;
2916 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2921 vf->mc_addrs_num = mc_addrs_num;
2922 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2928 is_i40evf_supported(struct rte_eth_dev *dev)
2930 return is_device_supported(dev, &rte_i40evf_pmd);