drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum i40e_virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum i40e_virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   __rte_unused int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 123                                 int on);
 124 static void i40evf_dev_close(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 131                                      uint16_t rx_queue_id);
 132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 133                                     uint16_t rx_queue_id);
 134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 135                                      uint16_t tx_queue_id);
 136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 137                                     uint16_t tx_queue_id);
 138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 139                                 struct ether_addr *addr,
 140                                 uint32_t index,
 141                                 uint32_t pool);
 142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                         struct rte_eth_rss_reta_entry64 *reta_conf,
 148                         uint16_t reta_size);
 149 static int i40evf_config_rss(struct i40e_vf *vf);
 150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 151                                       struct rte_eth_rss_conf *rss_conf);
 152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 153                                         struct rte_eth_rss_conf *rss_conf);
 154 static int
 155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 156 static int
 157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 159                                    uint8_t *msg,
 160                                    uint16_t msglen);
 161
 162 /* Default hash key buffer for RSS */
 163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 164
 165 struct rte_i40evf_xstats_name_off {
 166         char name[RTE_ETH_XSTATS_NAME_SIZE];
 167         unsigned offset;
 168 };
 169
 170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 171         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 172         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 179         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 180         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 182         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 183         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 184 };
 185
 186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 187                 sizeof(rte_i40evf_stats_strings[0]))
 188
 189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 190         .dev_configure        = i40evf_dev_configure,
 191         .dev_start            = i40evf_dev_start,
 192         .dev_stop             = i40evf_dev_stop,
 193         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 194         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 195         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 196         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 197         .link_update          = i40evf_dev_link_update,
 198         .stats_get            = i40evf_dev_stats_get,
 199         .xstats_get           = i40evf_dev_xstats_get,
 200         .xstats_get_names     = i40evf_dev_xstats_get_names,
 201         .xstats_reset         = i40evf_dev_xstats_reset,
 202         .dev_close            = i40evf_dev_close,
 203         .dev_infos_get        = i40evf_dev_info_get,
 204         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 205         .vlan_filter_set      = i40evf_vlan_filter_set,
 206         .vlan_offload_set     = i40evf_vlan_offload_set,
 207         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 208         .rx_queue_start       = i40evf_dev_rx_queue_start,
 209         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 210         .tx_queue_start       = i40evf_dev_tx_queue_start,
 211         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 212         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 213         .rx_queue_release     = i40e_dev_rx_queue_release,
 214         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 215         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 216         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 217         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 218         .tx_queue_release     = i40e_dev_tx_queue_release,
 219         .rx_queue_count       = i40e_dev_rx_queue_count,
 220         .rxq_info_get         = i40e_rxq_info_get,
 221         .txq_info_get         = i40e_txq_info_get,
 222         .mac_addr_add         = i40evf_add_mac_addr,
 223         .mac_addr_remove      = i40evf_del_mac_addr,
 224         .reta_update          = i40evf_dev_rss_reta_update,
 225         .reta_query           = i40evf_dev_rss_reta_query,
 226         .rss_hash_update      = i40evf_dev_rss_hash_update,
 227         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 228 };
 229
 230 /*
 231  * Read data in admin queue to get msg from pf driver
 232  */
 233 static enum i40evf_aq_result
 234 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 235 {
 236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 237         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 238         struct i40e_arq_event_info event;
 239         enum i40e_virtchnl_ops opcode;
 240         enum i40e_status_code retval;
 241         int ret;
 242         enum i40evf_aq_result result = I40EVF_MSG_NON;
 243
 244         event.buf_len = data->buf_len;
 245         event.msg_buf = data->msg;
 246         ret = i40e_clean_arq_element(hw, &event, NULL);
 247         /* Can't read any msg from adminQ */
 248         if (ret) {
 249                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 250                         result = I40EVF_MSG_ERR;
 251                 return result;
 252         }
 253
 254         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 255         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 256         /* pf sys event */
 257         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 258                 struct i40e_virtchnl_pf_event *vpe =
 259                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 260
 261                 result = I40EVF_MSG_SYS;
 262                 switch (vpe->event) {
 263                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 264                         vf->link_up =
 265                                 vpe->event_data.link_event.link_status;
 266                         vf->link_speed =
 267                                 vpe->event_data.link_event.link_speed;
 268                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 269                         PMD_DRV_LOG(INFO, "Link status update:%s",
 270                                     vf->link_up ? "up" : "down");
 271                         break;
 272                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 273                         vf->vf_reset = true;
 274                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 275                         PMD_DRV_LOG(INFO, "vf is reseting");
 276                         break;
 277                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 278                         vf->dev_closed = true;
 279                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 280                         PMD_DRV_LOG(INFO, "PF driver closed");
 281                         break;
 282                 default:
 283                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 284                                     __func__, vpe->event);
 285                 }
 286         } else {
 287                 /* async reply msg on command issued by vf previously */
 288                 result = I40EVF_MSG_CMD;
 289                 /* Actual data length read from PF */
 290                 data->msg_len = event.msg_len;
 291         }
 292
 293         data->result = retval;
 294         data->ops = opcode;
 295
 296         return result;
 297 }
 298
 299 /**
 300  * clear current command. Only call in case execute
 301  * _atomic_set_cmd successfully.
 302  */
 303 static inline void
 304 _clear_cmd(struct i40e_vf *vf)
 305 {
 306         rte_wmb();
 307         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 308 }
 309
 310 /*
 311  * Check there is pending cmd in execution. If none, set new command.
 312  */
 313 static inline int
 314 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 315 {
 316         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 317                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 318
 319         if (!ret)
 320                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 321
 322         return !ret;
 323 }
 324
 325 #define MAX_TRY_TIMES 200
 326 #define ASQ_DELAY_MS  10
 327
 328 static int
 329 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 330 {
 331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 332         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 333         struct i40evf_arq_msg_info info;
 334         enum i40evf_aq_result ret;
 335         int err, i = 0;
 336
 337         if (_atomic_set_cmd(vf, args->ops))
 338                 return -1;
 339
 340         info.msg = args->out_buffer;
 341         info.buf_len = args->out_size;
 342         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 343         info.result = I40E_SUCCESS;
 344
 345         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 346                      args->in_args, args->in_args_size, NULL);
 347         if (err) {
 348                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 349                 _clear_cmd(vf);
 350                 return err;
 351         }
 352
 353         switch (args->ops) {
 354         case I40E_VIRTCHNL_OP_RESET_VF:
 355                 /*no need to process in this function */
 356                 err = 0;
 357                 break;
 358         case I40E_VIRTCHNL_OP_VERSION:
 359         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 360                 /* for init adminq commands, need to poll the response */
 361                 err = -1;
 362                 do {
 363                         ret = i40evf_read_pfmsg(dev, &info);
 364                         if (ret == I40EVF_MSG_CMD) {
 365                                 err = 0;
 366                                 break;
 367                         } else if (ret == I40EVF_MSG_ERR)
 368                                 break;
 369                         rte_delay_ms(ASQ_DELAY_MS);
 370                         /* If don't read msg or read sys event, continue */
 371                 } while (i++ < MAX_TRY_TIMES);
 372                 _clear_cmd(vf);
 373                 break;
 374
 375         default:
 376                 /* for other adminq in running time, waiting the cmd done flag */
 377                 err = -1;
 378                 do {
 379                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 380                                 err = 0;
 381                                 break;
 382                         }
 383                         rte_delay_ms(ASQ_DELAY_MS);
 384                         /* If don't read msg or read sys event, continue */
 385                 } while (i++ < MAX_TRY_TIMES);
 386                 break;
 387         }
 388
 389         return err | vf->cmd_retval;
 390 }
 391
 392 /*
 393  * Check API version with sync wait until version read or fail from admin queue
 394  */
 395 static int
 396 i40evf_check_api_version(struct rte_eth_dev *dev)
 397 {
 398         struct i40e_virtchnl_version_info version, *pver;
 399         int err;
 400         struct vf_cmd_info args;
 401         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 402
 403         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 404         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 405
 406         args.ops = I40E_VIRTCHNL_OP_VERSION;
 407         args.in_args = (uint8_t *)&version;
 408         args.in_args_size = sizeof(version);
 409         args.out_buffer = vf->aq_resp;
 410         args.out_size = I40E_AQ_BUF_SZ;
 411
 412         err = i40evf_execute_vf_cmd(dev, &args);
 413         if (err) {
 414                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 415                 return err;
 416         }
 417
 418         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 419         vf->version_major = pver->major;
 420         vf->version_minor = pver->minor;
 421         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 422                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 423         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 424                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 425                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 426         else {
 427                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 428                                         vf->version_major, vf->version_minor,
 429                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 430                                                 I40E_VIRTCHNL_VERSION_MINOR);
 431                 return -1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int
 438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 439 {
 440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 441         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 442         int err;
 443         struct vf_cmd_info args;
 444         uint32_t caps, len;
 445
 446         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 447         args.out_buffer = vf->aq_resp;
 448         args.out_size = I40E_AQ_BUF_SZ;
 449         if (PF_IS_V11(vf)) {
 450                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 451                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 452                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 453                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 454                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 455                 args.in_args = (uint8_t *)&caps;
 456                 args.in_args_size = sizeof(caps);
 457         } else {
 458                 args.in_args = NULL;
 459                 args.in_args_size = 0;
 460         }
 461         err = i40evf_execute_vf_cmd(dev, &args);
 462
 463         if (err) {
 464                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 465                 return err;
 466         }
 467
 468         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 469                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 470
 471         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 472                         RTE_MIN(args.out_size, len));
 473         i40e_vf_parse_hw_config(hw, vf->vf_res);
 474
 475         return 0;
 476 }
 477
 478 static int
 479 i40evf_config_promisc(struct rte_eth_dev *dev,
 480                       bool enable_unicast,
 481                       bool enable_multicast)
 482 {
 483         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 484         int err;
 485         struct vf_cmd_info args;
 486         struct i40e_virtchnl_promisc_info promisc;
 487
 488         promisc.flags = 0;
 489         promisc.vsi_id = vf->vsi_res->vsi_id;
 490
 491         if (enable_unicast)
 492                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 493
 494         if (enable_multicast)
 495                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 496
 497         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 498         args.in_args = (uint8_t *)&promisc;
 499         args.in_args_size = sizeof(promisc);
 500         args.out_buffer = vf->aq_resp;
 501         args.out_size = I40E_AQ_BUF_SZ;
 502
 503         err = i40evf_execute_vf_cmd(dev, &args);
 504
 505         if (err)
 506                 PMD_DRV_LOG(ERR, "fail to execute command "
 507                             "CONFIG_PROMISCUOUS_MODE");
 508         return err;
 509 }
 510
 511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 512 static int
 513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 514                                 bool enable_vlan_strip)
 515 {
 516         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 517         int err;
 518         struct vf_cmd_info args;
 519         struct i40e_virtchnl_vlan_offload_info offload;
 520
 521         offload.vsi_id = vf->vsi_res->vsi_id;
 522         offload.enable_vlan_strip = enable_vlan_strip;
 523
 524         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 525         args.in_args = (uint8_t *)&offload;
 526         args.in_args_size = sizeof(offload);
 527         args.out_buffer = vf->aq_resp;
 528         args.out_size = I40E_AQ_BUF_SZ;
 529
 530         err = i40evf_execute_vf_cmd(dev, &args);
 531         if (err)
 532                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 533
 534         return err;
 535 }
 536
 537 static int
 538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 539                                 struct i40e_vsi_vlan_pvid_info *info)
 540 {
 541         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 542         int err;
 543         struct vf_cmd_info args;
 544         struct i40e_virtchnl_pvid_info tpid_info;
 545
 546         if (info == NULL) {
 547                 PMD_DRV_LOG(ERR, "invalid parameters");
 548                 return I40E_ERR_PARAM;
 549         }
 550
 551         memset(&tpid_info, 0, sizeof(tpid_info));
 552         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 553         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 554
 555         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 556         args.in_args = (uint8_t *)&tpid_info;
 557         args.in_args_size = sizeof(tpid_info);
 558         args.out_buffer = vf->aq_resp;
 559         args.out_size = I40E_AQ_BUF_SZ;
 560
 561         err = i40evf_execute_vf_cmd(dev, &args);
 562         if (err)
 563                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 564
 565         return err;
 566 }
 567
 568 static void
 569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 570                                   uint16_t vsi_id,
 571                                   uint16_t queue_id,
 572                                   uint16_t nb_txq,
 573                                   struct i40e_tx_queue *txq)
 574 {
 575         txq_info->vsi_id = vsi_id;
 576         txq_info->queue_id = queue_id;
 577         if (queue_id < nb_txq) {
 578                 txq_info->ring_len = txq->nb_tx_desc;
 579                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 580         }
 581 }
 582
 583 static void
 584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 585                                   uint16_t vsi_id,
 586                                   uint16_t queue_id,
 587                                   uint16_t nb_rxq,
 588                                   uint32_t max_pkt_size,
 589                                   struct i40e_rx_queue *rxq)
 590 {
 591         rxq_info->vsi_id = vsi_id;
 592         rxq_info->queue_id = queue_id;
 593         rxq_info->max_pkt_size = max_pkt_size;
 594         if (queue_id < nb_rxq) {
 595                 rxq_info->ring_len = rxq->nb_rx_desc;
 596                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 597                 rxq_info->databuffer_size =
 598                         (rte_pktmbuf_data_room_size(rxq->mp) -
 599                                 RTE_PKTMBUF_HEADROOM);
 600         }
 601 }
 602
 603 /* It configures VSI queues to co-work with Linux PF host */
 604 static int
 605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 606 {
 607         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 608         struct i40e_rx_queue **rxq =
 609                 (struct i40e_rx_queue **)dev->data->rx_queues;
 610         struct i40e_tx_queue **txq =
 611                 (struct i40e_tx_queue **)dev->data->tx_queues;
 612         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 613         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 614         struct vf_cmd_info args;
 615         uint16_t i, nb_qp = vf->num_queue_pairs;
 616         const uint32_t size =
 617                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 618         uint8_t buff[size];
 619         int ret;
 620
 621         memset(buff, 0, sizeof(buff));
 622         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 623         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 624         vc_vqci->num_queue_pairs = nb_qp;
 625
 626         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 627                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 628                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 629                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 630                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 631                                         vf->max_pkt_len, rxq[i]);
 632         }
 633         memset(&args, 0, sizeof(args));
 634         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 635         args.in_args = (uint8_t *)vc_vqci;
 636         args.in_args_size = size;
 637         args.out_buffer = vf->aq_resp;
 638         args.out_size = I40E_AQ_BUF_SZ;
 639         ret = i40evf_execute_vf_cmd(dev, &args);
 640         if (ret)
 641                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 642                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 643
 644         return ret;
 645 }
 646
 647 /* It configures VSI queues to co-work with DPDK PF host */
 648 static int
 649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 650 {
 651         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 652         struct i40e_rx_queue **rxq =
 653                 (struct i40e_rx_queue **)dev->data->rx_queues;
 654         struct i40e_tx_queue **txq =
 655                 (struct i40e_tx_queue **)dev->data->tx_queues;
 656         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 657         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 658         struct vf_cmd_info args;
 659         uint16_t i, nb_qp = vf->num_queue_pairs;
 660         const uint32_t size =
 661                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 662         uint8_t buff[size];
 663         int ret;
 664
 665         memset(buff, 0, sizeof(buff));
 666         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 667         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 668         vc_vqcei->num_queue_pairs = nb_qp;
 669         vc_qpei = vc_vqcei->qpair;
 670         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 671                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 672                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 673                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 674                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 675                                         vf->max_pkt_len, rxq[i]);
 676                 if (i < dev->data->nb_rx_queues)
 677                         /*
 678                          * It adds extra info for configuring VSI queues, which
 679                          * is needed to enable the configurable crc stripping
 680                          * in VF.
 681                          */
 682                         vc_qpei->rxq_ext.crcstrip =
 683                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 684         }
 685         memset(&args, 0, sizeof(args));
 686         args.ops =
 687                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 688         args.in_args = (uint8_t *)vc_vqcei;
 689         args.in_args_size = size;
 690         args.out_buffer = vf->aq_resp;
 691         args.out_size = I40E_AQ_BUF_SZ;
 692         ret = i40evf_execute_vf_cmd(dev, &args);
 693         if (ret)
 694                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 695                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 696
 697         return ret;
 698 }
 699
 700 static int
 701 i40evf_configure_queues(struct rte_eth_dev *dev)
 702 {
 703         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 704
 705         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 706                 /* To support DPDK PF host */
 707                 return i40evf_configure_vsi_queues_ext(dev);
 708         else
 709                 /* To support Linux PF host */
 710                 return i40evf_configure_vsi_queues(dev);
 711 }
 712
 713 static int
 714 i40evf_config_irq_map(struct rte_eth_dev *dev)
 715 {
 716         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 717         struct vf_cmd_info args;
 718         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 719                 sizeof(struct i40e_virtchnl_vector_map)];
 720         struct i40e_virtchnl_irq_map_info *map_info;
 721         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 722         uint32_t vector_id;
 723         int i, err;
 724
 725         if (rte_intr_allow_others(intr_handle)) {
 726                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 727                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 728                 else
 729                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 730         } else {
 731                 vector_id = I40E_MISC_VEC_ID;
 732         }
 733
 734         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 735         map_info->num_vectors = 1;
 736         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 737         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 738         /* Alway use default dynamic MSIX interrupt */
 739         map_info->vecmap[0].vector_id = vector_id;
 740         /* Don't map any tx queue */
 741         map_info->vecmap[0].txq_map = 0;
 742         map_info->vecmap[0].rxq_map = 0;
 743         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 744                 map_info->vecmap[0].rxq_map |= 1 << i;
 745                 if (rte_intr_dp_is_en(intr_handle))
 746                         intr_handle->intr_vec[i] = vector_id;
 747         }
 748
 749         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 750         args.in_args = (u8 *)cmd_buffer;
 751         args.in_args_size = sizeof(cmd_buffer);
 752         args.out_buffer = vf->aq_resp;
 753         args.out_size = I40E_AQ_BUF_SZ;
 754         err = i40evf_execute_vf_cmd(dev, &args);
 755         if (err)
 756                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 757
 758         return err;
 759 }
 760
 761 static int
 762 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 763                                 bool on)
 764 {
 765         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 766         struct i40e_virtchnl_queue_select queue_select;
 767         int err;
 768         struct vf_cmd_info args;
 769         memset(&queue_select, 0, sizeof(queue_select));
 770         queue_select.vsi_id = vf->vsi_res->vsi_id;
 771
 772         if (isrx)
 773                 queue_select.rx_queues |= 1 << qid;
 774         else
 775                 queue_select.tx_queues |= 1 << qid;
 776
 777         if (on)
 778                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 779         else
 780                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 781         args.in_args = (u8 *)&queue_select;
 782         args.in_args_size = sizeof(queue_select);
 783         args.out_buffer = vf->aq_resp;
 784         args.out_size = I40E_AQ_BUF_SZ;
 785         err = i40evf_execute_vf_cmd(dev, &args);
 786         if (err)
 787                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 788                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 789
 790         return err;
 791 }
 792
 793 static int
 794 i40evf_start_queues(struct rte_eth_dev *dev)
 795 {
 796         struct rte_eth_dev_data *dev_data = dev->data;
 797         int i;
 798         struct i40e_rx_queue *rxq;
 799         struct i40e_tx_queue *txq;
 800
 801         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 802                 rxq = dev_data->rx_queues[i];
 803                 if (rxq->rx_deferred_start)
 804                         continue;
 805                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 806                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 807                         return -1;
 808                 }
 809         }
 810
 811         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 812                 txq = dev_data->tx_queues[i];
 813                 if (txq->tx_deferred_start)
 814                         continue;
 815                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 816                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 817                         return -1;
 818                 }
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int
 825 i40evf_stop_queues(struct rte_eth_dev *dev)
 826 {
 827         int i;
 828
 829         /* Stop TX queues first */
 830         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 831                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 832                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 833                         return -1;
 834                 }
 835         }
 836
 837         /* Then stop RX queues */
 838         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 839                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 840                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 841                         return -1;
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847
 848 static void
 849 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 850                     struct ether_addr *addr,
 851                     __rte_unused uint32_t index,
 852                     __rte_unused uint32_t pool)
 853 {
 854         struct i40e_virtchnl_ether_addr_list *list;
 855         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 856         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 857                         sizeof(struct i40e_virtchnl_ether_addr)];
 858         int err;
 859         struct vf_cmd_info args;
 860
 861         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 862                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 863                             addr->addr_bytes[0], addr->addr_bytes[1],
 864                             addr->addr_bytes[2], addr->addr_bytes[3],
 865                             addr->addr_bytes[4], addr->addr_bytes[5]);
 866                 return;
 867         }
 868
 869         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 870         list->vsi_id = vf->vsi_res->vsi_id;
 871         list->num_elements = 1;
 872         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 873                                         sizeof(addr->addr_bytes));
 874
 875         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 876         args.in_args = cmd_buffer;
 877         args.in_args_size = sizeof(cmd_buffer);
 878         args.out_buffer = vf->aq_resp;
 879         args.out_size = I40E_AQ_BUF_SZ;
 880         err = i40evf_execute_vf_cmd(dev, &args);
 881         if (err)
 882                 PMD_DRV_LOG(ERR, "fail to execute command "
 883                             "OP_ADD_ETHER_ADDRESS");
 884
 885         return;
 886 }
 887
 888 static void
 889 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 890 {
 891         struct i40e_virtchnl_ether_addr_list *list;
 892         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 893         struct rte_eth_dev_data *data = dev->data;
 894         struct ether_addr *addr;
 895         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 896                         sizeof(struct i40e_virtchnl_ether_addr)];
 897         int err;
 898         struct vf_cmd_info args;
 899
 900         addr = &(data->mac_addrs[index]);
 901
 902         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 903                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 904                             addr->addr_bytes[0], addr->addr_bytes[1],
 905                             addr->addr_bytes[2], addr->addr_bytes[3],
 906                             addr->addr_bytes[4], addr->addr_bytes[5]);
 907                 return;
 908         }
 909
 910         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 911         list->vsi_id = vf->vsi_res->vsi_id;
 912         list->num_elements = 1;
 913         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 914                         sizeof(addr->addr_bytes));
 915
 916         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 917         args.in_args = cmd_buffer;
 918         args.in_args_size = sizeof(cmd_buffer);
 919         args.out_buffer = vf->aq_resp;
 920         args.out_size = I40E_AQ_BUF_SZ;
 921         err = i40evf_execute_vf_cmd(dev, &args);
 922         if (err)
 923                 PMD_DRV_LOG(ERR, "fail to execute command "
 924                             "OP_DEL_ETHER_ADDRESS");
 925         return;
 926 }
 927
 928 static int
 929 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 930 {
 931         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 932         struct i40e_virtchnl_queue_select q_stats;
 933         int err;
 934         struct vf_cmd_info args;
 935
 936         memset(&q_stats, 0, sizeof(q_stats));
 937         q_stats.vsi_id = vf->vsi_res->vsi_id;
 938         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 939         args.in_args = (u8 *)&q_stats;
 940         args.in_args_size = sizeof(q_stats);
 941         args.out_buffer = vf->aq_resp;
 942         args.out_size = I40E_AQ_BUF_SZ;
 943
 944         err = i40evf_execute_vf_cmd(dev, &args);
 945         if (err) {
 946                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 947                 *pstats = NULL;
 948                 return err;
 949         }
 950         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 951         return 0;
 952 }
 953
 954 static int
 955 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 956 {
 957         int ret;
 958         struct i40e_eth_stats *pstats = NULL;
 959
 960         ret = i40evf_update_stats(dev, &pstats);
 961         if (ret != 0)
 962                 return 0;
 963
 964         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 965                                                 pstats->rx_broadcast;
 966         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 967                                                 pstats->tx_unicast;
 968         stats->ierrors = pstats->rx_discards;
 969         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 970         stats->ibytes = pstats->rx_bytes;
 971         stats->obytes = pstats->tx_bytes;
 972
 973         return 0;
 974 }
 975
 976 static void
 977 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 978 {
 979         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 980         struct i40e_eth_stats *pstats = NULL;
 981
 982         /* read stat values to clear hardware registers */
 983         i40evf_update_stats(dev, &pstats);
 984
 985         /* set stats offset base on current values */
 986         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 987 }
 988
 989 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 990                                       struct rte_eth_xstat_name *xstats_names,
 991                                       __rte_unused unsigned limit)
 992 {
 993         unsigned i;
 994
 995         if (xstats_names != NULL)
 996                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 997                         snprintf(xstats_names[i].name,
 998                                 sizeof(xstats_names[i].name),
 999                                 "%s", rte_i40evf_stats_strings[i].name);
1000                 }
1001         return I40EVF_NB_XSTATS;
1002 }
1003
1004 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1005                                  struct rte_eth_xstat *xstats, unsigned n)
1006 {
1007         int ret;
1008         unsigned i;
1009         struct i40e_eth_stats *pstats = NULL;
1010
1011         if (n < I40EVF_NB_XSTATS)
1012                 return I40EVF_NB_XSTATS;
1013
1014         ret = i40evf_update_stats(dev, &pstats);
1015         if (ret != 0)
1016                 return 0;
1017
1018         if (!xstats)
1019                 return 0;
1020
1021         /* loop over xstats array and values from pstats */
1022         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1023                 xstats[i].id = i;
1024                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1025                         rte_i40evf_stats_strings[i].offset);
1026         }
1027
1028         return I40EVF_NB_XSTATS;
1029 }
1030
1031 static int
1032 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1033 {
1034         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1035         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1036         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1037                                                         sizeof(uint16_t)];
1038         int err;
1039         struct vf_cmd_info args;
1040
1041         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1042         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1043         vlan_list->num_elements = 1;
1044         vlan_list->vlan_id[0] = vlanid;
1045
1046         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1047         args.in_args = (u8 *)&cmd_buffer;
1048         args.in_args_size = sizeof(cmd_buffer);
1049         args.out_buffer = vf->aq_resp;
1050         args.out_size = I40E_AQ_BUF_SZ;
1051         err = i40evf_execute_vf_cmd(dev, &args);
1052         if (err)
1053                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1054
1055         return err;
1056 }
1057
1058 static int
1059 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1060 {
1061         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1062         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1063         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1064                                                         sizeof(uint16_t)];
1065         int err;
1066         struct vf_cmd_info args;
1067
1068         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1069         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1070         vlan_list->num_elements = 1;
1071         vlan_list->vlan_id[0] = vlanid;
1072
1073         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1074         args.in_args = (u8 *)&cmd_buffer;
1075         args.in_args_size = sizeof(cmd_buffer);
1076         args.out_buffer = vf->aq_resp;
1077         args.out_size = I40E_AQ_BUF_SZ;
1078         err = i40evf_execute_vf_cmd(dev, &args);
1079         if (err)
1080                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1081
1082         return err;
1083 }
1084
1085 static const struct rte_pci_id pci_id_i40evf_map[] = {
1086         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1087         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1088         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1089         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1090         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1091         { .vendor_id = 0, /* sentinel */ },
1092 };
1093
1094 static inline int
1095 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1096                                     struct rte_eth_link *link)
1097 {
1098         struct rte_eth_link *dst = &(dev->data->dev_link);
1099         struct rte_eth_link *src = link;
1100
1101         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1102                                         *(uint64_t *)src) == 0)
1103                 return -1;
1104
1105         return 0;
1106 }
1107
1108 /* Disable IRQ0 */
1109 static inline void
1110 i40evf_disable_irq0(struct i40e_hw *hw)
1111 {
1112         /* Disable all interrupt types */
1113         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1114         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1115                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1116         I40EVF_WRITE_FLUSH(hw);
1117 }
1118
1119 /* Enable IRQ0 */
1120 static inline void
1121 i40evf_enable_irq0(struct i40e_hw *hw)
1122 {
1123         /* Enable admin queue interrupt trigger */
1124         uint32_t val;
1125
1126         i40evf_disable_irq0(hw);
1127         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1128         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1129                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1130         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1131
1132         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1133                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1134                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1135                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1136
1137         I40EVF_WRITE_FLUSH(hw);
1138 }
1139
1140 static int
1141 i40evf_reset_vf(struct i40e_hw *hw)
1142 {
1143         int i, reset;
1144
1145         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1147                 return -1;
1148         }
1149         /**
1150           * After issuing vf reset command to pf, pf won't necessarily
1151           * reset vf, it depends on what state it exactly is. If it's not
1152           * initialized yet, it won't have vf reset since it's in a certain
1153           * state. If not, it will try to reset. Even vf is reset, pf will
1154           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1155           * it to ACTIVE. In this duration, vf may not catch the moment that
1156           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1157           */
1158         rte_delay_ms(200);
1159
1160         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1161                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1162                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1163                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1164                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1165                         break;
1166                 else
1167                         rte_delay_ms(50);
1168         }
1169
1170         if (i >= MAX_RESET_WAIT_CNT) {
1171                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1172                 return -1;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int
1179 i40evf_init_vf(struct rte_eth_dev *dev)
1180 {
1181         int i, err, bufsz;
1182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1184         struct ether_addr *p_mac_addr;
1185         uint16_t interval =
1186                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1187
1188         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1189         vf->dev_data = dev->data;
1190         err = i40e_set_mac_type(hw);
1191         if (err) {
1192                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1193                 goto err;
1194         }
1195
1196         i40e_init_adminq_parameter(hw);
1197         err = i40e_init_adminq(hw);
1198         if (err) {
1199                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1200                 goto err;
1201         }
1202
1203         /* Reset VF and wait until it's complete */
1204         if (i40evf_reset_vf(hw)) {
1205                 PMD_INIT_LOG(ERR, "reset NIC failed");
1206                 goto err_aq;
1207         }
1208
1209         /* VF reset, shutdown admin queue and initialize again */
1210         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1212                 return -1;
1213         }
1214
1215         i40e_init_adminq_parameter(hw);
1216         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1217                 PMD_INIT_LOG(ERR, "init_adminq failed");
1218                 return -1;
1219         }
1220         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1221         if (!vf->aq_resp) {
1222                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1223                         goto err_aq;
1224         }
1225         if (i40evf_check_api_version(dev) != 0) {
1226                 PMD_INIT_LOG(ERR, "check_api version failed");
1227                 goto err_aq;
1228         }
1229         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1230                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1231         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1232         if (!vf->vf_res) {
1233                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1234                         goto err_aq;
1235         }
1236
1237         if (i40evf_get_vf_resource(dev) != 0) {
1238                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1239                 goto err_alloc;
1240         }
1241
1242         /* got VF config message back from PF, now we can parse it */
1243         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1244                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1245                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1246         }
1247
1248         if (!vf->vsi_res) {
1249                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1250                 goto err_alloc;
1251         }
1252
1253         if (hw->mac.type == I40E_MAC_X722_VF)
1254                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1255         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1256         vf->vsi.type = vf->vsi_res->vsi_type;
1257         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1258         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1259
1260         /* Store the MAC address configured by host, or generate random one */
1261         p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1262         if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1263                 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1264         else
1265                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1266
1267         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1268         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1269                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1270                                (I40E_ITR_INDEX_DEFAULT <<
1271                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1272                                (interval <<
1273                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1274                 I40EVF_WRITE_FLUSH(hw);
1275         }
1276
1277         return 0;
1278
1279 err_alloc:
1280         rte_free(vf->vf_res);
1281 err_aq:
1282         i40e_shutdown_adminq(hw); /* ignore error */
1283 err:
1284         return -1;
1285 }
1286
1287 static int
1288 i40evf_uninit_vf(struct rte_eth_dev *dev)
1289 {
1290         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292
1293         PMD_INIT_FUNC_TRACE();
1294
1295         if (hw->adapter_stopped == 0)
1296                 i40evf_dev_close(dev);
1297         rte_free(vf->vf_res);
1298         vf->vf_res = NULL;
1299         rte_free(vf->aq_resp);
1300         vf->aq_resp = NULL;
1301
1302         return 0;
1303 }
1304
1305 static void
1306 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1307                            uint8_t *msg,
1308                            __rte_unused uint16_t msglen)
1309 {
1310         struct i40e_virtchnl_pf_event *pf_msg =
1311                         (struct i40e_virtchnl_pf_event *)msg;
1312         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1313
1314         switch (pf_msg->event) {
1315         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1316                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1317                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1318                 break;
1319         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1320                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1321                 vf->link_up = pf_msg->event_data.link_event.link_status;
1322                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1323                 break;
1324         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1325                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1326                 break;
1327         default:
1328                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1329                 break;
1330         }
1331 }
1332
1333 static void
1334 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1335 {
1336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1338         struct i40e_arq_event_info info;
1339         struct i40e_virtchnl_msg *v_msg;
1340         uint16_t pending, opcode;
1341         int ret;
1342
1343         info.buf_len = I40E_AQ_BUF_SZ;
1344         if (!vf->aq_resp) {
1345                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1346                 return;
1347         }
1348         info.msg_buf = vf->aq_resp;
1349         v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1350
1351         pending = 1;
1352         while (pending) {
1353                 ret = i40e_clean_arq_element(hw, &info, &pending);
1354
1355                 if (ret != I40E_SUCCESS) {
1356                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1357                                     "ret: %d", ret);
1358                         break;
1359                 }
1360                 opcode = rte_le_to_cpu_16(info.desc.opcode);
1361
1362                 switch (opcode) {
1363                 case i40e_aqc_opc_send_msg_to_vf:
1364                         if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1365                                 /* process event*/
1366                                 i40evf_handle_pf_event(dev, info.msg_buf,
1367                                                        info.msg_len);
1368                         else {
1369                                 /* read message and it's expected one */
1370                                 if (v_msg->v_opcode == vf->pend_cmd) {
1371                                         vf->cmd_retval = v_msg->v_retval;
1372                                         /* prevent compiler reordering */
1373                                         rte_compiler_barrier();
1374                                         _clear_cmd(vf);
1375                                 } else
1376                                         PMD_DRV_LOG(ERR, "command mismatch,"
1377                                                 "expect %u, get %u",
1378                                                 vf->pend_cmd, v_msg->v_opcode);
1379                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1380                                              " opcode = %d\n", v_msg->v_opcode);
1381                         }
1382                         break;
1383                 default:
1384                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1385                                     opcode);
1386                         break;
1387                 }
1388         }
1389 }
1390
1391 /**
1392  * Interrupt handler triggered by NIC  for handling
1393  * specific interrupt. Only adminq interrupt is processed in VF.
1394  *
1395  * @param handle
1396  *  Pointer to interrupt handle.
1397  * @param param
1398  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1399  *
1400  * @return
1401  *  void
1402  */
1403 static void
1404 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1405                              void *param)
1406 {
1407         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         uint32_t icr0;
1410
1411         i40evf_disable_irq0(hw);
1412
1413         /* read out interrupt causes */
1414         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1415
1416         /* No interrupt event indicated */
1417         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1418                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1419                 goto done;
1420         }
1421
1422         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1423                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1424                 i40evf_handle_aq_msg(dev);
1425         }
1426
1427         /* Link Status Change interrupt */
1428         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1429                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1430                                    " do nothing\n");
1431
1432 done:
1433         i40evf_enable_irq0(hw);
1434         rte_intr_enable(&dev->pci_dev->intr_handle);
1435 }
1436
1437 static int
1438 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1439 {
1440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1441                         eth_dev->data->dev_private);
1442         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         /* assign ops func pointer */
1447         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1448         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1449         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1450
1451         /*
1452          * For secondary processes, we don't initialise any further as primary
1453          * has already done this work.
1454          */
1455         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1456                 i40e_set_rx_function(eth_dev);
1457                 i40e_set_tx_function(eth_dev);
1458                 return 0;
1459         }
1460
1461         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1462
1463         hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1464         hw->device_id = eth_dev->pci_dev->id.device_id;
1465         hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1466         hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1467         hw->bus.device = eth_dev->pci_dev->addr.devid;
1468         hw->bus.func = eth_dev->pci_dev->addr.function;
1469         hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1470         hw->adapter_stopped = 0;
1471
1472         if(i40evf_init_vf(eth_dev) != 0) {
1473                 PMD_INIT_LOG(ERR, "Init vf failed");
1474                 return -1;
1475         }
1476
1477         /* register callback func to eal lib */
1478         rte_intr_callback_register(&pci_dev->intr_handle,
1479                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1480
1481         /* enable uio intr after callback register */
1482         rte_intr_enable(&pci_dev->intr_handle);
1483
1484         /* configure and enable device interrupt */
1485         i40evf_enable_irq0(hw);
1486
1487         /* copy mac addr */
1488         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1489                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1490                                         0);
1491         if (eth_dev->data->mac_addrs == NULL) {
1492                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1493                                 " store MAC addresses",
1494                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1495                 return -ENOMEM;
1496         }
1497         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1498                         &eth_dev->data->mac_addrs[0]);
1499
1500         return 0;
1501 }
1502
1503 static int
1504 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1505 {
1506         PMD_INIT_FUNC_TRACE();
1507
1508         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1509                 return -EPERM;
1510
1511         eth_dev->dev_ops = NULL;
1512         eth_dev->rx_pkt_burst = NULL;
1513         eth_dev->tx_pkt_burst = NULL;
1514
1515         if (i40evf_uninit_vf(eth_dev) != 0) {
1516                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1517                 return -1;
1518         }
1519
1520         rte_free(eth_dev->data->mac_addrs);
1521         eth_dev->data->mac_addrs = NULL;
1522
1523         return 0;
1524 }
1525 /*
1526  * virtual function driver struct
1527  */
1528 static struct eth_driver rte_i40evf_pmd = {
1529         .pci_drv = {
1530                 .id_table = pci_id_i40evf_map,
1531                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1532                 .probe = rte_eth_dev_pci_probe,
1533                 .remove = rte_eth_dev_pci_remove,
1534         },
1535         .eth_dev_init = i40evf_dev_init,
1536         .eth_dev_uninit = i40evf_dev_uninit,
1537         .dev_private_size = sizeof(struct i40e_adapter),
1538 };
1539
1540 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1541 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1542 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1543
1544 static int
1545 i40evf_dev_configure(struct rte_eth_dev *dev)
1546 {
1547         struct i40e_adapter *ad =
1548                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1549         struct rte_eth_conf *conf = &dev->data->dev_conf;
1550         struct i40e_vf *vf;
1551
1552         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1553          * allocation or vector Rx preconditions we will reset it.
1554          */
1555         ad->rx_bulk_alloc_allowed = true;
1556         ad->rx_vec_allowed = true;
1557         ad->tx_simple_allowed = true;
1558         ad->tx_vec_allowed = true;
1559
1560         /* For non-DPDK PF drivers, VF has no ability to disable HW
1561          * CRC strip, and is implicitly enabled by the PF.
1562          */
1563         if (!conf->rxmode.hw_strip_crc) {
1564                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1565                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1566                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1567                         /* Peer is running non-DPDK PF driver. */
1568                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1569                         return -EINVAL;
1570                 }
1571         }
1572
1573         return i40evf_init_vlan(dev);
1574 }
1575
1576 static int
1577 i40evf_init_vlan(struct rte_eth_dev *dev)
1578 {
1579         struct rte_eth_dev_data *data = dev->data;
1580         int ret;
1581
1582         /* Apply vlan offload setting */
1583         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1584
1585         /* Apply pvid setting */
1586         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1587                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1588         return ret;
1589 }
1590
1591 static void
1592 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1593 {
1594         bool enable_vlan_strip = 0;
1595         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1596         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1597
1598         /* Linux pf host doesn't support vlan offload yet */
1599         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1600                 /* Vlan stripping setting */
1601                 if (mask & ETH_VLAN_STRIP_MASK) {
1602                         /* Enable or disable VLAN stripping */
1603                         if (dev_conf->rxmode.hw_vlan_strip)
1604                                 enable_vlan_strip = 1;
1605                         else
1606                                 enable_vlan_strip = 0;
1607
1608                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1609                 }
1610         }
1611 }
1612
1613 static int
1614 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1615 {
1616         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1617         struct i40e_vsi_vlan_pvid_info info;
1618         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1619
1620         memset(&info, 0, sizeof(info));
1621         info.on = on;
1622
1623         /* Linux pf host don't support vlan offload yet */
1624         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1625                 if (info.on)
1626                         info.config.pvid = pvid;
1627                 else {
1628                         info.config.reject.tagged =
1629                                 dev_conf->txmode.hw_vlan_reject_tagged;
1630                         info.config.reject.untagged =
1631                                 dev_conf->txmode.hw_vlan_reject_untagged;
1632                 }
1633                 return i40evf_config_vlan_pvid(dev, &info);
1634         }
1635
1636         return 0;
1637 }
1638
1639 static int
1640 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1641 {
1642         struct i40e_rx_queue *rxq;
1643         int err = 0;
1644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645
1646         PMD_INIT_FUNC_TRACE();
1647
1648         if (rx_queue_id < dev->data->nb_rx_queues) {
1649                 rxq = dev->data->rx_queues[rx_queue_id];
1650
1651                 err = i40e_alloc_rx_queue_mbufs(rxq);
1652                 if (err) {
1653                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1654                         return err;
1655                 }
1656
1657                 rte_wmb();
1658
1659                 /* Init the RX tail register. */
1660                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1661                 I40EVF_WRITE_FLUSH(hw);
1662
1663                 /* Ready to switch the queue on */
1664                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1665
1666                 if (err)
1667                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1668                                     rx_queue_id);
1669                 else
1670                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1671         }
1672
1673         return err;
1674 }
1675
1676 static int
1677 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1678 {
1679         struct i40e_rx_queue *rxq;
1680         int err;
1681
1682         if (rx_queue_id < dev->data->nb_rx_queues) {
1683                 rxq = dev->data->rx_queues[rx_queue_id];
1684
1685                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1686
1687                 if (err) {
1688                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1689                                     rx_queue_id);
1690                         return err;
1691                 }
1692
1693                 i40e_rx_queue_release_mbufs(rxq);
1694                 i40e_reset_rx_queue(rxq);
1695                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static int
1702 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1703 {
1704         int err = 0;
1705
1706         PMD_INIT_FUNC_TRACE();
1707
1708         if (tx_queue_id < dev->data->nb_tx_queues) {
1709
1710                 /* Ready to switch the queue on */
1711                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1712
1713                 if (err)
1714                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1715                                     tx_queue_id);
1716                 else
1717                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1718         }
1719
1720         return err;
1721 }
1722
1723 static int
1724 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1725 {
1726         struct i40e_tx_queue *txq;
1727         int err;
1728
1729         if (tx_queue_id < dev->data->nb_tx_queues) {
1730                 txq = dev->data->tx_queues[tx_queue_id];
1731
1732                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1733
1734                 if (err) {
1735                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1736                                     tx_queue_id);
1737                         return err;
1738                 }
1739
1740                 i40e_tx_queue_release_mbufs(txq);
1741                 i40e_reset_tx_queue(txq);
1742                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1743         }
1744
1745         return 0;
1746 }
1747
1748 static int
1749 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1750 {
1751         int ret;
1752
1753         if (on)
1754                 ret = i40evf_add_vlan(dev, vlan_id);
1755         else
1756                 ret = i40evf_del_vlan(dev,vlan_id);
1757
1758         return ret;
1759 }
1760
1761 static int
1762 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1763 {
1764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765         struct rte_eth_dev_data *dev_data = dev->data;
1766         struct rte_pktmbuf_pool_private *mbp_priv;
1767         uint16_t buf_size, len;
1768
1769         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1770         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1771         I40EVF_WRITE_FLUSH(hw);
1772
1773         /* Calculate the maximum packet length allowed */
1774         mbp_priv = rte_mempool_get_priv(rxq->mp);
1775         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1776                                         RTE_PKTMBUF_HEADROOM);
1777         rxq->hs_mode = i40e_header_split_none;
1778         rxq->rx_hdr_len = 0;
1779         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1780         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1781         rxq->max_pkt_len = RTE_MIN(len,
1782                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1783
1784         /**
1785          * Check if the jumbo frame and maximum packet length are set correctly
1786          */
1787         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1788                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1789                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1790                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1791                                 "larger than %u and smaller than %u, as jumbo "
1792                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1793                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1794                         return I40E_ERR_CONFIG;
1795                 }
1796         } else {
1797                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1798                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1799                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1800                                 "larger than %u and smaller than %u, as jumbo "
1801                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1802                                                 (uint32_t)ETHER_MAX_LEN);
1803                         return I40E_ERR_CONFIG;
1804                 }
1805         }
1806
1807         if (dev_data->dev_conf.rxmode.enable_scatter ||
1808             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1809                 dev_data->scattered_rx = 1;
1810         }
1811
1812         return 0;
1813 }
1814
1815 static int
1816 i40evf_rx_init(struct rte_eth_dev *dev)
1817 {
1818         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1819         uint16_t i;
1820         int ret = I40E_SUCCESS;
1821         struct i40e_rx_queue **rxq =
1822                 (struct i40e_rx_queue **)dev->data->rx_queues;
1823
1824         i40evf_config_rss(vf);
1825         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1826                 if (!rxq[i] || !rxq[i]->q_set)
1827                         continue;
1828                 ret = i40evf_rxq_init(dev, rxq[i]);
1829                 if (ret != I40E_SUCCESS)
1830                         break;
1831         }
1832         if (ret == I40E_SUCCESS)
1833                 i40e_set_rx_function(dev);
1834
1835         return ret;
1836 }
1837
1838 static void
1839 i40evf_tx_init(struct rte_eth_dev *dev)
1840 {
1841         uint16_t i;
1842         struct i40e_tx_queue **txq =
1843                 (struct i40e_tx_queue **)dev->data->tx_queues;
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845
1846         for (i = 0; i < dev->data->nb_tx_queues; i++)
1847                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1848
1849         i40e_set_tx_function(dev);
1850 }
1851
1852 static inline void
1853 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1854 {
1855         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1858
1859         if (!rte_intr_allow_others(intr_handle)) {
1860                 I40E_WRITE_REG(hw,
1861                                I40E_VFINT_DYN_CTL01,
1862                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1863                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1864                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1865                 I40EVF_WRITE_FLUSH(hw);
1866                 return;
1867         }
1868
1869         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1870                 /* To support DPDK PF host */
1871                 I40E_WRITE_REG(hw,
1872                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1873                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1874                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1875         /* If host driver is kernel driver, do nothing.
1876          * Interrupt 0 is used for rx packets, but don't set
1877          * I40E_VFINT_DYN_CTL01,
1878          * because it is already done in i40evf_enable_irq0.
1879          */
1880
1881         I40EVF_WRITE_FLUSH(hw);
1882 }
1883
1884 static inline void
1885 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1886 {
1887         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1890
1891         if (!rte_intr_allow_others(intr_handle)) {
1892                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1893                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1894                 I40EVF_WRITE_FLUSH(hw);
1895                 return;
1896         }
1897
1898         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1899                 I40E_WRITE_REG(hw,
1900                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1901                                                     - 1),
1902                                0);
1903         /* If host driver is kernel driver, do nothing.
1904          * Interrupt 0 is used for rx packets, but don't zero
1905          * I40E_VFINT_DYN_CTL01,
1906          * because interrupt 0 is also used for adminq processing.
1907          */
1908
1909         I40EVF_WRITE_FLUSH(hw);
1910 }
1911
1912 static int
1913 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1914 {
1915         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         uint16_t interval =
1918                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1919         uint16_t msix_intr;
1920
1921         msix_intr = intr_handle->intr_vec[queue_id];
1922         if (msix_intr == I40E_MISC_VEC_ID)
1923                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1924                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1925                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1926                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1927                                (interval <<
1928                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1929         else
1930                 I40E_WRITE_REG(hw,
1931                                I40E_VFINT_DYN_CTLN1(msix_intr -
1932                                                     I40E_RX_VEC_START),
1933                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1934                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1935                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1936                                (interval <<
1937                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1938
1939         I40EVF_WRITE_FLUSH(hw);
1940
1941         rte_intr_enable(&dev->pci_dev->intr_handle);
1942
1943         return 0;
1944 }
1945
1946 static int
1947 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1948 {
1949         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         uint16_t msix_intr;
1952
1953         msix_intr = intr_handle->intr_vec[queue_id];
1954         if (msix_intr == I40E_MISC_VEC_ID)
1955                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1956         else
1957                 I40E_WRITE_REG(hw,
1958                                I40E_VFINT_DYN_CTLN1(msix_intr -
1959                                                     I40E_RX_VEC_START),
1960                                0);
1961
1962         I40EVF_WRITE_FLUSH(hw);
1963
1964         return 0;
1965 }
1966
1967 static void
1968 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1969 {
1970         struct i40e_virtchnl_ether_addr_list *list;
1971         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1972         int err, i, j;
1973         int next_begin = 0;
1974         int begin = 0;
1975         uint32_t len;
1976         struct ether_addr *addr;
1977         struct vf_cmd_info args;
1978
1979         do {
1980                 j = 0;
1981                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1982                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1983                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1984                                 continue;
1985                         len += sizeof(struct i40e_virtchnl_ether_addr);
1986                         if (len >= I40E_AQ_BUF_SZ) {
1987                                 next_begin = i + 1;
1988                                 break;
1989                         }
1990                 }
1991
1992                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1993
1994                 for (i = begin; i < next_begin; i++) {
1995                         addr = &dev->data->mac_addrs[i];
1996                         if (is_zero_ether_addr(addr))
1997                                 continue;
1998                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
1999                                          sizeof(addr->addr_bytes));
2000                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2001                                     addr->addr_bytes[0], addr->addr_bytes[1],
2002                                     addr->addr_bytes[2], addr->addr_bytes[3],
2003                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2004                         j++;
2005                 }
2006                 list->vsi_id = vf->vsi_res->vsi_id;
2007                 list->num_elements = j;
2008                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2009                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2010                 args.in_args = (uint8_t *)list;
2011                 args.in_args_size = len;
2012                 args.out_buffer = vf->aq_resp;
2013                 args.out_size = I40E_AQ_BUF_SZ;
2014                 err = i40evf_execute_vf_cmd(dev, &args);
2015                 if (err)
2016                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2017                                     add ? "OP_ADD_ETHER_ADDRESS" :
2018                                     "OP_DEL_ETHER_ADDRESS");
2019                 rte_free(list);
2020                 begin = next_begin;
2021         } while (begin < I40E_NUM_MACADDR_MAX);
2022 }
2023
2024 static int
2025 i40evf_dev_start(struct rte_eth_dev *dev)
2026 {
2027         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2030         uint32_t intr_vector = 0;
2031
2032         PMD_INIT_FUNC_TRACE();
2033
2034         hw->adapter_stopped = 0;
2035
2036         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2037         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2038                                         dev->data->nb_tx_queues);
2039
2040         /* check and configure queue intr-vector mapping */
2041         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2042                 intr_vector = dev->data->nb_rx_queues;
2043                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2044                         return -1;
2045         }
2046
2047         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2048                 intr_handle->intr_vec =
2049                         rte_zmalloc("intr_vec",
2050                                     dev->data->nb_rx_queues * sizeof(int), 0);
2051                 if (!intr_handle->intr_vec) {
2052                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2053                                      " intr_vec\n", dev->data->nb_rx_queues);
2054                         return -ENOMEM;
2055                 }
2056         }
2057
2058         if (i40evf_rx_init(dev) != 0){
2059                 PMD_DRV_LOG(ERR, "failed to do RX init");
2060                 return -1;
2061         }
2062
2063         i40evf_tx_init(dev);
2064
2065         if (i40evf_configure_queues(dev) != 0) {
2066                 PMD_DRV_LOG(ERR, "configure queues failed");
2067                 goto err_queue;
2068         }
2069         if (i40evf_config_irq_map(dev)) {
2070                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2071                 goto err_queue;
2072         }
2073
2074         /* Set all mac addrs */
2075         i40evf_add_del_all_mac_addr(dev, TRUE);
2076
2077         if (i40evf_start_queues(dev) != 0) {
2078                 PMD_DRV_LOG(ERR, "enable queues failed");
2079                 goto err_mac;
2080         }
2081
2082         i40evf_enable_queues_intr(dev);
2083         return 0;
2084
2085 err_mac:
2086         i40evf_add_del_all_mac_addr(dev, FALSE);
2087 err_queue:
2088         return -1;
2089 }
2090
2091 static void
2092 i40evf_dev_stop(struct rte_eth_dev *dev)
2093 {
2094         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2095
2096         PMD_INIT_FUNC_TRACE();
2097
2098         i40evf_stop_queues(dev);
2099         i40evf_disable_queues_intr(dev);
2100         i40e_dev_clear_queues(dev);
2101
2102         /* Clean datapath event and queue/vec mapping */
2103         rte_intr_efd_disable(intr_handle);
2104         if (intr_handle->intr_vec) {
2105                 rte_free(intr_handle->intr_vec);
2106                 intr_handle->intr_vec = NULL;
2107         }
2108         /* remove all mac addrs */
2109         i40evf_add_del_all_mac_addr(dev, FALSE);
2110
2111 }
2112
2113 static int
2114 i40evf_dev_link_update(struct rte_eth_dev *dev,
2115                        __rte_unused int wait_to_complete)
2116 {
2117         struct rte_eth_link new_link;
2118         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2119         /*
2120          * DPDK pf host provide interfacet to acquire link status
2121          * while Linux driver does not
2122          */
2123
2124         /* Linux driver PF host */
2125         switch (vf->link_speed) {
2126         case I40E_LINK_SPEED_100MB:
2127                 new_link.link_speed = ETH_SPEED_NUM_100M;
2128                 break;
2129         case I40E_LINK_SPEED_1GB:
2130                 new_link.link_speed = ETH_SPEED_NUM_1G;
2131                 break;
2132         case I40E_LINK_SPEED_10GB:
2133                 new_link.link_speed = ETH_SPEED_NUM_10G;
2134                 break;
2135         case I40E_LINK_SPEED_20GB:
2136                 new_link.link_speed = ETH_SPEED_NUM_20G;
2137                 break;
2138         case I40E_LINK_SPEED_40GB:
2139                 new_link.link_speed = ETH_SPEED_NUM_40G;
2140                 break;
2141         default:
2142                 new_link.link_speed = ETH_SPEED_NUM_100M;
2143                 break;
2144         }
2145         /* full duplex only */
2146         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2147         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2148                                              ETH_LINK_DOWN;
2149
2150         i40evf_dev_atomic_write_link_status(dev, &new_link);
2151
2152         return 0;
2153 }
2154
2155 static void
2156 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2157 {
2158         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2159         int ret;
2160
2161         /* If enabled, just return */
2162         if (vf->promisc_unicast_enabled)
2163                 return;
2164
2165         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2166         if (ret == 0)
2167                 vf->promisc_unicast_enabled = TRUE;
2168 }
2169
2170 static void
2171 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2172 {
2173         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2174         int ret;
2175
2176         /* If disabled, just return */
2177         if (!vf->promisc_unicast_enabled)
2178                 return;
2179
2180         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2181         if (ret == 0)
2182                 vf->promisc_unicast_enabled = FALSE;
2183 }
2184
2185 static void
2186 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2187 {
2188         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2189         int ret;
2190
2191         /* If enabled, just return */
2192         if (vf->promisc_multicast_enabled)
2193                 return;
2194
2195         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2196         if (ret == 0)
2197                 vf->promisc_multicast_enabled = TRUE;
2198 }
2199
2200 static void
2201 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2202 {
2203         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2204         int ret;
2205
2206         /* If enabled, just return */
2207         if (!vf->promisc_multicast_enabled)
2208                 return;
2209
2210         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2211         if (ret == 0)
2212                 vf->promisc_multicast_enabled = FALSE;
2213 }
2214
2215 static void
2216 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2217 {
2218         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2219
2220         memset(dev_info, 0, sizeof(*dev_info));
2221         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2222         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2223         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2224         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2225         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2226         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2227         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2228         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2229         dev_info->rx_offload_capa =
2230                 DEV_RX_OFFLOAD_VLAN_STRIP |
2231                 DEV_RX_OFFLOAD_QINQ_STRIP |
2232                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2233                 DEV_RX_OFFLOAD_UDP_CKSUM |
2234                 DEV_RX_OFFLOAD_TCP_CKSUM;
2235         dev_info->tx_offload_capa =
2236                 DEV_TX_OFFLOAD_VLAN_INSERT |
2237                 DEV_TX_OFFLOAD_QINQ_INSERT |
2238                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2239                 DEV_TX_OFFLOAD_UDP_CKSUM |
2240                 DEV_TX_OFFLOAD_TCP_CKSUM |
2241                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2242
2243         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2244                 .rx_thresh = {
2245                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2246                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2247                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2248                 },
2249                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2250                 .rx_drop_en = 0,
2251         };
2252
2253         dev_info->default_txconf = (struct rte_eth_txconf) {
2254                 .tx_thresh = {
2255                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2256                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2257                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2258                 },
2259                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2260                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2261                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2262                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2263         };
2264
2265         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2266                 .nb_max = I40E_MAX_RING_DESC,
2267                 .nb_min = I40E_MIN_RING_DESC,
2268                 .nb_align = I40E_ALIGN_RING_DESC,
2269         };
2270
2271         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2272                 .nb_max = I40E_MAX_RING_DESC,
2273                 .nb_min = I40E_MIN_RING_DESC,
2274                 .nb_align = I40E_ALIGN_RING_DESC,
2275         };
2276 }
2277
2278 static void
2279 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2280 {
2281         if (i40evf_get_statics(dev, stats))
2282                 PMD_DRV_LOG(ERR, "Get statics failed");
2283 }
2284
2285 static void
2286 i40evf_dev_close(struct rte_eth_dev *dev)
2287 {
2288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         struct rte_pci_device *pci_dev = dev->pci_dev;
2290
2291         i40evf_dev_stop(dev);
2292         hw->adapter_stopped = 1;
2293         i40e_dev_free_queues(dev);
2294         i40evf_reset_vf(hw);
2295         i40e_shutdown_adminq(hw);
2296         /* disable uio intr before callback unregister */
2297         rte_intr_disable(&pci_dev->intr_handle);
2298
2299         /* unregister callback func from eal lib */
2300         rte_intr_callback_unregister(&pci_dev->intr_handle,
2301                 i40evf_dev_interrupt_handler, (void *)dev);
2302         i40evf_disable_irq0(hw);
2303 }
2304
2305 static int
2306 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2307 {
2308         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2309         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2310         int ret;
2311
2312         if (!lut)
2313                 return -EINVAL;
2314
2315         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2316                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2317                                           lut, lut_size);
2318                 if (ret) {
2319                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2320                         return ret;
2321                 }
2322         } else {
2323                 uint32_t *lut_dw = (uint32_t *)lut;
2324                 uint16_t i, lut_size_dw = lut_size / 4;
2325
2326                 for (i = 0; i < lut_size_dw; i++)
2327                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2328         }
2329
2330         return 0;
2331 }
2332
2333 static int
2334 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2335 {
2336         struct i40e_vf *vf;
2337         struct i40e_hw *hw;
2338         int ret;
2339
2340         if (!vsi || !lut)
2341                 return -EINVAL;
2342
2343         vf = I40E_VSI_TO_VF(vsi);
2344         hw = I40E_VSI_TO_HW(vsi);
2345
2346         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2347                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2348                                           lut, lut_size);
2349                 if (ret) {
2350                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2351                         return ret;
2352                 }
2353         } else {
2354                 uint32_t *lut_dw = (uint32_t *)lut;
2355                 uint16_t i, lut_size_dw = lut_size / 4;
2356
2357                 for (i = 0; i < lut_size_dw; i++)
2358                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2359                 I40EVF_WRITE_FLUSH(hw);
2360         }
2361
2362         return 0;
2363 }
2364
2365 static int
2366 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2367                            struct rte_eth_rss_reta_entry64 *reta_conf,
2368                            uint16_t reta_size)
2369 {
2370         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2371         uint8_t *lut;
2372         uint16_t i, idx, shift;
2373         int ret;
2374
2375         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2376                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2377                         "(%d) doesn't match the number of hardware can "
2378                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2379                 return -EINVAL;
2380         }
2381
2382         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2383         if (!lut) {
2384                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2385                 return -ENOMEM;
2386         }
2387         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2388         if (ret)
2389                 goto out;
2390         for (i = 0; i < reta_size; i++) {
2391                 idx = i / RTE_RETA_GROUP_SIZE;
2392                 shift = i % RTE_RETA_GROUP_SIZE;
2393                 if (reta_conf[idx].mask & (1ULL << shift))
2394                         lut[i] = reta_conf[idx].reta[shift];
2395         }
2396         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2397
2398 out:
2399         rte_free(lut);
2400
2401         return ret;
2402 }
2403
2404 static int
2405 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2406                           struct rte_eth_rss_reta_entry64 *reta_conf,
2407                           uint16_t reta_size)
2408 {
2409         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2410         uint16_t i, idx, shift;
2411         uint8_t *lut;
2412         int ret;
2413
2414         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2415                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2416                         "(%d) doesn't match the number of hardware can "
2417                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2418                 return -EINVAL;
2419         }
2420
2421         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2422         if (!lut) {
2423                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2424                 return -ENOMEM;
2425         }
2426
2427         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2428         if (ret)
2429                 goto out;
2430         for (i = 0; i < reta_size; i++) {
2431                 idx = i / RTE_RETA_GROUP_SIZE;
2432                 shift = i % RTE_RETA_GROUP_SIZE;
2433                 if (reta_conf[idx].mask & (1ULL << shift))
2434                         reta_conf[idx].reta[shift] = lut[i];
2435         }
2436
2437 out:
2438         rte_free(lut);
2439
2440         return ret;
2441 }
2442
2443 static int
2444 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2445 {
2446         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2448         int ret = 0;
2449
2450         if (!key || key_len == 0) {
2451                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2452                 return 0;
2453         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2454                 sizeof(uint32_t)) {
2455                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2456                 return -EINVAL;
2457         }
2458
2459         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2460                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2461                         (struct i40e_aqc_get_set_rss_key_data *)key;
2462
2463                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2464                 if (ret)
2465                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2466                                      "via AQ");
2467         } else {
2468                 uint32_t *hash_key = (uint32_t *)key;
2469                 uint16_t i;
2470
2471                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2472                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2473                 I40EVF_WRITE_FLUSH(hw);
2474         }
2475
2476         return ret;
2477 }
2478
2479 static int
2480 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2481 {
2482         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2483         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2484         int ret;
2485
2486         if (!key || !key_len)
2487                 return -EINVAL;
2488
2489         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2490                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2491                         (struct i40e_aqc_get_set_rss_key_data *)key);
2492                 if (ret) {
2493                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2494                         return ret;
2495                 }
2496         } else {
2497                 uint32_t *key_dw = (uint32_t *)key;
2498                 uint16_t i;
2499
2500                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2501                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2502         }
2503         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2504
2505         return 0;
2506 }
2507
2508 static int
2509 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2510 {
2511         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2512         uint64_t rss_hf, hena;
2513         int ret;
2514
2515         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2516                                  rss_conf->rss_key_len);
2517         if (ret)
2518                 return ret;
2519
2520         rss_hf = rss_conf->rss_hf;
2521         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2522         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2523         if (hw->mac.type == I40E_MAC_X722)
2524                 hena &= ~I40E_RSS_HENA_ALL_X722;
2525         else
2526                 hena &= ~I40E_RSS_HENA_ALL;
2527         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2528         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2529         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2530         I40EVF_WRITE_FLUSH(hw);
2531
2532         return 0;
2533 }
2534
2535 static void
2536 i40evf_disable_rss(struct i40e_vf *vf)
2537 {
2538         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2539         uint64_t hena;
2540
2541         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2542         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2543         if (hw->mac.type == I40E_MAC_X722)
2544                 hena &= ~I40E_RSS_HENA_ALL_X722;
2545         else
2546                 hena &= ~I40E_RSS_HENA_ALL;
2547         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2548         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2549         I40EVF_WRITE_FLUSH(hw);
2550 }
2551
2552 static int
2553 i40evf_config_rss(struct i40e_vf *vf)
2554 {
2555         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2556         struct rte_eth_rss_conf rss_conf;
2557         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2558         uint16_t num;
2559
2560         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2561                 i40evf_disable_rss(vf);
2562                 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2563                 return 0;
2564         }
2565
2566         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2567         /* Fill out the look up table */
2568         for (i = 0, j = 0; i < nb_q; i++, j++) {
2569                 if (j >= num)
2570                         j = 0;
2571                 lut = (lut << 8) | j;
2572                 if ((i & 3) == 3)
2573                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2574         }
2575
2576         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2577         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2578                 i40evf_disable_rss(vf);
2579                 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2580                 return 0;
2581         }
2582
2583         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2584                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2585                 /* Calculate the default hash key */
2586                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2587                         rss_key_default[i] = (uint32_t)rte_rand();
2588                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2589                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2590                         sizeof(uint32_t);
2591         }
2592
2593         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2594 }
2595
2596 static int
2597 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2598                            struct rte_eth_rss_conf *rss_conf)
2599 {
2600         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2603         uint64_t hena;
2604
2605         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2606         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2607         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2608                  ? I40E_RSS_HENA_ALL_X722
2609                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2610                 if (rss_hf != 0) /* Enable RSS */
2611                         return -EINVAL;
2612                 return 0;
2613         }
2614
2615         /* RSS enabled */
2616         if (rss_hf == 0) /* Disable RSS */
2617                 return -EINVAL;
2618
2619         return i40evf_hw_rss_hash_set(vf, rss_conf);
2620 }
2621
2622 static int
2623 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2624                              struct rte_eth_rss_conf *rss_conf)
2625 {
2626         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         uint64_t hena;
2629
2630         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2631                            &rss_conf->rss_key_len);
2632
2633         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2634         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2635         rss_conf->rss_hf = i40e_parse_hena(hena);
2636
2637         return 0;
2638 }