1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set,
141 uint32_t nb_mc_addr);
143 /* Default hash key buffer for RSS */
144 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
146 struct rte_i40evf_xstats_name_off {
147 char name[RTE_ETH_XSTATS_NAME_SIZE];
151 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
152 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
153 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
154 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
155 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
156 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
157 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
158 rx_unknown_protocol)},
159 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
160 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
161 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
162 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
163 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
164 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
167 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
168 sizeof(rte_i40evf_stats_strings[0]))
170 static const struct eth_dev_ops i40evf_eth_dev_ops = {
171 .dev_configure = i40evf_dev_configure,
172 .dev_start = i40evf_dev_start,
173 .dev_stop = i40evf_dev_stop,
174 .promiscuous_enable = i40evf_dev_promiscuous_enable,
175 .promiscuous_disable = i40evf_dev_promiscuous_disable,
176 .allmulticast_enable = i40evf_dev_allmulticast_enable,
177 .allmulticast_disable = i40evf_dev_allmulticast_disable,
178 .link_update = i40evf_dev_link_update,
179 .stats_get = i40evf_dev_stats_get,
180 .stats_reset = i40evf_dev_xstats_reset,
181 .xstats_get = i40evf_dev_xstats_get,
182 .xstats_get_names = i40evf_dev_xstats_get_names,
183 .xstats_reset = i40evf_dev_xstats_reset,
184 .dev_close = i40evf_dev_close,
185 .dev_reset = i40evf_dev_reset,
186 .dev_infos_get = i40evf_dev_info_get,
187 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
188 .vlan_filter_set = i40evf_vlan_filter_set,
189 .vlan_offload_set = i40evf_vlan_offload_set,
190 .rx_queue_start = i40evf_dev_rx_queue_start,
191 .rx_queue_stop = i40evf_dev_rx_queue_stop,
192 .tx_queue_start = i40evf_dev_tx_queue_start,
193 .tx_queue_stop = i40evf_dev_tx_queue_stop,
194 .rx_queue_setup = i40e_dev_rx_queue_setup,
195 .rx_queue_release = i40e_dev_rx_queue_release,
196 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
197 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
198 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
199 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
200 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
201 .tx_queue_setup = i40e_dev_tx_queue_setup,
202 .tx_queue_release = i40e_dev_tx_queue_release,
203 .rx_queue_count = i40e_dev_rx_queue_count,
204 .rxq_info_get = i40e_rxq_info_get,
205 .txq_info_get = i40e_txq_info_get,
206 .mac_addr_add = i40evf_add_mac_addr,
207 .mac_addr_remove = i40evf_del_mac_addr,
208 .set_mc_addr_list = i40evf_set_mc_addr_list,
209 .reta_update = i40evf_dev_rss_reta_update,
210 .reta_query = i40evf_dev_rss_reta_query,
211 .rss_hash_update = i40evf_dev_rss_hash_update,
212 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
213 .mtu_set = i40evf_dev_mtu_set,
214 .mac_addr_set = i40evf_set_default_mac_addr,
218 * Read data in admin queue to get msg from pf driver
220 static enum i40evf_aq_result
221 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
223 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
224 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
225 struct i40e_arq_event_info event;
226 enum virtchnl_ops opcode;
227 enum i40e_status_code retval;
229 enum i40evf_aq_result result = I40EVF_MSG_NON;
231 event.buf_len = data->buf_len;
232 event.msg_buf = data->msg;
233 ret = i40e_clean_arq_element(hw, &event, NULL);
234 /* Can't read any msg from adminQ */
236 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
237 result = I40EVF_MSG_ERR;
241 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
242 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
244 if (opcode == VIRTCHNL_OP_EVENT) {
245 struct virtchnl_pf_event *vpe =
246 (struct virtchnl_pf_event *)event.msg_buf;
248 result = I40EVF_MSG_SYS;
249 switch (vpe->event) {
250 case VIRTCHNL_EVENT_LINK_CHANGE:
252 vpe->event_data.link_event.link_status;
254 vpe->event_data.link_event.link_speed;
255 vf->pend_msg |= PFMSG_LINK_CHANGE;
256 PMD_DRV_LOG(INFO, "Link status update:%s",
257 vf->link_up ? "up" : "down");
259 case VIRTCHNL_EVENT_RESET_IMPENDING:
261 vf->pend_msg |= PFMSG_RESET_IMPENDING;
262 PMD_DRV_LOG(INFO, "vf is reseting");
264 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
265 vf->dev_closed = true;
266 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
267 PMD_DRV_LOG(INFO, "PF driver closed");
270 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
271 __func__, vpe->event);
274 /* async reply msg on command issued by vf previously */
275 result = I40EVF_MSG_CMD;
276 /* Actual data length read from PF */
277 data->msg_len = event.msg_len;
280 data->result = retval;
287 * clear current command. Only call in case execute
288 * _atomic_set_cmd successfully.
291 _clear_cmd(struct i40e_vf *vf)
294 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
298 * Check there is pending cmd in execution. If none, set new command.
301 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
303 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
304 VIRTCHNL_OP_UNKNOWN, ops);
307 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
312 #define MAX_TRY_TIMES 200
313 #define ASQ_DELAY_MS 10
316 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
320 struct i40evf_arq_msg_info info;
321 enum i40evf_aq_result ret;
324 if (_atomic_set_cmd(vf, args->ops))
327 info.msg = args->out_buffer;
328 info.buf_len = args->out_size;
329 info.ops = VIRTCHNL_OP_UNKNOWN;
330 info.result = I40E_SUCCESS;
332 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
333 args->in_args, args->in_args_size, NULL);
335 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
341 case VIRTCHNL_OP_RESET_VF:
342 /*no need to process in this function */
345 case VIRTCHNL_OP_VERSION:
346 case VIRTCHNL_OP_GET_VF_RESOURCES:
347 /* for init adminq commands, need to poll the response */
350 ret = i40evf_read_pfmsg(dev, &info);
351 vf->cmd_retval = info.result;
352 if (ret == I40EVF_MSG_CMD) {
355 } else if (ret == I40EVF_MSG_ERR)
357 rte_delay_ms(ASQ_DELAY_MS);
358 /* If don't read msg or read sys event, continue */
359 } while (i++ < MAX_TRY_TIMES);
362 case VIRTCHNL_OP_REQUEST_QUEUES:
364 * ignore async reply, only wait for system message,
365 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
366 * if not, means request queues failed.
370 ret = i40evf_read_pfmsg(dev, &info);
371 vf->cmd_retval = info.result;
372 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
375 } else if (ret == I40EVF_MSG_ERR ||
376 ret == I40EVF_MSG_CMD) {
379 rte_delay_ms(ASQ_DELAY_MS);
380 /* If don't read msg or read sys event, continue */
381 } while (i++ < MAX_TRY_TIMES);
386 /* for other adminq in running time, waiting the cmd done flag */
389 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
393 rte_delay_ms(ASQ_DELAY_MS);
394 /* If don't read msg or read sys event, continue */
395 } while (i++ < MAX_TRY_TIMES);
396 /* If there's no response is received, clear command */
397 if (i >= MAX_TRY_TIMES) {
398 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
404 return err | vf->cmd_retval;
408 * Check API version with sync wait until version read or fail from admin queue
411 i40evf_check_api_version(struct rte_eth_dev *dev)
413 struct virtchnl_version_info version, *pver;
415 struct vf_cmd_info args;
416 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
418 version.major = VIRTCHNL_VERSION_MAJOR;
419 version.minor = VIRTCHNL_VERSION_MINOR;
421 args.ops = VIRTCHNL_OP_VERSION;
422 args.in_args = (uint8_t *)&version;
423 args.in_args_size = sizeof(version);
424 args.out_buffer = vf->aq_resp;
425 args.out_size = I40E_AQ_BUF_SZ;
427 err = i40evf_execute_vf_cmd(dev, &args);
429 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
433 pver = (struct virtchnl_version_info *)args.out_buffer;
434 vf->version_major = pver->major;
435 vf->version_minor = pver->minor;
436 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
437 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
438 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
440 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
441 vf->version_major, vf->version_minor,
442 VIRTCHNL_VERSION_MAJOR,
443 VIRTCHNL_VERSION_MINOR);
451 i40evf_get_vf_resource(struct rte_eth_dev *dev)
453 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
454 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
456 struct vf_cmd_info args;
459 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
460 args.out_buffer = vf->aq_resp;
461 args.out_size = I40E_AQ_BUF_SZ;
463 caps = VIRTCHNL_VF_OFFLOAD_L2 |
464 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
465 VIRTCHNL_VF_OFFLOAD_RSS_REG |
466 VIRTCHNL_VF_OFFLOAD_VLAN |
467 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
468 args.in_args = (uint8_t *)∩︀
469 args.in_args_size = sizeof(caps);
472 args.in_args_size = 0;
474 err = i40evf_execute_vf_cmd(dev, &args);
477 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
481 len = sizeof(struct virtchnl_vf_resource) +
482 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
484 rte_memcpy(vf->vf_res, args.out_buffer,
485 RTE_MIN(args.out_size, len));
486 i40e_vf_parse_hw_config(hw, vf->vf_res);
492 i40evf_config_promisc(struct rte_eth_dev *dev,
494 bool enable_multicast)
496 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
498 struct vf_cmd_info args;
499 struct virtchnl_promisc_info promisc;
502 promisc.vsi_id = vf->vsi_res->vsi_id;
505 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
507 if (enable_multicast)
508 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
510 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
511 args.in_args = (uint8_t *)&promisc;
512 args.in_args_size = sizeof(promisc);
513 args.out_buffer = vf->aq_resp;
514 args.out_size = I40E_AQ_BUF_SZ;
516 err = i40evf_execute_vf_cmd(dev, &args);
519 PMD_DRV_LOG(ERR, "fail to execute command "
520 "CONFIG_PROMISCUOUS_MODE");
525 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
527 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
528 struct vf_cmd_info args;
531 memset(&args, 0, sizeof(args));
532 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
534 args.in_args_size = 0;
535 args.out_buffer = vf->aq_resp;
536 args.out_size = I40E_AQ_BUF_SZ;
537 ret = i40evf_execute_vf_cmd(dev, &args);
539 PMD_DRV_LOG(ERR, "Failed to execute command of "
540 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
546 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
548 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
549 struct vf_cmd_info args;
552 memset(&args, 0, sizeof(args));
553 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
555 args.in_args_size = 0;
556 args.out_buffer = vf->aq_resp;
557 args.out_size = I40E_AQ_BUF_SZ;
558 ret = i40evf_execute_vf_cmd(dev, &args);
560 PMD_DRV_LOG(ERR, "Failed to execute command of "
561 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
567 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
571 struct i40e_tx_queue *txq)
573 txq_info->vsi_id = vsi_id;
574 txq_info->queue_id = queue_id;
575 if (queue_id < nb_txq) {
576 txq_info->ring_len = txq->nb_tx_desc;
577 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
582 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
586 uint32_t max_pkt_size,
587 struct i40e_rx_queue *rxq)
589 rxq_info->vsi_id = vsi_id;
590 rxq_info->queue_id = queue_id;
591 rxq_info->max_pkt_size = max_pkt_size;
592 if (queue_id < nb_rxq) {
593 rxq_info->ring_len = rxq->nb_rx_desc;
594 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
595 rxq_info->databuffer_size =
596 (rte_pktmbuf_data_room_size(rxq->mp) -
597 RTE_PKTMBUF_HEADROOM);
602 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
604 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
605 struct i40e_rx_queue **rxq =
606 (struct i40e_rx_queue **)dev->data->rx_queues;
607 struct i40e_tx_queue **txq =
608 (struct i40e_tx_queue **)dev->data->tx_queues;
609 struct virtchnl_vsi_queue_config_info *vc_vqci;
610 struct virtchnl_queue_pair_info *vc_qpi;
611 struct vf_cmd_info args;
612 uint16_t i, nb_qp = vf->num_queue_pairs;
613 const uint32_t size =
614 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
618 memset(buff, 0, sizeof(buff));
619 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
620 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
621 vc_vqci->num_queue_pairs = nb_qp;
623 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
624 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
625 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
626 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
627 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
628 vf->max_pkt_len, rxq[i]);
630 memset(&args, 0, sizeof(args));
631 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
632 args.in_args = (uint8_t *)vc_vqci;
633 args.in_args_size = size;
634 args.out_buffer = vf->aq_resp;
635 args.out_size = I40E_AQ_BUF_SZ;
636 ret = i40evf_execute_vf_cmd(dev, &args);
638 PMD_DRV_LOG(ERR, "Failed to execute command of "
639 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
645 i40evf_config_irq_map(struct rte_eth_dev *dev)
647 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
648 struct vf_cmd_info args;
649 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
650 sizeof(struct virtchnl_vector_map)];
651 struct virtchnl_irq_map_info *map_info;
652 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
653 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
657 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
658 rte_intr_allow_others(intr_handle))
659 vector_id = I40E_RX_VEC_START;
661 vector_id = I40E_MISC_VEC_ID;
663 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
664 map_info->num_vectors = 1;
665 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
666 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
667 /* Alway use default dynamic MSIX interrupt */
668 map_info->vecmap[0].vector_id = vector_id;
669 /* Don't map any tx queue */
670 map_info->vecmap[0].txq_map = 0;
671 map_info->vecmap[0].rxq_map = 0;
672 for (i = 0; i < dev->data->nb_rx_queues; i++) {
673 map_info->vecmap[0].rxq_map |= 1 << i;
674 if (rte_intr_dp_is_en(intr_handle))
675 intr_handle->intr_vec[i] = vector_id;
678 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
679 args.in_args = (u8 *)cmd_buffer;
680 args.in_args_size = sizeof(cmd_buffer);
681 args.out_buffer = vf->aq_resp;
682 args.out_size = I40E_AQ_BUF_SZ;
683 err = i40evf_execute_vf_cmd(dev, &args);
685 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
691 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
694 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
695 struct virtchnl_queue_select queue_select;
697 struct vf_cmd_info args;
698 memset(&queue_select, 0, sizeof(queue_select));
699 queue_select.vsi_id = vf->vsi_res->vsi_id;
702 queue_select.rx_queues |= 1 << qid;
704 queue_select.tx_queues |= 1 << qid;
707 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
709 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
710 args.in_args = (u8 *)&queue_select;
711 args.in_args_size = sizeof(queue_select);
712 args.out_buffer = vf->aq_resp;
713 args.out_size = I40E_AQ_BUF_SZ;
714 err = i40evf_execute_vf_cmd(dev, &args);
716 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
717 isrx ? "RX" : "TX", qid, on ? "on" : "off");
723 i40evf_start_queues(struct rte_eth_dev *dev)
725 struct rte_eth_dev_data *dev_data = dev->data;
727 struct i40e_rx_queue *rxq;
728 struct i40e_tx_queue *txq;
730 for (i = 0; i < dev->data->nb_rx_queues; i++) {
731 rxq = dev_data->rx_queues[i];
732 if (rxq->rx_deferred_start)
734 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
735 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
740 for (i = 0; i < dev->data->nb_tx_queues; i++) {
741 txq = dev_data->tx_queues[i];
742 if (txq->tx_deferred_start)
744 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
745 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
754 i40evf_stop_queues(struct rte_eth_dev *dev)
758 /* Stop TX queues first */
759 for (i = 0; i < dev->data->nb_tx_queues; i++) {
760 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
761 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
766 /* Then stop RX queues */
767 for (i = 0; i < dev->data->nb_rx_queues; i++) {
768 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
769 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
778 i40evf_add_mac_addr(struct rte_eth_dev *dev,
779 struct ether_addr *addr,
780 __rte_unused uint32_t index,
781 __rte_unused uint32_t pool)
783 struct virtchnl_ether_addr_list *list;
784 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
785 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
786 sizeof(struct virtchnl_ether_addr)];
788 struct vf_cmd_info args;
790 if (is_zero_ether_addr(addr)) {
791 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
792 addr->addr_bytes[0], addr->addr_bytes[1],
793 addr->addr_bytes[2], addr->addr_bytes[3],
794 addr->addr_bytes[4], addr->addr_bytes[5]);
795 return I40E_ERR_INVALID_MAC_ADDR;
798 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
799 list->vsi_id = vf->vsi_res->vsi_id;
800 list->num_elements = 1;
801 rte_memcpy(list->list[0].addr, addr->addr_bytes,
802 sizeof(addr->addr_bytes));
804 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
805 args.in_args = cmd_buffer;
806 args.in_args_size = sizeof(cmd_buffer);
807 args.out_buffer = vf->aq_resp;
808 args.out_size = I40E_AQ_BUF_SZ;
809 err = i40evf_execute_vf_cmd(dev, &args);
811 PMD_DRV_LOG(ERR, "fail to execute command "
812 "OP_ADD_ETHER_ADDRESS");
820 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
821 struct ether_addr *addr)
823 struct virtchnl_ether_addr_list *list;
824 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
825 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
826 sizeof(struct virtchnl_ether_addr)];
828 struct vf_cmd_info args;
830 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
831 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
832 addr->addr_bytes[0], addr->addr_bytes[1],
833 addr->addr_bytes[2], addr->addr_bytes[3],
834 addr->addr_bytes[4], addr->addr_bytes[5]);
838 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
839 list->vsi_id = vf->vsi_res->vsi_id;
840 list->num_elements = 1;
841 rte_memcpy(list->list[0].addr, addr->addr_bytes,
842 sizeof(addr->addr_bytes));
844 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
845 args.in_args = cmd_buffer;
846 args.in_args_size = sizeof(cmd_buffer);
847 args.out_buffer = vf->aq_resp;
848 args.out_size = I40E_AQ_BUF_SZ;
849 err = i40evf_execute_vf_cmd(dev, &args);
851 PMD_DRV_LOG(ERR, "fail to execute command "
852 "OP_DEL_ETHER_ADDRESS");
859 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
861 struct rte_eth_dev_data *data = dev->data;
862 struct ether_addr *addr;
864 addr = &data->mac_addrs[index];
866 i40evf_del_mac_addr_by_addr(dev, addr);
870 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
872 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
873 struct virtchnl_queue_select q_stats;
875 struct vf_cmd_info args;
877 memset(&q_stats, 0, sizeof(q_stats));
878 q_stats.vsi_id = vf->vsi_res->vsi_id;
879 args.ops = VIRTCHNL_OP_GET_STATS;
880 args.in_args = (u8 *)&q_stats;
881 args.in_args_size = sizeof(q_stats);
882 args.out_buffer = vf->aq_resp;
883 args.out_size = I40E_AQ_BUF_SZ;
885 err = i40evf_execute_vf_cmd(dev, &args);
887 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
891 *pstats = (struct i40e_eth_stats *)args.out_buffer;
896 i40evf_stat_update_48(uint64_t *offset,
899 if (*stat >= *offset)
900 *stat = *stat - *offset;
902 *stat = (uint64_t)((*stat +
903 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
905 *stat &= I40E_48_BIT_MASK;
909 i40evf_stat_update_32(uint64_t *offset,
912 if (*stat >= *offset)
913 *stat = (uint64_t)(*stat - *offset);
915 *stat = (uint64_t)((*stat +
916 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
920 i40evf_update_stats(struct i40e_vsi *vsi,
921 struct i40e_eth_stats *nes)
923 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
925 i40evf_stat_update_48(&oes->rx_bytes,
927 i40evf_stat_update_48(&oes->rx_unicast,
929 i40evf_stat_update_48(&oes->rx_multicast,
931 i40evf_stat_update_48(&oes->rx_broadcast,
933 i40evf_stat_update_32(&oes->rx_discards,
935 i40evf_stat_update_32(&oes->rx_unknown_protocol,
936 &nes->rx_unknown_protocol);
937 i40evf_stat_update_48(&oes->tx_bytes,
939 i40evf_stat_update_48(&oes->tx_unicast,
941 i40evf_stat_update_48(&oes->tx_multicast,
943 i40evf_stat_update_48(&oes->tx_broadcast,
945 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
946 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
950 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
953 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
954 struct i40e_eth_stats *pstats = NULL;
956 /* read stat values to clear hardware registers */
957 ret = i40evf_query_stats(dev, &pstats);
959 /* set stats offset base on current values */
961 vf->vsi.eth_stats_offset = *pstats;
964 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
965 struct rte_eth_xstat_name *xstats_names,
966 __rte_unused unsigned limit)
970 if (xstats_names != NULL)
971 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
972 snprintf(xstats_names[i].name,
973 sizeof(xstats_names[i].name),
974 "%s", rte_i40evf_stats_strings[i].name);
976 return I40EVF_NB_XSTATS;
979 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
980 struct rte_eth_xstat *xstats, unsigned n)
984 struct i40e_eth_stats *pstats = NULL;
985 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
986 struct i40e_vsi *vsi = &vf->vsi;
988 if (n < I40EVF_NB_XSTATS)
989 return I40EVF_NB_XSTATS;
991 ret = i40evf_query_stats(dev, &pstats);
998 i40evf_update_stats(vsi, pstats);
1000 /* loop over xstats array and values from pstats */
1001 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1003 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1004 rte_i40evf_stats_strings[i].offset);
1007 return I40EVF_NB_XSTATS;
1011 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1013 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1014 struct virtchnl_vlan_filter_list *vlan_list;
1015 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1018 struct vf_cmd_info args;
1020 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1021 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1022 vlan_list->num_elements = 1;
1023 vlan_list->vlan_id[0] = vlanid;
1025 args.ops = VIRTCHNL_OP_ADD_VLAN;
1026 args.in_args = (u8 *)&cmd_buffer;
1027 args.in_args_size = sizeof(cmd_buffer);
1028 args.out_buffer = vf->aq_resp;
1029 args.out_size = I40E_AQ_BUF_SZ;
1030 err = i40evf_execute_vf_cmd(dev, &args);
1032 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1038 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1040 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1041 struct virtchnl_vf_res_request vfres;
1042 struct vf_cmd_info args;
1045 vfres.num_queue_pairs = num;
1047 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1048 args.in_args = (u8 *)&vfres;
1049 args.in_args_size = sizeof(vfres);
1050 args.out_buffer = vf->aq_resp;
1051 args.out_size = I40E_AQ_BUF_SZ;
1052 err = i40evf_execute_vf_cmd(dev, &args);
1054 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1060 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1062 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1063 struct virtchnl_vlan_filter_list *vlan_list;
1064 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1067 struct vf_cmd_info args;
1069 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1070 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1071 vlan_list->num_elements = 1;
1072 vlan_list->vlan_id[0] = vlanid;
1074 args.ops = VIRTCHNL_OP_DEL_VLAN;
1075 args.in_args = (u8 *)&cmd_buffer;
1076 args.in_args_size = sizeof(cmd_buffer);
1077 args.out_buffer = vf->aq_resp;
1078 args.out_size = I40E_AQ_BUF_SZ;
1079 err = i40evf_execute_vf_cmd(dev, &args);
1081 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1086 static const struct rte_pci_id pci_id_i40evf_map[] = {
1087 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1088 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1089 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1090 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1091 { .vendor_id = 0, /* sentinel */ },
1096 i40evf_disable_irq0(struct i40e_hw *hw)
1098 /* Disable all interrupt types */
1099 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1100 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1101 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1102 I40EVF_WRITE_FLUSH(hw);
1107 i40evf_enable_irq0(struct i40e_hw *hw)
1109 /* Enable admin queue interrupt trigger */
1112 i40evf_disable_irq0(hw);
1113 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1114 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1115 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1116 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1118 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1119 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1120 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1121 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1123 I40EVF_WRITE_FLUSH(hw);
1127 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1130 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1133 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1134 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1135 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1136 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1137 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1138 reset == VIRTCHNL_VFR_COMPLETED)
1143 if (i >= MAX_RESET_WAIT_CNT)
1146 vf->vf_reset = false;
1147 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1152 i40evf_reset_vf(struct rte_eth_dev *dev)
1155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1157 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1158 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1162 * After issuing vf reset command to pf, pf won't necessarily
1163 * reset vf, it depends on what state it exactly is. If it's not
1164 * initialized yet, it won't have vf reset since it's in a certain
1165 * state. If not, it will try to reset. Even vf is reset, pf will
1166 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1167 * it to ACTIVE. In this duration, vf may not catch the moment that
1168 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1172 ret = i40evf_check_vf_reset_done(dev);
1174 PMD_INIT_LOG(ERR, "VF is still resetting");
1182 i40evf_init_vf(struct rte_eth_dev *dev)
1185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1188 i40e_calc_itr_interval(0, 0);
1190 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1191 vf->dev_data = dev->data;
1192 err = i40e_set_mac_type(hw);
1194 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1198 err = i40evf_check_vf_reset_done(dev);
1202 i40e_init_adminq_parameter(hw);
1203 err = i40e_init_adminq(hw);
1205 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1209 /* Reset VF and wait until it's complete */
1210 if (i40evf_reset_vf(dev)) {
1211 PMD_INIT_LOG(ERR, "reset NIC failed");
1215 /* VF reset, shutdown admin queue and initialize again */
1216 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1221 i40e_init_adminq_parameter(hw);
1222 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1223 PMD_INIT_LOG(ERR, "init_adminq failed");
1227 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1229 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1232 if (i40evf_check_api_version(dev) != 0) {
1233 PMD_INIT_LOG(ERR, "check_api version failed");
1236 bufsz = sizeof(struct virtchnl_vf_resource) +
1237 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1238 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1240 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1244 if (i40evf_get_vf_resource(dev) != 0) {
1245 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1249 /* got VF config message back from PF, now we can parse it */
1250 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1251 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1252 vf->vsi_res = &vf->vf_res->vsi_res[i];
1256 PMD_INIT_LOG(ERR, "no LAN VSI found");
1260 if (hw->mac.type == I40E_MAC_X722_VF)
1261 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1262 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1264 switch (vf->vsi_res->vsi_type) {
1265 case VIRTCHNL_VSI_SRIOV:
1266 vf->vsi.type = I40E_VSI_SRIOV;
1269 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1272 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1273 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1275 /* Store the MAC address configured by host, or generate random one */
1276 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1277 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1279 eth_random_addr(hw->mac.addr); /* Generate a random one */
1281 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1282 (I40E_ITR_INDEX_DEFAULT <<
1283 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1285 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1286 I40EVF_WRITE_FLUSH(hw);
1291 rte_free(vf->vf_res);
1294 rte_free(vf->aq_resp);
1296 i40e_shutdown_adminq(hw); /* ignore error */
1302 i40evf_uninit_vf(struct rte_eth_dev *dev)
1304 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1305 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 PMD_INIT_FUNC_TRACE();
1309 if (hw->adapter_closed == 0)
1310 i40evf_dev_close(dev);
1311 rte_free(vf->vf_res);
1313 rte_free(vf->aq_resp);
1320 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1321 __rte_unused uint16_t msglen)
1323 struct virtchnl_pf_event *pf_msg =
1324 (struct virtchnl_pf_event *)msg;
1325 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1327 switch (pf_msg->event) {
1328 case VIRTCHNL_EVENT_RESET_IMPENDING:
1329 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1330 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1333 case VIRTCHNL_EVENT_LINK_CHANGE:
1334 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1335 vf->link_up = pf_msg->event_data.link_event.link_status;
1336 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1338 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1339 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1342 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1348 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1350 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1352 struct i40e_arq_event_info info;
1353 uint16_t pending, aq_opc;
1354 enum virtchnl_ops msg_opc;
1355 enum i40e_status_code msg_ret;
1358 info.buf_len = I40E_AQ_BUF_SZ;
1360 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1363 info.msg_buf = vf->aq_resp;
1367 ret = i40e_clean_arq_element(hw, &info, &pending);
1369 if (ret != I40E_SUCCESS) {
1370 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1374 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1375 /* For the message sent from pf to vf, opcode is stored in
1376 * cookie_high of struct i40e_aq_desc, while return error code
1377 * are stored in cookie_low, Which is done by
1378 * i40e_aq_send_msg_to_vf in PF driver.*/
1379 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1380 info.desc.cookie_high);
1381 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1382 info.desc.cookie_low);
1384 case i40e_aqc_opc_send_msg_to_vf:
1385 if (msg_opc == VIRTCHNL_OP_EVENT)
1387 i40evf_handle_pf_event(dev, info.msg_buf,
1390 /* read message and it's expected one */
1391 if (msg_opc == vf->pend_cmd) {
1392 vf->cmd_retval = msg_ret;
1393 /* prevent compiler reordering */
1394 rte_compiler_barrier();
1397 PMD_DRV_LOG(ERR, "command mismatch,"
1398 "expect %u, get %u",
1399 vf->pend_cmd, msg_opc);
1400 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1401 " opcode = %d", msg_opc);
1405 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1413 * Interrupt handler triggered by NIC for handling
1414 * specific interrupt. Only adminq interrupt is processed in VF.
1417 * Pointer to interrupt handle.
1419 * The address of parameter (struct rte_eth_dev *) regsitered before.
1425 i40evf_dev_alarm_handler(void *param)
1427 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1428 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431 i40evf_disable_irq0(hw);
1433 /* read out interrupt causes */
1434 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1436 /* No interrupt event indicated */
1437 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1440 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1441 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1442 i40evf_handle_aq_msg(dev);
1445 /* Link Status Change interrupt */
1446 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1447 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1451 i40evf_enable_irq0(hw);
1452 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1453 i40evf_dev_alarm_handler, dev);
1457 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1460 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1461 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1463 PMD_INIT_FUNC_TRACE();
1465 /* assign ops func pointer */
1466 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1467 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1468 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1471 * For secondary processes, we don't initialise any further as primary
1472 * has already done this work.
1474 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1475 i40e_set_rx_function(eth_dev);
1476 i40e_set_tx_function(eth_dev);
1479 i40e_set_default_ptype_table(eth_dev);
1480 i40e_set_default_pctype_table(eth_dev);
1481 rte_eth_copy_pci_info(eth_dev, pci_dev);
1483 hw->vendor_id = pci_dev->id.vendor_id;
1484 hw->device_id = pci_dev->id.device_id;
1485 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1486 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1487 hw->bus.device = pci_dev->addr.devid;
1488 hw->bus.func = pci_dev->addr.function;
1489 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1490 hw->adapter_stopped = 0;
1491 hw->adapter_closed = 0;
1493 if(i40evf_init_vf(eth_dev) != 0) {
1494 PMD_INIT_LOG(ERR, "Init vf failed");
1498 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1499 i40evf_dev_alarm_handler, eth_dev);
1501 /* configure and enable device interrupt */
1502 i40evf_enable_irq0(hw);
1505 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1506 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1508 if (eth_dev->data->mac_addrs == NULL) {
1509 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1510 " store MAC addresses",
1511 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1514 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1515 ð_dev->data->mac_addrs[0]);
1521 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1523 PMD_INIT_FUNC_TRACE();
1525 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1528 eth_dev->dev_ops = NULL;
1529 eth_dev->rx_pkt_burst = NULL;
1530 eth_dev->tx_pkt_burst = NULL;
1532 if (i40evf_uninit_vf(eth_dev) != 0) {
1533 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1540 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1541 struct rte_pci_device *pci_dev)
1543 return rte_eth_dev_pci_generic_probe(pci_dev,
1544 sizeof(struct i40e_adapter), i40evf_dev_init);
1547 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1549 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1553 * virtual function driver struct
1555 static struct rte_pci_driver rte_i40evf_pmd = {
1556 .id_table = pci_id_i40evf_map,
1557 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1558 .probe = eth_i40evf_pci_probe,
1559 .remove = eth_i40evf_pci_remove,
1562 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1563 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1564 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1567 i40evf_dev_configure(struct rte_eth_dev *dev)
1569 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1570 struct i40e_adapter *ad =
1571 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1572 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1573 dev->data->nb_tx_queues);
1575 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1576 * allocation or vector Rx preconditions we will reset it.
1578 ad->rx_bulk_alloc_allowed = true;
1579 ad->rx_vec_allowed = true;
1580 ad->tx_simple_allowed = true;
1581 ad->tx_vec_allowed = true;
1583 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1586 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1587 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1588 ret = i40evf_request_queues(dev, num_queue_pairs);
1592 ret = i40evf_dev_reset(dev);
1597 return i40evf_init_vlan(dev);
1601 i40evf_init_vlan(struct rte_eth_dev *dev)
1603 /* Apply vlan offload setting */
1604 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1610 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1612 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1613 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1615 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1618 /* Vlan stripping setting */
1619 if (mask & ETH_VLAN_STRIP_MASK) {
1620 /* Enable or disable VLAN stripping */
1621 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1622 i40evf_enable_vlan_strip(dev);
1624 i40evf_disable_vlan_strip(dev);
1631 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1633 struct i40e_rx_queue *rxq;
1635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637 PMD_INIT_FUNC_TRACE();
1639 rxq = dev->data->rx_queues[rx_queue_id];
1641 err = i40e_alloc_rx_queue_mbufs(rxq);
1643 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1649 /* Init the RX tail register. */
1650 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1651 I40EVF_WRITE_FLUSH(hw);
1653 /* Ready to switch the queue on */
1654 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1656 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1660 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1666 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1668 struct i40e_rx_queue *rxq;
1671 rxq = dev->data->rx_queues[rx_queue_id];
1673 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1675 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1680 i40e_rx_queue_release_mbufs(rxq);
1681 i40e_reset_rx_queue(rxq);
1682 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1688 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1692 PMD_INIT_FUNC_TRACE();
1694 /* Ready to switch the queue on */
1695 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1697 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1701 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1707 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1709 struct i40e_tx_queue *txq;
1712 txq = dev->data->tx_queues[tx_queue_id];
1714 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1716 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1721 i40e_tx_queue_release_mbufs(txq);
1722 i40e_reset_tx_queue(txq);
1723 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1729 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1734 ret = i40evf_add_vlan(dev, vlan_id);
1736 ret = i40evf_del_vlan(dev,vlan_id);
1742 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745 struct rte_eth_dev_data *dev_data = dev->data;
1746 struct rte_pktmbuf_pool_private *mbp_priv;
1747 uint16_t buf_size, len;
1749 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1750 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1751 I40EVF_WRITE_FLUSH(hw);
1753 /* Calculate the maximum packet length allowed */
1754 mbp_priv = rte_mempool_get_priv(rxq->mp);
1755 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1756 RTE_PKTMBUF_HEADROOM);
1757 rxq->hs_mode = i40e_header_split_none;
1758 rxq->rx_hdr_len = 0;
1759 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1760 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1761 rxq->max_pkt_len = RTE_MIN(len,
1762 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1765 * Check if the jumbo frame and maximum packet length are set correctly
1767 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1768 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1769 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1770 PMD_DRV_LOG(ERR, "maximum packet length must be "
1771 "larger than %u and smaller than %u, as jumbo "
1772 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1773 (uint32_t)I40E_FRAME_SIZE_MAX);
1774 return I40E_ERR_CONFIG;
1777 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1778 rxq->max_pkt_len > ETHER_MAX_LEN) {
1779 PMD_DRV_LOG(ERR, "maximum packet length must be "
1780 "larger than %u and smaller than %u, as jumbo "
1781 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1782 (uint32_t)ETHER_MAX_LEN);
1783 return I40E_ERR_CONFIG;
1787 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1788 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1789 dev_data->scattered_rx = 1;
1796 i40evf_rx_init(struct rte_eth_dev *dev)
1798 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1800 int ret = I40E_SUCCESS;
1801 struct i40e_rx_queue **rxq =
1802 (struct i40e_rx_queue **)dev->data->rx_queues;
1804 i40evf_config_rss(vf);
1805 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1806 if (!rxq[i] || !rxq[i]->q_set)
1808 ret = i40evf_rxq_init(dev, rxq[i]);
1809 if (ret != I40E_SUCCESS)
1812 if (ret == I40E_SUCCESS)
1813 i40e_set_rx_function(dev);
1819 i40evf_tx_init(struct rte_eth_dev *dev)
1822 struct i40e_tx_queue **txq =
1823 (struct i40e_tx_queue **)dev->data->tx_queues;
1824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826 for (i = 0; i < dev->data->nb_tx_queues; i++)
1827 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1829 i40e_set_tx_function(dev);
1833 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1835 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1837 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1839 if (!rte_intr_allow_others(intr_handle)) {
1841 I40E_VFINT_DYN_CTL01,
1842 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1843 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1844 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1845 I40EVF_WRITE_FLUSH(hw);
1849 I40EVF_WRITE_FLUSH(hw);
1853 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1855 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1857 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1859 if (!rte_intr_allow_others(intr_handle)) {
1860 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1861 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1862 I40EVF_WRITE_FLUSH(hw);
1866 I40EVF_WRITE_FLUSH(hw);
1870 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1872 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1873 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 i40e_calc_itr_interval(0, 0);
1879 msix_intr = intr_handle->intr_vec[queue_id];
1880 if (msix_intr == I40E_MISC_VEC_ID)
1881 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1882 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1883 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1884 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1886 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1889 I40E_VFINT_DYN_CTLN1(msix_intr -
1891 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1892 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1893 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1895 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1897 I40EVF_WRITE_FLUSH(hw);
1903 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1905 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1906 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 msix_intr = intr_handle->intr_vec[queue_id];
1911 if (msix_intr == I40E_MISC_VEC_ID)
1912 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1915 I40E_VFINT_DYN_CTLN1(msix_intr -
1919 I40EVF_WRITE_FLUSH(hw);
1925 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1927 struct virtchnl_ether_addr_list *list;
1928 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1933 struct ether_addr *addr;
1934 struct vf_cmd_info args;
1938 len = sizeof(struct virtchnl_ether_addr_list);
1939 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1940 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1942 len += sizeof(struct virtchnl_ether_addr);
1943 if (len >= I40E_AQ_BUF_SZ) {
1949 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1951 PMD_DRV_LOG(ERR, "fail to allocate memory");
1955 for (i = begin; i < next_begin; i++) {
1956 addr = &dev->data->mac_addrs[i];
1957 if (is_zero_ether_addr(addr))
1959 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1960 sizeof(addr->addr_bytes));
1961 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1962 addr->addr_bytes[0], addr->addr_bytes[1],
1963 addr->addr_bytes[2], addr->addr_bytes[3],
1964 addr->addr_bytes[4], addr->addr_bytes[5]);
1967 list->vsi_id = vf->vsi_res->vsi_id;
1968 list->num_elements = j;
1969 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1970 VIRTCHNL_OP_DEL_ETH_ADDR;
1971 args.in_args = (uint8_t *)list;
1972 args.in_args_size = len;
1973 args.out_buffer = vf->aq_resp;
1974 args.out_size = I40E_AQ_BUF_SZ;
1975 err = i40evf_execute_vf_cmd(dev, &args);
1977 PMD_DRV_LOG(ERR, "fail to execute command %s",
1978 add ? "OP_ADD_ETHER_ADDRESS" :
1979 "OP_DEL_ETHER_ADDRESS");
1988 } while (begin < I40E_NUM_MACADDR_MAX);
1992 i40evf_dev_start(struct rte_eth_dev *dev)
1994 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1995 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1997 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1998 uint32_t intr_vector = 0;
2000 PMD_INIT_FUNC_TRACE();
2002 hw->adapter_stopped = 0;
2004 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2005 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2006 dev->data->nb_tx_queues);
2008 /* check and configure queue intr-vector mapping */
2009 if (rte_intr_cap_multiple(intr_handle) &&
2010 dev->data->dev_conf.intr_conf.rxq) {
2011 intr_vector = dev->data->nb_rx_queues;
2012 if (rte_intr_efd_enable(intr_handle, intr_vector))
2016 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2017 intr_handle->intr_vec =
2018 rte_zmalloc("intr_vec",
2019 dev->data->nb_rx_queues * sizeof(int), 0);
2020 if (!intr_handle->intr_vec) {
2021 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2022 " intr_vec", dev->data->nb_rx_queues);
2027 if (i40evf_rx_init(dev) != 0){
2028 PMD_DRV_LOG(ERR, "failed to do RX init");
2032 i40evf_tx_init(dev);
2034 if (i40evf_configure_vsi_queues(dev) != 0) {
2035 PMD_DRV_LOG(ERR, "configure queues failed");
2038 if (i40evf_config_irq_map(dev)) {
2039 PMD_DRV_LOG(ERR, "config_irq_map failed");
2043 /* Set all mac addrs */
2044 i40evf_add_del_all_mac_addr(dev, TRUE);
2045 /* Set all multicast addresses */
2046 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2049 if (i40evf_start_queues(dev) != 0) {
2050 PMD_DRV_LOG(ERR, "enable queues failed");
2054 /* only enable interrupt in rx interrupt mode */
2055 if (dev->data->dev_conf.intr_conf.rxq != 0)
2056 rte_intr_enable(intr_handle);
2058 i40evf_enable_queues_intr(dev);
2063 i40evf_add_del_all_mac_addr(dev, FALSE);
2064 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2071 i40evf_dev_stop(struct rte_eth_dev *dev)
2073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2074 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2078 PMD_INIT_FUNC_TRACE();
2080 if (dev->data->dev_conf.intr_conf.rxq != 0)
2081 rte_intr_disable(intr_handle);
2083 if (hw->adapter_stopped == 1)
2085 i40evf_stop_queues(dev);
2086 i40evf_disable_queues_intr(dev);
2087 i40e_dev_clear_queues(dev);
2089 /* Clean datapath event and queue/vec mapping */
2090 rte_intr_efd_disable(intr_handle);
2091 if (intr_handle->intr_vec) {
2092 rte_free(intr_handle->intr_vec);
2093 intr_handle->intr_vec = NULL;
2095 /* remove all mac addrs */
2096 i40evf_add_del_all_mac_addr(dev, FALSE);
2097 /* remove all multicast addresses */
2098 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2100 hw->adapter_stopped = 1;
2105 i40evf_dev_link_update(struct rte_eth_dev *dev,
2106 __rte_unused int wait_to_complete)
2108 struct rte_eth_link new_link;
2109 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2111 * DPDK pf host provide interfacet to acquire link status
2112 * while Linux driver does not
2115 memset(&new_link, 0, sizeof(new_link));
2116 /* Linux driver PF host */
2117 switch (vf->link_speed) {
2118 case I40E_LINK_SPEED_100MB:
2119 new_link.link_speed = ETH_SPEED_NUM_100M;
2121 case I40E_LINK_SPEED_1GB:
2122 new_link.link_speed = ETH_SPEED_NUM_1G;
2124 case I40E_LINK_SPEED_10GB:
2125 new_link.link_speed = ETH_SPEED_NUM_10G;
2127 case I40E_LINK_SPEED_20GB:
2128 new_link.link_speed = ETH_SPEED_NUM_20G;
2130 case I40E_LINK_SPEED_25GB:
2131 new_link.link_speed = ETH_SPEED_NUM_25G;
2133 case I40E_LINK_SPEED_40GB:
2134 new_link.link_speed = ETH_SPEED_NUM_40G;
2137 new_link.link_speed = ETH_SPEED_NUM_100M;
2140 /* full duplex only */
2141 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2142 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2144 new_link.link_autoneg =
2145 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2147 return rte_eth_linkstatus_set(dev, &new_link);
2151 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2153 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2156 /* If enabled, just return */
2157 if (vf->promisc_unicast_enabled)
2160 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2162 vf->promisc_unicast_enabled = TRUE;
2166 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2168 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2171 /* If disabled, just return */
2172 if (!vf->promisc_unicast_enabled)
2175 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2177 vf->promisc_unicast_enabled = FALSE;
2181 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2183 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2186 /* If enabled, just return */
2187 if (vf->promisc_multicast_enabled)
2190 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2192 vf->promisc_multicast_enabled = TRUE;
2196 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2198 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2201 /* If enabled, just return */
2202 if (!vf->promisc_multicast_enabled)
2205 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2207 vf->promisc_multicast_enabled = FALSE;
2211 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2213 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2215 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2216 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2217 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2218 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2219 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2220 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2221 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2222 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2223 dev_info->rx_queue_offload_capa = 0;
2224 dev_info->rx_offload_capa =
2225 DEV_RX_OFFLOAD_VLAN_STRIP |
2226 DEV_RX_OFFLOAD_QINQ_STRIP |
2227 DEV_RX_OFFLOAD_IPV4_CKSUM |
2228 DEV_RX_OFFLOAD_UDP_CKSUM |
2229 DEV_RX_OFFLOAD_TCP_CKSUM |
2230 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2231 DEV_RX_OFFLOAD_SCATTER |
2232 DEV_RX_OFFLOAD_JUMBO_FRAME |
2233 DEV_RX_OFFLOAD_VLAN_FILTER;
2235 dev_info->tx_queue_offload_capa = 0;
2236 dev_info->tx_offload_capa =
2237 DEV_TX_OFFLOAD_VLAN_INSERT |
2238 DEV_TX_OFFLOAD_QINQ_INSERT |
2239 DEV_TX_OFFLOAD_IPV4_CKSUM |
2240 DEV_TX_OFFLOAD_UDP_CKSUM |
2241 DEV_TX_OFFLOAD_TCP_CKSUM |
2242 DEV_TX_OFFLOAD_SCTP_CKSUM |
2243 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2244 DEV_TX_OFFLOAD_TCP_TSO |
2245 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2246 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2247 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2248 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2249 DEV_TX_OFFLOAD_MULTI_SEGS;
2251 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2253 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2254 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2255 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2257 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2262 dev_info->default_txconf = (struct rte_eth_txconf) {
2264 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2265 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2266 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2268 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2269 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2273 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2274 .nb_max = I40E_MAX_RING_DESC,
2275 .nb_min = I40E_MIN_RING_DESC,
2276 .nb_align = I40E_ALIGN_RING_DESC,
2279 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2280 .nb_max = I40E_MAX_RING_DESC,
2281 .nb_min = I40E_MIN_RING_DESC,
2282 .nb_align = I40E_ALIGN_RING_DESC,
2287 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2290 struct i40e_eth_stats *pstats = NULL;
2291 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2292 struct i40e_vsi *vsi = &vf->vsi;
2294 ret = i40evf_query_stats(dev, &pstats);
2296 i40evf_update_stats(vsi, pstats);
2298 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2299 pstats->rx_broadcast;
2300 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2302 stats->imissed = pstats->rx_discards;
2303 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2304 stats->ibytes = pstats->rx_bytes;
2305 stats->obytes = pstats->tx_bytes;
2307 PMD_DRV_LOG(ERR, "Get statistics failed");
2313 i40evf_dev_close(struct rte_eth_dev *dev)
2315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317 i40evf_dev_stop(dev);
2318 i40e_dev_free_queues(dev);
2320 * disable promiscuous mode before reset vf
2321 * it is a workaround solution when work with kernel driver
2322 * and it is not the normal way
2324 i40evf_dev_promiscuous_disable(dev);
2325 i40evf_dev_allmulticast_disable(dev);
2327 i40evf_reset_vf(dev);
2328 i40e_shutdown_adminq(hw);
2329 i40evf_disable_irq0(hw);
2330 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2331 hw->adapter_closed = 1;
2335 * Reset VF device only to re-initialize resources in PMD layer
2338 i40evf_dev_reset(struct rte_eth_dev *dev)
2342 ret = i40evf_dev_uninit(dev);
2346 ret = i40evf_dev_init(dev);
2352 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2354 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2355 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2361 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2362 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2365 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2369 uint32_t *lut_dw = (uint32_t *)lut;
2370 uint16_t i, lut_size_dw = lut_size / 4;
2372 for (i = 0; i < lut_size_dw; i++)
2373 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2380 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2389 vf = I40E_VSI_TO_VF(vsi);
2390 hw = I40E_VSI_TO_HW(vsi);
2392 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2393 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2396 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2400 uint32_t *lut_dw = (uint32_t *)lut;
2401 uint16_t i, lut_size_dw = lut_size / 4;
2403 for (i = 0; i < lut_size_dw; i++)
2404 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2405 I40EVF_WRITE_FLUSH(hw);
2412 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2413 struct rte_eth_rss_reta_entry64 *reta_conf,
2416 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2418 uint16_t i, idx, shift;
2421 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2422 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2423 "(%d) doesn't match the number of hardware can "
2424 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2428 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2430 PMD_DRV_LOG(ERR, "No memory can be allocated");
2433 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2436 for (i = 0; i < reta_size; i++) {
2437 idx = i / RTE_RETA_GROUP_SIZE;
2438 shift = i % RTE_RETA_GROUP_SIZE;
2439 if (reta_conf[idx].mask & (1ULL << shift))
2440 lut[i] = reta_conf[idx].reta[shift];
2442 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2451 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2452 struct rte_eth_rss_reta_entry64 *reta_conf,
2455 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2456 uint16_t i, idx, shift;
2460 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2461 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2462 "(%d) doesn't match the number of hardware can "
2463 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2467 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2469 PMD_DRV_LOG(ERR, "No memory can be allocated");
2473 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2476 for (i = 0; i < reta_size; i++) {
2477 idx = i / RTE_RETA_GROUP_SIZE;
2478 shift = i % RTE_RETA_GROUP_SIZE;
2479 if (reta_conf[idx].mask & (1ULL << shift))
2480 reta_conf[idx].reta[shift] = lut[i];
2490 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2492 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2493 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2496 if (!key || key_len == 0) {
2497 PMD_DRV_LOG(DEBUG, "No key to be configured");
2499 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2501 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2505 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2506 struct i40e_aqc_get_set_rss_key_data *key_dw =
2507 (struct i40e_aqc_get_set_rss_key_data *)key;
2509 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2511 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2514 uint32_t *hash_key = (uint32_t *)key;
2517 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2518 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2519 I40EVF_WRITE_FLUSH(hw);
2526 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2528 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2529 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2532 if (!key || !key_len)
2535 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2536 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2537 (struct i40e_aqc_get_set_rss_key_data *)key);
2539 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2543 uint32_t *key_dw = (uint32_t *)key;
2546 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2547 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2549 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2555 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2557 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2561 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2562 rss_conf->rss_key_len);
2566 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2567 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2568 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2569 I40EVF_WRITE_FLUSH(hw);
2575 i40evf_disable_rss(struct i40e_vf *vf)
2577 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2579 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2580 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2581 I40EVF_WRITE_FLUSH(hw);
2585 i40evf_config_rss(struct i40e_vf *vf)
2587 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2588 struct rte_eth_rss_conf rss_conf;
2589 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2592 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2593 i40evf_disable_rss(vf);
2594 PMD_DRV_LOG(DEBUG, "RSS not configured");
2598 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2599 /* Fill out the look up table */
2600 for (i = 0, j = 0; i < nb_q; i++, j++) {
2603 lut = (lut << 8) | j;
2605 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2608 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2609 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2610 i40evf_disable_rss(vf);
2611 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2615 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2616 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2617 /* Calculate the default hash key */
2618 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2619 rss_key_default[i] = (uint32_t)rte_rand();
2620 rss_conf.rss_key = (uint8_t *)rss_key_default;
2621 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2625 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2629 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2630 struct rte_eth_rss_conf *rss_conf)
2632 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2633 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2637 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2638 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2640 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2641 if (rss_hf != 0) /* Enable RSS */
2647 if (rss_hf == 0) /* Disable RSS */
2650 return i40evf_hw_rss_hash_set(vf, rss_conf);
2654 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2655 struct rte_eth_rss_conf *rss_conf)
2657 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2662 &rss_conf->rss_key_len);
2664 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2665 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2666 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2672 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2674 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2675 struct rte_eth_dev_data *dev_data = vf->dev_data;
2676 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2679 /* check if mtu is within the allowed range */
2680 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2683 /* mtu setting is forbidden if port is start */
2684 if (dev_data->dev_started) {
2685 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2690 if (frame_size > ETHER_MAX_LEN)
2691 dev_data->dev_conf.rxmode.offloads |=
2692 DEV_RX_OFFLOAD_JUMBO_FRAME;
2694 dev_data->dev_conf.rxmode.offloads &=
2695 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2696 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2702 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2703 struct ether_addr *mac_addr)
2705 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708 if (!is_valid_assigned_ether_addr(mac_addr)) {
2709 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2713 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2716 i40evf_del_mac_addr_by_addr(dev, (struct ether_addr *)hw->mac.addr);
2718 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2721 ether_addr_copy(mac_addr, (struct ether_addr *)hw->mac.addr);
2726 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2727 struct ether_addr *mc_addrs,
2728 uint32_t mc_addrs_num, bool add)
2730 struct virtchnl_ether_addr_list *list;
2731 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2732 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2733 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2736 struct vf_cmd_info args;
2738 if (mc_addrs == NULL || mc_addrs_num == 0)
2741 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2744 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2745 list->vsi_id = vf->vsi_res->vsi_id;
2746 list->num_elements = mc_addrs_num;
2748 for (i = 0; i < mc_addrs_num; i++) {
2749 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2750 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2751 mc_addrs[i].addr_bytes[0],
2752 mc_addrs[i].addr_bytes[1],
2753 mc_addrs[i].addr_bytes[2],
2754 mc_addrs[i].addr_bytes[3],
2755 mc_addrs[i].addr_bytes[4],
2756 mc_addrs[i].addr_bytes[5]);
2760 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2761 sizeof(list->list[i].addr));
2764 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2765 args.in_args = cmd_buffer;
2766 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2767 i * sizeof(struct virtchnl_ether_addr);
2768 args.out_buffer = vf->aq_resp;
2769 args.out_size = I40E_AQ_BUF_SZ;
2770 err = i40evf_execute_vf_cmd(dev, &args);
2772 PMD_DRV_LOG(ERR, "fail to execute command %s",
2773 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2781 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addrs,
2782 uint32_t mc_addrs_num)
2784 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2787 /* flush previous addresses */
2788 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2793 vf->mc_addrs_num = 0;
2796 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2801 vf->mc_addrs_num = mc_addrs_num;
2802 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));