1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct rte_ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct rte_ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct rte_ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr);
144 i40evf_dev_alarm_handler(void *param);
146 /* Default hash key buffer for RSS */
147 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
149 struct rte_i40evf_xstats_name_off {
150 char name[RTE_ETH_XSTATS_NAME_SIZE];
154 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
155 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
156 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
157 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
158 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
159 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
160 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
161 rx_unknown_protocol)},
162 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
163 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
164 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
165 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
166 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
167 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
170 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
171 sizeof(rte_i40evf_stats_strings[0]))
173 static const struct eth_dev_ops i40evf_eth_dev_ops = {
174 .dev_configure = i40evf_dev_configure,
175 .dev_start = i40evf_dev_start,
176 .dev_stop = i40evf_dev_stop,
177 .promiscuous_enable = i40evf_dev_promiscuous_enable,
178 .promiscuous_disable = i40evf_dev_promiscuous_disable,
179 .allmulticast_enable = i40evf_dev_allmulticast_enable,
180 .allmulticast_disable = i40evf_dev_allmulticast_disable,
181 .link_update = i40evf_dev_link_update,
182 .stats_get = i40evf_dev_stats_get,
183 .stats_reset = i40evf_dev_xstats_reset,
184 .xstats_get = i40evf_dev_xstats_get,
185 .xstats_get_names = i40evf_dev_xstats_get_names,
186 .xstats_reset = i40evf_dev_xstats_reset,
187 .dev_close = i40evf_dev_close,
188 .dev_reset = i40evf_dev_reset,
189 .dev_infos_get = i40evf_dev_info_get,
190 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
191 .vlan_filter_set = i40evf_vlan_filter_set,
192 .vlan_offload_set = i40evf_vlan_offload_set,
193 .rx_queue_start = i40evf_dev_rx_queue_start,
194 .rx_queue_stop = i40evf_dev_rx_queue_stop,
195 .tx_queue_start = i40evf_dev_tx_queue_start,
196 .tx_queue_stop = i40evf_dev_tx_queue_stop,
197 .rx_queue_setup = i40e_dev_rx_queue_setup,
198 .rx_queue_release = i40e_dev_rx_queue_release,
199 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
200 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
201 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
202 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
203 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
204 .tx_queue_setup = i40e_dev_tx_queue_setup,
205 .tx_queue_release = i40e_dev_tx_queue_release,
206 .rx_queue_count = i40e_dev_rx_queue_count,
207 .rxq_info_get = i40e_rxq_info_get,
208 .txq_info_get = i40e_txq_info_get,
209 .mac_addr_add = i40evf_add_mac_addr,
210 .mac_addr_remove = i40evf_del_mac_addr,
211 .set_mc_addr_list = i40evf_set_mc_addr_list,
212 .reta_update = i40evf_dev_rss_reta_update,
213 .reta_query = i40evf_dev_rss_reta_query,
214 .rss_hash_update = i40evf_dev_rss_hash_update,
215 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
216 .mtu_set = i40evf_dev_mtu_set,
217 .mac_addr_set = i40evf_set_default_mac_addr,
221 * Read data in admin queue to get msg from pf driver
223 static enum i40evf_aq_result
224 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
227 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
228 struct i40e_arq_event_info event;
229 enum virtchnl_ops opcode;
230 enum i40e_status_code retval;
232 enum i40evf_aq_result result = I40EVF_MSG_NON;
234 event.buf_len = data->buf_len;
235 event.msg_buf = data->msg;
236 ret = i40e_clean_arq_element(hw, &event, NULL);
237 /* Can't read any msg from adminQ */
239 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
240 result = I40EVF_MSG_ERR;
244 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
245 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
247 if (opcode == VIRTCHNL_OP_EVENT) {
248 struct virtchnl_pf_event *vpe =
249 (struct virtchnl_pf_event *)event.msg_buf;
251 result = I40EVF_MSG_SYS;
252 switch (vpe->event) {
253 case VIRTCHNL_EVENT_LINK_CHANGE:
255 vpe->event_data.link_event.link_status;
257 vpe->event_data.link_event.link_speed;
258 vf->pend_msg |= PFMSG_LINK_CHANGE;
259 PMD_DRV_LOG(INFO, "Link status update:%s",
260 vf->link_up ? "up" : "down");
262 case VIRTCHNL_EVENT_RESET_IMPENDING:
264 vf->pend_msg |= PFMSG_RESET_IMPENDING;
265 PMD_DRV_LOG(INFO, "vf is reseting");
267 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
268 vf->dev_closed = true;
269 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
270 PMD_DRV_LOG(INFO, "PF driver closed");
273 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
274 __func__, vpe->event);
277 /* async reply msg on command issued by vf previously */
278 result = I40EVF_MSG_CMD;
279 /* Actual data length read from PF */
280 data->msg_len = event.msg_len;
283 data->result = retval;
290 * clear current command. Only call in case execute
291 * _atomic_set_cmd successfully.
294 _clear_cmd(struct i40e_vf *vf)
297 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
301 * Check there is pending cmd in execution. If none, set new command.
304 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
306 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
307 VIRTCHNL_OP_UNKNOWN, ops);
310 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
315 #define MAX_TRY_TIMES 200
316 #define ASQ_DELAY_MS 10
319 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
322 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
323 struct i40evf_arq_msg_info info;
324 enum i40evf_aq_result ret;
327 if (_atomic_set_cmd(vf, args->ops))
330 info.msg = args->out_buffer;
331 info.buf_len = args->out_size;
332 info.ops = VIRTCHNL_OP_UNKNOWN;
333 info.result = I40E_SUCCESS;
335 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
336 args->in_args, args->in_args_size, NULL);
338 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
344 case VIRTCHNL_OP_RESET_VF:
345 /*no need to process in this function */
348 case VIRTCHNL_OP_VERSION:
349 case VIRTCHNL_OP_GET_VF_RESOURCES:
350 /* for init adminq commands, need to poll the response */
353 ret = i40evf_read_pfmsg(dev, &info);
354 vf->cmd_retval = info.result;
355 if (ret == I40EVF_MSG_CMD) {
358 } else if (ret == I40EVF_MSG_ERR)
360 rte_delay_ms(ASQ_DELAY_MS);
361 /* If don't read msg or read sys event, continue */
362 } while (i++ < MAX_TRY_TIMES);
365 case VIRTCHNL_OP_REQUEST_QUEUES:
367 * ignore async reply, only wait for system message,
368 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
369 * if not, means request queues failed.
373 ret = i40evf_read_pfmsg(dev, &info);
374 vf->cmd_retval = info.result;
375 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
378 } else if (ret == I40EVF_MSG_ERR ||
379 ret == I40EVF_MSG_CMD) {
382 rte_delay_ms(ASQ_DELAY_MS);
383 /* If don't read msg or read sys event, continue */
384 } while (i++ < MAX_TRY_TIMES);
389 /* for other adminq in running time, waiting the cmd done flag */
392 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
396 rte_delay_ms(ASQ_DELAY_MS);
397 /* If don't read msg or read sys event, continue */
398 } while (i++ < MAX_TRY_TIMES);
399 /* If there's no response is received, clear command */
400 if (i >= MAX_TRY_TIMES) {
401 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
407 return err | vf->cmd_retval;
411 * Check API version with sync wait until version read or fail from admin queue
414 i40evf_check_api_version(struct rte_eth_dev *dev)
416 struct virtchnl_version_info version, *pver;
418 struct vf_cmd_info args;
419 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
421 version.major = VIRTCHNL_VERSION_MAJOR;
422 version.minor = VIRTCHNL_VERSION_MINOR;
424 args.ops = VIRTCHNL_OP_VERSION;
425 args.in_args = (uint8_t *)&version;
426 args.in_args_size = sizeof(version);
427 args.out_buffer = vf->aq_resp;
428 args.out_size = I40E_AQ_BUF_SZ;
430 err = i40evf_execute_vf_cmd(dev, &args);
432 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
436 pver = (struct virtchnl_version_info *)args.out_buffer;
437 vf->version_major = pver->major;
438 vf->version_minor = pver->minor;
439 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
440 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
441 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
443 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
444 vf->version_major, vf->version_minor,
445 VIRTCHNL_VERSION_MAJOR,
446 VIRTCHNL_VERSION_MINOR);
454 i40evf_get_vf_resource(struct rte_eth_dev *dev)
456 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
457 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
459 struct vf_cmd_info args;
462 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
463 args.out_buffer = vf->aq_resp;
464 args.out_size = I40E_AQ_BUF_SZ;
466 caps = VIRTCHNL_VF_OFFLOAD_L2 |
467 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
468 VIRTCHNL_VF_OFFLOAD_RSS_REG |
469 VIRTCHNL_VF_OFFLOAD_VLAN |
470 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
471 args.in_args = (uint8_t *)∩︀
472 args.in_args_size = sizeof(caps);
475 args.in_args_size = 0;
477 err = i40evf_execute_vf_cmd(dev, &args);
480 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
484 len = sizeof(struct virtchnl_vf_resource) +
485 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
487 rte_memcpy(vf->vf_res, args.out_buffer,
488 RTE_MIN(args.out_size, len));
489 i40e_vf_parse_hw_config(hw, vf->vf_res);
495 i40evf_config_promisc(struct rte_eth_dev *dev,
497 bool enable_multicast)
499 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
501 struct vf_cmd_info args;
502 struct virtchnl_promisc_info promisc;
505 promisc.vsi_id = vf->vsi_res->vsi_id;
508 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
510 if (enable_multicast)
511 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
513 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
514 args.in_args = (uint8_t *)&promisc;
515 args.in_args_size = sizeof(promisc);
516 args.out_buffer = vf->aq_resp;
517 args.out_size = I40E_AQ_BUF_SZ;
519 err = i40evf_execute_vf_cmd(dev, &args);
522 PMD_DRV_LOG(ERR, "fail to execute command "
523 "CONFIG_PROMISCUOUS_MODE");
528 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
530 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
531 struct vf_cmd_info args;
534 memset(&args, 0, sizeof(args));
535 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
537 args.in_args_size = 0;
538 args.out_buffer = vf->aq_resp;
539 args.out_size = I40E_AQ_BUF_SZ;
540 ret = i40evf_execute_vf_cmd(dev, &args);
542 PMD_DRV_LOG(ERR, "Failed to execute command of "
543 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
549 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
551 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
552 struct vf_cmd_info args;
555 memset(&args, 0, sizeof(args));
556 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
558 args.in_args_size = 0;
559 args.out_buffer = vf->aq_resp;
560 args.out_size = I40E_AQ_BUF_SZ;
561 ret = i40evf_execute_vf_cmd(dev, &args);
563 PMD_DRV_LOG(ERR, "Failed to execute command of "
564 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
570 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
574 struct i40e_tx_queue *txq)
576 txq_info->vsi_id = vsi_id;
577 txq_info->queue_id = queue_id;
578 if (queue_id < nb_txq && txq) {
579 txq_info->ring_len = txq->nb_tx_desc;
580 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
585 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
589 uint32_t max_pkt_size,
590 struct i40e_rx_queue *rxq)
592 rxq_info->vsi_id = vsi_id;
593 rxq_info->queue_id = queue_id;
594 rxq_info->max_pkt_size = max_pkt_size;
595 if (queue_id < nb_rxq && rxq) {
596 rxq_info->ring_len = rxq->nb_rx_desc;
597 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
598 rxq_info->databuffer_size =
599 (rte_pktmbuf_data_room_size(rxq->mp) -
600 RTE_PKTMBUF_HEADROOM);
605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
607 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
608 struct i40e_rx_queue **rxq =
609 (struct i40e_rx_queue **)dev->data->rx_queues;
610 struct i40e_tx_queue **txq =
611 (struct i40e_tx_queue **)dev->data->tx_queues;
612 struct virtchnl_vsi_queue_config_info *vc_vqci;
613 struct virtchnl_queue_pair_info *vc_qpi;
614 struct vf_cmd_info args;
615 uint16_t i, nb_qp = vf->num_queue_pairs;
616 const uint32_t size =
617 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
621 memset(buff, 0, sizeof(buff));
622 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
623 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
624 vc_vqci->num_queue_pairs = nb_qp;
626 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
627 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
628 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
629 txq ? txq[i] : NULL);
630 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
631 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
632 vf->max_pkt_len, rxq ? rxq[i] : NULL);
634 memset(&args, 0, sizeof(args));
635 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
636 args.in_args = (uint8_t *)vc_vqci;
637 args.in_args_size = size;
638 args.out_buffer = vf->aq_resp;
639 args.out_size = I40E_AQ_BUF_SZ;
640 ret = i40evf_execute_vf_cmd(dev, &args);
642 PMD_DRV_LOG(ERR, "Failed to execute command of "
643 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
649 i40evf_config_irq_map(struct rte_eth_dev *dev)
651 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
652 struct vf_cmd_info args;
653 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
654 sizeof(struct virtchnl_vector_map)];
655 struct virtchnl_irq_map_info *map_info;
656 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
657 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
661 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
662 rte_intr_allow_others(intr_handle))
663 vector_id = I40E_RX_VEC_START;
665 vector_id = I40E_MISC_VEC_ID;
667 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
668 map_info->num_vectors = 1;
669 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
670 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
671 /* Alway use default dynamic MSIX interrupt */
672 map_info->vecmap[0].vector_id = vector_id;
673 /* Don't map any tx queue */
674 map_info->vecmap[0].txq_map = 0;
675 map_info->vecmap[0].rxq_map = 0;
676 for (i = 0; i < dev->data->nb_rx_queues; i++) {
677 map_info->vecmap[0].rxq_map |= 1 << i;
678 if (rte_intr_dp_is_en(intr_handle))
679 intr_handle->intr_vec[i] = vector_id;
682 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
683 args.in_args = (u8 *)cmd_buffer;
684 args.in_args_size = sizeof(cmd_buffer);
685 args.out_buffer = vf->aq_resp;
686 args.out_size = I40E_AQ_BUF_SZ;
687 err = i40evf_execute_vf_cmd(dev, &args);
689 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
695 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
698 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
699 struct virtchnl_queue_select queue_select;
701 struct vf_cmd_info args;
702 memset(&queue_select, 0, sizeof(queue_select));
703 queue_select.vsi_id = vf->vsi_res->vsi_id;
706 queue_select.rx_queues |= 1 << qid;
708 queue_select.tx_queues |= 1 << qid;
711 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
713 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
714 args.in_args = (u8 *)&queue_select;
715 args.in_args_size = sizeof(queue_select);
716 args.out_buffer = vf->aq_resp;
717 args.out_size = I40E_AQ_BUF_SZ;
718 err = i40evf_execute_vf_cmd(dev, &args);
720 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
721 isrx ? "RX" : "TX", qid, on ? "on" : "off");
727 i40evf_start_queues(struct rte_eth_dev *dev)
729 struct rte_eth_dev_data *dev_data = dev->data;
731 struct i40e_rx_queue *rxq;
732 struct i40e_tx_queue *txq;
734 for (i = 0; i < dev->data->nb_rx_queues; i++) {
735 rxq = dev_data->rx_queues[i];
736 if (rxq->rx_deferred_start)
738 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
739 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
744 for (i = 0; i < dev->data->nb_tx_queues; i++) {
745 txq = dev_data->tx_queues[i];
746 if (txq->tx_deferred_start)
748 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
749 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
758 i40evf_stop_queues(struct rte_eth_dev *dev)
762 /* Stop TX queues first */
763 for (i = 0; i < dev->data->nb_tx_queues; i++) {
764 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
765 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
770 /* Then stop RX queues */
771 for (i = 0; i < dev->data->nb_rx_queues; i++) {
772 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
773 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
782 i40evf_add_mac_addr(struct rte_eth_dev *dev,
783 struct rte_ether_addr *addr,
784 __rte_unused uint32_t index,
785 __rte_unused uint32_t pool)
787 struct virtchnl_ether_addr_list *list;
788 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
789 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
790 sizeof(struct virtchnl_ether_addr)];
792 struct vf_cmd_info args;
794 if (rte_is_zero_ether_addr(addr)) {
795 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
796 addr->addr_bytes[0], addr->addr_bytes[1],
797 addr->addr_bytes[2], addr->addr_bytes[3],
798 addr->addr_bytes[4], addr->addr_bytes[5]);
799 return I40E_ERR_INVALID_MAC_ADDR;
802 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
803 list->vsi_id = vf->vsi_res->vsi_id;
804 list->num_elements = 1;
805 rte_memcpy(list->list[0].addr, addr->addr_bytes,
806 sizeof(addr->addr_bytes));
808 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
809 args.in_args = cmd_buffer;
810 args.in_args_size = sizeof(cmd_buffer);
811 args.out_buffer = vf->aq_resp;
812 args.out_size = I40E_AQ_BUF_SZ;
813 err = i40evf_execute_vf_cmd(dev, &args);
815 PMD_DRV_LOG(ERR, "fail to execute command "
816 "OP_ADD_ETHER_ADDRESS");
824 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
825 struct rte_ether_addr *addr)
827 struct virtchnl_ether_addr_list *list;
828 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
829 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
830 sizeof(struct virtchnl_ether_addr)];
832 struct vf_cmd_info args;
834 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
835 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
836 addr->addr_bytes[0], addr->addr_bytes[1],
837 addr->addr_bytes[2], addr->addr_bytes[3],
838 addr->addr_bytes[4], addr->addr_bytes[5]);
842 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
843 list->vsi_id = vf->vsi_res->vsi_id;
844 list->num_elements = 1;
845 rte_memcpy(list->list[0].addr, addr->addr_bytes,
846 sizeof(addr->addr_bytes));
848 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
849 args.in_args = cmd_buffer;
850 args.in_args_size = sizeof(cmd_buffer);
851 args.out_buffer = vf->aq_resp;
852 args.out_size = I40E_AQ_BUF_SZ;
853 err = i40evf_execute_vf_cmd(dev, &args);
855 PMD_DRV_LOG(ERR, "fail to execute command "
856 "OP_DEL_ETHER_ADDRESS");
863 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
865 struct rte_eth_dev_data *data = dev->data;
866 struct rte_ether_addr *addr;
868 addr = &data->mac_addrs[index];
870 i40evf_del_mac_addr_by_addr(dev, addr);
874 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
876 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
877 struct virtchnl_queue_select q_stats;
879 struct vf_cmd_info args;
881 memset(&q_stats, 0, sizeof(q_stats));
882 q_stats.vsi_id = vf->vsi_res->vsi_id;
883 args.ops = VIRTCHNL_OP_GET_STATS;
884 args.in_args = (u8 *)&q_stats;
885 args.in_args_size = sizeof(q_stats);
886 args.out_buffer = vf->aq_resp;
887 args.out_size = I40E_AQ_BUF_SZ;
889 err = i40evf_execute_vf_cmd(dev, &args);
891 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
895 *pstats = (struct i40e_eth_stats *)args.out_buffer;
900 i40evf_stat_update_48(uint64_t *offset,
903 if (*stat >= *offset)
904 *stat = *stat - *offset;
906 *stat = (uint64_t)((*stat +
907 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
909 *stat &= I40E_48_BIT_MASK;
913 i40evf_stat_update_32(uint64_t *offset,
916 if (*stat >= *offset)
917 *stat = (uint64_t)(*stat - *offset);
919 *stat = (uint64_t)((*stat +
920 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
924 i40evf_update_stats(struct i40e_vsi *vsi,
925 struct i40e_eth_stats *nes)
927 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
929 i40evf_stat_update_48(&oes->rx_bytes,
931 i40evf_stat_update_48(&oes->rx_unicast,
933 i40evf_stat_update_48(&oes->rx_multicast,
935 i40evf_stat_update_48(&oes->rx_broadcast,
937 i40evf_stat_update_32(&oes->rx_discards,
939 i40evf_stat_update_32(&oes->rx_unknown_protocol,
940 &nes->rx_unknown_protocol);
941 i40evf_stat_update_48(&oes->tx_bytes,
943 i40evf_stat_update_48(&oes->tx_unicast,
945 i40evf_stat_update_48(&oes->tx_multicast,
947 i40evf_stat_update_48(&oes->tx_broadcast,
949 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
950 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
954 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
957 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
958 struct i40e_eth_stats *pstats = NULL;
960 /* read stat values to clear hardware registers */
961 ret = i40evf_query_stats(dev, &pstats);
963 /* set stats offset base on current values */
965 vf->vsi.eth_stats_offset = *pstats;
970 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
971 struct rte_eth_xstat_name *xstats_names,
972 __rte_unused unsigned limit)
976 if (xstats_names != NULL)
977 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
978 snprintf(xstats_names[i].name,
979 sizeof(xstats_names[i].name),
980 "%s", rte_i40evf_stats_strings[i].name);
982 return I40EVF_NB_XSTATS;
985 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
986 struct rte_eth_xstat *xstats, unsigned n)
990 struct i40e_eth_stats *pstats = NULL;
991 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
992 struct i40e_vsi *vsi = &vf->vsi;
994 if (n < I40EVF_NB_XSTATS)
995 return I40EVF_NB_XSTATS;
997 ret = i40evf_query_stats(dev, &pstats);
1004 i40evf_update_stats(vsi, pstats);
1006 /* loop over xstats array and values from pstats */
1007 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1009 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1010 rte_i40evf_stats_strings[i].offset);
1013 return I40EVF_NB_XSTATS;
1017 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1019 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1020 struct virtchnl_vlan_filter_list *vlan_list;
1021 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1024 struct vf_cmd_info args;
1026 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1027 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1028 vlan_list->num_elements = 1;
1029 vlan_list->vlan_id[0] = vlanid;
1031 args.ops = VIRTCHNL_OP_ADD_VLAN;
1032 args.in_args = (u8 *)&cmd_buffer;
1033 args.in_args_size = sizeof(cmd_buffer);
1034 args.out_buffer = vf->aq_resp;
1035 args.out_size = I40E_AQ_BUF_SZ;
1036 err = i40evf_execute_vf_cmd(dev, &args);
1038 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1044 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1046 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1047 struct virtchnl_vf_res_request vfres;
1048 struct vf_cmd_info args;
1051 vfres.num_queue_pairs = num;
1053 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1054 args.in_args = (u8 *)&vfres;
1055 args.in_args_size = sizeof(vfres);
1056 args.out_buffer = vf->aq_resp;
1057 args.out_size = I40E_AQ_BUF_SZ;
1059 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1060 err = i40evf_execute_vf_cmd(dev, &args);
1062 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1064 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1065 i40evf_dev_alarm_handler, dev);
1070 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1072 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1073 struct virtchnl_vlan_filter_list *vlan_list;
1074 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1077 struct vf_cmd_info args;
1079 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1080 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1081 vlan_list->num_elements = 1;
1082 vlan_list->vlan_id[0] = vlanid;
1084 args.ops = VIRTCHNL_OP_DEL_VLAN;
1085 args.in_args = (u8 *)&cmd_buffer;
1086 args.in_args_size = sizeof(cmd_buffer);
1087 args.out_buffer = vf->aq_resp;
1088 args.out_size = I40E_AQ_BUF_SZ;
1089 err = i40evf_execute_vf_cmd(dev, &args);
1091 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1096 static const struct rte_pci_id pci_id_i40evf_map[] = {
1097 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1098 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1099 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1100 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1101 { .vendor_id = 0, /* sentinel */ },
1106 i40evf_disable_irq0(struct i40e_hw *hw)
1108 /* Disable all interrupt types */
1109 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1110 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1111 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1112 I40EVF_WRITE_FLUSH(hw);
1117 i40evf_enable_irq0(struct i40e_hw *hw)
1119 /* Enable admin queue interrupt trigger */
1122 i40evf_disable_irq0(hw);
1123 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1124 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1125 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1126 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1128 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1129 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1130 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1131 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1133 I40EVF_WRITE_FLUSH(hw);
1137 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1140 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1143 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1144 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1145 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1146 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1147 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1148 reset == VIRTCHNL_VFR_COMPLETED)
1153 if (i >= MAX_RESET_WAIT_CNT)
1156 vf->vf_reset = false;
1157 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1162 i40evf_reset_vf(struct rte_eth_dev *dev)
1165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1168 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1172 * After issuing vf reset command to pf, pf won't necessarily
1173 * reset vf, it depends on what state it exactly is. If it's not
1174 * initialized yet, it won't have vf reset since it's in a certain
1175 * state. If not, it will try to reset. Even vf is reset, pf will
1176 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1177 * it to ACTIVE. In this duration, vf may not catch the moment that
1178 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1182 ret = i40evf_check_vf_reset_done(dev);
1184 PMD_INIT_LOG(ERR, "VF is still resetting");
1192 i40evf_init_vf(struct rte_eth_dev *dev)
1195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1198 i40e_calc_itr_interval(0, 0);
1200 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1201 vf->dev_data = dev->data;
1202 err = i40e_set_mac_type(hw);
1204 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1208 err = i40evf_check_vf_reset_done(dev);
1212 i40e_init_adminq_parameter(hw);
1213 err = i40e_init_adminq(hw);
1215 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1219 /* Reset VF and wait until it's complete */
1220 if (i40evf_reset_vf(dev)) {
1221 PMD_INIT_LOG(ERR, "reset NIC failed");
1225 /* VF reset, shutdown admin queue and initialize again */
1226 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1227 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1231 i40e_init_adminq_parameter(hw);
1232 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1233 PMD_INIT_LOG(ERR, "init_adminq failed");
1237 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1239 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1242 if (i40evf_check_api_version(dev) != 0) {
1243 PMD_INIT_LOG(ERR, "check_api version failed");
1246 bufsz = sizeof(struct virtchnl_vf_resource) +
1247 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1248 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1250 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1254 if (i40evf_get_vf_resource(dev) != 0) {
1255 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1259 /* got VF config message back from PF, now we can parse it */
1260 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1261 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1262 vf->vsi_res = &vf->vf_res->vsi_res[i];
1266 PMD_INIT_LOG(ERR, "no LAN VSI found");
1270 if (hw->mac.type == I40E_MAC_X722_VF)
1271 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1272 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1274 switch (vf->vsi_res->vsi_type) {
1275 case VIRTCHNL_VSI_SRIOV:
1276 vf->vsi.type = I40E_VSI_SRIOV;
1279 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1282 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1283 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1285 /* Store the MAC address configured by host, or generate random one */
1286 if (rte_is_valid_assigned_ether_addr(
1287 (struct rte_ether_addr *)hw->mac.addr))
1288 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1290 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1292 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1293 (I40E_ITR_INDEX_DEFAULT <<
1294 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1296 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1297 I40EVF_WRITE_FLUSH(hw);
1302 rte_free(vf->vf_res);
1305 rte_free(vf->aq_resp);
1307 i40e_shutdown_adminq(hw); /* ignore error */
1313 i40evf_uninit_vf(struct rte_eth_dev *dev)
1315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317 PMD_INIT_FUNC_TRACE();
1319 if (hw->adapter_closed == 0)
1320 i40evf_dev_close(dev);
1326 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1327 __rte_unused uint16_t msglen)
1329 struct virtchnl_pf_event *pf_msg =
1330 (struct virtchnl_pf_event *)msg;
1331 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1333 switch (pf_msg->event) {
1334 case VIRTCHNL_EVENT_RESET_IMPENDING:
1335 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1336 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1339 case VIRTCHNL_EVENT_LINK_CHANGE:
1340 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1341 vf->link_up = pf_msg->event_data.link_event.link_status;
1342 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1344 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1345 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1348 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1354 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1358 struct i40e_arq_event_info info;
1359 uint16_t pending, aq_opc;
1360 enum virtchnl_ops msg_opc;
1361 enum i40e_status_code msg_ret;
1364 info.buf_len = I40E_AQ_BUF_SZ;
1366 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1369 info.msg_buf = vf->aq_resp;
1373 ret = i40e_clean_arq_element(hw, &info, &pending);
1375 if (ret != I40E_SUCCESS) {
1376 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1380 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1381 /* For the message sent from pf to vf, opcode is stored in
1382 * cookie_high of struct i40e_aq_desc, while return error code
1383 * are stored in cookie_low, Which is done by
1384 * i40e_aq_send_msg_to_vf in PF driver.*/
1385 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1386 info.desc.cookie_high);
1387 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1388 info.desc.cookie_low);
1390 case i40e_aqc_opc_send_msg_to_vf:
1391 if (msg_opc == VIRTCHNL_OP_EVENT)
1393 i40evf_handle_pf_event(dev, info.msg_buf,
1396 /* read message and it's expected one */
1397 if (msg_opc == vf->pend_cmd) {
1398 vf->cmd_retval = msg_ret;
1399 /* prevent compiler reordering */
1400 rte_compiler_barrier();
1403 PMD_DRV_LOG(ERR, "command mismatch,"
1404 "expect %u, get %u",
1405 vf->pend_cmd, msg_opc);
1406 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1407 " opcode = %d", msg_opc);
1411 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1419 * Interrupt handler triggered by NIC for handling
1420 * specific interrupt. Only adminq interrupt is processed in VF.
1423 * Pointer to interrupt handle.
1425 * The address of parameter (struct rte_eth_dev *) regsitered before.
1431 i40evf_dev_alarm_handler(void *param)
1433 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1434 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437 i40evf_disable_irq0(hw);
1439 /* read out interrupt causes */
1440 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1442 /* No interrupt event indicated */
1443 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1446 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1447 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1448 i40evf_handle_aq_msg(dev);
1451 /* Link Status Change interrupt */
1452 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1453 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1457 i40evf_enable_irq0(hw);
1458 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1459 i40evf_dev_alarm_handler, dev);
1463 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1466 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1467 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1469 PMD_INIT_FUNC_TRACE();
1471 /* assign ops func pointer */
1472 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1473 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1474 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1477 * For secondary processes, we don't initialise any further as primary
1478 * has already done this work.
1480 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1481 i40e_set_rx_function(eth_dev);
1482 i40e_set_tx_function(eth_dev);
1485 i40e_set_default_ptype_table(eth_dev);
1486 rte_eth_copy_pci_info(eth_dev, pci_dev);
1488 hw->vendor_id = pci_dev->id.vendor_id;
1489 hw->device_id = pci_dev->id.device_id;
1490 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1491 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1492 hw->bus.device = pci_dev->addr.devid;
1493 hw->bus.func = pci_dev->addr.function;
1494 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1495 hw->adapter_stopped = 0;
1496 hw->adapter_closed = 0;
1498 /* Pass the information to the rte_eth_dev_close() that it should also
1499 * release the private port resources.
1501 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1503 if(i40evf_init_vf(eth_dev) != 0) {
1504 PMD_INIT_LOG(ERR, "Init vf failed");
1508 i40e_set_default_pctype_table(eth_dev);
1509 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1510 i40evf_dev_alarm_handler, eth_dev);
1512 /* configure and enable device interrupt */
1513 i40evf_enable_irq0(hw);
1516 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1517 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1519 if (eth_dev->data->mac_addrs == NULL) {
1520 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1521 " store MAC addresses",
1522 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1525 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1526 ð_dev->data->mac_addrs[0]);
1532 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1534 PMD_INIT_FUNC_TRACE();
1536 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1539 if (i40evf_uninit_vf(eth_dev) != 0) {
1540 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1547 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1548 struct rte_pci_device *pci_dev)
1550 return rte_eth_dev_pci_generic_probe(pci_dev,
1551 sizeof(struct i40e_adapter), i40evf_dev_init);
1554 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1556 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1560 * virtual function driver struct
1562 static struct rte_pci_driver rte_i40evf_pmd = {
1563 .id_table = pci_id_i40evf_map,
1564 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1565 .probe = eth_i40evf_pci_probe,
1566 .remove = eth_i40evf_pci_remove,
1569 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1570 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1571 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1574 i40evf_dev_configure(struct rte_eth_dev *dev)
1576 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1577 struct i40e_adapter *ad =
1578 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1579 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1580 dev->data->nb_tx_queues);
1582 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1583 * allocation or vector Rx preconditions we will reset it.
1585 ad->rx_bulk_alloc_allowed = true;
1586 ad->rx_vec_allowed = true;
1587 ad->tx_simple_allowed = true;
1588 ad->tx_vec_allowed = true;
1590 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1593 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1594 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1595 ret = i40evf_request_queues(dev, num_queue_pairs);
1599 ret = i40evf_dev_reset(dev);
1604 return i40evf_init_vlan(dev);
1608 i40evf_init_vlan(struct rte_eth_dev *dev)
1610 /* Apply vlan offload setting */
1611 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1617 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1619 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1620 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1622 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1625 /* Vlan stripping setting */
1626 if (mask & ETH_VLAN_STRIP_MASK) {
1627 /* Enable or disable VLAN stripping */
1628 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1629 i40evf_enable_vlan_strip(dev);
1631 i40evf_disable_vlan_strip(dev);
1638 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1640 struct i40e_rx_queue *rxq;
1642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644 PMD_INIT_FUNC_TRACE();
1646 rxq = dev->data->rx_queues[rx_queue_id];
1648 err = i40e_alloc_rx_queue_mbufs(rxq);
1650 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1656 /* Init the RX tail register. */
1657 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1658 I40EVF_WRITE_FLUSH(hw);
1660 /* Ready to switch the queue on */
1661 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1663 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1667 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1673 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1675 struct i40e_rx_queue *rxq;
1678 rxq = dev->data->rx_queues[rx_queue_id];
1680 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1682 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1687 i40e_rx_queue_release_mbufs(rxq);
1688 i40e_reset_rx_queue(rxq);
1689 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1695 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1699 PMD_INIT_FUNC_TRACE();
1701 /* Ready to switch the queue on */
1702 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1704 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1708 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1714 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1716 struct i40e_tx_queue *txq;
1719 txq = dev->data->tx_queues[tx_queue_id];
1721 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1723 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1728 i40e_tx_queue_release_mbufs(txq);
1729 i40e_reset_tx_queue(txq);
1730 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1736 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1741 ret = i40evf_add_vlan(dev, vlan_id);
1743 ret = i40evf_del_vlan(dev,vlan_id);
1749 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752 struct rte_eth_dev_data *dev_data = dev->data;
1753 struct rte_pktmbuf_pool_private *mbp_priv;
1754 uint16_t buf_size, len;
1756 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1757 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1758 I40EVF_WRITE_FLUSH(hw);
1760 /* Calculate the maximum packet length allowed */
1761 mbp_priv = rte_mempool_get_priv(rxq->mp);
1762 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1763 RTE_PKTMBUF_HEADROOM);
1764 rxq->hs_mode = i40e_header_split_none;
1765 rxq->rx_hdr_len = 0;
1766 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1767 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1768 rxq->max_pkt_len = RTE_MIN(len,
1769 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1772 * Check if the jumbo frame and maximum packet length are set correctly
1774 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1775 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1776 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1777 PMD_DRV_LOG(ERR, "maximum packet length must be "
1778 "larger than %u and smaller than %u, as jumbo "
1779 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1780 (uint32_t)I40E_FRAME_SIZE_MAX);
1781 return I40E_ERR_CONFIG;
1784 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1785 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1786 PMD_DRV_LOG(ERR, "maximum packet length must be "
1787 "larger than %u and smaller than %u, as jumbo "
1788 "frame is disabled",
1789 (uint32_t)RTE_ETHER_MIN_LEN,
1790 (uint32_t)RTE_ETHER_MAX_LEN);
1791 return I40E_ERR_CONFIG;
1795 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1796 rxq->max_pkt_len > buf_size)
1797 dev_data->scattered_rx = 1;
1803 i40evf_rx_init(struct rte_eth_dev *dev)
1805 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1807 int ret = I40E_SUCCESS;
1808 struct i40e_rx_queue **rxq =
1809 (struct i40e_rx_queue **)dev->data->rx_queues;
1811 i40evf_config_rss(vf);
1812 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1813 if (!rxq[i] || !rxq[i]->q_set)
1815 ret = i40evf_rxq_init(dev, rxq[i]);
1816 if (ret != I40E_SUCCESS)
1819 if (ret == I40E_SUCCESS)
1820 i40e_set_rx_function(dev);
1826 i40evf_tx_init(struct rte_eth_dev *dev)
1829 struct i40e_tx_queue **txq =
1830 (struct i40e_tx_queue **)dev->data->tx_queues;
1831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 for (i = 0; i < dev->data->nb_tx_queues; i++)
1834 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1836 i40e_set_tx_function(dev);
1840 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1844 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1846 if (!rte_intr_allow_others(intr_handle)) {
1848 I40E_VFINT_DYN_CTL01,
1849 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1850 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1851 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1852 I40EVF_WRITE_FLUSH(hw);
1856 I40EVF_WRITE_FLUSH(hw);
1860 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1862 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1864 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1866 if (!rte_intr_allow_others(intr_handle)) {
1867 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1868 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1869 I40EVF_WRITE_FLUSH(hw);
1873 I40EVF_WRITE_FLUSH(hw);
1877 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1879 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1880 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1881 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883 i40e_calc_itr_interval(0, 0);
1886 msix_intr = intr_handle->intr_vec[queue_id];
1887 if (msix_intr == I40E_MISC_VEC_ID)
1888 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1889 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1890 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1891 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1893 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1896 I40E_VFINT_DYN_CTLN1(msix_intr -
1898 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1899 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1900 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1902 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1904 I40EVF_WRITE_FLUSH(hw);
1910 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1912 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1913 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1914 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 msix_intr = intr_handle->intr_vec[queue_id];
1918 if (msix_intr == I40E_MISC_VEC_ID)
1919 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1922 I40E_VFINT_DYN_CTLN1(msix_intr -
1926 I40EVF_WRITE_FLUSH(hw);
1932 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1934 struct virtchnl_ether_addr_list *list;
1935 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1940 struct rte_ether_addr *addr;
1941 struct vf_cmd_info args;
1945 len = sizeof(struct virtchnl_ether_addr_list);
1946 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1947 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
1949 len += sizeof(struct virtchnl_ether_addr);
1950 if (len >= I40E_AQ_BUF_SZ) {
1956 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1958 PMD_DRV_LOG(ERR, "fail to allocate memory");
1962 for (i = begin; i < next_begin; i++) {
1963 addr = &dev->data->mac_addrs[i];
1964 if (rte_is_zero_ether_addr(addr))
1966 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1967 sizeof(addr->addr_bytes));
1968 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1969 addr->addr_bytes[0], addr->addr_bytes[1],
1970 addr->addr_bytes[2], addr->addr_bytes[3],
1971 addr->addr_bytes[4], addr->addr_bytes[5]);
1974 list->vsi_id = vf->vsi_res->vsi_id;
1975 list->num_elements = j;
1976 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1977 VIRTCHNL_OP_DEL_ETH_ADDR;
1978 args.in_args = (uint8_t *)list;
1979 args.in_args_size = len;
1980 args.out_buffer = vf->aq_resp;
1981 args.out_size = I40E_AQ_BUF_SZ;
1982 err = i40evf_execute_vf_cmd(dev, &args);
1984 PMD_DRV_LOG(ERR, "fail to execute command %s",
1985 add ? "OP_ADD_ETHER_ADDRESS" :
1986 "OP_DEL_ETHER_ADDRESS");
1995 } while (begin < I40E_NUM_MACADDR_MAX);
1999 i40evf_dev_start(struct rte_eth_dev *dev)
2001 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2004 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2005 uint32_t intr_vector = 0;
2007 PMD_INIT_FUNC_TRACE();
2009 hw->adapter_stopped = 0;
2011 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2012 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2013 dev->data->nb_tx_queues);
2015 /* check and configure queue intr-vector mapping */
2016 if (rte_intr_cap_multiple(intr_handle) &&
2017 dev->data->dev_conf.intr_conf.rxq) {
2018 intr_vector = dev->data->nb_rx_queues;
2019 if (rte_intr_efd_enable(intr_handle, intr_vector))
2023 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2024 intr_handle->intr_vec =
2025 rte_zmalloc("intr_vec",
2026 dev->data->nb_rx_queues * sizeof(int), 0);
2027 if (!intr_handle->intr_vec) {
2028 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2029 " intr_vec", dev->data->nb_rx_queues);
2034 if (i40evf_rx_init(dev) != 0){
2035 PMD_DRV_LOG(ERR, "failed to do RX init");
2039 i40evf_tx_init(dev);
2041 if (i40evf_configure_vsi_queues(dev) != 0) {
2042 PMD_DRV_LOG(ERR, "configure queues failed");
2045 if (i40evf_config_irq_map(dev)) {
2046 PMD_DRV_LOG(ERR, "config_irq_map failed");
2050 /* Set all mac addrs */
2051 i40evf_add_del_all_mac_addr(dev, TRUE);
2052 /* Set all multicast addresses */
2053 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2056 if (i40evf_start_queues(dev) != 0) {
2057 PMD_DRV_LOG(ERR, "enable queues failed");
2061 /* only enable interrupt in rx interrupt mode */
2062 if (dev->data->dev_conf.intr_conf.rxq != 0)
2063 rte_intr_enable(intr_handle);
2065 i40evf_enable_queues_intr(dev);
2070 i40evf_add_del_all_mac_addr(dev, FALSE);
2071 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2078 i40evf_dev_stop(struct rte_eth_dev *dev)
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2085 PMD_INIT_FUNC_TRACE();
2087 if (dev->data->dev_conf.intr_conf.rxq != 0)
2088 rte_intr_disable(intr_handle);
2090 if (hw->adapter_stopped == 1)
2092 i40evf_stop_queues(dev);
2093 i40evf_disable_queues_intr(dev);
2094 i40e_dev_clear_queues(dev);
2096 /* Clean datapath event and queue/vec mapping */
2097 rte_intr_efd_disable(intr_handle);
2098 if (intr_handle->intr_vec) {
2099 rte_free(intr_handle->intr_vec);
2100 intr_handle->intr_vec = NULL;
2102 /* remove all mac addrs */
2103 i40evf_add_del_all_mac_addr(dev, FALSE);
2104 /* remove all multicast addresses */
2105 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2107 hw->adapter_stopped = 1;
2112 i40evf_dev_link_update(struct rte_eth_dev *dev,
2113 __rte_unused int wait_to_complete)
2115 struct rte_eth_link new_link;
2116 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2118 * DPDK pf host provide interfacet to acquire link status
2119 * while Linux driver does not
2122 memset(&new_link, 0, sizeof(new_link));
2123 /* Linux driver PF host */
2124 switch (vf->link_speed) {
2125 case I40E_LINK_SPEED_100MB:
2126 new_link.link_speed = ETH_SPEED_NUM_100M;
2128 case I40E_LINK_SPEED_1GB:
2129 new_link.link_speed = ETH_SPEED_NUM_1G;
2131 case I40E_LINK_SPEED_10GB:
2132 new_link.link_speed = ETH_SPEED_NUM_10G;
2134 case I40E_LINK_SPEED_20GB:
2135 new_link.link_speed = ETH_SPEED_NUM_20G;
2137 case I40E_LINK_SPEED_25GB:
2138 new_link.link_speed = ETH_SPEED_NUM_25G;
2140 case I40E_LINK_SPEED_40GB:
2141 new_link.link_speed = ETH_SPEED_NUM_40G;
2144 new_link.link_speed = ETH_SPEED_NUM_100M;
2147 /* full duplex only */
2148 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2149 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2151 new_link.link_autoneg =
2152 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2154 return rte_eth_linkstatus_set(dev, &new_link);
2158 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2160 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2163 /* If enabled, just return */
2164 if (vf->promisc_unicast_enabled)
2167 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2169 vf->promisc_unicast_enabled = TRUE;
2177 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2179 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2182 /* If disabled, just return */
2183 if (!vf->promisc_unicast_enabled)
2186 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2188 vf->promisc_unicast_enabled = FALSE;
2196 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2198 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2201 /* If enabled, just return */
2202 if (vf->promisc_multicast_enabled)
2205 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2207 vf->promisc_multicast_enabled = TRUE;
2215 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2217 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2220 /* If enabled, just return */
2221 if (!vf->promisc_multicast_enabled)
2224 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2226 vf->promisc_multicast_enabled = FALSE;
2234 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2236 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2238 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2239 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2240 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2241 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2242 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2243 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2244 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2245 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2246 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2247 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2248 dev_info->rx_queue_offload_capa = 0;
2249 dev_info->rx_offload_capa =
2250 DEV_RX_OFFLOAD_VLAN_STRIP |
2251 DEV_RX_OFFLOAD_QINQ_STRIP |
2252 DEV_RX_OFFLOAD_IPV4_CKSUM |
2253 DEV_RX_OFFLOAD_UDP_CKSUM |
2254 DEV_RX_OFFLOAD_TCP_CKSUM |
2255 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2256 DEV_RX_OFFLOAD_SCATTER |
2257 DEV_RX_OFFLOAD_JUMBO_FRAME |
2258 DEV_RX_OFFLOAD_VLAN_FILTER;
2260 dev_info->tx_queue_offload_capa = 0;
2261 dev_info->tx_offload_capa =
2262 DEV_TX_OFFLOAD_VLAN_INSERT |
2263 DEV_TX_OFFLOAD_QINQ_INSERT |
2264 DEV_TX_OFFLOAD_IPV4_CKSUM |
2265 DEV_TX_OFFLOAD_UDP_CKSUM |
2266 DEV_TX_OFFLOAD_TCP_CKSUM |
2267 DEV_TX_OFFLOAD_SCTP_CKSUM |
2268 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2269 DEV_TX_OFFLOAD_TCP_TSO |
2270 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2271 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2272 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2273 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2274 DEV_TX_OFFLOAD_MULTI_SEGS;
2276 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2278 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2279 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2280 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2282 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2287 dev_info->default_txconf = (struct rte_eth_txconf) {
2289 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2290 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2291 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2293 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2294 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2298 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2299 .nb_max = I40E_MAX_RING_DESC,
2300 .nb_min = I40E_MIN_RING_DESC,
2301 .nb_align = I40E_ALIGN_RING_DESC,
2304 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2305 .nb_max = I40E_MAX_RING_DESC,
2306 .nb_min = I40E_MIN_RING_DESC,
2307 .nb_align = I40E_ALIGN_RING_DESC,
2314 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2317 struct i40e_eth_stats *pstats = NULL;
2318 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2319 struct i40e_vsi *vsi = &vf->vsi;
2321 ret = i40evf_query_stats(dev, &pstats);
2323 i40evf_update_stats(vsi, pstats);
2325 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2326 pstats->rx_broadcast;
2327 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2329 stats->imissed = pstats->rx_discards;
2330 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2331 stats->ibytes = pstats->rx_bytes;
2332 stats->obytes = pstats->tx_bytes;
2334 PMD_DRV_LOG(ERR, "Get statistics failed");
2340 i40evf_dev_close(struct rte_eth_dev *dev)
2342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2345 i40evf_dev_stop(dev);
2346 i40e_dev_free_queues(dev);
2348 * disable promiscuous mode before reset vf
2349 * it is a workaround solution when work with kernel driver
2350 * and it is not the normal way
2352 i40evf_dev_promiscuous_disable(dev);
2353 i40evf_dev_allmulticast_disable(dev);
2354 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2356 i40evf_reset_vf(dev);
2357 i40e_shutdown_adminq(hw);
2358 i40evf_disable_irq0(hw);
2360 dev->dev_ops = NULL;
2361 dev->rx_pkt_burst = NULL;
2362 dev->tx_pkt_burst = NULL;
2364 rte_free(vf->vf_res);
2366 rte_free(vf->aq_resp);
2369 hw->adapter_closed = 1;
2373 * Reset VF device only to re-initialize resources in PMD layer
2376 i40evf_dev_reset(struct rte_eth_dev *dev)
2380 ret = i40evf_dev_uninit(dev);
2384 ret = i40evf_dev_init(dev);
2390 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2392 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2393 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2399 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2400 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2403 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2407 uint32_t *lut_dw = (uint32_t *)lut;
2408 uint16_t i, lut_size_dw = lut_size / 4;
2410 for (i = 0; i < lut_size_dw; i++)
2411 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2418 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2427 vf = I40E_VSI_TO_VF(vsi);
2428 hw = I40E_VSI_TO_HW(vsi);
2430 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2431 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2434 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2438 uint32_t *lut_dw = (uint32_t *)lut;
2439 uint16_t i, lut_size_dw = lut_size / 4;
2441 for (i = 0; i < lut_size_dw; i++)
2442 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2443 I40EVF_WRITE_FLUSH(hw);
2450 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2451 struct rte_eth_rss_reta_entry64 *reta_conf,
2454 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2456 uint16_t i, idx, shift;
2459 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2460 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2461 "(%d) doesn't match the number of hardware can "
2462 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2466 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2468 PMD_DRV_LOG(ERR, "No memory can be allocated");
2471 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2474 for (i = 0; i < reta_size; i++) {
2475 idx = i / RTE_RETA_GROUP_SIZE;
2476 shift = i % RTE_RETA_GROUP_SIZE;
2477 if (reta_conf[idx].mask & (1ULL << shift))
2478 lut[i] = reta_conf[idx].reta[shift];
2480 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2489 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2490 struct rte_eth_rss_reta_entry64 *reta_conf,
2493 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2494 uint16_t i, idx, shift;
2498 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2499 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2500 "(%d) doesn't match the number of hardware can "
2501 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2505 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2507 PMD_DRV_LOG(ERR, "No memory can be allocated");
2511 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2514 for (i = 0; i < reta_size; i++) {
2515 idx = i / RTE_RETA_GROUP_SIZE;
2516 shift = i % RTE_RETA_GROUP_SIZE;
2517 if (reta_conf[idx].mask & (1ULL << shift))
2518 reta_conf[idx].reta[shift] = lut[i];
2528 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2530 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2534 if (!key || key_len == 0) {
2535 PMD_DRV_LOG(DEBUG, "No key to be configured");
2537 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2539 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2543 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2544 struct i40e_aqc_get_set_rss_key_data *key_dw =
2545 (struct i40e_aqc_get_set_rss_key_data *)key;
2547 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2549 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2552 uint32_t *hash_key = (uint32_t *)key;
2555 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2556 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2557 I40EVF_WRITE_FLUSH(hw);
2564 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2566 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2567 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570 if (!key || !key_len)
2573 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2574 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2575 (struct i40e_aqc_get_set_rss_key_data *)key);
2577 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2581 uint32_t *key_dw = (uint32_t *)key;
2584 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2585 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2587 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2593 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2595 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2599 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2600 rss_conf->rss_key_len);
2604 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2605 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2606 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2607 I40EVF_WRITE_FLUSH(hw);
2613 i40evf_disable_rss(struct i40e_vf *vf)
2615 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2617 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2618 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2619 I40EVF_WRITE_FLUSH(hw);
2623 i40evf_config_rss(struct i40e_vf *vf)
2625 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2626 struct rte_eth_rss_conf rss_conf;
2627 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2628 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2633 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2634 i40evf_disable_rss(vf);
2635 PMD_DRV_LOG(DEBUG, "RSS not configured");
2639 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2640 /* Fill out the look up table */
2641 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2642 for (i = 0, j = 0; i < nb_q; i++, j++) {
2645 lut = (lut << 8) | j;
2647 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2650 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2652 PMD_DRV_LOG(ERR, "No memory can be allocated");
2656 for (i = 0; i < rss_lut_size; i++)
2657 lut_info[i] = i % vf->num_queue_pairs;
2659 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2666 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2667 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2668 i40evf_disable_rss(vf);
2669 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2673 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2674 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2675 /* Calculate the default hash key */
2676 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2677 rss_key_default[i] = (uint32_t)rte_rand();
2678 rss_conf.rss_key = (uint8_t *)rss_key_default;
2679 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2683 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2687 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2688 struct rte_eth_rss_conf *rss_conf)
2690 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2691 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2695 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2696 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2698 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2699 if (rss_hf != 0) /* Enable RSS */
2705 if (rss_hf == 0) /* Disable RSS */
2708 return i40evf_hw_rss_hash_set(vf, rss_conf);
2712 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2713 struct rte_eth_rss_conf *rss_conf)
2715 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2716 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2720 &rss_conf->rss_key_len);
2722 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2723 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2724 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2730 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2732 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2733 struct rte_eth_dev_data *dev_data = vf->dev_data;
2734 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2737 /* check if mtu is within the allowed range */
2738 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2741 /* mtu setting is forbidden if port is start */
2742 if (dev_data->dev_started) {
2743 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2748 if (frame_size > RTE_ETHER_MAX_LEN)
2749 dev_data->dev_conf.rxmode.offloads |=
2750 DEV_RX_OFFLOAD_JUMBO_FRAME;
2752 dev_data->dev_conf.rxmode.offloads &=
2753 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2754 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2760 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2761 struct rte_ether_addr *mac_addr)
2763 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2764 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2767 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2771 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2774 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2776 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2779 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2784 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2785 struct rte_ether_addr *mc_addrs,
2786 uint32_t mc_addrs_num, bool add)
2788 struct virtchnl_ether_addr_list *list;
2789 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2790 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2791 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2794 struct vf_cmd_info args;
2796 if (mc_addrs == NULL || mc_addrs_num == 0)
2799 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2802 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2803 list->vsi_id = vf->vsi_res->vsi_id;
2804 list->num_elements = mc_addrs_num;
2806 for (i = 0; i < mc_addrs_num; i++) {
2807 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2808 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2809 mc_addrs[i].addr_bytes[0],
2810 mc_addrs[i].addr_bytes[1],
2811 mc_addrs[i].addr_bytes[2],
2812 mc_addrs[i].addr_bytes[3],
2813 mc_addrs[i].addr_bytes[4],
2814 mc_addrs[i].addr_bytes[5]);
2818 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2819 sizeof(list->list[i].addr));
2822 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2823 args.in_args = cmd_buffer;
2824 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2825 i * sizeof(struct virtchnl_ether_addr);
2826 args.out_buffer = vf->aq_resp;
2827 args.out_size = I40E_AQ_BUF_SZ;
2828 err = i40evf_execute_vf_cmd(dev, &args);
2830 PMD_DRV_LOG(ERR, "fail to execute command %s",
2831 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2839 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2840 struct rte_ether_addr *mc_addrs,
2841 uint32_t mc_addrs_num)
2843 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2846 /* flush previous addresses */
2847 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2852 vf->mc_addrs_num = 0;
2855 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2860 vf->mc_addrs_num = mc_addrs_num;
2861 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2867 is_i40evf_supported(struct rte_eth_dev *dev)
2869 return is_device_supported(dev, &rte_i40evf_pmd);