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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstats *xstats, unsigned n);
115 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
116 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
119 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
121 static void i40evf_dev_close(struct rte_eth_dev *dev);
122 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40evf_get_link_status(struct rte_eth_dev *dev,
127 struct rte_eth_link *link);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
157 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
161 /* Default hash key buffer for RSS */
162 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
164 struct rte_i40evf_xstats_name_off {
165 char name[RTE_ETH_XSTATS_NAME_SIZE];
169 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
170 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
171 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
172 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
173 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
174 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
175 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
176 rx_unknown_protocol)},
177 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
178 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
179 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
180 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
185 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
186 sizeof(rte_i40evf_stats_strings[0]))
188 static const struct eth_dev_ops i40evf_eth_dev_ops = {
189 .dev_configure = i40evf_dev_configure,
190 .dev_start = i40evf_dev_start,
191 .dev_stop = i40evf_dev_stop,
192 .promiscuous_enable = i40evf_dev_promiscuous_enable,
193 .promiscuous_disable = i40evf_dev_promiscuous_disable,
194 .allmulticast_enable = i40evf_dev_allmulticast_enable,
195 .allmulticast_disable = i40evf_dev_allmulticast_disable,
196 .link_update = i40evf_dev_link_update,
197 .stats_get = i40evf_dev_stats_get,
198 .xstats_get = i40evf_dev_xstats_get,
199 .xstats_reset = i40evf_dev_xstats_reset,
200 .dev_close = i40evf_dev_close,
201 .dev_infos_get = i40evf_dev_info_get,
202 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
203 .vlan_filter_set = i40evf_vlan_filter_set,
204 .vlan_offload_set = i40evf_vlan_offload_set,
205 .vlan_pvid_set = i40evf_vlan_pvid_set,
206 .rx_queue_start = i40evf_dev_rx_queue_start,
207 .rx_queue_stop = i40evf_dev_rx_queue_stop,
208 .tx_queue_start = i40evf_dev_tx_queue_start,
209 .tx_queue_stop = i40evf_dev_tx_queue_stop,
210 .rx_queue_setup = i40e_dev_rx_queue_setup,
211 .rx_queue_release = i40e_dev_rx_queue_release,
212 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
213 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
214 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
215 .tx_queue_setup = i40e_dev_tx_queue_setup,
216 .tx_queue_release = i40e_dev_tx_queue_release,
217 .rx_queue_count = i40e_dev_rx_queue_count,
218 .rxq_info_get = i40e_rxq_info_get,
219 .txq_info_get = i40e_txq_info_get,
220 .mac_addr_add = i40evf_add_mac_addr,
221 .mac_addr_remove = i40evf_del_mac_addr,
222 .reta_update = i40evf_dev_rss_reta_update,
223 .reta_query = i40evf_dev_rss_reta_query,
224 .rss_hash_update = i40evf_dev_rss_hash_update,
225 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
229 * Read data in admin queue to get msg from pf driver
231 static enum i40evf_aq_result
232 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
234 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
235 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
236 struct i40e_arq_event_info event;
237 enum i40e_virtchnl_ops opcode;
238 enum i40e_status_code retval;
240 enum i40evf_aq_result result = I40EVF_MSG_NON;
242 event.buf_len = data->buf_len;
243 event.msg_buf = data->msg;
244 ret = i40e_clean_arq_element(hw, &event, NULL);
245 /* Can't read any msg from adminQ */
247 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
248 result = I40EVF_MSG_ERR;
252 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
253 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
255 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
256 struct i40e_virtchnl_pf_event *vpe =
257 (struct i40e_virtchnl_pf_event *)event.msg_buf;
259 result = I40EVF_MSG_SYS;
260 switch (vpe->event) {
261 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
263 vpe->event_data.link_event.link_status;
265 vpe->event_data.link_event.link_speed;
266 vf->pend_msg |= PFMSG_LINK_CHANGE;
267 PMD_DRV_LOG(INFO, "Link status update:%s",
268 vf->link_up ? "up" : "down");
270 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
272 vf->pend_msg |= PFMSG_RESET_IMPENDING;
273 PMD_DRV_LOG(INFO, "vf is reseting");
275 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
276 vf->dev_closed = true;
277 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
278 PMD_DRV_LOG(INFO, "PF driver closed");
281 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
282 __func__, vpe->event);
285 /* async reply msg on command issued by vf previously */
286 result = I40EVF_MSG_CMD;
287 /* Actual data length read from PF */
288 data->msg_len = event.msg_len;
291 data->result = retval;
298 * clear current command. Only call in case execute
299 * _atomic_set_cmd successfully.
302 _clear_cmd(struct i40e_vf *vf)
305 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
309 * Check there is pending cmd in execution. If none, set new command.
312 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
314 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
315 I40E_VIRTCHNL_OP_UNKNOWN, ops);
318 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
323 #define MAX_TRY_TIMES 200
324 #define ASQ_DELAY_MS 10
327 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
330 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
331 struct i40evf_arq_msg_info info;
332 enum i40evf_aq_result ret;
336 if (_atomic_set_cmd(vf, args->ops))
339 info.msg = args->out_buffer;
340 info.buf_len = args->out_size;
341 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
342 info.result = I40E_SUCCESS;
344 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
345 args->in_args, args->in_args_size, NULL);
347 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
353 case I40E_VIRTCHNL_OP_RESET_VF:
354 /*no need to process in this function */
356 case I40E_VIRTCHNL_OP_VERSION:
357 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
358 /* for init adminq commands, need to poll the response */
360 ret = i40evf_read_pfmsg(dev, &info);
361 if (ret == I40EVF_MSG_CMD) {
364 } else if (ret == I40EVF_MSG_ERR) {
368 rte_delay_ms(ASQ_DELAY_MS);
369 /* If don't read msg or read sys event, continue */
370 } while (i++ < MAX_TRY_TIMES);
375 /* for other adminq in running time, waiting the cmd done flag */
377 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
381 rte_delay_ms(ASQ_DELAY_MS);
382 /* If don't read msg or read sys event, continue */
383 } while (i++ < MAX_TRY_TIMES);
387 return err | vf->cmd_retval;
391 * Check API version with sync wait until version read or fail from admin queue
394 i40evf_check_api_version(struct rte_eth_dev *dev)
396 struct i40e_virtchnl_version_info version, *pver;
398 struct vf_cmd_info args;
399 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
401 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
402 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
404 args.ops = I40E_VIRTCHNL_OP_VERSION;
405 args.in_args = (uint8_t *)&version;
406 args.in_args_size = sizeof(version);
407 args.out_buffer = vf->aq_resp;
408 args.out_size = I40E_AQ_BUF_SZ;
410 err = i40evf_execute_vf_cmd(dev, &args);
412 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
416 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
417 vf->version_major = pver->major;
418 vf->version_minor = pver->minor;
419 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
420 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
421 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
422 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
423 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
425 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
426 vf->version_major, vf->version_minor,
427 I40E_VIRTCHNL_VERSION_MAJOR,
428 I40E_VIRTCHNL_VERSION_MINOR);
436 i40evf_get_vf_resource(struct rte_eth_dev *dev)
438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
439 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
441 struct vf_cmd_info args;
444 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
445 args.out_buffer = vf->aq_resp;
446 args.out_size = I40E_AQ_BUF_SZ;
448 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
449 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
450 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
451 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
452 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
453 args.in_args = (uint8_t *)∩︀
454 args.in_args_size = sizeof(caps);
457 args.in_args_size = 0;
459 err = i40evf_execute_vf_cmd(dev, &args);
462 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
466 len = sizeof(struct i40e_virtchnl_vf_resource) +
467 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
469 (void)rte_memcpy(vf->vf_res, args.out_buffer,
470 RTE_MIN(args.out_size, len));
471 i40e_vf_parse_hw_config(hw, vf->vf_res);
477 i40evf_config_promisc(struct rte_eth_dev *dev,
479 bool enable_multicast)
481 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
483 struct vf_cmd_info args;
484 struct i40e_virtchnl_promisc_info promisc;
487 promisc.vsi_id = vf->vsi_res->vsi_id;
490 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
492 if (enable_multicast)
493 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
495 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
496 args.in_args = (uint8_t *)&promisc;
497 args.in_args_size = sizeof(promisc);
498 args.out_buffer = vf->aq_resp;
499 args.out_size = I40E_AQ_BUF_SZ;
501 err = i40evf_execute_vf_cmd(dev, &args);
504 PMD_DRV_LOG(ERR, "fail to execute command "
505 "CONFIG_PROMISCUOUS_MODE");
509 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
511 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
512 bool enable_vlan_strip)
514 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
516 struct vf_cmd_info args;
517 struct i40e_virtchnl_vlan_offload_info offload;
519 offload.vsi_id = vf->vsi_res->vsi_id;
520 offload.enable_vlan_strip = enable_vlan_strip;
522 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
523 args.in_args = (uint8_t *)&offload;
524 args.in_args_size = sizeof(offload);
525 args.out_buffer = vf->aq_resp;
526 args.out_size = I40E_AQ_BUF_SZ;
528 err = i40evf_execute_vf_cmd(dev, &args);
530 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
536 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
537 struct i40e_vsi_vlan_pvid_info *info)
539 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
541 struct vf_cmd_info args;
542 struct i40e_virtchnl_pvid_info tpid_info;
545 PMD_DRV_LOG(ERR, "invalid parameters");
546 return I40E_ERR_PARAM;
549 memset(&tpid_info, 0, sizeof(tpid_info));
550 tpid_info.vsi_id = vf->vsi_res->vsi_id;
551 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
553 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
554 args.in_args = (uint8_t *)&tpid_info;
555 args.in_args_size = sizeof(tpid_info);
556 args.out_buffer = vf->aq_resp;
557 args.out_size = I40E_AQ_BUF_SZ;
559 err = i40evf_execute_vf_cmd(dev, &args);
561 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
567 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
571 struct i40e_tx_queue *txq)
573 txq_info->vsi_id = vsi_id;
574 txq_info->queue_id = queue_id;
575 if (queue_id < nb_txq) {
576 txq_info->ring_len = txq->nb_tx_desc;
577 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
582 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
586 uint32_t max_pkt_size,
587 struct i40e_rx_queue *rxq)
589 rxq_info->vsi_id = vsi_id;
590 rxq_info->queue_id = queue_id;
591 rxq_info->max_pkt_size = max_pkt_size;
592 if (queue_id < nb_rxq) {
593 rxq_info->ring_len = rxq->nb_rx_desc;
594 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
595 rxq_info->databuffer_size =
596 (rte_pktmbuf_data_room_size(rxq->mp) -
597 RTE_PKTMBUF_HEADROOM);
601 /* It configures VSI queues to co-work with Linux PF host */
603 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
605 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
606 struct i40e_rx_queue **rxq =
607 (struct i40e_rx_queue **)dev->data->rx_queues;
608 struct i40e_tx_queue **txq =
609 (struct i40e_tx_queue **)dev->data->tx_queues;
610 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
611 struct i40e_virtchnl_queue_pair_info *vc_qpi;
612 struct vf_cmd_info args;
613 uint16_t i, nb_qp = vf->num_queue_pairs;
614 const uint32_t size =
615 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
619 memset(buff, 0, sizeof(buff));
620 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
621 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
622 vc_vqci->num_queue_pairs = nb_qp;
624 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
625 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
626 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
627 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
628 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
629 vf->max_pkt_len, rxq[i]);
631 memset(&args, 0, sizeof(args));
632 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
633 args.in_args = (uint8_t *)vc_vqci;
634 args.in_args_size = size;
635 args.out_buffer = vf->aq_resp;
636 args.out_size = I40E_AQ_BUF_SZ;
637 ret = i40evf_execute_vf_cmd(dev, &args);
639 PMD_DRV_LOG(ERR, "Failed to execute command of "
640 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
645 /* It configures VSI queues to co-work with DPDK PF host */
647 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
649 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
650 struct i40e_rx_queue **rxq =
651 (struct i40e_rx_queue **)dev->data->rx_queues;
652 struct i40e_tx_queue **txq =
653 (struct i40e_tx_queue **)dev->data->tx_queues;
654 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
655 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
656 struct vf_cmd_info args;
657 uint16_t i, nb_qp = vf->num_queue_pairs;
658 const uint32_t size =
659 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
663 memset(buff, 0, sizeof(buff));
664 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
665 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
666 vc_vqcei->num_queue_pairs = nb_qp;
667 vc_qpei = vc_vqcei->qpair;
668 for (i = 0; i < nb_qp; i++, vc_qpei++) {
669 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
670 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
671 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
672 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
673 vf->max_pkt_len, rxq[i]);
674 if (i < dev->data->nb_rx_queues)
676 * It adds extra info for configuring VSI queues, which
677 * is needed to enable the configurable crc stripping
680 vc_qpei->rxq_ext.crcstrip =
681 dev->data->dev_conf.rxmode.hw_strip_crc;
683 memset(&args, 0, sizeof(args));
685 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
686 args.in_args = (uint8_t *)vc_vqcei;
687 args.in_args_size = size;
688 args.out_buffer = vf->aq_resp;
689 args.out_size = I40E_AQ_BUF_SZ;
690 ret = i40evf_execute_vf_cmd(dev, &args);
692 PMD_DRV_LOG(ERR, "Failed to execute command of "
693 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
699 i40evf_configure_queues(struct rte_eth_dev *dev)
701 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
703 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
704 /* To support DPDK PF host */
705 return i40evf_configure_vsi_queues_ext(dev);
707 /* To support Linux PF host */
708 return i40evf_configure_vsi_queues(dev);
712 i40evf_config_irq_map(struct rte_eth_dev *dev)
714 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
715 struct vf_cmd_info args;
716 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
717 sizeof(struct i40e_virtchnl_vector_map)];
718 struct i40e_virtchnl_irq_map_info *map_info;
719 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
723 if (rte_intr_allow_others(intr_handle)) {
724 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
725 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
727 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
729 vector_id = I40E_MISC_VEC_ID;
732 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
733 map_info->num_vectors = 1;
734 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
735 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
736 /* Alway use default dynamic MSIX interrupt */
737 map_info->vecmap[0].vector_id = vector_id;
738 /* Don't map any tx queue */
739 map_info->vecmap[0].txq_map = 0;
740 map_info->vecmap[0].rxq_map = 0;
741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
742 map_info->vecmap[0].rxq_map |= 1 << i;
743 if (rte_intr_dp_is_en(intr_handle))
744 intr_handle->intr_vec[i] = vector_id;
747 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
748 args.in_args = (u8 *)cmd_buffer;
749 args.in_args_size = sizeof(cmd_buffer);
750 args.out_buffer = vf->aq_resp;
751 args.out_size = I40E_AQ_BUF_SZ;
752 err = i40evf_execute_vf_cmd(dev, &args);
754 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
760 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
763 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
764 struct i40e_virtchnl_queue_select queue_select;
766 struct vf_cmd_info args;
767 memset(&queue_select, 0, sizeof(queue_select));
768 queue_select.vsi_id = vf->vsi_res->vsi_id;
771 queue_select.rx_queues |= 1 << qid;
773 queue_select.tx_queues |= 1 << qid;
776 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
778 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
779 args.in_args = (u8 *)&queue_select;
780 args.in_args_size = sizeof(queue_select);
781 args.out_buffer = vf->aq_resp;
782 args.out_size = I40E_AQ_BUF_SZ;
783 err = i40evf_execute_vf_cmd(dev, &args);
785 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
786 isrx ? "RX" : "TX", qid, on ? "on" : "off");
792 i40evf_start_queues(struct rte_eth_dev *dev)
794 struct rte_eth_dev_data *dev_data = dev->data;
796 struct i40e_rx_queue *rxq;
797 struct i40e_tx_queue *txq;
799 for (i = 0; i < dev->data->nb_rx_queues; i++) {
800 rxq = dev_data->rx_queues[i];
801 if (rxq->rx_deferred_start)
803 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
804 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
809 for (i = 0; i < dev->data->nb_tx_queues; i++) {
810 txq = dev_data->tx_queues[i];
811 if (txq->tx_deferred_start)
813 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
814 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
823 i40evf_stop_queues(struct rte_eth_dev *dev)
827 /* Stop TX queues first */
828 for (i = 0; i < dev->data->nb_tx_queues; i++) {
829 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
830 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
835 /* Then stop RX queues */
836 for (i = 0; i < dev->data->nb_rx_queues; i++) {
837 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
838 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
847 i40evf_add_mac_addr(struct rte_eth_dev *dev,
848 struct ether_addr *addr,
849 __rte_unused uint32_t index,
850 __rte_unused uint32_t pool)
852 struct i40e_virtchnl_ether_addr_list *list;
853 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
854 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
855 sizeof(struct i40e_virtchnl_ether_addr)];
857 struct vf_cmd_info args;
859 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
860 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
861 addr->addr_bytes[0], addr->addr_bytes[1],
862 addr->addr_bytes[2], addr->addr_bytes[3],
863 addr->addr_bytes[4], addr->addr_bytes[5]);
867 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
868 list->vsi_id = vf->vsi_res->vsi_id;
869 list->num_elements = 1;
870 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
871 sizeof(addr->addr_bytes));
873 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
874 args.in_args = cmd_buffer;
875 args.in_args_size = sizeof(cmd_buffer);
876 args.out_buffer = vf->aq_resp;
877 args.out_size = I40E_AQ_BUF_SZ;
878 err = i40evf_execute_vf_cmd(dev, &args);
880 PMD_DRV_LOG(ERR, "fail to execute command "
881 "OP_ADD_ETHER_ADDRESS");
887 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
889 struct i40e_virtchnl_ether_addr_list *list;
890 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
891 struct rte_eth_dev_data *data = dev->data;
892 struct ether_addr *addr;
893 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
894 sizeof(struct i40e_virtchnl_ether_addr)];
896 struct vf_cmd_info args;
898 addr = &(data->mac_addrs[index]);
900 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
901 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
902 addr->addr_bytes[0], addr->addr_bytes[1],
903 addr->addr_bytes[2], addr->addr_bytes[3],
904 addr->addr_bytes[4], addr->addr_bytes[5]);
908 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
909 list->vsi_id = vf->vsi_res->vsi_id;
910 list->num_elements = 1;
911 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
912 sizeof(addr->addr_bytes));
914 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
915 args.in_args = cmd_buffer;
916 args.in_args_size = sizeof(cmd_buffer);
917 args.out_buffer = vf->aq_resp;
918 args.out_size = I40E_AQ_BUF_SZ;
919 err = i40evf_execute_vf_cmd(dev, &args);
921 PMD_DRV_LOG(ERR, "fail to execute command "
922 "OP_DEL_ETHER_ADDRESS");
927 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
929 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
930 struct i40e_virtchnl_queue_select q_stats;
932 struct vf_cmd_info args;
934 memset(&q_stats, 0, sizeof(q_stats));
935 q_stats.vsi_id = vf->vsi_res->vsi_id;
936 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
937 args.in_args = (u8 *)&q_stats;
938 args.in_args_size = sizeof(q_stats);
939 args.out_buffer = vf->aq_resp;
940 args.out_size = I40E_AQ_BUF_SZ;
942 err = i40evf_execute_vf_cmd(dev, &args);
944 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
948 *pstats = (struct i40e_eth_stats *)args.out_buffer;
953 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
956 struct i40e_eth_stats *pstats = NULL;
958 ret = i40evf_update_stats(dev, &pstats);
962 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
963 pstats->rx_broadcast;
964 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
966 stats->ierrors = pstats->rx_discards;
967 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
968 stats->ibytes = pstats->rx_bytes;
969 stats->obytes = pstats->tx_bytes;
975 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
977 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
978 struct i40e_eth_stats *pstats = NULL;
980 /* read stat values to clear hardware registers */
981 i40evf_update_stats(dev, &pstats);
983 /* set stats offset base on current values */
984 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
987 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
988 struct rte_eth_xstats *xstats, unsigned n)
992 struct i40e_eth_stats *pstats = NULL;
994 if (n < I40EVF_NB_XSTATS)
995 return I40EVF_NB_XSTATS;
997 ret = i40evf_update_stats(dev, &pstats);
1004 /* loop over xstats array and values from pstats */
1005 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1006 snprintf(xstats[i].name, sizeof(xstats[i].name),
1007 "%s", rte_i40evf_stats_strings[i].name);
1008 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1009 rte_i40evf_stats_strings[i].offset);
1012 return I40EVF_NB_XSTATS;
1016 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1018 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1019 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1020 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1023 struct vf_cmd_info args;
1025 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1026 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1027 vlan_list->num_elements = 1;
1028 vlan_list->vlan_id[0] = vlanid;
1030 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1031 args.in_args = (u8 *)&cmd_buffer;
1032 args.in_args_size = sizeof(cmd_buffer);
1033 args.out_buffer = vf->aq_resp;
1034 args.out_size = I40E_AQ_BUF_SZ;
1035 err = i40evf_execute_vf_cmd(dev, &args);
1037 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1043 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1045 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1046 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1047 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1050 struct vf_cmd_info args;
1052 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1053 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1054 vlan_list->num_elements = 1;
1055 vlan_list->vlan_id[0] = vlanid;
1057 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1058 args.in_args = (u8 *)&cmd_buffer;
1059 args.in_args_size = sizeof(cmd_buffer);
1060 args.out_buffer = vf->aq_resp;
1061 args.out_size = I40E_AQ_BUF_SZ;
1062 err = i40evf_execute_vf_cmd(dev, &args);
1064 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1070 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1072 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1074 struct vf_cmd_info args;
1075 struct rte_eth_link *new_link;
1077 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1078 args.in_args = NULL;
1079 args.in_args_size = 0;
1080 args.out_buffer = vf->aq_resp;
1081 args.out_size = I40E_AQ_BUF_SZ;
1082 err = i40evf_execute_vf_cmd(dev, &args);
1084 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1088 new_link = (struct rte_eth_link *)args.out_buffer;
1089 (void)rte_memcpy(link, new_link, sizeof(*link));
1094 static const struct rte_pci_id pci_id_i40evf_map[] = {
1095 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1096 #include "rte_pci_dev_ids.h"
1097 { .vendor_id = 0, /* sentinel */ },
1101 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1102 struct rte_eth_link *link)
1104 struct rte_eth_link *dst = &(dev->data->dev_link);
1105 struct rte_eth_link *src = link;
1107 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1108 *(uint64_t *)src) == 0)
1116 i40evf_disable_irq0(struct i40e_hw *hw)
1118 /* Disable all interrupt types */
1119 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1120 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1121 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1122 I40EVF_WRITE_FLUSH(hw);
1127 i40evf_enable_irq0(struct i40e_hw *hw)
1129 /* Enable admin queue interrupt trigger */
1132 i40evf_disable_irq0(hw);
1133 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1134 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1135 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1136 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1138 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1139 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1140 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1141 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1143 I40EVF_WRITE_FLUSH(hw);
1147 i40evf_reset_vf(struct i40e_hw *hw)
1151 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1152 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1156 * After issuing vf reset command to pf, pf won't necessarily
1157 * reset vf, it depends on what state it exactly is. If it's not
1158 * initialized yet, it won't have vf reset since it's in a certain
1159 * state. If not, it will try to reset. Even vf is reset, pf will
1160 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1161 * it to ACTIVE. In this duration, vf may not catch the moment that
1162 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1166 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1167 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1168 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1169 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1170 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1176 if (i >= MAX_RESET_WAIT_CNT) {
1177 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1185 i40evf_init_vf(struct rte_eth_dev *dev)
1188 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1190 struct ether_addr *p_mac_addr;
1192 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1194 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1195 vf->dev_data = dev->data;
1196 err = i40e_set_mac_type(hw);
1198 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1202 i40e_init_adminq_parameter(hw);
1203 err = i40e_init_adminq(hw);
1205 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1209 /* Reset VF and wait until it's complete */
1210 if (i40evf_reset_vf(hw)) {
1211 PMD_INIT_LOG(ERR, "reset NIC failed");
1215 /* VF reset, shutdown admin queue and initialize again */
1216 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1221 i40e_init_adminq_parameter(hw);
1222 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1223 PMD_INIT_LOG(ERR, "init_adminq failed");
1226 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1228 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1231 if (i40evf_check_api_version(dev) != 0) {
1232 PMD_INIT_LOG(ERR, "check_api version failed");
1235 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1236 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1237 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1239 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1243 if (i40evf_get_vf_resource(dev) != 0) {
1244 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1248 /* got VF config message back from PF, now we can parse it */
1249 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1250 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1251 vf->vsi_res = &vf->vf_res->vsi_res[i];
1255 PMD_INIT_LOG(ERR, "no LAN VSI found");
1259 if (hw->mac.type == I40E_MAC_X722_VF)
1260 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1261 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1262 vf->vsi.type = vf->vsi_res->vsi_type;
1263 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1264 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1266 /* Store the MAC address configured by host, or generate random one */
1267 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1268 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1269 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1271 eth_random_addr(hw->mac.addr); /* Generate a random one */
1273 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1274 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1275 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1276 (I40E_ITR_INDEX_DEFAULT <<
1277 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1279 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1280 I40EVF_WRITE_FLUSH(hw);
1286 rte_free(vf->vf_res);
1288 i40e_shutdown_adminq(hw); /* ignore error */
1294 i40evf_uninit_vf(struct rte_eth_dev *dev)
1296 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1297 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299 PMD_INIT_FUNC_TRACE();
1301 if (hw->adapter_stopped == 0)
1302 i40evf_dev_close(dev);
1303 rte_free(vf->vf_res);
1305 rte_free(vf->aq_resp);
1312 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1314 __rte_unused uint16_t msglen)
1316 struct i40e_virtchnl_pf_event *pf_msg =
1317 (struct i40e_virtchnl_pf_event *)msg;
1318 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1320 switch (pf_msg->event) {
1321 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1322 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1323 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
1325 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1326 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1327 vf->link_up = pf_msg->event_data.link_event.link_status;
1328 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1330 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1331 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1334 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1340 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1344 struct i40e_arq_event_info info;
1345 struct i40e_virtchnl_msg *v_msg;
1346 uint16_t pending, opcode;
1349 info.buf_len = I40E_AQ_BUF_SZ;
1351 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1354 info.msg_buf = vf->aq_resp;
1355 v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1359 ret = i40e_clean_arq_element(hw, &info, &pending);
1361 if (ret != I40E_SUCCESS) {
1362 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1366 opcode = rte_le_to_cpu_16(info.desc.opcode);
1369 case i40e_aqc_opc_send_msg_to_vf:
1370 if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1372 i40evf_handle_pf_event(dev, info.msg_buf,
1375 /* read message and it's expected one */
1376 if (v_msg->v_opcode == vf->pend_cmd) {
1377 vf->cmd_retval = v_msg->v_retval;
1378 /* prevent compiler reordering */
1379 rte_compiler_barrier();
1382 PMD_DRV_LOG(ERR, "command mismatch,"
1383 "expect %u, get %u",
1384 vf->pend_cmd, v_msg->v_opcode);
1385 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1386 " opcode = %d\n", v_msg->v_opcode);
1390 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1398 * Interrupt handler triggered by NIC for handling
1399 * specific interrupt. Only adminq interrupt is processed in VF.
1402 * Pointer to interrupt handle.
1404 * The address of parameter (struct rte_eth_dev *) regsitered before.
1410 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1413 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1414 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 i40evf_disable_irq0(hw);
1419 /* read out interrupt causes */
1420 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1422 /* No interrupt event indicated */
1423 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1424 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1428 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1429 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1430 i40evf_handle_aq_msg(dev);
1433 /* Link Status Change interrupt */
1434 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1435 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1439 i40evf_enable_irq0(hw);
1440 rte_intr_enable(&dev->pci_dev->intr_handle);
1444 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1447 eth_dev->data->dev_private);
1448 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1450 PMD_INIT_FUNC_TRACE();
1452 /* assign ops func pointer */
1453 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1454 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1455 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1458 * For secondary processes, we don't initialise any further as primary
1459 * has already done this work.
1461 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1462 i40e_set_rx_function(eth_dev);
1463 i40e_set_tx_function(eth_dev);
1467 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1469 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1470 hw->device_id = eth_dev->pci_dev->id.device_id;
1471 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1472 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1473 hw->bus.device = eth_dev->pci_dev->addr.devid;
1474 hw->bus.func = eth_dev->pci_dev->addr.function;
1475 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1476 hw->adapter_stopped = 0;
1478 if(i40evf_init_vf(eth_dev) != 0) {
1479 PMD_INIT_LOG(ERR, "Init vf failed");
1483 /* register callback func to eal lib */
1484 rte_intr_callback_register(&pci_dev->intr_handle,
1485 i40evf_dev_interrupt_handler, (void *)eth_dev);
1487 /* enable uio intr after callback register */
1488 rte_intr_enable(&pci_dev->intr_handle);
1490 /* configure and enable device interrupt */
1491 i40evf_enable_irq0(hw);
1494 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1495 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1497 if (eth_dev->data->mac_addrs == NULL) {
1498 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1499 " store MAC addresses",
1500 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1503 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1504 ð_dev->data->mac_addrs[0]);
1510 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1512 PMD_INIT_FUNC_TRACE();
1514 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1517 eth_dev->dev_ops = NULL;
1518 eth_dev->rx_pkt_burst = NULL;
1519 eth_dev->tx_pkt_burst = NULL;
1521 if (i40evf_uninit_vf(eth_dev) != 0) {
1522 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1526 rte_free(eth_dev->data->mac_addrs);
1527 eth_dev->data->mac_addrs = NULL;
1532 * virtual function driver struct
1534 static struct eth_driver rte_i40evf_pmd = {
1536 .name = "rte_i40evf_pmd",
1537 .id_table = pci_id_i40evf_map,
1538 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1540 .eth_dev_init = i40evf_dev_init,
1541 .eth_dev_uninit = i40evf_dev_uninit,
1542 .dev_private_size = sizeof(struct i40e_adapter),
1546 * VF Driver initialization routine.
1547 * Invoked one at EAL init time.
1548 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1551 rte_i40evf_pmd_init(const char *name __rte_unused,
1552 const char *params __rte_unused)
1554 PMD_INIT_FUNC_TRACE();
1556 rte_eth_driver_register(&rte_i40evf_pmd);
1561 static struct rte_driver rte_i40evf_driver = {
1563 .init = rte_i40evf_pmd_init,
1566 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1569 i40evf_dev_configure(struct rte_eth_dev *dev)
1571 struct i40e_adapter *ad =
1572 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1573 struct rte_eth_conf *conf = &dev->data->dev_conf;
1576 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1577 * allocation or vector Rx preconditions we will reset it.
1579 ad->rx_bulk_alloc_allowed = true;
1580 ad->rx_vec_allowed = true;
1581 ad->tx_simple_allowed = true;
1582 ad->tx_vec_allowed = true;
1584 /* For non-DPDK PF drivers, VF has no ability to disable HW
1585 * CRC strip, and is implicitly enabled by the PF.
1587 if (!conf->rxmode.hw_strip_crc) {
1588 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1589 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1590 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1591 /* Peer is running non-DPDK PF driver. */
1592 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1597 return i40evf_init_vlan(dev);
1601 i40evf_init_vlan(struct rte_eth_dev *dev)
1603 struct rte_eth_dev_data *data = dev->data;
1606 /* Apply vlan offload setting */
1607 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1609 /* Apply pvid setting */
1610 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1611 data->dev_conf.txmode.hw_vlan_insert_pvid);
1616 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1618 bool enable_vlan_strip = 0;
1619 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1620 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1622 /* Linux pf host doesn't support vlan offload yet */
1623 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1624 /* Vlan stripping setting */
1625 if (mask & ETH_VLAN_STRIP_MASK) {
1626 /* Enable or disable VLAN stripping */
1627 if (dev_conf->rxmode.hw_vlan_strip)
1628 enable_vlan_strip = 1;
1630 enable_vlan_strip = 0;
1632 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1638 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1640 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1641 struct i40e_vsi_vlan_pvid_info info;
1642 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1644 memset(&info, 0, sizeof(info));
1647 /* Linux pf host don't support vlan offload yet */
1648 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1650 info.config.pvid = pvid;
1652 info.config.reject.tagged =
1653 dev_conf->txmode.hw_vlan_reject_tagged;
1654 info.config.reject.untagged =
1655 dev_conf->txmode.hw_vlan_reject_untagged;
1657 return i40evf_config_vlan_pvid(dev, &info);
1664 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1666 struct i40e_rx_queue *rxq;
1668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670 PMD_INIT_FUNC_TRACE();
1672 if (rx_queue_id < dev->data->nb_rx_queues) {
1673 rxq = dev->data->rx_queues[rx_queue_id];
1675 err = i40e_alloc_rx_queue_mbufs(rxq);
1677 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1683 /* Init the RX tail register. */
1684 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1685 I40EVF_WRITE_FLUSH(hw);
1687 /* Ready to switch the queue on */
1688 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1691 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1694 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1701 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1703 struct i40e_rx_queue *rxq;
1706 if (rx_queue_id < dev->data->nb_rx_queues) {
1707 rxq = dev->data->rx_queues[rx_queue_id];
1709 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1712 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1717 i40e_rx_queue_release_mbufs(rxq);
1718 i40e_reset_rx_queue(rxq);
1719 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1726 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1730 PMD_INIT_FUNC_TRACE();
1732 if (tx_queue_id < dev->data->nb_tx_queues) {
1734 /* Ready to switch the queue on */
1735 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1738 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1741 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1748 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1750 struct i40e_tx_queue *txq;
1753 if (tx_queue_id < dev->data->nb_tx_queues) {
1754 txq = dev->data->tx_queues[tx_queue_id];
1756 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1759 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1764 i40e_tx_queue_release_mbufs(txq);
1765 i40e_reset_tx_queue(txq);
1766 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1773 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1778 ret = i40evf_add_vlan(dev, vlan_id);
1780 ret = i40evf_del_vlan(dev,vlan_id);
1786 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1788 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789 struct rte_eth_dev_data *dev_data = dev->data;
1790 struct rte_pktmbuf_pool_private *mbp_priv;
1791 uint16_t buf_size, len;
1793 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1794 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1795 I40EVF_WRITE_FLUSH(hw);
1797 /* Calculate the maximum packet length allowed */
1798 mbp_priv = rte_mempool_get_priv(rxq->mp);
1799 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1800 RTE_PKTMBUF_HEADROOM);
1801 rxq->hs_mode = i40e_header_split_none;
1802 rxq->rx_hdr_len = 0;
1803 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1804 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1805 rxq->max_pkt_len = RTE_MIN(len,
1806 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1809 * Check if the jumbo frame and maximum packet length are set correctly
1811 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1812 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1813 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1814 PMD_DRV_LOG(ERR, "maximum packet length must be "
1815 "larger than %u and smaller than %u, as jumbo "
1816 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1817 (uint32_t)I40E_FRAME_SIZE_MAX);
1818 return I40E_ERR_CONFIG;
1821 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1822 rxq->max_pkt_len > ETHER_MAX_LEN) {
1823 PMD_DRV_LOG(ERR, "maximum packet length must be "
1824 "larger than %u and smaller than %u, as jumbo "
1825 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1826 (uint32_t)ETHER_MAX_LEN);
1827 return I40E_ERR_CONFIG;
1831 if (dev_data->dev_conf.rxmode.enable_scatter ||
1832 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1833 dev_data->scattered_rx = 1;
1840 i40evf_rx_init(struct rte_eth_dev *dev)
1842 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1844 int ret = I40E_SUCCESS;
1845 struct i40e_rx_queue **rxq =
1846 (struct i40e_rx_queue **)dev->data->rx_queues;
1848 i40evf_config_rss(vf);
1849 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1850 if (!rxq[i] || !rxq[i]->q_set)
1852 ret = i40evf_rxq_init(dev, rxq[i]);
1853 if (ret != I40E_SUCCESS)
1856 if (ret == I40E_SUCCESS)
1857 i40e_set_rx_function(dev);
1863 i40evf_tx_init(struct rte_eth_dev *dev)
1866 struct i40e_tx_queue **txq =
1867 (struct i40e_tx_queue **)dev->data->tx_queues;
1868 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870 for (i = 0; i < dev->data->nb_tx_queues; i++)
1871 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1873 i40e_set_tx_function(dev);
1877 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1879 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1883 if (!rte_intr_allow_others(intr_handle)) {
1885 I40E_VFINT_DYN_CTL01,
1886 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1887 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1888 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1889 I40EVF_WRITE_FLUSH(hw);
1893 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1894 /* To support DPDK PF host */
1896 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1897 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1898 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1899 /* If host driver is kernel driver, do nothing.
1900 * Interrupt 0 is used for rx packets, but don't set
1901 * I40E_VFINT_DYN_CTL01,
1902 * because it is already done in i40evf_enable_irq0.
1905 I40EVF_WRITE_FLUSH(hw);
1909 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1911 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1915 if (!rte_intr_allow_others(intr_handle)) {
1916 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1917 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1918 I40EVF_WRITE_FLUSH(hw);
1922 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1924 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1927 /* If host driver is kernel driver, do nothing.
1928 * Interrupt 0 is used for rx packets, but don't zero
1929 * I40E_VFINT_DYN_CTL01,
1930 * because interrupt 0 is also used for adminq processing.
1933 I40EVF_WRITE_FLUSH(hw);
1937 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1939 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1945 msix_intr = intr_handle->intr_vec[queue_id];
1946 if (msix_intr == I40E_MISC_VEC_ID)
1947 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1948 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1949 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1950 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1952 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1955 I40E_VFINT_DYN_CTLN1(msix_intr -
1957 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1958 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1959 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1961 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1963 I40EVF_WRITE_FLUSH(hw);
1965 rte_intr_enable(&dev->pci_dev->intr_handle);
1971 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1973 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977 msix_intr = intr_handle->intr_vec[queue_id];
1978 if (msix_intr == I40E_MISC_VEC_ID)
1979 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1982 I40E_VFINT_DYN_CTLN1(msix_intr -
1986 I40EVF_WRITE_FLUSH(hw);
1992 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1994 struct i40e_virtchnl_ether_addr_list *list;
1995 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2000 struct ether_addr *addr;
2001 struct vf_cmd_info args;
2005 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2006 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2007 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2009 len += sizeof(struct i40e_virtchnl_ether_addr);
2010 if (len >= I40E_AQ_BUF_SZ) {
2016 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2018 for (i = begin; i < next_begin; i++) {
2019 addr = &dev->data->mac_addrs[i];
2020 if (is_zero_ether_addr(addr))
2022 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2023 sizeof(addr->addr_bytes));
2024 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2025 addr->addr_bytes[0], addr->addr_bytes[1],
2026 addr->addr_bytes[2], addr->addr_bytes[3],
2027 addr->addr_bytes[4], addr->addr_bytes[5]);
2030 list->vsi_id = vf->vsi_res->vsi_id;
2031 list->num_elements = j;
2032 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2033 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2034 args.in_args = (uint8_t *)list;
2035 args.in_args_size = len;
2036 args.out_buffer = vf->aq_resp;
2037 args.out_size = I40E_AQ_BUF_SZ;
2038 err = i40evf_execute_vf_cmd(dev, &args);
2040 PMD_DRV_LOG(ERR, "fail to execute command %s",
2041 add ? "OP_ADD_ETHER_ADDRESS" :
2042 "OP_DEL_ETHER_ADDRESS");
2045 } while (begin < I40E_NUM_MACADDR_MAX);
2049 i40evf_dev_start(struct rte_eth_dev *dev)
2051 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2052 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2054 uint32_t intr_vector = 0;
2056 PMD_INIT_FUNC_TRACE();
2058 hw->adapter_stopped = 0;
2060 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2061 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2062 dev->data->nb_tx_queues);
2064 /* check and configure queue intr-vector mapping */
2065 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2066 intr_vector = dev->data->nb_rx_queues;
2067 if (rte_intr_efd_enable(intr_handle, intr_vector))
2071 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2072 intr_handle->intr_vec =
2073 rte_zmalloc("intr_vec",
2074 dev->data->nb_rx_queues * sizeof(int), 0);
2075 if (!intr_handle->intr_vec) {
2076 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2077 " intr_vec\n", dev->data->nb_rx_queues);
2082 if (i40evf_rx_init(dev) != 0){
2083 PMD_DRV_LOG(ERR, "failed to do RX init");
2087 i40evf_tx_init(dev);
2089 if (i40evf_configure_queues(dev) != 0) {
2090 PMD_DRV_LOG(ERR, "configure queues failed");
2093 if (i40evf_config_irq_map(dev)) {
2094 PMD_DRV_LOG(ERR, "config_irq_map failed");
2098 /* Set all mac addrs */
2099 i40evf_add_del_all_mac_addr(dev, TRUE);
2101 if (i40evf_start_queues(dev) != 0) {
2102 PMD_DRV_LOG(ERR, "enable queues failed");
2106 i40evf_enable_queues_intr(dev);
2110 i40evf_add_del_all_mac_addr(dev, FALSE);
2116 i40evf_dev_stop(struct rte_eth_dev *dev)
2118 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2120 PMD_INIT_FUNC_TRACE();
2122 i40evf_stop_queues(dev);
2123 i40evf_disable_queues_intr(dev);
2124 i40e_dev_clear_queues(dev);
2126 /* Clean datapath event and queue/vec mapping */
2127 rte_intr_efd_disable(intr_handle);
2128 if (intr_handle->intr_vec) {
2129 rte_free(intr_handle->intr_vec);
2130 intr_handle->intr_vec = NULL;
2132 /* remove all mac addrs */
2133 i40evf_add_del_all_mac_addr(dev, FALSE);
2138 i40evf_dev_link_update(struct rte_eth_dev *dev,
2139 __rte_unused int wait_to_complete)
2141 struct rte_eth_link new_link;
2142 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2144 * DPDK pf host provide interfacet to acquire link status
2145 * while Linux driver does not
2147 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
2148 i40evf_get_link_status(dev, &new_link);
2150 /* Linux driver PF host */
2151 switch (vf->link_speed) {
2152 case I40E_LINK_SPEED_100MB:
2153 new_link.link_speed = ETH_SPEED_NUM_100M;
2155 case I40E_LINK_SPEED_1GB:
2156 new_link.link_speed = ETH_SPEED_NUM_1G;
2158 case I40E_LINK_SPEED_10GB:
2159 new_link.link_speed = ETH_SPEED_NUM_10G;
2161 case I40E_LINK_SPEED_20GB:
2162 new_link.link_speed = ETH_SPEED_NUM_20G;
2164 case I40E_LINK_SPEED_40GB:
2165 new_link.link_speed = ETH_SPEED_NUM_40G;
2168 new_link.link_speed = ETH_SPEED_NUM_100M;
2171 /* full duplex only */
2172 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2173 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2176 i40evf_dev_atomic_write_link_status(dev, &new_link);
2182 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2184 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2187 /* If enabled, just return */
2188 if (vf->promisc_unicast_enabled)
2191 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2193 vf->promisc_unicast_enabled = TRUE;
2197 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2202 /* If disabled, just return */
2203 if (!vf->promisc_unicast_enabled)
2206 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2208 vf->promisc_unicast_enabled = FALSE;
2212 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2214 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2217 /* If enabled, just return */
2218 if (vf->promisc_multicast_enabled)
2221 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2223 vf->promisc_multicast_enabled = TRUE;
2227 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2232 /* If enabled, just return */
2233 if (!vf->promisc_multicast_enabled)
2236 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2238 vf->promisc_multicast_enabled = FALSE;
2242 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2244 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2246 memset(dev_info, 0, sizeof(*dev_info));
2247 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2248 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2249 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2250 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2251 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2252 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2253 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2254 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2255 dev_info->rx_offload_capa =
2256 DEV_RX_OFFLOAD_VLAN_STRIP |
2257 DEV_RX_OFFLOAD_QINQ_STRIP |
2258 DEV_RX_OFFLOAD_IPV4_CKSUM |
2259 DEV_RX_OFFLOAD_UDP_CKSUM |
2260 DEV_RX_OFFLOAD_TCP_CKSUM;
2261 dev_info->tx_offload_capa =
2262 DEV_TX_OFFLOAD_VLAN_INSERT |
2263 DEV_TX_OFFLOAD_QINQ_INSERT |
2264 DEV_TX_OFFLOAD_IPV4_CKSUM |
2265 DEV_TX_OFFLOAD_UDP_CKSUM |
2266 DEV_TX_OFFLOAD_TCP_CKSUM |
2267 DEV_TX_OFFLOAD_SCTP_CKSUM;
2269 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2271 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2272 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2273 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2275 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2279 dev_info->default_txconf = (struct rte_eth_txconf) {
2281 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2282 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2283 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2285 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2286 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2287 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2288 ETH_TXQ_FLAGS_NOOFFLOADS,
2291 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2292 .nb_max = I40E_MAX_RING_DESC,
2293 .nb_min = I40E_MIN_RING_DESC,
2294 .nb_align = I40E_ALIGN_RING_DESC,
2297 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2298 .nb_max = I40E_MAX_RING_DESC,
2299 .nb_min = I40E_MIN_RING_DESC,
2300 .nb_align = I40E_ALIGN_RING_DESC,
2305 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2307 if (i40evf_get_statics(dev, stats))
2308 PMD_DRV_LOG(ERR, "Get statics failed");
2312 i40evf_dev_close(struct rte_eth_dev *dev)
2314 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315 struct rte_pci_device *pci_dev = dev->pci_dev;
2317 i40evf_dev_stop(dev);
2318 hw->adapter_stopped = 1;
2319 i40e_dev_free_queues(dev);
2320 i40evf_reset_vf(hw);
2321 i40e_shutdown_adminq(hw);
2322 /* disable uio intr before callback unregister */
2323 rte_intr_disable(&pci_dev->intr_handle);
2325 /* unregister callback func from eal lib */
2326 rte_intr_callback_unregister(&pci_dev->intr_handle,
2327 i40evf_dev_interrupt_handler, (void *)dev);
2328 i40evf_disable_irq0(hw);
2332 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2334 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2335 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2341 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2342 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2345 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2349 uint32_t *lut_dw = (uint32_t *)lut;
2350 uint16_t i, lut_size_dw = lut_size / 4;
2352 for (i = 0; i < lut_size_dw; i++)
2353 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2360 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2362 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2363 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2369 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2370 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2373 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2377 uint32_t *lut_dw = (uint32_t *)lut;
2378 uint16_t i, lut_size_dw = lut_size / 4;
2380 for (i = 0; i < lut_size_dw; i++)
2381 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2382 I40EVF_WRITE_FLUSH(hw);
2389 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2390 struct rte_eth_rss_reta_entry64 *reta_conf,
2393 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2395 uint16_t i, idx, shift;
2398 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2399 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2400 "(%d) doesn't match the number of hardware can "
2401 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2405 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2407 PMD_DRV_LOG(ERR, "No memory can be allocated");
2410 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2413 for (i = 0; i < reta_size; i++) {
2414 idx = i / RTE_RETA_GROUP_SIZE;
2415 shift = i % RTE_RETA_GROUP_SIZE;
2416 if (reta_conf[idx].mask & (1ULL << shift))
2417 lut[i] = reta_conf[idx].reta[shift];
2419 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2428 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2429 struct rte_eth_rss_reta_entry64 *reta_conf,
2432 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2433 uint16_t i, idx, shift;
2437 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2438 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2439 "(%d) doesn't match the number of hardware can "
2440 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2444 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2446 PMD_DRV_LOG(ERR, "No memory can be allocated");
2450 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2453 for (i = 0; i < reta_size; i++) {
2454 idx = i / RTE_RETA_GROUP_SIZE;
2455 shift = i % RTE_RETA_GROUP_SIZE;
2456 if (reta_conf[idx].mask & (1ULL << shift))
2457 reta_conf[idx].reta[shift] = lut[i];
2467 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2469 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2470 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2473 if (!key || key_len == 0) {
2474 PMD_DRV_LOG(DEBUG, "No key to be configured");
2476 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2478 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2482 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2483 struct i40e_aqc_get_set_rss_key_data *key_dw =
2484 (struct i40e_aqc_get_set_rss_key_data *)key;
2486 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2488 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2491 uint32_t *hash_key = (uint32_t *)key;
2494 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2495 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2496 I40EVF_WRITE_FLUSH(hw);
2503 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2505 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2506 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2509 if (!key || !key_len)
2512 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2513 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2514 (struct i40e_aqc_get_set_rss_key_data *)key);
2516 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2520 uint32_t *key_dw = (uint32_t *)key;
2523 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2524 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2526 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2532 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2534 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2535 uint64_t rss_hf, hena;
2538 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2539 rss_conf->rss_key_len);
2543 rss_hf = rss_conf->rss_hf;
2544 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2545 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2546 hena &= ~I40E_RSS_HENA_ALL;
2547 hena |= i40e_config_hena(rss_hf);
2548 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2549 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2550 I40EVF_WRITE_FLUSH(hw);
2556 i40evf_disable_rss(struct i40e_vf *vf)
2558 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2561 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2562 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2563 hena &= ~I40E_RSS_HENA_ALL;
2564 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2565 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2566 I40EVF_WRITE_FLUSH(hw);
2570 i40evf_config_rss(struct i40e_vf *vf)
2572 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2573 struct rte_eth_rss_conf rss_conf;
2574 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2577 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2578 i40evf_disable_rss(vf);
2579 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2583 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2584 /* Fill out the look up table */
2585 for (i = 0, j = 0; i < nb_q; i++, j++) {
2588 lut = (lut << 8) | j;
2590 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2593 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2594 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2595 i40evf_disable_rss(vf);
2596 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2600 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2601 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2602 /* Calculate the default hash key */
2603 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2604 rss_key_default[i] = (uint32_t)rte_rand();
2605 rss_conf.rss_key = (uint8_t *)rss_key_default;
2606 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2610 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2614 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2615 struct rte_eth_rss_conf *rss_conf)
2617 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2618 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2622 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2623 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2624 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2625 if (rss_hf != 0) /* Enable RSS */
2631 if (rss_hf == 0) /* Disable RSS */
2634 return i40evf_hw_rss_hash_set(vf, rss_conf);
2638 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2639 struct rte_eth_rss_conf *rss_conf)
2641 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2646 &rss_conf->rss_key_len);
2648 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2649 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2650 rss_conf->rss_hf = i40e_parse_hena(hena);