4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstats *xstats, unsigned n);
115 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
116 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
119 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
121 static void i40evf_dev_close(struct rte_eth_dev *dev);
122 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40evf_get_link_status(struct rte_eth_dev *dev,
127 struct rte_eth_link *link);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
157 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
161 /* Default hash key buffer for RSS */
162 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
164 struct rte_i40evf_xstats_name_off {
165 char name[RTE_ETH_XSTATS_NAME_SIZE];
169 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
170 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
171 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
172 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
173 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
174 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
175 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
176 rx_unknown_protocol)},
177 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
178 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
179 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
180 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
185 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
186 sizeof(rte_i40evf_stats_strings[0]))
188 static const struct eth_dev_ops i40evf_eth_dev_ops = {
189 .dev_configure = i40evf_dev_configure,
190 .dev_start = i40evf_dev_start,
191 .dev_stop = i40evf_dev_stop,
192 .promiscuous_enable = i40evf_dev_promiscuous_enable,
193 .promiscuous_disable = i40evf_dev_promiscuous_disable,
194 .allmulticast_enable = i40evf_dev_allmulticast_enable,
195 .allmulticast_disable = i40evf_dev_allmulticast_disable,
196 .link_update = i40evf_dev_link_update,
197 .stats_get = i40evf_dev_stats_get,
198 .xstats_get = i40evf_dev_xstats_get,
199 .xstats_reset = i40evf_dev_xstats_reset,
200 .dev_close = i40evf_dev_close,
201 .dev_infos_get = i40evf_dev_info_get,
202 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
203 .vlan_filter_set = i40evf_vlan_filter_set,
204 .vlan_offload_set = i40evf_vlan_offload_set,
205 .vlan_pvid_set = i40evf_vlan_pvid_set,
206 .rx_queue_start = i40evf_dev_rx_queue_start,
207 .rx_queue_stop = i40evf_dev_rx_queue_stop,
208 .tx_queue_start = i40evf_dev_tx_queue_start,
209 .tx_queue_stop = i40evf_dev_tx_queue_stop,
210 .rx_queue_setup = i40e_dev_rx_queue_setup,
211 .rx_queue_release = i40e_dev_rx_queue_release,
212 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
213 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
214 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
215 .tx_queue_setup = i40e_dev_tx_queue_setup,
216 .tx_queue_release = i40e_dev_tx_queue_release,
217 .mac_addr_add = i40evf_add_mac_addr,
218 .mac_addr_remove = i40evf_del_mac_addr,
219 .reta_update = i40evf_dev_rss_reta_update,
220 .reta_query = i40evf_dev_rss_reta_query,
221 .rss_hash_update = i40evf_dev_rss_hash_update,
222 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
226 * Read data in admin queue to get msg from pf driver
228 static enum i40evf_aq_result
229 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
232 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
233 struct i40e_arq_event_info event;
234 enum i40e_virtchnl_ops opcode;
235 enum i40e_status_code retval;
237 enum i40evf_aq_result result = I40EVF_MSG_NON;
239 event.buf_len = data->buf_len;
240 event.msg_buf = data->msg;
241 ret = i40e_clean_arq_element(hw, &event, NULL);
242 /* Can't read any msg from adminQ */
244 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
245 result = I40EVF_MSG_ERR;
249 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
250 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
252 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
253 struct i40e_virtchnl_pf_event *vpe =
254 (struct i40e_virtchnl_pf_event *)event.msg_buf;
256 result = I40EVF_MSG_SYS;
257 switch (vpe->event) {
258 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
260 vpe->event_data.link_event.link_status;
261 vf->pend_msg |= PFMSG_LINK_CHANGE;
262 PMD_DRV_LOG(INFO, "Link status update:%s",
263 vf->link_up ? "up" : "down");
265 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
267 vf->pend_msg |= PFMSG_RESET_IMPENDING;
268 PMD_DRV_LOG(INFO, "vf is reseting");
270 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
271 vf->dev_closed = true;
272 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
273 PMD_DRV_LOG(INFO, "PF driver closed");
276 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
277 __func__, vpe->event);
280 /* async reply msg on command issued by vf previously */
281 result = I40EVF_MSG_CMD;
282 /* Actual data length read from PF */
283 data->msg_len = event.msg_len;
286 data->result = retval;
293 * clear current command. Only call in case execute
294 * _atomic_set_cmd successfully.
297 _clear_cmd(struct i40e_vf *vf)
300 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
304 * Check there is pending cmd in execution. If none, set new command.
307 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
309 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
310 I40E_VIRTCHNL_OP_UNKNOWN, ops);
313 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
318 #define MAX_TRY_TIMES 200
319 #define ASQ_DELAY_MS 10
322 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
324 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
325 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
326 struct i40evf_arq_msg_info info;
327 enum i40evf_aq_result ret;
331 if (_atomic_set_cmd(vf, args->ops))
334 info.msg = args->out_buffer;
335 info.buf_len = args->out_size;
336 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
337 info.result = I40E_SUCCESS;
339 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
340 args->in_args, args->in_args_size, NULL);
342 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
348 case I40E_VIRTCHNL_OP_RESET_VF:
349 /*no need to process in this function */
351 case I40E_VIRTCHNL_OP_VERSION:
352 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
353 /* for init adminq commands, need to poll the response */
355 ret = i40evf_read_pfmsg(dev, &info);
356 if (ret == I40EVF_MSG_CMD) {
359 } else if (ret == I40EVF_MSG_ERR) {
363 rte_delay_ms(ASQ_DELAY_MS);
364 /* If don't read msg or read sys event, continue */
365 } while (i++ < MAX_TRY_TIMES);
370 /* for other adminq in running time, waiting the cmd done flag */
372 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
376 rte_delay_ms(ASQ_DELAY_MS);
377 /* If don't read msg or read sys event, continue */
378 } while (i++ < MAX_TRY_TIMES);
382 return err | vf->cmd_retval;
386 * Check API version with sync wait until version read or fail from admin queue
389 i40evf_check_api_version(struct rte_eth_dev *dev)
391 struct i40e_virtchnl_version_info version, *pver;
393 struct vf_cmd_info args;
394 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
396 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
397 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
399 args.ops = I40E_VIRTCHNL_OP_VERSION;
400 args.in_args = (uint8_t *)&version;
401 args.in_args_size = sizeof(version);
402 args.out_buffer = vf->aq_resp;
403 args.out_size = I40E_AQ_BUF_SZ;
405 err = i40evf_execute_vf_cmd(dev, &args);
407 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
411 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
412 vf->version_major = pver->major;
413 vf->version_minor = pver->minor;
414 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
415 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
416 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
417 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
418 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
420 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
421 vf->version_major, vf->version_minor,
422 I40E_VIRTCHNL_VERSION_MAJOR,
423 I40E_VIRTCHNL_VERSION_MINOR);
431 i40evf_get_vf_resource(struct rte_eth_dev *dev)
433 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
434 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
436 struct vf_cmd_info args;
439 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
440 args.out_buffer = vf->aq_resp;
441 args.out_size = I40E_AQ_BUF_SZ;
443 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
444 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
445 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
446 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
447 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
448 args.in_args = (uint8_t *)∩︀
449 args.in_args_size = sizeof(caps);
452 args.in_args_size = 0;
454 err = i40evf_execute_vf_cmd(dev, &args);
457 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
461 len = sizeof(struct i40e_virtchnl_vf_resource) +
462 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
464 (void)rte_memcpy(vf->vf_res, args.out_buffer,
465 RTE_MIN(args.out_size, len));
466 i40e_vf_parse_hw_config(hw, vf->vf_res);
472 i40evf_config_promisc(struct rte_eth_dev *dev,
474 bool enable_multicast)
476 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
478 struct vf_cmd_info args;
479 struct i40e_virtchnl_promisc_info promisc;
482 promisc.vsi_id = vf->vsi_res->vsi_id;
485 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
487 if (enable_multicast)
488 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
490 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
491 args.in_args = (uint8_t *)&promisc;
492 args.in_args_size = sizeof(promisc);
493 args.out_buffer = vf->aq_resp;
494 args.out_size = I40E_AQ_BUF_SZ;
496 err = i40evf_execute_vf_cmd(dev, &args);
499 PMD_DRV_LOG(ERR, "fail to execute command "
500 "CONFIG_PROMISCUOUS_MODE");
504 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
506 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
507 bool enable_vlan_strip)
509 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
511 struct vf_cmd_info args;
512 struct i40e_virtchnl_vlan_offload_info offload;
514 offload.vsi_id = vf->vsi_res->vsi_id;
515 offload.enable_vlan_strip = enable_vlan_strip;
517 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
518 args.in_args = (uint8_t *)&offload;
519 args.in_args_size = sizeof(offload);
520 args.out_buffer = vf->aq_resp;
521 args.out_size = I40E_AQ_BUF_SZ;
523 err = i40evf_execute_vf_cmd(dev, &args);
525 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
531 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
532 struct i40e_vsi_vlan_pvid_info *info)
534 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
536 struct vf_cmd_info args;
537 struct i40e_virtchnl_pvid_info tpid_info;
539 if (dev == NULL || info == NULL) {
540 PMD_DRV_LOG(ERR, "invalid parameters");
541 return I40E_ERR_PARAM;
544 memset(&tpid_info, 0, sizeof(tpid_info));
545 tpid_info.vsi_id = vf->vsi_res->vsi_id;
546 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
548 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
549 args.in_args = (uint8_t *)&tpid_info;
550 args.in_args_size = sizeof(tpid_info);
551 args.out_buffer = vf->aq_resp;
552 args.out_size = I40E_AQ_BUF_SZ;
554 err = i40evf_execute_vf_cmd(dev, &args);
556 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
562 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
566 struct i40e_tx_queue *txq)
568 txq_info->vsi_id = vsi_id;
569 txq_info->queue_id = queue_id;
570 if (queue_id < nb_txq) {
571 txq_info->ring_len = txq->nb_tx_desc;
572 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
577 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
581 uint32_t max_pkt_size,
582 struct i40e_rx_queue *rxq)
584 rxq_info->vsi_id = vsi_id;
585 rxq_info->queue_id = queue_id;
586 rxq_info->max_pkt_size = max_pkt_size;
587 if (queue_id < nb_rxq) {
588 rxq_info->ring_len = rxq->nb_rx_desc;
589 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
590 rxq_info->databuffer_size =
591 (rte_pktmbuf_data_room_size(rxq->mp) -
592 RTE_PKTMBUF_HEADROOM);
596 /* It configures VSI queues to co-work with Linux PF host */
598 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
600 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
601 struct i40e_rx_queue **rxq =
602 (struct i40e_rx_queue **)dev->data->rx_queues;
603 struct i40e_tx_queue **txq =
604 (struct i40e_tx_queue **)dev->data->tx_queues;
605 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
606 struct i40e_virtchnl_queue_pair_info *vc_qpi;
607 struct vf_cmd_info args;
608 uint16_t i, nb_qp = vf->num_queue_pairs;
609 const uint32_t size =
610 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
614 memset(buff, 0, sizeof(buff));
615 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
616 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
617 vc_vqci->num_queue_pairs = nb_qp;
619 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
620 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
621 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
622 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
623 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
624 vf->max_pkt_len, rxq[i]);
626 memset(&args, 0, sizeof(args));
627 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
628 args.in_args = (uint8_t *)vc_vqci;
629 args.in_args_size = size;
630 args.out_buffer = vf->aq_resp;
631 args.out_size = I40E_AQ_BUF_SZ;
632 ret = i40evf_execute_vf_cmd(dev, &args);
634 PMD_DRV_LOG(ERR, "Failed to execute command of "
635 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
640 /* It configures VSI queues to co-work with DPDK PF host */
642 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
644 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
645 struct i40e_rx_queue **rxq =
646 (struct i40e_rx_queue **)dev->data->rx_queues;
647 struct i40e_tx_queue **txq =
648 (struct i40e_tx_queue **)dev->data->tx_queues;
649 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
650 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
651 struct vf_cmd_info args;
652 uint16_t i, nb_qp = vf->num_queue_pairs;
653 const uint32_t size =
654 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
658 memset(buff, 0, sizeof(buff));
659 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
660 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
661 vc_vqcei->num_queue_pairs = nb_qp;
662 vc_qpei = vc_vqcei->qpair;
663 for (i = 0; i < nb_qp; i++, vc_qpei++) {
664 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
665 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
666 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
667 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
668 vf->max_pkt_len, rxq[i]);
669 if (i < dev->data->nb_rx_queues)
671 * It adds extra info for configuring VSI queues, which
672 * is needed to enable the configurable crc stripping
675 vc_qpei->rxq_ext.crcstrip =
676 dev->data->dev_conf.rxmode.hw_strip_crc;
678 memset(&args, 0, sizeof(args));
680 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
681 args.in_args = (uint8_t *)vc_vqcei;
682 args.in_args_size = size;
683 args.out_buffer = vf->aq_resp;
684 args.out_size = I40E_AQ_BUF_SZ;
685 ret = i40evf_execute_vf_cmd(dev, &args);
687 PMD_DRV_LOG(ERR, "Failed to execute command of "
688 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
694 i40evf_configure_queues(struct rte_eth_dev *dev)
696 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
698 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
699 /* To support DPDK PF host */
700 return i40evf_configure_vsi_queues_ext(dev);
702 /* To support Linux PF host */
703 return i40evf_configure_vsi_queues(dev);
707 i40evf_config_irq_map(struct rte_eth_dev *dev)
709 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
710 struct vf_cmd_info args;
711 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
712 sizeof(struct i40e_virtchnl_vector_map)];
713 struct i40e_virtchnl_irq_map_info *map_info;
714 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
718 if (rte_intr_allow_others(intr_handle)) {
719 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
720 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
722 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
724 vector_id = I40E_MISC_VEC_ID;
727 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
728 map_info->num_vectors = 1;
729 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
730 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
731 /* Alway use default dynamic MSIX interrupt */
732 map_info->vecmap[0].vector_id = vector_id;
733 /* Don't map any tx queue */
734 map_info->vecmap[0].txq_map = 0;
735 map_info->vecmap[0].rxq_map = 0;
736 for (i = 0; i < dev->data->nb_rx_queues; i++) {
737 map_info->vecmap[0].rxq_map |= 1 << i;
738 if (rte_intr_dp_is_en(intr_handle))
739 intr_handle->intr_vec[i] = vector_id;
742 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
743 args.in_args = (u8 *)cmd_buffer;
744 args.in_args_size = sizeof(cmd_buffer);
745 args.out_buffer = vf->aq_resp;
746 args.out_size = I40E_AQ_BUF_SZ;
747 err = i40evf_execute_vf_cmd(dev, &args);
749 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
755 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
758 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
759 struct i40e_virtchnl_queue_select queue_select;
761 struct vf_cmd_info args;
762 memset(&queue_select, 0, sizeof(queue_select));
763 queue_select.vsi_id = vf->vsi_res->vsi_id;
766 queue_select.rx_queues |= 1 << qid;
768 queue_select.tx_queues |= 1 << qid;
771 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
773 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
774 args.in_args = (u8 *)&queue_select;
775 args.in_args_size = sizeof(queue_select);
776 args.out_buffer = vf->aq_resp;
777 args.out_size = I40E_AQ_BUF_SZ;
778 err = i40evf_execute_vf_cmd(dev, &args);
780 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
781 isrx ? "RX" : "TX", qid, on ? "on" : "off");
787 i40evf_start_queues(struct rte_eth_dev *dev)
789 struct rte_eth_dev_data *dev_data = dev->data;
791 struct i40e_rx_queue *rxq;
792 struct i40e_tx_queue *txq;
794 for (i = 0; i < dev->data->nb_rx_queues; i++) {
795 rxq = dev_data->rx_queues[i];
796 if (rxq->rx_deferred_start)
798 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
799 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
804 for (i = 0; i < dev->data->nb_tx_queues; i++) {
805 txq = dev_data->tx_queues[i];
806 if (txq->tx_deferred_start)
808 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
809 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
818 i40evf_stop_queues(struct rte_eth_dev *dev)
822 /* Stop TX queues first */
823 for (i = 0; i < dev->data->nb_tx_queues; i++) {
824 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
825 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
830 /* Then stop RX queues */
831 for (i = 0; i < dev->data->nb_rx_queues; i++) {
832 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
833 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
842 i40evf_add_mac_addr(struct rte_eth_dev *dev,
843 struct ether_addr *addr,
844 __rte_unused uint32_t index,
845 __rte_unused uint32_t pool)
847 struct i40e_virtchnl_ether_addr_list *list;
848 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
849 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
850 sizeof(struct i40e_virtchnl_ether_addr)];
852 struct vf_cmd_info args;
854 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
855 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
856 addr->addr_bytes[0], addr->addr_bytes[1],
857 addr->addr_bytes[2], addr->addr_bytes[3],
858 addr->addr_bytes[4], addr->addr_bytes[5]);
862 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
863 list->vsi_id = vf->vsi_res->vsi_id;
864 list->num_elements = 1;
865 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
866 sizeof(addr->addr_bytes));
868 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
869 args.in_args = cmd_buffer;
870 args.in_args_size = sizeof(cmd_buffer);
871 args.out_buffer = vf->aq_resp;
872 args.out_size = I40E_AQ_BUF_SZ;
873 err = i40evf_execute_vf_cmd(dev, &args);
875 PMD_DRV_LOG(ERR, "fail to execute command "
876 "OP_ADD_ETHER_ADDRESS");
882 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
884 struct i40e_virtchnl_ether_addr_list *list;
885 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
886 struct rte_eth_dev_data *data = dev->data;
887 struct ether_addr *addr;
888 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
889 sizeof(struct i40e_virtchnl_ether_addr)];
891 struct vf_cmd_info args;
893 addr = &(data->mac_addrs[index]);
895 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
896 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
897 addr->addr_bytes[0], addr->addr_bytes[1],
898 addr->addr_bytes[2], addr->addr_bytes[3],
899 addr->addr_bytes[4], addr->addr_bytes[5]);
903 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
904 list->vsi_id = vf->vsi_res->vsi_id;
905 list->num_elements = 1;
906 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
907 sizeof(addr->addr_bytes));
909 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
910 args.in_args = cmd_buffer;
911 args.in_args_size = sizeof(cmd_buffer);
912 args.out_buffer = vf->aq_resp;
913 args.out_size = I40E_AQ_BUF_SZ;
914 err = i40evf_execute_vf_cmd(dev, &args);
916 PMD_DRV_LOG(ERR, "fail to execute command "
917 "OP_DEL_ETHER_ADDRESS");
922 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
924 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
925 struct i40e_virtchnl_queue_select q_stats;
927 struct vf_cmd_info args;
929 memset(&q_stats, 0, sizeof(q_stats));
930 q_stats.vsi_id = vf->vsi_res->vsi_id;
931 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
932 args.in_args = (u8 *)&q_stats;
933 args.in_args_size = sizeof(q_stats);
934 args.out_buffer = vf->aq_resp;
935 args.out_size = I40E_AQ_BUF_SZ;
937 err = i40evf_execute_vf_cmd(dev, &args);
939 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
943 *pstats = (struct i40e_eth_stats *)args.out_buffer;
948 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
951 struct i40e_eth_stats *pstats = NULL;
953 ret = i40evf_update_stats(dev, &pstats);
957 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
958 pstats->rx_broadcast;
959 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
961 stats->ierrors = pstats->rx_discards;
962 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
963 stats->ibytes = pstats->rx_bytes;
964 stats->obytes = pstats->tx_bytes;
970 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
972 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
973 struct i40e_eth_stats *pstats = NULL;
975 /* read stat values to clear hardware registers */
976 i40evf_update_stats(dev, &pstats);
978 /* set stats offset base on current values */
979 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
982 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
983 struct rte_eth_xstats *xstats, unsigned n)
987 struct i40e_eth_stats *pstats = NULL;
989 if (n < I40EVF_NB_XSTATS)
990 return I40EVF_NB_XSTATS;
992 ret = i40evf_update_stats(dev, &pstats);
999 /* loop over xstats array and values from pstats */
1000 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1001 snprintf(xstats[i].name, sizeof(xstats[i].name),
1002 "%s", rte_i40evf_stats_strings[i].name);
1003 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1004 rte_i40evf_stats_strings[i].offset);
1007 return I40EVF_NB_XSTATS;
1011 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1013 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1014 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1015 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1018 struct vf_cmd_info args;
1020 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1021 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1022 vlan_list->num_elements = 1;
1023 vlan_list->vlan_id[0] = vlanid;
1025 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1026 args.in_args = (u8 *)&cmd_buffer;
1027 args.in_args_size = sizeof(cmd_buffer);
1028 args.out_buffer = vf->aq_resp;
1029 args.out_size = I40E_AQ_BUF_SZ;
1030 err = i40evf_execute_vf_cmd(dev, &args);
1032 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1038 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1040 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1041 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1042 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1045 struct vf_cmd_info args;
1047 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1048 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1049 vlan_list->num_elements = 1;
1050 vlan_list->vlan_id[0] = vlanid;
1052 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1053 args.in_args = (u8 *)&cmd_buffer;
1054 args.in_args_size = sizeof(cmd_buffer);
1055 args.out_buffer = vf->aq_resp;
1056 args.out_size = I40E_AQ_BUF_SZ;
1057 err = i40evf_execute_vf_cmd(dev, &args);
1059 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1065 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1067 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1069 struct vf_cmd_info args;
1070 struct rte_eth_link *new_link;
1072 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1073 args.in_args = NULL;
1074 args.in_args_size = 0;
1075 args.out_buffer = vf->aq_resp;
1076 args.out_size = I40E_AQ_BUF_SZ;
1077 err = i40evf_execute_vf_cmd(dev, &args);
1079 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1083 new_link = (struct rte_eth_link *)args.out_buffer;
1084 (void)rte_memcpy(link, new_link, sizeof(*link));
1089 static const struct rte_pci_id pci_id_i40evf_map[] = {
1090 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1091 #include "rte_pci_dev_ids.h"
1092 { .vendor_id = 0, /* sentinel */ },
1096 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1097 struct rte_eth_link *link)
1099 struct rte_eth_link *dst = &(dev->data->dev_link);
1100 struct rte_eth_link *src = link;
1102 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1103 *(uint64_t *)src) == 0)
1111 i40evf_disable_irq0(struct i40e_hw *hw)
1113 /* Disable all interrupt types */
1114 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1115 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1116 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1117 I40EVF_WRITE_FLUSH(hw);
1122 i40evf_enable_irq0(struct i40e_hw *hw)
1124 /* Enable admin queue interrupt trigger */
1127 i40evf_disable_irq0(hw);
1128 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1129 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1130 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1131 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1133 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1134 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1135 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1136 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1138 I40EVF_WRITE_FLUSH(hw);
1142 i40evf_reset_vf(struct i40e_hw *hw)
1146 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1147 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1151 * After issuing vf reset command to pf, pf won't necessarily
1152 * reset vf, it depends on what state it exactly is. If it's not
1153 * initialized yet, it won't have vf reset since it's in a certain
1154 * state. If not, it will try to reset. Even vf is reset, pf will
1155 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1156 * it to ACTIVE. In this duration, vf may not catch the moment that
1157 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1161 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1162 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1163 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1164 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1165 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1171 if (i >= MAX_RESET_WAIT_CNT) {
1172 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1180 i40evf_init_vf(struct rte_eth_dev *dev)
1183 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1185 struct ether_addr *p_mac_addr;
1187 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1189 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1190 vf->dev_data = dev->data;
1191 err = i40e_set_mac_type(hw);
1193 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1197 i40e_init_adminq_parameter(hw);
1198 err = i40e_init_adminq(hw);
1200 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1204 /* Reset VF and wait until it's complete */
1205 if (i40evf_reset_vf(hw)) {
1206 PMD_INIT_LOG(ERR, "reset NIC failed");
1210 /* VF reset, shutdown admin queue and initialize again */
1211 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1212 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1216 i40e_init_adminq_parameter(hw);
1217 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "init_adminq failed");
1221 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1223 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1226 if (i40evf_check_api_version(dev) != 0) {
1227 PMD_INIT_LOG(ERR, "check_api version failed");
1230 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1231 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1232 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1234 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1238 if (i40evf_get_vf_resource(dev) != 0) {
1239 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1243 /* got VF config message back from PF, now we can parse it */
1244 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1245 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1246 vf->vsi_res = &vf->vf_res->vsi_res[i];
1250 PMD_INIT_LOG(ERR, "no LAN VSI found");
1254 if (hw->mac.type == I40E_MAC_X722_VF)
1255 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1256 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1257 vf->vsi.type = vf->vsi_res->vsi_type;
1258 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1259 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1261 /* Store the MAC address configured by host, or generate random one */
1262 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1263 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1264 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1266 eth_random_addr(hw->mac.addr); /* Generate a random one */
1268 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1269 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1270 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1271 (I40E_ITR_INDEX_DEFAULT <<
1272 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1274 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1275 I40EVF_WRITE_FLUSH(hw);
1281 rte_free(vf->vf_res);
1283 i40e_shutdown_adminq(hw); /* ignore error */
1289 i40evf_uninit_vf(struct rte_eth_dev *dev)
1291 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294 PMD_INIT_FUNC_TRACE();
1296 if (hw->adapter_stopped == 0)
1297 i40evf_dev_close(dev);
1298 rte_free(vf->vf_res);
1300 rte_free(vf->aq_resp);
1307 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1309 __rte_unused uint16_t msglen)
1311 struct i40e_virtchnl_pf_event *pf_msg =
1312 (struct i40e_virtchnl_pf_event *)msg;
1314 switch (pf_msg->event) {
1315 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1316 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1317 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
1319 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1320 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1322 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1323 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1326 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1332 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1334 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1336 struct i40e_arq_event_info info;
1337 struct i40e_virtchnl_msg *v_msg;
1338 uint16_t pending, opcode;
1341 info.buf_len = I40E_AQ_BUF_SZ;
1343 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1346 info.msg_buf = vf->aq_resp;
1347 v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1351 ret = i40e_clean_arq_element(hw, &info, &pending);
1353 if (ret != I40E_SUCCESS) {
1354 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1358 opcode = rte_le_to_cpu_16(info.desc.opcode);
1361 case i40e_aqc_opc_send_msg_to_vf:
1362 if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1364 i40evf_handle_pf_event(dev, info.msg_buf,
1367 /* read message and it's expected one */
1368 if (v_msg->v_opcode == vf->pend_cmd) {
1369 vf->cmd_retval = v_msg->v_retval;
1370 /* prevent compiler reordering */
1371 rte_compiler_barrier();
1374 PMD_DRV_LOG(ERR, "command mismatch,"
1375 "expect %u, get %u",
1376 vf->pend_cmd, v_msg->v_opcode);
1377 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1378 " opcode = %d\n", v_msg->v_opcode);
1382 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1390 * Interrupt handler triggered by NIC for handling
1391 * specific interrupt. Only adminq interrupt is processed in VF.
1394 * Pointer to interrupt handle.
1396 * The address of parameter (struct rte_eth_dev *) regsitered before.
1402 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1405 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409 i40evf_disable_irq0(hw);
1411 /* read out interrupt causes */
1412 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1414 /* No interrupt event indicated */
1415 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1416 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1420 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1421 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1422 i40evf_handle_aq_msg(dev);
1425 /* Link Status Change interrupt */
1426 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1427 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1431 i40evf_enable_irq0(hw);
1432 rte_intr_enable(&dev->pci_dev->intr_handle);
1436 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1439 eth_dev->data->dev_private);
1440 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1442 PMD_INIT_FUNC_TRACE();
1444 /* assign ops func pointer */
1445 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1446 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1447 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1450 * For secondary processes, we don't initialise any further as primary
1451 * has already done this work.
1453 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1454 i40e_set_rx_function(eth_dev);
1455 i40e_set_tx_function(eth_dev);
1459 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1461 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1462 hw->device_id = eth_dev->pci_dev->id.device_id;
1463 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1464 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1465 hw->bus.device = eth_dev->pci_dev->addr.devid;
1466 hw->bus.func = eth_dev->pci_dev->addr.function;
1467 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1468 hw->adapter_stopped = 0;
1470 if(i40evf_init_vf(eth_dev) != 0) {
1471 PMD_INIT_LOG(ERR, "Init vf failed");
1475 /* register callback func to eal lib */
1476 rte_intr_callback_register(&pci_dev->intr_handle,
1477 i40evf_dev_interrupt_handler, (void *)eth_dev);
1479 /* enable uio intr after callback register */
1480 rte_intr_enable(&pci_dev->intr_handle);
1482 /* configure and enable device interrupt */
1483 i40evf_enable_irq0(hw);
1486 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1487 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1489 if (eth_dev->data->mac_addrs == NULL) {
1490 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1491 " store MAC addresses",
1492 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1495 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1496 ð_dev->data->mac_addrs[0]);
1502 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1504 PMD_INIT_FUNC_TRACE();
1506 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1509 eth_dev->dev_ops = NULL;
1510 eth_dev->rx_pkt_burst = NULL;
1511 eth_dev->tx_pkt_burst = NULL;
1513 if (i40evf_uninit_vf(eth_dev) != 0) {
1514 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1518 rte_free(eth_dev->data->mac_addrs);
1519 eth_dev->data->mac_addrs = NULL;
1524 * virtual function driver struct
1526 static struct eth_driver rte_i40evf_pmd = {
1528 .name = "rte_i40evf_pmd",
1529 .id_table = pci_id_i40evf_map,
1530 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1532 .eth_dev_init = i40evf_dev_init,
1533 .eth_dev_uninit = i40evf_dev_uninit,
1534 .dev_private_size = sizeof(struct i40e_adapter),
1538 * VF Driver initialization routine.
1539 * Invoked one at EAL init time.
1540 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1543 rte_i40evf_pmd_init(const char *name __rte_unused,
1544 const char *params __rte_unused)
1546 PMD_INIT_FUNC_TRACE();
1548 rte_eth_driver_register(&rte_i40evf_pmd);
1553 static struct rte_driver rte_i40evf_driver = {
1555 .init = rte_i40evf_pmd_init,
1558 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1561 i40evf_dev_configure(struct rte_eth_dev *dev)
1563 struct i40e_adapter *ad =
1564 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1566 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1567 * allocation or vector Rx preconditions we will reset it.
1569 ad->rx_bulk_alloc_allowed = true;
1570 ad->rx_vec_allowed = true;
1571 ad->tx_simple_allowed = true;
1572 ad->tx_vec_allowed = true;
1574 return i40evf_init_vlan(dev);
1578 i40evf_init_vlan(struct rte_eth_dev *dev)
1580 struct rte_eth_dev_data *data = dev->data;
1583 /* Apply vlan offload setting */
1584 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1586 /* Apply pvid setting */
1587 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1588 data->dev_conf.txmode.hw_vlan_insert_pvid);
1593 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1595 bool enable_vlan_strip = 0;
1596 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1597 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1599 /* Linux pf host doesn't support vlan offload yet */
1600 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1601 /* Vlan stripping setting */
1602 if (mask & ETH_VLAN_STRIP_MASK) {
1603 /* Enable or disable VLAN stripping */
1604 if (dev_conf->rxmode.hw_vlan_strip)
1605 enable_vlan_strip = 1;
1607 enable_vlan_strip = 0;
1609 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1615 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1617 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1618 struct i40e_vsi_vlan_pvid_info info;
1619 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1621 memset(&info, 0, sizeof(info));
1624 /* Linux pf host don't support vlan offload yet */
1625 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1627 info.config.pvid = pvid;
1629 info.config.reject.tagged =
1630 dev_conf->txmode.hw_vlan_reject_tagged;
1631 info.config.reject.untagged =
1632 dev_conf->txmode.hw_vlan_reject_untagged;
1634 return i40evf_config_vlan_pvid(dev, &info);
1641 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1643 struct i40e_rx_queue *rxq;
1645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647 PMD_INIT_FUNC_TRACE();
1649 if (rx_queue_id < dev->data->nb_rx_queues) {
1650 rxq = dev->data->rx_queues[rx_queue_id];
1652 err = i40e_alloc_rx_queue_mbufs(rxq);
1654 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1660 /* Init the RX tail register. */
1661 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1662 I40EVF_WRITE_FLUSH(hw);
1664 /* Ready to switch the queue on */
1665 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1668 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1671 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1678 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1680 struct i40e_rx_queue *rxq;
1683 if (rx_queue_id < dev->data->nb_rx_queues) {
1684 rxq = dev->data->rx_queues[rx_queue_id];
1686 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1689 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1694 i40e_rx_queue_release_mbufs(rxq);
1695 i40e_reset_rx_queue(rxq);
1696 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1703 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1707 PMD_INIT_FUNC_TRACE();
1709 if (tx_queue_id < dev->data->nb_tx_queues) {
1711 /* Ready to switch the queue on */
1712 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1715 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1718 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1725 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1727 struct i40e_tx_queue *txq;
1730 if (tx_queue_id < dev->data->nb_tx_queues) {
1731 txq = dev->data->tx_queues[tx_queue_id];
1733 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1736 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1741 i40e_tx_queue_release_mbufs(txq);
1742 i40e_reset_tx_queue(txq);
1743 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1750 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1755 ret = i40evf_add_vlan(dev, vlan_id);
1757 ret = i40evf_del_vlan(dev,vlan_id);
1763 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766 struct rte_eth_dev_data *dev_data = dev->data;
1767 struct rte_pktmbuf_pool_private *mbp_priv;
1768 uint16_t buf_size, len;
1770 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1771 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1772 I40EVF_WRITE_FLUSH(hw);
1774 /* Calculate the maximum packet length allowed */
1775 mbp_priv = rte_mempool_get_priv(rxq->mp);
1776 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1777 RTE_PKTMBUF_HEADROOM);
1778 rxq->hs_mode = i40e_header_split_none;
1779 rxq->rx_hdr_len = 0;
1780 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1781 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1782 rxq->max_pkt_len = RTE_MIN(len,
1783 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1786 * Check if the jumbo frame and maximum packet length are set correctly
1788 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1789 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1790 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1791 PMD_DRV_LOG(ERR, "maximum packet length must be "
1792 "larger than %u and smaller than %u, as jumbo "
1793 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1794 (uint32_t)I40E_FRAME_SIZE_MAX);
1795 return I40E_ERR_CONFIG;
1798 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1799 rxq->max_pkt_len > ETHER_MAX_LEN) {
1800 PMD_DRV_LOG(ERR, "maximum packet length must be "
1801 "larger than %u and smaller than %u, as jumbo "
1802 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1803 (uint32_t)ETHER_MAX_LEN);
1804 return I40E_ERR_CONFIG;
1808 if (dev_data->dev_conf.rxmode.enable_scatter ||
1809 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1810 dev_data->scattered_rx = 1;
1817 i40evf_rx_init(struct rte_eth_dev *dev)
1819 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1821 int ret = I40E_SUCCESS;
1822 struct i40e_rx_queue **rxq =
1823 (struct i40e_rx_queue **)dev->data->rx_queues;
1825 i40evf_config_rss(vf);
1826 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1827 if (!rxq[i] || !rxq[i]->q_set)
1829 ret = i40evf_rxq_init(dev, rxq[i]);
1830 if (ret != I40E_SUCCESS)
1833 if (ret == I40E_SUCCESS)
1834 i40e_set_rx_function(dev);
1840 i40evf_tx_init(struct rte_eth_dev *dev)
1843 struct i40e_tx_queue **txq =
1844 (struct i40e_tx_queue **)dev->data->tx_queues;
1845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 for (i = 0; i < dev->data->nb_tx_queues; i++)
1848 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1850 i40e_set_tx_function(dev);
1854 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1856 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1860 if (!rte_intr_allow_others(intr_handle)) {
1862 I40E_VFINT_DYN_CTL01,
1863 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1864 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1865 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1866 I40EVF_WRITE_FLUSH(hw);
1870 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1871 /* To support DPDK PF host */
1873 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1874 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1875 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1876 /* If host driver is kernel driver, do nothing.
1877 * Interrupt 0 is used for rx packets, but don't set
1878 * I40E_VFINT_DYN_CTL01,
1879 * because it is already done in i40evf_enable_irq0.
1882 I40EVF_WRITE_FLUSH(hw);
1886 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1888 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1892 if (!rte_intr_allow_others(intr_handle)) {
1893 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1894 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1895 I40EVF_WRITE_FLUSH(hw);
1899 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1901 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1904 /* If host driver is kernel driver, do nothing.
1905 * Interrupt 0 is used for rx packets, but don't zero
1906 * I40E_VFINT_DYN_CTL01,
1907 * because interrupt 0 is also used for adminq processing.
1910 I40EVF_WRITE_FLUSH(hw);
1914 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1916 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1922 msix_intr = intr_handle->intr_vec[queue_id];
1923 if (msix_intr == I40E_MISC_VEC_ID)
1924 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1925 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1926 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1927 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1929 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1932 I40E_VFINT_DYN_CTLN1(msix_intr -
1934 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1935 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1936 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1938 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1940 I40EVF_WRITE_FLUSH(hw);
1942 rte_intr_enable(&dev->pci_dev->intr_handle);
1948 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1950 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1951 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954 msix_intr = intr_handle->intr_vec[queue_id];
1955 if (msix_intr == I40E_MISC_VEC_ID)
1956 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1959 I40E_VFINT_DYN_CTLN1(msix_intr -
1963 I40EVF_WRITE_FLUSH(hw);
1969 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1971 struct i40e_virtchnl_ether_addr_list *list;
1972 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1977 struct ether_addr *addr;
1978 struct vf_cmd_info args;
1982 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1983 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1984 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1986 len += sizeof(struct i40e_virtchnl_ether_addr);
1987 if (len >= I40E_AQ_BUF_SZ) {
1993 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1995 for (i = begin; i < next_begin; i++) {
1996 addr = &dev->data->mac_addrs[i];
1997 if (is_zero_ether_addr(addr))
1999 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2000 sizeof(addr->addr_bytes));
2001 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2002 addr->addr_bytes[0], addr->addr_bytes[1],
2003 addr->addr_bytes[2], addr->addr_bytes[3],
2004 addr->addr_bytes[4], addr->addr_bytes[5]);
2007 list->vsi_id = vf->vsi_res->vsi_id;
2008 list->num_elements = j;
2009 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2010 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2011 args.in_args = (uint8_t *)list;
2012 args.in_args_size = len;
2013 args.out_buffer = vf->aq_resp;
2014 args.out_size = I40E_AQ_BUF_SZ;
2015 err = i40evf_execute_vf_cmd(dev, &args);
2017 PMD_DRV_LOG(ERR, "fail to execute command %s",
2018 add ? "OP_ADD_ETHER_ADDRESS" :
2019 "OP_DEL_ETHER_ADDRESS");
2022 } while (begin < I40E_NUM_MACADDR_MAX);
2026 i40evf_dev_start(struct rte_eth_dev *dev)
2028 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2031 uint32_t intr_vector = 0;
2033 PMD_INIT_FUNC_TRACE();
2035 hw->adapter_stopped = 0;
2037 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2038 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2039 dev->data->nb_tx_queues);
2041 /* check and configure queue intr-vector mapping */
2042 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2043 intr_vector = dev->data->nb_rx_queues;
2044 if (rte_intr_efd_enable(intr_handle, intr_vector))
2048 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2049 intr_handle->intr_vec =
2050 rte_zmalloc("intr_vec",
2051 dev->data->nb_rx_queues * sizeof(int), 0);
2052 if (!intr_handle->intr_vec) {
2053 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2054 " intr_vec\n", dev->data->nb_rx_queues);
2059 if (i40evf_rx_init(dev) != 0){
2060 PMD_DRV_LOG(ERR, "failed to do RX init");
2064 i40evf_tx_init(dev);
2066 if (i40evf_configure_queues(dev) != 0) {
2067 PMD_DRV_LOG(ERR, "configure queues failed");
2070 if (i40evf_config_irq_map(dev)) {
2071 PMD_DRV_LOG(ERR, "config_irq_map failed");
2075 /* Set all mac addrs */
2076 i40evf_add_del_all_mac_addr(dev, TRUE);
2078 if (i40evf_start_queues(dev) != 0) {
2079 PMD_DRV_LOG(ERR, "enable queues failed");
2083 i40evf_enable_queues_intr(dev);
2087 i40evf_add_del_all_mac_addr(dev, FALSE);
2093 i40evf_dev_stop(struct rte_eth_dev *dev)
2095 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2097 PMD_INIT_FUNC_TRACE();
2099 i40evf_stop_queues(dev);
2100 i40evf_disable_queues_intr(dev);
2101 i40e_dev_clear_queues(dev);
2103 /* Clean datapath event and queue/vec mapping */
2104 rte_intr_efd_disable(intr_handle);
2105 if (intr_handle->intr_vec) {
2106 rte_free(intr_handle->intr_vec);
2107 intr_handle->intr_vec = NULL;
2109 /* remove all mac addrs */
2110 i40evf_add_del_all_mac_addr(dev, FALSE);
2115 i40evf_dev_link_update(struct rte_eth_dev *dev,
2116 __rte_unused int wait_to_complete)
2118 struct rte_eth_link new_link;
2119 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2121 * DPDK pf host provide interfacet to acquire link status
2122 * while Linux driver does not
2124 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
2125 i40evf_get_link_status(dev, &new_link);
2127 /* Always assume it's up, for Linux driver PF host */
2128 new_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;
2129 new_link.link_speed = ETH_LINK_SPEED_10000;
2130 new_link.link_status = 1;
2132 i40evf_dev_atomic_write_link_status(dev, &new_link);
2138 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2140 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2143 /* If enabled, just return */
2144 if (vf->promisc_unicast_enabled)
2147 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2149 vf->promisc_unicast_enabled = TRUE;
2153 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2155 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2158 /* If disabled, just return */
2159 if (!vf->promisc_unicast_enabled)
2162 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2164 vf->promisc_unicast_enabled = FALSE;
2168 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2170 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2173 /* If enabled, just return */
2174 if (vf->promisc_multicast_enabled)
2177 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2179 vf->promisc_multicast_enabled = TRUE;
2183 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2185 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2188 /* If enabled, just return */
2189 if (!vf->promisc_multicast_enabled)
2192 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2194 vf->promisc_multicast_enabled = FALSE;
2198 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2200 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2202 memset(dev_info, 0, sizeof(*dev_info));
2203 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2204 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2205 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2206 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2207 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2208 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2209 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2210 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2211 dev_info->rx_offload_capa =
2212 DEV_RX_OFFLOAD_VLAN_STRIP |
2213 DEV_RX_OFFLOAD_QINQ_STRIP |
2214 DEV_RX_OFFLOAD_IPV4_CKSUM |
2215 DEV_RX_OFFLOAD_UDP_CKSUM |
2216 DEV_RX_OFFLOAD_TCP_CKSUM;
2217 dev_info->tx_offload_capa =
2218 DEV_TX_OFFLOAD_VLAN_INSERT |
2219 DEV_TX_OFFLOAD_QINQ_INSERT |
2220 DEV_TX_OFFLOAD_IPV4_CKSUM |
2221 DEV_TX_OFFLOAD_UDP_CKSUM |
2222 DEV_TX_OFFLOAD_TCP_CKSUM |
2223 DEV_TX_OFFLOAD_SCTP_CKSUM;
2225 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2227 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2228 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2229 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2231 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2235 dev_info->default_txconf = (struct rte_eth_txconf) {
2237 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2238 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2239 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2241 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2242 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2243 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2244 ETH_TXQ_FLAGS_NOOFFLOADS,
2247 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2248 .nb_max = I40E_MAX_RING_DESC,
2249 .nb_min = I40E_MIN_RING_DESC,
2250 .nb_align = I40E_ALIGN_RING_DESC,
2253 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2254 .nb_max = I40E_MAX_RING_DESC,
2255 .nb_min = I40E_MIN_RING_DESC,
2256 .nb_align = I40E_ALIGN_RING_DESC,
2261 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2263 if (i40evf_get_statics(dev, stats))
2264 PMD_DRV_LOG(ERR, "Get statics failed");
2268 i40evf_dev_close(struct rte_eth_dev *dev)
2270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271 struct rte_pci_device *pci_dev = dev->pci_dev;
2273 i40evf_dev_stop(dev);
2274 hw->adapter_stopped = 1;
2275 i40e_dev_free_queues(dev);
2276 i40evf_reset_vf(hw);
2277 i40e_shutdown_adminq(hw);
2278 /* disable uio intr before callback unregister */
2279 rte_intr_disable(&pci_dev->intr_handle);
2281 /* unregister callback func from eal lib */
2282 rte_intr_callback_unregister(&pci_dev->intr_handle,
2283 i40evf_dev_interrupt_handler, (void *)dev);
2284 i40evf_disable_irq0(hw);
2288 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2290 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2291 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2297 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2298 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2301 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2305 uint32_t *lut_dw = (uint32_t *)lut;
2306 uint16_t i, lut_size_dw = lut_size / 4;
2308 for (i = 0; i < lut_size_dw; i++)
2309 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2316 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2318 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2319 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2325 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2326 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2329 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2333 uint32_t *lut_dw = (uint32_t *)lut;
2334 uint16_t i, lut_size_dw = lut_size / 4;
2336 for (i = 0; i < lut_size_dw; i++)
2337 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2338 I40EVF_WRITE_FLUSH(hw);
2345 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2346 struct rte_eth_rss_reta_entry64 *reta_conf,
2349 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2351 uint16_t i, idx, shift;
2354 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2355 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2356 "(%d) doesn't match the number of hardware can "
2357 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2361 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2363 PMD_DRV_LOG(ERR, "No memory can be allocated");
2366 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2369 for (i = 0; i < reta_size; i++) {
2370 idx = i / RTE_RETA_GROUP_SIZE;
2371 shift = i % RTE_RETA_GROUP_SIZE;
2372 if (reta_conf[idx].mask & (1ULL << shift))
2373 lut[i] = reta_conf[idx].reta[shift];
2375 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2384 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2385 struct rte_eth_rss_reta_entry64 *reta_conf,
2388 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2389 uint16_t i, idx, shift;
2393 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2394 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2395 "(%d) doesn't match the number of hardware can "
2396 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2400 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2402 PMD_DRV_LOG(ERR, "No memory can be allocated");
2406 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2409 for (i = 0; i < reta_size; i++) {
2410 idx = i / RTE_RETA_GROUP_SIZE;
2411 shift = i % RTE_RETA_GROUP_SIZE;
2412 if (reta_conf[idx].mask & (1ULL << shift))
2413 reta_conf[idx].reta[shift] = lut[i];
2423 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2425 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2426 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2429 if (!key || key_len == 0) {
2430 PMD_DRV_LOG(DEBUG, "No key to be configured");
2432 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2434 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2438 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2439 struct i40e_aqc_get_set_rss_key_data *key_dw =
2440 (struct i40e_aqc_get_set_rss_key_data *)key;
2442 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2444 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2447 uint32_t *hash_key = (uint32_t *)key;
2450 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2451 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2452 I40EVF_WRITE_FLUSH(hw);
2459 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2461 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2462 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2465 if (!key || !key_len)
2468 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2469 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2470 (struct i40e_aqc_get_set_rss_key_data *)key);
2472 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2476 uint32_t *key_dw = (uint32_t *)key;
2479 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2480 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2482 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2488 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2490 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2491 uint64_t rss_hf, hena;
2494 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2495 rss_conf->rss_key_len);
2499 rss_hf = rss_conf->rss_hf;
2500 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2501 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2502 hena &= ~I40E_RSS_HENA_ALL;
2503 hena |= i40e_config_hena(rss_hf);
2504 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2505 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2506 I40EVF_WRITE_FLUSH(hw);
2512 i40evf_disable_rss(struct i40e_vf *vf)
2514 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2517 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2518 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2519 hena &= ~I40E_RSS_HENA_ALL;
2520 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2521 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2522 I40EVF_WRITE_FLUSH(hw);
2526 i40evf_config_rss(struct i40e_vf *vf)
2528 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2529 struct rte_eth_rss_conf rss_conf;
2530 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2533 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2534 i40evf_disable_rss(vf);
2535 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2539 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2540 /* Fill out the look up table */
2541 for (i = 0, j = 0; i < nb_q; i++, j++) {
2544 lut = (lut << 8) | j;
2546 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2549 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2550 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2551 i40evf_disable_rss(vf);
2552 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2556 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2557 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2558 /* Calculate the default hash key */
2559 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2560 rss_key_default[i] = (uint32_t)rte_rand();
2561 rss_conf.rss_key = (uint8_t *)rss_key_default;
2562 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2566 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2570 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2571 struct rte_eth_rss_conf *rss_conf)
2573 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2578 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2579 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2580 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2581 if (rss_hf != 0) /* Enable RSS */
2587 if (rss_hf == 0) /* Disable RSS */
2590 return i40evf_hw_rss_hash_set(vf, rss_conf);
2594 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2595 struct rte_eth_rss_conf *rss_conf)
2597 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2602 &rss_conf->rss_key_len);
2604 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2605 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2606 rss_conf->rss_hf = i40e_parse_hena(hena);