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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
124 static void i40evf_dev_close(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
129 static int i40evf_get_link_status(struct rte_eth_dev *dev,
130 struct rte_eth_link *link);
131 static int i40evf_init_vlan(struct rte_eth_dev *dev);
132 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
133 uint16_t rx_queue_id);
134 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
135 uint16_t rx_queue_id);
136 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
137 uint16_t tx_queue_id);
138 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
139 uint16_t tx_queue_id);
140 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
141 struct ether_addr *addr,
144 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
145 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
149 struct rte_eth_rss_reta_entry64 *reta_conf,
151 static int i40evf_config_rss(struct i40e_vf *vf);
152 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
153 struct rte_eth_rss_conf *rss_conf);
154 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
155 struct rte_eth_rss_conf *rss_conf);
157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
160 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
164 /* Default hash key buffer for RSS */
165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
167 struct rte_i40evf_xstats_name_off {
168 char name[RTE_ETH_XSTATS_NAME_SIZE];
172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
173 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
174 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
175 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
176 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
177 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
178 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
179 rx_unknown_protocol)},
180 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
183 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
184 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
185 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
189 sizeof(rte_i40evf_stats_strings[0]))
191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
192 .dev_configure = i40evf_dev_configure,
193 .dev_start = i40evf_dev_start,
194 .dev_stop = i40evf_dev_stop,
195 .promiscuous_enable = i40evf_dev_promiscuous_enable,
196 .promiscuous_disable = i40evf_dev_promiscuous_disable,
197 .allmulticast_enable = i40evf_dev_allmulticast_enable,
198 .allmulticast_disable = i40evf_dev_allmulticast_disable,
199 .link_update = i40evf_dev_link_update,
200 .stats_get = i40evf_dev_stats_get,
201 .xstats_get = i40evf_dev_xstats_get,
202 .xstats_get_names = i40evf_dev_xstats_get_names,
203 .xstats_reset = i40evf_dev_xstats_reset,
204 .dev_close = i40evf_dev_close,
205 .dev_infos_get = i40evf_dev_info_get,
206 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
207 .vlan_filter_set = i40evf_vlan_filter_set,
208 .vlan_offload_set = i40evf_vlan_offload_set,
209 .vlan_pvid_set = i40evf_vlan_pvid_set,
210 .rx_queue_start = i40evf_dev_rx_queue_start,
211 .rx_queue_stop = i40evf_dev_rx_queue_stop,
212 .tx_queue_start = i40evf_dev_tx_queue_start,
213 .tx_queue_stop = i40evf_dev_tx_queue_stop,
214 .rx_queue_setup = i40e_dev_rx_queue_setup,
215 .rx_queue_release = i40e_dev_rx_queue_release,
216 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
217 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
218 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
219 .tx_queue_setup = i40e_dev_tx_queue_setup,
220 .tx_queue_release = i40e_dev_tx_queue_release,
221 .rx_queue_count = i40e_dev_rx_queue_count,
222 .rxq_info_get = i40e_rxq_info_get,
223 .txq_info_get = i40e_txq_info_get,
224 .mac_addr_add = i40evf_add_mac_addr,
225 .mac_addr_remove = i40evf_del_mac_addr,
226 .reta_update = i40evf_dev_rss_reta_update,
227 .reta_query = i40evf_dev_rss_reta_query,
228 .rss_hash_update = i40evf_dev_rss_hash_update,
229 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
233 * Read data in admin queue to get msg from pf driver
235 static enum i40evf_aq_result
236 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
239 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
240 struct i40e_arq_event_info event;
241 enum i40e_virtchnl_ops opcode;
242 enum i40e_status_code retval;
244 enum i40evf_aq_result result = I40EVF_MSG_NON;
246 event.buf_len = data->buf_len;
247 event.msg_buf = data->msg;
248 ret = i40e_clean_arq_element(hw, &event, NULL);
249 /* Can't read any msg from adminQ */
251 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
252 result = I40EVF_MSG_ERR;
256 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
257 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
259 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
260 struct i40e_virtchnl_pf_event *vpe =
261 (struct i40e_virtchnl_pf_event *)event.msg_buf;
263 result = I40EVF_MSG_SYS;
264 switch (vpe->event) {
265 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
267 vpe->event_data.link_event.link_status;
269 vpe->event_data.link_event.link_speed;
270 vf->pend_msg |= PFMSG_LINK_CHANGE;
271 PMD_DRV_LOG(INFO, "Link status update:%s",
272 vf->link_up ? "up" : "down");
274 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
276 vf->pend_msg |= PFMSG_RESET_IMPENDING;
277 PMD_DRV_LOG(INFO, "vf is reseting");
279 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
280 vf->dev_closed = true;
281 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
282 PMD_DRV_LOG(INFO, "PF driver closed");
285 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
286 __func__, vpe->event);
289 /* async reply msg on command issued by vf previously */
290 result = I40EVF_MSG_CMD;
291 /* Actual data length read from PF */
292 data->msg_len = event.msg_len;
295 data->result = retval;
302 * clear current command. Only call in case execute
303 * _atomic_set_cmd successfully.
306 _clear_cmd(struct i40e_vf *vf)
309 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
313 * Check there is pending cmd in execution. If none, set new command.
316 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
318 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
319 I40E_VIRTCHNL_OP_UNKNOWN, ops);
322 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
327 #define MAX_TRY_TIMES 200
328 #define ASQ_DELAY_MS 10
331 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
333 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
334 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
335 struct i40evf_arq_msg_info info;
336 enum i40evf_aq_result ret;
339 if (_atomic_set_cmd(vf, args->ops))
342 info.msg = args->out_buffer;
343 info.buf_len = args->out_size;
344 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
345 info.result = I40E_SUCCESS;
347 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
348 args->in_args, args->in_args_size, NULL);
350 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
356 case I40E_VIRTCHNL_OP_RESET_VF:
357 /*no need to process in this function */
360 case I40E_VIRTCHNL_OP_VERSION:
361 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
362 /* for init adminq commands, need to poll the response */
365 ret = i40evf_read_pfmsg(dev, &info);
366 if (ret == I40EVF_MSG_CMD) {
369 } else if (ret == I40EVF_MSG_ERR)
371 rte_delay_ms(ASQ_DELAY_MS);
372 /* If don't read msg or read sys event, continue */
373 } while (i++ < MAX_TRY_TIMES);
378 /* for other adminq in running time, waiting the cmd done flag */
381 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
385 rte_delay_ms(ASQ_DELAY_MS);
386 /* If don't read msg or read sys event, continue */
387 } while (i++ < MAX_TRY_TIMES);
391 return err | vf->cmd_retval;
395 * Check API version with sync wait until version read or fail from admin queue
398 i40evf_check_api_version(struct rte_eth_dev *dev)
400 struct i40e_virtchnl_version_info version, *pver;
402 struct vf_cmd_info args;
403 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
405 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
406 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
408 args.ops = I40E_VIRTCHNL_OP_VERSION;
409 args.in_args = (uint8_t *)&version;
410 args.in_args_size = sizeof(version);
411 args.out_buffer = vf->aq_resp;
412 args.out_size = I40E_AQ_BUF_SZ;
414 err = i40evf_execute_vf_cmd(dev, &args);
416 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
420 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
421 vf->version_major = pver->major;
422 vf->version_minor = pver->minor;
423 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
424 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
425 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
426 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
427 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
429 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
430 vf->version_major, vf->version_minor,
431 I40E_VIRTCHNL_VERSION_MAJOR,
432 I40E_VIRTCHNL_VERSION_MINOR);
440 i40evf_get_vf_resource(struct rte_eth_dev *dev)
442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
443 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
445 struct vf_cmd_info args;
448 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
449 args.out_buffer = vf->aq_resp;
450 args.out_size = I40E_AQ_BUF_SZ;
452 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
453 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
454 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
455 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
456 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
457 args.in_args = (uint8_t *)∩︀
458 args.in_args_size = sizeof(caps);
461 args.in_args_size = 0;
463 err = i40evf_execute_vf_cmd(dev, &args);
466 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
470 len = sizeof(struct i40e_virtchnl_vf_resource) +
471 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
473 (void)rte_memcpy(vf->vf_res, args.out_buffer,
474 RTE_MIN(args.out_size, len));
475 i40e_vf_parse_hw_config(hw, vf->vf_res);
481 i40evf_config_promisc(struct rte_eth_dev *dev,
483 bool enable_multicast)
485 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
487 struct vf_cmd_info args;
488 struct i40e_virtchnl_promisc_info promisc;
491 promisc.vsi_id = vf->vsi_res->vsi_id;
494 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
496 if (enable_multicast)
497 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
499 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
500 args.in_args = (uint8_t *)&promisc;
501 args.in_args_size = sizeof(promisc);
502 args.out_buffer = vf->aq_resp;
503 args.out_size = I40E_AQ_BUF_SZ;
505 err = i40evf_execute_vf_cmd(dev, &args);
508 PMD_DRV_LOG(ERR, "fail to execute command "
509 "CONFIG_PROMISCUOUS_MODE");
513 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
515 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
516 bool enable_vlan_strip)
518 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
520 struct vf_cmd_info args;
521 struct i40e_virtchnl_vlan_offload_info offload;
523 offload.vsi_id = vf->vsi_res->vsi_id;
524 offload.enable_vlan_strip = enable_vlan_strip;
526 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
527 args.in_args = (uint8_t *)&offload;
528 args.in_args_size = sizeof(offload);
529 args.out_buffer = vf->aq_resp;
530 args.out_size = I40E_AQ_BUF_SZ;
532 err = i40evf_execute_vf_cmd(dev, &args);
534 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
540 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
541 struct i40e_vsi_vlan_pvid_info *info)
543 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
545 struct vf_cmd_info args;
546 struct i40e_virtchnl_pvid_info tpid_info;
549 PMD_DRV_LOG(ERR, "invalid parameters");
550 return I40E_ERR_PARAM;
553 memset(&tpid_info, 0, sizeof(tpid_info));
554 tpid_info.vsi_id = vf->vsi_res->vsi_id;
555 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
557 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
558 args.in_args = (uint8_t *)&tpid_info;
559 args.in_args_size = sizeof(tpid_info);
560 args.out_buffer = vf->aq_resp;
561 args.out_size = I40E_AQ_BUF_SZ;
563 err = i40evf_execute_vf_cmd(dev, &args);
565 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
571 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
575 struct i40e_tx_queue *txq)
577 txq_info->vsi_id = vsi_id;
578 txq_info->queue_id = queue_id;
579 if (queue_id < nb_txq) {
580 txq_info->ring_len = txq->nb_tx_desc;
581 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
586 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
590 uint32_t max_pkt_size,
591 struct i40e_rx_queue *rxq)
593 rxq_info->vsi_id = vsi_id;
594 rxq_info->queue_id = queue_id;
595 rxq_info->max_pkt_size = max_pkt_size;
596 if (queue_id < nb_rxq) {
597 rxq_info->ring_len = rxq->nb_rx_desc;
598 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
599 rxq_info->databuffer_size =
600 (rte_pktmbuf_data_room_size(rxq->mp) -
601 RTE_PKTMBUF_HEADROOM);
605 /* It configures VSI queues to co-work with Linux PF host */
607 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
609 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
610 struct i40e_rx_queue **rxq =
611 (struct i40e_rx_queue **)dev->data->rx_queues;
612 struct i40e_tx_queue **txq =
613 (struct i40e_tx_queue **)dev->data->tx_queues;
614 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
615 struct i40e_virtchnl_queue_pair_info *vc_qpi;
616 struct vf_cmd_info args;
617 uint16_t i, nb_qp = vf->num_queue_pairs;
618 const uint32_t size =
619 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
623 memset(buff, 0, sizeof(buff));
624 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
625 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
626 vc_vqci->num_queue_pairs = nb_qp;
628 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
629 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
630 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
631 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
632 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
633 vf->max_pkt_len, rxq[i]);
635 memset(&args, 0, sizeof(args));
636 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
637 args.in_args = (uint8_t *)vc_vqci;
638 args.in_args_size = size;
639 args.out_buffer = vf->aq_resp;
640 args.out_size = I40E_AQ_BUF_SZ;
641 ret = i40evf_execute_vf_cmd(dev, &args);
643 PMD_DRV_LOG(ERR, "Failed to execute command of "
644 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
649 /* It configures VSI queues to co-work with DPDK PF host */
651 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
653 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
654 struct i40e_rx_queue **rxq =
655 (struct i40e_rx_queue **)dev->data->rx_queues;
656 struct i40e_tx_queue **txq =
657 (struct i40e_tx_queue **)dev->data->tx_queues;
658 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
659 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
660 struct vf_cmd_info args;
661 uint16_t i, nb_qp = vf->num_queue_pairs;
662 const uint32_t size =
663 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
667 memset(buff, 0, sizeof(buff));
668 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
669 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
670 vc_vqcei->num_queue_pairs = nb_qp;
671 vc_qpei = vc_vqcei->qpair;
672 for (i = 0; i < nb_qp; i++, vc_qpei++) {
673 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
674 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
675 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
676 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
677 vf->max_pkt_len, rxq[i]);
678 if (i < dev->data->nb_rx_queues)
680 * It adds extra info for configuring VSI queues, which
681 * is needed to enable the configurable crc stripping
684 vc_qpei->rxq_ext.crcstrip =
685 dev->data->dev_conf.rxmode.hw_strip_crc;
687 memset(&args, 0, sizeof(args));
689 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
690 args.in_args = (uint8_t *)vc_vqcei;
691 args.in_args_size = size;
692 args.out_buffer = vf->aq_resp;
693 args.out_size = I40E_AQ_BUF_SZ;
694 ret = i40evf_execute_vf_cmd(dev, &args);
696 PMD_DRV_LOG(ERR, "Failed to execute command of "
697 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
703 i40evf_configure_queues(struct rte_eth_dev *dev)
705 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
707 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
708 /* To support DPDK PF host */
709 return i40evf_configure_vsi_queues_ext(dev);
711 /* To support Linux PF host */
712 return i40evf_configure_vsi_queues(dev);
716 i40evf_config_irq_map(struct rte_eth_dev *dev)
718 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
719 struct vf_cmd_info args;
720 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
721 sizeof(struct i40e_virtchnl_vector_map)];
722 struct i40e_virtchnl_irq_map_info *map_info;
723 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
727 if (rte_intr_allow_others(intr_handle)) {
728 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
729 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
731 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
733 vector_id = I40E_MISC_VEC_ID;
736 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
737 map_info->num_vectors = 1;
738 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
739 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
740 /* Alway use default dynamic MSIX interrupt */
741 map_info->vecmap[0].vector_id = vector_id;
742 /* Don't map any tx queue */
743 map_info->vecmap[0].txq_map = 0;
744 map_info->vecmap[0].rxq_map = 0;
745 for (i = 0; i < dev->data->nb_rx_queues; i++) {
746 map_info->vecmap[0].rxq_map |= 1 << i;
747 if (rte_intr_dp_is_en(intr_handle))
748 intr_handle->intr_vec[i] = vector_id;
751 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
752 args.in_args = (u8 *)cmd_buffer;
753 args.in_args_size = sizeof(cmd_buffer);
754 args.out_buffer = vf->aq_resp;
755 args.out_size = I40E_AQ_BUF_SZ;
756 err = i40evf_execute_vf_cmd(dev, &args);
758 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
764 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
767 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
768 struct i40e_virtchnl_queue_select queue_select;
770 struct vf_cmd_info args;
771 memset(&queue_select, 0, sizeof(queue_select));
772 queue_select.vsi_id = vf->vsi_res->vsi_id;
775 queue_select.rx_queues |= 1 << qid;
777 queue_select.tx_queues |= 1 << qid;
780 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
782 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
783 args.in_args = (u8 *)&queue_select;
784 args.in_args_size = sizeof(queue_select);
785 args.out_buffer = vf->aq_resp;
786 args.out_size = I40E_AQ_BUF_SZ;
787 err = i40evf_execute_vf_cmd(dev, &args);
789 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
790 isrx ? "RX" : "TX", qid, on ? "on" : "off");
796 i40evf_start_queues(struct rte_eth_dev *dev)
798 struct rte_eth_dev_data *dev_data = dev->data;
800 struct i40e_rx_queue *rxq;
801 struct i40e_tx_queue *txq;
803 for (i = 0; i < dev->data->nb_rx_queues; i++) {
804 rxq = dev_data->rx_queues[i];
805 if (rxq->rx_deferred_start)
807 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
808 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
813 for (i = 0; i < dev->data->nb_tx_queues; i++) {
814 txq = dev_data->tx_queues[i];
815 if (txq->tx_deferred_start)
817 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
818 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
827 i40evf_stop_queues(struct rte_eth_dev *dev)
831 /* Stop TX queues first */
832 for (i = 0; i < dev->data->nb_tx_queues; i++) {
833 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
834 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
839 /* Then stop RX queues */
840 for (i = 0; i < dev->data->nb_rx_queues; i++) {
841 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
842 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
851 i40evf_add_mac_addr(struct rte_eth_dev *dev,
852 struct ether_addr *addr,
853 __rte_unused uint32_t index,
854 __rte_unused uint32_t pool)
856 struct i40e_virtchnl_ether_addr_list *list;
857 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
858 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
859 sizeof(struct i40e_virtchnl_ether_addr)];
861 struct vf_cmd_info args;
863 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
864 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
865 addr->addr_bytes[0], addr->addr_bytes[1],
866 addr->addr_bytes[2], addr->addr_bytes[3],
867 addr->addr_bytes[4], addr->addr_bytes[5]);
871 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
872 list->vsi_id = vf->vsi_res->vsi_id;
873 list->num_elements = 1;
874 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
875 sizeof(addr->addr_bytes));
877 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
878 args.in_args = cmd_buffer;
879 args.in_args_size = sizeof(cmd_buffer);
880 args.out_buffer = vf->aq_resp;
881 args.out_size = I40E_AQ_BUF_SZ;
882 err = i40evf_execute_vf_cmd(dev, &args);
884 PMD_DRV_LOG(ERR, "fail to execute command "
885 "OP_ADD_ETHER_ADDRESS");
891 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
893 struct i40e_virtchnl_ether_addr_list *list;
894 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
895 struct rte_eth_dev_data *data = dev->data;
896 struct ether_addr *addr;
897 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
898 sizeof(struct i40e_virtchnl_ether_addr)];
900 struct vf_cmd_info args;
902 addr = &(data->mac_addrs[index]);
904 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
905 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
906 addr->addr_bytes[0], addr->addr_bytes[1],
907 addr->addr_bytes[2], addr->addr_bytes[3],
908 addr->addr_bytes[4], addr->addr_bytes[5]);
912 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
913 list->vsi_id = vf->vsi_res->vsi_id;
914 list->num_elements = 1;
915 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
916 sizeof(addr->addr_bytes));
918 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
919 args.in_args = cmd_buffer;
920 args.in_args_size = sizeof(cmd_buffer);
921 args.out_buffer = vf->aq_resp;
922 args.out_size = I40E_AQ_BUF_SZ;
923 err = i40evf_execute_vf_cmd(dev, &args);
925 PMD_DRV_LOG(ERR, "fail to execute command "
926 "OP_DEL_ETHER_ADDRESS");
931 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
933 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
934 struct i40e_virtchnl_queue_select q_stats;
936 struct vf_cmd_info args;
938 memset(&q_stats, 0, sizeof(q_stats));
939 q_stats.vsi_id = vf->vsi_res->vsi_id;
940 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
941 args.in_args = (u8 *)&q_stats;
942 args.in_args_size = sizeof(q_stats);
943 args.out_buffer = vf->aq_resp;
944 args.out_size = I40E_AQ_BUF_SZ;
946 err = i40evf_execute_vf_cmd(dev, &args);
948 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
952 *pstats = (struct i40e_eth_stats *)args.out_buffer;
957 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
960 struct i40e_eth_stats *pstats = NULL;
962 ret = i40evf_update_stats(dev, &pstats);
966 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
967 pstats->rx_broadcast;
968 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
970 stats->ierrors = pstats->rx_discards;
971 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
972 stats->ibytes = pstats->rx_bytes;
973 stats->obytes = pstats->tx_bytes;
979 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
981 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
982 struct i40e_eth_stats *pstats = NULL;
984 /* read stat values to clear hardware registers */
985 i40evf_update_stats(dev, &pstats);
987 /* set stats offset base on current values */
988 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
991 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
992 struct rte_eth_xstat_name *xstats_names,
993 __rte_unused unsigned limit)
997 if (xstats_names != NULL)
998 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
999 snprintf(xstats_names[i].name,
1000 sizeof(xstats_names[i].name),
1001 "%s", rte_i40evf_stats_strings[i].name);
1003 return I40EVF_NB_XSTATS;
1006 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1007 struct rte_eth_xstat *xstats, unsigned n)
1011 struct i40e_eth_stats *pstats = NULL;
1013 if (n < I40EVF_NB_XSTATS)
1014 return I40EVF_NB_XSTATS;
1016 ret = i40evf_update_stats(dev, &pstats);
1023 /* loop over xstats array and values from pstats */
1024 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1026 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1027 rte_i40evf_stats_strings[i].offset);
1030 return I40EVF_NB_XSTATS;
1034 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1036 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1037 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1038 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1041 struct vf_cmd_info args;
1043 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1044 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1045 vlan_list->num_elements = 1;
1046 vlan_list->vlan_id[0] = vlanid;
1048 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1049 args.in_args = (u8 *)&cmd_buffer;
1050 args.in_args_size = sizeof(cmd_buffer);
1051 args.out_buffer = vf->aq_resp;
1052 args.out_size = I40E_AQ_BUF_SZ;
1053 err = i40evf_execute_vf_cmd(dev, &args);
1055 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1061 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1063 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1064 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1065 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1068 struct vf_cmd_info args;
1070 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1071 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1072 vlan_list->num_elements = 1;
1073 vlan_list->vlan_id[0] = vlanid;
1075 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1076 args.in_args = (u8 *)&cmd_buffer;
1077 args.in_args_size = sizeof(cmd_buffer);
1078 args.out_buffer = vf->aq_resp;
1079 args.out_size = I40E_AQ_BUF_SZ;
1080 err = i40evf_execute_vf_cmd(dev, &args);
1082 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1088 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
1090 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1092 struct vf_cmd_info args;
1093 struct rte_eth_link *new_link;
1095 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
1096 args.in_args = NULL;
1097 args.in_args_size = 0;
1098 args.out_buffer = vf->aq_resp;
1099 args.out_size = I40E_AQ_BUF_SZ;
1100 err = i40evf_execute_vf_cmd(dev, &args);
1102 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
1106 new_link = (struct rte_eth_link *)args.out_buffer;
1107 (void)rte_memcpy(link, new_link, sizeof(*link));
1112 static const struct rte_pci_id pci_id_i40evf_map[] = {
1113 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1114 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1115 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1116 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1117 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1118 { .vendor_id = 0, /* sentinel */ },
1122 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1123 struct rte_eth_link *link)
1125 struct rte_eth_link *dst = &(dev->data->dev_link);
1126 struct rte_eth_link *src = link;
1128 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1129 *(uint64_t *)src) == 0)
1137 i40evf_disable_irq0(struct i40e_hw *hw)
1139 /* Disable all interrupt types */
1140 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1141 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1142 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1143 I40EVF_WRITE_FLUSH(hw);
1148 i40evf_enable_irq0(struct i40e_hw *hw)
1150 /* Enable admin queue interrupt trigger */
1153 i40evf_disable_irq0(hw);
1154 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1155 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1156 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1157 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1159 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1160 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1161 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1162 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1164 I40EVF_WRITE_FLUSH(hw);
1168 i40evf_reset_vf(struct i40e_hw *hw)
1172 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1177 * After issuing vf reset command to pf, pf won't necessarily
1178 * reset vf, it depends on what state it exactly is. If it's not
1179 * initialized yet, it won't have vf reset since it's in a certain
1180 * state. If not, it will try to reset. Even vf is reset, pf will
1181 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1182 * it to ACTIVE. In this duration, vf may not catch the moment that
1183 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1187 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1188 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1189 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1190 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1191 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1197 if (i >= MAX_RESET_WAIT_CNT) {
1198 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1206 i40evf_init_vf(struct rte_eth_dev *dev)
1209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1210 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1211 struct ether_addr *p_mac_addr;
1213 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1215 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1216 vf->dev_data = dev->data;
1217 err = i40e_set_mac_type(hw);
1219 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1223 i40e_init_adminq_parameter(hw);
1224 err = i40e_init_adminq(hw);
1226 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1230 /* Reset VF and wait until it's complete */
1231 if (i40evf_reset_vf(hw)) {
1232 PMD_INIT_LOG(ERR, "reset NIC failed");
1236 /* VF reset, shutdown admin queue and initialize again */
1237 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1238 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1242 i40e_init_adminq_parameter(hw);
1243 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1244 PMD_INIT_LOG(ERR, "init_adminq failed");
1247 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1249 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1252 if (i40evf_check_api_version(dev) != 0) {
1253 PMD_INIT_LOG(ERR, "check_api version failed");
1256 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1257 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1258 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1260 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1264 if (i40evf_get_vf_resource(dev) != 0) {
1265 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1269 /* got VF config message back from PF, now we can parse it */
1270 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1271 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1272 vf->vsi_res = &vf->vf_res->vsi_res[i];
1276 PMD_INIT_LOG(ERR, "no LAN VSI found");
1280 if (hw->mac.type == I40E_MAC_X722_VF)
1281 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1282 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1283 vf->vsi.type = vf->vsi_res->vsi_type;
1284 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1285 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1287 /* Store the MAC address configured by host, or generate random one */
1288 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1289 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1290 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1292 eth_random_addr(hw->mac.addr); /* Generate a random one */
1294 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1295 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1296 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1297 (I40E_ITR_INDEX_DEFAULT <<
1298 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1300 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1301 I40EVF_WRITE_FLUSH(hw);
1307 rte_free(vf->vf_res);
1309 i40e_shutdown_adminq(hw); /* ignore error */
1315 i40evf_uninit_vf(struct rte_eth_dev *dev)
1317 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320 PMD_INIT_FUNC_TRACE();
1322 if (hw->adapter_stopped == 0)
1323 i40evf_dev_close(dev);
1324 rte_free(vf->vf_res);
1326 rte_free(vf->aq_resp);
1333 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1335 __rte_unused uint16_t msglen)
1337 struct i40e_virtchnl_pf_event *pf_msg =
1338 (struct i40e_virtchnl_pf_event *)msg;
1339 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1341 switch (pf_msg->event) {
1342 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1343 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1344 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
1346 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1347 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1348 vf->link_up = pf_msg->event_data.link_event.link_status;
1349 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1351 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1352 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1355 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1361 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1365 struct i40e_arq_event_info info;
1366 struct i40e_virtchnl_msg *v_msg;
1367 uint16_t pending, opcode;
1370 info.buf_len = I40E_AQ_BUF_SZ;
1372 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1375 info.msg_buf = vf->aq_resp;
1376 v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1380 ret = i40e_clean_arq_element(hw, &info, &pending);
1382 if (ret != I40E_SUCCESS) {
1383 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1387 opcode = rte_le_to_cpu_16(info.desc.opcode);
1390 case i40e_aqc_opc_send_msg_to_vf:
1391 if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1393 i40evf_handle_pf_event(dev, info.msg_buf,
1396 /* read message and it's expected one */
1397 if (v_msg->v_opcode == vf->pend_cmd) {
1398 vf->cmd_retval = v_msg->v_retval;
1399 /* prevent compiler reordering */
1400 rte_compiler_barrier();
1403 PMD_DRV_LOG(ERR, "command mismatch,"
1404 "expect %u, get %u",
1405 vf->pend_cmd, v_msg->v_opcode);
1406 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1407 " opcode = %d\n", v_msg->v_opcode);
1411 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1419 * Interrupt handler triggered by NIC for handling
1420 * specific interrupt. Only adminq interrupt is processed in VF.
1423 * Pointer to interrupt handle.
1425 * The address of parameter (struct rte_eth_dev *) regsitered before.
1431 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1434 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1435 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438 i40evf_disable_irq0(hw);
1440 /* read out interrupt causes */
1441 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1443 /* No interrupt event indicated */
1444 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1445 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1449 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1450 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1451 i40evf_handle_aq_msg(dev);
1454 /* Link Status Change interrupt */
1455 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1456 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1460 i40evf_enable_irq0(hw);
1461 rte_intr_enable(&dev->pci_dev->intr_handle);
1465 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1468 eth_dev->data->dev_private);
1469 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1471 PMD_INIT_FUNC_TRACE();
1473 /* assign ops func pointer */
1474 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1475 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1476 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1479 * For secondary processes, we don't initialise any further as primary
1480 * has already done this work.
1482 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1483 i40e_set_rx_function(eth_dev);
1484 i40e_set_tx_function(eth_dev);
1488 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1490 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1491 hw->device_id = eth_dev->pci_dev->id.device_id;
1492 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1493 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1494 hw->bus.device = eth_dev->pci_dev->addr.devid;
1495 hw->bus.func = eth_dev->pci_dev->addr.function;
1496 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1497 hw->adapter_stopped = 0;
1499 if(i40evf_init_vf(eth_dev) != 0) {
1500 PMD_INIT_LOG(ERR, "Init vf failed");
1504 /* register callback func to eal lib */
1505 rte_intr_callback_register(&pci_dev->intr_handle,
1506 i40evf_dev_interrupt_handler, (void *)eth_dev);
1508 /* enable uio intr after callback register */
1509 rte_intr_enable(&pci_dev->intr_handle);
1511 /* configure and enable device interrupt */
1512 i40evf_enable_irq0(hw);
1515 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1516 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1518 if (eth_dev->data->mac_addrs == NULL) {
1519 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1520 " store MAC addresses",
1521 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1524 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1525 ð_dev->data->mac_addrs[0]);
1531 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1533 PMD_INIT_FUNC_TRACE();
1535 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1538 eth_dev->dev_ops = NULL;
1539 eth_dev->rx_pkt_burst = NULL;
1540 eth_dev->tx_pkt_burst = NULL;
1542 if (i40evf_uninit_vf(eth_dev) != 0) {
1543 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1547 rte_free(eth_dev->data->mac_addrs);
1548 eth_dev->data->mac_addrs = NULL;
1553 * virtual function driver struct
1555 static struct eth_driver rte_i40evf_pmd = {
1557 .name = "rte_i40evf_pmd",
1558 .id_table = pci_id_i40evf_map,
1559 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1561 .eth_dev_init = i40evf_dev_init,
1562 .eth_dev_uninit = i40evf_dev_uninit,
1563 .dev_private_size = sizeof(struct i40e_adapter),
1567 * VF Driver initialization routine.
1568 * Invoked one at EAL init time.
1569 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1572 rte_i40evf_pmd_init(const char *name __rte_unused,
1573 const char *params __rte_unused)
1575 PMD_INIT_FUNC_TRACE();
1577 rte_eth_driver_register(&rte_i40evf_pmd);
1582 static struct rte_driver rte_i40evf_driver = {
1584 .init = rte_i40evf_pmd_init,
1587 PMD_REGISTER_DRIVER(rte_i40evf_driver, i40evf);
1588 DRIVER_REGISTER_PCI_TABLE(i40evf, pci_id_i40evf_map);
1591 i40evf_dev_configure(struct rte_eth_dev *dev)
1593 struct i40e_adapter *ad =
1594 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1595 struct rte_eth_conf *conf = &dev->data->dev_conf;
1598 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1599 * allocation or vector Rx preconditions we will reset it.
1601 ad->rx_bulk_alloc_allowed = true;
1602 ad->rx_vec_allowed = true;
1603 ad->tx_simple_allowed = true;
1604 ad->tx_vec_allowed = true;
1606 /* For non-DPDK PF drivers, VF has no ability to disable HW
1607 * CRC strip, and is implicitly enabled by the PF.
1609 if (!conf->rxmode.hw_strip_crc) {
1610 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1611 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1612 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1613 /* Peer is running non-DPDK PF driver. */
1614 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1619 return i40evf_init_vlan(dev);
1623 i40evf_init_vlan(struct rte_eth_dev *dev)
1625 struct rte_eth_dev_data *data = dev->data;
1628 /* Apply vlan offload setting */
1629 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1631 /* Apply pvid setting */
1632 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1633 data->dev_conf.txmode.hw_vlan_insert_pvid);
1638 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1640 bool enable_vlan_strip = 0;
1641 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1642 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1644 /* Linux pf host doesn't support vlan offload yet */
1645 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1646 /* Vlan stripping setting */
1647 if (mask & ETH_VLAN_STRIP_MASK) {
1648 /* Enable or disable VLAN stripping */
1649 if (dev_conf->rxmode.hw_vlan_strip)
1650 enable_vlan_strip = 1;
1652 enable_vlan_strip = 0;
1654 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1660 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1662 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1663 struct i40e_vsi_vlan_pvid_info info;
1664 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1666 memset(&info, 0, sizeof(info));
1669 /* Linux pf host don't support vlan offload yet */
1670 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1672 info.config.pvid = pvid;
1674 info.config.reject.tagged =
1675 dev_conf->txmode.hw_vlan_reject_tagged;
1676 info.config.reject.untagged =
1677 dev_conf->txmode.hw_vlan_reject_untagged;
1679 return i40evf_config_vlan_pvid(dev, &info);
1686 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1688 struct i40e_rx_queue *rxq;
1690 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 PMD_INIT_FUNC_TRACE();
1694 if (rx_queue_id < dev->data->nb_rx_queues) {
1695 rxq = dev->data->rx_queues[rx_queue_id];
1697 err = i40e_alloc_rx_queue_mbufs(rxq);
1699 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1705 /* Init the RX tail register. */
1706 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1707 I40EVF_WRITE_FLUSH(hw);
1709 /* Ready to switch the queue on */
1710 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1713 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1716 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1723 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1725 struct i40e_rx_queue *rxq;
1728 if (rx_queue_id < dev->data->nb_rx_queues) {
1729 rxq = dev->data->rx_queues[rx_queue_id];
1731 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1734 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1739 i40e_rx_queue_release_mbufs(rxq);
1740 i40e_reset_rx_queue(rxq);
1741 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1748 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1752 PMD_INIT_FUNC_TRACE();
1754 if (tx_queue_id < dev->data->nb_tx_queues) {
1756 /* Ready to switch the queue on */
1757 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1760 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1763 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1770 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1772 struct i40e_tx_queue *txq;
1775 if (tx_queue_id < dev->data->nb_tx_queues) {
1776 txq = dev->data->tx_queues[tx_queue_id];
1778 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1781 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1786 i40e_tx_queue_release_mbufs(txq);
1787 i40e_reset_tx_queue(txq);
1788 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1795 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1800 ret = i40evf_add_vlan(dev, vlan_id);
1802 ret = i40evf_del_vlan(dev,vlan_id);
1808 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1811 struct rte_eth_dev_data *dev_data = dev->data;
1812 struct rte_pktmbuf_pool_private *mbp_priv;
1813 uint16_t buf_size, len;
1815 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1816 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1817 I40EVF_WRITE_FLUSH(hw);
1819 /* Calculate the maximum packet length allowed */
1820 mbp_priv = rte_mempool_get_priv(rxq->mp);
1821 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1822 RTE_PKTMBUF_HEADROOM);
1823 rxq->hs_mode = i40e_header_split_none;
1824 rxq->rx_hdr_len = 0;
1825 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1826 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1827 rxq->max_pkt_len = RTE_MIN(len,
1828 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1831 * Check if the jumbo frame and maximum packet length are set correctly
1833 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1834 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1835 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1836 PMD_DRV_LOG(ERR, "maximum packet length must be "
1837 "larger than %u and smaller than %u, as jumbo "
1838 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1839 (uint32_t)I40E_FRAME_SIZE_MAX);
1840 return I40E_ERR_CONFIG;
1843 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1844 rxq->max_pkt_len > ETHER_MAX_LEN) {
1845 PMD_DRV_LOG(ERR, "maximum packet length must be "
1846 "larger than %u and smaller than %u, as jumbo "
1847 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1848 (uint32_t)ETHER_MAX_LEN);
1849 return I40E_ERR_CONFIG;
1853 if (dev_data->dev_conf.rxmode.enable_scatter ||
1854 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1855 dev_data->scattered_rx = 1;
1862 i40evf_rx_init(struct rte_eth_dev *dev)
1864 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1866 int ret = I40E_SUCCESS;
1867 struct i40e_rx_queue **rxq =
1868 (struct i40e_rx_queue **)dev->data->rx_queues;
1870 i40evf_config_rss(vf);
1871 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1872 if (!rxq[i] || !rxq[i]->q_set)
1874 ret = i40evf_rxq_init(dev, rxq[i]);
1875 if (ret != I40E_SUCCESS)
1878 if (ret == I40E_SUCCESS)
1879 i40e_set_rx_function(dev);
1885 i40evf_tx_init(struct rte_eth_dev *dev)
1888 struct i40e_tx_queue **txq =
1889 (struct i40e_tx_queue **)dev->data->tx_queues;
1890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892 for (i = 0; i < dev->data->nb_tx_queues; i++)
1893 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1895 i40e_set_tx_function(dev);
1899 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1901 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1902 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1905 if (!rte_intr_allow_others(intr_handle)) {
1907 I40E_VFINT_DYN_CTL01,
1908 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1909 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1910 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1911 I40EVF_WRITE_FLUSH(hw);
1915 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1916 /* To support DPDK PF host */
1918 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1919 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1920 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1921 /* If host driver is kernel driver, do nothing.
1922 * Interrupt 0 is used for rx packets, but don't set
1923 * I40E_VFINT_DYN_CTL01,
1924 * because it is already done in i40evf_enable_irq0.
1927 I40EVF_WRITE_FLUSH(hw);
1931 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1933 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1937 if (!rte_intr_allow_others(intr_handle)) {
1938 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1939 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1940 I40EVF_WRITE_FLUSH(hw);
1944 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1946 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1949 /* If host driver is kernel driver, do nothing.
1950 * Interrupt 0 is used for rx packets, but don't zero
1951 * I40E_VFINT_DYN_CTL01,
1952 * because interrupt 0 is also used for adminq processing.
1955 I40EVF_WRITE_FLUSH(hw);
1959 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1961 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1962 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1967 msix_intr = intr_handle->intr_vec[queue_id];
1968 if (msix_intr == I40E_MISC_VEC_ID)
1969 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1970 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1971 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1972 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1974 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1977 I40E_VFINT_DYN_CTLN1(msix_intr -
1979 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1980 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1981 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1983 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1985 I40EVF_WRITE_FLUSH(hw);
1987 rte_intr_enable(&dev->pci_dev->intr_handle);
1993 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1995 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1996 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999 msix_intr = intr_handle->intr_vec[queue_id];
2000 if (msix_intr == I40E_MISC_VEC_ID)
2001 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2004 I40E_VFINT_DYN_CTLN1(msix_intr -
2008 I40EVF_WRITE_FLUSH(hw);
2014 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2016 struct i40e_virtchnl_ether_addr_list *list;
2017 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2022 struct ether_addr *addr;
2023 struct vf_cmd_info args;
2027 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2028 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2029 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2031 len += sizeof(struct i40e_virtchnl_ether_addr);
2032 if (len >= I40E_AQ_BUF_SZ) {
2038 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2040 for (i = begin; i < next_begin; i++) {
2041 addr = &dev->data->mac_addrs[i];
2042 if (is_zero_ether_addr(addr))
2044 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2045 sizeof(addr->addr_bytes));
2046 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2047 addr->addr_bytes[0], addr->addr_bytes[1],
2048 addr->addr_bytes[2], addr->addr_bytes[3],
2049 addr->addr_bytes[4], addr->addr_bytes[5]);
2052 list->vsi_id = vf->vsi_res->vsi_id;
2053 list->num_elements = j;
2054 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2055 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2056 args.in_args = (uint8_t *)list;
2057 args.in_args_size = len;
2058 args.out_buffer = vf->aq_resp;
2059 args.out_size = I40E_AQ_BUF_SZ;
2060 err = i40evf_execute_vf_cmd(dev, &args);
2062 PMD_DRV_LOG(ERR, "fail to execute command %s",
2063 add ? "OP_ADD_ETHER_ADDRESS" :
2064 "OP_DEL_ETHER_ADDRESS");
2067 } while (begin < I40E_NUM_MACADDR_MAX);
2071 i40evf_dev_start(struct rte_eth_dev *dev)
2073 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2076 uint32_t intr_vector = 0;
2078 PMD_INIT_FUNC_TRACE();
2080 hw->adapter_stopped = 0;
2082 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2083 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2084 dev->data->nb_tx_queues);
2086 /* check and configure queue intr-vector mapping */
2087 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2088 intr_vector = dev->data->nb_rx_queues;
2089 if (rte_intr_efd_enable(intr_handle, intr_vector))
2093 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2094 intr_handle->intr_vec =
2095 rte_zmalloc("intr_vec",
2096 dev->data->nb_rx_queues * sizeof(int), 0);
2097 if (!intr_handle->intr_vec) {
2098 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2099 " intr_vec\n", dev->data->nb_rx_queues);
2104 if (i40evf_rx_init(dev) != 0){
2105 PMD_DRV_LOG(ERR, "failed to do RX init");
2109 i40evf_tx_init(dev);
2111 if (i40evf_configure_queues(dev) != 0) {
2112 PMD_DRV_LOG(ERR, "configure queues failed");
2115 if (i40evf_config_irq_map(dev)) {
2116 PMD_DRV_LOG(ERR, "config_irq_map failed");
2120 /* Set all mac addrs */
2121 i40evf_add_del_all_mac_addr(dev, TRUE);
2123 if (i40evf_start_queues(dev) != 0) {
2124 PMD_DRV_LOG(ERR, "enable queues failed");
2128 i40evf_enable_queues_intr(dev);
2132 i40evf_add_del_all_mac_addr(dev, FALSE);
2138 i40evf_dev_stop(struct rte_eth_dev *dev)
2140 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2142 PMD_INIT_FUNC_TRACE();
2144 i40evf_stop_queues(dev);
2145 i40evf_disable_queues_intr(dev);
2146 i40e_dev_clear_queues(dev);
2148 /* Clean datapath event and queue/vec mapping */
2149 rte_intr_efd_disable(intr_handle);
2150 if (intr_handle->intr_vec) {
2151 rte_free(intr_handle->intr_vec);
2152 intr_handle->intr_vec = NULL;
2154 /* remove all mac addrs */
2155 i40evf_add_del_all_mac_addr(dev, FALSE);
2160 i40evf_dev_link_update(struct rte_eth_dev *dev,
2161 __rte_unused int wait_to_complete)
2163 struct rte_eth_link new_link;
2164 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2166 * DPDK pf host provide interfacet to acquire link status
2167 * while Linux driver does not
2169 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
2170 i40evf_get_link_status(dev, &new_link);
2172 /* Linux driver PF host */
2173 switch (vf->link_speed) {
2174 case I40E_LINK_SPEED_100MB:
2175 new_link.link_speed = ETH_SPEED_NUM_100M;
2177 case I40E_LINK_SPEED_1GB:
2178 new_link.link_speed = ETH_SPEED_NUM_1G;
2180 case I40E_LINK_SPEED_10GB:
2181 new_link.link_speed = ETH_SPEED_NUM_10G;
2183 case I40E_LINK_SPEED_20GB:
2184 new_link.link_speed = ETH_SPEED_NUM_20G;
2186 case I40E_LINK_SPEED_40GB:
2187 new_link.link_speed = ETH_SPEED_NUM_40G;
2190 new_link.link_speed = ETH_SPEED_NUM_100M;
2193 /* full duplex only */
2194 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2195 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2198 i40evf_dev_atomic_write_link_status(dev, &new_link);
2204 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2206 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2209 /* If enabled, just return */
2210 if (vf->promisc_unicast_enabled)
2213 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2215 vf->promisc_unicast_enabled = TRUE;
2219 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2221 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2224 /* If disabled, just return */
2225 if (!vf->promisc_unicast_enabled)
2228 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2230 vf->promisc_unicast_enabled = FALSE;
2234 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2236 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2239 /* If enabled, just return */
2240 if (vf->promisc_multicast_enabled)
2243 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2245 vf->promisc_multicast_enabled = TRUE;
2249 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2251 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2254 /* If enabled, just return */
2255 if (!vf->promisc_multicast_enabled)
2258 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2260 vf->promisc_multicast_enabled = FALSE;
2264 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2266 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2268 memset(dev_info, 0, sizeof(*dev_info));
2269 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2270 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2271 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2272 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2273 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2274 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2275 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2276 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2277 dev_info->rx_offload_capa =
2278 DEV_RX_OFFLOAD_VLAN_STRIP |
2279 DEV_RX_OFFLOAD_QINQ_STRIP |
2280 DEV_RX_OFFLOAD_IPV4_CKSUM |
2281 DEV_RX_OFFLOAD_UDP_CKSUM |
2282 DEV_RX_OFFLOAD_TCP_CKSUM;
2283 dev_info->tx_offload_capa =
2284 DEV_TX_OFFLOAD_VLAN_INSERT |
2285 DEV_TX_OFFLOAD_QINQ_INSERT |
2286 DEV_TX_OFFLOAD_IPV4_CKSUM |
2287 DEV_TX_OFFLOAD_UDP_CKSUM |
2288 DEV_TX_OFFLOAD_TCP_CKSUM |
2289 DEV_TX_OFFLOAD_SCTP_CKSUM;
2291 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2293 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2294 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2295 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2297 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2301 dev_info->default_txconf = (struct rte_eth_txconf) {
2303 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2304 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2305 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2307 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2308 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2309 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2310 ETH_TXQ_FLAGS_NOOFFLOADS,
2313 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2314 .nb_max = I40E_MAX_RING_DESC,
2315 .nb_min = I40E_MIN_RING_DESC,
2316 .nb_align = I40E_ALIGN_RING_DESC,
2319 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2320 .nb_max = I40E_MAX_RING_DESC,
2321 .nb_min = I40E_MIN_RING_DESC,
2322 .nb_align = I40E_ALIGN_RING_DESC,
2327 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2329 if (i40evf_get_statics(dev, stats))
2330 PMD_DRV_LOG(ERR, "Get statics failed");
2334 i40evf_dev_close(struct rte_eth_dev *dev)
2336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337 struct rte_pci_device *pci_dev = dev->pci_dev;
2339 i40evf_dev_stop(dev);
2340 hw->adapter_stopped = 1;
2341 i40e_dev_free_queues(dev);
2342 i40evf_reset_vf(hw);
2343 i40e_shutdown_adminq(hw);
2344 /* disable uio intr before callback unregister */
2345 rte_intr_disable(&pci_dev->intr_handle);
2347 /* unregister callback func from eal lib */
2348 rte_intr_callback_unregister(&pci_dev->intr_handle,
2349 i40evf_dev_interrupt_handler, (void *)dev);
2350 i40evf_disable_irq0(hw);
2354 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2356 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2357 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2363 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2364 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2367 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2371 uint32_t *lut_dw = (uint32_t *)lut;
2372 uint16_t i, lut_size_dw = lut_size / 4;
2374 for (i = 0; i < lut_size_dw; i++)
2375 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2382 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2391 vf = I40E_VSI_TO_VF(vsi);
2392 hw = I40E_VSI_TO_HW(vsi);
2394 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2395 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2398 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2402 uint32_t *lut_dw = (uint32_t *)lut;
2403 uint16_t i, lut_size_dw = lut_size / 4;
2405 for (i = 0; i < lut_size_dw; i++)
2406 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2407 I40EVF_WRITE_FLUSH(hw);
2414 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2415 struct rte_eth_rss_reta_entry64 *reta_conf,
2418 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2420 uint16_t i, idx, shift;
2423 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2424 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2425 "(%d) doesn't match the number of hardware can "
2426 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2430 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2432 PMD_DRV_LOG(ERR, "No memory can be allocated");
2435 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2438 for (i = 0; i < reta_size; i++) {
2439 idx = i / RTE_RETA_GROUP_SIZE;
2440 shift = i % RTE_RETA_GROUP_SIZE;
2441 if (reta_conf[idx].mask & (1ULL << shift))
2442 lut[i] = reta_conf[idx].reta[shift];
2444 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2453 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2454 struct rte_eth_rss_reta_entry64 *reta_conf,
2457 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2458 uint16_t i, idx, shift;
2462 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2463 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2464 "(%d) doesn't match the number of hardware can "
2465 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2469 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2471 PMD_DRV_LOG(ERR, "No memory can be allocated");
2475 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2478 for (i = 0; i < reta_size; i++) {
2479 idx = i / RTE_RETA_GROUP_SIZE;
2480 shift = i % RTE_RETA_GROUP_SIZE;
2481 if (reta_conf[idx].mask & (1ULL << shift))
2482 reta_conf[idx].reta[shift] = lut[i];
2492 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2494 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2495 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2498 if (!key || key_len == 0) {
2499 PMD_DRV_LOG(DEBUG, "No key to be configured");
2501 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2503 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2507 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2508 struct i40e_aqc_get_set_rss_key_data *key_dw =
2509 (struct i40e_aqc_get_set_rss_key_data *)key;
2511 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2513 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2516 uint32_t *hash_key = (uint32_t *)key;
2519 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2520 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2521 I40EVF_WRITE_FLUSH(hw);
2528 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2530 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2534 if (!key || !key_len)
2537 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2538 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2539 (struct i40e_aqc_get_set_rss_key_data *)key);
2541 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2545 uint32_t *key_dw = (uint32_t *)key;
2548 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2549 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2551 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2557 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2559 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2560 uint64_t rss_hf, hena;
2563 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2564 rss_conf->rss_key_len);
2568 rss_hf = rss_conf->rss_hf;
2569 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2570 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2571 hena &= ~I40E_RSS_HENA_ALL;
2572 hena |= i40e_config_hena(rss_hf);
2573 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2574 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2575 I40EVF_WRITE_FLUSH(hw);
2581 i40evf_disable_rss(struct i40e_vf *vf)
2583 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2586 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2587 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2588 hena &= ~I40E_RSS_HENA_ALL;
2589 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2590 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2591 I40EVF_WRITE_FLUSH(hw);
2595 i40evf_config_rss(struct i40e_vf *vf)
2597 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2598 struct rte_eth_rss_conf rss_conf;
2599 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2602 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2603 i40evf_disable_rss(vf);
2604 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2608 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2609 /* Fill out the look up table */
2610 for (i = 0, j = 0; i < nb_q; i++, j++) {
2613 lut = (lut << 8) | j;
2615 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2618 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2619 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2620 i40evf_disable_rss(vf);
2621 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2625 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2626 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2627 /* Calculate the default hash key */
2628 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2629 rss_key_default[i] = (uint32_t)rte_rand();
2630 rss_conf.rss_key = (uint8_t *)rss_key_default;
2631 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2635 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2639 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2640 struct rte_eth_rss_conf *rss_conf)
2642 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2647 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2648 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2649 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2650 if (rss_hf != 0) /* Enable RSS */
2656 if (rss_hf == 0) /* Disable RSS */
2659 return i40evf_hw_rss_hash_set(vf, rss_conf);
2663 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2664 struct rte_eth_rss_conf *rss_conf)
2666 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2671 &rss_conf->rss_key_len);
2673 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2674 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2675 rss_conf->rss_hf = i40e_parse_hena(hena);