1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int i40evf_init_vlan(struct rte_eth_dev *dev);
101 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
102 uint16_t rx_queue_id);
103 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
104 uint16_t rx_queue_id);
105 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
106 uint16_t tx_queue_id);
107 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
108 uint16_t tx_queue_id);
109 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
110 struct rte_ether_addr *addr,
113 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
114 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
115 struct rte_eth_rss_reta_entry64 *reta_conf,
117 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
118 struct rte_eth_rss_reta_entry64 *reta_conf,
120 static int i40evf_config_rss(struct i40e_vf *vf);
121 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
122 struct rte_eth_rss_conf *rss_conf);
123 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
124 struct rte_eth_rss_conf *rss_conf);
125 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr);
129 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
131 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
132 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
137 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
138 struct rte_ether_addr *mc_addr_set,
139 uint32_t nb_mc_addr, bool add);
141 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
142 struct rte_ether_addr *mc_addr_set,
143 uint32_t nb_mc_addr);
145 i40evf_dev_alarm_handler(void *param);
147 /* Default hash key buffer for RSS */
148 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
150 struct rte_i40evf_xstats_name_off {
151 char name[RTE_ETH_XSTATS_NAME_SIZE];
155 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
156 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
157 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
158 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
159 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
160 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
161 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
162 rx_unknown_protocol)},
163 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
164 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
165 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
166 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
167 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
168 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
171 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
172 sizeof(rte_i40evf_stats_strings[0]))
174 static const struct eth_dev_ops i40evf_eth_dev_ops = {
175 .dev_configure = i40evf_dev_configure,
176 .dev_start = i40evf_dev_start,
177 .dev_stop = i40evf_dev_stop,
178 .promiscuous_enable = i40evf_dev_promiscuous_enable,
179 .promiscuous_disable = i40evf_dev_promiscuous_disable,
180 .allmulticast_enable = i40evf_dev_allmulticast_enable,
181 .allmulticast_disable = i40evf_dev_allmulticast_disable,
182 .link_update = i40evf_dev_link_update,
183 .stats_get = i40evf_dev_stats_get,
184 .stats_reset = i40evf_dev_xstats_reset,
185 .xstats_get = i40evf_dev_xstats_get,
186 .xstats_get_names = i40evf_dev_xstats_get_names,
187 .xstats_reset = i40evf_dev_xstats_reset,
188 .dev_close = i40evf_dev_close,
189 .dev_reset = i40evf_dev_reset,
190 .dev_infos_get = i40evf_dev_info_get,
191 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
192 .vlan_filter_set = i40evf_vlan_filter_set,
193 .vlan_offload_set = i40evf_vlan_offload_set,
194 .rx_queue_start = i40evf_dev_rx_queue_start,
195 .rx_queue_stop = i40evf_dev_rx_queue_stop,
196 .tx_queue_start = i40evf_dev_tx_queue_start,
197 .tx_queue_stop = i40evf_dev_tx_queue_stop,
198 .rx_queue_setup = i40e_dev_rx_queue_setup,
199 .rx_queue_release = i40e_dev_rx_queue_release,
200 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
201 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
202 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
203 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
204 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
205 .tx_queue_setup = i40e_dev_tx_queue_setup,
206 .tx_queue_release = i40e_dev_tx_queue_release,
207 .rx_queue_count = i40e_dev_rx_queue_count,
208 .rxq_info_get = i40e_rxq_info_get,
209 .txq_info_get = i40e_txq_info_get,
210 .mac_addr_add = i40evf_add_mac_addr,
211 .mac_addr_remove = i40evf_del_mac_addr,
212 .set_mc_addr_list = i40evf_set_mc_addr_list,
213 .reta_update = i40evf_dev_rss_reta_update,
214 .reta_query = i40evf_dev_rss_reta_query,
215 .rss_hash_update = i40evf_dev_rss_hash_update,
216 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
217 .mtu_set = i40evf_dev_mtu_set,
218 .mac_addr_set = i40evf_set_default_mac_addr,
219 .tx_done_cleanup = i40e_tx_done_cleanup,
223 * Read data in admin queue to get msg from pf driver
225 static enum i40evf_aq_result
226 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
230 struct i40e_arq_event_info event;
231 enum virtchnl_ops opcode;
232 enum i40e_status_code retval;
234 enum i40evf_aq_result result = I40EVF_MSG_NON;
236 event.buf_len = data->buf_len;
237 event.msg_buf = data->msg;
238 ret = i40e_clean_arq_element(hw, &event, NULL);
239 /* Can't read any msg from adminQ */
241 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
242 result = I40EVF_MSG_ERR;
246 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
247 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
249 if (opcode == VIRTCHNL_OP_EVENT) {
250 struct virtchnl_pf_event *vpe =
251 (struct virtchnl_pf_event *)event.msg_buf;
253 result = I40EVF_MSG_SYS;
254 switch (vpe->event) {
255 case VIRTCHNL_EVENT_LINK_CHANGE:
257 vpe->event_data.link_event.link_status;
259 vpe->event_data.link_event.link_speed;
260 vf->pend_msg |= PFMSG_LINK_CHANGE;
261 PMD_DRV_LOG(INFO, "Link status update:%s",
262 vf->link_up ? "up" : "down");
264 case VIRTCHNL_EVENT_RESET_IMPENDING:
266 vf->pend_msg |= PFMSG_RESET_IMPENDING;
267 PMD_DRV_LOG(INFO, "vf is reseting");
269 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
270 vf->dev_closed = true;
271 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
272 PMD_DRV_LOG(INFO, "PF driver closed");
275 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
276 __func__, vpe->event);
279 /* async reply msg on command issued by vf previously */
280 result = I40EVF_MSG_CMD;
281 /* Actual data length read from PF */
282 data->msg_len = event.msg_len;
285 data->result = retval;
292 * clear current command. Only call in case execute
293 * _atomic_set_cmd successfully.
296 _clear_cmd(struct i40e_vf *vf)
299 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
303 * Check there is pending cmd in execution. If none, set new command.
306 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
308 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
309 VIRTCHNL_OP_UNKNOWN, ops);
312 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
317 #define MAX_TRY_TIMES 200
318 #define ASQ_DELAY_MS 10
321 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
323 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
324 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
325 struct i40evf_arq_msg_info info;
326 enum i40evf_aq_result ret;
329 if (_atomic_set_cmd(vf, args->ops))
332 info.msg = args->out_buffer;
333 info.buf_len = args->out_size;
334 info.ops = VIRTCHNL_OP_UNKNOWN;
335 info.result = I40E_SUCCESS;
337 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
338 args->in_args, args->in_args_size, NULL);
340 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
346 case VIRTCHNL_OP_RESET_VF:
347 /*no need to process in this function */
350 case VIRTCHNL_OP_VERSION:
351 case VIRTCHNL_OP_GET_VF_RESOURCES:
352 /* for init adminq commands, need to poll the response */
355 ret = i40evf_read_pfmsg(dev, &info);
356 vf->cmd_retval = info.result;
357 if (ret == I40EVF_MSG_CMD) {
360 } else if (ret == I40EVF_MSG_ERR)
362 rte_delay_ms(ASQ_DELAY_MS);
363 /* If don't read msg or read sys event, continue */
364 } while (i++ < MAX_TRY_TIMES);
367 case VIRTCHNL_OP_REQUEST_QUEUES:
369 * ignore async reply, only wait for system message,
370 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
371 * if not, means request queues failed.
375 ret = i40evf_read_pfmsg(dev, &info);
376 vf->cmd_retval = info.result;
377 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
380 } else if (ret == I40EVF_MSG_ERR ||
381 ret == I40EVF_MSG_CMD) {
384 rte_delay_ms(ASQ_DELAY_MS);
385 /* If don't read msg or read sys event, continue */
386 } while (i++ < MAX_TRY_TIMES);
391 /* for other adminq in running time, waiting the cmd done flag */
394 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
398 rte_delay_ms(ASQ_DELAY_MS);
399 /* If don't read msg or read sys event, continue */
400 } while (i++ < MAX_TRY_TIMES);
401 /* If there's no response is received, clear command */
402 if (i >= MAX_TRY_TIMES) {
403 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
409 return err | vf->cmd_retval;
413 * Check API version with sync wait until version read or fail from admin queue
416 i40evf_check_api_version(struct rte_eth_dev *dev)
418 struct virtchnl_version_info version, *pver;
420 struct vf_cmd_info args;
421 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
423 version.major = VIRTCHNL_VERSION_MAJOR;
424 version.minor = VIRTCHNL_VERSION_MINOR;
426 args.ops = VIRTCHNL_OP_VERSION;
427 args.in_args = (uint8_t *)&version;
428 args.in_args_size = sizeof(version);
429 args.out_buffer = vf->aq_resp;
430 args.out_size = I40E_AQ_BUF_SZ;
432 err = i40evf_execute_vf_cmd(dev, &args);
434 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
438 pver = (struct virtchnl_version_info *)args.out_buffer;
439 vf->version_major = pver->major;
440 vf->version_minor = pver->minor;
441 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
442 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
443 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
445 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
446 vf->version_major, vf->version_minor,
447 VIRTCHNL_VERSION_MAJOR,
448 VIRTCHNL_VERSION_MINOR);
456 i40evf_get_vf_resource(struct rte_eth_dev *dev)
458 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
461 struct vf_cmd_info args;
464 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
465 args.out_buffer = vf->aq_resp;
466 args.out_size = I40E_AQ_BUF_SZ;
468 caps = VIRTCHNL_VF_OFFLOAD_L2 |
469 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
470 VIRTCHNL_VF_OFFLOAD_RSS_REG |
471 VIRTCHNL_VF_OFFLOAD_VLAN |
472 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
473 args.in_args = (uint8_t *)∩︀
474 args.in_args_size = sizeof(caps);
477 args.in_args_size = 0;
479 err = i40evf_execute_vf_cmd(dev, &args);
482 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
486 len = sizeof(struct virtchnl_vf_resource) +
487 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
489 rte_memcpy(vf->vf_res, args.out_buffer,
490 RTE_MIN(args.out_size, len));
491 i40e_vf_parse_hw_config(hw, vf->vf_res);
497 i40evf_config_promisc(struct rte_eth_dev *dev,
499 bool enable_multicast)
501 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
503 struct vf_cmd_info args;
504 struct virtchnl_promisc_info promisc;
507 promisc.vsi_id = vf->vsi_res->vsi_id;
510 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
512 if (enable_multicast)
513 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
515 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
516 args.in_args = (uint8_t *)&promisc;
517 args.in_args_size = sizeof(promisc);
518 args.out_buffer = vf->aq_resp;
519 args.out_size = I40E_AQ_BUF_SZ;
521 err = i40evf_execute_vf_cmd(dev, &args);
524 PMD_DRV_LOG(ERR, "fail to execute command "
525 "CONFIG_PROMISCUOUS_MODE");
527 if (err == I40E_NOT_SUPPORTED)
533 vf->promisc_unicast_enabled = enable_unicast;
534 vf->promisc_multicast_enabled = enable_multicast;
539 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
541 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
542 struct vf_cmd_info args;
545 memset(&args, 0, sizeof(args));
546 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
548 args.in_args_size = 0;
549 args.out_buffer = vf->aq_resp;
550 args.out_size = I40E_AQ_BUF_SZ;
551 ret = i40evf_execute_vf_cmd(dev, &args);
553 PMD_DRV_LOG(ERR, "Failed to execute command of "
554 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
560 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
562 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
563 struct vf_cmd_info args;
566 memset(&args, 0, sizeof(args));
567 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
569 args.in_args_size = 0;
570 args.out_buffer = vf->aq_resp;
571 args.out_size = I40E_AQ_BUF_SZ;
572 ret = i40evf_execute_vf_cmd(dev, &args);
574 PMD_DRV_LOG(ERR, "Failed to execute command of "
575 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
581 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
585 struct i40e_tx_queue *txq)
587 txq_info->vsi_id = vsi_id;
588 txq_info->queue_id = queue_id;
589 if (queue_id < nb_txq && txq) {
590 txq_info->ring_len = txq->nb_tx_desc;
591 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
596 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
600 uint32_t max_pkt_size,
601 struct i40e_rx_queue *rxq)
603 rxq_info->vsi_id = vsi_id;
604 rxq_info->queue_id = queue_id;
605 rxq_info->max_pkt_size = max_pkt_size;
606 if (queue_id < nb_rxq && rxq) {
607 rxq_info->ring_len = rxq->nb_rx_desc;
608 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
609 rxq_info->databuffer_size =
610 (rte_pktmbuf_data_room_size(rxq->mp) -
611 RTE_PKTMBUF_HEADROOM);
616 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
618 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
619 struct i40e_rx_queue **rxq =
620 (struct i40e_rx_queue **)dev->data->rx_queues;
621 struct i40e_tx_queue **txq =
622 (struct i40e_tx_queue **)dev->data->tx_queues;
623 struct virtchnl_vsi_queue_config_info *vc_vqci;
624 struct virtchnl_queue_pair_info *vc_qpi;
625 struct vf_cmd_info args;
626 uint16_t i, nb_qp = vf->num_queue_pairs;
627 const uint32_t size =
628 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
632 memset(buff, 0, sizeof(buff));
633 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
634 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
635 vc_vqci->num_queue_pairs = nb_qp;
637 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
638 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
639 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
640 txq ? txq[i] : NULL);
641 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
642 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
643 vf->max_pkt_len, rxq ? rxq[i] : NULL);
645 memset(&args, 0, sizeof(args));
646 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
647 args.in_args = (uint8_t *)vc_vqci;
648 args.in_args_size = size;
649 args.out_buffer = vf->aq_resp;
650 args.out_size = I40E_AQ_BUF_SZ;
651 ret = i40evf_execute_vf_cmd(dev, &args);
653 PMD_DRV_LOG(ERR, "Failed to execute command of "
654 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
660 i40evf_config_irq_map(struct rte_eth_dev *dev)
662 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
663 struct vf_cmd_info args;
664 uint8_t *cmd_buffer = NULL;
665 struct virtchnl_irq_map_info *map_info;
666 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
667 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
668 uint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;
669 uint16_t rxq_map[vf->vf_res->max_vectors];
672 memset(rxq_map, 0, sizeof(rxq_map));
673 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
674 rte_intr_allow_others(intr_handle)) {
675 msix_base = I40E_RX_VEC_START;
676 /* For interrupt mode, available vector id is from 1. */
677 max_vectors = vf->vf_res->max_vectors - 1;
678 nb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);
681 for (i = 0; i < dev->data->nb_rx_queues; i++) {
682 rxq_map[vec] |= 1 << i;
683 intr_handle->intr_vec[i] = vec++;
684 if (vec >= vf->vf_res->max_vectors)
688 msix_base = I40E_MISC_VEC_ID;
691 for (i = 0; i < dev->data->nb_rx_queues; i++) {
692 rxq_map[msix_base] |= 1 << i;
693 if (rte_intr_dp_is_en(intr_handle))
694 intr_handle->intr_vec[i] = msix_base;
698 cmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +
699 sizeof(struct virtchnl_vector_map) * nb_msix;
700 cmd_buffer = rte_zmalloc("i40e", cmd_buffer_size, 0);
702 PMD_DRV_LOG(ERR, "Failed to allocate memory");
703 return I40E_ERR_NO_MEMORY;
706 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
707 map_info->num_vectors = nb_msix;
708 for (i = 0; i < nb_msix; i++) {
709 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
710 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
711 map_info->vecmap[i].vector_id = msix_base + i;
712 map_info->vecmap[i].txq_map = 0;
713 map_info->vecmap[i].rxq_map = rxq_map[msix_base + i];
716 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
717 args.in_args = (u8 *)cmd_buffer;
718 args.in_args_size = cmd_buffer_size;
719 args.out_buffer = vf->aq_resp;
720 args.out_size = I40E_AQ_BUF_SZ;
721 err = i40evf_execute_vf_cmd(dev, &args);
723 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
725 rte_free(cmd_buffer);
731 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
734 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
735 struct virtchnl_queue_select queue_select;
737 struct vf_cmd_info args;
738 memset(&queue_select, 0, sizeof(queue_select));
739 queue_select.vsi_id = vf->vsi_res->vsi_id;
742 queue_select.rx_queues |= 1 << qid;
744 queue_select.tx_queues |= 1 << qid;
747 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
749 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
750 args.in_args = (u8 *)&queue_select;
751 args.in_args_size = sizeof(queue_select);
752 args.out_buffer = vf->aq_resp;
753 args.out_size = I40E_AQ_BUF_SZ;
754 err = i40evf_execute_vf_cmd(dev, &args);
756 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
757 isrx ? "RX" : "TX", qid, on ? "on" : "off");
763 i40evf_start_queues(struct rte_eth_dev *dev)
765 struct rte_eth_dev_data *dev_data = dev->data;
767 struct i40e_rx_queue *rxq;
768 struct i40e_tx_queue *txq;
770 for (i = 0; i < dev->data->nb_rx_queues; i++) {
771 rxq = dev_data->rx_queues[i];
772 if (rxq->rx_deferred_start)
774 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
775 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
780 for (i = 0; i < dev->data->nb_tx_queues; i++) {
781 txq = dev_data->tx_queues[i];
782 if (txq->tx_deferred_start)
784 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
785 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
794 i40evf_stop_queues(struct rte_eth_dev *dev)
798 /* Stop TX queues first */
799 for (i = 0; i < dev->data->nb_tx_queues; i++) {
800 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
801 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
805 /* Then stop RX queues */
806 for (i = 0; i < dev->data->nb_rx_queues; i++) {
807 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
808 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
816 i40evf_add_mac_addr(struct rte_eth_dev *dev,
817 struct rte_ether_addr *addr,
818 __rte_unused uint32_t index,
819 __rte_unused uint32_t pool)
821 struct virtchnl_ether_addr_list *list;
822 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
823 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
824 sizeof(struct virtchnl_ether_addr)];
826 struct vf_cmd_info args;
828 if (rte_is_zero_ether_addr(addr)) {
829 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
830 addr->addr_bytes[0], addr->addr_bytes[1],
831 addr->addr_bytes[2], addr->addr_bytes[3],
832 addr->addr_bytes[4], addr->addr_bytes[5]);
833 return I40E_ERR_INVALID_MAC_ADDR;
836 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
837 list->vsi_id = vf->vsi_res->vsi_id;
838 list->num_elements = 1;
839 rte_memcpy(list->list[0].addr, addr->addr_bytes,
840 sizeof(addr->addr_bytes));
842 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
843 args.in_args = cmd_buffer;
844 args.in_args_size = sizeof(cmd_buffer);
845 args.out_buffer = vf->aq_resp;
846 args.out_size = I40E_AQ_BUF_SZ;
847 err = i40evf_execute_vf_cmd(dev, &args);
849 PMD_DRV_LOG(ERR, "fail to execute command "
850 "OP_ADD_ETHER_ADDRESS");
858 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
859 struct rte_ether_addr *addr)
861 struct virtchnl_ether_addr_list *list;
862 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
863 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
864 sizeof(struct virtchnl_ether_addr)];
866 struct vf_cmd_info args;
868 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
869 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
870 addr->addr_bytes[0], addr->addr_bytes[1],
871 addr->addr_bytes[2], addr->addr_bytes[3],
872 addr->addr_bytes[4], addr->addr_bytes[5]);
876 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
877 list->vsi_id = vf->vsi_res->vsi_id;
878 list->num_elements = 1;
879 rte_memcpy(list->list[0].addr, addr->addr_bytes,
880 sizeof(addr->addr_bytes));
882 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
883 args.in_args = cmd_buffer;
884 args.in_args_size = sizeof(cmd_buffer);
885 args.out_buffer = vf->aq_resp;
886 args.out_size = I40E_AQ_BUF_SZ;
887 err = i40evf_execute_vf_cmd(dev, &args);
889 PMD_DRV_LOG(ERR, "fail to execute command "
890 "OP_DEL_ETHER_ADDRESS");
897 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
899 struct rte_eth_dev_data *data = dev->data;
900 struct rte_ether_addr *addr;
902 addr = &data->mac_addrs[index];
904 i40evf_del_mac_addr_by_addr(dev, addr);
908 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
910 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
911 struct virtchnl_queue_select q_stats;
913 struct vf_cmd_info args;
915 memset(&q_stats, 0, sizeof(q_stats));
916 q_stats.vsi_id = vf->vsi_res->vsi_id;
917 args.ops = VIRTCHNL_OP_GET_STATS;
918 args.in_args = (u8 *)&q_stats;
919 args.in_args_size = sizeof(q_stats);
920 args.out_buffer = vf->aq_resp;
921 args.out_size = I40E_AQ_BUF_SZ;
923 err = i40evf_execute_vf_cmd(dev, &args);
925 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
929 *pstats = (struct i40e_eth_stats *)args.out_buffer;
934 i40evf_stat_update_48(uint64_t *offset,
937 if (*stat >= *offset)
938 *stat = *stat - *offset;
940 *stat = (uint64_t)((*stat +
941 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
943 *stat &= I40E_48_BIT_MASK;
947 i40evf_stat_update_32(uint64_t *offset,
950 if (*stat >= *offset)
951 *stat = (uint64_t)(*stat - *offset);
953 *stat = (uint64_t)((*stat +
954 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
958 i40evf_update_stats(struct i40e_vsi *vsi,
959 struct i40e_eth_stats *nes)
961 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
963 i40evf_stat_update_48(&oes->rx_bytes,
965 i40evf_stat_update_48(&oes->rx_unicast,
967 i40evf_stat_update_48(&oes->rx_multicast,
969 i40evf_stat_update_48(&oes->rx_broadcast,
971 i40evf_stat_update_32(&oes->rx_discards,
973 i40evf_stat_update_32(&oes->rx_unknown_protocol,
974 &nes->rx_unknown_protocol);
975 i40evf_stat_update_48(&oes->tx_bytes,
977 i40evf_stat_update_48(&oes->tx_unicast,
979 i40evf_stat_update_48(&oes->tx_multicast,
981 i40evf_stat_update_48(&oes->tx_broadcast,
983 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
984 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
988 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
991 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
992 struct i40e_eth_stats *pstats = NULL;
994 /* read stat values to clear hardware registers */
995 ret = i40evf_query_stats(dev, &pstats);
997 /* set stats offset base on current values */
999 vf->vsi.eth_stats_offset = *pstats;
1004 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1005 struct rte_eth_xstat_name *xstats_names,
1006 __rte_unused unsigned limit)
1010 if (xstats_names != NULL)
1011 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1012 snprintf(xstats_names[i].name,
1013 sizeof(xstats_names[i].name),
1014 "%s", rte_i40evf_stats_strings[i].name);
1016 return I40EVF_NB_XSTATS;
1019 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1020 struct rte_eth_xstat *xstats, unsigned n)
1024 struct i40e_eth_stats *pstats = NULL;
1025 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1026 struct i40e_vsi *vsi = &vf->vsi;
1028 if (n < I40EVF_NB_XSTATS)
1029 return I40EVF_NB_XSTATS;
1031 ret = i40evf_query_stats(dev, &pstats);
1038 i40evf_update_stats(vsi, pstats);
1040 /* loop over xstats array and values from pstats */
1041 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1043 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1044 rte_i40evf_stats_strings[i].offset);
1047 return I40EVF_NB_XSTATS;
1051 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1053 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1054 struct virtchnl_vlan_filter_list *vlan_list;
1055 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1058 struct vf_cmd_info args;
1060 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1061 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1062 vlan_list->num_elements = 1;
1063 vlan_list->vlan_id[0] = vlanid;
1065 args.ops = VIRTCHNL_OP_ADD_VLAN;
1066 args.in_args = (u8 *)&cmd_buffer;
1067 args.in_args_size = sizeof(cmd_buffer);
1068 args.out_buffer = vf->aq_resp;
1069 args.out_size = I40E_AQ_BUF_SZ;
1070 err = i40evf_execute_vf_cmd(dev, &args);
1072 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1078 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1080 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1081 struct virtchnl_vf_res_request vfres;
1082 struct vf_cmd_info args;
1085 vfres.num_queue_pairs = num;
1087 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1088 args.in_args = (u8 *)&vfres;
1089 args.in_args_size = sizeof(vfres);
1090 args.out_buffer = vf->aq_resp;
1091 args.out_size = I40E_AQ_BUF_SZ;
1093 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1095 err = i40evf_execute_vf_cmd(dev, &args);
1097 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);
1099 if (err != I40E_SUCCESS) {
1100 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1104 /* The PF will issue a reset to the VF when change the number of
1105 * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then
1106 * wait 10ms and set it to ACTIVE. In this duration, vf may not catch
1107 * the moment that COMPLETE is set. So, for vf, we'll try to wait a
1112 err = i40evf_check_vf_reset_done(dev);
1114 PMD_DRV_LOG(ERR, "VF is still resetting");
1120 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1122 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1123 struct virtchnl_vlan_filter_list *vlan_list;
1124 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1127 struct vf_cmd_info args;
1129 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1130 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1131 vlan_list->num_elements = 1;
1132 vlan_list->vlan_id[0] = vlanid;
1134 args.ops = VIRTCHNL_OP_DEL_VLAN;
1135 args.in_args = (u8 *)&cmd_buffer;
1136 args.in_args_size = sizeof(cmd_buffer);
1137 args.out_buffer = vf->aq_resp;
1138 args.out_size = I40E_AQ_BUF_SZ;
1139 err = i40evf_execute_vf_cmd(dev, &args);
1141 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1146 static const struct rte_pci_id pci_id_i40evf_map[] = {
1147 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1148 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1149 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1150 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1151 { .vendor_id = 0, /* sentinel */ },
1156 i40evf_disable_irq0(struct i40e_hw *hw)
1158 /* Disable all interrupt types */
1159 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1160 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1161 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1162 I40EVF_WRITE_FLUSH(hw);
1167 i40evf_enable_irq0(struct i40e_hw *hw)
1169 /* Enable admin queue interrupt trigger */
1172 i40evf_disable_irq0(hw);
1173 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1174 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1175 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1176 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1178 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1179 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1180 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1181 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1183 I40EVF_WRITE_FLUSH(hw);
1187 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1190 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1193 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1194 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1195 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1196 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1197 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1198 reset == VIRTCHNL_VFR_COMPLETED)
1203 if (i >= MAX_RESET_WAIT_CNT)
1206 vf->vf_reset = false;
1207 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1212 i40evf_reset_vf(struct rte_eth_dev *dev)
1215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1222 * After issuing vf reset command to pf, pf won't necessarily
1223 * reset vf, it depends on what state it exactly is. If it's not
1224 * initialized yet, it won't have vf reset since it's in a certain
1225 * state. If not, it will try to reset. Even vf is reset, pf will
1226 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1227 * it to ACTIVE. In this duration, vf may not catch the moment that
1228 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1232 ret = i40evf_check_vf_reset_done(dev);
1234 PMD_INIT_LOG(ERR, "VF is still resetting");
1242 i40evf_init_vf(struct rte_eth_dev *dev)
1245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1248 i40e_calc_itr_interval(0, 0);
1250 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1251 vf->dev_data = dev->data;
1252 err = i40e_set_mac_type(hw);
1254 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1258 err = i40evf_check_vf_reset_done(dev);
1262 i40e_init_adminq_parameter(hw);
1263 err = i40e_init_adminq(hw);
1265 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1269 /* Reset VF and wait until it's complete */
1270 if (i40evf_reset_vf(dev)) {
1271 PMD_INIT_LOG(ERR, "reset NIC failed");
1275 /* VF reset, shutdown admin queue and initialize again */
1276 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1277 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1281 i40e_init_adminq_parameter(hw);
1282 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1283 PMD_INIT_LOG(ERR, "init_adminq failed");
1287 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1289 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1292 if (i40evf_check_api_version(dev) != 0) {
1293 PMD_INIT_LOG(ERR, "check_api version failed");
1296 bufsz = sizeof(struct virtchnl_vf_resource) +
1297 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1298 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1300 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1304 if (i40evf_get_vf_resource(dev) != 0) {
1305 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1309 /* got VF config message back from PF, now we can parse it */
1310 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1311 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1312 vf->vsi_res = &vf->vf_res->vsi_res[i];
1316 PMD_INIT_LOG(ERR, "no LAN VSI found");
1320 if (hw->mac.type == I40E_MAC_X722_VF)
1321 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1322 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1324 switch (vf->vsi_res->vsi_type) {
1325 case VIRTCHNL_VSI_SRIOV:
1326 vf->vsi.type = I40E_VSI_SRIOV;
1329 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1332 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1333 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1335 /* Store the MAC address configured by host, or generate random one */
1336 if (!rte_is_valid_assigned_ether_addr(
1337 (struct rte_ether_addr *)hw->mac.addr))
1338 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1340 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1341 (I40E_ITR_INDEX_DEFAULT <<
1342 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1344 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1345 I40EVF_WRITE_FLUSH(hw);
1350 rte_free(vf->vf_res);
1353 rte_free(vf->aq_resp);
1355 i40e_shutdown_adminq(hw); /* ignore error */
1361 i40evf_uninit_vf(struct rte_eth_dev *dev)
1363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1365 PMD_INIT_FUNC_TRACE();
1367 if (hw->adapter_closed == 0)
1368 i40evf_dev_close(dev);
1374 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1375 __rte_unused uint16_t msglen)
1377 struct virtchnl_pf_event *pf_msg =
1378 (struct virtchnl_pf_event *)msg;
1379 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1381 switch (pf_msg->event) {
1382 case VIRTCHNL_EVENT_RESET_IMPENDING:
1383 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1384 _rte_eth_dev_callback_process(dev,
1385 RTE_ETH_EVENT_INTR_RESET, NULL);
1387 case VIRTCHNL_EVENT_LINK_CHANGE:
1388 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1389 vf->link_up = pf_msg->event_data.link_event.link_status;
1390 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1391 i40evf_dev_link_update(dev, 0);
1392 _rte_eth_dev_callback_process(dev,
1393 RTE_ETH_EVENT_INTR_LSC, NULL);
1395 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1396 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1399 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1405 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1407 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1409 struct i40e_arq_event_info info;
1410 uint16_t pending, aq_opc;
1411 enum virtchnl_ops msg_opc;
1412 enum i40e_status_code msg_ret;
1415 info.buf_len = I40E_AQ_BUF_SZ;
1417 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1420 info.msg_buf = vf->aq_resp;
1424 ret = i40e_clean_arq_element(hw, &info, &pending);
1426 if (ret != I40E_SUCCESS) {
1427 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1431 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1432 /* For the message sent from pf to vf, opcode is stored in
1433 * cookie_high of struct i40e_aq_desc, while return error code
1434 * are stored in cookie_low, Which is done by
1435 * i40e_aq_send_msg_to_vf in PF driver.*/
1436 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1437 info.desc.cookie_high);
1438 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1439 info.desc.cookie_low);
1441 case i40e_aqc_opc_send_msg_to_vf:
1442 if (msg_opc == VIRTCHNL_OP_EVENT)
1444 i40evf_handle_pf_event(dev, info.msg_buf,
1447 /* read message and it's expected one */
1448 if (msg_opc == vf->pend_cmd) {
1449 vf->cmd_retval = msg_ret;
1450 /* prevent compiler reordering */
1451 rte_compiler_barrier();
1454 PMD_DRV_LOG(ERR, "command mismatch,"
1455 "expect %u, get %u",
1456 vf->pend_cmd, msg_opc);
1457 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1458 " opcode = %d", msg_opc);
1462 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1470 * Interrupt handler triggered by NIC for handling
1471 * specific interrupt. Only adminq interrupt is processed in VF.
1474 * Pointer to interrupt handle.
1476 * The address of parameter (struct rte_eth_dev *) regsitered before.
1482 i40evf_dev_alarm_handler(void *param)
1484 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1485 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488 i40evf_disable_irq0(hw);
1490 /* read out interrupt causes */
1491 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1493 /* No interrupt event indicated */
1494 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1497 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1498 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1499 i40evf_handle_aq_msg(dev);
1502 /* Link Status Change interrupt */
1503 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1504 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1508 i40evf_enable_irq0(hw);
1509 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1510 i40evf_dev_alarm_handler, dev);
1514 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1517 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1520 PMD_INIT_FUNC_TRACE();
1522 /* assign ops func pointer */
1523 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1524 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1525 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1528 * For secondary processes, we don't initialise any further as primary
1529 * has already done this work.
1531 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1532 i40e_set_rx_function(eth_dev);
1533 i40e_set_tx_function(eth_dev);
1536 i40e_set_default_ptype_table(eth_dev);
1537 rte_eth_copy_pci_info(eth_dev, pci_dev);
1539 hw->vendor_id = pci_dev->id.vendor_id;
1540 hw->device_id = pci_dev->id.device_id;
1541 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1542 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1543 hw->bus.device = pci_dev->addr.devid;
1544 hw->bus.func = pci_dev->addr.function;
1545 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1546 hw->adapter_stopped = 1;
1547 hw->adapter_closed = 0;
1549 /* Pass the information to the rte_eth_dev_close() that it should also
1550 * release the private port resources.
1552 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1554 if(i40evf_init_vf(eth_dev) != 0) {
1555 PMD_INIT_LOG(ERR, "Init vf failed");
1559 i40e_set_default_pctype_table(eth_dev);
1560 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1561 i40evf_dev_alarm_handler, eth_dev);
1563 /* configure and enable device interrupt */
1564 i40evf_enable_irq0(hw);
1567 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1568 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1570 if (eth_dev->data->mac_addrs == NULL) {
1571 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1572 " store MAC addresses",
1573 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1576 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1577 ð_dev->data->mac_addrs[0]);
1583 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1585 PMD_INIT_FUNC_TRACE();
1587 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1590 if (i40evf_uninit_vf(eth_dev) != 0) {
1591 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1598 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1599 struct rte_pci_device *pci_dev)
1601 return rte_eth_dev_pci_generic_probe(pci_dev,
1602 sizeof(struct i40e_adapter), i40evf_dev_init);
1605 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1607 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1611 * virtual function driver struct
1613 static struct rte_pci_driver rte_i40evf_pmd = {
1614 .id_table = pci_id_i40evf_map,
1615 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1616 .probe = eth_i40evf_pci_probe,
1617 .remove = eth_i40evf_pci_remove,
1620 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1621 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1622 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1625 i40evf_dev_configure(struct rte_eth_dev *dev)
1627 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1628 struct i40e_adapter *ad =
1629 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1630 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1631 dev->data->nb_tx_queues);
1633 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1634 * allocation or vector Rx preconditions we will reset it.
1636 ad->rx_bulk_alloc_allowed = true;
1637 ad->rx_vec_allowed = true;
1638 ad->tx_simple_allowed = true;
1639 ad->tx_vec_allowed = true;
1641 dev->data->dev_conf.intr_conf.lsc =
1642 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);
1644 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1648 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1650 "For secondary processes, change queue pairs is not supported!");
1654 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 if (!hw->adapter_stopped) {
1656 PMD_DRV_LOG(ERR, "Device must be stopped first!");
1660 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1661 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1662 ret = i40evf_request_queues(dev, num_queue_pairs);
1666 ret = i40evf_dev_reset(dev);
1671 return i40evf_init_vlan(dev);
1675 i40evf_init_vlan(struct rte_eth_dev *dev)
1677 /* Apply vlan offload setting */
1678 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1684 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1686 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1687 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1689 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1692 /* Vlan stripping setting */
1693 if (mask & ETH_VLAN_STRIP_MASK) {
1694 /* Enable or disable VLAN stripping */
1695 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1696 i40evf_enable_vlan_strip(dev);
1698 i40evf_disable_vlan_strip(dev);
1705 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1707 struct i40e_rx_queue *rxq;
1709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1711 PMD_INIT_FUNC_TRACE();
1713 rxq = dev->data->rx_queues[rx_queue_id];
1715 err = i40e_alloc_rx_queue_mbufs(rxq);
1717 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1723 /* Init the RX tail register. */
1724 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1725 I40EVF_WRITE_FLUSH(hw);
1727 /* Ready to switch the queue on */
1728 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1730 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1734 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1740 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1742 struct i40e_rx_queue *rxq;
1745 rxq = dev->data->rx_queues[rx_queue_id];
1747 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1749 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1754 i40e_rx_queue_release_mbufs(rxq);
1755 i40e_reset_rx_queue(rxq);
1756 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1762 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1766 PMD_INIT_FUNC_TRACE();
1768 /* Ready to switch the queue on */
1769 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1771 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1775 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1781 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1783 struct i40e_tx_queue *txq;
1786 txq = dev->data->tx_queues[tx_queue_id];
1788 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1790 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1795 i40e_tx_queue_release_mbufs(txq);
1796 i40e_reset_tx_queue(txq);
1797 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1803 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1808 ret = i40evf_add_vlan(dev, vlan_id);
1810 ret = i40evf_del_vlan(dev,vlan_id);
1816 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1819 struct rte_eth_dev_data *dev_data = dev->data;
1820 struct rte_pktmbuf_pool_private *mbp_priv;
1821 uint16_t buf_size, len;
1823 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1824 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1825 I40EVF_WRITE_FLUSH(hw);
1827 /* Calculate the maximum packet length allowed */
1828 mbp_priv = rte_mempool_get_priv(rxq->mp);
1829 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1830 RTE_PKTMBUF_HEADROOM);
1831 rxq->hs_mode = i40e_header_split_none;
1832 rxq->rx_hdr_len = 0;
1833 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1834 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1835 rxq->max_pkt_len = RTE_MIN(len,
1836 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1839 * Check if the jumbo frame and maximum packet length are set correctly
1841 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1842 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1843 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1844 PMD_DRV_LOG(ERR, "maximum packet length must be "
1845 "larger than %u and smaller than %u, as jumbo "
1846 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1847 (uint32_t)I40E_FRAME_SIZE_MAX);
1848 return I40E_ERR_CONFIG;
1851 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1852 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1853 PMD_DRV_LOG(ERR, "maximum packet length must be "
1854 "larger than %u and smaller than %u, as jumbo "
1855 "frame is disabled",
1856 (uint32_t)RTE_ETHER_MIN_LEN,
1857 (uint32_t)RTE_ETHER_MAX_LEN);
1858 return I40E_ERR_CONFIG;
1862 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1863 rxq->max_pkt_len > buf_size)
1864 dev_data->scattered_rx = 1;
1870 i40evf_rx_init(struct rte_eth_dev *dev)
1872 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1874 int ret = I40E_SUCCESS;
1875 struct i40e_rx_queue **rxq =
1876 (struct i40e_rx_queue **)dev->data->rx_queues;
1878 i40evf_config_rss(vf);
1879 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1880 if (!rxq[i] || !rxq[i]->q_set)
1882 ret = i40evf_rxq_init(dev, rxq[i]);
1883 if (ret != I40E_SUCCESS)
1886 if (ret == I40E_SUCCESS)
1887 i40e_set_rx_function(dev);
1893 i40evf_tx_init(struct rte_eth_dev *dev)
1896 struct i40e_tx_queue **txq =
1897 (struct i40e_tx_queue **)dev->data->tx_queues;
1898 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900 for (i = 0; i < dev->data->nb_tx_queues; i++)
1901 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1903 i40e_set_tx_function(dev);
1907 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1911 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1913 if (!rte_intr_allow_others(intr_handle)) {
1915 I40E_VFINT_DYN_CTL01,
1916 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1917 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1918 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1919 I40EVF_WRITE_FLUSH(hw);
1923 I40EVF_WRITE_FLUSH(hw);
1927 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1929 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1931 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1933 if (!rte_intr_allow_others(intr_handle)) {
1934 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1935 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1936 I40EVF_WRITE_FLUSH(hw);
1940 I40EVF_WRITE_FLUSH(hw);
1944 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1947 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1948 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 i40e_calc_itr_interval(0, 0);
1953 msix_intr = intr_handle->intr_vec[queue_id];
1954 if (msix_intr == I40E_MISC_VEC_ID)
1955 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1956 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1957 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1958 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1960 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1963 I40E_VFINT_DYN_CTLN1(msix_intr -
1965 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1966 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1967 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1969 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1971 I40EVF_WRITE_FLUSH(hw);
1977 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1980 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984 msix_intr = intr_handle->intr_vec[queue_id];
1985 if (msix_intr == I40E_MISC_VEC_ID)
1986 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1989 I40E_VFINT_DYN_CTLN1(msix_intr -
1993 I40EVF_WRITE_FLUSH(hw);
1999 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2001 struct virtchnl_ether_addr_list *list;
2002 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2007 struct rte_ether_addr *addr;
2008 struct vf_cmd_info args;
2012 len = sizeof(struct virtchnl_ether_addr_list);
2013 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2014 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
2016 len += sizeof(struct virtchnl_ether_addr);
2017 if (len >= I40E_AQ_BUF_SZ) {
2023 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2025 PMD_DRV_LOG(ERR, "fail to allocate memory");
2029 for (i = begin; i < next_begin; i++) {
2030 addr = &dev->data->mac_addrs[i];
2031 if (rte_is_zero_ether_addr(addr))
2033 rte_memcpy(list->list[j].addr, addr->addr_bytes,
2034 sizeof(addr->addr_bytes));
2035 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2036 addr->addr_bytes[0], addr->addr_bytes[1],
2037 addr->addr_bytes[2], addr->addr_bytes[3],
2038 addr->addr_bytes[4], addr->addr_bytes[5]);
2041 list->vsi_id = vf->vsi_res->vsi_id;
2042 list->num_elements = j;
2043 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2044 VIRTCHNL_OP_DEL_ETH_ADDR;
2045 args.in_args = (uint8_t *)list;
2046 args.in_args_size = len;
2047 args.out_buffer = vf->aq_resp;
2048 args.out_size = I40E_AQ_BUF_SZ;
2049 err = i40evf_execute_vf_cmd(dev, &args);
2051 PMD_DRV_LOG(ERR, "fail to execute command %s",
2052 add ? "OP_ADD_ETHER_ADDRESS" :
2053 "OP_DEL_ETHER_ADDRESS");
2062 } while (begin < I40E_NUM_MACADDR_MAX);
2066 i40evf_dev_start(struct rte_eth_dev *dev)
2068 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2069 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2071 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2072 uint32_t intr_vector = 0;
2074 PMD_INIT_FUNC_TRACE();
2076 hw->adapter_stopped = 0;
2078 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2079 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2080 dev->data->nb_tx_queues);
2082 /* check and configure queue intr-vector mapping */
2083 if (rte_intr_cap_multiple(intr_handle) &&
2084 dev->data->dev_conf.intr_conf.rxq) {
2085 intr_vector = dev->data->nb_rx_queues;
2086 if (rte_intr_efd_enable(intr_handle, intr_vector))
2090 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2091 intr_handle->intr_vec =
2092 rte_zmalloc("intr_vec",
2093 dev->data->nb_rx_queues * sizeof(int), 0);
2094 if (!intr_handle->intr_vec) {
2095 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2096 " intr_vec", dev->data->nb_rx_queues);
2101 if (i40evf_rx_init(dev) != 0){
2102 PMD_DRV_LOG(ERR, "failed to do RX init");
2106 i40evf_tx_init(dev);
2108 if (i40evf_configure_vsi_queues(dev) != 0) {
2109 PMD_DRV_LOG(ERR, "configure queues failed");
2112 if (i40evf_config_irq_map(dev)) {
2113 PMD_DRV_LOG(ERR, "config_irq_map failed");
2117 /* Set all mac addrs */
2118 i40evf_add_del_all_mac_addr(dev, TRUE);
2119 /* Set all multicast addresses */
2120 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2123 if (i40evf_start_queues(dev) != 0) {
2124 PMD_DRV_LOG(ERR, "enable queues failed");
2128 /* only enable interrupt in rx interrupt mode */
2129 if (dev->data->dev_conf.intr_conf.rxq != 0)
2130 rte_intr_enable(intr_handle);
2132 i40evf_enable_queues_intr(dev);
2137 i40evf_add_del_all_mac_addr(dev, FALSE);
2138 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2145 i40evf_dev_stop(struct rte_eth_dev *dev)
2147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2148 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2149 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2152 PMD_INIT_FUNC_TRACE();
2154 if (dev->data->dev_conf.intr_conf.rxq != 0)
2155 rte_intr_disable(intr_handle);
2157 if (hw->adapter_stopped == 1)
2159 i40evf_stop_queues(dev);
2160 i40evf_disable_queues_intr(dev);
2161 i40e_dev_clear_queues(dev);
2163 /* Clean datapath event and queue/vec mapping */
2164 rte_intr_efd_disable(intr_handle);
2165 if (intr_handle->intr_vec) {
2166 rte_free(intr_handle->intr_vec);
2167 intr_handle->intr_vec = NULL;
2169 /* remove all mac addrs */
2170 i40evf_add_del_all_mac_addr(dev, FALSE);
2171 /* remove all multicast addresses */
2172 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2174 hw->adapter_stopped = 1;
2179 i40evf_dev_link_update(struct rte_eth_dev *dev,
2180 __rte_unused int wait_to_complete)
2182 struct rte_eth_link new_link;
2183 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2185 * DPDK pf host provide interfacet to acquire link status
2186 * while Linux driver does not
2189 memset(&new_link, 0, sizeof(new_link));
2190 /* Linux driver PF host */
2191 switch (vf->link_speed) {
2192 case I40E_LINK_SPEED_100MB:
2193 new_link.link_speed = ETH_SPEED_NUM_100M;
2195 case I40E_LINK_SPEED_1GB:
2196 new_link.link_speed = ETH_SPEED_NUM_1G;
2198 case I40E_LINK_SPEED_10GB:
2199 new_link.link_speed = ETH_SPEED_NUM_10G;
2201 case I40E_LINK_SPEED_20GB:
2202 new_link.link_speed = ETH_SPEED_NUM_20G;
2204 case I40E_LINK_SPEED_25GB:
2205 new_link.link_speed = ETH_SPEED_NUM_25G;
2207 case I40E_LINK_SPEED_40GB:
2208 new_link.link_speed = ETH_SPEED_NUM_40G;
2212 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2214 new_link.link_speed = ETH_SPEED_NUM_NONE;
2217 /* full duplex only */
2218 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219 new_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
2220 new_link.link_autoneg =
2221 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2223 return rte_eth_linkstatus_set(dev, &new_link);
2227 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2231 return i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);
2235 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2237 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2239 return i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);
2243 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2245 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2247 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);
2251 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2253 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2255 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);
2259 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2261 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2263 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2264 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2265 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2266 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2267 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2268 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2269 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2270 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2271 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2272 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2273 dev_info->rx_queue_offload_capa = 0;
2274 dev_info->rx_offload_capa =
2275 DEV_RX_OFFLOAD_VLAN_STRIP |
2276 DEV_RX_OFFLOAD_QINQ_STRIP |
2277 DEV_RX_OFFLOAD_IPV4_CKSUM |
2278 DEV_RX_OFFLOAD_UDP_CKSUM |
2279 DEV_RX_OFFLOAD_TCP_CKSUM |
2280 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2281 DEV_RX_OFFLOAD_SCATTER |
2282 DEV_RX_OFFLOAD_JUMBO_FRAME |
2283 DEV_RX_OFFLOAD_VLAN_FILTER;
2285 dev_info->tx_queue_offload_capa = 0;
2286 dev_info->tx_offload_capa =
2287 DEV_TX_OFFLOAD_VLAN_INSERT |
2288 DEV_TX_OFFLOAD_QINQ_INSERT |
2289 DEV_TX_OFFLOAD_IPV4_CKSUM |
2290 DEV_TX_OFFLOAD_UDP_CKSUM |
2291 DEV_TX_OFFLOAD_TCP_CKSUM |
2292 DEV_TX_OFFLOAD_SCTP_CKSUM |
2293 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2294 DEV_TX_OFFLOAD_TCP_TSO |
2295 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2296 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2297 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2298 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2299 DEV_TX_OFFLOAD_MULTI_SEGS;
2301 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2303 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2304 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2305 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2307 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2312 dev_info->default_txconf = (struct rte_eth_txconf) {
2314 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2315 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2316 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2318 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2319 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2323 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2324 .nb_max = I40E_MAX_RING_DESC,
2325 .nb_min = I40E_MIN_RING_DESC,
2326 .nb_align = I40E_ALIGN_RING_DESC,
2329 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2330 .nb_max = I40E_MAX_RING_DESC,
2331 .nb_min = I40E_MIN_RING_DESC,
2332 .nb_align = I40E_ALIGN_RING_DESC,
2339 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2342 struct i40e_eth_stats *pstats = NULL;
2343 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2344 struct i40e_vsi *vsi = &vf->vsi;
2346 ret = i40evf_query_stats(dev, &pstats);
2348 i40evf_update_stats(vsi, pstats);
2350 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2351 pstats->rx_broadcast;
2352 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2354 stats->imissed = pstats->rx_discards;
2355 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2356 stats->ibytes = pstats->rx_bytes;
2357 stats->obytes = pstats->tx_bytes;
2359 PMD_DRV_LOG(ERR, "Get statistics failed");
2365 i40evf_dev_close(struct rte_eth_dev *dev)
2367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2370 i40evf_dev_stop(dev);
2371 i40e_dev_free_queues(dev);
2373 * disable promiscuous mode before reset vf
2374 * it is a workaround solution when work with kernel driver
2375 * and it is not the normal way
2377 if (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)
2378 i40evf_config_promisc(dev, false, false);
2380 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2382 i40evf_reset_vf(dev);
2383 i40e_shutdown_adminq(hw);
2384 i40evf_disable_irq0(hw);
2386 dev->dev_ops = NULL;
2387 dev->rx_pkt_burst = NULL;
2388 dev->tx_pkt_burst = NULL;
2390 rte_free(vf->vf_res);
2392 rte_free(vf->aq_resp);
2395 hw->adapter_closed = 1;
2399 * Reset VF device only to re-initialize resources in PMD layer
2402 i40evf_dev_reset(struct rte_eth_dev *dev)
2406 ret = i40evf_dev_uninit(dev);
2410 ret = i40evf_dev_init(dev);
2416 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2418 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2419 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2425 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2426 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2429 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2433 uint32_t *lut_dw = (uint32_t *)lut;
2434 uint16_t i, lut_size_dw = lut_size / 4;
2436 for (i = 0; i < lut_size_dw; i++)
2437 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2444 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2453 vf = I40E_VSI_TO_VF(vsi);
2454 hw = I40E_VSI_TO_HW(vsi);
2456 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2457 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2460 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2464 uint32_t *lut_dw = (uint32_t *)lut;
2465 uint16_t i, lut_size_dw = lut_size / 4;
2467 for (i = 0; i < lut_size_dw; i++)
2468 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2469 I40EVF_WRITE_FLUSH(hw);
2476 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2477 struct rte_eth_rss_reta_entry64 *reta_conf,
2480 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2482 uint16_t i, idx, shift;
2485 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2486 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2487 "(%d) doesn't match the number of hardware can "
2488 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2492 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2494 PMD_DRV_LOG(ERR, "No memory can be allocated");
2497 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2500 for (i = 0; i < reta_size; i++) {
2501 idx = i / RTE_RETA_GROUP_SIZE;
2502 shift = i % RTE_RETA_GROUP_SIZE;
2503 if (reta_conf[idx].mask & (1ULL << shift))
2504 lut[i] = reta_conf[idx].reta[shift];
2506 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2515 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2516 struct rte_eth_rss_reta_entry64 *reta_conf,
2519 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2520 uint16_t i, idx, shift;
2524 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2525 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2526 "(%d) doesn't match the number of hardware can "
2527 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2531 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2533 PMD_DRV_LOG(ERR, "No memory can be allocated");
2537 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2540 for (i = 0; i < reta_size; i++) {
2541 idx = i / RTE_RETA_GROUP_SIZE;
2542 shift = i % RTE_RETA_GROUP_SIZE;
2543 if (reta_conf[idx].mask & (1ULL << shift))
2544 reta_conf[idx].reta[shift] = lut[i];
2554 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2556 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2557 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2560 if (!key || key_len == 0) {
2561 PMD_DRV_LOG(DEBUG, "No key to be configured");
2563 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2565 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2569 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2570 struct i40e_aqc_get_set_rss_key_data *key_dw =
2571 (struct i40e_aqc_get_set_rss_key_data *)key;
2573 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2575 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2578 uint32_t *hash_key = (uint32_t *)key;
2581 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2582 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2583 I40EVF_WRITE_FLUSH(hw);
2590 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2592 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2596 if (!key || !key_len)
2599 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2600 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2601 (struct i40e_aqc_get_set_rss_key_data *)key);
2603 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2607 uint32_t *key_dw = (uint32_t *)key;
2610 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2611 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2613 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2619 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2621 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2625 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2626 rss_conf->rss_key_len);
2630 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2631 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2632 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2633 I40EVF_WRITE_FLUSH(hw);
2639 i40evf_disable_rss(struct i40e_vf *vf)
2641 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2643 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2644 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2645 I40EVF_WRITE_FLUSH(hw);
2649 i40evf_config_rss(struct i40e_vf *vf)
2651 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2652 struct rte_eth_rss_conf rss_conf;
2653 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2654 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2659 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2660 i40evf_disable_rss(vf);
2661 PMD_DRV_LOG(DEBUG, "RSS not configured");
2665 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2666 /* Fill out the look up table */
2667 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2668 for (i = 0, j = 0; i < nb_q; i++, j++) {
2671 lut = (lut << 8) | j;
2673 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2676 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2678 PMD_DRV_LOG(ERR, "No memory can be allocated");
2682 for (i = 0; i < rss_lut_size; i++)
2683 lut_info[i] = i % vf->num_queue_pairs;
2685 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2692 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2693 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2694 i40evf_disable_rss(vf);
2695 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2699 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2700 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2701 /* Calculate the default hash key */
2702 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2703 rss_key_default[i] = (uint32_t)rte_rand();
2704 rss_conf.rss_key = (uint8_t *)rss_key_default;
2705 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2709 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2713 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2714 struct rte_eth_rss_conf *rss_conf)
2716 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2721 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2722 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2724 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2725 if (rss_hf != 0) /* Enable RSS */
2731 if (rss_hf == 0) /* Disable RSS */
2734 return i40evf_hw_rss_hash_set(vf, rss_conf);
2738 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2739 struct rte_eth_rss_conf *rss_conf)
2741 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2746 &rss_conf->rss_key_len);
2748 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2749 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2750 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2756 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2758 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2759 struct rte_eth_dev_data *dev_data = vf->dev_data;
2760 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2763 /* check if mtu is within the allowed range */
2764 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2767 /* mtu setting is forbidden if port is start */
2768 if (dev_data->dev_started) {
2769 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2774 if (frame_size > RTE_ETHER_MAX_LEN)
2775 dev_data->dev_conf.rxmode.offloads |=
2776 DEV_RX_OFFLOAD_JUMBO_FRAME;
2778 dev_data->dev_conf.rxmode.offloads &=
2779 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2780 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2786 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2787 struct rte_ether_addr *mac_addr)
2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2792 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2796 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2798 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2801 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2806 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2807 struct rte_ether_addr *mc_addrs,
2808 uint32_t mc_addrs_num, bool add)
2810 struct virtchnl_ether_addr_list *list;
2811 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2812 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2813 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2816 struct vf_cmd_info args;
2818 if (mc_addrs == NULL || mc_addrs_num == 0)
2821 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2824 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2825 list->vsi_id = vf->vsi_res->vsi_id;
2826 list->num_elements = mc_addrs_num;
2828 for (i = 0; i < mc_addrs_num; i++) {
2829 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2830 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2831 mc_addrs[i].addr_bytes[0],
2832 mc_addrs[i].addr_bytes[1],
2833 mc_addrs[i].addr_bytes[2],
2834 mc_addrs[i].addr_bytes[3],
2835 mc_addrs[i].addr_bytes[4],
2836 mc_addrs[i].addr_bytes[5]);
2840 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2841 sizeof(list->list[i].addr));
2844 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2845 args.in_args = cmd_buffer;
2846 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2847 i * sizeof(struct virtchnl_ether_addr);
2848 args.out_buffer = vf->aq_resp;
2849 args.out_size = I40E_AQ_BUF_SZ;
2850 err = i40evf_execute_vf_cmd(dev, &args);
2852 PMD_DRV_LOG(ERR, "fail to execute command %s",
2853 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2861 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2862 struct rte_ether_addr *mc_addrs,
2863 uint32_t mc_addrs_num)
2865 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2868 /* flush previous addresses */
2869 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2874 vf->mc_addrs_num = 0;
2877 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2882 vf->mc_addrs_num = mc_addrs_num;
2883 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2889 is_i40evf_supported(struct rte_eth_dev *dev)
2891 return is_device_supported(dev, &rte_i40evf_pmd);