1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set,
141 uint32_t nb_mc_addr);
143 /* Default hash key buffer for RSS */
144 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
146 struct rte_i40evf_xstats_name_off {
147 char name[RTE_ETH_XSTATS_NAME_SIZE];
151 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
152 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
153 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
154 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
155 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
156 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
157 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
158 rx_unknown_protocol)},
159 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
160 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
161 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
162 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
163 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
164 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
167 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
168 sizeof(rte_i40evf_stats_strings[0]))
170 static const struct eth_dev_ops i40evf_eth_dev_ops = {
171 .dev_configure = i40evf_dev_configure,
172 .dev_start = i40evf_dev_start,
173 .dev_stop = i40evf_dev_stop,
174 .promiscuous_enable = i40evf_dev_promiscuous_enable,
175 .promiscuous_disable = i40evf_dev_promiscuous_disable,
176 .allmulticast_enable = i40evf_dev_allmulticast_enable,
177 .allmulticast_disable = i40evf_dev_allmulticast_disable,
178 .link_update = i40evf_dev_link_update,
179 .stats_get = i40evf_dev_stats_get,
180 .stats_reset = i40evf_dev_xstats_reset,
181 .xstats_get = i40evf_dev_xstats_get,
182 .xstats_get_names = i40evf_dev_xstats_get_names,
183 .xstats_reset = i40evf_dev_xstats_reset,
184 .dev_close = i40evf_dev_close,
185 .dev_reset = i40evf_dev_reset,
186 .dev_infos_get = i40evf_dev_info_get,
187 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
188 .vlan_filter_set = i40evf_vlan_filter_set,
189 .vlan_offload_set = i40evf_vlan_offload_set,
190 .rx_queue_start = i40evf_dev_rx_queue_start,
191 .rx_queue_stop = i40evf_dev_rx_queue_stop,
192 .tx_queue_start = i40evf_dev_tx_queue_start,
193 .tx_queue_stop = i40evf_dev_tx_queue_stop,
194 .rx_queue_setup = i40e_dev_rx_queue_setup,
195 .rx_queue_release = i40e_dev_rx_queue_release,
196 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
197 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
198 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
199 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
200 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
201 .tx_queue_setup = i40e_dev_tx_queue_setup,
202 .tx_queue_release = i40e_dev_tx_queue_release,
203 .rx_queue_count = i40e_dev_rx_queue_count,
204 .rxq_info_get = i40e_rxq_info_get,
205 .txq_info_get = i40e_txq_info_get,
206 .mac_addr_add = i40evf_add_mac_addr,
207 .mac_addr_remove = i40evf_del_mac_addr,
208 .set_mc_addr_list = i40evf_set_mc_addr_list,
209 .reta_update = i40evf_dev_rss_reta_update,
210 .reta_query = i40evf_dev_rss_reta_query,
211 .rss_hash_update = i40evf_dev_rss_hash_update,
212 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
213 .mtu_set = i40evf_dev_mtu_set,
214 .mac_addr_set = i40evf_set_default_mac_addr,
218 * Read data in admin queue to get msg from pf driver
220 static enum i40evf_aq_result
221 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
223 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
224 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
225 struct i40e_arq_event_info event;
226 enum virtchnl_ops opcode;
227 enum i40e_status_code retval;
229 enum i40evf_aq_result result = I40EVF_MSG_NON;
231 event.buf_len = data->buf_len;
232 event.msg_buf = data->msg;
233 ret = i40e_clean_arq_element(hw, &event, NULL);
234 /* Can't read any msg from adminQ */
236 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
237 result = I40EVF_MSG_ERR;
241 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
242 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
244 if (opcode == VIRTCHNL_OP_EVENT) {
245 struct virtchnl_pf_event *vpe =
246 (struct virtchnl_pf_event *)event.msg_buf;
248 result = I40EVF_MSG_SYS;
249 switch (vpe->event) {
250 case VIRTCHNL_EVENT_LINK_CHANGE:
252 vpe->event_data.link_event.link_status;
254 vpe->event_data.link_event.link_speed;
255 vf->pend_msg |= PFMSG_LINK_CHANGE;
256 PMD_DRV_LOG(INFO, "Link status update:%s",
257 vf->link_up ? "up" : "down");
259 case VIRTCHNL_EVENT_RESET_IMPENDING:
261 vf->pend_msg |= PFMSG_RESET_IMPENDING;
262 PMD_DRV_LOG(INFO, "vf is reseting");
264 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
265 vf->dev_closed = true;
266 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
267 PMD_DRV_LOG(INFO, "PF driver closed");
270 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
271 __func__, vpe->event);
274 /* async reply msg on command issued by vf previously */
275 result = I40EVF_MSG_CMD;
276 /* Actual data length read from PF */
277 data->msg_len = event.msg_len;
280 data->result = retval;
287 * clear current command. Only call in case execute
288 * _atomic_set_cmd successfully.
291 _clear_cmd(struct i40e_vf *vf)
294 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
298 * Check there is pending cmd in execution. If none, set new command.
301 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
303 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
304 VIRTCHNL_OP_UNKNOWN, ops);
307 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
312 #define MAX_TRY_TIMES 200
313 #define ASQ_DELAY_MS 10
316 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
320 struct i40evf_arq_msg_info info;
321 enum i40evf_aq_result ret;
324 if (_atomic_set_cmd(vf, args->ops))
327 info.msg = args->out_buffer;
328 info.buf_len = args->out_size;
329 info.ops = VIRTCHNL_OP_UNKNOWN;
330 info.result = I40E_SUCCESS;
332 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
333 args->in_args, args->in_args_size, NULL);
335 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
341 case VIRTCHNL_OP_RESET_VF:
342 /*no need to process in this function */
345 case VIRTCHNL_OP_VERSION:
346 case VIRTCHNL_OP_GET_VF_RESOURCES:
347 /* for init adminq commands, need to poll the response */
350 ret = i40evf_read_pfmsg(dev, &info);
351 vf->cmd_retval = info.result;
352 if (ret == I40EVF_MSG_CMD) {
355 } else if (ret == I40EVF_MSG_ERR)
357 rte_delay_ms(ASQ_DELAY_MS);
358 /* If don't read msg or read sys event, continue */
359 } while (i++ < MAX_TRY_TIMES);
364 /* for other adminq in running time, waiting the cmd done flag */
367 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
371 rte_delay_ms(ASQ_DELAY_MS);
372 /* If don't read msg or read sys event, continue */
373 } while (i++ < MAX_TRY_TIMES);
374 /* If there's no response is received, clear command */
375 if (i >= MAX_TRY_TIMES) {
376 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
382 return err | vf->cmd_retval;
386 * Check API version with sync wait until version read or fail from admin queue
389 i40evf_check_api_version(struct rte_eth_dev *dev)
391 struct virtchnl_version_info version, *pver;
393 struct vf_cmd_info args;
394 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
396 version.major = VIRTCHNL_VERSION_MAJOR;
397 version.minor = VIRTCHNL_VERSION_MINOR;
399 args.ops = VIRTCHNL_OP_VERSION;
400 args.in_args = (uint8_t *)&version;
401 args.in_args_size = sizeof(version);
402 args.out_buffer = vf->aq_resp;
403 args.out_size = I40E_AQ_BUF_SZ;
405 err = i40evf_execute_vf_cmd(dev, &args);
407 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
411 pver = (struct virtchnl_version_info *)args.out_buffer;
412 vf->version_major = pver->major;
413 vf->version_minor = pver->minor;
414 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
415 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
416 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
418 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
419 vf->version_major, vf->version_minor,
420 VIRTCHNL_VERSION_MAJOR,
421 VIRTCHNL_VERSION_MINOR);
429 i40evf_get_vf_resource(struct rte_eth_dev *dev)
431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
432 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
434 struct vf_cmd_info args;
437 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
438 args.out_buffer = vf->aq_resp;
439 args.out_size = I40E_AQ_BUF_SZ;
441 caps = VIRTCHNL_VF_OFFLOAD_L2 |
442 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
443 VIRTCHNL_VF_OFFLOAD_RSS_REG |
444 VIRTCHNL_VF_OFFLOAD_VLAN |
445 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
446 args.in_args = (uint8_t *)∩︀
447 args.in_args_size = sizeof(caps);
450 args.in_args_size = 0;
452 err = i40evf_execute_vf_cmd(dev, &args);
455 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
459 len = sizeof(struct virtchnl_vf_resource) +
460 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
462 rte_memcpy(vf->vf_res, args.out_buffer,
463 RTE_MIN(args.out_size, len));
464 i40e_vf_parse_hw_config(hw, vf->vf_res);
470 i40evf_config_promisc(struct rte_eth_dev *dev,
472 bool enable_multicast)
474 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
476 struct vf_cmd_info args;
477 struct virtchnl_promisc_info promisc;
480 promisc.vsi_id = vf->vsi_res->vsi_id;
483 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
485 if (enable_multicast)
486 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
488 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
489 args.in_args = (uint8_t *)&promisc;
490 args.in_args_size = sizeof(promisc);
491 args.out_buffer = vf->aq_resp;
492 args.out_size = I40E_AQ_BUF_SZ;
494 err = i40evf_execute_vf_cmd(dev, &args);
497 PMD_DRV_LOG(ERR, "fail to execute command "
498 "CONFIG_PROMISCUOUS_MODE");
503 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
505 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
506 struct vf_cmd_info args;
509 memset(&args, 0, sizeof(args));
510 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
512 args.in_args_size = 0;
513 args.out_buffer = vf->aq_resp;
514 args.out_size = I40E_AQ_BUF_SZ;
515 ret = i40evf_execute_vf_cmd(dev, &args);
517 PMD_DRV_LOG(ERR, "Failed to execute command of "
518 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
524 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
526 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
527 struct vf_cmd_info args;
530 memset(&args, 0, sizeof(args));
531 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
533 args.in_args_size = 0;
534 args.out_buffer = vf->aq_resp;
535 args.out_size = I40E_AQ_BUF_SZ;
536 ret = i40evf_execute_vf_cmd(dev, &args);
538 PMD_DRV_LOG(ERR, "Failed to execute command of "
539 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
545 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
549 struct i40e_tx_queue *txq)
551 txq_info->vsi_id = vsi_id;
552 txq_info->queue_id = queue_id;
553 if (queue_id < nb_txq) {
554 txq_info->ring_len = txq->nb_tx_desc;
555 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
560 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
564 uint32_t max_pkt_size,
565 struct i40e_rx_queue *rxq)
567 rxq_info->vsi_id = vsi_id;
568 rxq_info->queue_id = queue_id;
569 rxq_info->max_pkt_size = max_pkt_size;
570 if (queue_id < nb_rxq) {
571 rxq_info->ring_len = rxq->nb_rx_desc;
572 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
573 rxq_info->databuffer_size =
574 (rte_pktmbuf_data_room_size(rxq->mp) -
575 RTE_PKTMBUF_HEADROOM);
580 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
582 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
583 struct i40e_rx_queue **rxq =
584 (struct i40e_rx_queue **)dev->data->rx_queues;
585 struct i40e_tx_queue **txq =
586 (struct i40e_tx_queue **)dev->data->tx_queues;
587 struct virtchnl_vsi_queue_config_info *vc_vqci;
588 struct virtchnl_queue_pair_info *vc_qpi;
589 struct vf_cmd_info args;
590 uint16_t i, nb_qp = vf->num_queue_pairs;
591 const uint32_t size =
592 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
596 memset(buff, 0, sizeof(buff));
597 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
598 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
599 vc_vqci->num_queue_pairs = nb_qp;
601 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
602 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
603 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
604 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
605 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
606 vf->max_pkt_len, rxq[i]);
608 memset(&args, 0, sizeof(args));
609 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
610 args.in_args = (uint8_t *)vc_vqci;
611 args.in_args_size = size;
612 args.out_buffer = vf->aq_resp;
613 args.out_size = I40E_AQ_BUF_SZ;
614 ret = i40evf_execute_vf_cmd(dev, &args);
616 PMD_DRV_LOG(ERR, "Failed to execute command of "
617 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
623 i40evf_config_irq_map(struct rte_eth_dev *dev)
625 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
626 struct vf_cmd_info args;
627 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
628 sizeof(struct virtchnl_vector_map)];
629 struct virtchnl_irq_map_info *map_info;
630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
631 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
635 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
636 rte_intr_allow_others(intr_handle))
637 vector_id = I40E_RX_VEC_START;
639 vector_id = I40E_MISC_VEC_ID;
641 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
642 map_info->num_vectors = 1;
643 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
644 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
645 /* Alway use default dynamic MSIX interrupt */
646 map_info->vecmap[0].vector_id = vector_id;
647 /* Don't map any tx queue */
648 map_info->vecmap[0].txq_map = 0;
649 map_info->vecmap[0].rxq_map = 0;
650 for (i = 0; i < dev->data->nb_rx_queues; i++) {
651 map_info->vecmap[0].rxq_map |= 1 << i;
652 if (rte_intr_dp_is_en(intr_handle))
653 intr_handle->intr_vec[i] = vector_id;
656 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
657 args.in_args = (u8 *)cmd_buffer;
658 args.in_args_size = sizeof(cmd_buffer);
659 args.out_buffer = vf->aq_resp;
660 args.out_size = I40E_AQ_BUF_SZ;
661 err = i40evf_execute_vf_cmd(dev, &args);
663 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
669 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
672 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
673 struct virtchnl_queue_select queue_select;
675 struct vf_cmd_info args;
676 memset(&queue_select, 0, sizeof(queue_select));
677 queue_select.vsi_id = vf->vsi_res->vsi_id;
680 queue_select.rx_queues |= 1 << qid;
682 queue_select.tx_queues |= 1 << qid;
685 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
687 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
688 args.in_args = (u8 *)&queue_select;
689 args.in_args_size = sizeof(queue_select);
690 args.out_buffer = vf->aq_resp;
691 args.out_size = I40E_AQ_BUF_SZ;
692 err = i40evf_execute_vf_cmd(dev, &args);
694 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
695 isrx ? "RX" : "TX", qid, on ? "on" : "off");
701 i40evf_start_queues(struct rte_eth_dev *dev)
703 struct rte_eth_dev_data *dev_data = dev->data;
705 struct i40e_rx_queue *rxq;
706 struct i40e_tx_queue *txq;
708 for (i = 0; i < dev->data->nb_rx_queues; i++) {
709 rxq = dev_data->rx_queues[i];
710 if (rxq->rx_deferred_start)
712 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
713 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
718 for (i = 0; i < dev->data->nb_tx_queues; i++) {
719 txq = dev_data->tx_queues[i];
720 if (txq->tx_deferred_start)
722 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
723 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
732 i40evf_stop_queues(struct rte_eth_dev *dev)
736 /* Stop TX queues first */
737 for (i = 0; i < dev->data->nb_tx_queues; i++) {
738 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
739 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
744 /* Then stop RX queues */
745 for (i = 0; i < dev->data->nb_rx_queues; i++) {
746 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
747 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
756 i40evf_add_mac_addr(struct rte_eth_dev *dev,
757 struct ether_addr *addr,
758 __rte_unused uint32_t index,
759 __rte_unused uint32_t pool)
761 struct virtchnl_ether_addr_list *list;
762 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
763 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
764 sizeof(struct virtchnl_ether_addr)];
766 struct vf_cmd_info args;
768 if (is_zero_ether_addr(addr)) {
769 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
770 addr->addr_bytes[0], addr->addr_bytes[1],
771 addr->addr_bytes[2], addr->addr_bytes[3],
772 addr->addr_bytes[4], addr->addr_bytes[5]);
773 return I40E_ERR_INVALID_MAC_ADDR;
776 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
777 list->vsi_id = vf->vsi_res->vsi_id;
778 list->num_elements = 1;
779 rte_memcpy(list->list[0].addr, addr->addr_bytes,
780 sizeof(addr->addr_bytes));
782 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
783 args.in_args = cmd_buffer;
784 args.in_args_size = sizeof(cmd_buffer);
785 args.out_buffer = vf->aq_resp;
786 args.out_size = I40E_AQ_BUF_SZ;
787 err = i40evf_execute_vf_cmd(dev, &args);
789 PMD_DRV_LOG(ERR, "fail to execute command "
790 "OP_ADD_ETHER_ADDRESS");
798 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
799 struct ether_addr *addr)
801 struct virtchnl_ether_addr_list *list;
802 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
803 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
804 sizeof(struct virtchnl_ether_addr)];
806 struct vf_cmd_info args;
808 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
809 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
810 addr->addr_bytes[0], addr->addr_bytes[1],
811 addr->addr_bytes[2], addr->addr_bytes[3],
812 addr->addr_bytes[4], addr->addr_bytes[5]);
816 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
817 list->vsi_id = vf->vsi_res->vsi_id;
818 list->num_elements = 1;
819 rte_memcpy(list->list[0].addr, addr->addr_bytes,
820 sizeof(addr->addr_bytes));
822 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
823 args.in_args = cmd_buffer;
824 args.in_args_size = sizeof(cmd_buffer);
825 args.out_buffer = vf->aq_resp;
826 args.out_size = I40E_AQ_BUF_SZ;
827 err = i40evf_execute_vf_cmd(dev, &args);
829 PMD_DRV_LOG(ERR, "fail to execute command "
830 "OP_DEL_ETHER_ADDRESS");
837 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
839 struct rte_eth_dev_data *data = dev->data;
840 struct ether_addr *addr;
842 addr = &data->mac_addrs[index];
844 i40evf_del_mac_addr_by_addr(dev, addr);
848 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
850 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
851 struct virtchnl_queue_select q_stats;
853 struct vf_cmd_info args;
855 memset(&q_stats, 0, sizeof(q_stats));
856 q_stats.vsi_id = vf->vsi_res->vsi_id;
857 args.ops = VIRTCHNL_OP_GET_STATS;
858 args.in_args = (u8 *)&q_stats;
859 args.in_args_size = sizeof(q_stats);
860 args.out_buffer = vf->aq_resp;
861 args.out_size = I40E_AQ_BUF_SZ;
863 err = i40evf_execute_vf_cmd(dev, &args);
865 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
869 *pstats = (struct i40e_eth_stats *)args.out_buffer;
874 i40evf_stat_update_48(uint64_t *offset,
877 if (*stat >= *offset)
878 *stat = *stat - *offset;
880 *stat = (uint64_t)((*stat +
881 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
883 *stat &= I40E_48_BIT_MASK;
887 i40evf_stat_update_32(uint64_t *offset,
890 if (*stat >= *offset)
891 *stat = (uint64_t)(*stat - *offset);
893 *stat = (uint64_t)((*stat +
894 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
898 i40evf_update_stats(struct i40e_vsi *vsi,
899 struct i40e_eth_stats *nes)
901 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
903 i40evf_stat_update_48(&oes->rx_bytes,
905 i40evf_stat_update_48(&oes->rx_unicast,
907 i40evf_stat_update_48(&oes->rx_multicast,
909 i40evf_stat_update_48(&oes->rx_broadcast,
911 i40evf_stat_update_32(&oes->rx_discards,
913 i40evf_stat_update_32(&oes->rx_unknown_protocol,
914 &nes->rx_unknown_protocol);
915 i40evf_stat_update_48(&oes->tx_bytes,
917 i40evf_stat_update_48(&oes->tx_unicast,
919 i40evf_stat_update_48(&oes->tx_multicast,
921 i40evf_stat_update_48(&oes->tx_broadcast,
923 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
924 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
928 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
931 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
932 struct i40e_eth_stats *pstats = NULL;
934 /* read stat values to clear hardware registers */
935 ret = i40evf_query_stats(dev, &pstats);
937 /* set stats offset base on current values */
939 vf->vsi.eth_stats_offset = *pstats;
942 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
943 struct rte_eth_xstat_name *xstats_names,
944 __rte_unused unsigned limit)
948 if (xstats_names != NULL)
949 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
950 snprintf(xstats_names[i].name,
951 sizeof(xstats_names[i].name),
952 "%s", rte_i40evf_stats_strings[i].name);
954 return I40EVF_NB_XSTATS;
957 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
958 struct rte_eth_xstat *xstats, unsigned n)
962 struct i40e_eth_stats *pstats = NULL;
963 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
964 struct i40e_vsi *vsi = &vf->vsi;
966 if (n < I40EVF_NB_XSTATS)
967 return I40EVF_NB_XSTATS;
969 ret = i40evf_query_stats(dev, &pstats);
976 i40evf_update_stats(vsi, pstats);
978 /* loop over xstats array and values from pstats */
979 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
981 xstats[i].value = *(uint64_t *)(((char *)pstats) +
982 rte_i40evf_stats_strings[i].offset);
985 return I40EVF_NB_XSTATS;
989 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
991 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
992 struct virtchnl_vlan_filter_list *vlan_list;
993 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
996 struct vf_cmd_info args;
998 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
999 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1000 vlan_list->num_elements = 1;
1001 vlan_list->vlan_id[0] = vlanid;
1003 args.ops = VIRTCHNL_OP_ADD_VLAN;
1004 args.in_args = (u8 *)&cmd_buffer;
1005 args.in_args_size = sizeof(cmd_buffer);
1006 args.out_buffer = vf->aq_resp;
1007 args.out_size = I40E_AQ_BUF_SZ;
1008 err = i40evf_execute_vf_cmd(dev, &args);
1010 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1016 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1018 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1019 struct virtchnl_vlan_filter_list *vlan_list;
1020 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1023 struct vf_cmd_info args;
1025 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1026 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1027 vlan_list->num_elements = 1;
1028 vlan_list->vlan_id[0] = vlanid;
1030 args.ops = VIRTCHNL_OP_DEL_VLAN;
1031 args.in_args = (u8 *)&cmd_buffer;
1032 args.in_args_size = sizeof(cmd_buffer);
1033 args.out_buffer = vf->aq_resp;
1034 args.out_size = I40E_AQ_BUF_SZ;
1035 err = i40evf_execute_vf_cmd(dev, &args);
1037 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1042 static const struct rte_pci_id pci_id_i40evf_map[] = {
1043 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1044 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1045 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1046 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1047 { .vendor_id = 0, /* sentinel */ },
1052 i40evf_disable_irq0(struct i40e_hw *hw)
1054 /* Disable all interrupt types */
1055 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1056 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1057 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1058 I40EVF_WRITE_FLUSH(hw);
1063 i40evf_enable_irq0(struct i40e_hw *hw)
1065 /* Enable admin queue interrupt trigger */
1068 i40evf_disable_irq0(hw);
1069 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1070 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1071 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1072 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1074 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1075 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1076 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1077 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1079 I40EVF_WRITE_FLUSH(hw);
1083 i40evf_check_vf_reset_done(struct i40e_hw *hw)
1087 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1088 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1089 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1090 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1091 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1092 reset == VIRTCHNL_VFR_COMPLETED)
1097 if (i >= MAX_RESET_WAIT_CNT)
1103 i40evf_reset_vf(struct i40e_hw *hw)
1107 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1108 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1112 * After issuing vf reset command to pf, pf won't necessarily
1113 * reset vf, it depends on what state it exactly is. If it's not
1114 * initialized yet, it won't have vf reset since it's in a certain
1115 * state. If not, it will try to reset. Even vf is reset, pf will
1116 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1117 * it to ACTIVE. In this duration, vf may not catch the moment that
1118 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1122 ret = i40evf_check_vf_reset_done(hw);
1124 PMD_INIT_LOG(ERR, "VF is still resetting");
1132 i40evf_init_vf(struct rte_eth_dev *dev)
1135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1138 i40e_calc_itr_interval(0, 0);
1140 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1141 vf->dev_data = dev->data;
1142 err = i40e_set_mac_type(hw);
1144 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1148 err = i40evf_check_vf_reset_done(hw);
1152 i40e_init_adminq_parameter(hw);
1153 err = i40e_init_adminq(hw);
1155 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1159 /* Reset VF and wait until it's complete */
1160 if (i40evf_reset_vf(hw)) {
1161 PMD_INIT_LOG(ERR, "reset NIC failed");
1165 /* VF reset, shutdown admin queue and initialize again */
1166 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1167 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1171 i40e_init_adminq_parameter(hw);
1172 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "init_adminq failed");
1177 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1179 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1182 if (i40evf_check_api_version(dev) != 0) {
1183 PMD_INIT_LOG(ERR, "check_api version failed");
1186 bufsz = sizeof(struct virtchnl_vf_resource) +
1187 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1188 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1190 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1194 if (i40evf_get_vf_resource(dev) != 0) {
1195 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1199 /* got VF config message back from PF, now we can parse it */
1200 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1201 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1202 vf->vsi_res = &vf->vf_res->vsi_res[i];
1206 PMD_INIT_LOG(ERR, "no LAN VSI found");
1210 if (hw->mac.type == I40E_MAC_X722_VF)
1211 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1212 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1214 switch (vf->vsi_res->vsi_type) {
1215 case VIRTCHNL_VSI_SRIOV:
1216 vf->vsi.type = I40E_VSI_SRIOV;
1219 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1222 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1223 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1225 /* Store the MAC address configured by host, or generate random one */
1226 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1227 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1229 eth_random_addr(hw->mac.addr); /* Generate a random one */
1231 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1232 (I40E_ITR_INDEX_DEFAULT <<
1233 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1235 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1236 I40EVF_WRITE_FLUSH(hw);
1241 rte_free(vf->vf_res);
1244 rte_free(vf->aq_resp);
1246 i40e_shutdown_adminq(hw); /* ignore error */
1252 i40evf_uninit_vf(struct rte_eth_dev *dev)
1254 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1257 PMD_INIT_FUNC_TRACE();
1259 if (hw->adapter_stopped == 0)
1260 i40evf_dev_close(dev);
1261 rte_free(vf->vf_res);
1263 rte_free(vf->aq_resp);
1270 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1271 __rte_unused uint16_t msglen)
1273 struct virtchnl_pf_event *pf_msg =
1274 (struct virtchnl_pf_event *)msg;
1275 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1277 switch (pf_msg->event) {
1278 case VIRTCHNL_EVENT_RESET_IMPENDING:
1279 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1280 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1283 case VIRTCHNL_EVENT_LINK_CHANGE:
1284 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1285 vf->link_up = pf_msg->event_data.link_event.link_status;
1286 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1288 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1289 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1292 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1298 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1300 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1302 struct i40e_arq_event_info info;
1303 uint16_t pending, aq_opc;
1304 enum virtchnl_ops msg_opc;
1305 enum i40e_status_code msg_ret;
1308 info.buf_len = I40E_AQ_BUF_SZ;
1310 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1313 info.msg_buf = vf->aq_resp;
1317 ret = i40e_clean_arq_element(hw, &info, &pending);
1319 if (ret != I40E_SUCCESS) {
1320 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1324 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1325 /* For the message sent from pf to vf, opcode is stored in
1326 * cookie_high of struct i40e_aq_desc, while return error code
1327 * are stored in cookie_low, Which is done by
1328 * i40e_aq_send_msg_to_vf in PF driver.*/
1329 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1330 info.desc.cookie_high);
1331 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1332 info.desc.cookie_low);
1334 case i40e_aqc_opc_send_msg_to_vf:
1335 if (msg_opc == VIRTCHNL_OP_EVENT)
1337 i40evf_handle_pf_event(dev, info.msg_buf,
1340 /* read message and it's expected one */
1341 if (msg_opc == vf->pend_cmd) {
1342 vf->cmd_retval = msg_ret;
1343 /* prevent compiler reordering */
1344 rte_compiler_barrier();
1347 PMD_DRV_LOG(ERR, "command mismatch,"
1348 "expect %u, get %u",
1349 vf->pend_cmd, msg_opc);
1350 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1351 " opcode = %d", msg_opc);
1355 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1363 * Interrupt handler triggered by NIC for handling
1364 * specific interrupt. Only adminq interrupt is processed in VF.
1367 * Pointer to interrupt handle.
1369 * The address of parameter (struct rte_eth_dev *) regsitered before.
1375 i40evf_dev_alarm_handler(void *param)
1377 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1378 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381 i40evf_disable_irq0(hw);
1383 /* read out interrupt causes */
1384 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1386 /* No interrupt event indicated */
1387 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1390 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1391 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1392 i40evf_handle_aq_msg(dev);
1395 /* Link Status Change interrupt */
1396 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1397 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1401 i40evf_enable_irq0(hw);
1402 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1403 i40evf_dev_alarm_handler, dev);
1407 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1410 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1411 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1413 PMD_INIT_FUNC_TRACE();
1415 /* assign ops func pointer */
1416 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1417 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1418 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1421 * For secondary processes, we don't initialise any further as primary
1422 * has already done this work.
1424 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1425 i40e_set_rx_function(eth_dev);
1426 i40e_set_tx_function(eth_dev);
1429 i40e_set_default_ptype_table(eth_dev);
1430 i40e_set_default_pctype_table(eth_dev);
1431 rte_eth_copy_pci_info(eth_dev, pci_dev);
1433 hw->vendor_id = pci_dev->id.vendor_id;
1434 hw->device_id = pci_dev->id.device_id;
1435 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1436 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1437 hw->bus.device = pci_dev->addr.devid;
1438 hw->bus.func = pci_dev->addr.function;
1439 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1440 hw->adapter_stopped = 0;
1442 if(i40evf_init_vf(eth_dev) != 0) {
1443 PMD_INIT_LOG(ERR, "Init vf failed");
1447 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1448 i40evf_dev_alarm_handler, eth_dev);
1450 /* configure and enable device interrupt */
1451 i40evf_enable_irq0(hw);
1454 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1455 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1457 if (eth_dev->data->mac_addrs == NULL) {
1458 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1459 " store MAC addresses",
1460 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1463 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1464 ð_dev->data->mac_addrs[0]);
1470 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1472 PMD_INIT_FUNC_TRACE();
1474 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1477 eth_dev->dev_ops = NULL;
1478 eth_dev->rx_pkt_burst = NULL;
1479 eth_dev->tx_pkt_burst = NULL;
1481 if (i40evf_uninit_vf(eth_dev) != 0) {
1482 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1489 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1490 struct rte_pci_device *pci_dev)
1492 return rte_eth_dev_pci_generic_probe(pci_dev,
1493 sizeof(struct i40e_adapter), i40evf_dev_init);
1496 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1498 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1502 * virtual function driver struct
1504 static struct rte_pci_driver rte_i40evf_pmd = {
1505 .id_table = pci_id_i40evf_map,
1506 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1507 .probe = eth_i40evf_pci_probe,
1508 .remove = eth_i40evf_pci_remove,
1511 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1512 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1513 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1516 i40evf_dev_configure(struct rte_eth_dev *dev)
1518 struct i40e_adapter *ad =
1519 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1521 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1522 * allocation or vector Rx preconditions we will reset it.
1524 ad->rx_bulk_alloc_allowed = true;
1525 ad->rx_vec_allowed = true;
1526 ad->tx_simple_allowed = true;
1527 ad->tx_vec_allowed = true;
1529 return i40evf_init_vlan(dev);
1533 i40evf_init_vlan(struct rte_eth_dev *dev)
1535 /* Apply vlan offload setting */
1536 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1542 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1544 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1545 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1547 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1550 /* Vlan stripping setting */
1551 if (mask & ETH_VLAN_STRIP_MASK) {
1552 /* Enable or disable VLAN stripping */
1553 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1554 i40evf_enable_vlan_strip(dev);
1556 i40evf_disable_vlan_strip(dev);
1563 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1565 struct i40e_rx_queue *rxq;
1567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569 PMD_INIT_FUNC_TRACE();
1571 rxq = dev->data->rx_queues[rx_queue_id];
1573 err = i40e_alloc_rx_queue_mbufs(rxq);
1575 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1581 /* Init the RX tail register. */
1582 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1583 I40EVF_WRITE_FLUSH(hw);
1585 /* Ready to switch the queue on */
1586 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1588 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1592 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1598 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1600 struct i40e_rx_queue *rxq;
1603 rxq = dev->data->rx_queues[rx_queue_id];
1605 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1607 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1612 i40e_rx_queue_release_mbufs(rxq);
1613 i40e_reset_rx_queue(rxq);
1614 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1620 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1624 PMD_INIT_FUNC_TRACE();
1626 /* Ready to switch the queue on */
1627 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1629 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1633 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1639 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1641 struct i40e_tx_queue *txq;
1644 txq = dev->data->tx_queues[tx_queue_id];
1646 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1648 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1653 i40e_tx_queue_release_mbufs(txq);
1654 i40e_reset_tx_queue(txq);
1655 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1661 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1666 ret = i40evf_add_vlan(dev, vlan_id);
1668 ret = i40evf_del_vlan(dev,vlan_id);
1674 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 struct rte_eth_dev_data *dev_data = dev->data;
1678 struct rte_pktmbuf_pool_private *mbp_priv;
1679 uint16_t buf_size, len;
1681 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1682 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1683 I40EVF_WRITE_FLUSH(hw);
1685 /* Calculate the maximum packet length allowed */
1686 mbp_priv = rte_mempool_get_priv(rxq->mp);
1687 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1688 RTE_PKTMBUF_HEADROOM);
1689 rxq->hs_mode = i40e_header_split_none;
1690 rxq->rx_hdr_len = 0;
1691 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1692 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1693 rxq->max_pkt_len = RTE_MIN(len,
1694 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1697 * Check if the jumbo frame and maximum packet length are set correctly
1699 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1700 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1701 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1702 PMD_DRV_LOG(ERR, "maximum packet length must be "
1703 "larger than %u and smaller than %u, as jumbo "
1704 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1705 (uint32_t)I40E_FRAME_SIZE_MAX);
1706 return I40E_ERR_CONFIG;
1709 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1710 rxq->max_pkt_len > ETHER_MAX_LEN) {
1711 PMD_DRV_LOG(ERR, "maximum packet length must be "
1712 "larger than %u and smaller than %u, as jumbo "
1713 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1714 (uint32_t)ETHER_MAX_LEN);
1715 return I40E_ERR_CONFIG;
1719 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1720 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1721 dev_data->scattered_rx = 1;
1728 i40evf_rx_init(struct rte_eth_dev *dev)
1730 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1732 int ret = I40E_SUCCESS;
1733 struct i40e_rx_queue **rxq =
1734 (struct i40e_rx_queue **)dev->data->rx_queues;
1736 i40evf_config_rss(vf);
1737 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1738 if (!rxq[i] || !rxq[i]->q_set)
1740 ret = i40evf_rxq_init(dev, rxq[i]);
1741 if (ret != I40E_SUCCESS)
1744 if (ret == I40E_SUCCESS)
1745 i40e_set_rx_function(dev);
1751 i40evf_tx_init(struct rte_eth_dev *dev)
1754 struct i40e_tx_queue **txq =
1755 (struct i40e_tx_queue **)dev->data->tx_queues;
1756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758 for (i = 0; i < dev->data->nb_tx_queues; i++)
1759 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1761 i40e_set_tx_function(dev);
1765 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1771 if (!rte_intr_allow_others(intr_handle)) {
1773 I40E_VFINT_DYN_CTL01,
1774 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1775 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1776 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1777 I40EVF_WRITE_FLUSH(hw);
1781 I40EVF_WRITE_FLUSH(hw);
1785 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1791 if (!rte_intr_allow_others(intr_handle)) {
1792 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1793 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1794 I40EVF_WRITE_FLUSH(hw);
1798 I40EVF_WRITE_FLUSH(hw);
1802 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1804 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1805 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1806 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1808 i40e_calc_itr_interval(0, 0);
1811 msix_intr = intr_handle->intr_vec[queue_id];
1812 if (msix_intr == I40E_MISC_VEC_ID)
1813 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1814 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1815 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1816 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1818 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1821 I40E_VFINT_DYN_CTLN1(msix_intr -
1823 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1824 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1825 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1827 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1829 I40EVF_WRITE_FLUSH(hw);
1835 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1837 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1838 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842 msix_intr = intr_handle->intr_vec[queue_id];
1843 if (msix_intr == I40E_MISC_VEC_ID)
1844 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1847 I40E_VFINT_DYN_CTLN1(msix_intr -
1851 I40EVF_WRITE_FLUSH(hw);
1857 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1859 struct virtchnl_ether_addr_list *list;
1860 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1865 struct ether_addr *addr;
1866 struct vf_cmd_info args;
1870 len = sizeof(struct virtchnl_ether_addr_list);
1871 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1872 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1874 len += sizeof(struct virtchnl_ether_addr);
1875 if (len >= I40E_AQ_BUF_SZ) {
1881 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1883 PMD_DRV_LOG(ERR, "fail to allocate memory");
1887 for (i = begin; i < next_begin; i++) {
1888 addr = &dev->data->mac_addrs[i];
1889 if (is_zero_ether_addr(addr))
1891 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1892 sizeof(addr->addr_bytes));
1893 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1894 addr->addr_bytes[0], addr->addr_bytes[1],
1895 addr->addr_bytes[2], addr->addr_bytes[3],
1896 addr->addr_bytes[4], addr->addr_bytes[5]);
1899 list->vsi_id = vf->vsi_res->vsi_id;
1900 list->num_elements = j;
1901 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1902 VIRTCHNL_OP_DEL_ETH_ADDR;
1903 args.in_args = (uint8_t *)list;
1904 args.in_args_size = len;
1905 args.out_buffer = vf->aq_resp;
1906 args.out_size = I40E_AQ_BUF_SZ;
1907 err = i40evf_execute_vf_cmd(dev, &args);
1909 PMD_DRV_LOG(ERR, "fail to execute command %s",
1910 add ? "OP_ADD_ETHER_ADDRESS" :
1911 "OP_DEL_ETHER_ADDRESS");
1920 } while (begin < I40E_NUM_MACADDR_MAX);
1924 i40evf_dev_start(struct rte_eth_dev *dev)
1926 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1927 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1929 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930 uint32_t intr_vector = 0;
1932 PMD_INIT_FUNC_TRACE();
1934 hw->adapter_stopped = 0;
1936 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1937 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1938 dev->data->nb_tx_queues);
1940 /* check and configure queue intr-vector mapping */
1941 if (rte_intr_cap_multiple(intr_handle) &&
1942 dev->data->dev_conf.intr_conf.rxq) {
1943 intr_vector = dev->data->nb_rx_queues;
1944 if (rte_intr_efd_enable(intr_handle, intr_vector))
1948 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1949 intr_handle->intr_vec =
1950 rte_zmalloc("intr_vec",
1951 dev->data->nb_rx_queues * sizeof(int), 0);
1952 if (!intr_handle->intr_vec) {
1953 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1954 " intr_vec", dev->data->nb_rx_queues);
1959 if (i40evf_rx_init(dev) != 0){
1960 PMD_DRV_LOG(ERR, "failed to do RX init");
1964 i40evf_tx_init(dev);
1966 if (i40evf_configure_vsi_queues(dev) != 0) {
1967 PMD_DRV_LOG(ERR, "configure queues failed");
1970 if (i40evf_config_irq_map(dev)) {
1971 PMD_DRV_LOG(ERR, "config_irq_map failed");
1975 /* Set all mac addrs */
1976 i40evf_add_del_all_mac_addr(dev, TRUE);
1977 /* Set all multicast addresses */
1978 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
1981 if (i40evf_start_queues(dev) != 0) {
1982 PMD_DRV_LOG(ERR, "enable queues failed");
1986 /* only enable interrupt in rx interrupt mode */
1987 if (dev->data->dev_conf.intr_conf.rxq != 0)
1988 rte_intr_enable(intr_handle);
1990 i40evf_enable_queues_intr(dev);
1995 i40evf_add_del_all_mac_addr(dev, FALSE);
1996 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2003 i40evf_dev_stop(struct rte_eth_dev *dev)
2005 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2007 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2010 PMD_INIT_FUNC_TRACE();
2012 if (dev->data->dev_conf.intr_conf.rxq != 0)
2013 rte_intr_disable(intr_handle);
2015 if (hw->adapter_stopped == 1)
2017 i40evf_stop_queues(dev);
2018 i40evf_disable_queues_intr(dev);
2019 i40e_dev_clear_queues(dev);
2021 /* Clean datapath event and queue/vec mapping */
2022 rte_intr_efd_disable(intr_handle);
2023 if (intr_handle->intr_vec) {
2024 rte_free(intr_handle->intr_vec);
2025 intr_handle->intr_vec = NULL;
2027 /* remove all mac addrs */
2028 i40evf_add_del_all_mac_addr(dev, FALSE);
2029 /* remove all multicast addresses */
2030 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2032 hw->adapter_stopped = 1;
2037 i40evf_dev_link_update(struct rte_eth_dev *dev,
2038 __rte_unused int wait_to_complete)
2040 struct rte_eth_link new_link;
2041 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2043 * DPDK pf host provide interfacet to acquire link status
2044 * while Linux driver does not
2047 memset(&new_link, 0, sizeof(new_link));
2048 /* Linux driver PF host */
2049 switch (vf->link_speed) {
2050 case I40E_LINK_SPEED_100MB:
2051 new_link.link_speed = ETH_SPEED_NUM_100M;
2053 case I40E_LINK_SPEED_1GB:
2054 new_link.link_speed = ETH_SPEED_NUM_1G;
2056 case I40E_LINK_SPEED_10GB:
2057 new_link.link_speed = ETH_SPEED_NUM_10G;
2059 case I40E_LINK_SPEED_20GB:
2060 new_link.link_speed = ETH_SPEED_NUM_20G;
2062 case I40E_LINK_SPEED_25GB:
2063 new_link.link_speed = ETH_SPEED_NUM_25G;
2065 case I40E_LINK_SPEED_40GB:
2066 new_link.link_speed = ETH_SPEED_NUM_40G;
2069 new_link.link_speed = ETH_SPEED_NUM_100M;
2072 /* full duplex only */
2073 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2074 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2076 new_link.link_autoneg =
2077 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2079 return rte_eth_linkstatus_set(dev, &new_link);
2083 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2085 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2088 /* If enabled, just return */
2089 if (vf->promisc_unicast_enabled)
2092 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2094 vf->promisc_unicast_enabled = TRUE;
2098 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2100 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2103 /* If disabled, just return */
2104 if (!vf->promisc_unicast_enabled)
2107 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2109 vf->promisc_unicast_enabled = FALSE;
2113 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2115 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2118 /* If enabled, just return */
2119 if (vf->promisc_multicast_enabled)
2122 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2124 vf->promisc_multicast_enabled = TRUE;
2128 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2130 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2133 /* If enabled, just return */
2134 if (!vf->promisc_multicast_enabled)
2137 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2139 vf->promisc_multicast_enabled = FALSE;
2143 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2145 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2147 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2148 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2149 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2150 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2151 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2152 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2153 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2154 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2155 dev_info->rx_queue_offload_capa = 0;
2156 dev_info->rx_offload_capa =
2157 DEV_RX_OFFLOAD_VLAN_STRIP |
2158 DEV_RX_OFFLOAD_QINQ_STRIP |
2159 DEV_RX_OFFLOAD_IPV4_CKSUM |
2160 DEV_RX_OFFLOAD_UDP_CKSUM |
2161 DEV_RX_OFFLOAD_TCP_CKSUM |
2162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2163 DEV_RX_OFFLOAD_SCATTER |
2164 DEV_RX_OFFLOAD_JUMBO_FRAME |
2165 DEV_RX_OFFLOAD_VLAN_FILTER;
2167 dev_info->tx_queue_offload_capa = 0;
2168 dev_info->tx_offload_capa =
2169 DEV_TX_OFFLOAD_VLAN_INSERT |
2170 DEV_TX_OFFLOAD_QINQ_INSERT |
2171 DEV_TX_OFFLOAD_IPV4_CKSUM |
2172 DEV_TX_OFFLOAD_UDP_CKSUM |
2173 DEV_TX_OFFLOAD_TCP_CKSUM |
2174 DEV_TX_OFFLOAD_SCTP_CKSUM |
2175 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2176 DEV_TX_OFFLOAD_TCP_TSO |
2177 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2178 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2179 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2180 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2181 DEV_TX_OFFLOAD_MULTI_SEGS;
2183 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2185 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2186 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2187 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2189 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2194 dev_info->default_txconf = (struct rte_eth_txconf) {
2196 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2197 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2198 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2200 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2201 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2205 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2206 .nb_max = I40E_MAX_RING_DESC,
2207 .nb_min = I40E_MIN_RING_DESC,
2208 .nb_align = I40E_ALIGN_RING_DESC,
2211 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2212 .nb_max = I40E_MAX_RING_DESC,
2213 .nb_min = I40E_MIN_RING_DESC,
2214 .nb_align = I40E_ALIGN_RING_DESC,
2219 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2222 struct i40e_eth_stats *pstats = NULL;
2223 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2224 struct i40e_vsi *vsi = &vf->vsi;
2226 ret = i40evf_query_stats(dev, &pstats);
2228 i40evf_update_stats(vsi, pstats);
2230 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2231 pstats->rx_broadcast;
2232 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2234 stats->imissed = pstats->rx_discards;
2235 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2236 stats->ibytes = pstats->rx_bytes;
2237 stats->obytes = pstats->tx_bytes;
2239 PMD_DRV_LOG(ERR, "Get statistics failed");
2245 i40evf_dev_close(struct rte_eth_dev *dev)
2247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249 i40evf_dev_stop(dev);
2250 i40e_dev_free_queues(dev);
2252 * disable promiscuous mode before reset vf
2253 * it is a workaround solution when work with kernel driver
2254 * and it is not the normal way
2256 i40evf_dev_promiscuous_disable(dev);
2257 i40evf_dev_allmulticast_disable(dev);
2259 i40evf_reset_vf(hw);
2260 i40e_shutdown_adminq(hw);
2261 i40evf_disable_irq0(hw);
2262 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2266 * Reset VF device only to re-initialize resources in PMD layer
2269 i40evf_dev_reset(struct rte_eth_dev *dev)
2273 ret = i40evf_dev_uninit(dev);
2277 ret = i40evf_dev_init(dev);
2283 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2285 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2286 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2292 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2293 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2296 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2300 uint32_t *lut_dw = (uint32_t *)lut;
2301 uint16_t i, lut_size_dw = lut_size / 4;
2303 for (i = 0; i < lut_size_dw; i++)
2304 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2311 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2320 vf = I40E_VSI_TO_VF(vsi);
2321 hw = I40E_VSI_TO_HW(vsi);
2323 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2324 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2327 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2331 uint32_t *lut_dw = (uint32_t *)lut;
2332 uint16_t i, lut_size_dw = lut_size / 4;
2334 for (i = 0; i < lut_size_dw; i++)
2335 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2336 I40EVF_WRITE_FLUSH(hw);
2343 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2344 struct rte_eth_rss_reta_entry64 *reta_conf,
2347 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2349 uint16_t i, idx, shift;
2352 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2353 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2354 "(%d) doesn't match the number of hardware can "
2355 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2359 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2361 PMD_DRV_LOG(ERR, "No memory can be allocated");
2364 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2367 for (i = 0; i < reta_size; i++) {
2368 idx = i / RTE_RETA_GROUP_SIZE;
2369 shift = i % RTE_RETA_GROUP_SIZE;
2370 if (reta_conf[idx].mask & (1ULL << shift))
2371 lut[i] = reta_conf[idx].reta[shift];
2373 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2382 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2383 struct rte_eth_rss_reta_entry64 *reta_conf,
2386 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2387 uint16_t i, idx, shift;
2391 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2392 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2393 "(%d) doesn't match the number of hardware can "
2394 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2398 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2400 PMD_DRV_LOG(ERR, "No memory can be allocated");
2404 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2407 for (i = 0; i < reta_size; i++) {
2408 idx = i / RTE_RETA_GROUP_SIZE;
2409 shift = i % RTE_RETA_GROUP_SIZE;
2410 if (reta_conf[idx].mask & (1ULL << shift))
2411 reta_conf[idx].reta[shift] = lut[i];
2421 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2423 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2424 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2427 if (!key || key_len == 0) {
2428 PMD_DRV_LOG(DEBUG, "No key to be configured");
2430 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2432 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2436 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2437 struct i40e_aqc_get_set_rss_key_data *key_dw =
2438 (struct i40e_aqc_get_set_rss_key_data *)key;
2440 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2442 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2445 uint32_t *hash_key = (uint32_t *)key;
2448 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2449 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2450 I40EVF_WRITE_FLUSH(hw);
2457 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2459 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2460 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2463 if (!key || !key_len)
2466 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2467 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2468 (struct i40e_aqc_get_set_rss_key_data *)key);
2470 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2474 uint32_t *key_dw = (uint32_t *)key;
2477 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2478 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2480 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2486 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2488 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2492 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2493 rss_conf->rss_key_len);
2497 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2498 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2499 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2500 I40EVF_WRITE_FLUSH(hw);
2506 i40evf_disable_rss(struct i40e_vf *vf)
2508 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2510 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2511 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2512 I40EVF_WRITE_FLUSH(hw);
2516 i40evf_config_rss(struct i40e_vf *vf)
2518 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2519 struct rte_eth_rss_conf rss_conf;
2520 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2523 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2524 i40evf_disable_rss(vf);
2525 PMD_DRV_LOG(DEBUG, "RSS not configured");
2529 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2530 /* Fill out the look up table */
2531 for (i = 0, j = 0; i < nb_q; i++, j++) {
2534 lut = (lut << 8) | j;
2536 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2539 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2540 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2541 i40evf_disable_rss(vf);
2542 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2546 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2547 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2548 /* Calculate the default hash key */
2549 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2550 rss_key_default[i] = (uint32_t)rte_rand();
2551 rss_conf.rss_key = (uint8_t *)rss_key_default;
2552 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2556 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2560 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2561 struct rte_eth_rss_conf *rss_conf)
2563 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2564 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2568 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2569 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2571 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2572 if (rss_hf != 0) /* Enable RSS */
2578 if (rss_hf == 0) /* Disable RSS */
2581 return i40evf_hw_rss_hash_set(vf, rss_conf);
2585 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2586 struct rte_eth_rss_conf *rss_conf)
2588 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2593 &rss_conf->rss_key_len);
2595 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2596 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2597 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2603 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2605 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2606 struct rte_eth_dev_data *dev_data = vf->dev_data;
2607 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2610 /* check if mtu is within the allowed range */
2611 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2614 /* mtu setting is forbidden if port is start */
2615 if (dev_data->dev_started) {
2616 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2621 if (frame_size > ETHER_MAX_LEN)
2622 dev_data->dev_conf.rxmode.offloads |=
2623 DEV_RX_OFFLOAD_JUMBO_FRAME;
2625 dev_data->dev_conf.rxmode.offloads &=
2626 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2627 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2633 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2634 struct ether_addr *mac_addr)
2636 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639 if (!is_valid_assigned_ether_addr(mac_addr)) {
2640 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2644 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2647 i40evf_del_mac_addr_by_addr(dev, (struct ether_addr *)hw->mac.addr);
2649 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2652 ether_addr_copy(mac_addr, (struct ether_addr *)hw->mac.addr);
2657 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2658 struct ether_addr *mc_addrs,
2659 uint32_t mc_addrs_num, bool add)
2661 struct virtchnl_ether_addr_list *list;
2662 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2663 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2664 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2667 struct vf_cmd_info args;
2669 if (mc_addrs == NULL || mc_addrs_num == 0)
2672 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2675 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2676 list->vsi_id = vf->vsi_res->vsi_id;
2677 list->num_elements = mc_addrs_num;
2679 for (i = 0; i < mc_addrs_num; i++) {
2680 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2681 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2682 mc_addrs[i].addr_bytes[0],
2683 mc_addrs[i].addr_bytes[1],
2684 mc_addrs[i].addr_bytes[2],
2685 mc_addrs[i].addr_bytes[3],
2686 mc_addrs[i].addr_bytes[4],
2687 mc_addrs[i].addr_bytes[5]);
2691 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2692 sizeof(list->list[i].addr));
2695 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2696 args.in_args = cmd_buffer;
2697 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2698 i * sizeof(struct virtchnl_ether_addr);
2699 args.out_buffer = vf->aq_resp;
2700 args.out_size = I40E_AQ_BUF_SZ;
2701 err = i40evf_execute_vf_cmd(dev, &args);
2703 PMD_DRV_LOG(ERR, "fail to execute command %s",
2704 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2712 i40evf_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addrs,
2713 uint32_t mc_addrs_num)
2715 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2718 /* flush previous addresses */
2719 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2724 vf->mc_addrs_num = 0;
2727 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2732 vf->mc_addrs_num = mc_addrs_num;
2733 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));