drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum i40e_virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum i40e_virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   __rte_unused int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 123                                 int on);
 124 static void i40evf_dev_close(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 131                                      uint16_t rx_queue_id);
 132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 133                                     uint16_t rx_queue_id);
 134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 135                                      uint16_t tx_queue_id);
 136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 137                                     uint16_t tx_queue_id);
 138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 139                                 struct ether_addr *addr,
 140                                 uint32_t index,
 141                                 uint32_t pool);
 142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                         struct rte_eth_rss_reta_entry64 *reta_conf,
 148                         uint16_t reta_size);
 149 static int i40evf_config_rss(struct i40e_vf *vf);
 150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 151                                       struct rte_eth_rss_conf *rss_conf);
 152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 153                                         struct rte_eth_rss_conf *rss_conf);
 154 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 155 static int
 156 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 157 static int
 158 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 159 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 160                                    uint8_t *msg,
 161                                    uint16_t msglen);
 162
 163 /* Default hash key buffer for RSS */
 164 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 165
 166 struct rte_i40evf_xstats_name_off {
 167         char name[RTE_ETH_XSTATS_NAME_SIZE];
 168         unsigned offset;
 169 };
 170
 171 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 172         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 173         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 174         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 175         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 176         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 177         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 178                 rx_unknown_protocol)},
 179         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 180         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 181         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 182         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 183         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 184         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 185 };
 186
 187 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 188                 sizeof(rte_i40evf_stats_strings[0]))
 189
 190 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 191         .dev_configure        = i40evf_dev_configure,
 192         .dev_start            = i40evf_dev_start,
 193         .dev_stop             = i40evf_dev_stop,
 194         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 195         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 196         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 197         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 198         .link_update          = i40evf_dev_link_update,
 199         .stats_get            = i40evf_dev_stats_get,
 200         .xstats_get           = i40evf_dev_xstats_get,
 201         .xstats_get_names     = i40evf_dev_xstats_get_names,
 202         .xstats_reset         = i40evf_dev_xstats_reset,
 203         .dev_close            = i40evf_dev_close,
 204         .dev_infos_get        = i40evf_dev_info_get,
 205         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 206         .vlan_filter_set      = i40evf_vlan_filter_set,
 207         .vlan_offload_set     = i40evf_vlan_offload_set,
 208         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 209         .rx_queue_start       = i40evf_dev_rx_queue_start,
 210         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 211         .tx_queue_start       = i40evf_dev_tx_queue_start,
 212         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 213         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 214         .rx_queue_release     = i40e_dev_rx_queue_release,
 215         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 216         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 217         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 218         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 219         .tx_queue_release     = i40e_dev_tx_queue_release,
 220         .rx_queue_count       = i40e_dev_rx_queue_count,
 221         .rxq_info_get         = i40e_rxq_info_get,
 222         .txq_info_get         = i40e_txq_info_get,
 223         .mac_addr_add         = i40evf_add_mac_addr,
 224         .mac_addr_remove      = i40evf_del_mac_addr,
 225         .reta_update          = i40evf_dev_rss_reta_update,
 226         .reta_query           = i40evf_dev_rss_reta_query,
 227         .rss_hash_update      = i40evf_dev_rss_hash_update,
 228         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 229         .mtu_set              = i40evf_dev_mtu_set,
 230 };
 231
 232 /*
 233  * Read data in admin queue to get msg from pf driver
 234  */
 235 static enum i40evf_aq_result
 236 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 237 {
 238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 239         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 240         struct i40e_arq_event_info event;
 241         enum i40e_virtchnl_ops opcode;
 242         enum i40e_status_code retval;
 243         int ret;
 244         enum i40evf_aq_result result = I40EVF_MSG_NON;
 245
 246         event.buf_len = data->buf_len;
 247         event.msg_buf = data->msg;
 248         ret = i40e_clean_arq_element(hw, &event, NULL);
 249         /* Can't read any msg from adminQ */
 250         if (ret) {
 251                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 252                         result = I40EVF_MSG_ERR;
 253                 return result;
 254         }
 255
 256         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 257         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 258         /* pf sys event */
 259         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 260                 struct i40e_virtchnl_pf_event *vpe =
 261                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 262
 263                 result = I40EVF_MSG_SYS;
 264                 switch (vpe->event) {
 265                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 266                         vf->link_up =
 267                                 vpe->event_data.link_event.link_status;
 268                         vf->link_speed =
 269                                 vpe->event_data.link_event.link_speed;
 270                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 271                         PMD_DRV_LOG(INFO, "Link status update:%s",
 272                                     vf->link_up ? "up" : "down");
 273                         break;
 274                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 275                         vf->vf_reset = true;
 276                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 277                         PMD_DRV_LOG(INFO, "vf is reseting");
 278                         break;
 279                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 280                         vf->dev_closed = true;
 281                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 282                         PMD_DRV_LOG(INFO, "PF driver closed");
 283                         break;
 284                 default:
 285                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 286                                     __func__, vpe->event);
 287                 }
 288         } else {
 289                 /* async reply msg on command issued by vf previously */
 290                 result = I40EVF_MSG_CMD;
 291                 /* Actual data length read from PF */
 292                 data->msg_len = event.msg_len;
 293         }
 294
 295         data->result = retval;
 296         data->ops = opcode;
 297
 298         return result;
 299 }
 300
 301 /**
 302  * clear current command. Only call in case execute
 303  * _atomic_set_cmd successfully.
 304  */
 305 static inline void
 306 _clear_cmd(struct i40e_vf *vf)
 307 {
 308         rte_wmb();
 309         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 310 }
 311
 312 /*
 313  * Check there is pending cmd in execution. If none, set new command.
 314  */
 315 static inline int
 316 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 317 {
 318         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 319                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 320
 321         if (!ret)
 322                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 323
 324         return !ret;
 325 }
 326
 327 #define MAX_TRY_TIMES 200
 328 #define ASQ_DELAY_MS  10
 329
 330 static int
 331 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 332 {
 333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 334         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 335         struct i40evf_arq_msg_info info;
 336         enum i40evf_aq_result ret;
 337         int err, i = 0;
 338
 339         if (_atomic_set_cmd(vf, args->ops))
 340                 return -1;
 341
 342         info.msg = args->out_buffer;
 343         info.buf_len = args->out_size;
 344         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 345         info.result = I40E_SUCCESS;
 346
 347         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 348                      args->in_args, args->in_args_size, NULL);
 349         if (err) {
 350                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 351                 _clear_cmd(vf);
 352                 return err;
 353         }
 354
 355         switch (args->ops) {
 356         case I40E_VIRTCHNL_OP_RESET_VF:
 357                 /*no need to process in this function */
 358                 err = 0;
 359                 break;
 360         case I40E_VIRTCHNL_OP_VERSION:
 361         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 362                 /* for init adminq commands, need to poll the response */
 363                 err = -1;
 364                 do {
 365                         ret = i40evf_read_pfmsg(dev, &info);
 366                         vf->cmd_retval = info.result;
 367                         if (ret == I40EVF_MSG_CMD) {
 368                                 err = 0;
 369                                 break;
 370                         } else if (ret == I40EVF_MSG_ERR)
 371                                 break;
 372                         rte_delay_ms(ASQ_DELAY_MS);
 373                         /* If don't read msg or read sys event, continue */
 374                 } while (i++ < MAX_TRY_TIMES);
 375                 _clear_cmd(vf);
 376                 break;
 377
 378         default:
 379                 /* for other adminq in running time, waiting the cmd done flag */
 380                 err = -1;
 381                 do {
 382                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 383                                 err = 0;
 384                                 break;
 385                         }
 386                         rte_delay_ms(ASQ_DELAY_MS);
 387                         /* If don't read msg or read sys event, continue */
 388                 } while (i++ < MAX_TRY_TIMES);
 389                 break;
 390         }
 391
 392         return err | vf->cmd_retval;
 393 }
 394
 395 /*
 396  * Check API version with sync wait until version read or fail from admin queue
 397  */
 398 static int
 399 i40evf_check_api_version(struct rte_eth_dev *dev)
 400 {
 401         struct i40e_virtchnl_version_info version, *pver;
 402         int err;
 403         struct vf_cmd_info args;
 404         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 405
 406         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 407         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 408
 409         args.ops = I40E_VIRTCHNL_OP_VERSION;
 410         args.in_args = (uint8_t *)&version;
 411         args.in_args_size = sizeof(version);
 412         args.out_buffer = vf->aq_resp;
 413         args.out_size = I40E_AQ_BUF_SZ;
 414
 415         err = i40evf_execute_vf_cmd(dev, &args);
 416         if (err) {
 417                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 418                 return err;
 419         }
 420
 421         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 422         vf->version_major = pver->major;
 423         vf->version_minor = pver->minor;
 424         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 425                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 426         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 427                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 428                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 429         else {
 430                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 431                                         vf->version_major, vf->version_minor,
 432                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 433                                                 I40E_VIRTCHNL_VERSION_MINOR);
 434                 return -1;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int
 441 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 442 {
 443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 444         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 445         int err;
 446         struct vf_cmd_info args;
 447         uint32_t caps, len;
 448
 449         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 450         args.out_buffer = vf->aq_resp;
 451         args.out_size = I40E_AQ_BUF_SZ;
 452         if (PF_IS_V11(vf)) {
 453                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 454                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 455                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 456                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 457                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 458                 args.in_args = (uint8_t *)&caps;
 459                 args.in_args_size = sizeof(caps);
 460         } else {
 461                 args.in_args = NULL;
 462                 args.in_args_size = 0;
 463         }
 464         err = i40evf_execute_vf_cmd(dev, &args);
 465
 466         if (err) {
 467                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 468                 return err;
 469         }
 470
 471         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 472                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 473
 474         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 475                         RTE_MIN(args.out_size, len));
 476         i40e_vf_parse_hw_config(hw, vf->vf_res);
 477
 478         return 0;
 479 }
 480
 481 static int
 482 i40evf_config_promisc(struct rte_eth_dev *dev,
 483                       bool enable_unicast,
 484                       bool enable_multicast)
 485 {
 486         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 487         int err;
 488         struct vf_cmd_info args;
 489         struct i40e_virtchnl_promisc_info promisc;
 490
 491         promisc.flags = 0;
 492         promisc.vsi_id = vf->vsi_res->vsi_id;
 493
 494         if (enable_unicast)
 495                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 496
 497         if (enable_multicast)
 498                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 499
 500         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 501         args.in_args = (uint8_t *)&promisc;
 502         args.in_args_size = sizeof(promisc);
 503         args.out_buffer = vf->aq_resp;
 504         args.out_size = I40E_AQ_BUF_SZ;
 505
 506         err = i40evf_execute_vf_cmd(dev, &args);
 507
 508         if (err)
 509                 PMD_DRV_LOG(ERR, "fail to execute command "
 510                             "CONFIG_PROMISCUOUS_MODE");
 511         return err;
 512 }
 513
 514 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 515 static int
 516 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 517                                 bool enable_vlan_strip)
 518 {
 519         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 520         int err;
 521         struct vf_cmd_info args;
 522         struct i40e_virtchnl_vlan_offload_info offload;
 523
 524         offload.vsi_id = vf->vsi_res->vsi_id;
 525         offload.enable_vlan_strip = enable_vlan_strip;
 526
 527         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 528         args.in_args = (uint8_t *)&offload;
 529         args.in_args_size = sizeof(offload);
 530         args.out_buffer = vf->aq_resp;
 531         args.out_size = I40E_AQ_BUF_SZ;
 532
 533         err = i40evf_execute_vf_cmd(dev, &args);
 534         if (err)
 535                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 536
 537         return err;
 538 }
 539
 540 static int
 541 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 542                                 struct i40e_vsi_vlan_pvid_info *info)
 543 {
 544         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 545         int err;
 546         struct vf_cmd_info args;
 547         struct i40e_virtchnl_pvid_info tpid_info;
 548
 549         if (info == NULL) {
 550                 PMD_DRV_LOG(ERR, "invalid parameters");
 551                 return I40E_ERR_PARAM;
 552         }
 553
 554         memset(&tpid_info, 0, sizeof(tpid_info));
 555         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 556         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 557
 558         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 559         args.in_args = (uint8_t *)&tpid_info;
 560         args.in_args_size = sizeof(tpid_info);
 561         args.out_buffer = vf->aq_resp;
 562         args.out_size = I40E_AQ_BUF_SZ;
 563
 564         err = i40evf_execute_vf_cmd(dev, &args);
 565         if (err)
 566                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 567
 568         return err;
 569 }
 570
 571 static void
 572 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 573                                   uint16_t vsi_id,
 574                                   uint16_t queue_id,
 575                                   uint16_t nb_txq,
 576                                   struct i40e_tx_queue *txq)
 577 {
 578         txq_info->vsi_id = vsi_id;
 579         txq_info->queue_id = queue_id;
 580         if (queue_id < nb_txq) {
 581                 txq_info->ring_len = txq->nb_tx_desc;
 582                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 583         }
 584 }
 585
 586 static void
 587 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 588                                   uint16_t vsi_id,
 589                                   uint16_t queue_id,
 590                                   uint16_t nb_rxq,
 591                                   uint32_t max_pkt_size,
 592                                   struct i40e_rx_queue *rxq)
 593 {
 594         rxq_info->vsi_id = vsi_id;
 595         rxq_info->queue_id = queue_id;
 596         rxq_info->max_pkt_size = max_pkt_size;
 597         if (queue_id < nb_rxq) {
 598                 rxq_info->ring_len = rxq->nb_rx_desc;
 599                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 600                 rxq_info->databuffer_size =
 601                         (rte_pktmbuf_data_room_size(rxq->mp) -
 602                                 RTE_PKTMBUF_HEADROOM);
 603         }
 604 }
 605
 606 /* It configures VSI queues to co-work with Linux PF host */
 607 static int
 608 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 609 {
 610         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 611         struct i40e_rx_queue **rxq =
 612                 (struct i40e_rx_queue **)dev->data->rx_queues;
 613         struct i40e_tx_queue **txq =
 614                 (struct i40e_tx_queue **)dev->data->tx_queues;
 615         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 616         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 617         struct vf_cmd_info args;
 618         uint16_t i, nb_qp = vf->num_queue_pairs;
 619         const uint32_t size =
 620                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 621         uint8_t buff[size];
 622         int ret;
 623
 624         memset(buff, 0, sizeof(buff));
 625         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 626         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 627         vc_vqci->num_queue_pairs = nb_qp;
 628
 629         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 630                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 631                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 632                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 633                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 634                                         vf->max_pkt_len, rxq[i]);
 635         }
 636         memset(&args, 0, sizeof(args));
 637         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 638         args.in_args = (uint8_t *)vc_vqci;
 639         args.in_args_size = size;
 640         args.out_buffer = vf->aq_resp;
 641         args.out_size = I40E_AQ_BUF_SZ;
 642         ret = i40evf_execute_vf_cmd(dev, &args);
 643         if (ret)
 644                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 645                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 646
 647         return ret;
 648 }
 649
 650 /* It configures VSI queues to co-work with DPDK PF host */
 651 static int
 652 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 653 {
 654         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 655         struct i40e_rx_queue **rxq =
 656                 (struct i40e_rx_queue **)dev->data->rx_queues;
 657         struct i40e_tx_queue **txq =
 658                 (struct i40e_tx_queue **)dev->data->tx_queues;
 659         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 660         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 661         struct vf_cmd_info args;
 662         uint16_t i, nb_qp = vf->num_queue_pairs;
 663         const uint32_t size =
 664                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 665         uint8_t buff[size];
 666         int ret;
 667
 668         memset(buff, 0, sizeof(buff));
 669         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 670         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 671         vc_vqcei->num_queue_pairs = nb_qp;
 672         vc_qpei = vc_vqcei->qpair;
 673         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 674                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 675                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 676                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 677                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 678                                         vf->max_pkt_len, rxq[i]);
 679                 if (i < dev->data->nb_rx_queues)
 680                         /*
 681                          * It adds extra info for configuring VSI queues, which
 682                          * is needed to enable the configurable crc stripping
 683                          * in VF.
 684                          */
 685                         vc_qpei->rxq_ext.crcstrip =
 686                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 687         }
 688         memset(&args, 0, sizeof(args));
 689         args.ops =
 690                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 691         args.in_args = (uint8_t *)vc_vqcei;
 692         args.in_args_size = size;
 693         args.out_buffer = vf->aq_resp;
 694         args.out_size = I40E_AQ_BUF_SZ;
 695         ret = i40evf_execute_vf_cmd(dev, &args);
 696         if (ret)
 697                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 698                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 699
 700         return ret;
 701 }
 702
 703 static int
 704 i40evf_configure_queues(struct rte_eth_dev *dev)
 705 {
 706         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 707
 708         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 709                 /* To support DPDK PF host */
 710                 return i40evf_configure_vsi_queues_ext(dev);
 711         else
 712                 /* To support Linux PF host */
 713                 return i40evf_configure_vsi_queues(dev);
 714 }
 715
 716 static int
 717 i40evf_config_irq_map(struct rte_eth_dev *dev)
 718 {
 719         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 720         struct vf_cmd_info args;
 721         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 722                 sizeof(struct i40e_virtchnl_vector_map)];
 723         struct i40e_virtchnl_irq_map_info *map_info;
 724         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 725         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 726         uint32_t vector_id;
 727         int i, err;
 728
 729         if (rte_intr_allow_others(intr_handle)) {
 730                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 731                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 732                 else
 733                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 734         } else {
 735                 vector_id = I40E_MISC_VEC_ID;
 736         }
 737
 738         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 739         map_info->num_vectors = 1;
 740         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 741         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 742         /* Alway use default dynamic MSIX interrupt */
 743         map_info->vecmap[0].vector_id = vector_id;
 744         /* Don't map any tx queue */
 745         map_info->vecmap[0].txq_map = 0;
 746         map_info->vecmap[0].rxq_map = 0;
 747         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 748                 map_info->vecmap[0].rxq_map |= 1 << i;
 749                 if (rte_intr_dp_is_en(intr_handle))
 750                         intr_handle->intr_vec[i] = vector_id;
 751         }
 752
 753         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 754         args.in_args = (u8 *)cmd_buffer;
 755         args.in_args_size = sizeof(cmd_buffer);
 756         args.out_buffer = vf->aq_resp;
 757         args.out_size = I40E_AQ_BUF_SZ;
 758         err = i40evf_execute_vf_cmd(dev, &args);
 759         if (err)
 760                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 761
 762         return err;
 763 }
 764
 765 static int
 766 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 767                                 bool on)
 768 {
 769         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 770         struct i40e_virtchnl_queue_select queue_select;
 771         int err;
 772         struct vf_cmd_info args;
 773         memset(&queue_select, 0, sizeof(queue_select));
 774         queue_select.vsi_id = vf->vsi_res->vsi_id;
 775
 776         if (isrx)
 777                 queue_select.rx_queues |= 1 << qid;
 778         else
 779                 queue_select.tx_queues |= 1 << qid;
 780
 781         if (on)
 782                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 783         else
 784                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 785         args.in_args = (u8 *)&queue_select;
 786         args.in_args_size = sizeof(queue_select);
 787         args.out_buffer = vf->aq_resp;
 788         args.out_size = I40E_AQ_BUF_SZ;
 789         err = i40evf_execute_vf_cmd(dev, &args);
 790         if (err)
 791                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 792                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 793
 794         return err;
 795 }
 796
 797 static int
 798 i40evf_start_queues(struct rte_eth_dev *dev)
 799 {
 800         struct rte_eth_dev_data *dev_data = dev->data;
 801         int i;
 802         struct i40e_rx_queue *rxq;
 803         struct i40e_tx_queue *txq;
 804
 805         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 806                 rxq = dev_data->rx_queues[i];
 807                 if (rxq->rx_deferred_start)
 808                         continue;
 809                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 810                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 811                         return -1;
 812                 }
 813         }
 814
 815         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 816                 txq = dev_data->tx_queues[i];
 817                 if (txq->tx_deferred_start)
 818                         continue;
 819                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 820                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 821                         return -1;
 822                 }
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int
 829 i40evf_stop_queues(struct rte_eth_dev *dev)
 830 {
 831         int i;
 832
 833         /* Stop TX queues first */
 834         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 835                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 836                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 837                         return -1;
 838                 }
 839         }
 840
 841         /* Then stop RX queues */
 842         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 843                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 844                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 845                         return -1;
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static void
 853 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 854                     struct ether_addr *addr,
 855                     __rte_unused uint32_t index,
 856                     __rte_unused uint32_t pool)
 857 {
 858         struct i40e_virtchnl_ether_addr_list *list;
 859         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 860         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 861                         sizeof(struct i40e_virtchnl_ether_addr)];
 862         int err;
 863         struct vf_cmd_info args;
 864
 865         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 866                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 867                             addr->addr_bytes[0], addr->addr_bytes[1],
 868                             addr->addr_bytes[2], addr->addr_bytes[3],
 869                             addr->addr_bytes[4], addr->addr_bytes[5]);
 870                 return;
 871         }
 872
 873         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 874         list->vsi_id = vf->vsi_res->vsi_id;
 875         list->num_elements = 1;
 876         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 877                                         sizeof(addr->addr_bytes));
 878
 879         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 880         args.in_args = cmd_buffer;
 881         args.in_args_size = sizeof(cmd_buffer);
 882         args.out_buffer = vf->aq_resp;
 883         args.out_size = I40E_AQ_BUF_SZ;
 884         err = i40evf_execute_vf_cmd(dev, &args);
 885         if (err)
 886                 PMD_DRV_LOG(ERR, "fail to execute command "
 887                             "OP_ADD_ETHER_ADDRESS");
 888
 889         return;
 890 }
 891
 892 static void
 893 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 894 {
 895         struct i40e_virtchnl_ether_addr_list *list;
 896         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 897         struct rte_eth_dev_data *data = dev->data;
 898         struct ether_addr *addr;
 899         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 900                         sizeof(struct i40e_virtchnl_ether_addr)];
 901         int err;
 902         struct vf_cmd_info args;
 903
 904         addr = &(data->mac_addrs[index]);
 905
 906         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 907                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 908                             addr->addr_bytes[0], addr->addr_bytes[1],
 909                             addr->addr_bytes[2], addr->addr_bytes[3],
 910                             addr->addr_bytes[4], addr->addr_bytes[5]);
 911                 return;
 912         }
 913
 914         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 915         list->vsi_id = vf->vsi_res->vsi_id;
 916         list->num_elements = 1;
 917         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 918                         sizeof(addr->addr_bytes));
 919
 920         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 921         args.in_args = cmd_buffer;
 922         args.in_args_size = sizeof(cmd_buffer);
 923         args.out_buffer = vf->aq_resp;
 924         args.out_size = I40E_AQ_BUF_SZ;
 925         err = i40evf_execute_vf_cmd(dev, &args);
 926         if (err)
 927                 PMD_DRV_LOG(ERR, "fail to execute command "
 928                             "OP_DEL_ETHER_ADDRESS");
 929         return;
 930 }
 931
 932 static int
 933 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 934 {
 935         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 936         struct i40e_virtchnl_queue_select q_stats;
 937         int err;
 938         struct vf_cmd_info args;
 939
 940         memset(&q_stats, 0, sizeof(q_stats));
 941         q_stats.vsi_id = vf->vsi_res->vsi_id;
 942         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 943         args.in_args = (u8 *)&q_stats;
 944         args.in_args_size = sizeof(q_stats);
 945         args.out_buffer = vf->aq_resp;
 946         args.out_size = I40E_AQ_BUF_SZ;
 947
 948         err = i40evf_execute_vf_cmd(dev, &args);
 949         if (err) {
 950                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 951                 *pstats = NULL;
 952                 return err;
 953         }
 954         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 955         return 0;
 956 }
 957
 958 static int
 959 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 960 {
 961         int ret;
 962         struct i40e_eth_stats *pstats = NULL;
 963
 964         ret = i40evf_update_stats(dev, &pstats);
 965         if (ret != 0)
 966                 return 0;
 967
 968         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 969                                                 pstats->rx_broadcast;
 970         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 971                                                 pstats->tx_unicast;
 972         stats->ierrors = pstats->rx_discards;
 973         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 974         stats->ibytes = pstats->rx_bytes;
 975         stats->obytes = pstats->tx_bytes;
 976
 977         return 0;
 978 }
 979
 980 static void
 981 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 982 {
 983         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 984         struct i40e_eth_stats *pstats = NULL;
 985
 986         /* read stat values to clear hardware registers */
 987         i40evf_update_stats(dev, &pstats);
 988
 989         /* set stats offset base on current values */
 990         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 991 }
 992
 993 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 994                                       struct rte_eth_xstat_name *xstats_names,
 995                                       __rte_unused unsigned limit)
 996 {
 997         unsigned i;
 998
 999         if (xstats_names != NULL)
1000                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1001                         snprintf(xstats_names[i].name,
1002                                 sizeof(xstats_names[i].name),
1003                                 "%s", rte_i40evf_stats_strings[i].name);
1004                 }
1005         return I40EVF_NB_XSTATS;
1006 }
1007
1008 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1009                                  struct rte_eth_xstat *xstats, unsigned n)
1010 {
1011         int ret;
1012         unsigned i;
1013         struct i40e_eth_stats *pstats = NULL;
1014
1015         if (n < I40EVF_NB_XSTATS)
1016                 return I40EVF_NB_XSTATS;
1017
1018         ret = i40evf_update_stats(dev, &pstats);
1019         if (ret != 0)
1020                 return 0;
1021
1022         if (!xstats)
1023                 return 0;
1024
1025         /* loop over xstats array and values from pstats */
1026         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1027                 xstats[i].id = i;
1028                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1029                         rte_i40evf_stats_strings[i].offset);
1030         }
1031
1032         return I40EVF_NB_XSTATS;
1033 }
1034
1035 static int
1036 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1037 {
1038         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1039         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1040         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1041                                                         sizeof(uint16_t)];
1042         int err;
1043         struct vf_cmd_info args;
1044
1045         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1046         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1047         vlan_list->num_elements = 1;
1048         vlan_list->vlan_id[0] = vlanid;
1049
1050         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1051         args.in_args = (u8 *)&cmd_buffer;
1052         args.in_args_size = sizeof(cmd_buffer);
1053         args.out_buffer = vf->aq_resp;
1054         args.out_size = I40E_AQ_BUF_SZ;
1055         err = i40evf_execute_vf_cmd(dev, &args);
1056         if (err)
1057                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1058
1059         return err;
1060 }
1061
1062 static int
1063 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1064 {
1065         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1066         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1067         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1068                                                         sizeof(uint16_t)];
1069         int err;
1070         struct vf_cmd_info args;
1071
1072         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1073         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1074         vlan_list->num_elements = 1;
1075         vlan_list->vlan_id[0] = vlanid;
1076
1077         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1078         args.in_args = (u8 *)&cmd_buffer;
1079         args.in_args_size = sizeof(cmd_buffer);
1080         args.out_buffer = vf->aq_resp;
1081         args.out_size = I40E_AQ_BUF_SZ;
1082         err = i40evf_execute_vf_cmd(dev, &args);
1083         if (err)
1084                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1085
1086         return err;
1087 }
1088
1089 static const struct rte_pci_id pci_id_i40evf_map[] = {
1090         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1091         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1092         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1093         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1094         { .vendor_id = 0, /* sentinel */ },
1095 };
1096
1097 static inline int
1098 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1099                                     struct rte_eth_link *link)
1100 {
1101         struct rte_eth_link *dst = &(dev->data->dev_link);
1102         struct rte_eth_link *src = link;
1103
1104         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1105                                         *(uint64_t *)src) == 0)
1106                 return -1;
1107
1108         return 0;
1109 }
1110
1111 /* Disable IRQ0 */
1112 static inline void
1113 i40evf_disable_irq0(struct i40e_hw *hw)
1114 {
1115         /* Disable all interrupt types */
1116         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1117         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1118                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1119         I40EVF_WRITE_FLUSH(hw);
1120 }
1121
1122 /* Enable IRQ0 */
1123 static inline void
1124 i40evf_enable_irq0(struct i40e_hw *hw)
1125 {
1126         /* Enable admin queue interrupt trigger */
1127         uint32_t val;
1128
1129         i40evf_disable_irq0(hw);
1130         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1131         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1132                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1133         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1134
1135         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1136                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1137                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1138                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1139
1140         I40EVF_WRITE_FLUSH(hw);
1141 }
1142
1143 static int
1144 i40evf_reset_vf(struct i40e_hw *hw)
1145 {
1146         int i, reset;
1147
1148         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1150                 return -1;
1151         }
1152         /**
1153           * After issuing vf reset command to pf, pf won't necessarily
1154           * reset vf, it depends on what state it exactly is. If it's not
1155           * initialized yet, it won't have vf reset since it's in a certain
1156           * state. If not, it will try to reset. Even vf is reset, pf will
1157           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1158           * it to ACTIVE. In this duration, vf may not catch the moment that
1159           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1160           */
1161         rte_delay_ms(200);
1162
1163         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1164                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1165                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1166                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1167                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1168                         break;
1169                 else
1170                         rte_delay_ms(50);
1171         }
1172
1173         if (i >= MAX_RESET_WAIT_CNT) {
1174                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1175                 return -1;
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int
1182 i40evf_init_vf(struct rte_eth_dev *dev)
1183 {
1184         int i, err, bufsz;
1185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1187         struct ether_addr *p_mac_addr;
1188         uint16_t interval =
1189                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1190
1191         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1192         vf->dev_data = dev->data;
1193         err = i40e_set_mac_type(hw);
1194         if (err) {
1195                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1196                 goto err;
1197         }
1198
1199         i40e_init_adminq_parameter(hw);
1200         err = i40e_init_adminq(hw);
1201         if (err) {
1202                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1203                 goto err;
1204         }
1205
1206         /* Reset VF and wait until it's complete */
1207         if (i40evf_reset_vf(hw)) {
1208                 PMD_INIT_LOG(ERR, "reset NIC failed");
1209                 goto err_aq;
1210         }
1211
1212         /* VF reset, shutdown admin queue and initialize again */
1213         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1215                 return -1;
1216         }
1217
1218         i40e_init_adminq_parameter(hw);
1219         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR, "init_adminq failed");
1221                 return -1;
1222         }
1223         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1224         if (!vf->aq_resp) {
1225                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1226                         goto err_aq;
1227         }
1228         if (i40evf_check_api_version(dev) != 0) {
1229                 PMD_INIT_LOG(ERR, "check_api version failed");
1230                 goto err_aq;
1231         }
1232         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1233                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1234         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1235         if (!vf->vf_res) {
1236                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1237                         goto err_aq;
1238         }
1239
1240         if (i40evf_get_vf_resource(dev) != 0) {
1241                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1242                 goto err_alloc;
1243         }
1244
1245         /* got VF config message back from PF, now we can parse it */
1246         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1247                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1248                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1249         }
1250
1251         if (!vf->vsi_res) {
1252                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1253                 goto err_alloc;
1254         }
1255
1256         if (hw->mac.type == I40E_MAC_X722_VF)
1257                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1258         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1259         vf->vsi.type = vf->vsi_res->vsi_type;
1260         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1261         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1262
1263         /* Store the MAC address configured by host, or generate random one */
1264         p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1265         if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1266                 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1267         else
1268                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1269
1270         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1271         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1272                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1273                                (I40E_ITR_INDEX_DEFAULT <<
1274                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1275                                (interval <<
1276                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1277                 I40EVF_WRITE_FLUSH(hw);
1278         }
1279
1280         return 0;
1281
1282 err_alloc:
1283         rte_free(vf->vf_res);
1284 err_aq:
1285         i40e_shutdown_adminq(hw); /* ignore error */
1286 err:
1287         return -1;
1288 }
1289
1290 static int
1291 i40evf_uninit_vf(struct rte_eth_dev *dev)
1292 {
1293         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (hw->adapter_stopped == 0)
1299                 i40evf_dev_close(dev);
1300         rte_free(vf->vf_res);
1301         vf->vf_res = NULL;
1302         rte_free(vf->aq_resp);
1303         vf->aq_resp = NULL;
1304
1305         return 0;
1306 }
1307
1308 static void
1309 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1310                            uint8_t *msg,
1311                            __rte_unused uint16_t msglen)
1312 {
1313         struct i40e_virtchnl_pf_event *pf_msg =
1314                         (struct i40e_virtchnl_pf_event *)msg;
1315         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1316
1317         switch (pf_msg->event) {
1318         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1319                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1320                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1321                 break;
1322         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1323                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1324                 vf->link_up = pf_msg->event_data.link_event.link_status;
1325                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1326                 break;
1327         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1328                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1329                 break;
1330         default:
1331                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1332                 break;
1333         }
1334 }
1335
1336 static void
1337 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1338 {
1339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1341         struct i40e_arq_event_info info;
1342         uint16_t pending, aq_opc;
1343         enum i40e_virtchnl_ops msg_opc;
1344         enum i40e_status_code msg_ret;
1345         int ret;
1346
1347         info.buf_len = I40E_AQ_BUF_SZ;
1348         if (!vf->aq_resp) {
1349                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1350                 return;
1351         }
1352         info.msg_buf = vf->aq_resp;
1353
1354         pending = 1;
1355         while (pending) {
1356                 ret = i40e_clean_arq_element(hw, &info, &pending);
1357
1358                 if (ret != I40E_SUCCESS) {
1359                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1360                                     "ret: %d", ret);
1361                         break;
1362                 }
1363                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1364                 /* For the message sent from pf to vf, opcode is stored in
1365                  * cookie_high of struct i40e_aq_desc, while return error code
1366                  * are stored in cookie_low, Which is done by
1367                  * i40e_aq_send_msg_to_vf in PF driver.*/
1368                 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1369                                                   info.desc.cookie_high);
1370                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1371                                                   info.desc.cookie_low);
1372                 switch (aq_opc) {
1373                 case i40e_aqc_opc_send_msg_to_vf:
1374                         if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1375                                 /* process event*/
1376                                 i40evf_handle_pf_event(dev, info.msg_buf,
1377                                                        info.msg_len);
1378                         else {
1379                                 /* read message and it's expected one */
1380                                 if (msg_opc == vf->pend_cmd) {
1381                                         vf->cmd_retval = msg_ret;
1382                                         /* prevent compiler reordering */
1383                                         rte_compiler_barrier();
1384                                         _clear_cmd(vf);
1385                                 } else
1386                                         PMD_DRV_LOG(ERR, "command mismatch,"
1387                                                 "expect %u, get %u",
1388                                                 vf->pend_cmd, msg_opc);
1389                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1390                                              " opcode = %d\n", msg_opc);
1391                         }
1392                         break;
1393                 default:
1394                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1395                                     aq_opc);
1396                         break;
1397                 }
1398         }
1399 }
1400
1401 /**
1402  * Interrupt handler triggered by NIC  for handling
1403  * specific interrupt. Only adminq interrupt is processed in VF.
1404  *
1405  * @param handle
1406  *  Pointer to interrupt handle.
1407  * @param param
1408  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1409  *
1410  * @return
1411  *  void
1412  */
1413 static void
1414 i40evf_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
1415                              void *param)
1416 {
1417         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         uint32_t icr0;
1420
1421         i40evf_disable_irq0(hw);
1422
1423         /* read out interrupt causes */
1424         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1425
1426         /* No interrupt event indicated */
1427         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1428                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1429                 goto done;
1430         }
1431
1432         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1433                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1434                 i40evf_handle_aq_msg(dev);
1435         }
1436
1437         /* Link Status Change interrupt */
1438         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1439                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1440                                    " do nothing\n");
1441
1442 done:
1443         i40evf_enable_irq0(hw);
1444         rte_intr_enable(intr_handle);
1445 }
1446
1447 static int
1448 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1449 {
1450         struct i40e_hw *hw
1451                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1452         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(eth_dev);
1453
1454         PMD_INIT_FUNC_TRACE();
1455
1456         /* assign ops func pointer */
1457         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1458         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1459         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1460
1461         /*
1462          * For secondary processes, we don't initialise any further as primary
1463          * has already done this work.
1464          */
1465         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1466                 i40e_set_rx_function(eth_dev);
1467                 i40e_set_tx_function(eth_dev);
1468                 return 0;
1469         }
1470
1471         rte_eth_copy_pci_info(eth_dev, pci_dev);
1472         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1473
1474         hw->vendor_id = pci_dev->id.vendor_id;
1475         hw->device_id = pci_dev->id.device_id;
1476         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1477         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1478         hw->bus.device = pci_dev->addr.devid;
1479         hw->bus.func = pci_dev->addr.function;
1480         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1481         hw->adapter_stopped = 0;
1482
1483         if(i40evf_init_vf(eth_dev) != 0) {
1484                 PMD_INIT_LOG(ERR, "Init vf failed");
1485                 return -1;
1486         }
1487
1488         /* register callback func to eal lib */
1489         rte_intr_callback_register(&pci_dev->intr_handle,
1490                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1491
1492         /* enable uio intr after callback register */
1493         rte_intr_enable(&pci_dev->intr_handle);
1494
1495         /* configure and enable device interrupt */
1496         i40evf_enable_irq0(hw);
1497
1498         /* copy mac addr */
1499         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1500                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1501                                         0);
1502         if (eth_dev->data->mac_addrs == NULL) {
1503                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1504                                 " store MAC addresses",
1505                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1506                 return -ENOMEM;
1507         }
1508         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1509                         &eth_dev->data->mac_addrs[0]);
1510
1511         return 0;
1512 }
1513
1514 static int
1515 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1516 {
1517         PMD_INIT_FUNC_TRACE();
1518
1519         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1520                 return -EPERM;
1521
1522         eth_dev->dev_ops = NULL;
1523         eth_dev->rx_pkt_burst = NULL;
1524         eth_dev->tx_pkt_burst = NULL;
1525
1526         if (i40evf_uninit_vf(eth_dev) != 0) {
1527                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1528                 return -1;
1529         }
1530
1531         rte_free(eth_dev->data->mac_addrs);
1532         eth_dev->data->mac_addrs = NULL;
1533
1534         return 0;
1535 }
1536 /*
1537  * virtual function driver struct
1538  */
1539 static struct eth_driver rte_i40evf_pmd = {
1540         .pci_drv = {
1541                 .id_table = pci_id_i40evf_map,
1542                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1543                 .probe = rte_eth_dev_pci_probe,
1544                 .remove = rte_eth_dev_pci_remove,
1545         },
1546         .eth_dev_init = i40evf_dev_init,
1547         .eth_dev_uninit = i40evf_dev_uninit,
1548         .dev_private_size = sizeof(struct i40e_adapter),
1549 };
1550
1551 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1552 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1553 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1554
1555 static int
1556 i40evf_dev_configure(struct rte_eth_dev *dev)
1557 {
1558         struct i40e_adapter *ad =
1559                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1560         struct rte_eth_conf *conf = &dev->data->dev_conf;
1561         struct i40e_vf *vf;
1562
1563         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1564          * allocation or vector Rx preconditions we will reset it.
1565          */
1566         ad->rx_bulk_alloc_allowed = true;
1567         ad->rx_vec_allowed = true;
1568         ad->tx_simple_allowed = true;
1569         ad->tx_vec_allowed = true;
1570
1571         /* For non-DPDK PF drivers, VF has no ability to disable HW
1572          * CRC strip, and is implicitly enabled by the PF.
1573          */
1574         if (!conf->rxmode.hw_strip_crc) {
1575                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1576                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1577                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1578                         /* Peer is running non-DPDK PF driver. */
1579                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1580                         return -EINVAL;
1581                 }
1582         }
1583
1584         return i40evf_init_vlan(dev);
1585 }
1586
1587 static int
1588 i40evf_init_vlan(struct rte_eth_dev *dev)
1589 {
1590         struct rte_eth_dev_data *data = dev->data;
1591         int ret;
1592
1593         /* Apply vlan offload setting */
1594         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1595
1596         /* Apply pvid setting */
1597         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1598                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1599         return ret;
1600 }
1601
1602 static void
1603 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1604 {
1605         bool enable_vlan_strip = 0;
1606         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1607         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1608
1609         /* Linux pf host doesn't support vlan offload yet */
1610         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1611                 /* Vlan stripping setting */
1612                 if (mask & ETH_VLAN_STRIP_MASK) {
1613                         /* Enable or disable VLAN stripping */
1614                         if (dev_conf->rxmode.hw_vlan_strip)
1615                                 enable_vlan_strip = 1;
1616                         else
1617                                 enable_vlan_strip = 0;
1618
1619                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1620                 }
1621         }
1622 }
1623
1624 static int
1625 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1626 {
1627         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1628         struct i40e_vsi_vlan_pvid_info info;
1629         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1630
1631         memset(&info, 0, sizeof(info));
1632         info.on = on;
1633
1634         /* Linux pf host don't support vlan offload yet */
1635         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1636                 if (info.on)
1637                         info.config.pvid = pvid;
1638                 else {
1639                         info.config.reject.tagged =
1640                                 dev_conf->txmode.hw_vlan_reject_tagged;
1641                         info.config.reject.untagged =
1642                                 dev_conf->txmode.hw_vlan_reject_untagged;
1643                 }
1644                 return i40evf_config_vlan_pvid(dev, &info);
1645         }
1646
1647         return 0;
1648 }
1649
1650 static int
1651 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1652 {
1653         struct i40e_rx_queue *rxq;
1654         int err = 0;
1655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656
1657         PMD_INIT_FUNC_TRACE();
1658
1659         if (rx_queue_id < dev->data->nb_rx_queues) {
1660                 rxq = dev->data->rx_queues[rx_queue_id];
1661
1662                 err = i40e_alloc_rx_queue_mbufs(rxq);
1663                 if (err) {
1664                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1665                         return err;
1666                 }
1667
1668                 rte_wmb();
1669
1670                 /* Init the RX tail register. */
1671                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1672                 I40EVF_WRITE_FLUSH(hw);
1673
1674                 /* Ready to switch the queue on */
1675                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1676
1677                 if (err)
1678                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1679                                     rx_queue_id);
1680                 else
1681                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1682         }
1683
1684         return err;
1685 }
1686
1687 static int
1688 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1689 {
1690         struct i40e_rx_queue *rxq;
1691         int err;
1692
1693         if (rx_queue_id < dev->data->nb_rx_queues) {
1694                 rxq = dev->data->rx_queues[rx_queue_id];
1695
1696                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1697
1698                 if (err) {
1699                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1700                                     rx_queue_id);
1701                         return err;
1702                 }
1703
1704                 i40e_rx_queue_release_mbufs(rxq);
1705                 i40e_reset_rx_queue(rxq);
1706                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int
1713 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1714 {
1715         int err = 0;
1716
1717         PMD_INIT_FUNC_TRACE();
1718
1719         if (tx_queue_id < dev->data->nb_tx_queues) {
1720
1721                 /* Ready to switch the queue on */
1722                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1723
1724                 if (err)
1725                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1726                                     tx_queue_id);
1727                 else
1728                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1729         }
1730
1731         return err;
1732 }
1733
1734 static int
1735 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1736 {
1737         struct i40e_tx_queue *txq;
1738         int err;
1739
1740         if (tx_queue_id < dev->data->nb_tx_queues) {
1741                 txq = dev->data->tx_queues[tx_queue_id];
1742
1743                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1744
1745                 if (err) {
1746                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1747                                     tx_queue_id);
1748                         return err;
1749                 }
1750
1751                 i40e_tx_queue_release_mbufs(txq);
1752                 i40e_reset_tx_queue(txq);
1753                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int
1760 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1761 {
1762         int ret;
1763
1764         if (on)
1765                 ret = i40evf_add_vlan(dev, vlan_id);
1766         else
1767                 ret = i40evf_del_vlan(dev,vlan_id);
1768
1769         return ret;
1770 }
1771
1772 static int
1773 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1774 {
1775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         struct rte_eth_dev_data *dev_data = dev->data;
1777         struct rte_pktmbuf_pool_private *mbp_priv;
1778         uint16_t buf_size, len;
1779
1780         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1781         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1782         I40EVF_WRITE_FLUSH(hw);
1783
1784         /* Calculate the maximum packet length allowed */
1785         mbp_priv = rte_mempool_get_priv(rxq->mp);
1786         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1787                                         RTE_PKTMBUF_HEADROOM);
1788         rxq->hs_mode = i40e_header_split_none;
1789         rxq->rx_hdr_len = 0;
1790         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1791         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1792         rxq->max_pkt_len = RTE_MIN(len,
1793                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1794
1795         /**
1796          * Check if the jumbo frame and maximum packet length are set correctly
1797          */
1798         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1799                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1800                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1801                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1802                                 "larger than %u and smaller than %u, as jumbo "
1803                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1804                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1805                         return I40E_ERR_CONFIG;
1806                 }
1807         } else {
1808                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1809                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1810                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1811                                 "larger than %u and smaller than %u, as jumbo "
1812                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1813                                                 (uint32_t)ETHER_MAX_LEN);
1814                         return I40E_ERR_CONFIG;
1815                 }
1816         }
1817
1818         if (dev_data->dev_conf.rxmode.enable_scatter ||
1819             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1820                 dev_data->scattered_rx = 1;
1821         }
1822
1823         return 0;
1824 }
1825
1826 static int
1827 i40evf_rx_init(struct rte_eth_dev *dev)
1828 {
1829         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1830         uint16_t i;
1831         int ret = I40E_SUCCESS;
1832         struct i40e_rx_queue **rxq =
1833                 (struct i40e_rx_queue **)dev->data->rx_queues;
1834
1835         i40evf_config_rss(vf);
1836         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1837                 if (!rxq[i] || !rxq[i]->q_set)
1838                         continue;
1839                 ret = i40evf_rxq_init(dev, rxq[i]);
1840                 if (ret != I40E_SUCCESS)
1841                         break;
1842         }
1843         if (ret == I40E_SUCCESS)
1844                 i40e_set_rx_function(dev);
1845
1846         return ret;
1847 }
1848
1849 static void
1850 i40evf_tx_init(struct rte_eth_dev *dev)
1851 {
1852         uint16_t i;
1853         struct i40e_tx_queue **txq =
1854                 (struct i40e_tx_queue **)dev->data->tx_queues;
1855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856
1857         for (i = 0; i < dev->data->nb_tx_queues; i++)
1858                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1859
1860         i40e_set_tx_function(dev);
1861 }
1862
1863 static inline void
1864 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1865 {
1866         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1869         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1870
1871         if (!rte_intr_allow_others(intr_handle)) {
1872                 I40E_WRITE_REG(hw,
1873                                I40E_VFINT_DYN_CTL01,
1874                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1875                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1876                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1877                 I40EVF_WRITE_FLUSH(hw);
1878                 return;
1879         }
1880
1881         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1882                 /* To support DPDK PF host */
1883                 I40E_WRITE_REG(hw,
1884                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1885                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1886                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1887         /* If host driver is kernel driver, do nothing.
1888          * Interrupt 0 is used for rx packets, but don't set
1889          * I40E_VFINT_DYN_CTL01,
1890          * because it is already done in i40evf_enable_irq0.
1891          */
1892
1893         I40EVF_WRITE_FLUSH(hw);
1894 }
1895
1896 static inline void
1897 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1902         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1903
1904         if (!rte_intr_allow_others(intr_handle)) {
1905                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1906                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1907                 I40EVF_WRITE_FLUSH(hw);
1908                 return;
1909         }
1910
1911         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1912                 I40E_WRITE_REG(hw,
1913                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1914                                                     - 1),
1915                                0);
1916         /* If host driver is kernel driver, do nothing.
1917          * Interrupt 0 is used for rx packets, but don't zero
1918          * I40E_VFINT_DYN_CTL01,
1919          * because interrupt 0 is also used for adminq processing.
1920          */
1921
1922         I40EVF_WRITE_FLUSH(hw);
1923 }
1924
1925 static int
1926 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1927 {
1928         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1929         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         uint16_t interval =
1932                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1933         uint16_t msix_intr;
1934
1935         msix_intr = intr_handle->intr_vec[queue_id];
1936         if (msix_intr == I40E_MISC_VEC_ID)
1937                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1938                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1939                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1940                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1941                                (interval <<
1942                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1943         else
1944                 I40E_WRITE_REG(hw,
1945                                I40E_VFINT_DYN_CTLN1(msix_intr -
1946                                                     I40E_RX_VEC_START),
1947                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1948                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1949                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1950                                (interval <<
1951                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1952
1953         I40EVF_WRITE_FLUSH(hw);
1954
1955         rte_intr_enable(&pci_dev->intr_handle);
1956
1957         return 0;
1958 }
1959
1960 static int
1961 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1962 {
1963         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1964         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966         uint16_t msix_intr;
1967
1968         msix_intr = intr_handle->intr_vec[queue_id];
1969         if (msix_intr == I40E_MISC_VEC_ID)
1970                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1971         else
1972                 I40E_WRITE_REG(hw,
1973                                I40E_VFINT_DYN_CTLN1(msix_intr -
1974                                                     I40E_RX_VEC_START),
1975                                0);
1976
1977         I40EVF_WRITE_FLUSH(hw);
1978
1979         return 0;
1980 }
1981
1982 static void
1983 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1984 {
1985         struct i40e_virtchnl_ether_addr_list *list;
1986         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1987         int err, i, j;
1988         int next_begin = 0;
1989         int begin = 0;
1990         uint32_t len;
1991         struct ether_addr *addr;
1992         struct vf_cmd_info args;
1993
1994         do {
1995                 j = 0;
1996                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1997                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1998                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1999                                 continue;
2000                         len += sizeof(struct i40e_virtchnl_ether_addr);
2001                         if (len >= I40E_AQ_BUF_SZ) {
2002                                 next_begin = i + 1;
2003                                 break;
2004                         }
2005                 }
2006
2007                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2008
2009                 for (i = begin; i < next_begin; i++) {
2010                         addr = &dev->data->mac_addrs[i];
2011                         if (is_zero_ether_addr(addr))
2012                                 continue;
2013                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2014                                          sizeof(addr->addr_bytes));
2015                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2016                                     addr->addr_bytes[0], addr->addr_bytes[1],
2017                                     addr->addr_bytes[2], addr->addr_bytes[3],
2018                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2019                         j++;
2020                 }
2021                 list->vsi_id = vf->vsi_res->vsi_id;
2022                 list->num_elements = j;
2023                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2024                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2025                 args.in_args = (uint8_t *)list;
2026                 args.in_args_size = len;
2027                 args.out_buffer = vf->aq_resp;
2028                 args.out_size = I40E_AQ_BUF_SZ;
2029                 err = i40evf_execute_vf_cmd(dev, &args);
2030                 if (err)
2031                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2032                                     add ? "OP_ADD_ETHER_ADDRESS" :
2033                                     "OP_DEL_ETHER_ADDRESS");
2034                 rte_free(list);
2035                 begin = next_begin;
2036         } while (begin < I40E_NUM_MACADDR_MAX);
2037 }
2038
2039 static int
2040 i40evf_dev_start(struct rte_eth_dev *dev)
2041 {
2042         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2044         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2045         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2046         uint32_t intr_vector = 0;
2047
2048         PMD_INIT_FUNC_TRACE();
2049
2050         hw->adapter_stopped = 0;
2051
2052         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2053         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2054                                         dev->data->nb_tx_queues);
2055
2056         /* check and configure queue intr-vector mapping */
2057         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2058                 intr_vector = dev->data->nb_rx_queues;
2059                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2060                         return -1;
2061         }
2062
2063         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2064                 intr_handle->intr_vec =
2065                         rte_zmalloc("intr_vec",
2066                                     dev->data->nb_rx_queues * sizeof(int), 0);
2067                 if (!intr_handle->intr_vec) {
2068                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2069                                      " intr_vec\n", dev->data->nb_rx_queues);
2070                         return -ENOMEM;
2071                 }
2072         }
2073
2074         if (i40evf_rx_init(dev) != 0){
2075                 PMD_DRV_LOG(ERR, "failed to do RX init");
2076                 return -1;
2077         }
2078
2079         i40evf_tx_init(dev);
2080
2081         if (i40evf_configure_queues(dev) != 0) {
2082                 PMD_DRV_LOG(ERR, "configure queues failed");
2083                 goto err_queue;
2084         }
2085         if (i40evf_config_irq_map(dev)) {
2086                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2087                 goto err_queue;
2088         }
2089
2090         /* Set all mac addrs */
2091         i40evf_add_del_all_mac_addr(dev, TRUE);
2092
2093         if (i40evf_start_queues(dev) != 0) {
2094                 PMD_DRV_LOG(ERR, "enable queues failed");
2095                 goto err_mac;
2096         }
2097
2098         i40evf_enable_queues_intr(dev);
2099         return 0;
2100
2101 err_mac:
2102         i40evf_add_del_all_mac_addr(dev, FALSE);
2103 err_queue:
2104         return -1;
2105 }
2106
2107 static void
2108 i40evf_dev_stop(struct rte_eth_dev *dev)
2109 {
2110         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2111         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         i40evf_stop_queues(dev);
2116         i40evf_disable_queues_intr(dev);
2117         i40e_dev_clear_queues(dev);
2118
2119         /* Clean datapath event and queue/vec mapping */
2120         rte_intr_efd_disable(intr_handle);
2121         if (intr_handle->intr_vec) {
2122                 rte_free(intr_handle->intr_vec);
2123                 intr_handle->intr_vec = NULL;
2124         }
2125         /* remove all mac addrs */
2126         i40evf_add_del_all_mac_addr(dev, FALSE);
2127
2128 }
2129
2130 static int
2131 i40evf_dev_link_update(struct rte_eth_dev *dev,
2132                        __rte_unused int wait_to_complete)
2133 {
2134         struct rte_eth_link new_link;
2135         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2136         /*
2137          * DPDK pf host provide interfacet to acquire link status
2138          * while Linux driver does not
2139          */
2140
2141         /* Linux driver PF host */
2142         switch (vf->link_speed) {
2143         case I40E_LINK_SPEED_100MB:
2144                 new_link.link_speed = ETH_SPEED_NUM_100M;
2145                 break;
2146         case I40E_LINK_SPEED_1GB:
2147                 new_link.link_speed = ETH_SPEED_NUM_1G;
2148                 break;
2149         case I40E_LINK_SPEED_10GB:
2150                 new_link.link_speed = ETH_SPEED_NUM_10G;
2151                 break;
2152         case I40E_LINK_SPEED_20GB:
2153                 new_link.link_speed = ETH_SPEED_NUM_20G;
2154                 break;
2155         case I40E_LINK_SPEED_40GB:
2156                 new_link.link_speed = ETH_SPEED_NUM_40G;
2157                 break;
2158         default:
2159                 new_link.link_speed = ETH_SPEED_NUM_100M;
2160                 break;
2161         }
2162         /* full duplex only */
2163         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2164         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2165                                              ETH_LINK_DOWN;
2166
2167         i40evf_dev_atomic_write_link_status(dev, &new_link);
2168
2169         return 0;
2170 }
2171
2172 static void
2173 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2174 {
2175         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2176         int ret;
2177
2178         /* If enabled, just return */
2179         if (vf->promisc_unicast_enabled)
2180                 return;
2181
2182         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2183         if (ret == 0)
2184                 vf->promisc_unicast_enabled = TRUE;
2185 }
2186
2187 static void
2188 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2189 {
2190         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2191         int ret;
2192
2193         /* If disabled, just return */
2194         if (!vf->promisc_unicast_enabled)
2195                 return;
2196
2197         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2198         if (ret == 0)
2199                 vf->promisc_unicast_enabled = FALSE;
2200 }
2201
2202 static void
2203 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2204 {
2205         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2206         int ret;
2207
2208         /* If enabled, just return */
2209         if (vf->promisc_multicast_enabled)
2210                 return;
2211
2212         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2213         if (ret == 0)
2214                 vf->promisc_multicast_enabled = TRUE;
2215 }
2216
2217 static void
2218 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2219 {
2220         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2221         int ret;
2222
2223         /* If enabled, just return */
2224         if (!vf->promisc_multicast_enabled)
2225                 return;
2226
2227         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2228         if (ret == 0)
2229                 vf->promisc_multicast_enabled = FALSE;
2230 }
2231
2232 static void
2233 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2234 {
2235         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2236
2237         memset(dev_info, 0, sizeof(*dev_info));
2238         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2239         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2240         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2241         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2242         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2243         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2244         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2245         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2246         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2247         dev_info->rx_offload_capa =
2248                 DEV_RX_OFFLOAD_VLAN_STRIP |
2249                 DEV_RX_OFFLOAD_QINQ_STRIP |
2250                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2251                 DEV_RX_OFFLOAD_UDP_CKSUM |
2252                 DEV_RX_OFFLOAD_TCP_CKSUM;
2253         dev_info->tx_offload_capa =
2254                 DEV_TX_OFFLOAD_VLAN_INSERT |
2255                 DEV_TX_OFFLOAD_QINQ_INSERT |
2256                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2257                 DEV_TX_OFFLOAD_UDP_CKSUM |
2258                 DEV_TX_OFFLOAD_TCP_CKSUM |
2259                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2260
2261         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2262                 .rx_thresh = {
2263                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2264                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2265                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2266                 },
2267                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2268                 .rx_drop_en = 0,
2269         };
2270
2271         dev_info->default_txconf = (struct rte_eth_txconf) {
2272                 .tx_thresh = {
2273                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2274                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2275                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2276                 },
2277                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2278                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2279                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2280                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2281         };
2282
2283         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2284                 .nb_max = I40E_MAX_RING_DESC,
2285                 .nb_min = I40E_MIN_RING_DESC,
2286                 .nb_align = I40E_ALIGN_RING_DESC,
2287         };
2288
2289         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2290                 .nb_max = I40E_MAX_RING_DESC,
2291                 .nb_min = I40E_MIN_RING_DESC,
2292                 .nb_align = I40E_ALIGN_RING_DESC,
2293         };
2294 }
2295
2296 static void
2297 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2298 {
2299         if (i40evf_get_statistics(dev, stats))
2300                 PMD_DRV_LOG(ERR, "Get statistics failed");
2301 }
2302
2303 static void
2304 i40evf_dev_close(struct rte_eth_dev *dev)
2305 {
2306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2308         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2309
2310         i40evf_dev_stop(dev);
2311         hw->adapter_stopped = 1;
2312         i40e_dev_free_queues(dev);
2313         i40evf_reset_vf(hw);
2314         i40e_shutdown_adminq(hw);
2315         /* disable uio intr before callback unregister */
2316         rte_intr_disable(intr_handle);
2317
2318         /* unregister callback func from eal lib */
2319         rte_intr_callback_unregister(intr_handle,
2320                                      i40evf_dev_interrupt_handler, dev);
2321         i40evf_disable_irq0(hw);
2322 }
2323
2324 static int
2325 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2326 {
2327         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2329         int ret;
2330
2331         if (!lut)
2332                 return -EINVAL;
2333
2334         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2335                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2336                                           lut, lut_size);
2337                 if (ret) {
2338                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2339                         return ret;
2340                 }
2341         } else {
2342                 uint32_t *lut_dw = (uint32_t *)lut;
2343                 uint16_t i, lut_size_dw = lut_size / 4;
2344
2345                 for (i = 0; i < lut_size_dw; i++)
2346                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int
2353 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2354 {
2355         struct i40e_vf *vf;
2356         struct i40e_hw *hw;
2357         int ret;
2358
2359         if (!vsi || !lut)
2360                 return -EINVAL;
2361
2362         vf = I40E_VSI_TO_VF(vsi);
2363         hw = I40E_VSI_TO_HW(vsi);
2364
2365         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2366                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2367                                           lut, lut_size);
2368                 if (ret) {
2369                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2370                         return ret;
2371                 }
2372         } else {
2373                 uint32_t *lut_dw = (uint32_t *)lut;
2374                 uint16_t i, lut_size_dw = lut_size / 4;
2375
2376                 for (i = 0; i < lut_size_dw; i++)
2377                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2378                 I40EVF_WRITE_FLUSH(hw);
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int
2385 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2386                            struct rte_eth_rss_reta_entry64 *reta_conf,
2387                            uint16_t reta_size)
2388 {
2389         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2390         uint8_t *lut;
2391         uint16_t i, idx, shift;
2392         int ret;
2393
2394         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2395                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2396                         "(%d) doesn't match the number of hardware can "
2397                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2398                 return -EINVAL;
2399         }
2400
2401         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2402         if (!lut) {
2403                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2404                 return -ENOMEM;
2405         }
2406         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2407         if (ret)
2408                 goto out;
2409         for (i = 0; i < reta_size; i++) {
2410                 idx = i / RTE_RETA_GROUP_SIZE;
2411                 shift = i % RTE_RETA_GROUP_SIZE;
2412                 if (reta_conf[idx].mask & (1ULL << shift))
2413                         lut[i] = reta_conf[idx].reta[shift];
2414         }
2415         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2416
2417 out:
2418         rte_free(lut);
2419
2420         return ret;
2421 }
2422
2423 static int
2424 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2425                           struct rte_eth_rss_reta_entry64 *reta_conf,
2426                           uint16_t reta_size)
2427 {
2428         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2429         uint16_t i, idx, shift;
2430         uint8_t *lut;
2431         int ret;
2432
2433         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2434                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2435                         "(%d) doesn't match the number of hardware can "
2436                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2437                 return -EINVAL;
2438         }
2439
2440         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2441         if (!lut) {
2442                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2443                 return -ENOMEM;
2444         }
2445
2446         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2447         if (ret)
2448                 goto out;
2449         for (i = 0; i < reta_size; i++) {
2450                 idx = i / RTE_RETA_GROUP_SIZE;
2451                 shift = i % RTE_RETA_GROUP_SIZE;
2452                 if (reta_conf[idx].mask & (1ULL << shift))
2453                         reta_conf[idx].reta[shift] = lut[i];
2454         }
2455
2456 out:
2457         rte_free(lut);
2458
2459         return ret;
2460 }
2461
2462 static int
2463 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2464 {
2465         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2466         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2467         int ret = 0;
2468
2469         if (!key || key_len == 0) {
2470                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2471                 return 0;
2472         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2473                 sizeof(uint32_t)) {
2474                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2475                 return -EINVAL;
2476         }
2477
2478         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2479                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2480                         (struct i40e_aqc_get_set_rss_key_data *)key;
2481
2482                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2483                 if (ret)
2484                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2485                                      "via AQ");
2486         } else {
2487                 uint32_t *hash_key = (uint32_t *)key;
2488                 uint16_t i;
2489
2490                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2491                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2492                 I40EVF_WRITE_FLUSH(hw);
2493         }
2494
2495         return ret;
2496 }
2497
2498 static int
2499 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2500 {
2501         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2503         int ret;
2504
2505         if (!key || !key_len)
2506                 return -EINVAL;
2507
2508         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2509                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2510                         (struct i40e_aqc_get_set_rss_key_data *)key);
2511                 if (ret) {
2512                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2513                         return ret;
2514                 }
2515         } else {
2516                 uint32_t *key_dw = (uint32_t *)key;
2517                 uint16_t i;
2518
2519                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2520                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2521         }
2522         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2523
2524         return 0;
2525 }
2526
2527 static int
2528 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2529 {
2530         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2531         uint64_t rss_hf, hena;
2532         int ret;
2533
2534         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2535                                  rss_conf->rss_key_len);
2536         if (ret)
2537                 return ret;
2538
2539         rss_hf = rss_conf->rss_hf;
2540         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2541         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2542         if (hw->mac.type == I40E_MAC_X722)
2543                 hena &= ~I40E_RSS_HENA_ALL_X722;
2544         else
2545                 hena &= ~I40E_RSS_HENA_ALL;
2546         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2547         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2548         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2549         I40EVF_WRITE_FLUSH(hw);
2550
2551         return 0;
2552 }
2553
2554 static void
2555 i40evf_disable_rss(struct i40e_vf *vf)
2556 {
2557         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2558         uint64_t hena;
2559
2560         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2561         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2562         if (hw->mac.type == I40E_MAC_X722)
2563                 hena &= ~I40E_RSS_HENA_ALL_X722;
2564         else
2565                 hena &= ~I40E_RSS_HENA_ALL;
2566         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2567         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2568         I40EVF_WRITE_FLUSH(hw);
2569 }
2570
2571 static int
2572 i40evf_config_rss(struct i40e_vf *vf)
2573 {
2574         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2575         struct rte_eth_rss_conf rss_conf;
2576         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2577         uint16_t num;
2578
2579         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2580                 i40evf_disable_rss(vf);
2581                 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2582                 return 0;
2583         }
2584
2585         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2586         /* Fill out the look up table */
2587         for (i = 0, j = 0; i < nb_q; i++, j++) {
2588                 if (j >= num)
2589                         j = 0;
2590                 lut = (lut << 8) | j;
2591                 if ((i & 3) == 3)
2592                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2593         }
2594
2595         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2596         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2597                 i40evf_disable_rss(vf);
2598                 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2599                 return 0;
2600         }
2601
2602         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2603                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2604                 /* Calculate the default hash key */
2605                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2606                         rss_key_default[i] = (uint32_t)rte_rand();
2607                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2608                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2609                         sizeof(uint32_t);
2610         }
2611
2612         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2613 }
2614
2615 static int
2616 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2617                            struct rte_eth_rss_conf *rss_conf)
2618 {
2619         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2621         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2622         uint64_t hena;
2623
2624         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2625         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2626         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2627                  ? I40E_RSS_HENA_ALL_X722
2628                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2629                 if (rss_hf != 0) /* Enable RSS */
2630                         return -EINVAL;
2631                 return 0;
2632         }
2633
2634         /* RSS enabled */
2635         if (rss_hf == 0) /* Disable RSS */
2636                 return -EINVAL;
2637
2638         return i40evf_hw_rss_hash_set(vf, rss_conf);
2639 }
2640
2641 static int
2642 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2643                              struct rte_eth_rss_conf *rss_conf)
2644 {
2645         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         uint64_t hena;
2648
2649         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2650                            &rss_conf->rss_key_len);
2651
2652         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2653         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2654         rss_conf->rss_hf = i40e_parse_hena(hena);
2655
2656         return 0;
2657 }
2658
2659 static int
2660 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2661 {
2662         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2663         struct rte_eth_dev_data *dev_data = vf->dev_data;
2664         uint32_t frame_size = mtu + ETHER_HDR_LEN
2665                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
2666         int ret = 0;
2667
2668         /* check if mtu is within the allowed range */
2669         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2670                 return -EINVAL;
2671
2672         /* mtu setting is forbidden if port is start */
2673         if (dev_data->dev_started) {
2674                 PMD_DRV_LOG(ERR,
2675                             "port %d must be stopped before configuration\n",
2676                             dev_data->port_id);
2677                 return -EBUSY;
2678         }
2679
2680         if (frame_size > ETHER_MAX_LEN)
2681                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2682         else
2683                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2684
2685         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2686
2687         return ret;
2688 }