1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int i40evf_init_vlan(struct rte_eth_dev *dev);
101 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
102 uint16_t rx_queue_id);
103 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
104 uint16_t rx_queue_id);
105 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
106 uint16_t tx_queue_id);
107 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
108 uint16_t tx_queue_id);
109 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
110 struct rte_ether_addr *addr,
113 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
114 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
115 struct rte_eth_rss_reta_entry64 *reta_conf,
117 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
118 struct rte_eth_rss_reta_entry64 *reta_conf,
120 static int i40evf_config_rss(struct i40e_vf *vf);
121 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
122 struct rte_eth_rss_conf *rss_conf);
123 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
124 struct rte_eth_rss_conf *rss_conf);
125 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr);
129 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
131 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
132 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
137 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
138 struct rte_ether_addr *mc_addr_set,
139 uint32_t nb_mc_addr, bool add);
141 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
142 struct rte_ether_addr *mc_addr_set,
143 uint32_t nb_mc_addr);
145 i40evf_dev_alarm_handler(void *param);
147 /* Default hash key buffer for RSS */
148 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
150 struct rte_i40evf_xstats_name_off {
151 char name[RTE_ETH_XSTATS_NAME_SIZE];
155 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
156 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
157 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
158 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
159 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
160 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
161 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
162 rx_unknown_protocol)},
163 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
164 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
165 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
166 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
167 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
168 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
171 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
172 sizeof(rte_i40evf_stats_strings[0]))
174 static const struct eth_dev_ops i40evf_eth_dev_ops = {
175 .dev_configure = i40evf_dev_configure,
176 .dev_start = i40evf_dev_start,
177 .dev_stop = i40evf_dev_stop,
178 .promiscuous_enable = i40evf_dev_promiscuous_enable,
179 .promiscuous_disable = i40evf_dev_promiscuous_disable,
180 .allmulticast_enable = i40evf_dev_allmulticast_enable,
181 .allmulticast_disable = i40evf_dev_allmulticast_disable,
182 .link_update = i40evf_dev_link_update,
183 .stats_get = i40evf_dev_stats_get,
184 .stats_reset = i40evf_dev_xstats_reset,
185 .xstats_get = i40evf_dev_xstats_get,
186 .xstats_get_names = i40evf_dev_xstats_get_names,
187 .xstats_reset = i40evf_dev_xstats_reset,
188 .dev_close = i40evf_dev_close,
189 .dev_reset = i40evf_dev_reset,
190 .dev_infos_get = i40evf_dev_info_get,
191 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
192 .vlan_filter_set = i40evf_vlan_filter_set,
193 .vlan_offload_set = i40evf_vlan_offload_set,
194 .rx_queue_start = i40evf_dev_rx_queue_start,
195 .rx_queue_stop = i40evf_dev_rx_queue_stop,
196 .tx_queue_start = i40evf_dev_tx_queue_start,
197 .tx_queue_stop = i40evf_dev_tx_queue_stop,
198 .rx_queue_setup = i40e_dev_rx_queue_setup,
199 .rx_queue_release = i40e_dev_rx_queue_release,
200 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
201 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
202 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
203 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
204 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
205 .tx_queue_setup = i40e_dev_tx_queue_setup,
206 .tx_queue_release = i40e_dev_tx_queue_release,
207 .rx_queue_count = i40e_dev_rx_queue_count,
208 .rxq_info_get = i40e_rxq_info_get,
209 .txq_info_get = i40e_txq_info_get,
210 .mac_addr_add = i40evf_add_mac_addr,
211 .mac_addr_remove = i40evf_del_mac_addr,
212 .set_mc_addr_list = i40evf_set_mc_addr_list,
213 .reta_update = i40evf_dev_rss_reta_update,
214 .reta_query = i40evf_dev_rss_reta_query,
215 .rss_hash_update = i40evf_dev_rss_hash_update,
216 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
217 .mtu_set = i40evf_dev_mtu_set,
218 .mac_addr_set = i40evf_set_default_mac_addr,
219 .tx_done_cleanup = i40e_tx_done_cleanup,
223 * Read data in admin queue to get msg from pf driver
225 static enum i40evf_aq_result
226 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
230 struct i40e_arq_event_info event;
231 enum virtchnl_ops opcode;
232 enum i40e_status_code retval;
234 enum i40evf_aq_result result = I40EVF_MSG_NON;
236 event.buf_len = data->buf_len;
237 event.msg_buf = data->msg;
238 ret = i40e_clean_arq_element(hw, &event, NULL);
239 /* Can't read any msg from adminQ */
241 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
242 result = I40EVF_MSG_ERR;
246 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
247 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
249 if (opcode == VIRTCHNL_OP_EVENT) {
250 struct virtchnl_pf_event *vpe =
251 (struct virtchnl_pf_event *)event.msg_buf;
253 result = I40EVF_MSG_SYS;
254 switch (vpe->event) {
255 case VIRTCHNL_EVENT_LINK_CHANGE:
257 vpe->event_data.link_event.link_status;
259 vpe->event_data.link_event.link_speed;
260 vf->pend_msg |= PFMSG_LINK_CHANGE;
261 PMD_DRV_LOG(INFO, "Link status update:%s",
262 vf->link_up ? "up" : "down");
264 case VIRTCHNL_EVENT_RESET_IMPENDING:
266 vf->pend_msg |= PFMSG_RESET_IMPENDING;
267 PMD_DRV_LOG(INFO, "vf is reseting");
269 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
270 vf->dev_closed = true;
271 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
272 PMD_DRV_LOG(INFO, "PF driver closed");
275 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
276 __func__, vpe->event);
279 /* async reply msg on command issued by vf previously */
280 result = I40EVF_MSG_CMD;
281 /* Actual data length read from PF */
282 data->msg_len = event.msg_len;
285 data->result = retval;
292 * clear current command. Only call in case execute
293 * _atomic_set_cmd successfully.
296 _clear_cmd(struct i40e_vf *vf)
299 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
303 * Check there is pending cmd in execution. If none, set new command.
306 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
308 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
309 VIRTCHNL_OP_UNKNOWN, ops);
312 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
317 #define MAX_TRY_TIMES 200
318 #define ASQ_DELAY_MS 10
321 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
323 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
324 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
325 struct i40evf_arq_msg_info info;
326 enum i40evf_aq_result ret;
329 if (_atomic_set_cmd(vf, args->ops))
332 info.msg = args->out_buffer;
333 info.buf_len = args->out_size;
334 info.ops = VIRTCHNL_OP_UNKNOWN;
335 info.result = I40E_SUCCESS;
337 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
338 args->in_args, args->in_args_size, NULL);
340 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
346 case VIRTCHNL_OP_RESET_VF:
347 /*no need to process in this function */
350 case VIRTCHNL_OP_VERSION:
351 case VIRTCHNL_OP_GET_VF_RESOURCES:
352 /* for init adminq commands, need to poll the response */
355 ret = i40evf_read_pfmsg(dev, &info);
356 vf->cmd_retval = info.result;
357 if (ret == I40EVF_MSG_CMD) {
360 } else if (ret == I40EVF_MSG_ERR)
362 rte_delay_ms(ASQ_DELAY_MS);
363 /* If don't read msg or read sys event, continue */
364 } while (i++ < MAX_TRY_TIMES);
367 case VIRTCHNL_OP_REQUEST_QUEUES:
369 * ignore async reply, only wait for system message,
370 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
371 * if not, means request queues failed.
375 ret = i40evf_read_pfmsg(dev, &info);
376 vf->cmd_retval = info.result;
377 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
380 } else if (ret == I40EVF_MSG_ERR ||
381 ret == I40EVF_MSG_CMD) {
384 rte_delay_ms(ASQ_DELAY_MS);
385 /* If don't read msg or read sys event, continue */
386 } while (i++ < MAX_TRY_TIMES);
391 /* for other adminq in running time, waiting the cmd done flag */
394 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
398 rte_delay_ms(ASQ_DELAY_MS);
399 /* If don't read msg or read sys event, continue */
400 } while (i++ < MAX_TRY_TIMES);
401 /* If there's no response is received, clear command */
402 if (i >= MAX_TRY_TIMES) {
403 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
409 return err | vf->cmd_retval;
413 * Check API version with sync wait until version read or fail from admin queue
416 i40evf_check_api_version(struct rte_eth_dev *dev)
418 struct virtchnl_version_info version, *pver;
420 struct vf_cmd_info args;
421 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
423 version.major = VIRTCHNL_VERSION_MAJOR;
424 version.minor = VIRTCHNL_VERSION_MINOR;
426 args.ops = VIRTCHNL_OP_VERSION;
427 args.in_args = (uint8_t *)&version;
428 args.in_args_size = sizeof(version);
429 args.out_buffer = vf->aq_resp;
430 args.out_size = I40E_AQ_BUF_SZ;
432 err = i40evf_execute_vf_cmd(dev, &args);
434 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
438 pver = (struct virtchnl_version_info *)args.out_buffer;
439 vf->version_major = pver->major;
440 vf->version_minor = pver->minor;
441 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
442 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
443 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
445 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
446 vf->version_major, vf->version_minor,
447 VIRTCHNL_VERSION_MAJOR,
448 VIRTCHNL_VERSION_MINOR);
456 i40evf_get_vf_resource(struct rte_eth_dev *dev)
458 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
461 struct vf_cmd_info args;
464 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
465 args.out_buffer = vf->aq_resp;
466 args.out_size = I40E_AQ_BUF_SZ;
468 caps = VIRTCHNL_VF_OFFLOAD_L2 |
469 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
470 VIRTCHNL_VF_OFFLOAD_RSS_REG |
471 VIRTCHNL_VF_OFFLOAD_VLAN |
472 VIRTCHNL_VF_OFFLOAD_RX_POLLING |
473 VIRTCHNL_VF_CAP_ADV_LINK_SPEED;
474 args.in_args = (uint8_t *)∩︀
475 args.in_args_size = sizeof(caps);
478 args.in_args_size = 0;
480 err = i40evf_execute_vf_cmd(dev, &args);
483 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
487 len = sizeof(struct virtchnl_vf_resource) +
488 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
490 rte_memcpy(vf->vf_res, args.out_buffer,
491 RTE_MIN(args.out_size, len));
492 i40e_vf_parse_hw_config(hw, vf->vf_res);
498 i40evf_config_promisc(struct rte_eth_dev *dev,
500 bool enable_multicast)
502 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
504 struct vf_cmd_info args;
505 struct virtchnl_promisc_info promisc;
508 promisc.vsi_id = vf->vsi_res->vsi_id;
511 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
513 if (enable_multicast)
514 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
516 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
517 args.in_args = (uint8_t *)&promisc;
518 args.in_args_size = sizeof(promisc);
519 args.out_buffer = vf->aq_resp;
520 args.out_size = I40E_AQ_BUF_SZ;
522 err = i40evf_execute_vf_cmd(dev, &args);
525 PMD_DRV_LOG(ERR, "fail to execute command "
526 "CONFIG_PROMISCUOUS_MODE");
528 if (err == I40E_NOT_SUPPORTED)
534 vf->promisc_unicast_enabled = enable_unicast;
535 vf->promisc_multicast_enabled = enable_multicast;
540 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
542 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
543 struct vf_cmd_info args;
546 memset(&args, 0, sizeof(args));
547 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
549 args.in_args_size = 0;
550 args.out_buffer = vf->aq_resp;
551 args.out_size = I40E_AQ_BUF_SZ;
552 ret = i40evf_execute_vf_cmd(dev, &args);
554 PMD_DRV_LOG(ERR, "Failed to execute command of "
555 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
561 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
563 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
564 struct vf_cmd_info args;
567 memset(&args, 0, sizeof(args));
568 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
570 args.in_args_size = 0;
571 args.out_buffer = vf->aq_resp;
572 args.out_size = I40E_AQ_BUF_SZ;
573 ret = i40evf_execute_vf_cmd(dev, &args);
575 PMD_DRV_LOG(ERR, "Failed to execute command of "
576 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
582 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
586 struct i40e_tx_queue *txq)
588 txq_info->vsi_id = vsi_id;
589 txq_info->queue_id = queue_id;
590 if (queue_id < nb_txq && txq) {
591 txq_info->ring_len = txq->nb_tx_desc;
592 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
597 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
601 uint32_t max_pkt_size,
602 struct i40e_rx_queue *rxq)
604 rxq_info->vsi_id = vsi_id;
605 rxq_info->queue_id = queue_id;
606 rxq_info->max_pkt_size = max_pkt_size;
607 if (queue_id < nb_rxq && rxq) {
608 rxq_info->ring_len = rxq->nb_rx_desc;
609 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
610 rxq_info->databuffer_size =
611 (rte_pktmbuf_data_room_size(rxq->mp) -
612 RTE_PKTMBUF_HEADROOM);
617 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
619 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
620 struct i40e_rx_queue **rxq =
621 (struct i40e_rx_queue **)dev->data->rx_queues;
622 struct i40e_tx_queue **txq =
623 (struct i40e_tx_queue **)dev->data->tx_queues;
624 struct virtchnl_vsi_queue_config_info *vc_vqci;
625 struct virtchnl_queue_pair_info *vc_qpi;
626 struct vf_cmd_info args;
627 uint16_t i, nb_qp = vf->num_queue_pairs;
628 const uint32_t size =
629 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
633 memset(buff, 0, sizeof(buff));
634 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
635 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
636 vc_vqci->num_queue_pairs = nb_qp;
638 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
639 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
640 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
641 txq ? txq[i] : NULL);
642 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
643 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
644 vf->max_pkt_len, rxq ? rxq[i] : NULL);
646 memset(&args, 0, sizeof(args));
647 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
648 args.in_args = (uint8_t *)vc_vqci;
649 args.in_args_size = size;
650 args.out_buffer = vf->aq_resp;
651 args.out_size = I40E_AQ_BUF_SZ;
652 ret = i40evf_execute_vf_cmd(dev, &args);
654 PMD_DRV_LOG(ERR, "Failed to execute command of "
655 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
661 i40evf_config_irq_map(struct rte_eth_dev *dev)
663 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
664 struct vf_cmd_info args;
665 uint8_t *cmd_buffer = NULL;
666 struct virtchnl_irq_map_info *map_info;
667 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
668 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
669 uint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;
670 uint16_t rxq_map[vf->vf_res->max_vectors];
673 memset(rxq_map, 0, sizeof(rxq_map));
674 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
675 rte_intr_allow_others(intr_handle)) {
676 msix_base = I40E_RX_VEC_START;
677 /* For interrupt mode, available vector id is from 1. */
678 max_vectors = vf->vf_res->max_vectors - 1;
679 nb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);
682 for (i = 0; i < dev->data->nb_rx_queues; i++) {
683 rxq_map[vec] |= 1 << i;
684 intr_handle->intr_vec[i] = vec++;
685 if (vec >= vf->vf_res->max_vectors)
689 msix_base = I40E_MISC_VEC_ID;
692 for (i = 0; i < dev->data->nb_rx_queues; i++) {
693 rxq_map[msix_base] |= 1 << i;
694 if (rte_intr_dp_is_en(intr_handle))
695 intr_handle->intr_vec[i] = msix_base;
699 cmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +
700 sizeof(struct virtchnl_vector_map) * nb_msix;
701 cmd_buffer = rte_zmalloc("i40e", cmd_buffer_size, 0);
703 PMD_DRV_LOG(ERR, "Failed to allocate memory");
704 return I40E_ERR_NO_MEMORY;
707 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
708 map_info->num_vectors = nb_msix;
709 for (i = 0; i < nb_msix; i++) {
710 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
711 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
712 map_info->vecmap[i].vector_id = msix_base + i;
713 map_info->vecmap[i].txq_map = 0;
714 map_info->vecmap[i].rxq_map = rxq_map[msix_base + i];
717 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
718 args.in_args = (u8 *)cmd_buffer;
719 args.in_args_size = cmd_buffer_size;
720 args.out_buffer = vf->aq_resp;
721 args.out_size = I40E_AQ_BUF_SZ;
722 err = i40evf_execute_vf_cmd(dev, &args);
724 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
726 rte_free(cmd_buffer);
732 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
735 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
736 struct virtchnl_queue_select queue_select;
738 struct vf_cmd_info args;
739 memset(&queue_select, 0, sizeof(queue_select));
740 queue_select.vsi_id = vf->vsi_res->vsi_id;
743 queue_select.rx_queues |= 1 << qid;
745 queue_select.tx_queues |= 1 << qid;
748 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
750 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
751 args.in_args = (u8 *)&queue_select;
752 args.in_args_size = sizeof(queue_select);
753 args.out_buffer = vf->aq_resp;
754 args.out_size = I40E_AQ_BUF_SZ;
755 err = i40evf_execute_vf_cmd(dev, &args);
757 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
758 isrx ? "RX" : "TX", qid, on ? "on" : "off");
764 i40evf_start_queues(struct rte_eth_dev *dev)
766 struct rte_eth_dev_data *dev_data = dev->data;
768 struct i40e_rx_queue *rxq;
769 struct i40e_tx_queue *txq;
771 for (i = 0; i < dev->data->nb_rx_queues; i++) {
772 rxq = dev_data->rx_queues[i];
773 if (rxq->rx_deferred_start)
775 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
776 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
781 for (i = 0; i < dev->data->nb_tx_queues; i++) {
782 txq = dev_data->tx_queues[i];
783 if (txq->tx_deferred_start)
785 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
786 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
795 i40evf_stop_queues(struct rte_eth_dev *dev)
799 /* Stop TX queues first */
800 for (i = 0; i < dev->data->nb_tx_queues; i++) {
801 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
802 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
806 /* Then stop RX queues */
807 for (i = 0; i < dev->data->nb_rx_queues; i++) {
808 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
809 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
817 i40evf_add_mac_addr(struct rte_eth_dev *dev,
818 struct rte_ether_addr *addr,
819 __rte_unused uint32_t index,
820 __rte_unused uint32_t pool)
822 struct virtchnl_ether_addr_list *list;
823 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
824 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
825 sizeof(struct virtchnl_ether_addr)];
827 struct vf_cmd_info args;
829 if (rte_is_zero_ether_addr(addr)) {
830 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
831 addr->addr_bytes[0], addr->addr_bytes[1],
832 addr->addr_bytes[2], addr->addr_bytes[3],
833 addr->addr_bytes[4], addr->addr_bytes[5]);
834 return I40E_ERR_INVALID_MAC_ADDR;
837 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
838 list->vsi_id = vf->vsi_res->vsi_id;
839 list->num_elements = 1;
840 rte_memcpy(list->list[0].addr, addr->addr_bytes,
841 sizeof(addr->addr_bytes));
843 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
844 args.in_args = cmd_buffer;
845 args.in_args_size = sizeof(cmd_buffer);
846 args.out_buffer = vf->aq_resp;
847 args.out_size = I40E_AQ_BUF_SZ;
848 err = i40evf_execute_vf_cmd(dev, &args);
850 PMD_DRV_LOG(ERR, "fail to execute command "
851 "OP_ADD_ETHER_ADDRESS");
859 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
860 struct rte_ether_addr *addr)
862 struct virtchnl_ether_addr_list *list;
863 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
864 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
865 sizeof(struct virtchnl_ether_addr)];
867 struct vf_cmd_info args;
869 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
870 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
871 addr->addr_bytes[0], addr->addr_bytes[1],
872 addr->addr_bytes[2], addr->addr_bytes[3],
873 addr->addr_bytes[4], addr->addr_bytes[5]);
877 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
878 list->vsi_id = vf->vsi_res->vsi_id;
879 list->num_elements = 1;
880 rte_memcpy(list->list[0].addr, addr->addr_bytes,
881 sizeof(addr->addr_bytes));
883 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
884 args.in_args = cmd_buffer;
885 args.in_args_size = sizeof(cmd_buffer);
886 args.out_buffer = vf->aq_resp;
887 args.out_size = I40E_AQ_BUF_SZ;
888 err = i40evf_execute_vf_cmd(dev, &args);
890 PMD_DRV_LOG(ERR, "fail to execute command "
891 "OP_DEL_ETHER_ADDRESS");
898 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
900 struct rte_eth_dev_data *data = dev->data;
901 struct rte_ether_addr *addr;
903 addr = &data->mac_addrs[index];
905 i40evf_del_mac_addr_by_addr(dev, addr);
909 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
911 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
912 struct virtchnl_queue_select q_stats;
914 struct vf_cmd_info args;
916 memset(&q_stats, 0, sizeof(q_stats));
917 q_stats.vsi_id = vf->vsi_res->vsi_id;
918 args.ops = VIRTCHNL_OP_GET_STATS;
919 args.in_args = (u8 *)&q_stats;
920 args.in_args_size = sizeof(q_stats);
921 args.out_buffer = vf->aq_resp;
922 args.out_size = I40E_AQ_BUF_SZ;
924 err = i40evf_execute_vf_cmd(dev, &args);
926 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
930 *pstats = (struct i40e_eth_stats *)args.out_buffer;
935 i40evf_stat_update_48(uint64_t *offset,
938 if (*stat >= *offset)
939 *stat = *stat - *offset;
941 *stat = (uint64_t)((*stat +
942 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
944 *stat &= I40E_48_BIT_MASK;
948 i40evf_stat_update_32(uint64_t *offset,
951 if (*stat >= *offset)
952 *stat = (uint64_t)(*stat - *offset);
954 *stat = (uint64_t)((*stat +
955 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
959 i40evf_update_stats(struct i40e_vsi *vsi,
960 struct i40e_eth_stats *nes)
962 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
964 i40evf_stat_update_48(&oes->rx_bytes,
966 i40evf_stat_update_48(&oes->rx_unicast,
968 i40evf_stat_update_48(&oes->rx_multicast,
970 i40evf_stat_update_48(&oes->rx_broadcast,
972 i40evf_stat_update_32(&oes->rx_discards,
974 i40evf_stat_update_32(&oes->rx_unknown_protocol,
975 &nes->rx_unknown_protocol);
976 i40evf_stat_update_48(&oes->tx_bytes,
978 i40evf_stat_update_48(&oes->tx_unicast,
980 i40evf_stat_update_48(&oes->tx_multicast,
982 i40evf_stat_update_48(&oes->tx_broadcast,
984 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
985 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
989 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
992 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
993 struct i40e_eth_stats *pstats = NULL;
995 /* read stat values to clear hardware registers */
996 ret = i40evf_query_stats(dev, &pstats);
998 /* set stats offset base on current values */
1000 vf->vsi.eth_stats_offset = *pstats;
1005 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1006 struct rte_eth_xstat_name *xstats_names,
1007 __rte_unused unsigned limit)
1011 if (xstats_names != NULL)
1012 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1013 snprintf(xstats_names[i].name,
1014 sizeof(xstats_names[i].name),
1015 "%s", rte_i40evf_stats_strings[i].name);
1017 return I40EVF_NB_XSTATS;
1020 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1021 struct rte_eth_xstat *xstats, unsigned n)
1025 struct i40e_eth_stats *pstats = NULL;
1026 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1027 struct i40e_vsi *vsi = &vf->vsi;
1029 if (n < I40EVF_NB_XSTATS)
1030 return I40EVF_NB_XSTATS;
1032 ret = i40evf_query_stats(dev, &pstats);
1039 i40evf_update_stats(vsi, pstats);
1041 /* loop over xstats array and values from pstats */
1042 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1044 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1045 rte_i40evf_stats_strings[i].offset);
1048 return I40EVF_NB_XSTATS;
1052 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1054 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1055 struct virtchnl_vlan_filter_list *vlan_list;
1056 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1059 struct vf_cmd_info args;
1061 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1062 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1063 vlan_list->num_elements = 1;
1064 vlan_list->vlan_id[0] = vlanid;
1066 args.ops = VIRTCHNL_OP_ADD_VLAN;
1067 args.in_args = (u8 *)&cmd_buffer;
1068 args.in_args_size = sizeof(cmd_buffer);
1069 args.out_buffer = vf->aq_resp;
1070 args.out_size = I40E_AQ_BUF_SZ;
1071 err = i40evf_execute_vf_cmd(dev, &args);
1073 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1079 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1081 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1082 struct virtchnl_vf_res_request vfres;
1083 struct vf_cmd_info args;
1086 vfres.num_queue_pairs = num;
1088 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1089 args.in_args = (u8 *)&vfres;
1090 args.in_args_size = sizeof(vfres);
1091 args.out_buffer = vf->aq_resp;
1092 args.out_size = I40E_AQ_BUF_SZ;
1094 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1096 err = i40evf_execute_vf_cmd(dev, &args);
1098 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);
1100 if (err != I40E_SUCCESS) {
1101 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1105 /* The PF will issue a reset to the VF when change the number of
1106 * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then
1107 * wait 10ms and set it to ACTIVE. In this duration, vf may not catch
1108 * the moment that COMPLETE is set. So, for vf, we'll try to wait a
1113 err = i40evf_check_vf_reset_done(dev);
1115 PMD_DRV_LOG(ERR, "VF is still resetting");
1121 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1123 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1124 struct virtchnl_vlan_filter_list *vlan_list;
1125 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1128 struct vf_cmd_info args;
1130 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1131 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1132 vlan_list->num_elements = 1;
1133 vlan_list->vlan_id[0] = vlanid;
1135 args.ops = VIRTCHNL_OP_DEL_VLAN;
1136 args.in_args = (u8 *)&cmd_buffer;
1137 args.in_args_size = sizeof(cmd_buffer);
1138 args.out_buffer = vf->aq_resp;
1139 args.out_size = I40E_AQ_BUF_SZ;
1140 err = i40evf_execute_vf_cmd(dev, &args);
1142 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1147 static const struct rte_pci_id pci_id_i40evf_map[] = {
1148 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1149 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1150 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1151 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1152 { .vendor_id = 0, /* sentinel */ },
1157 i40evf_disable_irq0(struct i40e_hw *hw)
1159 /* Disable all interrupt types */
1160 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1161 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1162 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1163 I40EVF_WRITE_FLUSH(hw);
1168 i40evf_enable_irq0(struct i40e_hw *hw)
1170 /* Enable admin queue interrupt trigger */
1173 i40evf_disable_irq0(hw);
1174 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1175 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1176 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1177 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1179 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1180 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1181 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1182 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1184 I40EVF_WRITE_FLUSH(hw);
1188 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1191 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1194 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1195 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1196 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1197 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1198 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1199 reset == VIRTCHNL_VFR_COMPLETED)
1204 if (i >= MAX_RESET_WAIT_CNT)
1207 vf->vf_reset = false;
1208 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1213 i40evf_reset_vf(struct rte_eth_dev *dev)
1216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1219 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1223 * After issuing vf reset command to pf, pf won't necessarily
1224 * reset vf, it depends on what state it exactly is. If it's not
1225 * initialized yet, it won't have vf reset since it's in a certain
1226 * state. If not, it will try to reset. Even vf is reset, pf will
1227 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1228 * it to ACTIVE. In this duration, vf may not catch the moment that
1229 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1233 ret = i40evf_check_vf_reset_done(dev);
1235 PMD_INIT_LOG(ERR, "VF is still resetting");
1243 i40evf_init_vf(struct rte_eth_dev *dev)
1246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1249 i40e_calc_itr_interval(0, 0);
1251 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1252 vf->dev_data = dev->data;
1253 err = i40e_set_mac_type(hw);
1255 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1259 err = i40evf_check_vf_reset_done(dev);
1263 i40e_init_adminq_parameter(hw);
1264 err = i40e_init_adminq(hw);
1266 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1270 /* Reset VF and wait until it's complete */
1271 if (i40evf_reset_vf(dev)) {
1272 PMD_INIT_LOG(ERR, "reset NIC failed");
1276 /* VF reset, shutdown admin queue and initialize again */
1277 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1278 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1282 i40e_init_adminq_parameter(hw);
1283 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1284 PMD_INIT_LOG(ERR, "init_adminq failed");
1288 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1290 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1293 if (i40evf_check_api_version(dev) != 0) {
1294 PMD_INIT_LOG(ERR, "check_api version failed");
1297 bufsz = sizeof(struct virtchnl_vf_resource) +
1298 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1299 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1301 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1305 if (i40evf_get_vf_resource(dev) != 0) {
1306 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1310 /* got VF config message back from PF, now we can parse it */
1311 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1312 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1313 vf->vsi_res = &vf->vf_res->vsi_res[i];
1317 PMD_INIT_LOG(ERR, "no LAN VSI found");
1321 if (hw->mac.type == I40E_MAC_X722_VF)
1322 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1323 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1325 switch (vf->vsi_res->vsi_type) {
1326 case VIRTCHNL_VSI_SRIOV:
1327 vf->vsi.type = I40E_VSI_SRIOV;
1330 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1333 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1334 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1336 /* Store the MAC address configured by host, or generate random one */
1337 if (!rte_is_valid_assigned_ether_addr(
1338 (struct rte_ether_addr *)hw->mac.addr))
1339 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1341 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1342 (I40E_ITR_INDEX_DEFAULT <<
1343 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1345 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1346 I40EVF_WRITE_FLUSH(hw);
1351 rte_free(vf->vf_res);
1354 rte_free(vf->aq_resp);
1356 i40e_shutdown_adminq(hw); /* ignore error */
1362 i40evf_uninit_vf(struct rte_eth_dev *dev)
1364 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 PMD_INIT_FUNC_TRACE();
1368 if (hw->adapter_closed == 0)
1369 i40evf_dev_close(dev);
1375 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1376 __rte_unused uint16_t msglen)
1378 struct virtchnl_pf_event *pf_msg =
1379 (struct virtchnl_pf_event *)msg;
1380 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1382 switch (pf_msg->event) {
1383 case VIRTCHNL_EVENT_RESET_IMPENDING:
1384 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1385 _rte_eth_dev_callback_process(dev,
1386 RTE_ETH_EVENT_INTR_RESET, NULL);
1388 case VIRTCHNL_EVENT_LINK_CHANGE:
1389 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1391 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {
1393 pf_msg->event_data.link_event_adv.link_status;
1395 switch (pf_msg->event_data.link_event_adv.link_speed) {
1396 case ETH_SPEED_NUM_100M:
1397 vf->link_speed = VIRTCHNL_LINK_SPEED_100MB;
1399 case ETH_SPEED_NUM_1G:
1400 vf->link_speed = VIRTCHNL_LINK_SPEED_1GB;
1402 case ETH_SPEED_NUM_2_5G:
1403 vf->link_speed = VIRTCHNL_LINK_SPEED_2_5GB;
1405 case ETH_SPEED_NUM_5G:
1406 vf->link_speed = VIRTCHNL_LINK_SPEED_5GB;
1408 case ETH_SPEED_NUM_10G:
1409 vf->link_speed = VIRTCHNL_LINK_SPEED_10GB;
1411 case ETH_SPEED_NUM_20G:
1412 vf->link_speed = VIRTCHNL_LINK_SPEED_20GB;
1414 case ETH_SPEED_NUM_25G:
1415 vf->link_speed = VIRTCHNL_LINK_SPEED_25GB;
1417 case ETH_SPEED_NUM_40G:
1418 vf->link_speed = VIRTCHNL_LINK_SPEED_40GB;
1421 vf->link_speed = VIRTCHNL_LINK_SPEED_UNKNOWN;
1426 pf_msg->event_data.link_event.link_status;
1428 pf_msg->event_data.link_event.link_speed;
1431 i40evf_dev_link_update(dev, 0);
1432 _rte_eth_dev_callback_process(dev,
1433 RTE_ETH_EVENT_INTR_LSC, NULL);
1435 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1436 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1439 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1445 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1447 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1449 struct i40e_arq_event_info info;
1450 uint16_t pending, aq_opc;
1451 enum virtchnl_ops msg_opc;
1452 enum i40e_status_code msg_ret;
1455 info.buf_len = I40E_AQ_BUF_SZ;
1457 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1460 info.msg_buf = vf->aq_resp;
1464 ret = i40e_clean_arq_element(hw, &info, &pending);
1466 if (ret != I40E_SUCCESS) {
1467 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1471 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1472 /* For the message sent from pf to vf, opcode is stored in
1473 * cookie_high of struct i40e_aq_desc, while return error code
1474 * are stored in cookie_low, Which is done by
1475 * i40e_aq_send_msg_to_vf in PF driver.*/
1476 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1477 info.desc.cookie_high);
1478 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1479 info.desc.cookie_low);
1481 case i40e_aqc_opc_send_msg_to_vf:
1482 if (msg_opc == VIRTCHNL_OP_EVENT)
1484 i40evf_handle_pf_event(dev, info.msg_buf,
1487 /* read message and it's expected one */
1488 if (msg_opc == vf->pend_cmd) {
1489 vf->cmd_retval = msg_ret;
1490 /* prevent compiler reordering */
1491 rte_compiler_barrier();
1494 PMD_DRV_LOG(ERR, "command mismatch,"
1495 "expect %u, get %u",
1496 vf->pend_cmd, msg_opc);
1497 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1498 " opcode = %d", msg_opc);
1502 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1510 * Interrupt handler triggered by NIC for handling
1511 * specific interrupt. Only adminq interrupt is processed in VF.
1514 * Pointer to interrupt handle.
1516 * The address of parameter (struct rte_eth_dev *) regsitered before.
1522 i40evf_dev_alarm_handler(void *param)
1524 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1528 i40evf_disable_irq0(hw);
1530 /* read out interrupt causes */
1531 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1533 /* No interrupt event indicated */
1534 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1537 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1538 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1539 i40evf_handle_aq_msg(dev);
1542 /* Link Status Change interrupt */
1543 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1544 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1548 i40evf_enable_irq0(hw);
1549 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1550 i40evf_dev_alarm_handler, dev);
1554 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1557 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1558 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560 PMD_INIT_FUNC_TRACE();
1562 /* assign ops func pointer */
1563 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1564 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1565 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1568 * For secondary processes, we don't initialise any further as primary
1569 * has already done this work.
1571 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1572 i40e_set_rx_function(eth_dev);
1573 i40e_set_tx_function(eth_dev);
1576 i40e_set_default_ptype_table(eth_dev);
1577 rte_eth_copy_pci_info(eth_dev, pci_dev);
1579 hw->vendor_id = pci_dev->id.vendor_id;
1580 hw->device_id = pci_dev->id.device_id;
1581 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1582 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1583 hw->bus.device = pci_dev->addr.devid;
1584 hw->bus.func = pci_dev->addr.function;
1585 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1586 hw->adapter_stopped = 1;
1587 hw->adapter_closed = 0;
1589 /* Pass the information to the rte_eth_dev_close() that it should also
1590 * release the private port resources.
1592 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1594 if(i40evf_init_vf(eth_dev) != 0) {
1595 PMD_INIT_LOG(ERR, "Init vf failed");
1599 i40e_set_default_pctype_table(eth_dev);
1600 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1601 i40evf_dev_alarm_handler, eth_dev);
1603 /* configure and enable device interrupt */
1604 i40evf_enable_irq0(hw);
1607 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1608 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1610 if (eth_dev->data->mac_addrs == NULL) {
1611 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1612 " store MAC addresses",
1613 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1616 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1617 ð_dev->data->mac_addrs[0]);
1623 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1625 PMD_INIT_FUNC_TRACE();
1627 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1630 if (i40evf_uninit_vf(eth_dev) != 0) {
1631 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1638 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1639 struct rte_pci_device *pci_dev)
1641 return rte_eth_dev_pci_generic_probe(pci_dev,
1642 sizeof(struct i40e_adapter), i40evf_dev_init);
1645 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1647 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1651 * virtual function driver struct
1653 static struct rte_pci_driver rte_i40evf_pmd = {
1654 .id_table = pci_id_i40evf_map,
1655 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1656 .probe = eth_i40evf_pci_probe,
1657 .remove = eth_i40evf_pci_remove,
1660 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1661 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1662 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1665 i40evf_dev_configure(struct rte_eth_dev *dev)
1667 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1668 struct i40e_adapter *ad =
1669 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1670 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1671 dev->data->nb_tx_queues);
1673 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1674 * allocation or vector Rx preconditions we will reset it.
1676 ad->rx_bulk_alloc_allowed = true;
1677 ad->rx_vec_allowed = true;
1678 ad->tx_simple_allowed = true;
1679 ad->tx_vec_allowed = true;
1681 dev->data->dev_conf.intr_conf.lsc =
1682 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);
1684 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1688 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1690 "For secondary processes, change queue pairs is not supported!");
1694 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 if (!hw->adapter_stopped) {
1696 PMD_DRV_LOG(ERR, "Device must be stopped first!");
1700 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1701 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1702 ret = i40evf_request_queues(dev, num_queue_pairs);
1706 ret = i40evf_dev_reset(dev);
1711 return i40evf_init_vlan(dev);
1715 i40evf_init_vlan(struct rte_eth_dev *dev)
1717 /* Apply vlan offload setting */
1718 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1724 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1726 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1727 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1729 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1732 /* Vlan stripping setting */
1733 if (mask & ETH_VLAN_STRIP_MASK) {
1734 /* Enable or disable VLAN stripping */
1735 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1736 i40evf_enable_vlan_strip(dev);
1738 i40evf_disable_vlan_strip(dev);
1745 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1747 struct i40e_rx_queue *rxq;
1749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751 PMD_INIT_FUNC_TRACE();
1753 rxq = dev->data->rx_queues[rx_queue_id];
1755 err = i40e_alloc_rx_queue_mbufs(rxq);
1757 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1763 /* Init the RX tail register. */
1764 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1765 I40EVF_WRITE_FLUSH(hw);
1767 /* Ready to switch the queue on */
1768 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1770 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1774 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1780 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1782 struct i40e_rx_queue *rxq;
1785 rxq = dev->data->rx_queues[rx_queue_id];
1787 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1789 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1794 i40e_rx_queue_release_mbufs(rxq);
1795 i40e_reset_rx_queue(rxq);
1796 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1802 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1806 PMD_INIT_FUNC_TRACE();
1808 /* Ready to switch the queue on */
1809 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1811 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1815 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1821 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1823 struct i40e_tx_queue *txq;
1826 txq = dev->data->tx_queues[tx_queue_id];
1828 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1830 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1835 i40e_tx_queue_release_mbufs(txq);
1836 i40e_reset_tx_queue(txq);
1837 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1843 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1848 ret = i40evf_add_vlan(dev, vlan_id);
1850 ret = i40evf_del_vlan(dev,vlan_id);
1856 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 struct rte_eth_dev_data *dev_data = dev->data;
1860 struct rte_pktmbuf_pool_private *mbp_priv;
1861 uint16_t buf_size, len;
1863 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1864 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1865 I40EVF_WRITE_FLUSH(hw);
1867 /* Calculate the maximum packet length allowed */
1868 mbp_priv = rte_mempool_get_priv(rxq->mp);
1869 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1870 RTE_PKTMBUF_HEADROOM);
1871 rxq->hs_mode = i40e_header_split_none;
1872 rxq->rx_hdr_len = 0;
1873 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1874 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1875 rxq->max_pkt_len = RTE_MIN(len,
1876 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1879 * Check if the jumbo frame and maximum packet length are set correctly
1881 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1882 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1883 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1884 PMD_DRV_LOG(ERR, "maximum packet length must be "
1885 "larger than %u and smaller than %u, as jumbo "
1886 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1887 (uint32_t)I40E_FRAME_SIZE_MAX);
1888 return I40E_ERR_CONFIG;
1891 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1892 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1893 PMD_DRV_LOG(ERR, "maximum packet length must be "
1894 "larger than %u and smaller than %u, as jumbo "
1895 "frame is disabled",
1896 (uint32_t)RTE_ETHER_MIN_LEN,
1897 (uint32_t)RTE_ETHER_MAX_LEN);
1898 return I40E_ERR_CONFIG;
1902 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1903 rxq->max_pkt_len > buf_size)
1904 dev_data->scattered_rx = 1;
1910 i40evf_rx_init(struct rte_eth_dev *dev)
1912 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1914 int ret = I40E_SUCCESS;
1915 struct i40e_rx_queue **rxq =
1916 (struct i40e_rx_queue **)dev->data->rx_queues;
1918 i40evf_config_rss(vf);
1919 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1920 if (!rxq[i] || !rxq[i]->q_set)
1922 ret = i40evf_rxq_init(dev, rxq[i]);
1923 if (ret != I40E_SUCCESS)
1926 if (ret == I40E_SUCCESS)
1927 i40e_set_rx_function(dev);
1933 i40evf_tx_init(struct rte_eth_dev *dev)
1936 struct i40e_tx_queue **txq =
1937 (struct i40e_tx_queue **)dev->data->tx_queues;
1938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 for (i = 0; i < dev->data->nb_tx_queues; i++)
1941 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1943 i40e_set_tx_function(dev);
1947 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1949 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1951 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1953 if (!rte_intr_allow_others(intr_handle)) {
1955 I40E_VFINT_DYN_CTL01,
1956 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1957 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1958 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1959 I40EVF_WRITE_FLUSH(hw);
1963 I40EVF_WRITE_FLUSH(hw);
1967 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1969 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1971 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1973 if (!rte_intr_allow_others(intr_handle)) {
1974 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1975 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1976 I40EVF_WRITE_FLUSH(hw);
1980 I40EVF_WRITE_FLUSH(hw);
1984 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990 i40e_calc_itr_interval(0, 0);
1993 msix_intr = intr_handle->intr_vec[queue_id];
1994 if (msix_intr == I40E_MISC_VEC_ID)
1995 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1996 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1997 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1998 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
2000 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
2003 I40E_VFINT_DYN_CTLN1(msix_intr -
2005 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2006 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2007 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2009 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2011 I40EVF_WRITE_FLUSH(hw);
2017 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2019 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2020 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024 msix_intr = intr_handle->intr_vec[queue_id];
2025 if (msix_intr == I40E_MISC_VEC_ID)
2026 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2029 I40E_VFINT_DYN_CTLN1(msix_intr -
2033 I40EVF_WRITE_FLUSH(hw);
2039 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2041 struct virtchnl_ether_addr_list *list;
2042 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2047 struct rte_ether_addr *addr;
2048 struct vf_cmd_info args;
2052 len = sizeof(struct virtchnl_ether_addr_list);
2053 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2054 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
2056 len += sizeof(struct virtchnl_ether_addr);
2057 if (len >= I40E_AQ_BUF_SZ) {
2063 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2065 PMD_DRV_LOG(ERR, "fail to allocate memory");
2069 for (i = begin; i < next_begin; i++) {
2070 addr = &dev->data->mac_addrs[i];
2071 if (rte_is_zero_ether_addr(addr))
2073 rte_memcpy(list->list[j].addr, addr->addr_bytes,
2074 sizeof(addr->addr_bytes));
2075 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2076 addr->addr_bytes[0], addr->addr_bytes[1],
2077 addr->addr_bytes[2], addr->addr_bytes[3],
2078 addr->addr_bytes[4], addr->addr_bytes[5]);
2081 list->vsi_id = vf->vsi_res->vsi_id;
2082 list->num_elements = j;
2083 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2084 VIRTCHNL_OP_DEL_ETH_ADDR;
2085 args.in_args = (uint8_t *)list;
2086 args.in_args_size = len;
2087 args.out_buffer = vf->aq_resp;
2088 args.out_size = I40E_AQ_BUF_SZ;
2089 err = i40evf_execute_vf_cmd(dev, &args);
2091 PMD_DRV_LOG(ERR, "fail to execute command %s",
2092 add ? "OP_ADD_ETHER_ADDRESS" :
2093 "OP_DEL_ETHER_ADDRESS");
2102 } while (begin < I40E_NUM_MACADDR_MAX);
2106 i40evf_dev_start(struct rte_eth_dev *dev)
2108 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2111 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2112 uint32_t intr_vector = 0;
2114 PMD_INIT_FUNC_TRACE();
2116 hw->adapter_stopped = 0;
2118 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2119 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2120 dev->data->nb_tx_queues);
2122 /* check and configure queue intr-vector mapping */
2123 if (rte_intr_cap_multiple(intr_handle) &&
2124 dev->data->dev_conf.intr_conf.rxq) {
2125 intr_vector = dev->data->nb_rx_queues;
2126 if (rte_intr_efd_enable(intr_handle, intr_vector))
2130 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2131 intr_handle->intr_vec =
2132 rte_zmalloc("intr_vec",
2133 dev->data->nb_rx_queues * sizeof(int), 0);
2134 if (!intr_handle->intr_vec) {
2135 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2136 " intr_vec", dev->data->nb_rx_queues);
2141 if (i40evf_rx_init(dev) != 0){
2142 PMD_DRV_LOG(ERR, "failed to do RX init");
2146 i40evf_tx_init(dev);
2148 if (i40evf_configure_vsi_queues(dev) != 0) {
2149 PMD_DRV_LOG(ERR, "configure queues failed");
2152 if (i40evf_config_irq_map(dev)) {
2153 PMD_DRV_LOG(ERR, "config_irq_map failed");
2157 /* Set all mac addrs */
2158 i40evf_add_del_all_mac_addr(dev, TRUE);
2159 /* Set all multicast addresses */
2160 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2163 if (i40evf_start_queues(dev) != 0) {
2164 PMD_DRV_LOG(ERR, "enable queues failed");
2168 /* only enable interrupt in rx interrupt mode */
2169 if (dev->data->dev_conf.intr_conf.rxq != 0)
2170 rte_intr_enable(intr_handle);
2172 i40evf_enable_queues_intr(dev);
2177 i40evf_add_del_all_mac_addr(dev, FALSE);
2178 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2185 i40evf_dev_stop(struct rte_eth_dev *dev)
2187 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2188 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2189 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2192 PMD_INIT_FUNC_TRACE();
2194 if (dev->data->dev_conf.intr_conf.rxq != 0)
2195 rte_intr_disable(intr_handle);
2197 if (hw->adapter_stopped == 1)
2199 i40evf_stop_queues(dev);
2200 i40evf_disable_queues_intr(dev);
2201 i40e_dev_clear_queues(dev);
2203 /* Clean datapath event and queue/vec mapping */
2204 rte_intr_efd_disable(intr_handle);
2205 if (intr_handle->intr_vec) {
2206 rte_free(intr_handle->intr_vec);
2207 intr_handle->intr_vec = NULL;
2209 /* remove all mac addrs */
2210 i40evf_add_del_all_mac_addr(dev, FALSE);
2211 /* remove all multicast addresses */
2212 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2214 hw->adapter_stopped = 1;
2219 i40evf_dev_link_update(struct rte_eth_dev *dev,
2220 __rte_unused int wait_to_complete)
2222 struct rte_eth_link new_link;
2223 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2225 * DPDK pf host provide interfacet to acquire link status
2226 * while Linux driver does not
2229 memset(&new_link, 0, sizeof(new_link));
2230 /* Linux driver PF host */
2231 switch (vf->link_speed) {
2232 case I40E_LINK_SPEED_100MB:
2233 new_link.link_speed = ETH_SPEED_NUM_100M;
2235 case I40E_LINK_SPEED_1GB:
2236 new_link.link_speed = ETH_SPEED_NUM_1G;
2238 case I40E_LINK_SPEED_10GB:
2239 new_link.link_speed = ETH_SPEED_NUM_10G;
2241 case I40E_LINK_SPEED_20GB:
2242 new_link.link_speed = ETH_SPEED_NUM_20G;
2244 case I40E_LINK_SPEED_25GB:
2245 new_link.link_speed = ETH_SPEED_NUM_25G;
2247 case I40E_LINK_SPEED_40GB:
2248 new_link.link_speed = ETH_SPEED_NUM_40G;
2252 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2254 new_link.link_speed = ETH_SPEED_NUM_NONE;
2257 /* full duplex only */
2258 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2259 new_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
2260 new_link.link_autoneg =
2261 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2263 return rte_eth_linkstatus_set(dev, &new_link);
2267 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2269 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2271 return i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);
2275 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2277 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2279 return i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);
2283 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2285 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2287 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);
2291 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2293 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2295 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);
2299 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2301 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2303 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2304 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2305 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2306 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2307 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2308 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2309 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2310 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2311 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2312 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2313 dev_info->rx_queue_offload_capa = 0;
2314 dev_info->rx_offload_capa =
2315 DEV_RX_OFFLOAD_VLAN_STRIP |
2316 DEV_RX_OFFLOAD_QINQ_STRIP |
2317 DEV_RX_OFFLOAD_IPV4_CKSUM |
2318 DEV_RX_OFFLOAD_UDP_CKSUM |
2319 DEV_RX_OFFLOAD_TCP_CKSUM |
2320 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2321 DEV_RX_OFFLOAD_SCATTER |
2322 DEV_RX_OFFLOAD_JUMBO_FRAME |
2323 DEV_RX_OFFLOAD_VLAN_FILTER;
2325 dev_info->tx_queue_offload_capa = 0;
2326 dev_info->tx_offload_capa =
2327 DEV_TX_OFFLOAD_VLAN_INSERT |
2328 DEV_TX_OFFLOAD_QINQ_INSERT |
2329 DEV_TX_OFFLOAD_IPV4_CKSUM |
2330 DEV_TX_OFFLOAD_UDP_CKSUM |
2331 DEV_TX_OFFLOAD_TCP_CKSUM |
2332 DEV_TX_OFFLOAD_SCTP_CKSUM |
2333 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2334 DEV_TX_OFFLOAD_TCP_TSO |
2335 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2336 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2337 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2338 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2339 DEV_TX_OFFLOAD_MULTI_SEGS;
2341 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2343 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2344 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2345 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2347 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2352 dev_info->default_txconf = (struct rte_eth_txconf) {
2354 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2355 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2356 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2358 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2359 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2363 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2364 .nb_max = I40E_MAX_RING_DESC,
2365 .nb_min = I40E_MIN_RING_DESC,
2366 .nb_align = I40E_ALIGN_RING_DESC,
2369 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2370 .nb_max = I40E_MAX_RING_DESC,
2371 .nb_min = I40E_MIN_RING_DESC,
2372 .nb_align = I40E_ALIGN_RING_DESC,
2379 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2382 struct i40e_eth_stats *pstats = NULL;
2383 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2384 struct i40e_vsi *vsi = &vf->vsi;
2386 ret = i40evf_query_stats(dev, &pstats);
2388 i40evf_update_stats(vsi, pstats);
2390 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2391 pstats->rx_broadcast;
2392 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2394 stats->imissed = pstats->rx_discards;
2395 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2396 stats->ibytes = pstats->rx_bytes;
2397 stats->obytes = pstats->tx_bytes;
2399 PMD_DRV_LOG(ERR, "Get statistics failed");
2405 i40evf_dev_close(struct rte_eth_dev *dev)
2407 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2410 i40evf_dev_stop(dev);
2411 i40e_dev_free_queues(dev);
2413 * disable promiscuous mode before reset vf
2414 * it is a workaround solution when work with kernel driver
2415 * and it is not the normal way
2417 if (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)
2418 i40evf_config_promisc(dev, false, false);
2420 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2422 i40evf_reset_vf(dev);
2423 i40e_shutdown_adminq(hw);
2424 i40evf_disable_irq0(hw);
2426 dev->dev_ops = NULL;
2427 dev->rx_pkt_burst = NULL;
2428 dev->tx_pkt_burst = NULL;
2430 rte_free(vf->vf_res);
2432 rte_free(vf->aq_resp);
2435 hw->adapter_closed = 1;
2439 * Reset VF device only to re-initialize resources in PMD layer
2442 i40evf_dev_reset(struct rte_eth_dev *dev)
2446 ret = i40evf_dev_uninit(dev);
2450 ret = i40evf_dev_init(dev);
2456 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2458 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2459 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2465 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2466 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2469 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2473 uint32_t *lut_dw = (uint32_t *)lut;
2474 uint16_t i, lut_size_dw = lut_size / 4;
2476 for (i = 0; i < lut_size_dw; i++)
2477 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2484 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2493 vf = I40E_VSI_TO_VF(vsi);
2494 hw = I40E_VSI_TO_HW(vsi);
2496 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2497 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2500 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2504 uint32_t *lut_dw = (uint32_t *)lut;
2505 uint16_t i, lut_size_dw = lut_size / 4;
2507 for (i = 0; i < lut_size_dw; i++)
2508 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2509 I40EVF_WRITE_FLUSH(hw);
2516 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2517 struct rte_eth_rss_reta_entry64 *reta_conf,
2520 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2522 uint16_t i, idx, shift;
2525 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2526 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2527 "(%d) doesn't match the number of hardware can "
2528 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2532 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2534 PMD_DRV_LOG(ERR, "No memory can be allocated");
2537 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2540 for (i = 0; i < reta_size; i++) {
2541 idx = i / RTE_RETA_GROUP_SIZE;
2542 shift = i % RTE_RETA_GROUP_SIZE;
2543 if (reta_conf[idx].mask & (1ULL << shift))
2544 lut[i] = reta_conf[idx].reta[shift];
2546 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2555 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2556 struct rte_eth_rss_reta_entry64 *reta_conf,
2559 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2560 uint16_t i, idx, shift;
2564 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2565 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2566 "(%d) doesn't match the number of hardware can "
2567 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2571 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2573 PMD_DRV_LOG(ERR, "No memory can be allocated");
2577 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2580 for (i = 0; i < reta_size; i++) {
2581 idx = i / RTE_RETA_GROUP_SIZE;
2582 shift = i % RTE_RETA_GROUP_SIZE;
2583 if (reta_conf[idx].mask & (1ULL << shift))
2584 reta_conf[idx].reta[shift] = lut[i];
2594 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2596 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2597 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2600 if (!key || key_len == 0) {
2601 PMD_DRV_LOG(DEBUG, "No key to be configured");
2603 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2605 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2609 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2610 struct i40e_aqc_get_set_rss_key_data *key_dw =
2611 (struct i40e_aqc_get_set_rss_key_data *)key;
2613 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2615 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2618 uint32_t *hash_key = (uint32_t *)key;
2621 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2622 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2623 I40EVF_WRITE_FLUSH(hw);
2630 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2632 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2633 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2636 if (!key || !key_len)
2639 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2640 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2641 (struct i40e_aqc_get_set_rss_key_data *)key);
2643 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2647 uint32_t *key_dw = (uint32_t *)key;
2650 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2651 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2653 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2659 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2661 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2665 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2666 rss_conf->rss_key_len);
2670 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2671 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2672 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2673 I40EVF_WRITE_FLUSH(hw);
2679 i40evf_disable_rss(struct i40e_vf *vf)
2681 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2683 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2684 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2685 I40EVF_WRITE_FLUSH(hw);
2689 i40evf_config_rss(struct i40e_vf *vf)
2691 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2692 struct rte_eth_rss_conf rss_conf;
2693 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2694 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2699 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2700 i40evf_disable_rss(vf);
2701 PMD_DRV_LOG(DEBUG, "RSS not configured");
2705 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2706 /* Fill out the look up table */
2707 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2708 for (i = 0, j = 0; i < nb_q; i++, j++) {
2711 lut = (lut << 8) | j;
2713 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2716 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2718 PMD_DRV_LOG(ERR, "No memory can be allocated");
2722 for (i = 0; i < rss_lut_size; i++)
2723 lut_info[i] = i % vf->num_queue_pairs;
2725 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2732 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2733 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2734 i40evf_disable_rss(vf);
2735 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2739 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2740 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2741 /* Calculate the default hash key */
2742 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2743 rss_key_default[i] = (uint32_t)rte_rand();
2744 rss_conf.rss_key = (uint8_t *)rss_key_default;
2745 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2749 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2753 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2754 struct rte_eth_rss_conf *rss_conf)
2756 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2757 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2761 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2762 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2764 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2765 if (rss_hf != 0) /* Enable RSS */
2771 if (rss_hf == 0) /* Disable RSS */
2774 return i40evf_hw_rss_hash_set(vf, rss_conf);
2778 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2779 struct rte_eth_rss_conf *rss_conf)
2781 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2786 &rss_conf->rss_key_len);
2788 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2789 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2790 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2796 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2798 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2799 struct rte_eth_dev_data *dev_data = vf->dev_data;
2800 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2803 /* check if mtu is within the allowed range */
2804 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2807 /* mtu setting is forbidden if port is start */
2808 if (dev_data->dev_started) {
2809 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2814 if (frame_size > RTE_ETHER_MAX_LEN)
2815 dev_data->dev_conf.rxmode.offloads |=
2816 DEV_RX_OFFLOAD_JUMBO_FRAME;
2818 dev_data->dev_conf.rxmode.offloads &=
2819 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2820 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2826 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2827 struct rte_ether_addr *mac_addr)
2829 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2832 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2836 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2838 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2841 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2846 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2847 struct rte_ether_addr *mc_addrs,
2848 uint32_t mc_addrs_num, bool add)
2850 struct virtchnl_ether_addr_list *list;
2851 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2852 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2853 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2856 struct vf_cmd_info args;
2858 if (mc_addrs == NULL || mc_addrs_num == 0)
2861 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2864 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2865 list->vsi_id = vf->vsi_res->vsi_id;
2866 list->num_elements = mc_addrs_num;
2868 for (i = 0; i < mc_addrs_num; i++) {
2869 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2870 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2871 mc_addrs[i].addr_bytes[0],
2872 mc_addrs[i].addr_bytes[1],
2873 mc_addrs[i].addr_bytes[2],
2874 mc_addrs[i].addr_bytes[3],
2875 mc_addrs[i].addr_bytes[4],
2876 mc_addrs[i].addr_bytes[5]);
2880 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2881 sizeof(list->list[i].addr));
2884 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2885 args.in_args = cmd_buffer;
2886 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2887 i * sizeof(struct virtchnl_ether_addr);
2888 args.out_buffer = vf->aq_resp;
2889 args.out_size = I40E_AQ_BUF_SZ;
2890 err = i40evf_execute_vf_cmd(dev, &args);
2892 PMD_DRV_LOG(ERR, "fail to execute command %s",
2893 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2901 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2902 struct rte_ether_addr *mc_addrs,
2903 uint32_t mc_addrs_num)
2905 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2908 /* flush previous addresses */
2909 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2914 vf->mc_addrs_num = 0;
2917 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2922 vf->mc_addrs_num = mc_addrs_num;
2923 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2929 is_i40evf_supported(struct rte_eth_dev *dev)
2931 return is_device_supported(dev, &rte_i40evf_pmd);