1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static void i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
97 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
99 static int i40evf_init_vlan(struct rte_eth_dev *dev);
100 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
101 uint16_t rx_queue_id);
102 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
103 uint16_t rx_queue_id);
104 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
105 uint16_t tx_queue_id);
106 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
107 uint16_t tx_queue_id);
108 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
109 struct rte_ether_addr *addr,
112 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
113 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_reta_entry64 *reta_conf,
116 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
117 struct rte_eth_rss_reta_entry64 *reta_conf,
119 static int i40evf_config_rss(struct i40e_vf *vf);
120 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
121 struct rte_eth_rss_conf *rss_conf);
122 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
123 struct rte_eth_rss_conf *rss_conf);
124 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
126 struct rte_ether_addr *mac_addr);
128 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
130 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
131 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
136 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
137 struct rte_ether_addr *mc_addr_set,
138 uint32_t nb_mc_addr, bool add);
140 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr);
144 i40evf_dev_alarm_handler(void *param);
146 /* Default hash key buffer for RSS */
147 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
149 struct rte_i40evf_xstats_name_off {
150 char name[RTE_ETH_XSTATS_NAME_SIZE];
154 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
155 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
156 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
157 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
158 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
159 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
160 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
161 rx_unknown_protocol)},
162 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
163 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
164 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
165 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
166 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
167 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
170 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
171 sizeof(rte_i40evf_stats_strings[0]))
173 static const struct eth_dev_ops i40evf_eth_dev_ops = {
174 .dev_configure = i40evf_dev_configure,
175 .dev_start = i40evf_dev_start,
176 .dev_stop = i40evf_dev_stop,
177 .promiscuous_enable = i40evf_dev_promiscuous_enable,
178 .promiscuous_disable = i40evf_dev_promiscuous_disable,
179 .allmulticast_enable = i40evf_dev_allmulticast_enable,
180 .allmulticast_disable = i40evf_dev_allmulticast_disable,
181 .link_update = i40evf_dev_link_update,
182 .stats_get = i40evf_dev_stats_get,
183 .stats_reset = i40evf_dev_xstats_reset,
184 .xstats_get = i40evf_dev_xstats_get,
185 .xstats_get_names = i40evf_dev_xstats_get_names,
186 .xstats_reset = i40evf_dev_xstats_reset,
187 .dev_close = i40evf_dev_close,
188 .dev_reset = i40evf_dev_reset,
189 .dev_infos_get = i40evf_dev_info_get,
190 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
191 .vlan_filter_set = i40evf_vlan_filter_set,
192 .vlan_offload_set = i40evf_vlan_offload_set,
193 .rx_queue_start = i40evf_dev_rx_queue_start,
194 .rx_queue_stop = i40evf_dev_rx_queue_stop,
195 .tx_queue_start = i40evf_dev_tx_queue_start,
196 .tx_queue_stop = i40evf_dev_tx_queue_stop,
197 .rx_queue_setup = i40e_dev_rx_queue_setup,
198 .rx_queue_release = i40e_dev_rx_queue_release,
199 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
200 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
201 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
202 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
203 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
204 .tx_queue_setup = i40e_dev_tx_queue_setup,
205 .tx_queue_release = i40e_dev_tx_queue_release,
206 .rx_queue_count = i40e_dev_rx_queue_count,
207 .rxq_info_get = i40e_rxq_info_get,
208 .txq_info_get = i40e_txq_info_get,
209 .mac_addr_add = i40evf_add_mac_addr,
210 .mac_addr_remove = i40evf_del_mac_addr,
211 .set_mc_addr_list = i40evf_set_mc_addr_list,
212 .reta_update = i40evf_dev_rss_reta_update,
213 .reta_query = i40evf_dev_rss_reta_query,
214 .rss_hash_update = i40evf_dev_rss_hash_update,
215 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
216 .mtu_set = i40evf_dev_mtu_set,
217 .mac_addr_set = i40evf_set_default_mac_addr,
221 * Read data in admin queue to get msg from pf driver
223 static enum i40evf_aq_result
224 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
227 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
228 struct i40e_arq_event_info event;
229 enum virtchnl_ops opcode;
230 enum i40e_status_code retval;
232 enum i40evf_aq_result result = I40EVF_MSG_NON;
234 event.buf_len = data->buf_len;
235 event.msg_buf = data->msg;
236 ret = i40e_clean_arq_element(hw, &event, NULL);
237 /* Can't read any msg from adminQ */
239 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
240 result = I40EVF_MSG_ERR;
244 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
245 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
247 if (opcode == VIRTCHNL_OP_EVENT) {
248 struct virtchnl_pf_event *vpe =
249 (struct virtchnl_pf_event *)event.msg_buf;
251 result = I40EVF_MSG_SYS;
252 switch (vpe->event) {
253 case VIRTCHNL_EVENT_LINK_CHANGE:
255 vpe->event_data.link_event.link_status;
257 vpe->event_data.link_event.link_speed;
258 vf->pend_msg |= PFMSG_LINK_CHANGE;
259 PMD_DRV_LOG(INFO, "Link status update:%s",
260 vf->link_up ? "up" : "down");
262 case VIRTCHNL_EVENT_RESET_IMPENDING:
264 vf->pend_msg |= PFMSG_RESET_IMPENDING;
265 PMD_DRV_LOG(INFO, "vf is reseting");
267 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
268 vf->dev_closed = true;
269 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
270 PMD_DRV_LOG(INFO, "PF driver closed");
273 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
274 __func__, vpe->event);
277 /* async reply msg on command issued by vf previously */
278 result = I40EVF_MSG_CMD;
279 /* Actual data length read from PF */
280 data->msg_len = event.msg_len;
283 data->result = retval;
290 * clear current command. Only call in case execute
291 * _atomic_set_cmd successfully.
294 _clear_cmd(struct i40e_vf *vf)
297 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
301 * Check there is pending cmd in execution. If none, set new command.
304 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
306 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
307 VIRTCHNL_OP_UNKNOWN, ops);
310 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
315 #define MAX_TRY_TIMES 200
316 #define ASQ_DELAY_MS 10
319 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
322 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
323 struct i40evf_arq_msg_info info;
324 enum i40evf_aq_result ret;
327 if (_atomic_set_cmd(vf, args->ops))
330 info.msg = args->out_buffer;
331 info.buf_len = args->out_size;
332 info.ops = VIRTCHNL_OP_UNKNOWN;
333 info.result = I40E_SUCCESS;
335 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
336 args->in_args, args->in_args_size, NULL);
338 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
344 case VIRTCHNL_OP_RESET_VF:
345 /*no need to process in this function */
348 case VIRTCHNL_OP_VERSION:
349 case VIRTCHNL_OP_GET_VF_RESOURCES:
350 /* for init adminq commands, need to poll the response */
353 ret = i40evf_read_pfmsg(dev, &info);
354 vf->cmd_retval = info.result;
355 if (ret == I40EVF_MSG_CMD) {
358 } else if (ret == I40EVF_MSG_ERR)
360 rte_delay_ms(ASQ_DELAY_MS);
361 /* If don't read msg or read sys event, continue */
362 } while (i++ < MAX_TRY_TIMES);
365 case VIRTCHNL_OP_REQUEST_QUEUES:
367 * ignore async reply, only wait for system message,
368 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
369 * if not, means request queues failed.
373 ret = i40evf_read_pfmsg(dev, &info);
374 vf->cmd_retval = info.result;
375 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
378 } else if (ret == I40EVF_MSG_ERR ||
379 ret == I40EVF_MSG_CMD) {
382 rte_delay_ms(ASQ_DELAY_MS);
383 /* If don't read msg or read sys event, continue */
384 } while (i++ < MAX_TRY_TIMES);
389 /* for other adminq in running time, waiting the cmd done flag */
392 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
396 rte_delay_ms(ASQ_DELAY_MS);
397 /* If don't read msg or read sys event, continue */
398 } while (i++ < MAX_TRY_TIMES);
399 /* If there's no response is received, clear command */
400 if (i >= MAX_TRY_TIMES) {
401 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
407 return err | vf->cmd_retval;
411 * Check API version with sync wait until version read or fail from admin queue
414 i40evf_check_api_version(struct rte_eth_dev *dev)
416 struct virtchnl_version_info version, *pver;
418 struct vf_cmd_info args;
419 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
421 version.major = VIRTCHNL_VERSION_MAJOR;
422 version.minor = VIRTCHNL_VERSION_MINOR;
424 args.ops = VIRTCHNL_OP_VERSION;
425 args.in_args = (uint8_t *)&version;
426 args.in_args_size = sizeof(version);
427 args.out_buffer = vf->aq_resp;
428 args.out_size = I40E_AQ_BUF_SZ;
430 err = i40evf_execute_vf_cmd(dev, &args);
432 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
436 pver = (struct virtchnl_version_info *)args.out_buffer;
437 vf->version_major = pver->major;
438 vf->version_minor = pver->minor;
439 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
440 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
441 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
443 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
444 vf->version_major, vf->version_minor,
445 VIRTCHNL_VERSION_MAJOR,
446 VIRTCHNL_VERSION_MINOR);
454 i40evf_get_vf_resource(struct rte_eth_dev *dev)
456 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
457 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
459 struct vf_cmd_info args;
462 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
463 args.out_buffer = vf->aq_resp;
464 args.out_size = I40E_AQ_BUF_SZ;
466 caps = VIRTCHNL_VF_OFFLOAD_L2 |
467 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
468 VIRTCHNL_VF_OFFLOAD_RSS_REG |
469 VIRTCHNL_VF_OFFLOAD_VLAN |
470 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
471 args.in_args = (uint8_t *)∩︀
472 args.in_args_size = sizeof(caps);
475 args.in_args_size = 0;
477 err = i40evf_execute_vf_cmd(dev, &args);
480 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
484 len = sizeof(struct virtchnl_vf_resource) +
485 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
487 rte_memcpy(vf->vf_res, args.out_buffer,
488 RTE_MIN(args.out_size, len));
489 i40e_vf_parse_hw_config(hw, vf->vf_res);
495 i40evf_config_promisc(struct rte_eth_dev *dev,
497 bool enable_multicast)
499 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
501 struct vf_cmd_info args;
502 struct virtchnl_promisc_info promisc;
505 promisc.vsi_id = vf->vsi_res->vsi_id;
508 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
510 if (enable_multicast)
511 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
513 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
514 args.in_args = (uint8_t *)&promisc;
515 args.in_args_size = sizeof(promisc);
516 args.out_buffer = vf->aq_resp;
517 args.out_size = I40E_AQ_BUF_SZ;
519 err = i40evf_execute_vf_cmd(dev, &args);
522 PMD_DRV_LOG(ERR, "fail to execute command "
523 "CONFIG_PROMISCUOUS_MODE");
528 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
530 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
531 struct vf_cmd_info args;
534 memset(&args, 0, sizeof(args));
535 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
537 args.in_args_size = 0;
538 args.out_buffer = vf->aq_resp;
539 args.out_size = I40E_AQ_BUF_SZ;
540 ret = i40evf_execute_vf_cmd(dev, &args);
542 PMD_DRV_LOG(ERR, "Failed to execute command of "
543 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
549 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
551 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
552 struct vf_cmd_info args;
555 memset(&args, 0, sizeof(args));
556 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
558 args.in_args_size = 0;
559 args.out_buffer = vf->aq_resp;
560 args.out_size = I40E_AQ_BUF_SZ;
561 ret = i40evf_execute_vf_cmd(dev, &args);
563 PMD_DRV_LOG(ERR, "Failed to execute command of "
564 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
570 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
574 struct i40e_tx_queue *txq)
576 txq_info->vsi_id = vsi_id;
577 txq_info->queue_id = queue_id;
578 if (queue_id < nb_txq && txq) {
579 txq_info->ring_len = txq->nb_tx_desc;
580 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
585 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
589 uint32_t max_pkt_size,
590 struct i40e_rx_queue *rxq)
592 rxq_info->vsi_id = vsi_id;
593 rxq_info->queue_id = queue_id;
594 rxq_info->max_pkt_size = max_pkt_size;
595 if (queue_id < nb_rxq && rxq) {
596 rxq_info->ring_len = rxq->nb_rx_desc;
597 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
598 rxq_info->databuffer_size =
599 (rte_pktmbuf_data_room_size(rxq->mp) -
600 RTE_PKTMBUF_HEADROOM);
605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
607 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
608 struct i40e_rx_queue **rxq =
609 (struct i40e_rx_queue **)dev->data->rx_queues;
610 struct i40e_tx_queue **txq =
611 (struct i40e_tx_queue **)dev->data->tx_queues;
612 struct virtchnl_vsi_queue_config_info *vc_vqci;
613 struct virtchnl_queue_pair_info *vc_qpi;
614 struct vf_cmd_info args;
615 uint16_t i, nb_qp = vf->num_queue_pairs;
616 const uint32_t size =
617 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
621 memset(buff, 0, sizeof(buff));
622 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
623 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
624 vc_vqci->num_queue_pairs = nb_qp;
626 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
627 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
628 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
629 txq ? txq[i] : NULL);
630 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
631 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
632 vf->max_pkt_len, rxq ? rxq[i] : NULL);
634 memset(&args, 0, sizeof(args));
635 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
636 args.in_args = (uint8_t *)vc_vqci;
637 args.in_args_size = size;
638 args.out_buffer = vf->aq_resp;
639 args.out_size = I40E_AQ_BUF_SZ;
640 ret = i40evf_execute_vf_cmd(dev, &args);
642 PMD_DRV_LOG(ERR, "Failed to execute command of "
643 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
649 i40evf_config_irq_map(struct rte_eth_dev *dev)
651 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
652 struct vf_cmd_info args;
653 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
654 sizeof(struct virtchnl_vector_map) * dev->data->nb_rx_queues];
655 struct virtchnl_irq_map_info *map_info;
656 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
657 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
662 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
663 rte_intr_allow_others(intr_handle))
664 vector_id = I40E_RX_VEC_START;
666 vector_id = I40E_MISC_VEC_ID;
668 nb_msix = RTE_MIN(vf->vf_res->max_vectors,
669 intr_handle->nb_efd);
671 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
672 map_info->num_vectors = dev->data->nb_rx_queues;
673 for (i = 0; i < dev->data->nb_rx_queues; i++) {
674 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
675 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
676 /* Always use default dynamic MSIX interrupt */
677 map_info->vecmap[i].vector_id = vector_id;
678 /* Don't map any tx queue */
679 map_info->vecmap[i].txq_map = 0;
680 map_info->vecmap[i].rxq_map = 1 << i;
681 if (rte_intr_dp_is_en(intr_handle))
682 intr_handle->intr_vec[i] = vector_id;
683 if (vector_id > I40E_MISC_VEC_ID)
685 if (vector_id > nb_msix)
686 vector_id = I40E_RX_VEC_START;
689 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
690 args.in_args = (u8 *)cmd_buffer;
691 args.in_args_size = sizeof(cmd_buffer);
692 args.out_buffer = vf->aq_resp;
693 args.out_size = I40E_AQ_BUF_SZ;
694 err = i40evf_execute_vf_cmd(dev, &args);
696 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
702 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
705 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
706 struct virtchnl_queue_select queue_select;
708 struct vf_cmd_info args;
709 memset(&queue_select, 0, sizeof(queue_select));
710 queue_select.vsi_id = vf->vsi_res->vsi_id;
713 queue_select.rx_queues |= 1 << qid;
715 queue_select.tx_queues |= 1 << qid;
718 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
720 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
721 args.in_args = (u8 *)&queue_select;
722 args.in_args_size = sizeof(queue_select);
723 args.out_buffer = vf->aq_resp;
724 args.out_size = I40E_AQ_BUF_SZ;
725 err = i40evf_execute_vf_cmd(dev, &args);
727 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
728 isrx ? "RX" : "TX", qid, on ? "on" : "off");
734 i40evf_start_queues(struct rte_eth_dev *dev)
736 struct rte_eth_dev_data *dev_data = dev->data;
738 struct i40e_rx_queue *rxq;
739 struct i40e_tx_queue *txq;
741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
742 rxq = dev_data->rx_queues[i];
743 if (rxq->rx_deferred_start)
745 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
746 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
751 for (i = 0; i < dev->data->nb_tx_queues; i++) {
752 txq = dev_data->tx_queues[i];
753 if (txq->tx_deferred_start)
755 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
756 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
765 i40evf_stop_queues(struct rte_eth_dev *dev)
769 /* Stop TX queues first */
770 for (i = 0; i < dev->data->nb_tx_queues; i++) {
771 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
772 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
777 /* Then stop RX queues */
778 for (i = 0; i < dev->data->nb_rx_queues; i++) {
779 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
780 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
789 i40evf_add_mac_addr(struct rte_eth_dev *dev,
790 struct rte_ether_addr *addr,
791 __rte_unused uint32_t index,
792 __rte_unused uint32_t pool)
794 struct virtchnl_ether_addr_list *list;
795 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
796 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
797 sizeof(struct virtchnl_ether_addr)];
799 struct vf_cmd_info args;
801 if (rte_is_zero_ether_addr(addr)) {
802 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
803 addr->addr_bytes[0], addr->addr_bytes[1],
804 addr->addr_bytes[2], addr->addr_bytes[3],
805 addr->addr_bytes[4], addr->addr_bytes[5]);
806 return I40E_ERR_INVALID_MAC_ADDR;
809 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
810 list->vsi_id = vf->vsi_res->vsi_id;
811 list->num_elements = 1;
812 rte_memcpy(list->list[0].addr, addr->addr_bytes,
813 sizeof(addr->addr_bytes));
815 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
816 args.in_args = cmd_buffer;
817 args.in_args_size = sizeof(cmd_buffer);
818 args.out_buffer = vf->aq_resp;
819 args.out_size = I40E_AQ_BUF_SZ;
820 err = i40evf_execute_vf_cmd(dev, &args);
822 PMD_DRV_LOG(ERR, "fail to execute command "
823 "OP_ADD_ETHER_ADDRESS");
831 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
832 struct rte_ether_addr *addr)
834 struct virtchnl_ether_addr_list *list;
835 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
836 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
837 sizeof(struct virtchnl_ether_addr)];
839 struct vf_cmd_info args;
841 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
842 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
843 addr->addr_bytes[0], addr->addr_bytes[1],
844 addr->addr_bytes[2], addr->addr_bytes[3],
845 addr->addr_bytes[4], addr->addr_bytes[5]);
849 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
850 list->vsi_id = vf->vsi_res->vsi_id;
851 list->num_elements = 1;
852 rte_memcpy(list->list[0].addr, addr->addr_bytes,
853 sizeof(addr->addr_bytes));
855 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
856 args.in_args = cmd_buffer;
857 args.in_args_size = sizeof(cmd_buffer);
858 args.out_buffer = vf->aq_resp;
859 args.out_size = I40E_AQ_BUF_SZ;
860 err = i40evf_execute_vf_cmd(dev, &args);
862 PMD_DRV_LOG(ERR, "fail to execute command "
863 "OP_DEL_ETHER_ADDRESS");
870 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
872 struct rte_eth_dev_data *data = dev->data;
873 struct rte_ether_addr *addr;
875 addr = &data->mac_addrs[index];
877 i40evf_del_mac_addr_by_addr(dev, addr);
881 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
883 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
884 struct virtchnl_queue_select q_stats;
886 struct vf_cmd_info args;
888 memset(&q_stats, 0, sizeof(q_stats));
889 q_stats.vsi_id = vf->vsi_res->vsi_id;
890 args.ops = VIRTCHNL_OP_GET_STATS;
891 args.in_args = (u8 *)&q_stats;
892 args.in_args_size = sizeof(q_stats);
893 args.out_buffer = vf->aq_resp;
894 args.out_size = I40E_AQ_BUF_SZ;
896 err = i40evf_execute_vf_cmd(dev, &args);
898 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
902 *pstats = (struct i40e_eth_stats *)args.out_buffer;
907 i40evf_stat_update_48(uint64_t *offset,
910 if (*stat >= *offset)
911 *stat = *stat - *offset;
913 *stat = (uint64_t)((*stat +
914 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
916 *stat &= I40E_48_BIT_MASK;
920 i40evf_stat_update_32(uint64_t *offset,
923 if (*stat >= *offset)
924 *stat = (uint64_t)(*stat - *offset);
926 *stat = (uint64_t)((*stat +
927 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
931 i40evf_update_stats(struct i40e_vsi *vsi,
932 struct i40e_eth_stats *nes)
934 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
936 i40evf_stat_update_48(&oes->rx_bytes,
938 i40evf_stat_update_48(&oes->rx_unicast,
940 i40evf_stat_update_48(&oes->rx_multicast,
942 i40evf_stat_update_48(&oes->rx_broadcast,
944 i40evf_stat_update_32(&oes->rx_discards,
946 i40evf_stat_update_32(&oes->rx_unknown_protocol,
947 &nes->rx_unknown_protocol);
948 i40evf_stat_update_48(&oes->tx_bytes,
950 i40evf_stat_update_48(&oes->tx_unicast,
952 i40evf_stat_update_48(&oes->tx_multicast,
954 i40evf_stat_update_48(&oes->tx_broadcast,
956 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
957 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
961 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
964 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
965 struct i40e_eth_stats *pstats = NULL;
967 /* read stat values to clear hardware registers */
968 ret = i40evf_query_stats(dev, &pstats);
970 /* set stats offset base on current values */
972 vf->vsi.eth_stats_offset = *pstats;
977 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
978 struct rte_eth_xstat_name *xstats_names,
979 __rte_unused unsigned limit)
983 if (xstats_names != NULL)
984 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
985 snprintf(xstats_names[i].name,
986 sizeof(xstats_names[i].name),
987 "%s", rte_i40evf_stats_strings[i].name);
989 return I40EVF_NB_XSTATS;
992 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
993 struct rte_eth_xstat *xstats, unsigned n)
997 struct i40e_eth_stats *pstats = NULL;
998 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
999 struct i40e_vsi *vsi = &vf->vsi;
1001 if (n < I40EVF_NB_XSTATS)
1002 return I40EVF_NB_XSTATS;
1004 ret = i40evf_query_stats(dev, &pstats);
1011 i40evf_update_stats(vsi, pstats);
1013 /* loop over xstats array and values from pstats */
1014 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1016 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1017 rte_i40evf_stats_strings[i].offset);
1020 return I40EVF_NB_XSTATS;
1024 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1026 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1027 struct virtchnl_vlan_filter_list *vlan_list;
1028 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1031 struct vf_cmd_info args;
1033 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1034 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1035 vlan_list->num_elements = 1;
1036 vlan_list->vlan_id[0] = vlanid;
1038 args.ops = VIRTCHNL_OP_ADD_VLAN;
1039 args.in_args = (u8 *)&cmd_buffer;
1040 args.in_args_size = sizeof(cmd_buffer);
1041 args.out_buffer = vf->aq_resp;
1042 args.out_size = I40E_AQ_BUF_SZ;
1043 err = i40evf_execute_vf_cmd(dev, &args);
1045 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1051 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1053 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1054 struct virtchnl_vf_res_request vfres;
1055 struct vf_cmd_info args;
1058 vfres.num_queue_pairs = num;
1060 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1061 args.in_args = (u8 *)&vfres;
1062 args.in_args_size = sizeof(vfres);
1063 args.out_buffer = vf->aq_resp;
1064 args.out_size = I40E_AQ_BUF_SZ;
1066 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1067 err = i40evf_execute_vf_cmd(dev, &args);
1069 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1071 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1072 i40evf_dev_alarm_handler, dev);
1077 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1079 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1080 struct virtchnl_vlan_filter_list *vlan_list;
1081 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1084 struct vf_cmd_info args;
1086 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1087 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1088 vlan_list->num_elements = 1;
1089 vlan_list->vlan_id[0] = vlanid;
1091 args.ops = VIRTCHNL_OP_DEL_VLAN;
1092 args.in_args = (u8 *)&cmd_buffer;
1093 args.in_args_size = sizeof(cmd_buffer);
1094 args.out_buffer = vf->aq_resp;
1095 args.out_size = I40E_AQ_BUF_SZ;
1096 err = i40evf_execute_vf_cmd(dev, &args);
1098 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1103 static const struct rte_pci_id pci_id_i40evf_map[] = {
1104 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1105 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1106 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1107 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1108 { .vendor_id = 0, /* sentinel */ },
1113 i40evf_disable_irq0(struct i40e_hw *hw)
1115 /* Disable all interrupt types */
1116 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1117 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1118 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1119 I40EVF_WRITE_FLUSH(hw);
1124 i40evf_enable_irq0(struct i40e_hw *hw)
1126 /* Enable admin queue interrupt trigger */
1129 i40evf_disable_irq0(hw);
1130 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1131 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1132 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1133 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1135 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1136 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1137 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1138 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1140 I40EVF_WRITE_FLUSH(hw);
1144 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1148 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1150 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1151 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1152 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1153 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1154 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1155 reset == VIRTCHNL_VFR_COMPLETED)
1160 if (i >= MAX_RESET_WAIT_CNT)
1163 vf->vf_reset = false;
1164 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1169 i40evf_reset_vf(struct rte_eth_dev *dev)
1172 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1175 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1179 * After issuing vf reset command to pf, pf won't necessarily
1180 * reset vf, it depends on what state it exactly is. If it's not
1181 * initialized yet, it won't have vf reset since it's in a certain
1182 * state. If not, it will try to reset. Even vf is reset, pf will
1183 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1184 * it to ACTIVE. In this duration, vf may not catch the moment that
1185 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1189 ret = i40evf_check_vf_reset_done(dev);
1191 PMD_INIT_LOG(ERR, "VF is still resetting");
1199 i40evf_init_vf(struct rte_eth_dev *dev)
1202 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1205 i40e_calc_itr_interval(0, 0);
1207 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1208 vf->dev_data = dev->data;
1209 err = i40e_set_mac_type(hw);
1211 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1215 err = i40evf_check_vf_reset_done(dev);
1219 i40e_init_adminq_parameter(hw);
1220 err = i40e_init_adminq(hw);
1222 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1226 /* Reset VF and wait until it's complete */
1227 if (i40evf_reset_vf(dev)) {
1228 PMD_INIT_LOG(ERR, "reset NIC failed");
1232 /* VF reset, shutdown admin queue and initialize again */
1233 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1234 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1238 i40e_init_adminq_parameter(hw);
1239 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1240 PMD_INIT_LOG(ERR, "init_adminq failed");
1244 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1246 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1249 if (i40evf_check_api_version(dev) != 0) {
1250 PMD_INIT_LOG(ERR, "check_api version failed");
1253 bufsz = sizeof(struct virtchnl_vf_resource) +
1254 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1255 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1257 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1261 if (i40evf_get_vf_resource(dev) != 0) {
1262 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1266 /* got VF config message back from PF, now we can parse it */
1267 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1268 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1269 vf->vsi_res = &vf->vf_res->vsi_res[i];
1273 PMD_INIT_LOG(ERR, "no LAN VSI found");
1277 if (hw->mac.type == I40E_MAC_X722_VF)
1278 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1279 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1281 switch (vf->vsi_res->vsi_type) {
1282 case VIRTCHNL_VSI_SRIOV:
1283 vf->vsi.type = I40E_VSI_SRIOV;
1286 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1289 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1290 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1292 /* Store the MAC address configured by host, or generate random one */
1293 if (rte_is_valid_assigned_ether_addr(
1294 (struct rte_ether_addr *)hw->mac.addr))
1295 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1297 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1299 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1300 (I40E_ITR_INDEX_DEFAULT <<
1301 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1303 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1304 I40EVF_WRITE_FLUSH(hw);
1309 rte_free(vf->vf_res);
1312 rte_free(vf->aq_resp);
1314 i40e_shutdown_adminq(hw); /* ignore error */
1320 i40evf_uninit_vf(struct rte_eth_dev *dev)
1322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324 PMD_INIT_FUNC_TRACE();
1326 if (hw->adapter_closed == 0)
1327 i40evf_dev_close(dev);
1333 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1334 __rte_unused uint16_t msglen)
1336 struct virtchnl_pf_event *pf_msg =
1337 (struct virtchnl_pf_event *)msg;
1338 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1340 switch (pf_msg->event) {
1341 case VIRTCHNL_EVENT_RESET_IMPENDING:
1342 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1343 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1346 case VIRTCHNL_EVENT_LINK_CHANGE:
1347 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1348 vf->link_up = pf_msg->event_data.link_event.link_status;
1349 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1351 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1352 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1355 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1361 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1365 struct i40e_arq_event_info info;
1366 uint16_t pending, aq_opc;
1367 enum virtchnl_ops msg_opc;
1368 enum i40e_status_code msg_ret;
1371 info.buf_len = I40E_AQ_BUF_SZ;
1373 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1376 info.msg_buf = vf->aq_resp;
1380 ret = i40e_clean_arq_element(hw, &info, &pending);
1382 if (ret != I40E_SUCCESS) {
1383 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1387 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1388 /* For the message sent from pf to vf, opcode is stored in
1389 * cookie_high of struct i40e_aq_desc, while return error code
1390 * are stored in cookie_low, Which is done by
1391 * i40e_aq_send_msg_to_vf in PF driver.*/
1392 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1393 info.desc.cookie_high);
1394 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1395 info.desc.cookie_low);
1397 case i40e_aqc_opc_send_msg_to_vf:
1398 if (msg_opc == VIRTCHNL_OP_EVENT)
1400 i40evf_handle_pf_event(dev, info.msg_buf,
1403 /* read message and it's expected one */
1404 if (msg_opc == vf->pend_cmd) {
1405 vf->cmd_retval = msg_ret;
1406 /* prevent compiler reordering */
1407 rte_compiler_barrier();
1410 PMD_DRV_LOG(ERR, "command mismatch,"
1411 "expect %u, get %u",
1412 vf->pend_cmd, msg_opc);
1413 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1414 " opcode = %d", msg_opc);
1418 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1426 * Interrupt handler triggered by NIC for handling
1427 * specific interrupt. Only adminq interrupt is processed in VF.
1430 * Pointer to interrupt handle.
1432 * The address of parameter (struct rte_eth_dev *) regsitered before.
1438 i40evf_dev_alarm_handler(void *param)
1440 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1444 i40evf_disable_irq0(hw);
1446 /* read out interrupt causes */
1447 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1449 /* No interrupt event indicated */
1450 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1453 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1454 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1455 i40evf_handle_aq_msg(dev);
1458 /* Link Status Change interrupt */
1459 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1460 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1464 i40evf_enable_irq0(hw);
1465 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1466 i40evf_dev_alarm_handler, dev);
1470 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1473 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1474 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1476 PMD_INIT_FUNC_TRACE();
1478 /* assign ops func pointer */
1479 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1480 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1481 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1484 * For secondary processes, we don't initialise any further as primary
1485 * has already done this work.
1487 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1488 i40e_set_rx_function(eth_dev);
1489 i40e_set_tx_function(eth_dev);
1492 i40e_set_default_ptype_table(eth_dev);
1493 rte_eth_copy_pci_info(eth_dev, pci_dev);
1495 hw->vendor_id = pci_dev->id.vendor_id;
1496 hw->device_id = pci_dev->id.device_id;
1497 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1498 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1499 hw->bus.device = pci_dev->addr.devid;
1500 hw->bus.func = pci_dev->addr.function;
1501 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1502 hw->adapter_stopped = 0;
1503 hw->adapter_closed = 0;
1505 /* Pass the information to the rte_eth_dev_close() that it should also
1506 * release the private port resources.
1508 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1510 if(i40evf_init_vf(eth_dev) != 0) {
1511 PMD_INIT_LOG(ERR, "Init vf failed");
1515 i40e_set_default_pctype_table(eth_dev);
1516 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1517 i40evf_dev_alarm_handler, eth_dev);
1519 /* configure and enable device interrupt */
1520 i40evf_enable_irq0(hw);
1523 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1524 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1526 if (eth_dev->data->mac_addrs == NULL) {
1527 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1528 " store MAC addresses",
1529 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1532 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1533 ð_dev->data->mac_addrs[0]);
1539 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1541 PMD_INIT_FUNC_TRACE();
1543 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1546 if (i40evf_uninit_vf(eth_dev) != 0) {
1547 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1554 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1555 struct rte_pci_device *pci_dev)
1557 return rte_eth_dev_pci_generic_probe(pci_dev,
1558 sizeof(struct i40e_adapter), i40evf_dev_init);
1561 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1563 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1567 * virtual function driver struct
1569 static struct rte_pci_driver rte_i40evf_pmd = {
1570 .id_table = pci_id_i40evf_map,
1571 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1572 .probe = eth_i40evf_pci_probe,
1573 .remove = eth_i40evf_pci_remove,
1576 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1577 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1578 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1581 i40evf_dev_configure(struct rte_eth_dev *dev)
1583 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1584 struct i40e_adapter *ad =
1585 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1586 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1587 dev->data->nb_tx_queues);
1589 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1590 * allocation or vector Rx preconditions we will reset it.
1592 ad->rx_bulk_alloc_allowed = true;
1593 ad->rx_vec_allowed = true;
1594 ad->tx_simple_allowed = true;
1595 ad->tx_vec_allowed = true;
1597 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1600 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1601 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1602 ret = i40evf_request_queues(dev, num_queue_pairs);
1606 ret = i40evf_dev_reset(dev);
1611 return i40evf_init_vlan(dev);
1615 i40evf_init_vlan(struct rte_eth_dev *dev)
1617 /* Apply vlan offload setting */
1618 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1624 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1626 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1627 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1629 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1632 /* Vlan stripping setting */
1633 if (mask & ETH_VLAN_STRIP_MASK) {
1634 /* Enable or disable VLAN stripping */
1635 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1636 i40evf_enable_vlan_strip(dev);
1638 i40evf_disable_vlan_strip(dev);
1645 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1647 struct i40e_rx_queue *rxq;
1649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651 PMD_INIT_FUNC_TRACE();
1653 rxq = dev->data->rx_queues[rx_queue_id];
1655 err = i40e_alloc_rx_queue_mbufs(rxq);
1657 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1663 /* Init the RX tail register. */
1664 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1665 I40EVF_WRITE_FLUSH(hw);
1667 /* Ready to switch the queue on */
1668 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1670 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1674 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1680 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1682 struct i40e_rx_queue *rxq;
1685 rxq = dev->data->rx_queues[rx_queue_id];
1687 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1689 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1694 i40e_rx_queue_release_mbufs(rxq);
1695 i40e_reset_rx_queue(rxq);
1696 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1702 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1706 PMD_INIT_FUNC_TRACE();
1708 /* Ready to switch the queue on */
1709 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1711 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1715 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1721 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1723 struct i40e_tx_queue *txq;
1726 txq = dev->data->tx_queues[tx_queue_id];
1728 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1730 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1735 i40e_tx_queue_release_mbufs(txq);
1736 i40e_reset_tx_queue(txq);
1737 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1743 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1748 ret = i40evf_add_vlan(dev, vlan_id);
1750 ret = i40evf_del_vlan(dev,vlan_id);
1756 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759 struct rte_eth_dev_data *dev_data = dev->data;
1760 struct rte_pktmbuf_pool_private *mbp_priv;
1761 uint16_t buf_size, len;
1763 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1764 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1765 I40EVF_WRITE_FLUSH(hw);
1767 /* Calculate the maximum packet length allowed */
1768 mbp_priv = rte_mempool_get_priv(rxq->mp);
1769 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1770 RTE_PKTMBUF_HEADROOM);
1771 rxq->hs_mode = i40e_header_split_none;
1772 rxq->rx_hdr_len = 0;
1773 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1774 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1775 rxq->max_pkt_len = RTE_MIN(len,
1776 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1779 * Check if the jumbo frame and maximum packet length are set correctly
1781 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1782 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
1783 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1784 PMD_DRV_LOG(ERR, "maximum packet length must be "
1785 "larger than %u and smaller than %u, as jumbo "
1786 "frame is enabled", (uint32_t)RTE_ETHER_MAX_LEN,
1787 (uint32_t)I40E_FRAME_SIZE_MAX);
1788 return I40E_ERR_CONFIG;
1791 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1792 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
1793 PMD_DRV_LOG(ERR, "maximum packet length must be "
1794 "larger than %u and smaller than %u, as jumbo "
1795 "frame is disabled",
1796 (uint32_t)RTE_ETHER_MIN_LEN,
1797 (uint32_t)RTE_ETHER_MAX_LEN);
1798 return I40E_ERR_CONFIG;
1802 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1803 rxq->max_pkt_len > buf_size)
1804 dev_data->scattered_rx = 1;
1810 i40evf_rx_init(struct rte_eth_dev *dev)
1812 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1814 int ret = I40E_SUCCESS;
1815 struct i40e_rx_queue **rxq =
1816 (struct i40e_rx_queue **)dev->data->rx_queues;
1818 i40evf_config_rss(vf);
1819 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1820 if (!rxq[i] || !rxq[i]->q_set)
1822 ret = i40evf_rxq_init(dev, rxq[i]);
1823 if (ret != I40E_SUCCESS)
1826 if (ret == I40E_SUCCESS)
1827 i40e_set_rx_function(dev);
1833 i40evf_tx_init(struct rte_eth_dev *dev)
1836 struct i40e_tx_queue **txq =
1837 (struct i40e_tx_queue **)dev->data->tx_queues;
1838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840 for (i = 0; i < dev->data->nb_tx_queues; i++)
1841 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1843 i40e_set_tx_function(dev);
1847 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1851 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1853 if (!rte_intr_allow_others(intr_handle)) {
1855 I40E_VFINT_DYN_CTL01,
1856 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1857 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1858 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1859 I40EVF_WRITE_FLUSH(hw);
1863 I40EVF_WRITE_FLUSH(hw);
1867 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1869 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873 if (!rte_intr_allow_others(intr_handle)) {
1874 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1875 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1876 I40EVF_WRITE_FLUSH(hw);
1880 I40EVF_WRITE_FLUSH(hw);
1884 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1886 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1887 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890 i40e_calc_itr_interval(0, 0);
1893 msix_intr = intr_handle->intr_vec[queue_id];
1894 if (msix_intr == I40E_MISC_VEC_ID)
1895 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1896 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1897 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1898 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1900 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1903 I40E_VFINT_DYN_CTLN1(msix_intr -
1905 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1906 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1907 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1909 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1911 I40EVF_WRITE_FLUSH(hw);
1917 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1919 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1920 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 msix_intr = intr_handle->intr_vec[queue_id];
1925 if (msix_intr == I40E_MISC_VEC_ID)
1926 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1929 I40E_VFINT_DYN_CTLN1(msix_intr -
1933 I40EVF_WRITE_FLUSH(hw);
1939 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1941 struct virtchnl_ether_addr_list *list;
1942 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1947 struct rte_ether_addr *addr;
1948 struct vf_cmd_info args;
1952 len = sizeof(struct virtchnl_ether_addr_list);
1953 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1954 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
1956 len += sizeof(struct virtchnl_ether_addr);
1957 if (len >= I40E_AQ_BUF_SZ) {
1963 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1965 PMD_DRV_LOG(ERR, "fail to allocate memory");
1969 for (i = begin; i < next_begin; i++) {
1970 addr = &dev->data->mac_addrs[i];
1971 if (rte_is_zero_ether_addr(addr))
1973 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1974 sizeof(addr->addr_bytes));
1975 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1976 addr->addr_bytes[0], addr->addr_bytes[1],
1977 addr->addr_bytes[2], addr->addr_bytes[3],
1978 addr->addr_bytes[4], addr->addr_bytes[5]);
1981 list->vsi_id = vf->vsi_res->vsi_id;
1982 list->num_elements = j;
1983 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1984 VIRTCHNL_OP_DEL_ETH_ADDR;
1985 args.in_args = (uint8_t *)list;
1986 args.in_args_size = len;
1987 args.out_buffer = vf->aq_resp;
1988 args.out_size = I40E_AQ_BUF_SZ;
1989 err = i40evf_execute_vf_cmd(dev, &args);
1991 PMD_DRV_LOG(ERR, "fail to execute command %s",
1992 add ? "OP_ADD_ETHER_ADDRESS" :
1993 "OP_DEL_ETHER_ADDRESS");
2002 } while (begin < I40E_NUM_MACADDR_MAX);
2006 i40evf_dev_start(struct rte_eth_dev *dev)
2008 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2011 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2012 uint32_t intr_vector = 0;
2014 PMD_INIT_FUNC_TRACE();
2016 hw->adapter_stopped = 0;
2018 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2019 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2020 dev->data->nb_tx_queues);
2022 /* check and configure queue intr-vector mapping */
2023 if (rte_intr_cap_multiple(intr_handle) &&
2024 dev->data->dev_conf.intr_conf.rxq) {
2025 intr_vector = dev->data->nb_rx_queues;
2026 if (rte_intr_efd_enable(intr_handle, intr_vector))
2030 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2031 intr_handle->intr_vec =
2032 rte_zmalloc("intr_vec",
2033 dev->data->nb_rx_queues * sizeof(int), 0);
2034 if (!intr_handle->intr_vec) {
2035 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2036 " intr_vec", dev->data->nb_rx_queues);
2041 if (i40evf_rx_init(dev) != 0){
2042 PMD_DRV_LOG(ERR, "failed to do RX init");
2046 i40evf_tx_init(dev);
2048 if (i40evf_configure_vsi_queues(dev) != 0) {
2049 PMD_DRV_LOG(ERR, "configure queues failed");
2052 if (i40evf_config_irq_map(dev)) {
2053 PMD_DRV_LOG(ERR, "config_irq_map failed");
2057 /* Set all mac addrs */
2058 i40evf_add_del_all_mac_addr(dev, TRUE);
2059 /* Set all multicast addresses */
2060 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2063 if (i40evf_start_queues(dev) != 0) {
2064 PMD_DRV_LOG(ERR, "enable queues failed");
2068 /* only enable interrupt in rx interrupt mode */
2069 if (dev->data->dev_conf.intr_conf.rxq != 0)
2070 rte_intr_enable(intr_handle);
2072 i40evf_enable_queues_intr(dev);
2077 i40evf_add_del_all_mac_addr(dev, FALSE);
2078 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2085 i40evf_dev_stop(struct rte_eth_dev *dev)
2087 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2088 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2089 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2092 PMD_INIT_FUNC_TRACE();
2094 if (dev->data->dev_conf.intr_conf.rxq != 0)
2095 rte_intr_disable(intr_handle);
2097 if (hw->adapter_stopped == 1)
2099 i40evf_stop_queues(dev);
2100 i40evf_disable_queues_intr(dev);
2101 i40e_dev_clear_queues(dev);
2103 /* Clean datapath event and queue/vec mapping */
2104 rte_intr_efd_disable(intr_handle);
2105 if (intr_handle->intr_vec) {
2106 rte_free(intr_handle->intr_vec);
2107 intr_handle->intr_vec = NULL;
2109 /* remove all mac addrs */
2110 i40evf_add_del_all_mac_addr(dev, FALSE);
2111 /* remove all multicast addresses */
2112 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2114 hw->adapter_stopped = 1;
2119 i40evf_dev_link_update(struct rte_eth_dev *dev,
2120 __rte_unused int wait_to_complete)
2122 struct rte_eth_link new_link;
2123 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2125 * DPDK pf host provide interfacet to acquire link status
2126 * while Linux driver does not
2129 memset(&new_link, 0, sizeof(new_link));
2130 /* Linux driver PF host */
2131 switch (vf->link_speed) {
2132 case I40E_LINK_SPEED_100MB:
2133 new_link.link_speed = ETH_SPEED_NUM_100M;
2135 case I40E_LINK_SPEED_1GB:
2136 new_link.link_speed = ETH_SPEED_NUM_1G;
2138 case I40E_LINK_SPEED_10GB:
2139 new_link.link_speed = ETH_SPEED_NUM_10G;
2141 case I40E_LINK_SPEED_20GB:
2142 new_link.link_speed = ETH_SPEED_NUM_20G;
2144 case I40E_LINK_SPEED_25GB:
2145 new_link.link_speed = ETH_SPEED_NUM_25G;
2147 case I40E_LINK_SPEED_40GB:
2148 new_link.link_speed = ETH_SPEED_NUM_40G;
2151 new_link.link_speed = ETH_SPEED_NUM_NONE;
2154 /* full duplex only */
2155 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2156 new_link.link_status = vf->link_up &&
2157 new_link.link_speed != ETH_SPEED_NUM_NONE
2160 new_link.link_autoneg =
2161 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2163 return rte_eth_linkstatus_set(dev, &new_link);
2167 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2169 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2172 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2174 vf->promisc_unicast_enabled = TRUE;
2182 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2184 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2187 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2189 vf->promisc_unicast_enabled = FALSE;
2197 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2202 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2204 vf->promisc_multicast_enabled = TRUE;
2212 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2214 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2217 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2219 vf->promisc_multicast_enabled = FALSE;
2227 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2231 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2232 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2233 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2234 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2235 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2236 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2237 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2238 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2239 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2240 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2241 dev_info->rx_queue_offload_capa = 0;
2242 dev_info->rx_offload_capa =
2243 DEV_RX_OFFLOAD_VLAN_STRIP |
2244 DEV_RX_OFFLOAD_QINQ_STRIP |
2245 DEV_RX_OFFLOAD_IPV4_CKSUM |
2246 DEV_RX_OFFLOAD_UDP_CKSUM |
2247 DEV_RX_OFFLOAD_TCP_CKSUM |
2248 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2249 DEV_RX_OFFLOAD_SCATTER |
2250 DEV_RX_OFFLOAD_JUMBO_FRAME |
2251 DEV_RX_OFFLOAD_VLAN_FILTER;
2253 dev_info->tx_queue_offload_capa = 0;
2254 dev_info->tx_offload_capa =
2255 DEV_TX_OFFLOAD_VLAN_INSERT |
2256 DEV_TX_OFFLOAD_QINQ_INSERT |
2257 DEV_TX_OFFLOAD_IPV4_CKSUM |
2258 DEV_TX_OFFLOAD_UDP_CKSUM |
2259 DEV_TX_OFFLOAD_TCP_CKSUM |
2260 DEV_TX_OFFLOAD_SCTP_CKSUM |
2261 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2262 DEV_TX_OFFLOAD_TCP_TSO |
2263 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2264 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2265 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2266 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2267 DEV_TX_OFFLOAD_MULTI_SEGS;
2269 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2271 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2272 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2273 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2275 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2280 dev_info->default_txconf = (struct rte_eth_txconf) {
2282 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2283 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2284 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2286 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2287 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2291 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2292 .nb_max = I40E_MAX_RING_DESC,
2293 .nb_min = I40E_MIN_RING_DESC,
2294 .nb_align = I40E_ALIGN_RING_DESC,
2297 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2298 .nb_max = I40E_MAX_RING_DESC,
2299 .nb_min = I40E_MIN_RING_DESC,
2300 .nb_align = I40E_ALIGN_RING_DESC,
2307 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2310 struct i40e_eth_stats *pstats = NULL;
2311 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2312 struct i40e_vsi *vsi = &vf->vsi;
2314 ret = i40evf_query_stats(dev, &pstats);
2316 i40evf_update_stats(vsi, pstats);
2318 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2319 pstats->rx_broadcast;
2320 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2322 stats->imissed = pstats->rx_discards;
2323 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2324 stats->ibytes = pstats->rx_bytes;
2325 stats->obytes = pstats->tx_bytes;
2327 PMD_DRV_LOG(ERR, "Get statistics failed");
2333 i40evf_dev_close(struct rte_eth_dev *dev)
2335 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2338 i40evf_dev_stop(dev);
2339 i40e_dev_free_queues(dev);
2341 * disable promiscuous mode before reset vf
2342 * it is a workaround solution when work with kernel driver
2343 * and it is not the normal way
2345 i40evf_dev_promiscuous_disable(dev);
2346 i40evf_dev_allmulticast_disable(dev);
2347 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2349 i40evf_reset_vf(dev);
2350 i40e_shutdown_adminq(hw);
2351 i40evf_disable_irq0(hw);
2353 dev->dev_ops = NULL;
2354 dev->rx_pkt_burst = NULL;
2355 dev->tx_pkt_burst = NULL;
2357 rte_free(vf->vf_res);
2359 rte_free(vf->aq_resp);
2362 hw->adapter_closed = 1;
2366 * Reset VF device only to re-initialize resources in PMD layer
2369 i40evf_dev_reset(struct rte_eth_dev *dev)
2373 ret = i40evf_dev_uninit(dev);
2377 ret = i40evf_dev_init(dev);
2383 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2385 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2386 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2392 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2393 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2396 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2400 uint32_t *lut_dw = (uint32_t *)lut;
2401 uint16_t i, lut_size_dw = lut_size / 4;
2403 for (i = 0; i < lut_size_dw; i++)
2404 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2411 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2420 vf = I40E_VSI_TO_VF(vsi);
2421 hw = I40E_VSI_TO_HW(vsi);
2423 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2424 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2427 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2431 uint32_t *lut_dw = (uint32_t *)lut;
2432 uint16_t i, lut_size_dw = lut_size / 4;
2434 for (i = 0; i < lut_size_dw; i++)
2435 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2436 I40EVF_WRITE_FLUSH(hw);
2443 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2444 struct rte_eth_rss_reta_entry64 *reta_conf,
2447 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2449 uint16_t i, idx, shift;
2452 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2453 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2454 "(%d) doesn't match the number of hardware can "
2455 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2459 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2461 PMD_DRV_LOG(ERR, "No memory can be allocated");
2464 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2467 for (i = 0; i < reta_size; i++) {
2468 idx = i / RTE_RETA_GROUP_SIZE;
2469 shift = i % RTE_RETA_GROUP_SIZE;
2470 if (reta_conf[idx].mask & (1ULL << shift))
2471 lut[i] = reta_conf[idx].reta[shift];
2473 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2482 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2483 struct rte_eth_rss_reta_entry64 *reta_conf,
2486 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2487 uint16_t i, idx, shift;
2491 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2492 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2493 "(%d) doesn't match the number of hardware can "
2494 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2498 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2500 PMD_DRV_LOG(ERR, "No memory can be allocated");
2504 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2507 for (i = 0; i < reta_size; i++) {
2508 idx = i / RTE_RETA_GROUP_SIZE;
2509 shift = i % RTE_RETA_GROUP_SIZE;
2510 if (reta_conf[idx].mask & (1ULL << shift))
2511 reta_conf[idx].reta[shift] = lut[i];
2521 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2523 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2527 if (!key || key_len == 0) {
2528 PMD_DRV_LOG(DEBUG, "No key to be configured");
2530 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2532 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2536 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2537 struct i40e_aqc_get_set_rss_key_data *key_dw =
2538 (struct i40e_aqc_get_set_rss_key_data *)key;
2540 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2542 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2545 uint32_t *hash_key = (uint32_t *)key;
2548 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2549 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2550 I40EVF_WRITE_FLUSH(hw);
2557 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2559 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2560 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2563 if (!key || !key_len)
2566 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2567 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2568 (struct i40e_aqc_get_set_rss_key_data *)key);
2570 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2574 uint32_t *key_dw = (uint32_t *)key;
2577 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2578 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2580 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2586 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2588 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2592 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2593 rss_conf->rss_key_len);
2597 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2598 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2599 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2600 I40EVF_WRITE_FLUSH(hw);
2606 i40evf_disable_rss(struct i40e_vf *vf)
2608 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2610 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2611 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2612 I40EVF_WRITE_FLUSH(hw);
2616 i40evf_config_rss(struct i40e_vf *vf)
2618 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2619 struct rte_eth_rss_conf rss_conf;
2620 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2621 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2626 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2627 i40evf_disable_rss(vf);
2628 PMD_DRV_LOG(DEBUG, "RSS not configured");
2632 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2633 /* Fill out the look up table */
2634 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2635 for (i = 0, j = 0; i < nb_q; i++, j++) {
2638 lut = (lut << 8) | j;
2640 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2643 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2645 PMD_DRV_LOG(ERR, "No memory can be allocated");
2649 for (i = 0; i < rss_lut_size; i++)
2650 lut_info[i] = i % vf->num_queue_pairs;
2652 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2659 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2660 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2661 i40evf_disable_rss(vf);
2662 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2666 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2667 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2668 /* Calculate the default hash key */
2669 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2670 rss_key_default[i] = (uint32_t)rte_rand();
2671 rss_conf.rss_key = (uint8_t *)rss_key_default;
2672 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2676 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2680 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2681 struct rte_eth_rss_conf *rss_conf)
2683 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2688 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2689 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2691 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2692 if (rss_hf != 0) /* Enable RSS */
2698 if (rss_hf == 0) /* Disable RSS */
2701 return i40evf_hw_rss_hash_set(vf, rss_conf);
2705 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2706 struct rte_eth_rss_conf *rss_conf)
2708 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2713 &rss_conf->rss_key_len);
2715 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2716 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2717 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2723 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2725 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2726 struct rte_eth_dev_data *dev_data = vf->dev_data;
2727 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2730 /* check if mtu is within the allowed range */
2731 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2734 /* mtu setting is forbidden if port is start */
2735 if (dev_data->dev_started) {
2736 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2741 if (frame_size > RTE_ETHER_MAX_LEN)
2742 dev_data->dev_conf.rxmode.offloads |=
2743 DEV_RX_OFFLOAD_JUMBO_FRAME;
2745 dev_data->dev_conf.rxmode.offloads &=
2746 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2747 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2753 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2754 struct rte_ether_addr *mac_addr)
2756 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2757 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2760 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2764 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2767 i40evf_del_mac_addr_by_addr(dev, (struct rte_ether_addr *)hw->mac.addr);
2769 if (i40evf_add_mac_addr(dev, mac_addr, 0, 0) != 0)
2772 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2777 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2778 struct rte_ether_addr *mc_addrs,
2779 uint32_t mc_addrs_num, bool add)
2781 struct virtchnl_ether_addr_list *list;
2782 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2783 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2784 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2787 struct vf_cmd_info args;
2789 if (mc_addrs == NULL || mc_addrs_num == 0)
2792 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2795 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2796 list->vsi_id = vf->vsi_res->vsi_id;
2797 list->num_elements = mc_addrs_num;
2799 for (i = 0; i < mc_addrs_num; i++) {
2800 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2801 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
2802 mc_addrs[i].addr_bytes[0],
2803 mc_addrs[i].addr_bytes[1],
2804 mc_addrs[i].addr_bytes[2],
2805 mc_addrs[i].addr_bytes[3],
2806 mc_addrs[i].addr_bytes[4],
2807 mc_addrs[i].addr_bytes[5]);
2811 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2812 sizeof(list->list[i].addr));
2815 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2816 args.in_args = cmd_buffer;
2817 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2818 i * sizeof(struct virtchnl_ether_addr);
2819 args.out_buffer = vf->aq_resp;
2820 args.out_size = I40E_AQ_BUF_SZ;
2821 err = i40evf_execute_vf_cmd(dev, &args);
2823 PMD_DRV_LOG(ERR, "fail to execute command %s",
2824 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2832 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2833 struct rte_ether_addr *mc_addrs,
2834 uint32_t mc_addrs_num)
2836 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2839 /* flush previous addresses */
2840 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2845 vf->mc_addrs_num = 0;
2848 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2853 vf->mc_addrs_num = mc_addrs_num;
2854 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
2860 is_i40evf_supported(struct rte_eth_dev *dev)
2862 return is_device_supported(dev, &rte_i40evf_pmd);