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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
124 static void i40evf_dev_close(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
131 uint16_t rx_queue_id);
132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
133 uint16_t rx_queue_id);
134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
135 uint16_t tx_queue_id);
136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
137 uint16_t tx_queue_id);
138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
139 struct ether_addr *addr,
142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
144 struct rte_eth_rss_reta_entry64 *reta_conf,
146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta_entry64 *reta_conf,
149 static int i40evf_config_rss(struct i40e_vf *vf);
150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
151 struct rte_eth_rss_conf *rss_conf);
152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
153 struct rte_eth_rss_conf *rss_conf);
154 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
156 struct ether_addr *mac_addr);
158 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
160 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
161 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
165 /* Default hash key buffer for RSS */
166 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
168 struct rte_i40evf_xstats_name_off {
169 char name[RTE_ETH_XSTATS_NAME_SIZE];
173 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
174 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
175 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
176 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
177 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
178 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
179 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
180 rx_unknown_protocol)},
181 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
183 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
184 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
185 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
186 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
189 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
190 sizeof(rte_i40evf_stats_strings[0]))
192 static const struct eth_dev_ops i40evf_eth_dev_ops = {
193 .dev_configure = i40evf_dev_configure,
194 .dev_start = i40evf_dev_start,
195 .dev_stop = i40evf_dev_stop,
196 .promiscuous_enable = i40evf_dev_promiscuous_enable,
197 .promiscuous_disable = i40evf_dev_promiscuous_disable,
198 .allmulticast_enable = i40evf_dev_allmulticast_enable,
199 .allmulticast_disable = i40evf_dev_allmulticast_disable,
200 .link_update = i40evf_dev_link_update,
201 .stats_get = i40evf_dev_stats_get,
202 .xstats_get = i40evf_dev_xstats_get,
203 .xstats_get_names = i40evf_dev_xstats_get_names,
204 .xstats_reset = i40evf_dev_xstats_reset,
205 .dev_close = i40evf_dev_close,
206 .dev_infos_get = i40evf_dev_info_get,
207 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
208 .vlan_filter_set = i40evf_vlan_filter_set,
209 .vlan_offload_set = i40evf_vlan_offload_set,
210 .vlan_pvid_set = i40evf_vlan_pvid_set,
211 .rx_queue_start = i40evf_dev_rx_queue_start,
212 .rx_queue_stop = i40evf_dev_rx_queue_stop,
213 .tx_queue_start = i40evf_dev_tx_queue_start,
214 .tx_queue_stop = i40evf_dev_tx_queue_stop,
215 .rx_queue_setup = i40e_dev_rx_queue_setup,
216 .rx_queue_release = i40e_dev_rx_queue_release,
217 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
218 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
219 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
220 .tx_queue_setup = i40e_dev_tx_queue_setup,
221 .tx_queue_release = i40e_dev_tx_queue_release,
222 .rx_queue_count = i40e_dev_rx_queue_count,
223 .rxq_info_get = i40e_rxq_info_get,
224 .txq_info_get = i40e_txq_info_get,
225 .mac_addr_add = i40evf_add_mac_addr,
226 .mac_addr_remove = i40evf_del_mac_addr,
227 .reta_update = i40evf_dev_rss_reta_update,
228 .reta_query = i40evf_dev_rss_reta_query,
229 .rss_hash_update = i40evf_dev_rss_hash_update,
230 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
231 .mtu_set = i40evf_dev_mtu_set,
232 .mac_addr_set = i40evf_set_default_mac_addr,
236 * Read data in admin queue to get msg from pf driver
238 static enum i40evf_aq_result
239 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
241 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
242 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
243 struct i40e_arq_event_info event;
244 enum i40e_virtchnl_ops opcode;
245 enum i40e_status_code retval;
247 enum i40evf_aq_result result = I40EVF_MSG_NON;
249 event.buf_len = data->buf_len;
250 event.msg_buf = data->msg;
251 ret = i40e_clean_arq_element(hw, &event, NULL);
252 /* Can't read any msg from adminQ */
254 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
255 result = I40EVF_MSG_ERR;
259 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
260 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
262 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
263 struct i40e_virtchnl_pf_event *vpe =
264 (struct i40e_virtchnl_pf_event *)event.msg_buf;
266 result = I40EVF_MSG_SYS;
267 switch (vpe->event) {
268 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
270 vpe->event_data.link_event.link_status;
272 vpe->event_data.link_event.link_speed;
273 vf->pend_msg |= PFMSG_LINK_CHANGE;
274 PMD_DRV_LOG(INFO, "Link status update:%s",
275 vf->link_up ? "up" : "down");
277 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
279 vf->pend_msg |= PFMSG_RESET_IMPENDING;
280 PMD_DRV_LOG(INFO, "vf is reseting");
282 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
283 vf->dev_closed = true;
284 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
285 PMD_DRV_LOG(INFO, "PF driver closed");
288 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
289 __func__, vpe->event);
292 /* async reply msg on command issued by vf previously */
293 result = I40EVF_MSG_CMD;
294 /* Actual data length read from PF */
295 data->msg_len = event.msg_len;
298 data->result = retval;
305 * clear current command. Only call in case execute
306 * _atomic_set_cmd successfully.
309 _clear_cmd(struct i40e_vf *vf)
312 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
316 * Check there is pending cmd in execution. If none, set new command.
319 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
321 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
322 I40E_VIRTCHNL_OP_UNKNOWN, ops);
325 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
330 #define MAX_TRY_TIMES 200
331 #define ASQ_DELAY_MS 10
334 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
337 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
338 struct i40evf_arq_msg_info info;
339 enum i40evf_aq_result ret;
342 if (_atomic_set_cmd(vf, args->ops))
345 info.msg = args->out_buffer;
346 info.buf_len = args->out_size;
347 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
348 info.result = I40E_SUCCESS;
350 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
351 args->in_args, args->in_args_size, NULL);
353 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
359 case I40E_VIRTCHNL_OP_RESET_VF:
360 /*no need to process in this function */
363 case I40E_VIRTCHNL_OP_VERSION:
364 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
365 /* for init adminq commands, need to poll the response */
368 ret = i40evf_read_pfmsg(dev, &info);
369 vf->cmd_retval = info.result;
370 if (ret == I40EVF_MSG_CMD) {
373 } else if (ret == I40EVF_MSG_ERR)
375 rte_delay_ms(ASQ_DELAY_MS);
376 /* If don't read msg or read sys event, continue */
377 } while (i++ < MAX_TRY_TIMES);
382 /* for other adminq in running time, waiting the cmd done flag */
385 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
389 rte_delay_ms(ASQ_DELAY_MS);
390 /* If don't read msg or read sys event, continue */
391 } while (i++ < MAX_TRY_TIMES);
395 return err | vf->cmd_retval;
399 * Check API version with sync wait until version read or fail from admin queue
402 i40evf_check_api_version(struct rte_eth_dev *dev)
404 struct i40e_virtchnl_version_info version, *pver;
406 struct vf_cmd_info args;
407 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
409 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
410 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
412 args.ops = I40E_VIRTCHNL_OP_VERSION;
413 args.in_args = (uint8_t *)&version;
414 args.in_args_size = sizeof(version);
415 args.out_buffer = vf->aq_resp;
416 args.out_size = I40E_AQ_BUF_SZ;
418 err = i40evf_execute_vf_cmd(dev, &args);
420 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
424 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
425 vf->version_major = pver->major;
426 vf->version_minor = pver->minor;
427 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
428 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
429 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
430 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
431 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
433 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
434 vf->version_major, vf->version_minor,
435 I40E_VIRTCHNL_VERSION_MAJOR,
436 I40E_VIRTCHNL_VERSION_MINOR);
444 i40evf_get_vf_resource(struct rte_eth_dev *dev)
446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
447 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
449 struct vf_cmd_info args;
452 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
453 args.out_buffer = vf->aq_resp;
454 args.out_size = I40E_AQ_BUF_SZ;
456 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
457 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
458 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
459 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
460 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
461 args.in_args = (uint8_t *)∩︀
462 args.in_args_size = sizeof(caps);
465 args.in_args_size = 0;
467 err = i40evf_execute_vf_cmd(dev, &args);
470 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
474 len = sizeof(struct i40e_virtchnl_vf_resource) +
475 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
477 (void)rte_memcpy(vf->vf_res, args.out_buffer,
478 RTE_MIN(args.out_size, len));
479 i40e_vf_parse_hw_config(hw, vf->vf_res);
485 i40evf_config_promisc(struct rte_eth_dev *dev,
487 bool enable_multicast)
489 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
491 struct vf_cmd_info args;
492 struct i40e_virtchnl_promisc_info promisc;
495 promisc.vsi_id = vf->vsi_res->vsi_id;
498 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
500 if (enable_multicast)
501 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
503 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
504 args.in_args = (uint8_t *)&promisc;
505 args.in_args_size = sizeof(promisc);
506 args.out_buffer = vf->aq_resp;
507 args.out_size = I40E_AQ_BUF_SZ;
509 err = i40evf_execute_vf_cmd(dev, &args);
512 PMD_DRV_LOG(ERR, "fail to execute command "
513 "CONFIG_PROMISCUOUS_MODE");
517 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
519 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
520 bool enable_vlan_strip)
522 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
524 struct vf_cmd_info args;
525 struct i40e_virtchnl_vlan_offload_info offload;
527 offload.vsi_id = vf->vsi_res->vsi_id;
528 offload.enable_vlan_strip = enable_vlan_strip;
530 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
531 args.in_args = (uint8_t *)&offload;
532 args.in_args_size = sizeof(offload);
533 args.out_buffer = vf->aq_resp;
534 args.out_size = I40E_AQ_BUF_SZ;
536 err = i40evf_execute_vf_cmd(dev, &args);
538 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
544 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
545 struct i40e_vsi_vlan_pvid_info *info)
547 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
549 struct vf_cmd_info args;
550 struct i40e_virtchnl_pvid_info tpid_info;
553 PMD_DRV_LOG(ERR, "invalid parameters");
554 return I40E_ERR_PARAM;
557 memset(&tpid_info, 0, sizeof(tpid_info));
558 tpid_info.vsi_id = vf->vsi_res->vsi_id;
559 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
561 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
562 args.in_args = (uint8_t *)&tpid_info;
563 args.in_args_size = sizeof(tpid_info);
564 args.out_buffer = vf->aq_resp;
565 args.out_size = I40E_AQ_BUF_SZ;
567 err = i40evf_execute_vf_cmd(dev, &args);
569 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
575 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
579 struct i40e_tx_queue *txq)
581 txq_info->vsi_id = vsi_id;
582 txq_info->queue_id = queue_id;
583 if (queue_id < nb_txq) {
584 txq_info->ring_len = txq->nb_tx_desc;
585 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
590 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
594 uint32_t max_pkt_size,
595 struct i40e_rx_queue *rxq)
597 rxq_info->vsi_id = vsi_id;
598 rxq_info->queue_id = queue_id;
599 rxq_info->max_pkt_size = max_pkt_size;
600 if (queue_id < nb_rxq) {
601 rxq_info->ring_len = rxq->nb_rx_desc;
602 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
603 rxq_info->databuffer_size =
604 (rte_pktmbuf_data_room_size(rxq->mp) -
605 RTE_PKTMBUF_HEADROOM);
609 /* It configures VSI queues to co-work with Linux PF host */
611 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
613 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
614 struct i40e_rx_queue **rxq =
615 (struct i40e_rx_queue **)dev->data->rx_queues;
616 struct i40e_tx_queue **txq =
617 (struct i40e_tx_queue **)dev->data->tx_queues;
618 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
619 struct i40e_virtchnl_queue_pair_info *vc_qpi;
620 struct vf_cmd_info args;
621 uint16_t i, nb_qp = vf->num_queue_pairs;
622 const uint32_t size =
623 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
627 memset(buff, 0, sizeof(buff));
628 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
629 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
630 vc_vqci->num_queue_pairs = nb_qp;
632 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
633 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
634 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
635 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
636 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
637 vf->max_pkt_len, rxq[i]);
639 memset(&args, 0, sizeof(args));
640 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
641 args.in_args = (uint8_t *)vc_vqci;
642 args.in_args_size = size;
643 args.out_buffer = vf->aq_resp;
644 args.out_size = I40E_AQ_BUF_SZ;
645 ret = i40evf_execute_vf_cmd(dev, &args);
647 PMD_DRV_LOG(ERR, "Failed to execute command of "
648 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES");
653 /* It configures VSI queues to co-work with DPDK PF host */
655 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
657 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
658 struct i40e_rx_queue **rxq =
659 (struct i40e_rx_queue **)dev->data->rx_queues;
660 struct i40e_tx_queue **txq =
661 (struct i40e_tx_queue **)dev->data->tx_queues;
662 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
663 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
664 struct vf_cmd_info args;
665 uint16_t i, nb_qp = vf->num_queue_pairs;
666 const uint32_t size =
667 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
671 memset(buff, 0, sizeof(buff));
672 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
673 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
674 vc_vqcei->num_queue_pairs = nb_qp;
675 vc_qpei = vc_vqcei->qpair;
676 for (i = 0; i < nb_qp; i++, vc_qpei++) {
677 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
678 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
679 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
680 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
681 vf->max_pkt_len, rxq[i]);
682 if (i < dev->data->nb_rx_queues)
684 * It adds extra info for configuring VSI queues, which
685 * is needed to enable the configurable crc stripping
688 vc_qpei->rxq_ext.crcstrip =
689 dev->data->dev_conf.rxmode.hw_strip_crc;
691 memset(&args, 0, sizeof(args));
693 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
694 args.in_args = (uint8_t *)vc_vqcei;
695 args.in_args_size = size;
696 args.out_buffer = vf->aq_resp;
697 args.out_size = I40E_AQ_BUF_SZ;
698 ret = i40evf_execute_vf_cmd(dev, &args);
700 PMD_DRV_LOG(ERR, "Failed to execute command of "
701 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT");
707 i40evf_configure_queues(struct rte_eth_dev *dev)
709 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
711 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
712 /* To support DPDK PF host */
713 return i40evf_configure_vsi_queues_ext(dev);
715 /* To support Linux PF host */
716 return i40evf_configure_vsi_queues(dev);
720 i40evf_config_irq_map(struct rte_eth_dev *dev)
722 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
723 struct vf_cmd_info args;
724 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
725 sizeof(struct i40e_virtchnl_vector_map)];
726 struct i40e_virtchnl_irq_map_info *map_info;
727 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
728 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
732 if (rte_intr_allow_others(intr_handle)) {
733 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
734 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
736 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
738 vector_id = I40E_MISC_VEC_ID;
741 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
742 map_info->num_vectors = 1;
743 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
744 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
745 /* Alway use default dynamic MSIX interrupt */
746 map_info->vecmap[0].vector_id = vector_id;
747 /* Don't map any tx queue */
748 map_info->vecmap[0].txq_map = 0;
749 map_info->vecmap[0].rxq_map = 0;
750 for (i = 0; i < dev->data->nb_rx_queues; i++) {
751 map_info->vecmap[0].rxq_map |= 1 << i;
752 if (rte_intr_dp_is_en(intr_handle))
753 intr_handle->intr_vec[i] = vector_id;
756 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
757 args.in_args = (u8 *)cmd_buffer;
758 args.in_args_size = sizeof(cmd_buffer);
759 args.out_buffer = vf->aq_resp;
760 args.out_size = I40E_AQ_BUF_SZ;
761 err = i40evf_execute_vf_cmd(dev, &args);
763 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
769 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
772 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
773 struct i40e_virtchnl_queue_select queue_select;
775 struct vf_cmd_info args;
776 memset(&queue_select, 0, sizeof(queue_select));
777 queue_select.vsi_id = vf->vsi_res->vsi_id;
780 queue_select.rx_queues |= 1 << qid;
782 queue_select.tx_queues |= 1 << qid;
785 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
787 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
788 args.in_args = (u8 *)&queue_select;
789 args.in_args_size = sizeof(queue_select);
790 args.out_buffer = vf->aq_resp;
791 args.out_size = I40E_AQ_BUF_SZ;
792 err = i40evf_execute_vf_cmd(dev, &args);
794 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
795 isrx ? "RX" : "TX", qid, on ? "on" : "off");
801 i40evf_start_queues(struct rte_eth_dev *dev)
803 struct rte_eth_dev_data *dev_data = dev->data;
805 struct i40e_rx_queue *rxq;
806 struct i40e_tx_queue *txq;
808 for (i = 0; i < dev->data->nb_rx_queues; i++) {
809 rxq = dev_data->rx_queues[i];
810 if (rxq->rx_deferred_start)
812 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
813 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
818 for (i = 0; i < dev->data->nb_tx_queues; i++) {
819 txq = dev_data->tx_queues[i];
820 if (txq->tx_deferred_start)
822 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
823 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
832 i40evf_stop_queues(struct rte_eth_dev *dev)
836 /* Stop TX queues first */
837 for (i = 0; i < dev->data->nb_tx_queues; i++) {
838 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
839 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
844 /* Then stop RX queues */
845 for (i = 0; i < dev->data->nb_rx_queues; i++) {
846 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
847 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
856 i40evf_add_mac_addr(struct rte_eth_dev *dev,
857 struct ether_addr *addr,
858 __rte_unused uint32_t index,
859 __rte_unused uint32_t pool)
861 struct i40e_virtchnl_ether_addr_list *list;
862 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
863 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
864 sizeof(struct i40e_virtchnl_ether_addr)];
866 struct vf_cmd_info args;
868 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
869 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
870 addr->addr_bytes[0], addr->addr_bytes[1],
871 addr->addr_bytes[2], addr->addr_bytes[3],
872 addr->addr_bytes[4], addr->addr_bytes[5]);
876 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
877 list->vsi_id = vf->vsi_res->vsi_id;
878 list->num_elements = 1;
879 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
880 sizeof(addr->addr_bytes));
882 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
883 args.in_args = cmd_buffer;
884 args.in_args_size = sizeof(cmd_buffer);
885 args.out_buffer = vf->aq_resp;
886 args.out_size = I40E_AQ_BUF_SZ;
887 err = i40evf_execute_vf_cmd(dev, &args);
889 PMD_DRV_LOG(ERR, "fail to execute command "
890 "OP_ADD_ETHER_ADDRESS");
896 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
897 struct ether_addr *addr)
899 struct i40e_virtchnl_ether_addr_list *list;
900 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
901 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
902 sizeof(struct i40e_virtchnl_ether_addr)];
904 struct vf_cmd_info args;
906 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
907 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
908 addr->addr_bytes[0], addr->addr_bytes[1],
909 addr->addr_bytes[2], addr->addr_bytes[3],
910 addr->addr_bytes[4], addr->addr_bytes[5]);
914 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
915 list->vsi_id = vf->vsi_res->vsi_id;
916 list->num_elements = 1;
917 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
918 sizeof(addr->addr_bytes));
920 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
921 args.in_args = cmd_buffer;
922 args.in_args_size = sizeof(cmd_buffer);
923 args.out_buffer = vf->aq_resp;
924 args.out_size = I40E_AQ_BUF_SZ;
925 err = i40evf_execute_vf_cmd(dev, &args);
927 PMD_DRV_LOG(ERR, "fail to execute command "
928 "OP_DEL_ETHER_ADDRESS");
933 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
935 struct rte_eth_dev_data *data = dev->data;
936 struct ether_addr *addr;
938 addr = &data->mac_addrs[index];
940 i40evf_del_mac_addr_by_addr(dev, addr);
944 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
946 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
947 struct i40e_virtchnl_queue_select q_stats;
949 struct vf_cmd_info args;
951 memset(&q_stats, 0, sizeof(q_stats));
952 q_stats.vsi_id = vf->vsi_res->vsi_id;
953 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
954 args.in_args = (u8 *)&q_stats;
955 args.in_args_size = sizeof(q_stats);
956 args.out_buffer = vf->aq_resp;
957 args.out_size = I40E_AQ_BUF_SZ;
959 err = i40evf_execute_vf_cmd(dev, &args);
961 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
965 *pstats = (struct i40e_eth_stats *)args.out_buffer;
970 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
973 struct i40e_eth_stats *pstats = NULL;
975 ret = i40evf_update_stats(dev, &pstats);
979 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
980 pstats->rx_broadcast;
981 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
983 stats->ierrors = pstats->rx_discards;
984 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
985 stats->ibytes = pstats->rx_bytes;
986 stats->obytes = pstats->tx_bytes;
992 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
994 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
995 struct i40e_eth_stats *pstats = NULL;
997 /* read stat values to clear hardware registers */
998 i40evf_update_stats(dev, &pstats);
1000 /* set stats offset base on current values */
1001 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
1004 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1005 struct rte_eth_xstat_name *xstats_names,
1006 __rte_unused unsigned limit)
1010 if (xstats_names != NULL)
1011 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1012 snprintf(xstats_names[i].name,
1013 sizeof(xstats_names[i].name),
1014 "%s", rte_i40evf_stats_strings[i].name);
1016 return I40EVF_NB_XSTATS;
1019 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1020 struct rte_eth_xstat *xstats, unsigned n)
1024 struct i40e_eth_stats *pstats = NULL;
1026 if (n < I40EVF_NB_XSTATS)
1027 return I40EVF_NB_XSTATS;
1029 ret = i40evf_update_stats(dev, &pstats);
1036 /* loop over xstats array and values from pstats */
1037 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1039 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1040 rte_i40evf_stats_strings[i].offset);
1043 return I40EVF_NB_XSTATS;
1047 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1049 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1050 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1051 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1054 struct vf_cmd_info args;
1056 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1057 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1058 vlan_list->num_elements = 1;
1059 vlan_list->vlan_id[0] = vlanid;
1061 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1062 args.in_args = (u8 *)&cmd_buffer;
1063 args.in_args_size = sizeof(cmd_buffer);
1064 args.out_buffer = vf->aq_resp;
1065 args.out_size = I40E_AQ_BUF_SZ;
1066 err = i40evf_execute_vf_cmd(dev, &args);
1068 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1074 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1076 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1077 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1078 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1081 struct vf_cmd_info args;
1083 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1084 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1085 vlan_list->num_elements = 1;
1086 vlan_list->vlan_id[0] = vlanid;
1088 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1089 args.in_args = (u8 *)&cmd_buffer;
1090 args.in_args_size = sizeof(cmd_buffer);
1091 args.out_buffer = vf->aq_resp;
1092 args.out_size = I40E_AQ_BUF_SZ;
1093 err = i40evf_execute_vf_cmd(dev, &args);
1095 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1100 static const struct rte_pci_id pci_id_i40evf_map[] = {
1101 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1102 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1103 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1104 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1105 { .vendor_id = 0, /* sentinel */ },
1109 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1110 struct rte_eth_link *link)
1112 struct rte_eth_link *dst = &(dev->data->dev_link);
1113 struct rte_eth_link *src = link;
1115 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1116 *(uint64_t *)src) == 0)
1124 i40evf_disable_irq0(struct i40e_hw *hw)
1126 /* Disable all interrupt types */
1127 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1128 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1129 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1130 I40EVF_WRITE_FLUSH(hw);
1135 i40evf_enable_irq0(struct i40e_hw *hw)
1137 /* Enable admin queue interrupt trigger */
1140 i40evf_disable_irq0(hw);
1141 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1142 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1143 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1144 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1146 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1147 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1148 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1149 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1151 I40EVF_WRITE_FLUSH(hw);
1155 i40evf_reset_vf(struct i40e_hw *hw)
1159 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1164 * After issuing vf reset command to pf, pf won't necessarily
1165 * reset vf, it depends on what state it exactly is. If it's not
1166 * initialized yet, it won't have vf reset since it's in a certain
1167 * state. If not, it will try to reset. Even vf is reset, pf will
1168 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1169 * it to ACTIVE. In this duration, vf may not catch the moment that
1170 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1174 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1175 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1176 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1177 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1178 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1184 if (i >= MAX_RESET_WAIT_CNT) {
1185 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1193 i40evf_init_vf(struct rte_eth_dev *dev)
1196 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1199 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1201 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1202 vf->dev_data = dev->data;
1203 err = i40e_set_mac_type(hw);
1205 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1209 i40e_init_adminq_parameter(hw);
1210 err = i40e_init_adminq(hw);
1212 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1216 /* Reset VF and wait until it's complete */
1217 if (i40evf_reset_vf(hw)) {
1218 PMD_INIT_LOG(ERR, "reset NIC failed");
1222 /* VF reset, shutdown admin queue and initialize again */
1223 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1224 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1228 i40e_init_adminq_parameter(hw);
1229 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1230 PMD_INIT_LOG(ERR, "init_adminq failed");
1233 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1235 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1238 if (i40evf_check_api_version(dev) != 0) {
1239 PMD_INIT_LOG(ERR, "check_api version failed");
1242 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1243 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1244 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1246 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1250 if (i40evf_get_vf_resource(dev) != 0) {
1251 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1255 /* got VF config message back from PF, now we can parse it */
1256 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1257 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1258 vf->vsi_res = &vf->vf_res->vsi_res[i];
1262 PMD_INIT_LOG(ERR, "no LAN VSI found");
1266 if (hw->mac.type == I40E_MAC_X722_VF)
1267 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1268 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1269 vf->vsi.type = vf->vsi_res->vsi_type;
1270 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1271 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1273 /* Store the MAC address configured by host, or generate random one */
1274 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1275 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1277 eth_random_addr(hw->mac.addr); /* Generate a random one */
1279 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1280 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1281 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1282 (I40E_ITR_INDEX_DEFAULT <<
1283 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1285 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1286 I40EVF_WRITE_FLUSH(hw);
1292 rte_free(vf->vf_res);
1294 i40e_shutdown_adminq(hw); /* ignore error */
1300 i40evf_uninit_vf(struct rte_eth_dev *dev)
1302 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305 PMD_INIT_FUNC_TRACE();
1307 if (hw->adapter_stopped == 0)
1308 i40evf_dev_close(dev);
1309 rte_free(vf->vf_res);
1311 rte_free(vf->aq_resp);
1318 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1320 __rte_unused uint16_t msglen)
1322 struct i40e_virtchnl_pf_event *pf_msg =
1323 (struct i40e_virtchnl_pf_event *)msg;
1324 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1326 switch (pf_msg->event) {
1327 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1328 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1329 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1331 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1332 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1333 vf->link_up = pf_msg->event_data.link_event.link_status;
1334 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1336 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1337 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1340 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1346 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1348 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1350 struct i40e_arq_event_info info;
1351 uint16_t pending, aq_opc;
1352 enum i40e_virtchnl_ops msg_opc;
1353 enum i40e_status_code msg_ret;
1356 info.buf_len = I40E_AQ_BUF_SZ;
1358 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1361 info.msg_buf = vf->aq_resp;
1365 ret = i40e_clean_arq_element(hw, &info, &pending);
1367 if (ret != I40E_SUCCESS) {
1368 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1372 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1373 /* For the message sent from pf to vf, opcode is stored in
1374 * cookie_high of struct i40e_aq_desc, while return error code
1375 * are stored in cookie_low, Which is done by
1376 * i40e_aq_send_msg_to_vf in PF driver.*/
1377 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1378 info.desc.cookie_high);
1379 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1380 info.desc.cookie_low);
1382 case i40e_aqc_opc_send_msg_to_vf:
1383 if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1385 i40evf_handle_pf_event(dev, info.msg_buf,
1388 /* read message and it's expected one */
1389 if (msg_opc == vf->pend_cmd) {
1390 vf->cmd_retval = msg_ret;
1391 /* prevent compiler reordering */
1392 rte_compiler_barrier();
1395 PMD_DRV_LOG(ERR, "command mismatch,"
1396 "expect %u, get %u",
1397 vf->pend_cmd, msg_opc);
1398 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1399 " opcode = %d", msg_opc);
1403 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1411 * Interrupt handler triggered by NIC for handling
1412 * specific interrupt. Only adminq interrupt is processed in VF.
1415 * Pointer to interrupt handle.
1417 * The address of parameter (struct rte_eth_dev *) regsitered before.
1423 i40evf_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
1426 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430 i40evf_disable_irq0(hw);
1432 /* read out interrupt causes */
1433 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1435 /* No interrupt event indicated */
1436 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1437 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1441 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1442 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1443 i40evf_handle_aq_msg(dev);
1446 /* Link Status Change interrupt */
1447 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1448 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1452 i40evf_enable_irq0(hw);
1453 rte_intr_enable(intr_handle);
1457 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1460 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1461 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(eth_dev);
1463 PMD_INIT_FUNC_TRACE();
1465 /* assign ops func pointer */
1466 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1467 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1468 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1471 * For secondary processes, we don't initialise any further as primary
1472 * has already done this work.
1474 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1475 i40e_set_rx_function(eth_dev);
1476 i40e_set_tx_function(eth_dev);
1480 rte_eth_copy_pci_info(eth_dev, pci_dev);
1481 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1483 hw->vendor_id = pci_dev->id.vendor_id;
1484 hw->device_id = pci_dev->id.device_id;
1485 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1486 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1487 hw->bus.device = pci_dev->addr.devid;
1488 hw->bus.func = pci_dev->addr.function;
1489 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1490 hw->adapter_stopped = 0;
1492 if(i40evf_init_vf(eth_dev) != 0) {
1493 PMD_INIT_LOG(ERR, "Init vf failed");
1497 /* register callback func to eal lib */
1498 rte_intr_callback_register(&pci_dev->intr_handle,
1499 i40evf_dev_interrupt_handler, (void *)eth_dev);
1501 /* enable uio intr after callback register */
1502 rte_intr_enable(&pci_dev->intr_handle);
1504 /* configure and enable device interrupt */
1505 i40evf_enable_irq0(hw);
1508 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1509 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1511 if (eth_dev->data->mac_addrs == NULL) {
1512 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1513 " store MAC addresses",
1514 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1517 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1518 ð_dev->data->mac_addrs[0]);
1524 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1526 PMD_INIT_FUNC_TRACE();
1528 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1531 eth_dev->dev_ops = NULL;
1532 eth_dev->rx_pkt_burst = NULL;
1533 eth_dev->tx_pkt_burst = NULL;
1535 if (i40evf_uninit_vf(eth_dev) != 0) {
1536 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1540 rte_free(eth_dev->data->mac_addrs);
1541 eth_dev->data->mac_addrs = NULL;
1546 * virtual function driver struct
1548 static struct eth_driver rte_i40evf_pmd = {
1550 .id_table = pci_id_i40evf_map,
1551 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1552 .probe = rte_eth_dev_pci_probe,
1553 .remove = rte_eth_dev_pci_remove,
1555 .eth_dev_init = i40evf_dev_init,
1556 .eth_dev_uninit = i40evf_dev_uninit,
1557 .dev_private_size = sizeof(struct i40e_adapter),
1560 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1561 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1562 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1565 i40evf_dev_configure(struct rte_eth_dev *dev)
1567 struct i40e_adapter *ad =
1568 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1569 struct rte_eth_conf *conf = &dev->data->dev_conf;
1572 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1573 * allocation or vector Rx preconditions we will reset it.
1575 ad->rx_bulk_alloc_allowed = true;
1576 ad->rx_vec_allowed = true;
1577 ad->tx_simple_allowed = true;
1578 ad->tx_vec_allowed = true;
1580 /* For non-DPDK PF drivers, VF has no ability to disable HW
1581 * CRC strip, and is implicitly enabled by the PF.
1583 if (!conf->rxmode.hw_strip_crc) {
1584 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1585 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1586 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1587 /* Peer is running non-DPDK PF driver. */
1588 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1593 return i40evf_init_vlan(dev);
1597 i40evf_init_vlan(struct rte_eth_dev *dev)
1599 struct rte_eth_dev_data *data = dev->data;
1602 /* Apply vlan offload setting */
1603 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1605 /* Apply pvid setting */
1606 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1607 data->dev_conf.txmode.hw_vlan_insert_pvid);
1612 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1614 bool enable_vlan_strip = 0;
1615 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1616 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1618 /* Linux pf host doesn't support vlan offload yet */
1619 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1620 /* Vlan stripping setting */
1621 if (mask & ETH_VLAN_STRIP_MASK) {
1622 /* Enable or disable VLAN stripping */
1623 if (dev_conf->rxmode.hw_vlan_strip)
1624 enable_vlan_strip = 1;
1626 enable_vlan_strip = 0;
1628 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1634 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1636 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1637 struct i40e_vsi_vlan_pvid_info info;
1638 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1640 memset(&info, 0, sizeof(info));
1643 /* Linux pf host don't support vlan offload yet */
1644 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1646 info.config.pvid = pvid;
1648 info.config.reject.tagged =
1649 dev_conf->txmode.hw_vlan_reject_tagged;
1650 info.config.reject.untagged =
1651 dev_conf->txmode.hw_vlan_reject_untagged;
1653 return i40evf_config_vlan_pvid(dev, &info);
1660 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1662 struct i40e_rx_queue *rxq;
1664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 PMD_INIT_FUNC_TRACE();
1668 if (rx_queue_id < dev->data->nb_rx_queues) {
1669 rxq = dev->data->rx_queues[rx_queue_id];
1671 err = i40e_alloc_rx_queue_mbufs(rxq);
1673 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1679 /* Init the RX tail register. */
1680 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1681 I40EVF_WRITE_FLUSH(hw);
1683 /* Ready to switch the queue on */
1684 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1687 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1690 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1697 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1699 struct i40e_rx_queue *rxq;
1702 if (rx_queue_id < dev->data->nb_rx_queues) {
1703 rxq = dev->data->rx_queues[rx_queue_id];
1705 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1708 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1713 i40e_rx_queue_release_mbufs(rxq);
1714 i40e_reset_rx_queue(rxq);
1715 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1722 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1726 PMD_INIT_FUNC_TRACE();
1728 if (tx_queue_id < dev->data->nb_tx_queues) {
1730 /* Ready to switch the queue on */
1731 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1734 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1737 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1744 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1746 struct i40e_tx_queue *txq;
1749 if (tx_queue_id < dev->data->nb_tx_queues) {
1750 txq = dev->data->tx_queues[tx_queue_id];
1752 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1755 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1760 i40e_tx_queue_release_mbufs(txq);
1761 i40e_reset_tx_queue(txq);
1762 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1769 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1774 ret = i40evf_add_vlan(dev, vlan_id);
1776 ret = i40evf_del_vlan(dev,vlan_id);
1782 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1785 struct rte_eth_dev_data *dev_data = dev->data;
1786 struct rte_pktmbuf_pool_private *mbp_priv;
1787 uint16_t buf_size, len;
1789 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1790 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1791 I40EVF_WRITE_FLUSH(hw);
1793 /* Calculate the maximum packet length allowed */
1794 mbp_priv = rte_mempool_get_priv(rxq->mp);
1795 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1796 RTE_PKTMBUF_HEADROOM);
1797 rxq->hs_mode = i40e_header_split_none;
1798 rxq->rx_hdr_len = 0;
1799 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1800 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1801 rxq->max_pkt_len = RTE_MIN(len,
1802 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1805 * Check if the jumbo frame and maximum packet length are set correctly
1807 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1808 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1809 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1810 PMD_DRV_LOG(ERR, "maximum packet length must be "
1811 "larger than %u and smaller than %u, as jumbo "
1812 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1813 (uint32_t)I40E_FRAME_SIZE_MAX);
1814 return I40E_ERR_CONFIG;
1817 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1818 rxq->max_pkt_len > ETHER_MAX_LEN) {
1819 PMD_DRV_LOG(ERR, "maximum packet length must be "
1820 "larger than %u and smaller than %u, as jumbo "
1821 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1822 (uint32_t)ETHER_MAX_LEN);
1823 return I40E_ERR_CONFIG;
1827 if (dev_data->dev_conf.rxmode.enable_scatter ||
1828 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1829 dev_data->scattered_rx = 1;
1836 i40evf_rx_init(struct rte_eth_dev *dev)
1838 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1840 int ret = I40E_SUCCESS;
1841 struct i40e_rx_queue **rxq =
1842 (struct i40e_rx_queue **)dev->data->rx_queues;
1844 i40evf_config_rss(vf);
1845 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1846 if (!rxq[i] || !rxq[i]->q_set)
1848 ret = i40evf_rxq_init(dev, rxq[i]);
1849 if (ret != I40E_SUCCESS)
1852 if (ret == I40E_SUCCESS)
1853 i40e_set_rx_function(dev);
1859 i40evf_tx_init(struct rte_eth_dev *dev)
1862 struct i40e_tx_queue **txq =
1863 (struct i40e_tx_queue **)dev->data->tx_queues;
1864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866 for (i = 0; i < dev->data->nb_tx_queues; i++)
1867 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1869 i40e_set_tx_function(dev);
1873 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1875 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1876 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1878 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1880 if (!rte_intr_allow_others(intr_handle)) {
1882 I40E_VFINT_DYN_CTL01,
1883 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1884 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1885 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1886 I40EVF_WRITE_FLUSH(hw);
1890 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1891 /* To support DPDK PF host */
1893 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1894 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1895 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1896 /* If host driver is kernel driver, do nothing.
1897 * Interrupt 0 is used for rx packets, but don't set
1898 * I40E_VFINT_DYN_CTL01,
1899 * because it is already done in i40evf_enable_irq0.
1902 I40EVF_WRITE_FLUSH(hw);
1906 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1908 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1911 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1913 if (!rte_intr_allow_others(intr_handle)) {
1914 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1915 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1916 I40EVF_WRITE_FLUSH(hw);
1920 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1922 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1925 /* If host driver is kernel driver, do nothing.
1926 * Interrupt 0 is used for rx packets, but don't zero
1927 * I40E_VFINT_DYN_CTL01,
1928 * because interrupt 0 is also used for adminq processing.
1931 I40EVF_WRITE_FLUSH(hw);
1935 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1937 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1938 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1944 msix_intr = intr_handle->intr_vec[queue_id];
1945 if (msix_intr == I40E_MISC_VEC_ID)
1946 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1947 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1948 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1949 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1951 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1954 I40E_VFINT_DYN_CTLN1(msix_intr -
1956 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1957 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1958 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1960 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1962 I40EVF_WRITE_FLUSH(hw);
1964 rte_intr_enable(&pci_dev->intr_handle);
1970 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1972 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1973 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977 msix_intr = intr_handle->intr_vec[queue_id];
1978 if (msix_intr == I40E_MISC_VEC_ID)
1979 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1982 I40E_VFINT_DYN_CTLN1(msix_intr -
1986 I40EVF_WRITE_FLUSH(hw);
1992 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1994 struct i40e_virtchnl_ether_addr_list *list;
1995 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2000 struct ether_addr *addr;
2001 struct vf_cmd_info args;
2005 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2006 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2007 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2009 len += sizeof(struct i40e_virtchnl_ether_addr);
2010 if (len >= I40E_AQ_BUF_SZ) {
2016 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2018 for (i = begin; i < next_begin; i++) {
2019 addr = &dev->data->mac_addrs[i];
2020 if (is_zero_ether_addr(addr))
2022 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2023 sizeof(addr->addr_bytes));
2024 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2025 addr->addr_bytes[0], addr->addr_bytes[1],
2026 addr->addr_bytes[2], addr->addr_bytes[3],
2027 addr->addr_bytes[4], addr->addr_bytes[5]);
2030 list->vsi_id = vf->vsi_res->vsi_id;
2031 list->num_elements = j;
2032 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2033 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2034 args.in_args = (uint8_t *)list;
2035 args.in_args_size = len;
2036 args.out_buffer = vf->aq_resp;
2037 args.out_size = I40E_AQ_BUF_SZ;
2038 err = i40evf_execute_vf_cmd(dev, &args);
2040 PMD_DRV_LOG(ERR, "fail to execute command %s",
2041 add ? "OP_ADD_ETHER_ADDRESS" :
2042 "OP_DEL_ETHER_ADDRESS");
2045 } while (begin < I40E_NUM_MACADDR_MAX);
2049 i40evf_dev_start(struct rte_eth_dev *dev)
2051 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2052 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 uint32_t intr_vector = 0;
2057 PMD_INIT_FUNC_TRACE();
2059 hw->adapter_stopped = 0;
2061 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2062 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2063 dev->data->nb_tx_queues);
2065 /* check and configure queue intr-vector mapping */
2066 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2067 intr_vector = dev->data->nb_rx_queues;
2068 if (rte_intr_efd_enable(intr_handle, intr_vector))
2072 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2073 intr_handle->intr_vec =
2074 rte_zmalloc("intr_vec",
2075 dev->data->nb_rx_queues * sizeof(int), 0);
2076 if (!intr_handle->intr_vec) {
2077 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2078 " intr_vec", dev->data->nb_rx_queues);
2083 if (i40evf_rx_init(dev) != 0){
2084 PMD_DRV_LOG(ERR, "failed to do RX init");
2088 i40evf_tx_init(dev);
2090 if (i40evf_configure_queues(dev) != 0) {
2091 PMD_DRV_LOG(ERR, "configure queues failed");
2094 if (i40evf_config_irq_map(dev)) {
2095 PMD_DRV_LOG(ERR, "config_irq_map failed");
2099 /* Set all mac addrs */
2100 i40evf_add_del_all_mac_addr(dev, TRUE);
2102 if (i40evf_start_queues(dev) != 0) {
2103 PMD_DRV_LOG(ERR, "enable queues failed");
2107 i40evf_enable_queues_intr(dev);
2111 i40evf_add_del_all_mac_addr(dev, FALSE);
2117 i40evf_dev_stop(struct rte_eth_dev *dev)
2119 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2120 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122 PMD_INIT_FUNC_TRACE();
2124 i40evf_stop_queues(dev);
2125 i40evf_disable_queues_intr(dev);
2126 i40e_dev_clear_queues(dev);
2128 /* Clean datapath event and queue/vec mapping */
2129 rte_intr_efd_disable(intr_handle);
2130 if (intr_handle->intr_vec) {
2131 rte_free(intr_handle->intr_vec);
2132 intr_handle->intr_vec = NULL;
2134 /* remove all mac addrs */
2135 i40evf_add_del_all_mac_addr(dev, FALSE);
2140 i40evf_dev_link_update(struct rte_eth_dev *dev,
2141 __rte_unused int wait_to_complete)
2143 struct rte_eth_link new_link;
2144 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2146 * DPDK pf host provide interfacet to acquire link status
2147 * while Linux driver does not
2150 /* Linux driver PF host */
2151 switch (vf->link_speed) {
2152 case I40E_LINK_SPEED_100MB:
2153 new_link.link_speed = ETH_SPEED_NUM_100M;
2155 case I40E_LINK_SPEED_1GB:
2156 new_link.link_speed = ETH_SPEED_NUM_1G;
2158 case I40E_LINK_SPEED_10GB:
2159 new_link.link_speed = ETH_SPEED_NUM_10G;
2161 case I40E_LINK_SPEED_20GB:
2162 new_link.link_speed = ETH_SPEED_NUM_20G;
2164 case I40E_LINK_SPEED_40GB:
2165 new_link.link_speed = ETH_SPEED_NUM_40G;
2168 new_link.link_speed = ETH_SPEED_NUM_100M;
2171 /* full duplex only */
2172 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2173 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2176 i40evf_dev_atomic_write_link_status(dev, &new_link);
2182 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2184 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2187 /* If enabled, just return */
2188 if (vf->promisc_unicast_enabled)
2191 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2193 vf->promisc_unicast_enabled = TRUE;
2197 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2202 /* If disabled, just return */
2203 if (!vf->promisc_unicast_enabled)
2206 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2208 vf->promisc_unicast_enabled = FALSE;
2212 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2214 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2217 /* If enabled, just return */
2218 if (vf->promisc_multicast_enabled)
2221 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2223 vf->promisc_multicast_enabled = TRUE;
2227 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2232 /* If enabled, just return */
2233 if (!vf->promisc_multicast_enabled)
2236 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2238 vf->promisc_multicast_enabled = FALSE;
2242 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2244 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2246 memset(dev_info, 0, sizeof(*dev_info));
2247 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2248 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2249 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2250 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2251 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2252 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2253 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2254 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2255 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2256 dev_info->rx_offload_capa =
2257 DEV_RX_OFFLOAD_VLAN_STRIP |
2258 DEV_RX_OFFLOAD_QINQ_STRIP |
2259 DEV_RX_OFFLOAD_IPV4_CKSUM |
2260 DEV_RX_OFFLOAD_UDP_CKSUM |
2261 DEV_RX_OFFLOAD_TCP_CKSUM;
2262 dev_info->tx_offload_capa =
2263 DEV_TX_OFFLOAD_VLAN_INSERT |
2264 DEV_TX_OFFLOAD_QINQ_INSERT |
2265 DEV_TX_OFFLOAD_IPV4_CKSUM |
2266 DEV_TX_OFFLOAD_UDP_CKSUM |
2267 DEV_TX_OFFLOAD_TCP_CKSUM |
2268 DEV_TX_OFFLOAD_SCTP_CKSUM;
2270 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2272 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2273 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2274 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2276 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2280 dev_info->default_txconf = (struct rte_eth_txconf) {
2282 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2283 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2284 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2286 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2287 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2288 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2289 ETH_TXQ_FLAGS_NOOFFLOADS,
2292 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2293 .nb_max = I40E_MAX_RING_DESC,
2294 .nb_min = I40E_MIN_RING_DESC,
2295 .nb_align = I40E_ALIGN_RING_DESC,
2298 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2299 .nb_max = I40E_MAX_RING_DESC,
2300 .nb_min = I40E_MIN_RING_DESC,
2301 .nb_align = I40E_ALIGN_RING_DESC,
2306 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2308 if (i40evf_get_statistics(dev, stats))
2309 PMD_DRV_LOG(ERR, "Get statistics failed");
2313 i40evf_dev_close(struct rte_eth_dev *dev)
2315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2317 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319 i40evf_dev_stop(dev);
2320 hw->adapter_stopped = 1;
2321 i40e_dev_free_queues(dev);
2322 i40evf_reset_vf(hw);
2323 i40e_shutdown_adminq(hw);
2324 /* disable uio intr before callback unregister */
2325 rte_intr_disable(intr_handle);
2327 /* unregister callback func from eal lib */
2328 rte_intr_callback_unregister(intr_handle,
2329 i40evf_dev_interrupt_handler, dev);
2330 i40evf_disable_irq0(hw);
2334 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2336 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2337 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2343 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2344 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2347 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2351 uint32_t *lut_dw = (uint32_t *)lut;
2352 uint16_t i, lut_size_dw = lut_size / 4;
2354 for (i = 0; i < lut_size_dw; i++)
2355 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2362 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2371 vf = I40E_VSI_TO_VF(vsi);
2372 hw = I40E_VSI_TO_HW(vsi);
2374 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2375 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2378 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2382 uint32_t *lut_dw = (uint32_t *)lut;
2383 uint16_t i, lut_size_dw = lut_size / 4;
2385 for (i = 0; i < lut_size_dw; i++)
2386 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2387 I40EVF_WRITE_FLUSH(hw);
2394 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2395 struct rte_eth_rss_reta_entry64 *reta_conf,
2398 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2400 uint16_t i, idx, shift;
2403 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2404 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2405 "(%d) doesn't match the number of hardware can "
2406 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2410 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2412 PMD_DRV_LOG(ERR, "No memory can be allocated");
2415 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2418 for (i = 0; i < reta_size; i++) {
2419 idx = i / RTE_RETA_GROUP_SIZE;
2420 shift = i % RTE_RETA_GROUP_SIZE;
2421 if (reta_conf[idx].mask & (1ULL << shift))
2422 lut[i] = reta_conf[idx].reta[shift];
2424 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2433 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2434 struct rte_eth_rss_reta_entry64 *reta_conf,
2437 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2438 uint16_t i, idx, shift;
2442 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2443 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2444 "(%d) doesn't match the number of hardware can "
2445 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2449 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2451 PMD_DRV_LOG(ERR, "No memory can be allocated");
2455 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2458 for (i = 0; i < reta_size; i++) {
2459 idx = i / RTE_RETA_GROUP_SIZE;
2460 shift = i % RTE_RETA_GROUP_SIZE;
2461 if (reta_conf[idx].mask & (1ULL << shift))
2462 reta_conf[idx].reta[shift] = lut[i];
2472 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2474 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2475 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2478 if (!key || key_len == 0) {
2479 PMD_DRV_LOG(DEBUG, "No key to be configured");
2481 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2483 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2487 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2488 struct i40e_aqc_get_set_rss_key_data *key_dw =
2489 (struct i40e_aqc_get_set_rss_key_data *)key;
2491 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2493 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2496 uint32_t *hash_key = (uint32_t *)key;
2499 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2500 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2501 I40EVF_WRITE_FLUSH(hw);
2508 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2510 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2511 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2514 if (!key || !key_len)
2517 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2518 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2519 (struct i40e_aqc_get_set_rss_key_data *)key);
2521 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2525 uint32_t *key_dw = (uint32_t *)key;
2528 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2529 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2531 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2537 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2539 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2540 uint64_t rss_hf, hena;
2543 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2544 rss_conf->rss_key_len);
2548 rss_hf = rss_conf->rss_hf;
2549 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2550 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2551 if (hw->mac.type == I40E_MAC_X722)
2552 hena &= ~I40E_RSS_HENA_ALL_X722;
2554 hena &= ~I40E_RSS_HENA_ALL;
2555 hena |= i40e_config_hena(rss_hf, hw->mac.type);
2556 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2557 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2558 I40EVF_WRITE_FLUSH(hw);
2564 i40evf_disable_rss(struct i40e_vf *vf)
2566 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2569 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2570 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2571 if (hw->mac.type == I40E_MAC_X722)
2572 hena &= ~I40E_RSS_HENA_ALL_X722;
2574 hena &= ~I40E_RSS_HENA_ALL;
2575 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2576 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2577 I40EVF_WRITE_FLUSH(hw);
2581 i40evf_config_rss(struct i40e_vf *vf)
2583 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2584 struct rte_eth_rss_conf rss_conf;
2585 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2588 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2589 i40evf_disable_rss(vf);
2590 PMD_DRV_LOG(DEBUG, "RSS not configured");
2594 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2595 /* Fill out the look up table */
2596 for (i = 0, j = 0; i < nb_q; i++, j++) {
2599 lut = (lut << 8) | j;
2601 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2604 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2605 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2606 i40evf_disable_rss(vf);
2607 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2611 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2612 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2613 /* Calculate the default hash key */
2614 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2615 rss_key_default[i] = (uint32_t)rte_rand();
2616 rss_conf.rss_key = (uint8_t *)rss_key_default;
2617 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2621 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2625 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2626 struct rte_eth_rss_conf *rss_conf)
2628 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2629 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2633 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2634 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2635 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2636 ? I40E_RSS_HENA_ALL_X722
2637 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2638 if (rss_hf != 0) /* Enable RSS */
2644 if (rss_hf == 0) /* Disable RSS */
2647 return i40evf_hw_rss_hash_set(vf, rss_conf);
2651 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2652 struct rte_eth_rss_conf *rss_conf)
2654 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2659 &rss_conf->rss_key_len);
2661 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2662 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2663 rss_conf->rss_hf = i40e_parse_hena(hena);
2669 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2671 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2672 struct rte_eth_dev_data *dev_data = vf->dev_data;
2673 uint32_t frame_size = mtu + ETHER_HDR_LEN
2674 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
2677 /* check if mtu is within the allowed range */
2678 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2681 /* mtu setting is forbidden if port is start */
2682 if (dev_data->dev_started) {
2683 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2688 if (frame_size > ETHER_MAX_LEN)
2689 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2691 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2693 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2699 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2700 struct ether_addr *mac_addr)
2702 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2704 if (!is_valid_assigned_ether_addr(mac_addr)) {
2705 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2709 if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2712 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2715 i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2717 i40evf_add_mac_addr(dev, mac_addr, 0, 0);