1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_byteorder.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
17 #include <rte_interrupts.h>
19 #include <rte_debug.h>
21 #include <rte_bus_pci.h>
22 #include <rte_atomic.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <ethdev_driver.h>
29 #include <ethdev_pci.h>
30 #include <rte_malloc.h>
33 #include "i40e_logs.h"
34 #include "base/i40e_prototype.h"
35 #include "base/i40e_adminq_cmd.h"
36 #include "base/i40e_type.h"
38 #include "i40e_rxtx.h"
39 #include "i40e_ethdev.h"
42 /* busy wait delay in msec */
43 #define I40EVF_BUSY_WAIT_DELAY 10
44 #define I40EVF_BUSY_WAIT_COUNT 50
45 #define MAX_RESET_WAIT_CNT 20
47 #define I40EVF_ALARM_INTERVAL 50000 /* us */
49 struct i40evf_arq_msg_info {
50 enum virtchnl_ops ops;
51 enum i40e_status_code result;
58 enum virtchnl_ops ops;
60 uint32_t in_args_size;
62 /* Input & output type. pass in buffer size and pass out
63 * actual return result
68 enum i40evf_aq_result {
69 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
70 I40EVF_MSG_NON, /* Read nothing from admin queue */
71 I40EVF_MSG_SYS, /* Read system msg from admin queue */
72 I40EVF_MSG_CMD, /* Read async command result */
75 static int i40evf_dev_configure(struct rte_eth_dev *dev);
76 static int i40evf_dev_start(struct rte_eth_dev *dev);
77 static int i40evf_dev_stop(struct rte_eth_dev *dev);
78 static int i40evf_dev_info_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *stats);
84 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned n);
86 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
87 struct rte_eth_xstat_name *xstats_names,
89 static int i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
90 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vlan_id, int on);
92 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static int i40evf_dev_close(struct rte_eth_dev *dev);
94 static int i40evf_dev_reset(struct rte_eth_dev *dev);
95 static int i40evf_check_vf_reset_done(struct rte_eth_dev *dev);
96 static int i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static int i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static int i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static int i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int i40evf_init_vlan(struct rte_eth_dev *dev);
101 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
102 uint16_t rx_queue_id);
103 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
104 uint16_t rx_queue_id);
105 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
106 uint16_t tx_queue_id);
107 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
108 uint16_t tx_queue_id);
109 static int i40evf_add_del_eth_addr(struct rte_eth_dev *dev,
110 struct rte_ether_addr *addr,
111 bool add, uint8_t type);
112 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
113 struct rte_ether_addr *addr,
116 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
117 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
118 struct rte_eth_rss_reta_entry64 *reta_conf,
120 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
121 struct rte_eth_rss_reta_entry64 *reta_conf,
123 static int i40evf_config_rss(struct i40e_vf *vf);
124 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
125 struct rte_eth_rss_conf *rss_conf);
126 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
127 struct rte_eth_rss_conf *rss_conf);
128 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
129 static int i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
130 struct rte_ether_addr *mac_addr);
132 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
134 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
135 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
140 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
141 struct rte_ether_addr *mc_addr_set,
142 uint32_t nb_mc_addr, bool add);
144 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
145 struct rte_ether_addr *mc_addr_set,
146 uint32_t nb_mc_addr);
148 i40evf_dev_alarm_handler(void *param);
150 /* Default hash key buffer for RSS */
151 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
153 struct rte_i40evf_xstats_name_off {
154 char name[RTE_ETH_XSTATS_NAME_SIZE];
158 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
159 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
160 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
161 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
162 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
163 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
164 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
165 rx_unknown_protocol)},
166 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
167 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
168 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
169 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
170 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
171 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
174 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
175 sizeof(rte_i40evf_stats_strings[0]))
177 static const struct eth_dev_ops i40evf_eth_dev_ops = {
178 .dev_configure = i40evf_dev_configure,
179 .dev_start = i40evf_dev_start,
180 .dev_stop = i40evf_dev_stop,
181 .promiscuous_enable = i40evf_dev_promiscuous_enable,
182 .promiscuous_disable = i40evf_dev_promiscuous_disable,
183 .allmulticast_enable = i40evf_dev_allmulticast_enable,
184 .allmulticast_disable = i40evf_dev_allmulticast_disable,
185 .link_update = i40evf_dev_link_update,
186 .stats_get = i40evf_dev_stats_get,
187 .stats_reset = i40evf_dev_xstats_reset,
188 .xstats_get = i40evf_dev_xstats_get,
189 .xstats_get_names = i40evf_dev_xstats_get_names,
190 .xstats_reset = i40evf_dev_xstats_reset,
191 .dev_close = i40evf_dev_close,
192 .dev_reset = i40evf_dev_reset,
193 .dev_infos_get = i40evf_dev_info_get,
194 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
195 .vlan_filter_set = i40evf_vlan_filter_set,
196 .vlan_offload_set = i40evf_vlan_offload_set,
197 .rx_queue_start = i40evf_dev_rx_queue_start,
198 .rx_queue_stop = i40evf_dev_rx_queue_stop,
199 .tx_queue_start = i40evf_dev_tx_queue_start,
200 .tx_queue_stop = i40evf_dev_tx_queue_stop,
201 .rx_queue_setup = i40e_dev_rx_queue_setup,
202 .rx_queue_release = i40e_dev_rx_queue_release,
203 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
204 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
205 .tx_queue_setup = i40e_dev_tx_queue_setup,
206 .tx_queue_release = i40e_dev_tx_queue_release,
207 .rxq_info_get = i40e_rxq_info_get,
208 .txq_info_get = i40e_txq_info_get,
209 .mac_addr_add = i40evf_add_mac_addr,
210 .mac_addr_remove = i40evf_del_mac_addr,
211 .set_mc_addr_list = i40evf_set_mc_addr_list,
212 .reta_update = i40evf_dev_rss_reta_update,
213 .reta_query = i40evf_dev_rss_reta_query,
214 .rss_hash_update = i40evf_dev_rss_hash_update,
215 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
216 .mtu_set = i40evf_dev_mtu_set,
217 .mac_addr_set = i40evf_set_default_mac_addr,
218 .tx_done_cleanup = i40e_tx_done_cleanup,
219 .get_monitor_addr = i40e_get_monitor_addr
223 * Read data in admin queue to get msg from pf driver
225 static enum i40evf_aq_result
226 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
229 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
230 struct i40e_arq_event_info event;
231 enum virtchnl_ops opcode;
232 enum i40e_status_code retval;
234 enum i40evf_aq_result result = I40EVF_MSG_NON;
236 event.buf_len = data->buf_len;
237 event.msg_buf = data->msg;
238 ret = i40e_clean_arq_element(hw, &event, NULL);
239 /* Can't read any msg from adminQ */
241 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
242 result = I40EVF_MSG_ERR;
246 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
247 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
249 if (opcode == VIRTCHNL_OP_EVENT) {
250 struct virtchnl_pf_event *vpe =
251 (struct virtchnl_pf_event *)event.msg_buf;
253 result = I40EVF_MSG_SYS;
254 switch (vpe->event) {
255 case VIRTCHNL_EVENT_LINK_CHANGE:
257 vpe->event_data.link_event.link_status;
259 vpe->event_data.link_event.link_speed;
260 vf->pend_msg |= PFMSG_LINK_CHANGE;
261 PMD_DRV_LOG(INFO, "Link status update:%s",
262 vf->link_up ? "up" : "down");
264 case VIRTCHNL_EVENT_RESET_IMPENDING:
266 vf->pend_msg |= PFMSG_RESET_IMPENDING;
267 PMD_DRV_LOG(INFO, "VF is resetting");
269 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
270 vf->dev_closed = true;
271 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
272 PMD_DRV_LOG(INFO, "PF driver closed");
275 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
276 __func__, vpe->event);
279 /* async reply msg on command issued by vf previously */
280 result = I40EVF_MSG_CMD;
281 /* Actual data length read from PF */
282 data->msg_len = event.msg_len;
285 data->result = retval;
292 * clear current command. Only call in case execute
293 * _atomic_set_cmd successfully.
296 _clear_cmd(struct i40e_vf *vf)
299 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
303 * Check there is pending cmd in execution. If none, set new command.
306 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
308 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
309 VIRTCHNL_OP_UNKNOWN, ops);
312 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
317 #define MAX_TRY_TIMES 200
318 #define ASQ_DELAY_MS 10
321 _i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
323 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
324 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
325 struct i40evf_arq_msg_info info;
326 enum i40evf_aq_result ret;
329 if (_atomic_set_cmd(vf, args->ops))
332 info.msg = args->out_buffer;
333 info.buf_len = args->out_size;
334 info.ops = VIRTCHNL_OP_UNKNOWN;
335 info.result = I40E_SUCCESS;
337 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
338 args->in_args, args->in_args_size, NULL);
340 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
346 case VIRTCHNL_OP_RESET_VF:
347 /*no need to process in this function */
350 case VIRTCHNL_OP_VERSION:
351 case VIRTCHNL_OP_GET_VF_RESOURCES:
352 /* for init adminq commands, need to poll the response */
355 ret = i40evf_read_pfmsg(dev, &info);
356 vf->cmd_retval = info.result;
357 if (ret == I40EVF_MSG_CMD) {
360 } else if (ret == I40EVF_MSG_ERR)
362 rte_delay_ms(ASQ_DELAY_MS);
363 /* If don't read msg or read sys event, continue */
364 } while (i++ < MAX_TRY_TIMES);
367 case VIRTCHNL_OP_REQUEST_QUEUES:
369 * ignore async reply, only wait for system message,
370 * vf_reset = true if get VIRTCHNL_EVENT_RESET_IMPENDING,
371 * if not, means request queues failed.
375 ret = i40evf_read_pfmsg(dev, &info);
376 vf->cmd_retval = info.result;
377 if (ret == I40EVF_MSG_SYS && vf->vf_reset) {
380 } else if (ret == I40EVF_MSG_ERR ||
381 ret == I40EVF_MSG_CMD) {
384 rte_delay_ms(ASQ_DELAY_MS);
385 /* If don't read msg or read sys event, continue */
386 } while (i++ < MAX_TRY_TIMES);
391 /* for other adminq in running time, waiting the cmd done flag */
394 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
398 rte_delay_ms(ASQ_DELAY_MS);
399 /* If don't read msg or read sys event, continue */
400 } while (i++ < MAX_TRY_TIMES);
401 /* If there's no response is received, clear command */
402 if (i >= MAX_TRY_TIMES) {
403 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
409 return err | vf->cmd_retval;
413 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
415 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
418 while (!rte_spinlock_trylock(&vf->cmd_send_lock))
419 rte_delay_us_sleep(50);
420 err = _i40evf_execute_vf_cmd(dev, args);
421 rte_spinlock_unlock(&vf->cmd_send_lock);
426 * Check API version with sync wait until version read or fail from admin queue
429 i40evf_check_api_version(struct rte_eth_dev *dev)
431 struct virtchnl_version_info version, *pver;
433 struct vf_cmd_info args;
434 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
436 version.major = VIRTCHNL_VERSION_MAJOR;
437 version.minor = VIRTCHNL_VERSION_MINOR;
439 args.ops = VIRTCHNL_OP_VERSION;
440 args.in_args = (uint8_t *)&version;
441 args.in_args_size = sizeof(version);
442 args.out_buffer = vf->aq_resp;
443 args.out_size = I40E_AQ_BUF_SZ;
445 err = i40evf_execute_vf_cmd(dev, &args);
447 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
451 pver = (struct virtchnl_version_info *)args.out_buffer;
452 vf->version_major = pver->major;
453 vf->version_minor = pver->minor;
454 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
455 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
456 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
458 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
459 vf->version_major, vf->version_minor,
460 VIRTCHNL_VERSION_MAJOR,
461 VIRTCHNL_VERSION_MINOR);
469 i40evf_get_vf_resource(struct rte_eth_dev *dev)
471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
472 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
474 struct vf_cmd_info args;
477 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
478 args.out_buffer = vf->aq_resp;
479 args.out_size = I40E_AQ_BUF_SZ;
481 caps = VIRTCHNL_VF_OFFLOAD_L2 |
482 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
483 VIRTCHNL_VF_OFFLOAD_RSS_REG |
484 VIRTCHNL_VF_OFFLOAD_VLAN |
485 VIRTCHNL_VF_OFFLOAD_RX_POLLING |
486 VIRTCHNL_VF_CAP_ADV_LINK_SPEED;
487 args.in_args = (uint8_t *)∩︀
488 args.in_args_size = sizeof(caps);
491 args.in_args_size = 0;
493 err = i40evf_execute_vf_cmd(dev, &args);
496 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
500 len = sizeof(struct virtchnl_vf_resource) +
501 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
503 rte_memcpy(vf->vf_res, args.out_buffer,
504 RTE_MIN(args.out_size, len));
505 i40e_vf_parse_hw_config(hw, vf->vf_res);
511 i40evf_config_promisc(struct rte_eth_dev *dev,
513 bool enable_multicast)
515 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
517 struct vf_cmd_info args;
518 struct virtchnl_promisc_info promisc;
521 promisc.vsi_id = vf->vsi_res->vsi_id;
524 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
526 if (enable_multicast)
527 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
529 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
530 args.in_args = (uint8_t *)&promisc;
531 args.in_args_size = sizeof(promisc);
532 args.out_buffer = vf->aq_resp;
533 args.out_size = I40E_AQ_BUF_SZ;
535 err = i40evf_execute_vf_cmd(dev, &args);
538 PMD_DRV_LOG(ERR, "fail to execute command "
539 "CONFIG_PROMISCUOUS_MODE");
541 if (err == I40E_NOT_SUPPORTED)
547 vf->promisc_unicast_enabled = enable_unicast;
548 vf->promisc_multicast_enabled = enable_multicast;
553 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
555 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
556 struct vf_cmd_info args;
559 memset(&args, 0, sizeof(args));
560 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
562 args.in_args_size = 0;
563 args.out_buffer = vf->aq_resp;
564 args.out_size = I40E_AQ_BUF_SZ;
565 ret = i40evf_execute_vf_cmd(dev, &args);
567 PMD_DRV_LOG(ERR, "Failed to execute command of "
568 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
574 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
576 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
577 struct vf_cmd_info args;
580 memset(&args, 0, sizeof(args));
581 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
583 args.in_args_size = 0;
584 args.out_buffer = vf->aq_resp;
585 args.out_size = I40E_AQ_BUF_SZ;
586 ret = i40evf_execute_vf_cmd(dev, &args);
588 PMD_DRV_LOG(ERR, "Failed to execute command of "
589 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
595 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
599 struct i40e_tx_queue *txq)
601 txq_info->vsi_id = vsi_id;
602 txq_info->queue_id = queue_id;
603 if (queue_id < nb_txq && txq) {
604 txq_info->ring_len = txq->nb_tx_desc;
605 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
610 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
614 uint32_t max_pkt_size,
615 struct i40e_rx_queue *rxq)
617 rxq_info->vsi_id = vsi_id;
618 rxq_info->queue_id = queue_id;
619 rxq_info->max_pkt_size = max_pkt_size;
620 if (queue_id < nb_rxq && rxq) {
621 rxq_info->ring_len = rxq->nb_rx_desc;
622 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
623 rxq_info->databuffer_size =
624 (rte_pktmbuf_data_room_size(rxq->mp) -
625 RTE_PKTMBUF_HEADROOM);
630 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
632 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
633 struct i40e_rx_queue **rxq =
634 (struct i40e_rx_queue **)dev->data->rx_queues;
635 struct i40e_tx_queue **txq =
636 (struct i40e_tx_queue **)dev->data->tx_queues;
637 struct virtchnl_vsi_queue_config_info *vc_vqci;
638 struct virtchnl_queue_pair_info *vc_qpi;
639 struct vf_cmd_info args;
640 uint16_t i, nb_qp = vf->num_queue_pairs;
641 const uint32_t size =
642 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
646 memset(buff, 0, sizeof(buff));
647 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
648 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
649 vc_vqci->num_queue_pairs = nb_qp;
651 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
652 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
653 vc_vqci->vsi_id, i, dev->data->nb_tx_queues,
654 txq ? txq[i] : NULL);
655 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
656 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
657 vf->max_pkt_len, rxq ? rxq[i] : NULL);
659 memset(&args, 0, sizeof(args));
660 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
661 args.in_args = (uint8_t *)vc_vqci;
662 args.in_args_size = size;
663 args.out_buffer = vf->aq_resp;
664 args.out_size = I40E_AQ_BUF_SZ;
665 ret = i40evf_execute_vf_cmd(dev, &args);
667 PMD_DRV_LOG(ERR, "Failed to execute command of "
668 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
674 i40evf_config_irq_map(struct rte_eth_dev *dev)
676 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
677 struct vf_cmd_info args;
678 uint8_t *cmd_buffer = NULL;
679 struct virtchnl_irq_map_info *map_info;
680 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
681 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
682 uint32_t vec, cmd_buffer_size, max_vectors, nb_msix, msix_base, i;
683 uint16_t rxq_map[vf->vf_res->max_vectors];
686 memset(rxq_map, 0, sizeof(rxq_map));
687 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
688 rte_intr_allow_others(intr_handle)) {
689 msix_base = I40E_RX_VEC_START;
690 /* For interrupt mode, available vector id is from 1. */
691 max_vectors = vf->vf_res->max_vectors - 1;
692 nb_msix = RTE_MIN(max_vectors, intr_handle->nb_efd);
695 for (i = 0; i < dev->data->nb_rx_queues; i++) {
696 rxq_map[vec] |= 1 << i;
697 intr_handle->intr_vec[i] = vec++;
698 if (vec >= vf->vf_res->max_vectors)
702 msix_base = I40E_MISC_VEC_ID;
705 for (i = 0; i < dev->data->nb_rx_queues; i++) {
706 rxq_map[msix_base] |= 1 << i;
707 if (rte_intr_dp_is_en(intr_handle))
708 intr_handle->intr_vec[i] = msix_base;
712 cmd_buffer_size = sizeof(struct virtchnl_irq_map_info) +
713 sizeof(struct virtchnl_vector_map) * nb_msix;
714 cmd_buffer = rte_zmalloc("i40e", cmd_buffer_size, 0);
716 PMD_DRV_LOG(ERR, "Failed to allocate memory");
717 return I40E_ERR_NO_MEMORY;
720 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
721 map_info->num_vectors = nb_msix;
722 for (i = 0; i < nb_msix; i++) {
723 map_info->vecmap[i].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
724 map_info->vecmap[i].vsi_id = vf->vsi_res->vsi_id;
725 map_info->vecmap[i].vector_id = msix_base + i;
726 map_info->vecmap[i].txq_map = 0;
727 map_info->vecmap[i].rxq_map = rxq_map[msix_base + i];
730 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
731 args.in_args = (u8 *)cmd_buffer;
732 args.in_args_size = cmd_buffer_size;
733 args.out_buffer = vf->aq_resp;
734 args.out_size = I40E_AQ_BUF_SZ;
735 err = i40evf_execute_vf_cmd(dev, &args);
737 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
739 rte_free(cmd_buffer);
745 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
748 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
749 struct virtchnl_queue_select queue_select;
751 struct vf_cmd_info args;
752 memset(&queue_select, 0, sizeof(queue_select));
753 queue_select.vsi_id = vf->vsi_res->vsi_id;
756 queue_select.rx_queues |= 1 << qid;
758 queue_select.tx_queues |= 1 << qid;
761 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
763 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
764 args.in_args = (u8 *)&queue_select;
765 args.in_args_size = sizeof(queue_select);
766 args.out_buffer = vf->aq_resp;
767 args.out_size = I40E_AQ_BUF_SZ;
768 err = i40evf_execute_vf_cmd(dev, &args);
770 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
771 isrx ? "RX" : "TX", qid, on ? "on" : "off");
777 i40evf_start_queues(struct rte_eth_dev *dev)
779 struct rte_eth_dev_data *dev_data = dev->data;
781 struct i40e_rx_queue *rxq;
782 struct i40e_tx_queue *txq;
784 for (i = 0; i < dev->data->nb_rx_queues; i++) {
785 rxq = dev_data->rx_queues[i];
786 if (rxq->rx_deferred_start)
788 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
789 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
794 for (i = 0; i < dev->data->nb_tx_queues; i++) {
795 txq = dev_data->tx_queues[i];
796 if (txq->tx_deferred_start)
798 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
799 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
808 i40evf_stop_queues(struct rte_eth_dev *dev)
812 /* Stop TX queues first */
813 for (i = 0; i < dev->data->nb_tx_queues; i++) {
814 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
815 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
819 /* Then stop RX queues */
820 for (i = 0; i < dev->data->nb_rx_queues; i++) {
821 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
822 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
830 i40evf_add_del_eth_addr(struct rte_eth_dev *dev,
831 struct rte_ether_addr *addr,
832 bool add, uint8_t type)
834 struct virtchnl_ether_addr_list *list;
835 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
836 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
837 sizeof(struct virtchnl_ether_addr)];
839 struct vf_cmd_info args;
841 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
842 list->vsi_id = vf->vsi_res->vsi_id;
843 list->num_elements = 1;
844 list->list[0].type = type;
845 rte_memcpy(list->list[0].addr, addr->addr_bytes,
846 sizeof(addr->addr_bytes));
848 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
849 args.in_args = cmd_buffer;
850 args.in_args_size = sizeof(cmd_buffer);
851 args.out_buffer = vf->aq_resp;
852 args.out_size = I40E_AQ_BUF_SZ;
853 err = i40evf_execute_vf_cmd(dev, &args);
855 PMD_DRV_LOG(ERR, "fail to execute command %s",
856 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
861 i40evf_add_mac_addr(struct rte_eth_dev *dev,
862 struct rte_ether_addr *addr,
863 __rte_unused uint32_t index,
864 __rte_unused uint32_t pool)
866 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
869 if (rte_is_zero_ether_addr(addr)) {
870 PMD_DRV_LOG(ERR, "Invalid mac:" RTE_ETHER_ADDR_PRT_FMT,
871 RTE_ETHER_ADDR_BYTES(addr));
872 return I40E_ERR_INVALID_MAC_ADDR;
875 err = i40evf_add_del_eth_addr(dev, addr, TRUE, VIRTCHNL_ETHER_ADDR_EXTRA);
878 PMD_DRV_LOG(ERR, "fail to add MAC address");
886 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
888 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
889 struct rte_eth_dev_data *data = dev->data;
890 struct rte_ether_addr *addr;
893 addr = &data->mac_addrs[index];
895 err = i40evf_add_del_eth_addr(dev, addr, FALSE, VIRTCHNL_ETHER_ADDR_EXTRA);
898 PMD_DRV_LOG(ERR, "fail to delete MAC address");
906 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
908 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
909 struct virtchnl_queue_select q_stats;
911 struct vf_cmd_info args;
913 memset(&q_stats, 0, sizeof(q_stats));
914 q_stats.vsi_id = vf->vsi_res->vsi_id;
915 args.ops = VIRTCHNL_OP_GET_STATS;
916 args.in_args = (u8 *)&q_stats;
917 args.in_args_size = sizeof(q_stats);
918 args.out_buffer = vf->aq_resp;
919 args.out_size = I40E_AQ_BUF_SZ;
921 err = i40evf_execute_vf_cmd(dev, &args);
923 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
927 *pstats = (struct i40e_eth_stats *)args.out_buffer;
932 i40evf_stat_update_48(uint64_t *offset,
935 if (*stat >= *offset)
936 *stat = *stat - *offset;
938 *stat = (uint64_t)((*stat +
939 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
941 *stat &= I40E_48_BIT_MASK;
945 i40evf_stat_update_32(uint64_t *offset,
948 if (*stat >= *offset)
949 *stat = (uint64_t)(*stat - *offset);
951 *stat = (uint64_t)((*stat +
952 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
956 i40evf_update_stats(struct i40e_vsi *vsi,
957 struct i40e_eth_stats *nes)
959 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
961 i40evf_stat_update_48(&oes->rx_bytes,
963 i40evf_stat_update_48(&oes->rx_unicast,
965 i40evf_stat_update_48(&oes->rx_multicast,
967 i40evf_stat_update_48(&oes->rx_broadcast,
969 i40evf_stat_update_32(&oes->rx_discards,
971 i40evf_stat_update_32(&oes->rx_unknown_protocol,
972 &nes->rx_unknown_protocol);
973 i40evf_stat_update_48(&oes->tx_bytes,
975 i40evf_stat_update_48(&oes->tx_unicast,
977 i40evf_stat_update_48(&oes->tx_multicast,
979 i40evf_stat_update_48(&oes->tx_broadcast,
981 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
982 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
986 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
989 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
990 struct i40e_eth_stats *pstats = NULL;
992 /* read stat values to clear hardware registers */
993 ret = i40evf_query_stats(dev, &pstats);
995 /* set stats offset base on current values */
997 vf->vsi.eth_stats_offset = *pstats;
1002 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1003 struct rte_eth_xstat_name *xstats_names,
1004 __rte_unused unsigned limit)
1008 if (xstats_names != NULL)
1009 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1010 snprintf(xstats_names[i].name,
1011 sizeof(xstats_names[i].name),
1012 "%s", rte_i40evf_stats_strings[i].name);
1014 return I40EVF_NB_XSTATS;
1017 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1018 struct rte_eth_xstat *xstats, unsigned n)
1022 struct i40e_eth_stats *pstats = NULL;
1023 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1024 struct i40e_vsi *vsi = &vf->vsi;
1026 if (n < I40EVF_NB_XSTATS)
1027 return I40EVF_NB_XSTATS;
1029 ret = i40evf_query_stats(dev, &pstats);
1036 i40evf_update_stats(vsi, pstats);
1038 /* loop over xstats array and values from pstats */
1039 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1041 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1042 rte_i40evf_stats_strings[i].offset);
1045 return I40EVF_NB_XSTATS;
1049 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1051 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1052 struct virtchnl_vlan_filter_list *vlan_list;
1053 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1056 struct vf_cmd_info args;
1058 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1059 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1060 vlan_list->num_elements = 1;
1061 vlan_list->vlan_id[0] = vlanid;
1063 args.ops = VIRTCHNL_OP_ADD_VLAN;
1064 args.in_args = (u8 *)&cmd_buffer;
1065 args.in_args_size = sizeof(cmd_buffer);
1066 args.out_buffer = vf->aq_resp;
1067 args.out_size = I40E_AQ_BUF_SZ;
1068 err = i40evf_execute_vf_cmd(dev, &args);
1070 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1074 * In linux kernel driver on receiving ADD_VLAN it enables
1075 * VLAN_STRIP by default. So reconfigure the vlan_offload
1076 * as it was done by the app earlier.
1078 err = i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1080 PMD_DRV_LOG(ERR, "fail to set vlan_strip");
1086 i40evf_request_queues(struct rte_eth_dev *dev, uint16_t num)
1088 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1089 struct virtchnl_vf_res_request vfres;
1090 struct vf_cmd_info args;
1093 vfres.num_queue_pairs = num;
1095 args.ops = VIRTCHNL_OP_REQUEST_QUEUES;
1096 args.in_args = (u8 *)&vfres;
1097 args.in_args_size = sizeof(vfres);
1098 args.out_buffer = vf->aq_resp;
1099 args.out_size = I40E_AQ_BUF_SZ;
1101 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
1103 err = i40evf_execute_vf_cmd(dev, &args);
1105 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL, i40evf_dev_alarm_handler, dev);
1107 if (err != I40E_SUCCESS) {
1108 PMD_DRV_LOG(ERR, "fail to execute command OP_REQUEST_QUEUES");
1112 /* The PF will issue a reset to the VF when change the number of
1113 * queues. The PF will set I40E_VFGEN_RSTAT to COMPLETE first, then
1114 * wait 10ms and set it to ACTIVE. In this duration, vf may not catch
1115 * the moment that COMPLETE is set. So, for vf, we'll try to wait a
1120 err = i40evf_check_vf_reset_done(dev);
1122 PMD_DRV_LOG(ERR, "VF is still resetting");
1128 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1130 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1131 struct virtchnl_vlan_filter_list *vlan_list;
1132 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1135 struct vf_cmd_info args;
1137 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1138 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1139 vlan_list->num_elements = 1;
1140 vlan_list->vlan_id[0] = vlanid;
1142 args.ops = VIRTCHNL_OP_DEL_VLAN;
1143 args.in_args = (u8 *)&cmd_buffer;
1144 args.in_args_size = sizeof(cmd_buffer);
1145 args.out_buffer = vf->aq_resp;
1146 args.out_size = I40E_AQ_BUF_SZ;
1147 err = i40evf_execute_vf_cmd(dev, &args);
1149 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1154 static const struct rte_pci_id pci_id_i40evf_map[] = {
1155 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1156 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1157 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1158 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1159 { .vendor_id = 0, /* sentinel */ },
1164 i40evf_disable_irq0(struct i40e_hw *hw)
1166 /* Disable all interrupt types */
1167 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1168 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1169 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1170 I40EVF_WRITE_FLUSH(hw);
1175 i40evf_enable_irq0(struct i40e_hw *hw)
1177 /* Enable admin queue interrupt trigger */
1180 i40evf_disable_irq0(hw);
1181 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1182 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1183 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1184 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1186 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1187 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1188 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1189 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1191 I40EVF_WRITE_FLUSH(hw);
1195 i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
1198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1201 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1202 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1203 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1204 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1205 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1206 reset == VIRTCHNL_VFR_COMPLETED)
1211 if (i >= MAX_RESET_WAIT_CNT)
1214 vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
1219 i40evf_reset_vf(struct rte_eth_dev *dev)
1222 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1225 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1229 * After issuing vf reset command to pf, pf won't necessarily
1230 * reset vf, it depends on what state it exactly is. If it's not
1231 * initialized yet, it won't have vf reset since it's in a certain
1232 * state. If not, it will try to reset. Even vf is reset, pf will
1233 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1234 * it to ACTIVE. In this duration, vf may not catch the moment that
1235 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1239 ret = i40evf_check_vf_reset_done(dev);
1241 PMD_INIT_LOG(ERR, "VF is still resetting");
1249 i40evf_init_vf(struct rte_eth_dev *dev)
1252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1255 i40e_calc_itr_interval(0, 0);
1257 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1258 vf->dev_data = dev->data;
1259 rte_spinlock_init(&vf->cmd_send_lock);
1260 err = i40e_set_mac_type(hw);
1262 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1266 err = i40evf_check_vf_reset_done(dev);
1270 i40e_init_adminq_parameter(hw);
1271 err = i40e_init_adminq(hw);
1273 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1277 /* Reset VF and wait until it's complete */
1278 if (i40evf_reset_vf(dev)) {
1279 PMD_INIT_LOG(ERR, "reset NIC failed");
1283 /* VF reset, shutdown admin queue and initialize again */
1284 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1285 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1289 i40e_init_adminq_parameter(hw);
1290 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1291 PMD_INIT_LOG(ERR, "init_adminq failed");
1295 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1297 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1300 if (i40evf_check_api_version(dev) != 0) {
1301 PMD_INIT_LOG(ERR, "check_api version failed");
1304 bufsz = sizeof(struct virtchnl_vf_resource) +
1305 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1306 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1308 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1312 if (i40evf_get_vf_resource(dev) != 0) {
1313 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1317 /* got VF config message back from PF, now we can parse it */
1318 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1319 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1320 vf->vsi_res = &vf->vf_res->vsi_res[i];
1324 PMD_INIT_LOG(ERR, "no LAN VSI found");
1328 if (hw->mac.type == I40E_MAC_X722_VF)
1329 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1330 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1332 switch (vf->vsi_res->vsi_type) {
1333 case VIRTCHNL_VSI_SRIOV:
1334 vf->vsi.type = I40E_VSI_SRIOV;
1337 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1340 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1341 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1343 /* Store the MAC address configured by host, or generate random one */
1344 if (!rte_is_valid_assigned_ether_addr(
1345 (struct rte_ether_addr *)hw->mac.addr))
1346 rte_eth_random_addr(hw->mac.addr); /* Generate a random one */
1348 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1349 (I40E_ITR_INDEX_DEFAULT <<
1350 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1352 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1353 I40EVF_WRITE_FLUSH(hw);
1358 rte_free(vf->vf_res);
1361 rte_free(vf->aq_resp);
1363 i40e_shutdown_adminq(hw); /* ignore error */
1369 i40evf_uninit_vf(struct rte_eth_dev *dev)
1371 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373 PMD_INIT_FUNC_TRACE();
1375 if (hw->adapter_closed == 0)
1376 i40evf_dev_close(dev);
1382 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1383 __rte_unused uint16_t msglen)
1385 struct virtchnl_pf_event *pf_msg =
1386 (struct virtchnl_pf_event *)msg;
1387 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1389 switch (pf_msg->event) {
1390 case VIRTCHNL_EVENT_RESET_IMPENDING:
1391 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1392 vf->vf_reset = true;
1393 rte_eth_dev_callback_process(dev,
1394 RTE_ETH_EVENT_INTR_RESET, NULL);
1396 case VIRTCHNL_EVENT_LINK_CHANGE:
1397 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1399 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_CAP_ADV_LINK_SPEED) {
1401 pf_msg->event_data.link_event_adv.link_status;
1403 switch (pf_msg->event_data.link_event_adv.link_speed) {
1404 case ETH_SPEED_NUM_100M:
1405 vf->link_speed = VIRTCHNL_LINK_SPEED_100MB;
1407 case ETH_SPEED_NUM_1G:
1408 vf->link_speed = VIRTCHNL_LINK_SPEED_1GB;
1410 case ETH_SPEED_NUM_2_5G:
1411 vf->link_speed = VIRTCHNL_LINK_SPEED_2_5GB;
1413 case ETH_SPEED_NUM_5G:
1414 vf->link_speed = VIRTCHNL_LINK_SPEED_5GB;
1416 case ETH_SPEED_NUM_10G:
1417 vf->link_speed = VIRTCHNL_LINK_SPEED_10GB;
1419 case ETH_SPEED_NUM_20G:
1420 vf->link_speed = VIRTCHNL_LINK_SPEED_20GB;
1422 case ETH_SPEED_NUM_25G:
1423 vf->link_speed = VIRTCHNL_LINK_SPEED_25GB;
1425 case ETH_SPEED_NUM_40G:
1426 vf->link_speed = VIRTCHNL_LINK_SPEED_40GB;
1429 vf->link_speed = VIRTCHNL_LINK_SPEED_UNKNOWN;
1434 pf_msg->event_data.link_event.link_status;
1436 pf_msg->event_data.link_event.link_speed;
1439 i40evf_dev_link_update(dev, 0);
1440 rte_eth_dev_callback_process(dev,
1441 RTE_ETH_EVENT_INTR_LSC, NULL);
1443 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1444 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1447 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1453 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1457 struct i40e_arq_event_info info;
1458 uint16_t pending, aq_opc;
1459 enum virtchnl_ops msg_opc;
1460 enum i40e_status_code msg_ret;
1463 info.buf_len = I40E_AQ_BUF_SZ;
1465 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1468 info.msg_buf = vf->aq_resp;
1472 ret = i40e_clean_arq_element(hw, &info, &pending);
1474 if (ret != I40E_SUCCESS) {
1475 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1479 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1480 /* For the message sent from pf to vf, opcode is stored in
1481 * cookie_high of struct i40e_aq_desc, while return error code
1482 * are stored in cookie_low, Which is done by
1483 * i40e_aq_send_msg_to_vf in PF driver.*/
1484 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1485 info.desc.cookie_high);
1486 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1487 info.desc.cookie_low);
1489 case i40e_aqc_opc_send_msg_to_vf:
1490 if (msg_opc == VIRTCHNL_OP_EVENT)
1492 i40evf_handle_pf_event(dev, info.msg_buf,
1495 /* read message and it's expected one */
1496 if ((volatile uint32_t)msg_opc ==
1498 vf->cmd_retval = msg_ret;
1499 /* prevent compiler reordering */
1500 rte_compiler_barrier();
1503 PMD_DRV_LOG(ERR, "command mismatch,"
1504 "expect %u, get %u",
1505 vf->pend_cmd, msg_opc);
1506 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1507 " opcode = %d", msg_opc);
1511 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1519 * Interrupt handler triggered by NIC for handling
1520 * specific interrupt. Only adminq interrupt is processed in VF.
1523 * Pointer to interrupt handle.
1525 * The address of parameter (struct rte_eth_dev *) regsitered before.
1531 i40evf_dev_alarm_handler(void *param)
1533 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1534 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537 i40evf_disable_irq0(hw);
1539 /* read out interrupt causes */
1540 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1542 /* No interrupt event indicated */
1543 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK))
1546 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1547 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1548 i40evf_handle_aq_msg(dev);
1551 /* Link Status Change interrupt */
1552 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1553 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1557 i40evf_enable_irq0(hw);
1558 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1559 i40evf_dev_alarm_handler, dev);
1563 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1566 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1569 PMD_INIT_FUNC_TRACE();
1571 /* assign ops func pointer */
1572 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1573 eth_dev->rx_queue_count = i40e_dev_rx_queue_count;
1574 eth_dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1575 eth_dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1576 eth_dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1577 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1578 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1581 * For secondary processes, we don't initialise any further as primary
1582 * has already done this work.
1584 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1585 i40e_set_rx_function(eth_dev);
1586 i40e_set_tx_function(eth_dev);
1589 i40e_set_default_ptype_table(eth_dev);
1590 rte_eth_copy_pci_info(eth_dev, pci_dev);
1591 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1593 hw->vendor_id = pci_dev->id.vendor_id;
1594 hw->device_id = pci_dev->id.device_id;
1595 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1596 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1597 hw->bus.device = pci_dev->addr.devid;
1598 hw->bus.func = pci_dev->addr.function;
1599 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1600 hw->adapter_stopped = 1;
1601 hw->adapter_closed = 0;
1603 if(i40evf_init_vf(eth_dev) != 0) {
1604 PMD_INIT_LOG(ERR, "Init vf failed");
1608 i40e_set_default_pctype_table(eth_dev);
1609 rte_eal_alarm_set(I40EVF_ALARM_INTERVAL,
1610 i40evf_dev_alarm_handler, eth_dev);
1612 /* configure and enable device interrupt */
1613 i40evf_enable_irq0(hw);
1616 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1617 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1619 if (eth_dev->data->mac_addrs == NULL) {
1620 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1621 " store MAC addresses",
1622 RTE_ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1625 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1626 ð_dev->data->mac_addrs[0]);
1632 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1634 PMD_INIT_FUNC_TRACE();
1636 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1639 if (i40evf_uninit_vf(eth_dev) != 0) {
1640 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1648 i40evf_check_driver_handler(__rte_unused const char *key,
1649 const char *value, __rte_unused void *opaque)
1651 if (strcmp(value, "i40evf"))
1658 i40evf_driver_selected(struct rte_devargs *devargs)
1660 struct rte_kvargs *kvlist;
1663 if (devargs == NULL)
1666 kvlist = rte_kvargs_parse(devargs->args, NULL);
1670 if (!rte_kvargs_count(kvlist, RTE_DEVARGS_KEY_DRIVER))
1673 /* i40evf driver selected when there's a key-value pair:
1676 if (rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_DRIVER,
1677 i40evf_check_driver_handler, NULL) < 0)
1683 rte_kvargs_free(kvlist);
1687 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1688 struct rte_pci_device *pci_dev)
1690 if (!i40evf_driver_selected(pci_dev->device.devargs))
1693 return rte_eth_dev_pci_generic_probe(pci_dev,
1694 sizeof(struct i40e_adapter), i40evf_dev_init);
1697 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1699 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1703 * virtual function driver struct
1705 static struct rte_pci_driver rte_i40evf_pmd = {
1706 .id_table = pci_id_i40evf_map,
1707 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1708 .probe = eth_i40evf_pci_probe,
1709 .remove = eth_i40evf_pci_remove,
1712 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1714 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1715 RTE_PMD_REGISTER_PARAM_STRING(net_i40e_vf, "driver=i40evf");
1718 i40evf_dev_configure(struct rte_eth_dev *dev)
1720 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1721 struct i40e_adapter *ad =
1722 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1723 uint16_t num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1724 dev->data->nb_tx_queues);
1726 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1727 * allocation or vector Rx preconditions we will reset it.
1729 ad->rx_bulk_alloc_allowed = true;
1730 ad->rx_vec_allowed = true;
1731 ad->tx_simple_allowed = true;
1732 ad->tx_vec_allowed = true;
1734 dev->data->dev_conf.intr_conf.lsc =
1735 !!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC);
1737 if (num_queue_pairs > vf->vsi_res->num_queue_pairs) {
1741 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1743 "For secondary processes, change queue pairs is not supported!");
1747 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1748 if (!hw->adapter_stopped) {
1749 PMD_DRV_LOG(ERR, "Device must be stopped first!");
1753 PMD_DRV_LOG(INFO, "change queue pairs from %u to %u",
1754 vf->vsi_res->num_queue_pairs, num_queue_pairs);
1755 ret = i40evf_request_queues(dev, num_queue_pairs);
1759 ret = i40evf_dev_reset(dev);
1764 return i40evf_init_vlan(dev);
1768 i40evf_init_vlan(struct rte_eth_dev *dev)
1770 /* Apply vlan offload setting */
1771 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1777 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1779 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1780 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1782 if (!(vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1785 /* Vlan stripping setting */
1786 if (mask & ETH_VLAN_STRIP_MASK) {
1787 /* Enable or disable VLAN stripping */
1788 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1789 i40evf_enable_vlan_strip(dev);
1791 i40evf_disable_vlan_strip(dev);
1798 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1800 struct i40e_rx_queue *rxq;
1802 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 PMD_INIT_FUNC_TRACE();
1806 rxq = dev->data->rx_queues[rx_queue_id];
1808 err = i40e_alloc_rx_queue_mbufs(rxq);
1810 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1816 /* Init the RX tail register. */
1817 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1818 I40EVF_WRITE_FLUSH(hw);
1820 /* Ready to switch the queue on */
1821 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1823 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1827 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1833 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1835 struct i40e_rx_queue *rxq;
1838 rxq = dev->data->rx_queues[rx_queue_id];
1840 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1842 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1847 i40e_rx_queue_release_mbufs(rxq);
1848 i40e_reset_rx_queue(rxq);
1849 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1855 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1859 PMD_INIT_FUNC_TRACE();
1861 /* Ready to switch the queue on */
1862 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1864 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1868 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1874 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1876 struct i40e_tx_queue *txq;
1879 txq = dev->data->tx_queues[tx_queue_id];
1881 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1883 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1888 i40e_tx_queue_release_mbufs(txq);
1889 i40e_reset_tx_queue(txq);
1890 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1896 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1901 ret = i40evf_add_vlan(dev, vlan_id);
1903 ret = i40evf_del_vlan(dev,vlan_id);
1909 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1911 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912 struct rte_eth_dev_data *dev_data = dev->data;
1913 struct rte_pktmbuf_pool_private *mbp_priv;
1914 uint16_t buf_size, len;
1916 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1917 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1918 I40EVF_WRITE_FLUSH(hw);
1920 /* Calculate the maximum packet length allowed */
1921 mbp_priv = rte_mempool_get_priv(rxq->mp);
1922 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1923 RTE_PKTMBUF_HEADROOM);
1924 rxq->hs_mode = i40e_header_split_none;
1925 rxq->rx_hdr_len = 0;
1926 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1927 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1928 rxq->max_pkt_len = RTE_MIN(len,
1929 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1932 * Check if the jumbo frame and maximum packet length are set correctly
1934 if (dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1935 if (rxq->max_pkt_len <= I40E_ETH_MAX_LEN ||
1936 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1937 PMD_DRV_LOG(ERR, "maximum packet length must be "
1938 "larger than %u and smaller than %u, as jumbo "
1939 "frame is enabled", (uint32_t)I40E_ETH_MAX_LEN,
1940 (uint32_t)I40E_FRAME_SIZE_MAX);
1941 return I40E_ERR_CONFIG;
1944 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
1945 rxq->max_pkt_len > I40E_ETH_MAX_LEN) {
1946 PMD_DRV_LOG(ERR, "maximum packet length must be "
1947 "larger than %u and smaller than %u, as jumbo "
1948 "frame is disabled",
1949 (uint32_t)RTE_ETHER_MIN_LEN,
1950 (uint32_t)I40E_ETH_MAX_LEN);
1951 return I40E_ERR_CONFIG;
1955 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
1956 rxq->max_pkt_len > buf_size)
1957 dev_data->scattered_rx = 1;
1963 i40evf_rx_init(struct rte_eth_dev *dev)
1965 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1967 int ret = I40E_SUCCESS;
1968 struct i40e_rx_queue **rxq =
1969 (struct i40e_rx_queue **)dev->data->rx_queues;
1971 i40evf_config_rss(vf);
1972 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1973 if (!rxq[i] || !rxq[i]->q_set)
1975 ret = i40evf_rxq_init(dev, rxq[i]);
1976 if (ret != I40E_SUCCESS)
1979 if (ret == I40E_SUCCESS)
1980 i40e_set_rx_function(dev);
1986 i40evf_tx_init(struct rte_eth_dev *dev)
1989 struct i40e_tx_queue **txq =
1990 (struct i40e_tx_queue **)dev->data->tx_queues;
1991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 for (i = 0; i < dev->data->nb_tx_queues; i++)
1994 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1996 i40e_set_tx_function(dev);
2000 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
2002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2004 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006 if (!rte_intr_allow_others(intr_handle)) {
2008 I40E_VFINT_DYN_CTL01,
2009 I40E_VFINT_DYN_CTL01_INTENA_MASK |
2010 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
2011 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
2012 I40EVF_WRITE_FLUSH(hw);
2016 I40EVF_WRITE_FLUSH(hw);
2020 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
2022 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2024 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2026 if (!rte_intr_allow_others(intr_handle)) {
2027 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
2028 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
2029 I40EVF_WRITE_FLUSH(hw);
2033 I40EVF_WRITE_FLUSH(hw);
2037 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2039 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2040 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2041 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043 i40e_calc_itr_interval(0, 0);
2046 msix_intr = intr_handle->intr_vec[queue_id];
2047 if (msix_intr == I40E_MISC_VEC_ID)
2048 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
2049 I40E_VFINT_DYN_CTL01_INTENA_MASK |
2050 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
2051 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
2053 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
2056 I40E_VFINT_DYN_CTLN1(msix_intr -
2058 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2059 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2060 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2062 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2064 I40EVF_WRITE_FLUSH(hw);
2070 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2072 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2073 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 msix_intr = intr_handle->intr_vec[queue_id];
2078 if (msix_intr == I40E_MISC_VEC_ID)
2079 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2082 I40E_VFINT_DYN_CTLN1(msix_intr -
2086 I40EVF_WRITE_FLUSH(hw);
2092 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2094 struct virtchnl_ether_addr_list *list;
2095 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2100 struct rte_ether_addr *addr;
2101 struct vf_cmd_info args;
2105 len = sizeof(struct virtchnl_ether_addr_list);
2106 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2107 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
2109 len += sizeof(struct virtchnl_ether_addr);
2110 if (len >= I40E_AQ_BUF_SZ) {
2116 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2118 PMD_DRV_LOG(ERR, "fail to allocate memory");
2122 for (i = begin; i < next_begin; i++) {
2123 addr = &dev->data->mac_addrs[i];
2124 if (rte_is_zero_ether_addr(addr))
2126 rte_memcpy(list->list[j].addr, addr->addr_bytes,
2127 sizeof(addr->addr_bytes));
2128 list->list[j].type = (j == 0 ?
2129 VIRTCHNL_ETHER_ADDR_PRIMARY :
2130 VIRTCHNL_ETHER_ADDR_EXTRA);
2131 PMD_DRV_LOG(DEBUG, "add/rm mac:" RTE_ETHER_ADDR_PRT_FMT,
2132 RTE_ETHER_ADDR_BYTES(addr));
2135 list->vsi_id = vf->vsi_res->vsi_id;
2136 list->num_elements = j;
2137 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2138 VIRTCHNL_OP_DEL_ETH_ADDR;
2139 args.in_args = (uint8_t *)list;
2140 args.in_args_size = len;
2141 args.out_buffer = vf->aq_resp;
2142 args.out_size = I40E_AQ_BUF_SZ;
2143 err = i40evf_execute_vf_cmd(dev, &args);
2145 PMD_DRV_LOG(ERR, "fail to execute command %s",
2146 add ? "OP_ADD_ETHER_ADDRESS" :
2147 "OP_DEL_ETHER_ADDRESS");
2156 } while (begin < I40E_NUM_MACADDR_MAX);
2160 i40evf_dev_start(struct rte_eth_dev *dev)
2162 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2165 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2166 uint32_t intr_vector = 0;
2168 PMD_INIT_FUNC_TRACE();
2170 hw->adapter_stopped = 0;
2172 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2173 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2174 dev->data->nb_tx_queues);
2176 /* check and configure queue intr-vector mapping */
2177 if (rte_intr_cap_multiple(intr_handle) &&
2178 dev->data->dev_conf.intr_conf.rxq) {
2179 intr_vector = dev->data->nb_rx_queues;
2180 if (rte_intr_efd_enable(intr_handle, intr_vector))
2184 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2185 intr_handle->intr_vec =
2186 rte_zmalloc("intr_vec",
2187 dev->data->nb_rx_queues * sizeof(int), 0);
2188 if (!intr_handle->intr_vec) {
2189 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2190 " intr_vec", dev->data->nb_rx_queues);
2195 if (i40evf_rx_init(dev) != 0){
2196 PMD_DRV_LOG(ERR, "failed to do RX init");
2200 i40evf_tx_init(dev);
2202 if (i40evf_configure_vsi_queues(dev) != 0) {
2203 PMD_DRV_LOG(ERR, "configure queues failed");
2206 if (i40evf_config_irq_map(dev)) {
2207 PMD_DRV_LOG(ERR, "config_irq_map failed");
2211 /* Set all mac addrs */
2212 i40evf_add_del_all_mac_addr(dev, TRUE);
2213 /* Set all multicast addresses */
2214 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2217 if (i40evf_start_queues(dev) != 0) {
2218 PMD_DRV_LOG(ERR, "enable queues failed");
2222 /* only enable interrupt in rx interrupt mode */
2223 if (dev->data->dev_conf.intr_conf.rxq != 0)
2224 rte_intr_enable(intr_handle);
2226 i40evf_enable_queues_intr(dev);
2231 i40evf_add_del_all_mac_addr(dev, FALSE);
2232 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2239 i40evf_dev_stop(struct rte_eth_dev *dev)
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2246 PMD_INIT_FUNC_TRACE();
2248 if (dev->data->dev_conf.intr_conf.rxq != 0)
2249 rte_intr_disable(intr_handle);
2251 if (hw->adapter_stopped == 1)
2253 i40evf_stop_queues(dev);
2254 i40evf_disable_queues_intr(dev);
2255 i40e_dev_clear_queues(dev);
2257 /* Clean datapath event and queue/vec mapping */
2258 rte_intr_efd_disable(intr_handle);
2259 if (intr_handle->intr_vec) {
2260 rte_free(intr_handle->intr_vec);
2261 intr_handle->intr_vec = NULL;
2263 /* remove all mac addrs */
2264 i40evf_add_del_all_mac_addr(dev, FALSE);
2265 /* remove all multicast addresses */
2266 i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2268 hw->adapter_stopped = 1;
2269 dev->data->dev_started = 0;
2275 i40evf_dev_link_update(struct rte_eth_dev *dev,
2276 __rte_unused int wait_to_complete)
2278 struct rte_eth_link new_link;
2279 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2281 * DPDK pf host provide interfacet to acquire link status
2282 * while Linux driver does not
2285 memset(&new_link, 0, sizeof(new_link));
2286 /* Linux driver PF host */
2287 switch (vf->link_speed) {
2288 case I40E_LINK_SPEED_100MB:
2289 new_link.link_speed = ETH_SPEED_NUM_100M;
2291 case I40E_LINK_SPEED_1GB:
2292 new_link.link_speed = ETH_SPEED_NUM_1G;
2294 case I40E_LINK_SPEED_10GB:
2295 new_link.link_speed = ETH_SPEED_NUM_10G;
2297 case I40E_LINK_SPEED_20GB:
2298 new_link.link_speed = ETH_SPEED_NUM_20G;
2300 case I40E_LINK_SPEED_25GB:
2301 new_link.link_speed = ETH_SPEED_NUM_25G;
2303 case I40E_LINK_SPEED_40GB:
2304 new_link.link_speed = ETH_SPEED_NUM_40G;
2308 new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2310 new_link.link_speed = ETH_SPEED_NUM_NONE;
2313 /* full duplex only */
2314 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2315 new_link.link_status = vf->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
2316 new_link.link_autoneg =
2317 !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2319 return rte_eth_linkstatus_set(dev, &new_link);
2323 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2325 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2327 return i40evf_config_promisc(dev, true, vf->promisc_multicast_enabled);
2331 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2333 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2335 return i40evf_config_promisc(dev, false, vf->promisc_multicast_enabled);
2339 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2341 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2343 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, true);
2347 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2349 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2351 return i40evf_config_promisc(dev, vf->promisc_unicast_enabled, false);
2355 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2357 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2359 dev_info->max_rx_queues = I40E_MAX_QP_NUM_PER_VF;
2360 dev_info->max_tx_queues = I40E_MAX_QP_NUM_PER_VF;
2361 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2362 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2363 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
2364 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2365 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2366 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2367 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2368 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2369 dev_info->rx_queue_offload_capa = 0;
2370 dev_info->rx_offload_capa =
2371 DEV_RX_OFFLOAD_VLAN_STRIP |
2372 DEV_RX_OFFLOAD_QINQ_STRIP |
2373 DEV_RX_OFFLOAD_IPV4_CKSUM |
2374 DEV_RX_OFFLOAD_UDP_CKSUM |
2375 DEV_RX_OFFLOAD_TCP_CKSUM |
2376 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2377 DEV_RX_OFFLOAD_SCATTER |
2378 DEV_RX_OFFLOAD_JUMBO_FRAME |
2379 DEV_RX_OFFLOAD_VLAN_FILTER;
2381 dev_info->tx_queue_offload_capa = 0;
2382 dev_info->tx_offload_capa =
2383 DEV_TX_OFFLOAD_VLAN_INSERT |
2384 DEV_TX_OFFLOAD_QINQ_INSERT |
2385 DEV_TX_OFFLOAD_IPV4_CKSUM |
2386 DEV_TX_OFFLOAD_UDP_CKSUM |
2387 DEV_TX_OFFLOAD_TCP_CKSUM |
2388 DEV_TX_OFFLOAD_SCTP_CKSUM |
2389 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2390 DEV_TX_OFFLOAD_TCP_TSO |
2391 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2392 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2393 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2394 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2395 DEV_TX_OFFLOAD_MULTI_SEGS;
2397 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2399 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2400 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2401 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2403 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2408 dev_info->default_txconf = (struct rte_eth_txconf) {
2410 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2411 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2412 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2414 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2415 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2419 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2420 .nb_max = I40E_MAX_RING_DESC,
2421 .nb_min = I40E_MIN_RING_DESC,
2422 .nb_align = I40E_ALIGN_RING_DESC,
2425 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2426 .nb_max = I40E_MAX_RING_DESC,
2427 .nb_min = I40E_MIN_RING_DESC,
2428 .nb_align = I40E_ALIGN_RING_DESC,
2435 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2438 struct i40e_eth_stats *pstats = NULL;
2439 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2440 struct i40e_vsi *vsi = &vf->vsi;
2442 ret = i40evf_query_stats(dev, &pstats);
2444 i40evf_update_stats(vsi, pstats);
2446 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2447 pstats->rx_broadcast;
2448 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2450 stats->imissed = pstats->rx_discards;
2451 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2452 stats->ibytes = pstats->rx_bytes;
2453 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
2454 stats->obytes = pstats->tx_bytes;
2456 PMD_DRV_LOG(ERR, "Get statistics failed");
2462 i40evf_dev_close(struct rte_eth_dev *dev)
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2466 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2469 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2472 ret = i40evf_dev_stop(dev);
2474 i40e_dev_free_queues(dev);
2476 * disable promiscuous mode before reset vf
2477 * it is a workaround solution when work with kernel driver
2478 * and it is not the normal way
2480 if (vf->promisc_unicast_enabled || vf->promisc_multicast_enabled)
2481 i40evf_config_promisc(dev, false, false);
2483 rte_eal_alarm_cancel(i40evf_dev_alarm_handler, dev);
2485 i40evf_reset_vf(dev);
2486 i40e_shutdown_adminq(hw);
2487 i40evf_disable_irq0(hw);
2490 * If the VF is reset via VFLR, the device will be knocked out of bus
2491 * master mode, and the driver will fail to recover from the reset. Fix
2492 * this by enabling bus mastering after every reset. In a non-VFLR case,
2493 * the bus master bit will not be disabled, and this call will have no
2496 if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
2497 vf->vf_reset = false;
2499 rte_free(vf->vf_res);
2501 rte_free(vf->aq_resp);
2504 hw->adapter_closed = 1;
2509 * Reset VF device only to re-initialize resources in PMD layer
2512 i40evf_dev_reset(struct rte_eth_dev *dev)
2516 ret = i40evf_dev_uninit(dev);
2520 ret = i40evf_dev_init(dev);
2526 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2528 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2529 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2535 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2536 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2539 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2543 uint32_t *lut_dw = (uint32_t *)lut;
2544 uint16_t i, lut_size_dw = lut_size / 4;
2546 for (i = 0; i < lut_size_dw; i++)
2547 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2554 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2563 vf = I40E_VSI_TO_VF(vsi);
2564 hw = I40E_VSI_TO_HW(vsi);
2566 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2567 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2570 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2574 uint32_t *lut_dw = (uint32_t *)lut;
2575 uint16_t i, lut_size_dw = lut_size / 4;
2577 for (i = 0; i < lut_size_dw; i++)
2578 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2579 I40EVF_WRITE_FLUSH(hw);
2586 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2587 struct rte_eth_rss_reta_entry64 *reta_conf,
2590 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2592 uint16_t i, idx, shift;
2595 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2596 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2597 "(%d) doesn't match the number of hardware can "
2598 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2602 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2604 PMD_DRV_LOG(ERR, "No memory can be allocated");
2607 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2610 for (i = 0; i < reta_size; i++) {
2611 idx = i / RTE_RETA_GROUP_SIZE;
2612 shift = i % RTE_RETA_GROUP_SIZE;
2613 if (reta_conf[idx].mask & (1ULL << shift))
2614 lut[i] = reta_conf[idx].reta[shift];
2616 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2625 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2626 struct rte_eth_rss_reta_entry64 *reta_conf,
2629 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2630 uint16_t i, idx, shift;
2634 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2635 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2636 "(%d) doesn't match the number of hardware can "
2637 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2641 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2643 PMD_DRV_LOG(ERR, "No memory can be allocated");
2647 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2650 for (i = 0; i < reta_size; i++) {
2651 idx = i / RTE_RETA_GROUP_SIZE;
2652 shift = i % RTE_RETA_GROUP_SIZE;
2653 if (reta_conf[idx].mask & (1ULL << shift))
2654 reta_conf[idx].reta[shift] = lut[i];
2664 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2666 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2670 if (!key || key_len == 0) {
2671 PMD_DRV_LOG(DEBUG, "No key to be configured");
2673 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2675 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2679 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2680 struct i40e_aqc_get_set_rss_key_data *key_dw =
2681 (struct i40e_aqc_get_set_rss_key_data *)key;
2683 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2685 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2688 uint32_t *hash_key = (uint32_t *)key;
2691 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2692 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2693 I40EVF_WRITE_FLUSH(hw);
2700 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2702 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2706 if (!key || !key_len)
2709 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2710 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2711 (struct i40e_aqc_get_set_rss_key_data *)key);
2713 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2717 uint32_t *key_dw = (uint32_t *)key;
2720 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2721 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2723 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2729 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2731 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2735 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2736 rss_conf->rss_key_len);
2740 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2741 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2742 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2743 I40EVF_WRITE_FLUSH(hw);
2749 i40evf_disable_rss(struct i40e_vf *vf)
2751 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2753 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2754 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2755 I40EVF_WRITE_FLUSH(hw);
2759 i40evf_config_rss(struct i40e_vf *vf)
2761 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2762 struct rte_eth_rss_conf rss_conf;
2763 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2764 uint32_t rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
2769 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2770 i40evf_disable_rss(vf);
2771 PMD_DRV_LOG(DEBUG, "RSS not configured");
2775 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2776 /* Fill out the look up table */
2777 if (!(vf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) {
2778 for (i = 0, j = 0; i < nb_q; i++, j++) {
2781 lut = (lut << 8) | j;
2783 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2786 lut_info = rte_zmalloc("i40e_rss_lut", rss_lut_size, 0);
2788 PMD_DRV_LOG(ERR, "No memory can be allocated");
2792 for (i = 0; i < rss_lut_size; i++)
2793 lut_info[i] = i % num;
2795 ret = i40evf_set_rss_lut(&vf->vsi, lut_info,
2802 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2803 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2804 i40evf_disable_rss(vf);
2805 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2809 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2810 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2811 /* Calculate the default hash key */
2812 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2813 rss_key_default[i] = (uint32_t)rte_rand();
2814 rss_conf.rss_key = (uint8_t *)rss_key_default;
2815 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2819 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2823 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2824 struct rte_eth_rss_conf *rss_conf)
2826 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2831 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2832 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2834 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2835 if (rss_hf != 0) /* Enable RSS */
2841 if (rss_hf == 0) /* Disable RSS */
2844 return i40evf_hw_rss_hash_set(vf, rss_conf);
2848 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2849 struct rte_eth_rss_conf *rss_conf)
2851 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2856 &rss_conf->rss_key_len);
2858 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2859 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2860 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2866 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2868 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2869 struct rte_eth_dev_data *dev_data = vf->dev_data;
2870 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2873 /* check if mtu is within the allowed range */
2874 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
2877 /* mtu setting is forbidden if port is start */
2878 if (dev_data->dev_started) {
2879 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2884 if (frame_size > I40E_ETH_MAX_LEN)
2885 dev_data->dev_conf.rxmode.offloads |=
2886 DEV_RX_OFFLOAD_JUMBO_FRAME;
2888 dev_data->dev_conf.rxmode.offloads &=
2889 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2890 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2896 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2897 struct rte_ether_addr *mac_addr)
2899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900 struct rte_ether_addr *old_addr;
2903 old_addr = (struct rte_ether_addr *)hw->mac.addr;
2905 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2906 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2910 if (rte_is_same_ether_addr(old_addr, mac_addr))
2913 i40evf_add_del_eth_addr(dev, old_addr, FALSE, VIRTCHNL_ETHER_ADDR_PRIMARY);
2915 ret = i40evf_add_del_eth_addr(dev, mac_addr, TRUE, VIRTCHNL_ETHER_ADDR_PRIMARY);
2919 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)hw->mac.addr);
2924 i40evf_add_del_mc_addr_list(struct rte_eth_dev *dev,
2925 struct rte_ether_addr *mc_addrs,
2926 uint32_t mc_addrs_num, bool add)
2928 struct virtchnl_ether_addr_list *list;
2929 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2930 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) +
2931 (I40E_NUM_MACADDR_MAX * sizeof(struct virtchnl_ether_addr))];
2934 struct vf_cmd_info args;
2936 if (mc_addrs == NULL || mc_addrs_num == 0)
2939 if (mc_addrs_num > I40E_NUM_MACADDR_MAX)
2942 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
2943 list->vsi_id = vf->vsi_res->vsi_id;
2944 list->num_elements = mc_addrs_num;
2946 for (i = 0; i < mc_addrs_num; i++) {
2947 if (!I40E_IS_MULTICAST(mc_addrs[i].addr_bytes)) {
2948 PMD_DRV_LOG(ERR, "Invalid mac:" RTE_ETHER_ADDR_PRT_FMT,
2949 RTE_ETHER_ADDR_BYTES(&mc_addrs[i]));
2953 memcpy(list->list[i].addr, mc_addrs[i].addr_bytes,
2954 sizeof(list->list[i].addr));
2955 list->list[i].type = VIRTCHNL_ETHER_ADDR_EXTRA;
2958 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR : VIRTCHNL_OP_DEL_ETH_ADDR;
2959 args.in_args = cmd_buffer;
2960 args.in_args_size = sizeof(struct virtchnl_ether_addr_list) +
2961 i * sizeof(struct virtchnl_ether_addr);
2962 args.out_buffer = vf->aq_resp;
2963 args.out_size = I40E_AQ_BUF_SZ;
2964 err = i40evf_execute_vf_cmd(dev, &args);
2966 PMD_DRV_LOG(ERR, "fail to execute command %s",
2967 add ? "OP_ADD_ETH_ADDR" : "OP_DEL_ETH_ADDR");
2975 i40evf_set_mc_addr_list(struct rte_eth_dev *dev,
2976 struct rte_ether_addr *mc_addrs,
2977 uint32_t mc_addrs_num)
2979 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2982 /* flush previous addresses */
2983 err = i40evf_add_del_mc_addr_list(dev, vf->mc_addrs, vf->mc_addrs_num,
2988 vf->mc_addrs_num = 0;
2991 err = i40evf_add_del_mc_addr_list(dev, mc_addrs, mc_addrs_num,
2996 vf->mc_addrs_num = mc_addrs_num;
2997 memcpy(vf->mc_addrs, mc_addrs, mc_addrs_num * sizeof(*mc_addrs));
3003 is_i40evf_supported(struct rte_eth_dev *dev)
3005 return is_device_supported(dev, &rte_i40evf_pmd);